Important notice
Dear Customer,
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In data sheets and application notes which still contain NXP or Philips Semiconductors references, use
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use http://www.nexperia.com
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Replace the copyright notice at the bottom of each page or elsewhere in the document, depending on
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- © NXP N.V. (year). All rights reserved or © Koninklijke Philips Electronics N.V. (year). All rights
reserved
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- © Nexperia B.V. (year). All rights reserved.
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1. Product profile
1.1 General description
PNP low VCEsat Breakthrough in Small Signal (BISS) single bipolar PNP transistor in a
SOT457 (SC-74) SMD plastic package.
NPN complement: PBSS4440D.
1.2 Features
Ultra low collector-emitter saturation voltage VCEsat
4 A continuous collector current capability IC (DC)
Up to 15 A peak current
Very low collector-emitter saturation resistance
High efficiency due to less heat generation
1.3 Applications
Power management functions
Charging circuits
DC-to-DC conversion
MOSFET gate driving
Power switches (e.g. motors, fans)
Thin Film Transistor (TFT) backlight inverter
1.4 Quick reference data
[1] Device mounted on a ceramic Printed-Circuit Board (PCB), AL2O3, standard footprint.
[2] Pulse test: tp≤300 μs; δ≤0.02.
PBSS5440D
40 V PNP low VCEsat (BISS) transistor
Rev. 02 — 14 December 2009 Product data sheet
Table 1. Quick reference data
Symbol Parameter Conditions Min Typ Max Unit
VCEO collector-emitter voltage open base - - −40 V
ICcollector current (DC) [1] --−4A
ICM peak collector current t = 1 ms or limited by
Tj(max)
--−15 A
RCEsat collector-emitter saturation
resistance IC=−6A;
IB=−600 mA [2] - 5575mΩ
PBSS5440D_2 © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 02 — 14 December 2009 2 of 13
NXP Semiconductors PBSS5440D
40 V PNP low VCEsat (BISS) transistor
2. Pinning information
3. Ordering information
4. Marking
5. Limiting values
Table 2. Pinning
Pin Description Simplified outline Symbol
1 collector
2 collector
3base
4emitter
5 collector
6 collector
132
4
56
4
3
1, 2, 5, 6
sym030
Table 3. Ordering information
Type number Package
Name Description Version
PBSS5440D SC-74 plastic surface mounted package; 6 leads SOT457
Table 4. Marking codes
Type number Marking code
PBSS5440D 71
Table 5. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter Conditions Min Max Unit
VCBO collector-base voltage open emitter - −40 V
VCEO collector-emitter voltage open base - −40 V
VEBO emitter-base voltage open collector - −5V
ICcollector current (DC) [1] -−4A
ICM peak collector current t = 1 ms or limited
by Tj(max)
-−15 A
IBbase current (DC) - −0.8 A
IBM peak base current tp≤300 μs-−2A
Ptot total power dissipation Tamb ≤ 25 °C[2] -360mW
[3] -600mW
[4] -750mW
[1] -1.1W
[2][5] -2.5W
PBSS5440D_2 © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 02 — 14 December 2009 3 of 13
NXP Semiconductors PBSS5440D
40 V PNP low VCEsat (BISS) transistor
[1] Device mounted on a ceramic PCB, AL2O3, standard footprint.
[2] Device mounted on an FR4 PCB, single-sided copper, tin-plated and standard footprint.
[3] Device mounted on an FR4 PCB, single-sided copper, tin-plated, mounting pad for collector 1 cm2.
[4] Device mounted on an FR4 PCB, single-sided copper, tin-plated, mounting pad for collector 6 cm2.
[5] Operated under pulsed conditions: Duty cycle δ≤10% and pulse width tp≤10 ms.
Tstg storage temperature −65 +150 °C
Tjjunction temperature - 150 °C
Tamb ambient temperature −65 +150 °C
(1) Ceramic PCB, AL2O3, standard footprint
(2) FR4 PCB, mounting pad for collector 6 cm2
(3) FR4 PCB, mounting pad for collector 1 cm2
(4) FR4 PCB, standard footprint
Fig 1. Power derating curves
Table 5. Limiting values …continued
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter Conditions Min Max Unit
(1)
Tamb (°C)
−75 17512525 75−25
006aaa270
800
400
1200
1600
Ptot
(mW)
0
(2)
(4)
(3)
PBSS5440D_2 © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 02 — 14 December 2009 4 of 13
NXP Semiconductors PBSS5440D
40 V PNP low VCEsat (BISS) transistor
6. Thermal characteristics
[1] Device mounted on an FR4 PCB, single-sided copper, tin-plated and standard footprint.
[2] Device mounted on an FR4 PCB, single-sided copper, tin-plated, mounting pad for collector 1 cm2.
[3] Device mounted on an FR4 PCB, single-sided copper, tin-plated, mounting pad for collector 6 cm2.
[4] Device mounted on a ceramic PCB, AL2O3, standard footprint.
[5] Operated under pulsed conditions: Duty cycle δ≤10% and pulse width tp≤10 ms.
Table 6. Thermal characteristics
Symbol Parameter Conditions Min Typ Max Unit
Rth(j-a) thermal resistance from
junction to ambient in free air [1] - - 350 K/W
[2] - - 208 K/W
[3] - - 160 K/W
[4] --113K/W
[1][5] --50K/W
Rth(j-sp) thermal resistance from
junction to solder point --45K/W
FR4 PCB, standard footprint
Fig 2. Transient thermal impedance from junctio n to ambient as a function of pulse time; typical values
006aaa271
10
1
102
103
Zth(j-a)
(K/W)
10−1
10−51010−2
10−4102
10−1
tp (s)
10−3103
1
duty cycle =
10.75
0.5
0.33
0.2
0.1
0.05
0.02
0.01
0
PBSS5440D_2 © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 02 — 14 December 2009 5 of 13
NXP Semiconductors PBSS5440D
40 V PNP low VCEsat (BISS) transistor
FR4 PCB, mounting pad for collector 1 cm2
Fig 3. Transient thermal impedance from junctio n to ambient as a function of pulse time; typical values
006aaa272
10
1
102
103
Zth(j-a)
(K/W)
10−1
10−51010−2
10−4102
10−1
tp (s)
10−3103
1
duty cycle =
10.75
0.5
0.33
0.2
0.1
0.05
0.02
0.01
0
FR4 PCB, mounting pad for collector 6 cm2
Fig 4. Transient thermal impedance from junctio n to ambient as a function of pulse time; typical values
006aaa273
10
1
102
103
Zth(j-a)
(K/W)
10−1
10−51010−2
10−4102
10−1
tp (s)
10−3103
1
duty cycle =
10.75
0.5
0.33
0.2
0.1
0.05
0.02
0.01
0
PBSS5440D_2 © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 02 — 14 December 2009 6 of 13
NXP Semiconductors PBSS5440D
40 V PNP low VCEsat (BISS) transistor
7. Characteristics
[1] Pulse test: tp≤300 μs; δ≤0.02.
Table 7. Characteristics
Tamb = 25
°
C unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
ICBO collector-base cut-off
current VCB = −30 V; IE = 0 A - - −0.1 μA
VCB = −30 V; IE = 0 A; Tj=150°C- - −50 μA
ICES collector-emitter
cut-off current VCE = −30 V; VBE = 0 V - - −0.1 μA
IEBO emitter-base cut-off
current VEB = −5 V; IC = 0 A - - −0.1 μA
hFE DC current gain VCE = −2 V; IC = −0.5 A 200 - -
VCE = −2 V; IC = −1 A [1] 200 - -
VCE = −2 V; IC = −2 A [1] 175 - -
VCE = −2 V; IC = −4 A [1] 80 - -
VCE = −2 V; IC = −6 A [1] 30 - -
VCEsat collector-emitter
saturation voltage IC = −0.5 A; I B = −50 mA - −46 −60 mV
IC = −1 A; IB = −50 mA - −70 −110 mV
IC = −2 A; IB = −200 mA - −120 −180 mV
IC = −4 A; IB = −400 mA [1] -−220 −300 mV
IC = −6 A; IB = −600 mA [1] -−320 −450 mV
RCEsat collector-emitter
saturation resistance IC = −6 A; IB = −600 mA [1] - 5575mΩ
VBEsat base-emitter
saturation voltage IC = −0.5 A; I B = −50 mA - −0.8 −0.85 V
IC = −1 A; IB = −50 mA - −0.84 −0.9 V
IC = −1 A; IB = −100 mA [1] -−0.84 −1V
IC = −4 A; IB = −400 mA [1] -−1.0 −1.1 V
VBEon base-emitter turn-on
voltage VCE = −2 V; IC = −2 A - −0.8 −1.0 V
tddelay time VCC = −10 V; IC = −2 A;
IBon =−0.1 A; IBoff =0.1A -12-ns
trrise time - 43 - ns
ton turn-on time - 55 - ns
tsstorage time - 240 - ns
tffall time - 80 - ns
toff turn-off time - 320 - ns
fTtransition frequency VCE = −10 V; IC = −0.1 A;
f=100MHz -110-MHz
Cccollector capacit ance VCB = −10 V; IE = ie = 0 A;
f=1MHz -50-pF
PBSS5440D_2 © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 02 — 14 December 2009 7 of 13
NXP Semiconductors PBSS5440D
40 V PNP low VCEsat (BISS) transistor
VCE =−2V
(1) Tamb = 100 °C
(2) Tamb = 25 °C
(3) Tamb =−55 °C
VCE =−2V
Tamb = 25 °C
Fig 5. DC current gain as a function of collector
current; typical values Fig 6. Base-emitter volt age as a function of collector
current; typical values
IC/IB=20
(1) Tamb = 100 °C
(2) Tamb = 25 °C
(3) Tamb =−55 °C
Tamb = 25 °C
(1) IC/IB= 100
(2) IC/IB=50
(3) IC/IB=10
Fig 7. Collector-emitter saturation voltage as a
function of collector current; typical values Fig 8. Collector-emitter saturation voltage as a
function of collector current; typical values
IC (mA)
−10−1−105
−104
−103
−1−102
−10
006aaa282
200
400
600
hFE
0
(1)
(2)
(3)
IC (mA)
−10−1−105
−104
−103
−1−102
−10
006aaa283
−0.8
−0.4
−1.2
−1.6
VBE
(V)
0
006aaa284
−10−1
−10−2
−1
VCEsat
(V)
−10−3
IC (mA)
−10−1−104
−103
−1−102
−10
(1)
(2)
(3)
−10−1
−10−2
−1
VCEsat
(V)
−10−3
006aaa285
IC (mA)
−10−1−105
−104
−103
−1−102
−10
(1)
(2)
(3)
PBSS5440D_2 © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 02 — 14 December 2009 8 of 13
NXP Semiconductors PBSS5440D
40 V PNP low VCEsat (BISS) transistor
IC/IB=20
(1) Tamb =−55 °C
(2) Tamb = 25 °C
(3) Tamb = 100 °C
Tamb = 25 °C
(1) IC/IB= 100
(2) IC/IB=50
(3) IC/IB=10
Fig 9. Base-emitter saturation voltage as a function
of collector current; typical values Fig 10. Collector-emitter satur ation resistance as a
function of collector current; typical values
IC (mA)
−10−1−105
−104
−103
−1−102
−10
006aaa287
−0.5
−0.9
−1.3
VBEsat
(V)
−0.1
(1)
(2)
(3)
IC (A)
−10−1−104
−103
−1−102
−10
006aaa327
1
10−1
102
10
103
RCEsat
(Ω)
10−2
(2)
(1)
(3)
Tamb =25°CI
C/IB=20
(1) Tamb = 100 °C
(2) Tamb = 25 °C
(3) Tamb =−55 °C
Fig 11. Collector current as a function of
collector -em itter voltage; ty pic a l va lues Fig 12. Collector-emitter saturation resistance as a
function of collector current; typical values
VCE (V)
0−2.0−1.6−0.8 −1.2−0.4
006aaa288
−4
−8
−12
IC
(A)
0
IB (mA) = −400
−360
−280
−240
−200
−160
−120
−80
−40
−320
006aaa289
IC (mA)
−10−1−104
−103
−1−102
−10
10−1
1
10
102
RCEsat
(Ω)
10−2
(1)
(2)
(3)
PBSS5440D_2 © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 02 — 14 December 2009 9 of 13
NXP Semiconductors PBSS5440D
40 V PNP low VCEsat (BISS) transistor
8. Test information
Fig 13. BISS transistor switching time definition
(1) VCC = −10 V; IC = −2 A; IBon =−0.1 A; IBoff =0.1A
Fig 14. Test circuit for switchin g tim es
006aaa266
−IBon (100 %)
−IB
input pulse
(idealized waveform)
−IBoff
90 %
10 %
−IC (100 %)
−IC
td
ton
90 %
10 %
tr
output pulse
(idealized waveform)
tf
t
ts
toff
RC
R2
R1
DUT
mgd624
Vo
RB
(probe)
450 Ω
(probe)
450 Ω
oscilloscope oscilloscope
VBB
VI
VCC
PBSS5440D_2 © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 02 — 14 December 2009 10 of 13
NXP Semiconductors PBSS5440D
40 V PNP low VCEsat (BISS) transistor
9. Package outline
10. Packing information
[1] For further information and the availability of packing methods, see Section 13.
[2] T1: normal taping
[3] T2: reverse taping
Fig 15. Package outline SOT457 (SC-74)
04-11-08Dimensions in mm
3.0
2.5
1.7
1.3
3.1
2.7
pin 1 index
1.9
0.26
0.10
0.40
0.25
0.95
1.1
0.9
0.6
0.2
132
4
56
Table 8. Packing methods
The indicated -xxx are the last three digits of the 12NC ordering code.[1]
Type number Package Description Packing quantity
3000 5000 10000
PBSS5440D SOT457 4 mm pitch, 8 mm tape and reel; T1 [2] -115 - -135
4 mm pitch, 8 mm tape and reel; T2 [3] -125 - -165
PBSS5440D_2 © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 02 — 14 December 2009 11 of 13
NXP Semiconductors PBSS5440D
40 V PNP low VCEsat (BISS) transistor
11. Revision history
Table 9. Revision history
Document ID Release date Data sheet status Cha nge notice Supersedes
PBSS5440D_2 20091214 Product data sheet - PBSS5440D_1
Modifications: •This data sheet was changed to reflec t the new company name NXP Semiconductors,
including new legal definitions and disclaimers. No changes were made to the technical
content.
•Figure 2 “Transient thermal impedance from junction to ambient as a function of pulse time;
typical values”: updated
•Figure 3 “Transient thermal impedance from junction to ambient as a function of pulse time;
typical values”: updated
•Figure 4 “Transient thermal impedance from junction to ambient as a function of pulse time;
typical values”: updated
•Figure 6 “Base-emitter voltage as a function of collector current; typical va lues”: updated
•Figure 11 “Collector current as a function of collector-emitter voltage; typical values”:
updated
PBSS5440D_1 20050427 Product data sheet - -
PBSS5440D_2 © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 02 — 14 December 2009 12 of 13
NXP Semiconductors PBSS5440D
40 V PNP low VCEsat (BISS) transistor
12. Legal information
12.1 Data sheet status
[1] Please consult the most recently issued document before initiating or completing a design.
[2] The term ‘short data sheet’ is explained in section “Definitions”.
[3] The product status of de vice(s) descr ibed in th is document m ay have cha nged since thi s document w as publish ed and may di ffe r in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
12.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warrant ies as to t he accuracy or completeness of
information included herein and shall have no liab ility for the consequences of
use of such information.
Short data sheet — A short dat a sheet is an extract from a full data sheet
with the same product type number(s) and tit le. A short data sh eet is intended
for quick reference only and shou ld not b e relied u pon to cont ain det ailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall pre va il.
12.3 Disclaimers
General — In formation in this document is believed to be accurate and
reliable. However, NXP Semiconductors does not give an y represent ations or
warranties, expressed or impli ed, as to the accuracy or completeness of such
information and shall have no liability for th e co nsequences of use of such
information.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all informa tion supplied prior
to the publication hereof .
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors accepts no liab ility for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
Applications — Applications that are described herein for any of these
products are for il lustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ra tings System of IEC 60134) may cause permanent
damage to the device. Limiting values are stress ratings only and operation of
the device at these or any other co nditions above those given in the
Characteristics sections of this document is not implied. Exposure to limiting
values for extended periods may af fect device reliability.
Terms and conditions of sale — NXP Semiconductors products are sold
subject to the general terms and conditions of commercial sale, as published
at http://www.nxp.com/profile/terms, including those pertaining to warranty,
intellectual property rights infringement and limitation of liability, unless
explicitly otherwise agreed to in writing by NXP Semiconductors. In case of
any inconsistency or conflict between inf ormation in this document and such
terms and conditions, the latter will prevail.
No offer to sell or license — Not hing in this document may be interpret ed or
construed as an of fer t o sell product s that is open for accept ance or the gr ant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Export control — This document as well as the item(s) described herein
may be subject to export control regulatio ns. Export might require a prior
authorization from national authorities.
Quick reference data — The Quick reference data is an extract of the
product data given in the Limiting values and Characteristics sections of this
document, and as such is not complete, exhaustive or legally binding.
12.4 Trademarks
Notice: All refe renced brands, produc t names, service names and trademarks
are the property of their respective ow ners.
13. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Document status[1][2] Product status[3] Definition
Objective [short] data sheet Development This document contain s data from the objective specification for product development.
Preliminary [short] dat a sheet Qualification This document contains data from the preliminary specification.
Product [short] data sheet Production This document contains the product specification.
NXP Semiconductors PBSS5440D
40 V PNP low VCEsat (BISS) transistor
© NXP B.V. 2010. All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 14 December 2009
Document identifier: PBSS5440D_2
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
14. Contents
1 Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1 General description . . . . . . . . . . . . . . . . . . . . . 1
1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.4 Quick reference data . . . . . . . . . . . . . . . . . . . . 1
2 Pinning information. . . . . . . . . . . . . . . . . . . . . . 2
3 Ordering information. . . . . . . . . . . . . . . . . . . . . 2
4 Marking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
5 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 2
6 Thermal characteristics . . . . . . . . . . . . . . . . . . 4
7 Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 6
8 Test information. . . . . . . . . . . . . . . . . . . . . . . . . 9
9 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 10
10 Packing information . . . . . . . . . . . . . . . . . . . . 10
11 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 11
12 Legal information. . . . . . . . . . . . . . . . . . . . . . . 12
12.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 12
12.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
12.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 12
12.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 12
13 Contact information. . . . . . . . . . . . . . . . . . . . . 12
14 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
