MT47H256M4HR-37E:E - Micron Technology, Inc.

Products and specifications discussed herein are subject to change by Micron without notice.

1Gb: x4, x8, x16 DDR2 SDRAM

Features

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DDR2 SDRAM

MT47H256M4 – 32 Meg x 4 x 8 banks

MT47H128M8 – 16 Meg x 8 x 8 banks

MT47H64M16 – 8 Meg x 16 x 8 banks

Features

•RoHS compliant

•V

DD = +1.8V ±0.1V, VDDQ = +1.8V ±0.1V

• JEDEC-standar d 1.8V I/O (SSTL_18-compatible)

• Differential data strobe (DQS, DQS#) option

•4n-bit prefetch architecture

• Duplicate output strobe (RDQS) option for x8

• DLL to align DQ and DQS transitions with CK

• 8 internal banks for concurrent operation

• Programmable CAS latency (CL)

• Posted CAS additive latency (AL)

• WRITE latency = READ latency - 1 tCK

• Selectable burst lengths (BL): 4 or 8

• Adjustable data-output drive strength

• 64ms, 8,192-cycle refresh

• On-die termination (ODT)

• Industrial temperature (IT) option

• Supports JEDEC clock jitter specification

Notes: 1. Not recommended for new designs.

Options Marking

• Configuration

–256 Meg x 4 (32 Meg x 4 x 8 banks) 256M4

–128 Meg x 8 (16 Meg x 8 x 8 banks) 128M8

–64 Meg x 16 (8 M eg x 16 x 8 banks) 64M16

• FBGA package (Pb-free)

–92-ball FBGA (11mm x 19mm) Rev. A BT

–84-ball FBGA (8mm x 12.5mm) Rev. E HR

–60-ball FBGA (8mm x 11.5mm) Rev. E HQ

• FBGA package (lead solder)

–84-ball FBGA (8mm x 12.5mm) Rev. E HW

–60-ball FBGA (8mm x 11.5mm) Rev. E HV

• Timing – cycle time

–1.875ns @ CL = 7 (DDR2-1066) -187E

–2.5ns @ CL = 5 (DDR2-800) -25E

–2.5ns @ CL = 6 (DDR2-800) -25

–3.0ns @ CL = 4 (DDR2-667) -3E

–3.0ns @ CL = 5 (DDR2-667) -3

–3.75ns @ CL = 4 (DDR2-533) -37E1

–5.0ns @ CL = 3 (DDR2-400) -5E1

• Self r efresh

–Standard None

–Low-power L

• Operating temperature

–Commercial (0°C ≤ TC ≤ 85°C) None

–Industrial (–40°C ≤ TC ≤ 95°C;

–40°C ≤ TA ≤ 85°C) IT

• Revision :A/:E

Table 1: Key Timing Parameters

Speed Grade

Data Rate (MT/s)

tRC (ns)CL = 3 CL = 4 CL = 5 CL = 6 CL = 7

-187E n/a n/a 667 800 1066 54

-25E n/a 533 800 n/a n/a 55

-25 n/a 533 667 800 n/a 55

-3E n/a 667 667 n/a n/a 54

-3 400 533 667 n/a n/a 55

-37E 400 533 n/a n/a n/a 55

-5E 400 400 n/a n/a n/a 55

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1Gb: x4, x8, x16 DDR2 SDRAM

Features

Figure 1: 1Gb DDR2 Part Numbers

Notes: 1. Not all spee ds and configur at ions are available in all packages.

FBGA Part Number System

Due to space limitations, FBGA-packaged components have an abbreviated part

marking that is differ ent from the part num ber. For a quick conv ersion of an FBGA code,

see the FBGA Part Marking Decoder on Micron’s Web site: www.micron.com.

Table 2: Addressing

Parameter 256 Meg x 4 128 Meg x 8 64 Meg x 16

Configuration 32 Meg x 4 x 8 banks 16 Meg x 8 x 8 banks 8 Meg x 16 x 8 banks

Refresh count 8K 8K 8K

Row address A0–A13 (16K) A0–A13 (16K) A0–A12 (8K)

Bank address BA0–BA2 (8) BA0–BA2 (8) BA0–BA2 (8)

Column address A0–A9, A11 (2K) A0–A9 (1K) A0–A9 (1K)

Package

Pb-free

92-ball 11mm x 19mm FBGA

84-ball 8mm x 12.5mm FBGA

60-ball 8mm x 11.5mm FBGA

Lead solder

84-ball 8mm x 12.5mm FBGA

60-ball 8mm x 11.5mm FBGA

Example Part Number: MT47H128M8BT-37E

Configuration

256 Meg x 4

128 Meg x 8

64 Meg x 16

256M4

128M8

64M16 Speed Grade

tCK = 1.875ns, CL = 7

tCK = 2.5ns, CL = 5

tCK = 2.5ns, CL = 6

tCK = 3ns, CL = 4

tCK = 3ns, CL = 5

tCK = 3.75ns, CL = 4

tCK = 5ns, CL = 3

-187E

-25E

-25

-3E

-3

-37E

-5E

Configuration

MT47H Package Speed

Revision

:A/:E

Low power

Industrial temperature

{

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1Gb: x4, x8, x16 DDR2 SDRAM

Table of Contents

FBGA Part Number System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2

State Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5

Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6

Industrial Temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6

Automotive Temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7

General Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7

Functional Block Diagrams. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8

Ball Assignments and Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

Electrical Specifications – Absolute Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24

Temperature and Thermal Impedance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24

Electrical Specifications – IDD Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

IDD Specifications and Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

IDD7 Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27

AC Timing Operating Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32

Notes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39

AC and DC Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42

ODT DC Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43

Input Electrical Characteristics and Operating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43

Output Electrical Characteristics and Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46

Output Driver Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48

Power and Ground Clamp Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52

AC Overshoot/Undershoot Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53

Input Slew Rate Derating. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55

Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67

Truth Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67

DESELECT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71

NO OPERATION (NOP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72

LOAD MODE (LM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72

ACTIVATE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72

READ. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72

WRITE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72

PRECHARGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73

REFRESH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73

SELF REFRESH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73

Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74

Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74

Mode Register (MR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76

Extended Mode Register (EMR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80

Extended Mode Register 2 (EMR2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84

Extended Mode Register 3 (EMR 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85

ACTIVATE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85

READ. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87

WRITE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97

PRECHARGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

REFRESH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

SELF REFRESH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

Power-Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

Precharge Power-Down Clock Frequency Change. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118

ODT Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

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1Gb: x4, x8, x16 DDR2 SDRAM

Table of Contents

MRS Command to ODT Update Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121

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1Gb: x4, x8, x16 DDR2 SDRAM

State Diagram

Figure 2: Simplified State Diagram

Notes: 1. This diagram provides the basic command flow. It is not comprehensive and do es not iden-

tify all timing requirements or possible command restrictions such as multibank interaction,

power down, entry/exit, etc.

Automatic Sequence

Command Sequence

PRE

Initialization

sequence

Self

refreshing

CKE_L

Refreshing

Precharge

power-

down

Setting

MRS

EMRS

CKE_H

REFRESH

Idle

all banks

precharged

CKE_L

(E)MRS

OCD

default

Activating

ACT

Bank

active

Reading

READ

Writing

WRITE

Active

power-

down

CKE_L

CKE_H

CKE_L

Writing

with

auto

precharge

Reading

with

auto

precharge

READ A

WRITE A

PRE, PRE_A

WRITE A

READ A

PRE , PRE_A

READ A

READ

WRITE

Precharging

CKE_H

WRITE READ

PRE, PRE_A

ACT = ACTIVATE

CKE_H = CKE HIGH, exit power-down or self refresh

CKE_L = CKE LOW, enter power-down

(E)MRS = (Extended) mode register set

PRE = PRECHARGE

PRE_A = PRECHARGE ALL

READ = READ

READ A = READ with auto precharge

REFRESH = REFRESH

SR = SELF REFRESH

WRITE = WRITE

WRITE A = WRITE with auto precharge

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1Gb: x4, x8, x16 DDR2 SDRAM

Functional Description

The DDR2 SDRAM uses a double da ta rate ar chitectur e to ac hieve high -speed oper ation.

The double data rate architecture is essentially a 4n-prefetch architecture, with an inter-

face designed to transfer two data word s per clock cycle at the I/O balls. A single read or

write access for the DDR2 SDRAM effectively consists of a single 4n-bit-wide, one-clock-

cycle data transfer at the internal DRAM core and four corresponding n-bit-wide, one-

half-clock-cycle data transfers at the I/O balls.

A bidirectional data strobe (DQS, DQS#) i s transmitted externally, along with data, for

use in data capture at the receiver. DQS is a strobe transmitted by the DDR2 SDRAM

during READs and by the memory controller during WRITEs. DQS is edge-aligned with

data for READs and center-aligned with data for WRITEs. The x16 offering has two data

strobes, one for the lower byte (LDQS, LDQS#) and one for the upper byte (UDQS,

UDQS#).

The DDR2 SDRAM operates from a differential clock (CK and CK#); the crossing of CK

going HIGH and CK# going LOW will be referred to as the positive edge of CK.

Commands (addre ss and control signals) are registered at every positive edge of CK.

Input data is registered on both edges of DQS, and output data is referenced to both

edges of DQS as well as to both edges of CK.

Read and write accesses to the DDR2 SDRAM are burst-oriented; accesses start at a

selected location and continue for a pr ogramme d number of locations in a progr ammed

sequence . A ccesses b egin with the r egistr ation of an ACTIVA TE command, which is then

followed by a READ or WRITE command. The address bits registered coincident with the

ACTIVATE command are used to select the bank and row to be accessed. The address

bits re gistere d coincident with the READ or WRITE command are used to select the bank

and the starting column location for the burst access.

The DDR2 SDRAM provides for programmable READ or WRITE burst lengths of four or

eight locations. DDR2 SDRAM supports interrupting a burst READ of eight with another

READ or a burst WRITE of eight with another WRITE. An AUTO PRECHARGE function

may be enabled to provide a self-timed row precharge that is initiated at the end of the

burst access.

As with standard DDR SDRAMs, the pipelined, multibank architecture of DDR2

SDRAMs allows for concurrent operation, thereby providing high, effective bandwidth

b y hiding row precharge and activation time.

A self refresh mode is provided, along with a power-saving, power-down mode.

All inputs are compatible with the JEDEC standard for SSTL_18. All full drive-strength

outputs are SSTL_18-compatible.

Industrial Temperature

The industrial temperature (IT) option, if offered, has two simultaneous r equirements:

ambient temperature surrounding the device cannot be less than –40°C or gr eater than

+85°C, and the case te mperat ur e cannot be less than –40°C or gr eater th an +95°C. JED EC

specifications require the refresh rate to double when TC exceeds +85°C; this also

requires use of the high-temperature self refr esh option. Additionally, ODT resistance

and the input/output impedance must be derated when TC is < 0°C or > +85°C.

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1Gb: x4, x8, x16 DDR2 SDRAM

Functional Description

Automotive Temperature

The automotive temperature (AT) option, if offered, has two simultaneous require-

ments: ambient temperature surrounding the device cannot be less than –40°C or

greater than +105°C, and the case temperature cannot be less than –40°C or greater than

+105°C. JEDEC specifications require the refresh rate to double when TC exceeds +85°C;

this also requires use of the high-temperature self refresh option. Additionally, ODT

resistance and the input/output impedance must be derated when TC is < 0°C or >

+85°C.

General Notes • The functionality and the timing specifications discussed in this data sheet are for the

DLL-enabled mode of operation.

• Throughout the data sheet, the various figures and text refer to DQs as “DQ.” The DQ

term is to be interpreted as any and all DQ collectively, unless specifically stated

otherwise. Additionally, the x16 is divided into 2 bytes: the lower byte and the upper

byte. For the lower byte (DQ0–DQ7), DM refers to LDM and DQS ref ers to LDQS. For

the upper byte (DQ8–DQ15), DM refers to UDM and DQS refers to UDQS.

• Complete functionality is described throughout the document, and any page or

diagram may have been simplified to convey a topic and may not be inclusive of all

requirements.

• Any specific requirement takes precedence over a general statement.

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1Gb: x4, x8, x16 DDR2 SDRAM

Functional Block Diagrams

The DDR2 SDRAM is a high-speed CMOS, dynamic random acces s memory. It is inter-

nally configured as a multi-bank DRAM.

Figure 3: 256 Meg x 4 Functional Block Diagram

Bank 5

Bank 6

Bank 7

Bank 4

Bank 7

Bank 4

Bank 5

Bank 6

Row-

address

MUX

Control

logic

Column-

address

counter/

latch

Mode

registers

A0–A13,

BA0–BA2

Address

512

(x16)

8,192

Column

decoder

Bank 0

Memory array

(16,384 x 512 x 16)

Bank 0

row-

address

latch

and

decoder

16,384

Sense amplifiers

Bank

control

logic

Bank 1

Bank 2

Bank 3

Refresh

counter

RCVRS

CK out

DATA

DQS, DQS#

CK, CK#

COL0, COL1

CK in

DRVRS

DLL

MUX

DQS

generator

Read

latch

WRITE

FIFO

and

drivers

Data

Mask

Bank 1

Bank 2

Bank 3

Input

registers

DQ0–DQ3

RAS#

CAS#

CS#

WE#

CK#

Command

decode

CKE

ODT

I/O gating

DM mask logicDQS, DQS#

VDDQ

sw1 sw2

VSSQ

sw1 sw2

ODT control

sw3

sw1 sw2 R3

sw3

sw1 sw2 R3

sw3

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1Gb: x4, x8, x16 DDR2 SDRAM

Functional Block Diagrams

Figure 4: 128 Meg x 8 Functional Block Diagram

Figure 5: 64 Meg x 16 Functional Block Diagram

Bank 5

Bank 6

Bank 7

Bank 4

Bank 7

Bank 4

Bank 5

Bank 6

Row-

address

MUX

Control

logic

Column-

address

counter/

latch

Mode

registers

A0–A13,

BA0–BA2

Address

256

(x32)

8,192

Column

decoder

Bank 0

Memory array

(16,384 x 256 x 32)

Bank 0

row-

address

latch

and

decoder

16,384

Sense amplifers

Bank

control

logic

Bank 1

Bank 2

Bank 3

Refresh

counter

CK out

Data

UDQS, UDQS#

LDQS, LDQS#

CK,CK#

CK, CK#

COL0, COL1

CK in

DRVRS

DLL

MUX

DQS

generator

Read

latch

WRITE

FIFO

and

drivers

Data

Mask

Bank 1

Bank 2

Bank 3

Input

registers

DQ0–DQ7

RAS#

CAS#

CS#

WE#

CK#

Command

decode

CKE

ODT

I/O gating

DM mask logicDQS, DQS#

RDQS#

RDQS

VDDQ

sw1 sw2

VSSQ

sw1 sw2

ODT control

sw3

sw1 sw2 R3

sw3

sw1 sw2 R3

sw3

RCVRS

Bank 5

Bank 6

Bank 7

Bank 4

Bank 7

Bank 4

Bank 5

Bank 6

Row-

address

MUX

Control

logic

Column-

address

counter/

latch

Mode

registers

A0–A12,

BA0–BA2

Address

(x64)

16,384

Column

decoder

Bank 0

Memory array

(8,192 x 256 x 64)

Bank 0

row-

address

latch

and

decoder

8,192

Sense amplifier

Bank

control

logic

Bank 1

Bank 2

Bank 3

Refresh

counter

1616

RCVRS

CK out

DATA

UDQS, UDQS#

LDQS, LDQS#

CK, CK#

COL0, COL1

CK in

DRVRS

DLL

MUX

DQS

generator

UDQS, UDQS#

LDQS, LDQS#

Read

latch

WRITE

FIFO

and

drivers

Data

Mask

Bank 1

Bank 2

Bank 3

Input

registers

UDM, LDM

DQ0–DQ15

sw1 sw2

VSSQ

sw1 sw2

ODT control

RAS#

CAS#

CS#

WE#

CK#

Command

decode

CKE

ODT

I/O gating

DM mask logic

sw3

sw1 sw2 R3

sw3

sw1 sw2 R3

sw3

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1Gb: x4, x8, x16 DDR2 SDRAM

Ball Assignments and Descriptions

Figure 6: 60-Ball FBGA – x4, x8 Ball Assignments (Top View)

465

NF,DQ7

NF,DQ5

ODT

NF,DQ6

NF,DQ4

BA2

NC, RDQS#/NU

DQ1

REF

CKE

BA0

A10

A12

DQS

DQ2

RAS#

CAS#

A11

RFU

DQS#/NU

DQ0

CK#

CS#

A13

DM, DM/RDQS

DQ3

WE#

BA1

RFU

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1Gb: x4, x8, x16 DDR2 SDRAM

Ball Assignments and Descriptions

Figure 7: 84-Ball FBGA – x16 Ball Assignments (Top View)

VDDQ

DQ15

VDDQ

DQ13

VDDQ

DQ7

VDDQ

DQ5

VDD

ODT

VDD

VSS

UDQS#/NU

VSSQ

DQ8

VSSQ

LDQS#/NU

VSSQ

DQ0

VSSQ

CK#

CS#

RFU

VSSQ

UDQS

VDDQ

DQ10

VSSQ

LDQS

VDDQ

DQ2

VSSDL

RAS#

CAS#

A11

RFU

VSS

UDM

VDDQ

DQ11

VSS

LDM

VDDQ

DQ3

VSS

WE#

BA1

RFU

VSSQ

DQ9

VSSQ

DQ1

VSSQ

VREF

CKE

BA0

A10

A12

VDD

DQ14

VDDQ

DQ12

VDD

DQ6

VDDQ

DQ4

VDDL

BA2

VSS

VDD

1234 67895

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1Gb: x4, x8, x16 DDR2 SDRAM

Ball Assignments and Descriptions

Figure 8: 92-Ball FBGA – x4, x8 Ball Assignments (Top View)

234 678951

NF, RDQS#/NU

DQ1

REF

CKE

BA0

A10

A12

NF,DQ6

NF,DQ4

BA2

DM/RDQS

DQ3

WE#

BA1

RFU

DQS

DQ2

RAS#

CAS#

A11

RFU

DQS#/NU

DQ0

CK#

CS#

A13

NF,DQ7

NF,DQ5

ODT

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1Gb: x4, x8, x16 DDR2 SDRAM

Ball Assignments and Descriptions

Figure 9: 92-Ball FBGA – x16 Ball Assignments (Top View)

234 678951

DQ9

DQ1

REF

CKE

BA0

A10

A12

DQ14

DQ12

DQ6

DQ4

BA2

UDM

DQ11

LDM

DQ3

WE#

BA1

RFU

UDQS

DQ10

LDQS

DQ2

RAS#

CAS#

A11

RFU

UDQS#/NU

DQ8

LDQS#/NU

DQ0

CK#

CS#

RFU

DQ15

DQ13

DQ7

DQ5

ODT

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1Gb: x4, x8, x16 DDR2 SDRAM

Ball Assignments and Descriptions

Table 3: FBGA 60-Ball – x4, x8 and 84-Ball – x16 Descriptions

x16 Ball

Number x4, x8 Ball

Number Symbol Type Description

M8, M3, M7,

N2, N8, N3,

N7, P2, P8,

P3, M2,

P7, R2

–A0–A2,

A3–A5,

A6–A8,

A9, A10,

A11, A12

Input Address inputs: Provide th e row address for ACTIVATE

commands, and the column address and auto precharge bit

(A10) for READ/WRITE commands, to select one location out of

the memory array in the respective bank. A10 sampled during a

PRECHARGE command determines whether the PRECHARGE

applies to one bank ( A10 LOW , bank selected by BA0–BA2) or all

banks (A10 HIGH). The address in puts also provide the op-code

during a LOAD MODE command.

–H8, H3, H7,

J2, J8, J3,

J7, K2, K8,

K3, H2,

K7, L2,

A0–A2,

A3–A5,

A6–A8,

A9, A10,

A11, A12,

A13

Input Address inputs: Provide th e row address for ACTIVATE

commands, and the column address and auto precharge bit

(A10) for READ/WRITE commands, to select one location out of

the memory array in the respective bank. A10 sampled during a

PRECHARGE command determines whether the PRECHARGE

applies to one bank ( A10 LOW , bank selected by BA0–BA2) or all

banks (A10 HIGH). The address in puts also provide the op-code

during a LOAD MODE command.

L2, L3,

L1 G2, G3,

G1 BA0–BA2 Input Bank address inputs: BA0–BA2 define to which bank an

ACTIVATE, READ, WRITE, or P RECHARGE command is being

applied. BA0 –B A 2 define which mode register including MR,

EMR, EMR(2), and EMR(3) is loaded during the LOAD MODE

command.

J8, K8 E8, F8 CK, CK# Input Clock: CK and CK# are differential clock inputs. All address and

control input signals are sampled on the crossing of the positive

edge of CK and negative edge of CK#. Output d ata (DQ and

DQS/DQS#) is referenced to the crossings of CK and CK#.

K2 F2 CKE Input Clock enable: CKE (regist ered HIGH) activates and CKE

(registered LOW) deactivates clocking circuitry on the DDR2

SDRAM. The specific circuitry that is enabled/disabled is

dependent on the DDR2 SDRAM configuration and operati ng

mode. CKE LOW provides precharge power-down and SELF

REFRESH operations (all banks idle), or active power-down (row

active in any bank). CKE is synchronou s fo r power-down entry,

power- down exit, ou tput disable, and for self refresh entry. CKE

is asynchronous for self refresh exit. Input buffers (excluding CK,

CK#, CKE, and ODT) are disabled during po wer-down. Input

buffers (excluding CKE) are disabled during self refresh. CKE is

an SSTL_18 input but w ill detec t a LVCMOS LOW level after V DD

is applied during first power-up. After VREF has become stable

during the power-on and initialization sequence, it must be

maintained for proper operation of the CKE receiver. For proper

SELF REFRESH operation, VREF must be maintained.

L8 G8 CS# Input Chip select: CS# enables (registered LOW) and disables

(registered HIGH) the command decoder. All commands are

masked when CS# is registered HIGH. CS# provides for external

bank sele ction on system s with mu ltiple r anks. CS# is cons idered

part of the command code.

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1Gb: x4, x8, x16 DDR2 SDRAM

Ball Assignments and Descriptions

F3, B3 B3 LDM, UDM

DM Input Input data mask: DM is an input mask signal for write data.

Input data is masked when DM is sampled HIGH along with that

input data during a WRITE access. DM is sampled on both edges

of DQS. Although DM balls are input-only, the DM loading is

designed to matc h that of DQ and DQS balls. LDM is DM for

lower byte DQ0–DQ7 and UDM is DM for upper byte

DQ8–DQ15.

K9 F9 ODT Input On-die termination: ODT (registered HIGH) enables

termination resistance internal to the DDR2 SDRAM. When

enabled, ODT is only applied to each of the following balls:

DQ0–DQ15, LDM, UDM, LDQS, LDQS#, UDQS, and UDQS# for

the x16; DQ0–DQ7, DQS, DQS#, RDQS, RDQS#, and DM for the

x8; DQ0–DQ3, DQS, DQS#, and DM for the x4. The ODT input

will be ignored if disabled via the LOAD MODE command.

K7, L7,

K3 F7, G7,

F3 RAS#, CAS#,

WE# Input Command inputs: RAS#, CAS#, and WE# (along with CS#)

define the command being entered.

G8, G2, H7,

H3, H1, H9,

F1, F9, C8,

C2, D7, D3,

D1, D9, B1,

–DQ0–DQ2,

DQ3–DQ5,

DQ6–DQ8,

DQ9–DQ11,

DQ12–DQ14,

DQ15

I/O Data input/output: Bidirectional data bus for 64 Meg x 16.

–C8, C2, D7,

D3, D1, D9,

B1, B9

DQ0–DQ2,

DQ3–DQ5,

DQ6–DQ7

I/O Data input/output: Bidirectional data bus for 128 Meg x 8.

–C8, C2, D7,

D3 DQ0–DQ2,

DQ3 I/O Data input/output: Bidirectional data bus for 256 Meg x 4.

– B7, A8 DQS, DQS# I/O Data strobe: Output with read data, input with write data for

source synchronous operation. Edge-aligned with read data,

center-aligned with write data. DQS# is only used when

differential data strobe mode is enabled via the LOAD MODE

command.

F7, E8 – LDQS, LDQS# I/O Data strobe for lower byte: Output with read data, input

with write data for source synchronous operation. Edge-aligned

with read data, center-aligned with write data. LDQS# is only

used when differential data strobe mode is enabled via the

LOAD MODE command.

B7, A8 – UDQS, UDQS# I/O Data strobe for upper byte: Output with read data, input

with write data for source synchronous operation. Edge-aligned

with read data, center-aligned with write data. UDQS# is only

used when differential data strobe mode is enabled via the

LOAD MODE command.

– B3, A2 RDQS, RDQS# Output Redundant data strobe: For 128 Meg x 8 only. R DQS is

enabled/disabled via the LOAD MODE command to the

extended mode register (EMR). When RDQS is enabled, RDQS is

output with read data only and is ignored during write data.

When RDQS is disabled, ball B3 becomes data mask (see DM

ball). RDQS# is only used when RDQS is enabled and differential

data strobe mode is enabled.

A1, E1, M9,

R1, J9A1, E9, L1, H9 VDD Supply Power supply: 1.8V ±0.1V.

Table 3: FBGA 60-Ball – x4, x8 and 84-Ball – x16 Descriptions (continued)

x16 Ball

Number x4, x8 Ball

Number Symbol Type Description

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1Gb: x4, x8, x16 DDR2 SDRAM

Ball Assignments and Descriptions

A9, C1, C3,

C7, C9, G3, E9,

G1, G7, G9,

A9, C1, C3, C7,

C9 VDDQ Supply DQ power supply: 1.8V ±0.1V. Isolated on the device for

improved noise immunity.

J1E1V

DDL Supply DLL power supply: 1.8V ±0.1V.

J2E2V

REF Supply SSTL_18 reference voltage (VDDQ/2).

A3, E3, J3, N1,

P9 A3, E3, J1, K9 VSS Supply Ground.

J7E7V

SSDL Supply DLL ground: Isolated on the device from VSS and VSSQ.

A7, B2, B8,

D2, D8, E7, F2,

F8, H2, H8

A7, B2, B8, D2,

D8 VSSQ Supply DQ ground: Isolated on the device for improved noise

immunity.

A2, E2 – NC – No connect: These balls should be left unconnected.

– B1, B9, D1, D9 NF – No function: x8: these balls are used as DQ4–DQ7; x4: they are

no function.

A8, E8 – NU – Not used: For x16 only. If EMR(E10) = 0, A8 and E8 are UDQS#

and LDQS#. If EMR(E10) = 1, then A8 and E8 are not used.

– A2, A8 NU – Not used: For x8 only. If EMR(E10) = 0, A2 and E8 are RDQS#

and DQS#. If EMR(E10) = 1, then A2 and E8 are not used.

R8, R3, R7 L3, L7 RFU – Reserved for future use: Row address bits A13 (x16 only),

A14, and A15.

Table 3: FBGA 60-Ball – x4, x8 and 84-Ball – x16 Descriptions (continued)

x16 Ball

Number x4, x8 Ball

Number Symbol Type Description

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1Gb: x4, x8, x16 DDR2 SDRAM

Ball Assignments and Descriptions

Table 4: 92-Ball – x4, x8, x16 Descriptions

x16 Ball

Number x4, x8 Ball

Number Symbol Type Description

R8, R3, R7,

T2, T8, T3, T7,

U2, U8, U3,

R2, U7, V2

–A0–A2,

A3–A6,

A7–A9,

A10–A12

Input Address inputs: Provide the row address for ACTIVATE

commands, and the co lu mn address and auto precharge bit (A10)

for READ/WRITE commands, to select one location out of the

memory array in the respective bank. A10 sampled during a

PRECHARGE command determines whether the PRECHARGE

applies to one bank (A10 LOW, bank selected by BA0–BA2) or all

banks (A10 HIGH). The address inputs also provide the op-code

during a LOAD MODE command.

–R8, R3, R7, T2,

T8, T3, T7, U2,

U8, U3, R2,

U7, V2, V8

A0–A3,

A4–A7,

A8–A10,

A11–A13

Input Address inputs: Provide the row address for ACTIVATE

commands, and the co lu mn address and auto precharge bit (A10)

for READ/WRITE commands, to select one location out of the

memory array in the respective bank. A10 sampled during a

PRECHARGE command determines whether the PRECHARGE

applies to one bank (A10 LOW, bank selected by BA0–BA2) or all

banks (A10 HIGH). The address inputs also provide the op-code

during a LOAD MODE command.

P2, P3, P1 P2, P3, P1 BA0–BA2 Input Bank address inputs: BA0–BA2 define to which bank an

ACTIVATE, READ, WRITE, or PRECHARGE command is being

applied. BA0–BA2 define which mode register incl ud in g MR , EMR,

EMR(2), and EMR(3) is loaded during the LOAD MODE command.

M8, N8 M8, N8 CK, CK# Input Clock: CK and CK# are differential clock inputs. All address and

control input signals are sampled on the crossing of the positive

edge of CK and negative edge of CK#. Output data (DQ and DQS/

DQS#) is referenced to the crossings of CK and CK#.

N2 N2 CKE Input Clock enable: CKE (registered HIGH) activates and CKE (registered

LOW) deactivates clocking circuitry on the DDR2 SDRAM. The

specific circuitry that is enab led/disabled is dependent on the

DDR2 SDRAM config uration and operating mode. CKE LOW

provides precharge power-down and SELF REFRESH operation (all

banks idle), or active power-down (row active in any bank). CKE is

synchronous for power-down entry, power-down exit, output

disable, and self refresh entry. CKE is asynchronous for self refresh

exit. Input buffers (excluding CK, CK#, CKE, and ODT) are disabled

during power-down. Input buffers (excluding CKE) are disabled

during self refresh. CKE is an SSTL_18 input but will detect a

LVCMOS LOW level after VDD is applied during first power-up.

After VREF has become stable during the power-on and

initialization sequence, it must be ma in ta ined for prop e r

operation of the CKE receiver. For proper SELF REFRESH operation,

VREF must be maintained.

P8 P8 CS# Input Chip select: CS# enables (registered LOW) and disables (registered

HIGH) the command decoder. All commands are masked when CS#

is registered HIGH. CS# provides for external bank se le ction on

systems with multiple ranks. CS# is considered part of the

command code.

J3, E3 J3 LDM, UDM,

(DM) Input Input data mask: DM is an input mask signal for write data. Input

data is masked when DM is concurrently sampled HIGH during a

WRITE access. DM is sampled on both edges of DQS. Although DM

balls are input-only, the DM loading is designed to match that of

DQ and DQS balls. LDM is DM for lower byte DQ0–DQ7 and UDM is

DM for upper byte DQ8–DQ15.

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1Gb: x4, x8, x16 DDR2 SDRAM

Ball Assignments and Descriptions

N9 N9 ODT Input On-die termination: ODT (registered HIGH) enables termination

resistance internal to the DDR2 SDRAM. When enabled, ODT is

only applied to each of the fo llowing balls: DQ0–DQ15, LDM,

UDM, LDQS, LDQS#, UDQS, and UDQS# for the x16; DQ0–DQ7,

DQS, DQS#, RDQS, RDQS#, and DM for the x8; DQ0–DQ3, DQS,

DQS#, and DM for the x4. The ODT input will be ignored if

disabled via the LOAD MODE command.

N7, P7,

N3 N7, P7,

N3 RAS#, CAS#,

WE# Input Command inputs: RAS#, CAS#, and WE# (along with CS#) define

the command being entered.

K8, K2, L7, L3,

L1, L9, J1, J9,

F8, F2, G7,

G3, G1, G9,

E1, E9

–DQ0–DQ3,

DQ4–DQ7,

DQ8–DQ10,

DQ11–DQ13,

DQ14–DQ15

I/O Data input/output: Bidirectional data bus for 64 Meg x 16.

–K8, K2, L7, L3,

L1, L9, J1, J9DQ0–DQ3,

DQ4–DQ7 I/O Data input/output: Bidirectional data bus for 128 Meg x 8.

–K8, K2, L7, L3 DQ0–DQ3 I/O Data input/output: Bidirectional dat a bus for 256 Meg x 4.

–J7, H8 DQS, DQS# I/O Data strobe: Output with read data, input with write data for

source synchronous operation . Edge-aligned with read data,

center-aligned with write data. DQS# is only used when

differential data strobe mode is enabled via the LOAD MODE

command.

J7,

H8 –LDQS,

LDQS# I/O Data strobe for lower byte: Output with read data, input with

write data for source synchronous operation. Edge-ali gned with

read data, center -alig ned with write data. LDQS# is only used

when differential data strobe mode is enabled via the LOAD

MODE command.

E7,

D8 – UDQS,

UDQS# I/O Data strobe for upper byte: Output with read data, input with

write data for source synchronous operation. Edge-ali gned with

read data, center -alig ned with write data. UDQS# is only used

when differential data strobe mode is enabled via the LOAD

MODE command.

–J3, H2 RDQS, RDQS# Output Redundant data strobe: For x8 only. RDQS is enabled/disabled

via the LOAD MODE command to the extended mode register

(EMR). When RDQS is enabled, RDQS is output with read data only

and is ignored during write data. When RDQS is disabled, ball J3

becomes data mask (see DM ball). RDQS# is only used when RDQS

is enabled and differential data strobe mode is enabled.

D1, H1, M9,

R9, V1 D1, H1, M9,

R9, V1 VDD Supply Power supply: 1.8V ±0.1V.

D9, F1, F3, F7,

F9, H9, K1,

K3, K7, K9

D9, H9, K1,

K3, K7, K9 VDDQ Supply DQ power supply: 1.8V ±0.1V. Isolated on the device for

improved noise immunity.

M1 M1 VDDL Supply DLL power supply: 1.8V ±0.1V.

M2 M2 VREF Supply SSTL_18 reference voltage (VDDQ/2).

D3, H3, M3,

T1, U9 D3, H3, M3,

T1, U9 VSS Supply Ground.

M7 M7 VSSDL Supply DLL ground: Isolated on the device from VSS and VSSQ.

Table 4: 92-Ball – x4, x8, x16 Descriptions (continued)

x16 Ball

Number x4, x8 Ball

Number Symbol Type Description

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1Gb: x4, x8, x16 DDR2 SDRAM

Ball Assignments and Descriptions

D7, E2, E8,

G2, G8, H7,

J2, J8, L2, L8

D7, H7, J2,

J8, L2, L8 VSSQ Supply DQ ground: Isolated on the device for improved noise immunity.

A1, A2, A8,

A9, D2, H2,

AA1, AA2,

AA8, AA9

A1, A2, A8,

A9, D2, D8,

E1–E3, E7–E9,

F1–F3, F7–F9,

G1–G3,

G7–G9, AA1,

AA2, AA8,

AA9

NC – No connect: These balls should be left unconnected.

–J1, J9, L1, L9,

H2 NF – No function: x8: these balls are used as DQ4–DQ7; x4, they are no

function.

D8, H8 – NU – Not used: For x16 only. If EMR(E10) = 0, D8 and H8 are UDQS# and

LDQS#. If EMR(E10) = 1, then D8 and H8 are not used.

– H2, H8 NU – Not used: For x8 only. If EMR(E10) = 0, H2 and H8 are RDQS# and

DQS#. If EMR(E10) = 1, then H2 and H8 are not used.

V3, V7, V8 V3, V7 RFU – Reserved for fut ure use: Row address bits A13 (V8 ) , A14 (V3),

and A15 (V7) are reserved.

Table 4: 92-Ball – x4, x8, x16 Descriptions (continued)

x16 Ball

Number x4, x8 Ball

Number Symbol Type Description

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1Gb: x4, x8, x16 DDR2 SDRAM

Package Dimensions

Figure 10: 60-Ball FBGA Package – x4, x8

Notes: 1. All dimensions are in millimeters.

Ball A1 ID

1.20 MAX

Mold compound: epoxy novolac

Substrate material: plastic laminate

Solder ball material:

96.5% Sn, 3% Ag, 0.5% Cu (Pb-free)

62% Sn, 36% Pb, 2% Ag (with lead)

0.8 TYP

8 ±0.10

987 321

4 ±0.05

3.20

0.8 ±0.05

0.155 ±0.013

Seating

plane

6.40

1.8 ±0.05

CTR

0.1 A

60X Ø0.45

Dimensions

apply to solder

balls post reflow.

Pre-reflow balls

are Ø0.45 on Ø0.33

NSMD ball pads.

11.5 ±0.10

Ball A1 ID

0.8 TYP

5.75 ±0.05

manufacturing visual aid

a = 0.38 (NOM)

b = 1.17 (NOM)

c = 2.20 (NOM)

d = 2.90 (NOM)

Nonconductive

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1Gb: x4, x8, x16 DDR2 SDRAM

Package Dimensions

Figure 11: 84-Ball FBGA Package – x16

Notes: 1. All dimensions are in millimeters.

Ball A1 ID

1.2 MAX

Mold compound: epoxy novolac

Substrate material: plastic laminate

0.8 TYP

8 ±0.1

4 ±0.05

3.2

5.6

0.8 ±0.05

0.155 ±0.013

Seating

plane A

11.2

6.4

1.8 ±0.05

CTR

0.1 A

84X Ø0.45

12.5 ±0.1

Ball A1 ID

6.25 ±0.05

987 321

Dimensions

apply to solder

balls post reflow.

Pre-reflow balls

are Ø0.42 on Ø0.33

NSMD ball pads.

0.8 TYP

Solder ball material:

96.5% Sn, 3% Ag, 0.5% Cu (Pb-free)

62% Sn, 36% Pb, 2% Ag (with lead)

manufacturing visual aid

a = 0.38 (NOM)

b = 1.17 (NOM)

c = 2.70 (NOM)

d = 3.40 (NOM)

Nonconductive

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1Gb: x4, x8, x16 DDR2 SDRAM

Package Dimensions

Figure 12: 92-Ball FBGA Package – x4, x8, x16

Notes: 1. All dimensions are in millimeters.

BALL A1 ID

SUBSTRATE:

PLASTIC LAMINATE

MOLD COMPOUND:

EPOXY NOVOLAC

SOLDER BALL MATERIAL:

96.5% Sn, 3% Ag, 0.5% Cu (Pb-FREE)

62% Sn, 36% Pb, 2% Ag (WITH LEAD)

SOLDER BALL PAD: Ø 0.33

NON SOLDER MASK DEFINED

SEATING

PLANE

0.80 ±0.05

BALL A9

SOLDER BALL

DIAMETER REFERS

TO POST REFLOW

CONDITION. THE

PRE-REFLOW

DIAMETER IS Ø 0.42.

0.10 C C

0.17 MAX

0.80

TYP

16.00

1.20 MAX

8.00

9.50 ±0.05

1.80 ±0.05

CTR

BALL A1 ID

BALL A1

0.80

TYP

5.50 ±0.05 3.20

11.00 ±0.10

6.40

92X Ø 0.45

2.40

19.00 ±0.10

NONCONDUCTIVE

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1Gb: x4, x8, x16 DDR2 SDRAM

FBGA Package Capacitance

Notes: 1. This par amet er is sa mpl ed. VDD = +1.8V ±0.1V, VDDQ = +1.8V ±0.1V, V REF = VSS, f = 100 MHz,

TC = 25°C, VOUT(DC) = VDDQ/2, VOUT (peak-to-peak) = 0.1V. DM input is grouped with I/O

balls, reflecting the fact that they are matched in loading.

2. The input capacitance per ball group will not differ by more than this maximum amount for

any given device.

3. ΔC are not pass/fail parameters but rather targets.

4. Reduce MAX limit by 0.25pF for -25, -25E, -187E speed devices.

5. Reduce MAX limit by 0.5pF for -3, -3E, -25, -25E, -187E speed devices.

6. The I/O capacitance per DQS and DQ byte/group will not differ by more than this maximum

amount for any given device.

Table 5: Input Capacitance

Parameter Symbol Min Max Units Notes

Input capacitance: CK, CK# CCK 1.0 2.0 pF 1

Delta input capacitance: CK, CK# CDCK –0.25pF2, 3

Input capacitance: Address bal ls, bank address balls, CS#,

RAS#, CAS#, WE#, CKE, ODT CI1.0 2.0 pF 1, 4

Delta input capacitance: Address balls, bank address balls,

CS#, RAS#, CAS#, WE#, CKE, ODT CDI –0.25pF2, 3

Input/outp ut ca paci tance: DQ, DQS, DM, NF CIO 2.5 4.0 pF 1, 5

Delta input/output capacitance: DQ, DQS, DM, NF CDIO – 0.5 pF 3, 6

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1Gb: x4, x8, x16 DDR2 SDRAM

Electrical Specifications – Absolute Ratings

S tresses gr eater than those listed may cause permanent damage to the device . This is a

stress r ating only, and functional operation of the device at these or any other conditions

outside those indic ated in the operational sections of this specification is not implied.

Exposure to absolute maximum rating conditions for extended periods may affect reli-

ability.

Notes: 1. VDD, VDDQ, and VDDL must be within 300mV of each other at all times.

2. VREF ≤ 0.6 × VDDQ; however, VREF may be ≥ VDDQ provided that VREF ≤ 300mV.

3. Voltage on any I/O may not exceed voltage on VDDQ.

Temperature and Thermal Impedance

It is imperative that the DDR2 SDRAM device’s te m perature specifica tions, show n in

Table 7 on page 25, be maintained in order to ensure the junction temperature is in the

proper operating range to meet data sheet specifications. An important step in main-

taining the proper junction temperature is using the device’s thermal impedances

correctly. The thermal impedances are listed in Table 8 on page 25 for the applicable

and available die revision and packages.

Incorr ectly using thermal impedances can produce significant errors. Read Micron tech-

nical note TN-00-08, “ Ther m al Applications” prior to using the thermal impedanc e s

listed in Table 8 on pa ge 2 5. For designs that are expected to last seve ral years and

require the flexibility to use several DRAM die shrinks, consider using final tar get theta

values (rather than existing values) to account for increased thermal impedances from

the die size reduction.

The DDR2 SDRAM device’s safe junction temperature range can be maintained when

the TC specifi cation is not exceeded. In applications where the device’s ambient temper-

ature is too high, use of forced air and/or heat sinks may be requir ed in order to satisfy

the case temperature specifications.

Table 6: Absolute Maximum DC Ratings

Parameter Symbol Min Max Units Notes

VDD supply voltage relative to VSS VDD –1.0 2.3 V 1

VDDQ supply voltage relative to VSSQVDDQ –0.5 2.3 V 1, 2

VDDL supply voltage relative to VSSLVDDL–0.5 2.3 V 1

Voltage on any ball relative to VSS VIN, VOUT –0.5 2.3 V 3

Input leakage current; any input 0V ≤ VIN ≤ VDD; all other balls

not under test = 0V II–5 5 µA

Output leakage current; 0V ≤ VOUT ≤ VDDQ; DQ and ODT

disabled IOZ –5 5 µA

VREF leakage current; VREF = Valid VREF level IVREF –2 2 µA

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1Gb: x4, x8, x16 DDR2 SDRAM

Electrical Specifications – Absolute Ratings

Notes: 1. MAX storage case temperature; TSTG is measured in the center of the package, as shown in

Figure 13. This case temperature limit is allowed to be exceeded briefly during package

reflow , as noted in Micron technical note TN-00-15, “Recommended Soldering Parameters.”

2. MAX operating case temperature; TC is measured in the center of the package, as shown in

Figure 13.

3. Device functionality is not guaranteed if the device exceeds maximum TC during operation.

4. Both temperature specifications must be satisfied.

5. Operating ambient temperature surroundi ng the package.

Figure 13: Example Temperature Test Point Location

Notes: 1. Thermal resistance data is based on a number of samples from multiple lots and should be

viewed as a typical number.

2. This is an estimate; simulated number and actual results could vary.

Table 7: Temperature Limits

Parameter Symbol Min Max Units Notes

Storage temperature TSTG –55 150 °C 1

Operating temperature: commercial TC085°C2, 3

Operating temperature: industrial TC–40 95 °C 2, 3, 4

TA–40 85 °C 4, 5

Table 8: Thermal Impedance

Die Revision Package Substrate θ JA (°C/W)

Airflow = 0m/s θ JA (°C/W)

Airflow = 1m/s θ JA (°C/W)

Airflow = 2m/s θ JB (°C/W) θ JC (°C/W)

A192-ball 2-layer 38.3 25.3 21.3 11.8 1.7

4-layer 24.7 18.1 16.0 10.8

E160-ball 2-layer 56.7 42.1 36.8 22.7 2.5

4-layer 40.2 32.8 29.9 22.1

84-ball 2-layer 52.9 41.3 35.7 21.6 2.5

4-layer 38.4 32 28.9 21.5

Last shrink

target268-ball 2-layer 65 48 45 25 5.0

4-layer 45 38 34 25

84-ball 2-layer 55 45 37 23 5.0

4-layer 40 35 30 23

Width (W)

0.5 (W)

Length (L)

0.5 (L)

Test point

Lmm x Wmm FGBA

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1Gb: x4, x8, x16 DDR2 SDRAM

Electrical Specifications – I

Parameters

Electrical Specifications – IDD Parameters

IDD Specifications and Conditions

Table 9: General IDD Parameters

IDD Parameters -187E -25E -25 -3E -3 -37E -5E Units

CL (IDD)7564543

tCK

tRCD (IDD)13.125 12.5 15 12 15 15 15 ns

tRC (IDD)58.125 57.5 60 57 60 60 55 ns

tRRD (IDD) - x4/x8 (1KB) 7.5 7.5 7.5 7.5 7.5 7.5 7.5 ns

tRRD (IDD) - x16 (2KB) 10 10 10 10 10 10 10 ns

tCK (IDD)1.875 2.5 2.5 3 3 3.75 5 ns

tRAS MIN (IDD)45 45 45 45 45 45 40 ns

tRAS MAX (IDD)70,000 70,000 70,000 70,000 70,000 70,000 70,000 ns

tRP (IDD)13.125 12.5 15 12 15 15 15 ns

tRFC (IDD - 256Mb) 75 75 75 75 75 75 75 ns

tRFC (IDD - 512Mb) 105 105 105 105 105 105 105 ns

tRFC (IDD - 1Gb) 127.5 127.5 127.5 127.5 127.5 127.5 127.5 ns

tRFC (IDD - 2Gb) 195 195 195 195 195 195 195 ns

tFAW (IDD) - x4/x8 (1KB) 35 35 35 37.5 37.5 37.5 37.5 ns

tFAW (IDD) - x16 (2KB) 45 45 45 50 50 50 50 ns

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1Gb: x4, x8, x16 DDR2 SDRAM

Electrical Specifications – I

Parameters

IDD7 Conditions

The detailed timings are shown below for I DD7. Wher e g ener al IDD parameters in Table 9

on page 26 conflict with pattern requirement s of Table 10, then Table 10 requirements

take precedence.

Notes: 1. A = active; RA = read auto precharge; D = dese le c t.

2. All banks are being int erleaved at tRC (IDD) without violating tRRD (IDD) using a BL = 4.

3. Control and address bus in puts are stable during deselects.

Table 10: IDD7 Timing Patterns (8-Bank Interleave READ Operation)

Speed Grade IDD7 Timing Patterns

Timing patterns for 8-bank x4/x8 devices

-5E A0 RA0 A1 RA1 A2 RA2 A3 RA3 A4 RA4 A5 RA5 A6 RA6 A7 RA7

-37E A0 RA0 A1 RA1 A2 RA2 A3 RA3 D D A4 RA4 A5 RA5 A6 RA6 A7 RA7 D D

-3 A0 RA0 D A1 RA1 D A2 RA2 D A3 RA3 D D A4 RA4 D A5 RA5 D A6 RA6 D A7 RA7 D D

-3E A0 RA0 D A1 RA1 D A2 RA2 D A3 RA3 D D A4 RA4 D A5 RA5 D A6 RA6 D A7 RA7 D D

-25 A0 RA0 D A1 RA1 D A2 RA2 D A3 RA3 D D D A4 RA4 D A5 RA5 D A6 RA6 D A7 RA7 D D D

-25E A0 RA0 D A1 RA1 D A2 RA2 D A3 RA3 D D D A4 RA4 D A5 RA5 D A6 RA6 D A7 RA7 D D D

-187E A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 D D D D D A4 RA4 D D A5 RA5 D D A6 RA6 D D A7 RA7 D D D

D D

Timing patterns for 8-bank x16 devices

-5E A0 RA0 A1 RA1 A2 RA2 A3 RA3 D D A4 RA4 A5 RA5 A6 RA6 A7 RA7 D D

-37E A0 RA0 D A1 RA1 D A2 RA2 D A3 RA3 D D D A4 RA4 D A5 RA5 D A6 RA6 D A7 RA7 D D D

-3 A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 D D D A4 RA4 D D A5 RA5 D D A6 RA6 D D A7 RA7 D D D

-3E A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 D D D A4 RA4 D D A5 RA5 D D A6 RA6 D D A7 RA7 D D D

-25 A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 D D D D A4 RA4 D D A5 RA5 D D A6 RA6 D D A7 RA7 D D D D

-25E A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 D D D D A4 RA4 D D A5 RA5 D D A6 RA6 D D A7 RA7 D D D D

-187E A0 RA0 D D D D A1 RA1 D D D D A2 RA2 D D D D A3 RA3 D D D D A4 RA4 D D D D A5 RA5 D D D D A6 RA6

D D D D A7 RA7 D D D D

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1Gb: x4, x8, x16 DDR2 SDRAM

Electrical Specifications – I

Parameters

Table 11: DDR2 IDD Specifications and Conditions (Die Revision A)

Notes: 1–7 (page 31) apply to the entire table

Parameter/Condition Symbol Configuration -25E/

-25 -3E/-3 -37E -5E Units

Operating one bank active-precharge current:

tCK = tCK (IDD), tRC = tRC (IDD),

tRAS = tRAS MIN (IDD); CKE is HIGH, CS# is HIGH

between valid commands; address bus inputs are

switching; Data bus inputs are switching

IDD0 x4, x8 100 90 80 70 mA

x16 150 135 110 110

Operating one bank active-read-precharge

current: IOUT = 0mA; BL = 4, CL = CL (IDD), AL = 0;

tCK = tCK (IDD), tRC = tRC (IDD),

tRAS = tRAS MIN (IDD), tRCD = tRCD (IDD); CKE is

HIGH, CS# is HIGH between valid commands;

address bus inputs are switching; Data pattern is

same as IDD4W

IDD1 x 4, x8 110 100 95 80 mA

x16 175 160 130 125

Precharge power-down current: All banks idle;

tCK = tCK (IDD); CKE is LOW; Other control and

address bus inputs are stable; Data bus inputs are

floating

IDD2Px4, x8, x167777mA

Precha rge quiet standby cur rent: All banks idle;

tCK = tCK (IDD); CKE is HIGH, CS# is HIGH; Other

control and address bus inputs are stable; Data bus

inputs are floating

IDD2Q x4, x8 65 55 41 35 mA

x16 75654540

Precharge standby current: All banks idle;

tCK = tCK (IDD); CKE is HIGH, CS# is HIGH; Other

control and address bus inputs are switching; Data

bus inputs are switching

IDD2N x4, x8 70 60 45 40 mA

x16 80705040

Active power-down current: All banks open;

tCK = tCK (IDD); CKE is LOW; Other control and

address bus inputs are stable; Data bus inputs are

floating

IDD3P Fast PDN exit

MR12 = 0 50 45 40 35 mA

Slow PDN exit

MR12 = 1 18 18 18 18

Active standby current: All banks open;

tCK = tCK (IDD), tRAS = tRAS MAX (IDD), tRP = tRP

(IDD); CKE is HIGH, CS# is HIGH between valid

commands; Other control and address bus inputs

are switching; Data bus inputs are switching

IDD3N x4, x8 75 70 60 45 mA

x16 85756055

Operating burst write current: All banks open,

continuous burst writes; BL = 4, CL = CL (IDD), AL = 0;

tCK = tCK (IDD), tRAS = tRAS MAX (IDD), tRP = tRP

(IDD); CKE is HIGH, CS# is HIGH between valid

commands; address bus inputs are switching; Data

bus inputs are switching

IDD4W x4, x8 185 160 140 110 mA

x16 315 210 180 160

Operating burst read current: All banks ope n,

continuous burst reads, IOUT = 0mA; BL = 4,

CL=CL(I

DD), AL = 0; tCK = tCK (IDD),

tRAS = tRAS MAX (IDD), tRP = tRP (IDD); CKE is HIGH,

CS# is HIGH between valid commands; address bus

inputs are switching; Data bus inputs are switching

IDD4R x4, x8 190 160 145 110 mA

x16 320 220 180 160

Burst refresh current: tCK = tCK (IDD); REFRESH

command at every tRFC (IDD) interval; CKE is HIGH,

CS# is HIGH between valid commands; Other

control and address bus inputs are switching; Data

bus inputs are switching

IDD5 x 4, x8 280 270 250 220 mA

x16 280 270 250 240

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1Gb: x4, x8, x16 DDR2 SDRAM

Electrical Specifications – I

Parameters

Self refresh current: CK and CK# at 0V;

CKE ≤ 0.2V; Other control and address bus inputs

are floating; Data bus inputs are floating

IDD6x4, x8, x167777mA

IDD6L 5555

Operating bank interleave read current: All

bank interleaving reads, IOUT = 0mA; BL = 4,

CL = CL (IDD), AL = tRCD (IDD) - 1 × tCK (IDD);

tCK = tCK (IDD), tRC = tRC (IDD), tRRD = tRRD (IDD),

tRCD = tRCD (IDD); CKE is HIGH, CS# is HIGH between

valid commands; address bus inputs are stable

during deselects; Data bus inputs are switching; See

“IDD7 Conditions” on page 27 for details

IDD7 x 4, x8 335 300 290 260 mA

x16 440 350 340 330

Table 11: DDR2 IDD Specifications and Conditions (Die Revision A) (continued)

Notes: 1–7 (page 31) apply to the entire table

Parameter/Condition Symbol Configuration -25E/

-25 -3E/-3 -37E -5E Units

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1Gb: x4, x8, x16 DDR2 SDRAM

Electrical Specifications – I

Parameters

Table 12: DDR2 IDD Specifications and Conditions (Die Revision E)

Notes: 1–7 (page 31) apply to the entire table

Parameter/Condition Symbol Configuration -187E -25E/

-25 -3E/

-3 -37E -5E Units

Operating one bank active-precharge current:

tCK = tCK (IDD), tRC = tRC (IDD), tRAS = tRAS MIN (IDD);

CKE is HIGH, CS# is HIGH between valid commands;

Address bus inputs are switching; Data bus inputs are

switching

IDD0 x4, x8 115 90 85 70 70 mA

x16 180 150 135 110 110

Operating one bank active-read-precharge curr ent:

IOUT = 0mA; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD),

tRC = tRC (I DD), tRAS = tRAS MIN (IDD), tRCD = tRCD (IDD);

CKE is HIGH, CS# is HIGH between valid commands;

Address bus inputs are switching; Data pattern is same

as IDD4W

IDD1 x4, x8 130 110 100 95 9 0 mA

x16 210 175 130 120 115

Precharge power-down current: All banks idle;

tCK = tCK (IDD); CKE is LOW; Other control and address

bus inputs are stable; Data bus inputs are floating

IDD2P x4, x8, x16 7 7 7 7 7 mA

Precharge quiet standby current: All banks idle;

tCK = tCK (IDD); CKE is HIGH, CS# is HIGH; Other control

and address bus inputs are stable; Data bus inputs are

floating

IDD2Q x4, x8 60 50 40 40 35 mA

x16 90 75 65 45 40

Precharge standby current: All banks idle;

tCK = tCK (IDD); CKE is HIGH, CS# is HIGH; Other control

and address bus inputs are switching; Data bus inputs

are switching

IDD2N x4, x8 60 50 40 40 35 mA

x16 95 80 70 50 40

Active power-down current: All banks open;

tCK = tCK (IDD); CKE is LOW; Other control and address

bus inputs are stable; Data bus inputs are floating

IDD3P Fast exit

MR12 = 0 50 40 30 30 30 mA

Slow exit

MR12 = 1 10 10 10 10 10

Active standby current: All banks open;

tCK = tCK (IDD), tRAS = tRAS MAX (IDD), tRP = tRP (IDD);

CKE is HIGH, CS# is HIGH between valid commands;

Other control and address bus inputs are switching;

Data bus inputs are switching

IDD3N x4, x8 70 60 55 45 40 mA

x16 95 85 75 60 55

Operating burst write current: All banks open,

continuous burst writes; BL = 4, CL = CL (IDD), AL = 0;

tCK = tCK (IDD), tRAS = tRAS MAX (IDD), tRP = tRP (IDD);

CKE is HIGH, CS# is HIGH between valid commands;

Address bus inputs are switching; Data bus inputs are

switching

IDD4W x4 190 145 120 110 90 mA

x8 210 160 135 125 105

x16 405 315 200 180 160

Operating burst read current: All banks open,

continuous burst reads, IOUT = 0mA; BL = 4,

CL = CL (IDD), AL = 0; tCK = tCK (IDD),

tRAS = tRAS MAX (IDD), tRP = tRP (IDD); CKE is HIGH, CS#

is HIGH between valid commands; Address bus inputs

are switching; Data bus inputs are switching

IDD4R x4 190 145 120 125 105 mA

x8 210 160 135 110 90

x16 420 320 220 180 160

Burst refresh current: tCK = tCK (IDD); REFRESH

command at every tRFC (IDD) interval; CKE is HIGH, CS# is

HIGH between valid commands; Other control and

address bus inputs are switching; Data bus inputs are

switching

IDD5 x4, x8 265 235 215 210 205 mA

x16 300 280 270 250 240

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1Gb: x4, x8, x16 DDR2 SDRAM

Electrical Specifications – I

Parameters

Notes: 1. IDD specifications are tested after the device is properly initialized. 0°C ≤ TC ≤ +85°C.

VDD = +1.8V ±0.1V, VDDQ = +1.8V ±0.1V, VDDL = +1.8V ±0.1V, VREF = VDDQ/2.

2. Input slew rate is specified by AC parametric test conditions (Table 9 on page 26).

3. IDD parameters are specified with ODT disabled.

4. Data bus consists of DQ, DM, DQS, DQS#, RDQS, RDQS#, LDQS, LDQS#, UDQS, and UDQS#.

IDD values must be met with all combinations of EMR bits 10 and 11.

5. Defini tions for IDD conditio ns:

6. IDD1, IDD4R, and IDD7 require A12 in EMR to be enabled during testing.

7. The following IDDs must be derated (IDD limits increase) on IT-option and AT-option devices

when operated outside of the range 0°C ≤ TC ≤ 85°C:

Self refresh current: CK and CK# at 0V; CKE ≤ 0.2V;

Other control and address bus inputs are floating; Dat a

bus inputs are floating

IDD6 x4, x8, x16 7 7 7 7 7 mA

IDD6L 5 5 5 5 5

Operating bank interleave read current: All bank

interleaving reads, IOUT = 0mA; BL = 4, CL = CL (IDD),

AL = tRCD (IDD) - 1 × tCK (IDD); tCK = tCK (IDD),

tRC = tRC (IDD), tRRD = tRRD (I DD), tRCD = tRCD (IDD); CKE

is HIGH, CS# is HIGH between valid commands; Address

bus inputs are stable during deselects; Data bus inputs

are switch in g; Se e “IDD7 Conditions” on page 27 for

details

IDD7 x4, x8 425 335 280 270 260 mA

x16 520 440 350 330 300

LOW VIN ≤ VIL(AC) MAX

HIGH VIN ≥ VIH(AC) MIN

Stable Inputs stable at a HIGH or LOW level

Floating Inputs at VREF = VDDQ/2

Switching Inputs changing between HIGH and LOW every other clock cycl e (once per

two clocks) for address and control signals

Switching Inputs changing between HIGH and LOW every other data transfer (once per

clock) for DQ signals, not including masks or strobes

When

TC ≤ 0°C IDD2P and IDD3P (slow) must be derated by 4 percent; IDD4R and IDD5W must be

derated by 2 percent; and IDD6 and IDD7 must be derated by 7 percent

When

TC ≥ 85°C IDD0, IDD1, IDD2N, IDD2Q, IDD3N, IDD3P (fast), IDD4R, IDD4W, and IDD5W must be

derated by 2 percent; IDD2P must be derated by 20 percent; IDD3Pslow must be

derated by 30 percent; and IDD6 must be derated by 80 percent (IDD6 will

increase by this amount if TC < 85°C and the 2X refresh option is still enabled)

Table 12: DDR2 IDD Specifications and Conditions (Die Revision E) (continued)

Notes: 1–7 (page 31) apply to the entire table

Parameter/Condition Symbol Configuration -187E -25E/

-25 -3E/

-3 -37E -5E Units

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1Gb: x4, x8, x16 DDR2 SDRAM

AC Timing Operating Specifications

Table 13: AC Operating Conditions for -187E, -25E, -3E, -3, -37E, and -5E Speeds (Sheet 1 of 7)

Not all speed grades listed may be supported for this device; refer to the title page for speeds supporte d;

Notes: 1–5 (page 39) apply to the entir e table; VDDQ = +1.8V ±0.1V, VDD = +1.8V ±0.1V

AC Characteristics -187E -25E -25 -3E -3 -37E -5E

Units NotesParameter Symbol Min Max Min Max Min Max Min Max Min Max Min Max Min Max

Clock

Clock cycle

time CL = 7 tCK

(AVG) 1.8758.0––––––––––––ns6, 7, 8,

CL = 6 tCK

(AVG) 2.58.0––2.58.0––––––––

CL = 5 tCK

(AVG) 3.0 8.0 2.5 8.0 3.0 8.0 3.0 8.0 3.0 8.0 – – – –

CL = 4 tCK

(AVG) – – 3.75 8.0 3.75 8.0 3.0 8.0 3.75 8.0 3.75 8.0 5.0 8.0

CL = 3 tCK

(AVG) – – ––––––5.08.05.08.05.08.0

CK high-level

width

tCH

(AVG) 0.48 0.52 0.48 0.52 0.48 0.52 0.48 0.52 0.48 0.52 0.48 0.52 0.48 0.52 tCK 10

CK low-level width tCL

(AVG) 0.48 0.52 0.48 0.52 0.48 0.52 0.48 0.52 0.48 0.52 0.48 0.52 0.48 0.52 tCK

Half clock period tHP MIN = lesser of

CH and

MAX = n/a ps 11

Absolute tCK tCK

(ABS) MIN = tCK (AVG) MIN + tJITPER (MIN)

MAX = tCK (AVG) MAX + tJITPER (MAX) ps

Absolute CK high-

level width

tCH

(ABS) MIN = tCK (AVG) MIN × tCH (AVG) MIN + tJITDTY (MIN)

MAX = tCK (AVG) MAX × tCH (AVG) MAX + tJITDTY (MAX) ps

Absolute CK low-

level width

tCL

(ABS) MIN = tCK (AVG) MIN × tCL (AVG) MIN + tJITDTY (MIN)

MAX = tCK (AVG) MAX × tCL (AVG) MAX + tJITDTY (MAX) ps

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1Gb: x4, x8, x16 DDR2 SDRAM

AC Timing Operating Specifications

Clock Jitter

Period jitter tJITPER –90 90 –100 100 –100 100 –125 125 –125 125 –125 125 –125 125 ps 12

Half period tJITDTY –75 75 –100 100 –100 100 –125 125 –125 125 –125 125 –150 150 ps 13

Cycle to cycl e tJITCC 180 200 200 250 250 250 250 ps 14

Cumulative error,

2 cycles

tERR2PER –132 132 –150 150 –150 150 –175 175 –175 175 –175 175 –175 175 ps 15

Cumulative error,

3 cycles

tERR3PER –157 157 –175 175 –175 175 –225 225 –225 225 –225 225 –225 225 ps 15

Cumulative error,

4 cycles

tERR4PER –175 175 –200 200 –200 200 –250 250 –250 250 –250 250 –250 250 ps 15

Cumulative error,

5 cycles

tERR5PER –188 188 –200 200 –200 200 –250 250 –250 250 –250 250 –250 250 ps 15, 16

Cumulative error,

6–10 cycles

tERR6–

10PER

–250 250 –300 300 –300 300 –350 350 –350 350 –350 350 –350 350 ps 15, 16

Cumulative error,

11–50 cycles

tERR11–

50PER

–425 425 –450 450 –450 450 –450 450 –450 450 –450 450 –450 450 ps 15

Table 13: AC Operating Conditions for -187E, -25E, -3E, -3, -37E, and -5E Speeds (Sheet 2 of 7)

Not all speed grades listed may be supported for this device; refer to the title page for speeds supporte d;

Notes: 1–5 (page 39) apply to the entir e table; VDDQ = +1.8V ±0.1V, VDD = +1.8V ±0.1V

AC Characteristics -187E -25E -25 -3E -3 -37E -5E

Units NotesParameter Symbol Min Max Min Max Min Max Min Max Min Max Min Max Min Max

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1Gb: x4, x8, x16 DDR2 SDRAM

AC Timing Operating Specifications

Data Strobe-Out

DQS output access

time from CK/CK#

tDQSCK –300 +300 –350 +350 –350 +350 –400 +400 –400 +400 –450 +450 –500 +500 ps 19

DQS read

preamble

tRPRE MIN = 0.9 × tCK

MAX = 1.1 × tCK

tCK 17,

18, 19

DQS read

postamble

tRPST MIN = 0.4 × tCK

MAX = 0.6 × tCK

tCK 17,

18,

19, 20

CK/CK# to DQS

Low-Z

tLZ1MIN = tAC (MIN)

MAX = tAC (MAX) ps 19,

21, 22

Data Strobe-In

DQS rising edge to

CK rising edg e

tDQSS MIN = –0.25 × tCK

MAX = +0.25 × tCK

tCK 18

DQS input-high

pulse width

tDQSH MIN = 0.35 × tCK

MAX = n/a

tCK 18

DQS input-low

pulse width

tDQSL MIN = 0.35 × tCK

MAX = n/a

tCK 18

DQS falling to CK

rising: setup time

tDSS MIN = 0.2 × tCK

MAX = n/a

tCK 18

DQS falling from

CK rising: hol d

time

tDSH MIN = 0.2 × tCK

MAX = n/a

tCK 18

Write preamble

setup time

tWPRES MIN = 0

MAX = n/a ps 23, 24

DQS write

preamble

tWPRE MIN = 0.35 × tCK

MAX = n/a

tCK 18

DQS write

postamble

tWPST MIN = 0.4 × tCK

MAX = 0.6 × tCK

tCK 18, 25

WRITE command

to first DQS

transition

– MIN = WL - tDQSS

MAX = WL + tDQSS

tCK

Table 13: AC Operating Conditions for -187E, -25E, -3E, -3, -37E, and -5E Speeds (Sheet 3 of 7)

Not all speed grades listed may be supported for this device; refer to the title page for speeds supporte d;

Notes: 1–5 (page 39) apply to the entir e table; VDDQ = +1.8V ±0.1V, VDD = +1.8V ±0.1V

AC Characteristics -187E -25E -25 -3E -3 -37E -5E

Units NotesParameter Symbol Min Max Min Max Min Max Min Max Min Max Min Max Min Max

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1Gb: x4, x8, x16 DDR2 SDRAM

AC Timing Operating Specifications

Data-Out

DQ output access

time from CK/CK#

tAC –350 +350 –400 +400 –400 +400 –450 +450 –450 +450 –500 +500 –600 +600 ps 19

DQS–DQ skew,

DQS to last DQ

valid, per group,

per access

tDQSQ – 175 – 200 – 200 – 240 – 240 – 300 – 350 ps 26, 27

DQ hold from next

DQS strobe

tQHS – 250 – 300 – 300 – 340 – 340 – 400 – 450 ps 28

DQ–DQS hold, DQS

to first DQ not

valid

tQH MIN = tHP - tQHS

MAX = n/a ps 26,

27, 28

CK/CK# to DQ, DQS

High-Z

tHZ MIN = n/a

MAX = tAC (MAX) ps 19,

21, 29

CK/CK# to DQ

Low-Z

tLZ2MIN = 2 × tAC (MIN)

MAX = tAC (MAX) ps 19,

21, 22

Data valid output

window DVW MIN = tQH - tDQSQ

MAX = n/a ns 26, 27

Data-In

DQ and DM input

setup time to DQS

tDSb0 – 50 – 50 – 100 – 100 – 100 – 150 – ps 26,

30, 31

DQ and DM input

hold time to DQS

tDHb75 – 125 – 125 – 175 – 175 – 225 – 275 – ps 26,

30, 31

DQ and DM input

setup time to DQS

tDSa200 – 250 – 250 – 300 – 300 – 350 – 400 – ps 26,

30, 31

DQ and DM input

hold time to DQS

tDHa200 – 250 – 250 – 300 – 300 – 350 – 400 – ps 26,

30, 31

DQ and DM input

pulse width

tDIPW MIN = 0.35 × tCK

MAX = n/a

tCK 18, 32

Table 13: AC Operating Conditions for -187E, -25E, -3E, -3, -37E, and -5E Speeds (Sheet 4 of 7)

Not all speed grades listed may be supported for this device; refer to the title page for speeds supporte d;

Notes: 1–5 (page 39) apply to the entir e table; VDDQ = +1.8V ±0.1V, VDD = +1.8V ±0.1V

AC Characteristics -187E -25E -25 -3E -3 -37E -5E

Units NotesParameter Symbol Min Max Min Max Min Max Min Max Min Max Min Max Min Max

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1Gb: x4, x8, x16 DDR2 SDRAM

AC Timing Operating Specifications

Command and Address

Input setup time tISb125 – 175 – 175 – 200 – 200 – 250 – 350 – ps 31, 33

Input hold time tIHb200 – 250 – 250 – 275 – 275 – 375 – 475 – ps 31, 33

Input setup time tISa325 – 375 – 375 – 400 – 400 – 500 – 600 – ps 31, 33

Input hold time tIHa325 – 375 – 375 – 400 – 400 – 500 – 600 – ps 31, 33

Input pulse width tIPW 0.6 – 0.6 – 0.6 – 0.6 – 0.6 – 0.6 – 0.6 – tCK 18, 32

ACTIVATE-to-

ACTIVATE delay,

same bank

tRC 54 – 55 – 55 – 54 – 55 – 55 – 55 – ns 18, 34

ACTIVATE-to-READ

or WRITE delay

tRCD 13.125 – 12.5 – 15 – 12 – 15 – 15 – 15 – ns 18

ACTIVATE-to-

PRECHARGE delay

tRAS 40 70K 45 70K 45 70K 40 70K 40 70K 40 70K 40 70K ns 18,

34, 35

PRECHARGE period tRP 13.125 – 12.5 – 15 – 12 – 15 – 15 – 15 – ns 18, 36

PRECHARGE

ALL period <1Gb tRPA 13.125 – 12.5 – 15 – 12 – 15 – 15 – 15 – ns 18, 36

>1Gb tRPA 15 – 15 – 17.5 15 18 18.75 20 ns 18, 36

ACTIVATE-

to-

ACTIVATE

delay

different

bank

x4, x8 tRRD 7.5 – 7.5 – 7.5 – 7.5 – 7.5 – 7.5 – 7 .5 – ns 18, 37

x16 tRRD10 – 10–10–10–10–10–10–ns18, 37

4-bank

activate

period

x4, x8 tF AW 35 – 35 – 35 – 37.5 – 37.5 – 37.5 – 37.5 – ns 18, 38

x16 tFAW45 – 45–45–50–50–50–50–ns18, 38

Internal READ-to-

PRECHARGE delay

tRTP 7.5 – 7.5 – 7.5 – 7.5 – 7.5 – 7.5 – 7.5 – ns 18,

37, 39

CAS#-to-CAS#

delay

tCCD2 – 2–2–2–2–2–2–

tCK 18

Write recovery

time

tWR 15 – 15 – 15 – 15 – 15 – 15 – 15 – ns 18, 37

Writ e AP re covery

+ precharge time

tDAL tWR +

tRP –tWR +

tRP –ns40

Internal WRITE-to-

READ delay

tWTR 7.5 – 7.5 – 7.5 – 7.5 – 7.5 – 7.5 – 10 – ns 18, 37

LOAD MODE cycle

time

tMRD2 – 2–2–2–2–2–2–

tCK 18

Table 13: AC Operating Conditions for -187E, -25E, -3E, -3, -37E, and -5E Speeds (Sheet 5 of 7)

Not all speed grades listed may be supported for this device; refer to the title page for speeds supporte d;

Notes: 1–5 (page 39) apply to the entir e table; VDDQ = +1.8V ±0.1V, VDD = +1.8V ±0.1V

AC Characteristics -187E -25E -25 -3E -3 -37E -5E

Units NotesParameter Symbol Min Max Min Max Min Max Min Max Min Max Min Max Min Max

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1Gb: x4, x8, x16 DDR2 SDRAM

AC Timing Operating Specifications

Refresh

REFRESH-

to-

ACTIVATE

or to-

REFRESH

interval

256Mb tRFC 75 70K 75 70K 75 70K 75 70K 75 70K 75 70K 75 70K ns 18, 41

512Mb 105 70K 105 70K 105 70K 105 70K 105 70K 105 70K 105 70K

1Gb 127.5 70K 127.5 70K 127.5 70K 127.5 70K 127.5 70K 127.5 70K 127.5 70K

2Gb 197.5 70K 197.5 70K 197.5 70K 197.5 70K 197.5 70K 197.5 70K 197.5 70K

Average periodic

refresh

(commercial)

tREFI – 7.8 – 7.8 – 7.8 – 7.8 – 7.8 – 7.8 – 7.8 µs 18, 41

Average periodic

refresh (industrial)

tREFIIT – 3.9 – 3.9 – 3.9 – 3.9 – 3.9 – 3.9 – 3.9 µs 18, 41

Average periodic

refresh

(automotive)

tREFIAT – 3.9 – 3.9 – 3.9 – 3.9 – 3.9 – 3.9 – 3.9 µs 18, 41

CKE LOW to CK,

CK# uncertainty

tDELAY MIN limit = tIS + tCK + tIH

MAX limit = n/a ns 42

Self Refresh

Exit SELF REFRESH

to nonREAD

command

tXSNR MIN limit = tRFC (MIN) + 10

MAX limit = n/a ns

Exit SELF REFRESH

to READ command

tXSRD MIN limit = 200

MAX limit = n/a

tCK 18

Exit SELF REFRESH

timing reference

tISXR MIN limit = tIS

MAX limit = n/a ps 33, 43

Power-Down

Exit active

power-

down to

READ

command

MR12

= 0

tXARD3 – 2–2–2–2–2–2–

tCK 18

MR12

= 1 10 -

AL – 8 - AL–8 - AL–7 - AL–7 - AL–6 - AL–6 - AL– tCK 18

Exit precharge

power-down to

any nonREAD

command

tXP 3 – 2–2–2–2–2–2–

tCK 18

CKE MIN HIGH/

LOW time

tCKE MIN = 3

MAX = n/a

tCK 18, 44

Table 13: AC Operating Conditions for -187E, -25E, -3E, -3, -37E, and -5E Speeds (Sheet 6 of 7)

Not all speed grades listed may be supported for this device; refer to the title page for speeds supporte d;

Notes: 1–5 (page 39) apply to the entir e table; VDDQ = +1.8V ±0.1V, VDD = +1.8V ±0.1V

AC Characteristics -187E -25E -25 -3E -3 -37E -5E

Units NotesParameter Symbol Min Max Min Max Min Max Min Max Min Max Min Max Min Max

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1Gb: x4, x8, x16 DDR2 SDRAM

AC Timing Operating Specifications

ODT

ODT to power-

down entry latency

tANPD4 – 3–3–3–3–3–3–

tCK 18

ODT power-down

exit latency

tAXPD11–10–10–8–8–8–8–

tCK 18

ODT turn-on delay tAOND 2 tCK 18

ODT turn-off delay tAOFD 2.5 tCK 18, 45

ODT turn-on tAON tAC

(MIN)

tAC

(MAX)

+ 2,575

MIN = tAC (MIN)

MAX = tAC (MAX) + 600 MIN = tAC (MIN)

MAX = tAC (MAX) + 700 MIN = tAC (MIN)

MAX = tAC (MAX) + 1,000 ps 19, 46

ODT turn-off tAOF MIN = tAC (MIN)

MAX = tAC (MAX) + 600 ps 47, 48

ODT turn-on

(power-down

mode)

tAONPD tAC

(MIN)

+ 2,000

2 ×

tCK +

tAC

(MAX)

1,000

MIN = tAC (MIN) + 2,000

MAX = 2 × tCK + tAC (MAX) + 1,000 ps 49

ODT turn-off

(power-down

mode)

tAOFPD MIN = tAC (MIN) + 2,000

MAX = 2.5 × tCK + tAC (MAX) + 1,000 ps

ODT enable from

MRS command

tMOD MIN = 12

MAX = n/a ns 18, 50

Table 13: AC Operating Conditions for -187E, -25E, -3E, -3, -37E, and -5E Speeds (Sheet 7 of 7)

Not all speed grades listed may be supported for this device; refer to the title page for speeds supporte d;

Notes: 1–5 (page 39) apply to the entir e table; VDDQ = +1.8V ±0.1V, VDD = +1.8V ±0.1V

AC Characteristics -187E -25E -25 -3E -3 -37E -5E

Units NotesParameter Symbol Min Max Min Max Min Max Min Max Min Max Min Max Min Max

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1Gb: x4, x8, x16 DDR2 SDRAM

AC Timing Operating Specifications

Notes 1. All voltages are referenced to VSS.

2. Tests for AC timing, IDD, and electrical AC and DC characteristics may be conducted

at nominal reference/supply voltage levels, but the related specifications and the

operation of the device are warranted for the full voltage range specified. ODT is dis-

abled for all measurements that are not ODT-specific.

3. Outputs measured with equivalent load (see Figure 17 on page 47).

4. AC timing and IDD tests may use a VIL-to-VIH swing of up to 1.0V in the test environ-

ment, and parameter specifications are guaranteed for the specified AC input levels

under normal use conditions. The slew rate for the input signals used to test the

device is 1.0 V/ns for signals in the range between VIL(AC) and VIH(AC). Slew rates

other than 1.0 V/ns may requir e the timing parameters to be derated as specified.

5. The A C and DC input leve l specifications are as defined in the SSTL_18 standard (that

is, the receiver will effectively switch as a result of the signal crossing the AC input

level and will remain in that state as long as the signal does not ring back above

[below] the DC input LOW [HIGH] level).

6. CK and CK# input slew rate is referenced at 1 V/ns (2 V/ns if measured differentially).

7. Operating fr equency is only allo wed to change duri ng self r efresh mode (see Fig ur e 81

on page 117), precharge power-down mode, or system reset condition (see “RESET”

on page 118). SSC allows for small deviations in operating frequency, provided the

SSC guidelines are satisfied.

8. The clock’s tCK (AVG) is the average clock over any 200 consecutive clocks and

tCK (AVG) MIN is the smallest clock rate allowed (except for a deviation due to

allowed clock jitter). Input clock jitter is allowed provided it does not exceed values

specified. Also, the jitter must be of a random Gaussian distribution in nature.

9. Spread spectrum is not included in the jitter specification values. However, the input

clock can accommodate spread spectrum at a sweep rate i n the ra nge 20–60 KHz with

an additional one percent tCK (AVG); however, the spread spectrum may not use a

clock rate below tCK (AVG) MIN or above tCK (AVG) MAX.

10. MIN (tCL, tCH) r efers to the smaller of the actual clock LOW time and the act ual cl ock

HIGH time driven to the device. The clock’s half period must also be of a Gaussian

distribution; tCH (AVG) and tCL (AVG) must be met with or without clock jitter and

with or without duty cycle jitter. tCH (AVG) and tCL (AVG) are the average of any 200

consecutive CK falling edges.

11. tHP (MIN) is the lesser of tCL and tCH actually applied to the device CK and CK#

inputs; thus, tHP (MIN) ≥ the lesser of tCL (ABS) MIN and tCH (ABS) MIN.

12. The period jitter (tJITPER) is the maximum deviation in the cl ock period from the av er-

age or nominal clock allowed in either the positive or negative direction. JEDEC spec-

ifies tighter jitter numbers during DLL locking time. During DLL lock time, the jitter

values should be 20 percent less those than noted in the table (DLL locked).

13. The half-period jitter (tJITDTY) applies to eithe r the high pulse of clock or the low

pulse of clock; however, the two cumulatively can not exceed tJITPER.

14. The cycle-to -cycle jitter (tJITCC) is the amount the clock period can deviate from one

cycle to the next. JEDEC specifie s tighter jitter numbers during DLL locking time.

During DLL lock time, the jitter values should be 20 percent less than those noted in

the table (DLL locked).

15. The cumulative jitter error (tERRnPER), where n is 2, 3, 4, 5, 6–10, or 11–50 is the

amount of clock time allowe d to consecutively accumulate away from the average

clock over any number of clock cycles.

16. JEDEC specifies using tERR6–10PER when derating clock-re lated output timing (see

notes 19 and 48). Micron requires less derating by allowing tERR5PER to be used.

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1Gb: x4, x8, x16 DDR2 SDRAM

AC Timing Operating Specifications

17. This parameter is not referenced to a specific voltage level but is specified when the

device output is no longer driving (tRPST) or beginning to drive (tRPRE).

18. The inputs to the DRAM must be aligned to the associated clock, that is, the actual

clock that latches it in. How ever, the input tim i ng (in ns) references to the tCK (AVG)

when determining the r equir ed number of clocks . The follo wing input par ameters ar e

determined by taking the specified percentage times the tCK (AVG) rather than tCK:

tIPW, tDIPW, tDQSS, tDQSH, tDQSL, tDSS, tDSH, tWPST, and tWPRE.

19. The DRAM output timing is aligned to the nominal or average clock. Most output

parameters must be derated by the actual jitter error when input clock jitter is

present; this will result in each parameter becoming larger. The following parameters

are required to be derated by subtracting tERR5PER (MAX): tAC (MIN), tDQSCK (MIN),

tLZDQS (MIN), tLZDQ (MIN), tA ON (MIN); while the following parameters ar e r e quir e d

to be derated by subtracting tERR5PER (MIN): tAC (MAX), tDQSCK (MAX), tHZ (MAX),

tLZDQS (MAX), tLZDQ (MAX), tAON (MAX). The parameter tRPRE (MIN) is derated by

subtracting tJITPER (MAX), while tRPRE (MAX), is derated by su btracting

tJITPER (MIN). The parameter tRPST (MIN) is derated by subtracting tJITDTY (MAX),

while tRPST (MAX), is derated by subtracting tJITDTY (MIN). Output timings that

require tERR5PER derating can be observed to have offsets relative to the clock; how-

ever, the total window will not degrade.

20. When DQS is used single-ended, the minimum limit is reduced by 100p s.

21. tHZ and tLZ transitions occur in the same access time windows as valid data transi-

tions. These parameters are not referenced to a specific voltage level, but specify

when the device output is no longer driving (tHZ) or begins driving (tLZ).

22. tLZ (MIN) will prevail over a tDQSCK (MIN) + tRPRE (MAX) conditio n.

23. This is not a device limit. The device will operate with a negative value, but system

performance could be degraded due to bus turnaround.

24. It is r ecommended that DQS be valid (HIGH or LOW) on or befor e the WRITE com-

mand. The case shown (DQS going from High-Z to logic LOW) applies when no

WRITEs were previously in progress on the bus. If a previous WRITE was in progress,

DQS could be HIGH during this time, depending on tDQSS.

25. The intent of the “Don’t Care” state after completion of the postamble is that the

DQS-driven signal should either be HIGH, LOW, or High-Z, and that any signal transi-

tion within the input switching region must follow valid input requirements. That is,

if DQS transitions HIGH (above VIH[DC] MIN), then it must not tr ansition LOW (below

VIH[DC]) prior to tDQSH (MIN).

26. R efer enced to e ach output group: x4 = DQS with DQ0–DQ3; x8 = DQS with DQ0–DQ7;

x16 = LDQS with DQ0–DQ7; and UDQS with DQ8–DQ15.

27. The data valid window is derived b y achieving other specifications: tHP (tCK/2),

tDQSQ, and tQH (tQH = tHP - tQHS). The data valid window derates in direct propor-

tion to the clock duty cycle and a practical data valid window can be derived.

28. tQH = tHP - tQHS; the worst case tQH would be the lesser of tCL(ABS) MAX or

tCH (ABS) MAX times tCK (ABS) MIN - tQHS. Minimizing the amount of tCH (AVG)

offset and value of tJITDTY will provide a larger tQH, which in turn will provide a larger

valid data out window.

29. This maximum value is derived fr om the referenced test load. tHZ (MAX) will prevail

over tDQSCK (MAX) + tRPST (MAX) condition.

30. The values listed are for the differe ntial DQS strobe (DQS and DQS#) with a differ en-

tial slew r ate of 2 V/ns (1 V/ns for each signal). Ther e ar e two sets of values listed: tDSa,

tDHa and tDSb, tDHb. The tDSa, tDHa values (for reference only) are equivalent to the

baseline values of tDSb, tDHb at VREF when the slew rate is 2 V/ns, differentially. The

baseline values, tDSb, tDHb, are the JEDEC-defined values, referenced from the logic

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1Gb: x4, x8, x16 DDR2 SDRAM

AC Timing Operating Specifications

trip points. tDSb is ref ere nced from VIH(AC) for a rising signal and VIL(AC) for a falling

signal, while tDHb is referenced from VIL(DC) for a rising signal and VIH(DC) for a fall-

ing signal. If the diffe rential DQS slew rate is not equal to 2 V/ ns, then the bas e li ne

values must be derated by adding the values from Tables 32 and 33 on pages 59–60. If

the DQS differential strobe featur e is not enabled, then the DQS strobe is single-

ended and the baseline values must be derated using Table 34 on page 61. Single-

ended DQS data timing is referenced at DQS crossing VREF. The correct timing values

for a single-ended DQS strobe are listed in Tables 35–37 on pages 61–62; list ed values

are already derated for slew rate variations and converted from baseline values to

VREF values.

31. VIL/VIH DDR2 overshoot/undershoot. See “AC Overshoot/Undershoot Specification”

on page 53.

32. For each input signal—not the group collectively.

33. There are two sets of values listed for command/address: tISa, tIHa and tISb, tIHb. The

tISa, tIHa values (for reference only) are equivalent to the baseline values of tISb, tIHb

at VREF when the slew rate is 1 V/ns. The baseline values, tISb, tIHb, are the JEDEC-

defined values, referenced from the logic trip points. tISb is referenced from VIH(AC)

for a rising signal and VIL(AC) for a falling signal, while tIHb is referenced from VIL(DC)

for a rising signal and VIH(DC) for a falling signal. If the command/address slew rate is

not equal to 1 V/ns, then the baseline values must be derated by adding the values

from Tables 30 and 31 on page 56.

34. This is applicable to READ cycles only. WRITE cycles gene rally require additional

time due to tWR during auto precharge.

35. READs and WRITEs with auto precharge are allo wed to be issued before tRAS (MIN) is

satisfied because tRAS lockout feature is supported in DDR2 SDRAM.

36. When a single-bank PRECHAR GE command is issued, tRP timing applies . tRPA timing

applies when the PRECHARGE (ALL) command is iss ued, r e gar dle ss of the number of

banks open. For 8-bank devices (≥1Gb), tRPA (MIN) = tRP (MIN)+ tCK (AVG)

(Table13 on page 32 lists tRP [MIN] + tCK [AVG] MIN).

37. This parameter has a two clock minimum requirement at any tCK.

38. The tFAW (MIN) parameter applies to all 8-bank DDR2 devices. No more than four

bank-ACTIVATE commands may be issued in a given tFAW (MIN) period. tRRD (MIN)

restriction still applies.

39. The minimum internal READ-to-PRECHARGE time. This is the time from which the

last 4-bit prefetch begins to when the PRECHARGE command can be issued. A 4-bit

pref etch is when the READ command internally latches the READ so that data will

output CL later. This parameter is only applicable when tRTP/(2 × tCK) > 1, such as

frequencies faster than 533 MHz when tRTP = 7.5ns . If tRTP/(2 × tCK) ≤ 1, then equa-

tion AL + BL/2 applies. tRAS (MIN) has to be satisfied as well. The DDR2 SDRAM will

automatically delay the internal PRECHARGE command until tRAS (MIN) has been

satisfied.

40. tDAL = (nWR) + (tRP/tCK). Each of these terms, if not already an integer, should be

rounded up to the next integer. tCK refers to the application clock period; nWR refers

to the tWR parameter stored in the MR9–MR11 For example , -37E at tCK = 3.75ns with

tWR programmed to four clocks would have tDAL = 4 + (15ns/3.75n s) clocks =

4 + (4 ) clocks = 8 clocks.

41. The refresh period is 64ms (commercial) or 32ms (industrial and automotive). This

equates to an average re fresh rate of 7.8125µs (commercial) or 3.9607µs (industrial

and automotive). To ensure all rows of all banks are properly refreshed, 8,192

REFRESH commands must be issued every 64ms (commercial) or 32ms (industrial

and automotive).

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AC and DC Operating Conditions

42. tDELAY is calculated from tIS + tCK + tIH so that CKE registration LOW is guaranteed

prior to CK, CK# being removed in a system RESET condition (see “RESET” on page

118).

43. tISXR is equal to tIS and is used for CKE setup time during self refresh exit, as shown in

Figure 71 on page 109.

44. tCKE (MIN) of three clocks means CKE must be registered on thre e co nsecutive posi-

tive clock edges. CKE must re main at the valid input level the entire time it takes to

achieve the three clocks of registration. Thus, after any CKE transition, CKE may not

transition from its valid level during the time period of tIS + 2 × tCK + tIH.

45. The half-clock of tAOFD’s 2.5 tCK assume s a 50/50 clock duty cycle. This half-clock

value must be derated by the amount of half-clock duty cycle error. For example, if

the clock duty cycl e w as 47/53, tAOFD would actually be 2.5 - 0.03, or 2.47, for

tAOF (MIN) and 2.5 + 0.03, or 2.53, for tAOF (MAX).

46. ODT turn-on time tAON (MIN) is when the device leaves High-Z and ODT resistance

begins to turn on. ODT turn-on time tAON (MAX) is when the ODT resistance is fully

on. Both are measured from tAOND.

47. ODT turn-off time tAOF (MIN) is when the device starts to turn off ODT resistance.

ODT turn off time tAOF (MAX) is when the bus is in High-Z. Both are measured from

tAOFD.

48. Half-clock output parameters must be de rated by the actual tERR5PER and tJITDTY

when input clock jitter is present; this will result in each parameter becoming larger.

The parameter tAOF (MIN) is required to be derated by subtract ing both

tERR5PER (MAX) and tJITDTY (MAX). The parameter tAOF (MAX) is requi red to be der-

ated by subtracting both tERR5PER (MIN) and tJITDTY (MIN).

49. The -187E maximum limit is 2 × tCK + tAC (MAX) + 1,000 but it will likely be

3xtCK + tAC (MAX) + 1,000 in the future.

50. Should use 8 tCK for backward compatibility.

AC and DC Operating Conditions

Notes: 1. VDD and VDDQ must track each other. VDDQ must be ≤ VDD.

2. VSSQ = VSSL = VSS.

3. VDDQ tracks with VDD; VDDL tracks with VDD.

4. VREF is expected to equal VDDQ/2 of the trans mitting device and to track variations in the

DC level of the same. Peak-to-peak noise (no ncommon mode) on VREF may not exceed ±1

percent of the DC value. Peak-to-peak AC noise on VREF may not exceed ±2 percent of

VREF(DC). This measurement is to be taken at the nearest VREF bypass capacitor.

5. VTT is not applied directly to the device. VTT is a system supply for signal termination resis-

tors, is expected to be set equal to VREF, and must track variations in the DC level of VREF.

Table 14: Recommended DC Operating Conditions (SSTL_18)

All voltages referen ce d to VSS

Parameter Symbol Min Nom Max Units Notes

Supply voltage VDD 1.7 1.8 1.9 V 1, 2

VDDL supply voltage VDDL 1.7 1.8 1.9 V 2, 3

I/O supply voltage VDDQ 1.7 1.8 1.9 V 2, 3

I/O reference voltage VREF(DC) 0.49 × VDDQ 0.50 × VDDQ 0.51 × VDDQV 4

I/O termination voltage (system) VTT VREF(DC) - 40 VREF(DC)VREF(DC) + 40 mV 5

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ODT DC Electrical Characteristics

Notes: 1. RTT1(EFF) and RTT2(EFF) are determined by separately applying VIH(AC) and VIL(AC) to the ball

being tested, and then measuring current, I(VIH(AC)), and I(VIL(AC)), respectively.

(EQ 1)

2. Minimum IT and AT device values are derated by six percent when the devices operate

between –40°C and 0°C (TC).

3. Measure voltage (VM) at tested ball with no load.

(EQ 2)

Input Electrical Characteristics and Operating Conditions

Notes: 1. VDDQ + 300mV allowed provided 1.9V is not exceeded.

Table 15: ODT DC Electrical Characteristics

All voltages are referenced to VSS

Parameter Symbol Min Nom Max Units Notes

RTT effective impedance value for 75Ω setting

EMR (A6, A2) = 0, 1 RTT1(EFF)607590Ω1, 2

RTT effective impedance value for 150Ω setting

EMR (A6, A2) = 1, 0 RTT2(EFF) 120 150 180 Ω1, 2

RTT effective impedance value for 50Ω setting

EMR (A6, A2) = 1, 1 RTT3(EFF)405060Ω1, 2

Deviation of VM with respec t to VDDQ/2 ΔVM –6 6 % 3

Table 16: Input DC Logic Levels

All voltages are referenced to VSS

Parameter Symbol Min Max Units

Input high (logi c 1) vol tag e VIH(DC)VREF(DC) + 125 VDDQ1mV

Input low (logic 0) voltage VIL(DC) –300 VREF(DC) - 125 mV

Table 17: Input AC Logic Levels

All voltages referen ce d to VSS

Parameter Symbol Min Max Units

Input high (logic 1) vol tage (-37E/-5E) VIH(AC)VREF(DC) + 250 VDDQ1mV

Input high (logic 1) voltage (-187E/-25E/-25/-3E/-3) VIH(AC)VREF(DC) + 200 VDDQ1mV

Input low (logic 0) voltage (-37E/-5E) VIL(AC)–300VREF(DC) - 250 mV

Input low (logic 0) voltage (-187E/-25E/-25 /-3E /-3) VIL(AC)–300VREF(DC) - 200 mV

RTT EFF() VIH AC()VIL AC()–

IH AC()()IVIL AC()()–

-------------------------------------------------------------

ΔVM 2VM×

VDDQ

------------------1–

⎝⎠

⎛⎞

100×=

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Input Electrical Characteristics and Operating Conditions

Figure 14: Single-Ended Input Signal Levels

Notes: 1. Numbers in diagram reflect nominal DDR2-400/DDR2-533 value s.

650mV

775mV

864mV

882mV

900mV

918mV

936mV

1,025mV

1,150mV

IL(AC)

IL(DC)

REF

- AC noise

REF

- DC error

REF

+ DC error

REF

+ AC noise

IH(DC)

IH(AC)

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Input Electrical Characteristics and Operating Conditions

Notes: 1. VIN(DC) specifies the allowable DC execution of each input of differential pair such as CK,

CK#, DQS, DQS#, LDQS, LDQS#, UDQS, UDQS#, and RDQS, RDQS#.

2. VID(DC) specifies the inpu t differ ential volt ag e | VTR - VCP| required for switching, where VTR

is the true input (such as CK, DQS, LDQS, UDQS) level and VCP is the complementary input

(such as CK#, DQS#, LDQS#, UDQS#) level. The minimum value is equal to VIH(DC) - VIL(DC).

Differential input signal levels are shown in Figure 15.

3. VID(AC) specifies the inpu t differ ential volt ag e | V TR - VCP| required for switching, wher e VTR

is the true input (such as CK, DQ S, LDQ S, UDQS, RDQS) level and VCP is the complementary

input (such as CK#, DQS#, LDQS#, UDQS#, RDQS#) level. The minimum value is equal to

VIH(AC) - VIL(AC), as shown in Table 17 on page 43.

4. The typical value of VIX(AC) is expected to be about 0.5 × VDDQ of the transmitting device

and VIX(AC) is expected to track variations in VDDQ. VIX(AC) indicates the voltage at which

differential input signals must cross, as shown in Figure 15.

5. VMP(DC) specifies the input differential common mode voltage (VTR + VCP)/2 where VTR is

the true input (CK, DQS) level and VCP is the complementary input (CK#, DQS#). VMP(DC) is

expected to be approximately 0.5 × VDDQ.

6. VDDQ + 300mV allowed provided 1.9V is not exceeded.

Figure 15: Differential Input Signal Levels

Notes: 1. TR and CP may not be more positive than VDDQ + 0.3V or more negative than VSS - 0.3V.

2. TR represents the CK, DQS, RDQS, LDQS, and UDQS signals; CP represents CK#, DQS#,

RDQS#, LDQS#, and UDQS# signals.

3. This provides a minimum of 850mV to a maximum of 950mV and is expected to be VDDQ/2.

4. TR and CP must cross in this region.

5. TR and CP must meet at least VID(DC) MIN when static and is centered around VMP(DC).

6. TR and CP must have a minimum 500mV peak-to-peak swing.

7. Numbers in diagram reflect nominal values (VDDQ = 1.8V).

Table 18: Differential Input Logic Levels

All voltages referen ce d to VSS

Parameter Symbol Min Max Units Notes

DC input signal voltage VIN(DC)–300 VDDQmV1, 6

DC differential input voltage VID(DC) 250 VDDQmV2, 6

AC differential input voltage VID(AC) 500 VDDQmV3, 6

AC differential cross-point voltage VIX(AC) 0.50 × VDDQ - 175 0.50 × VDDQ + 175 mV 4

Input midpoint voltage VMP(DC) 850 950 mV 5

TR2

CP2

2.1V

VDDQ = 1.8V

VIN(DC) MAX1

VIN(DC) MIN1

–0.30V

0.9V

1.075V

0.725V VID(AC)6

VID(DC)5

VMP(DC)3VIX(AC)4

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Output Electrical Characteristics and Operating Conditions

Notes: 1. The typical value of VOX(AC) is expected to be about 0.5 × VDDQ of the transmitting device

and VOX(AC) is expected to track variations in VDDQ. VOX(AC) indicates the voltage at which

differential output signals must cross.

Figure 16: Differential Output Signal Levels

Notes: 1. For IOH(DC); VDDQ = 1.7V, VOUT = 1,420mV. (VOUT - VDDQ)/IOH must be less than 21Ω for val-

ues of VOUT between VDDQ and VDDQ - 280mV.

2. For IOL(DC); VDDQ = 1.7V, VOUT = 280mV. VOUT/IOL must be less than 21Ω for values of VOUT

between 0V and 280mV.

3. The DC value of VREF applied to the receiving device is set to VTT.

4. The values of IOH(DC) and IOL(DC) are based on th e conditions given in Notes 1 and 2. They

are used to test device drive current capability to ensure VIH (MIN) plus a noise margin and

VIL (MAX) minus a noise margin are delivered to an SSTL_18 receiver. The actual current val-

ues are derived by shifting the desired driver operating point (see output IV curves) along a

21Ω load line to define a convenient driver current for measurement.

Table 19: Differential AC Output Parameters

Parameter Symbol Min Max Units Notes

AC differential cross-point voltage VOX(AC) 0.50 × VDDQ - 125 0.50 × VDDQ + 125 mV 1

AC differential voltage swing VSWING 1.0 mV

Table 20: Output DC Current Drive

Parameter Symbol Value Units Notes

Output MIN source DC current IOH –13.4 mA 1, 2, 4

Output MIN sink DC current IOL 13.4 mA 2, 3, 4

Crossing point

VOX

VSSQ

VSWING

VDDQ

VTR

VCP

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Output Electrical Characteristics and Operating Conditions

Notes: 1. Absolute specifications: 0°C ≤ TC ≤ +85°C; VDDQ = +1.8V ±0.1V, VDD = +1.8V ±0.1V.

2. Impedance measurement conditions for output source DC current: VDDQ = 1.7V;

VOUT = 1,420mV; (VOUT - VDDQ)/IOH must be less than 23.4Ω for values of VOUT between

VDDQ and VDDQ - 280mV. The impedance measurement condition for output sink DC cur-

rent: VDDQ = 1.7V; VOUT = 280mV; VOUT/IOL must be less than 23.4Ω for values of VOUT

between 0V and 280mV.

3. Mismatch is an absolute va lue between pull-up and pull-dow n; bo th are measured at the

same temperature and voltage.

4. Output slew rate for falling and rising edges is measured between VTT - 250mV and

VTT + 250mV for single-ended signals. For dif ferential signals (DQS, DQS#), output slew rate

is measured between DQS - DQS# = –500mV and DQS# - DQS = + 500mV. Output slew rate is

guaranteed by design but is not necessarily tested on each device.

5. The absolute value of the slew rate as measured from VIL(DC) MAX to V IH(DC) MIN is equal to

or greater than the slew rate as measured from VIL(AC) MAX to VIH(AC) MIN. This is guaran-

teed by design and characterization.

6. IT and AT devices requir e an addi ti onal 0.4 V/ ns in th e MAX lim it wh en TC is between –40°C

and 0°C.

Figure 17: Output Slew Rate Load

Table 21: Output Characteristics

Parameter Min Nom Max Units Notes

Output impedance See “Output Driv er Cha r acteristic s” on

page 48 Ω1, 2

Pull-up and pull -down mismatch 04Ω1, 2, 3

Output slew rate 1.5 5 V/ns 1, 4, 5, 6

Output

(VOUT) Reference

point

25Ω

VTT = VDDQ/2

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Output Driver Characteristics

Figure 18: Full Strength Pull-Down Characteristics

Table 22: Full Strength Pull-Down Current (mA)

Voltage (V) Min Nom Max

0.0 0.00 0.00 0.00

0.1 4.30 5.63 7.95

0.2 8.60 11.30 15.90

0.3 12.90 16.52 23.85

0.4 16.90 22.19 31.80

0.5 20.40 27.59 39.75

0.6 23.28 32.39 47.70

0.7 25.44 36.45 55.55

0.8 26.79 40.38 62.95

0.9 27.67 44.01 69.55

1.0 28.38 47.01 75.35

1.1 28.96 49.63 80.35

1.2 29.46 51.71 84.55

1.3 29.90 53.32 87.95

1.4 30.29 54.9 90.70

1.5 30.65 56.03 93.00

1.6 30.98 57.07 95.05

1.7 31.31 58.16 97.05

1.8 31.64 59.27 99.05

1.9 31.96 60.35 101.05

VOUT (V)

0.0 0.5 1.0 1.5

120

100

IOUT (MA)

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Output Driver Characteristics

Figure 19: Full Strength Pull-Up Characteristi cs

Table 23: Full Strength Pull-Up Current (mA)

Voltage (V) Min Nom Max

0.0 0.00 0.00 0.00

0.1 –4.30 –5.63 –7.95

0.2 –8.60 –11.30 –15.90

0.3 –12.90 –16.52 –23.85

0.4 –16.90 –22.19 –31.80

0.5 –20.40 –27.59 –39.75

0.6 –23.28 –32.39 –47.70

0.7 –25.44 –36.45 –55.55

0.8 –26.79 –40.38 –62.95

0.9 –27.67 –44.01 –69.55

1.0 –28.38 –47.01 –75.35

1.1 –28.96 –49.63 –80.35

1.2 –29.46 –51.71 –84.55

1.3 –29.90 –53.32 –87.95

1.4 –30.29 –54.90 –90.70

1.5 –30.65 –56.03 –93.00

1.6 –30.98 –57.07 –95.05

1.7 –31.31 –58.16 –97.05

1.8 –31.64 –59.27 –99.05

1.9 –31.96 –60.35 –101.05

VDDQ - VOUT (V)

–20

–40

–60

–80

–100

–120 0 0.5 1.0 1.5

IOUT (mA)

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Output Driver Characteristics

Figure 20: Reduced Strength Pull-Down Characteristics

Table 24: Reduced Strength Pull-Down Current (mA)

Voltage (V) Min Nom Max

0.0 0.000.000.00

0.1 1.722.984.77

0.2 3.445.999.54

0.3 5.16 8.75 14.31

0.4 6.76 11.76 19.08

0.5 8.16 14.62 23.85

0.6 9.31 17.17 28.62

0.7 10.18 19.32 33.33

0.8 10.72 21.40 37.77

0.9 11.07 23.32 41.73

1.0 11.35 24.92 45.21

1.1 11.58 26.30 48.21

1.2 11.78 27.41 50.73

1.3 11.96 28.26 52.77

1.4 12.12 29.10 54.42

1.5 12.26 29.70 55.80

1.6 12.39 30.25 57.03

1.7 12.52 30.82 58.23

1.8 12.66 31.41 59.43

1.9 12.78 31.98 60.63

00.0 0.5 1.0 1.5

VOUT (V)

IOUT (mV)

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Output Driver Characteristics

Figure 21: Reduced Strength Pull-Up Characteristics

Table 25: Reduced Strength Pull-Up Current (mA)

Voltage (V) Min Nom Max

0.0 0.00 0.00 0.00

0.1 –1.72 –2.98 –4.77

0.2 –3.44 –5.99 –9.54

0.3 –5.16 –8.75 –14.31

0.4 –6.76 –11.76 –19.08

0.5 –8.16 –14.62 –23.85

0.6 –9.31 –17.17 –28.62

0.7 –10.18 –19.32 –33.33

0.8 –10.72 –21.40 –37.77

0.9 –11.07 –23.32 –41.73

1.0 –11.35 –24.92 –45.21

1.1 –11.58 –26.30 –48.21

1.2 –11.78 –27.41 –50.73

1.3 –11.96 –28.26 –52.77

1.4 –12.12 –29.10 –54.42

1.5 –12.26 –29.69 –55.8

1.6 –12.39 –30.25 –57.03

1.7 –12.52 –30.82 –58.23

1.8 –12.66 –31.42 –59.43

1.9 –12.78 –31.98 –60.63

–10

–20

–30

–40

–50

–60

–70 0.0 0.5 1.0 1.5

VDDQ - VOUT (V)

IOUT (mV)

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Power and Ground Clamp Characteristics

Power and ground clamps are provided on the following input-only balls: Address balls,

bank address balls, CS#, RAS#, CAS#, WE#, ODT, and CKE.

Figure 22: Input Clamp Characteristics

Table 26: Input Clamp Characteristics

Voltage Across Clamp

(V) Minimum Power Clamp Current

(mA) Minimum Ground Clamp Current

(mA)

0.0 0.0 0.0

0.1 0.0 0.0

0.2 0.0 0.0

0.3 0.0 0.0

0.4 0.0 0.0

0.5 0.0 0.0

0.6 0.0 0.0

0.7 0.0 0.0

0.8 0.1 0.1

0.9 1.0 1.0

1.0 2.5 2.5

1.1 4.7 4.7

1.2 6.8 6.8

1.3 9.1 9.1

1.4 11.0 11.0

1.5 13.5 13.5

1.6 16.0 16.0

1.7 18.2 18.2

1.8 21.0 21.0

Voltage Across Clamp (V)

Minimum Clamp Current (mA)

0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8

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AC Overshoot/Undershoot Specification

Some revisions will support the 0.9V maximum average amplitude instead of the 0.5V

maximum average amplitude shown in Tables 27 and 28.

Figure 23: Overshoot

Figure 24: Undershoot

Table 27: Address and Control Balls

Applies to address balls, bank address balls, CS#, RAS#, CAS#, WE#, CKE, ODT

Parameter

Specification

-187E -25/-25E -3/-3E -37E -5E

Maximum peak amplitude allowed for overshoot area (see

Figure 23) 0.50V 0.50V 0.50V 0.50V 0.50V

Maximum peak amplitude allowed for undershoot area

(see Figure 24) 0.50V 0.50V 0.50V 0.50V 0.50V

Maximum overshoot area above VDD (see Figure 23) 0.5 Vns 0.66 Vns 0.80 Vns 1.00 Vns 1.33 Vns

Maximum undershoot area below VSS (see Figure 24) 0.5 Vns 0.66 Vns 0.80 Vns 1.00 Vns 1.33 Vns

Table 28: Clock, Data, Strobe, and Mask B alls

Applies to DQ, DQS, DQS#, RDQS, RDQS#, UDQS, UDQS#, LDQS, LDQS#, DM, UDM, LDM

Parameter

Specification

-187E -25/-25E -3/-3E -37E -5E

Maximum peak amplitude allowed for overshoot area (see

Figure 23) 0.50V 0.50V 0.50V 0.50V 0.50V

Maximum peak amplitude allowed for undershoot area

(see Figure 24) 0.50V 0.50V 0.50V 0.50V 0.50V

Maximum overshoot area above VDDQ (see Figure 23) 0.19 Vns 0.23 Vns 0.23 Vns 0.28 Vns 0.38 Vns

Maximum undershoot area below VSSQ (see Figure 24) 0.19 Vns 0.23 Vns 0.23 Vns 0.28 Vns 0.38 Vns

Maximum amplitudeOvershoot area

VDD/VDDQ

VSS/VSSQ

VOLTS (V)

Time (ns)

VSS/VSSQ

Maximum amplitudeUndershoot area

Time (ns)

Volts (V)

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1Gb: x4, x8, x16 DDR2 SDRAM

AC Overshoot/Undershoot Specification

Notes: 1. All voltages referenc e d to VSS.

2. Input waveform setup timing (tISb) is referenced from th e input signal c ro s sing at the

VIH(AC) level for a rising signal and VIL(AC) for a falling signal applied to the device under

test, as shown in Figure 33 on page 65.

3. See “Input Slew Rate Derating” on page 55.

4. The slew rate for single-ended inputs is measured from DC level to AC level, VIL(DC) to

VIH(AC) on the rising edge and VIL(AC) to VIH(DC) on the falling edge. For signals referenced

to VREF, the valid intersection is where the “tangent” line intersects VREF, as shown in

Figures 26, 28, 30, and 32.

5. Input waveform hold (tIHb) timing is referenced from the input signal crossing at the VIL(DC)

level for a rising signal and VIH(DC) for a falling signal applied to the device under test, as

shown in Figure 33 on page 65.

6. Input waveform setup timing (tDS) and hold timing (tDH) for single-ended data strobe is

referenced from the crossing of DQS, UDQS, or LDQS through the VREF level applied to the

device under test, as shown in Figure 35 on page 66.

7. Input waveform setup timing (tDS) and hold timing (tDH) when differential data strobe is

enabled is referenced from the cross-point of DQS/DQS#, UDQS/UDQS#, or LDQS/LDQS#, as

shown in Figure 34 on page 65.

8. Input waveform timing is referenced to the crossing point level (VIX) of two input signals

(VTR and VCP) applied to the device under test, where VTR is the true input signal and VCP is

the complementary input signal, as shown in Figure 36 on page 66.

9. The slew rate for differentially ended inputs is measured from twice the DC level to twice

the AC level: 2 × VIL(DC) to 2 × VIH(AC) on the rising edge and 2 × VIL(AC) to 2 × VIH(DC) on the

falling edge. For example, the CK/CK# would be –250mV to +500mV for CK rising edge and

would be +250mV to –500mV for CK falling edge.

Table 29: AC Input Test Conditions

Parameter Symbol Min Max Units Notes

Input setup timing measurement reference level address

balls, bank address balls, CS#, RAS#, CAS#, WE#, ODT, DM,

UDM, LDM, and CKE

VRS See Note 2 1, 2, 3,

Input hold timing measurement reference level address

balls, bank address balls, CS#, RAS#, CAS#, WE#, ODT, DM,

UDM, LDM, and CKE

VRH See Note 5 1, 3, 4,

Input timing measurement reference level (single-ended)

DQS for x4, x8; UDQS, LDQS for x16 VREF(DC)VDDQ × 0.49 VDDQ × 0.51 V 1, 3, 4,

Input timing measurement reference level (differential)

CK, CK# for x4, x8, x16; DQS, DQS# for x4, x8; RDQS,

RDQS# for x8; UDQS, UDQS#, LDQS, LDQS# for x16

VRD VIX(AC) V 1, 3, 7,

8, 9

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1Gb: x4, x8, x16 DDR2 SDRAM

Input Slew Rate Derating

For all input signals, the total tIS (setup time) and tIH (hold time) required is calculated

by adding the data sheet tIS (base) and tIH (base) valu e to the ΔtIS and ΔtIH derating

value, re spectively. Example: tIS (total setup time) = tIS (base) + ΔtIS.

tIS, the nominal slew rate for a rising signal, is defined as the slew rate between the last

crossing of VREF(DC) and the first crossing of VIH(AC) MIN. Setup nominal slew rate (tIS)

for a falling signal is defined as the slew rate between the last cr ossing of VREF(DC) and

the first crossing of VIL(AC) MAX.

If the actual signal is always earlier than the nominal slew rate line between shaded

“VREF(DC) to AC region,” use the nominal slew rate for the derating value (Figure 25 on

page 57).

If the actual signal is later than the nominal slew rate line anywhere between the shaded

“VREF(DC) to AC region,” the slew rate of a tangent line to the actual signal from the AC

level to DC level is used f or the de rating value (see Figure26 on page 57).

tIH, the nominal slew rate for a rising signal, is defined as the slew rate between the last

crossing of VIL(DC) MAX and the first crossing of VREF(DC). tIH, nominal slew rate for a

falling signal, is defined as the slew rate between the last crossing of VIH(DC) MIN and

the first crossing of VREF(DC).

If the actual signal is always later than the nominal slew r ate line be tween shaded “ D C to

VREF(DC) region,” use the nominal slew rate for the derating value (Figure 27 on

page 58).

If the actual signal is earlier than the nominal slew rate line anywhere between shaded

“DC to VREF(DC) region,” the slew rate of a tangent line to the actual signal from the DC

level to VREF(DC) level is used for the derating value (Figure 28 on page 58).

Although the total setup time might be negative for slow slew rates (a valid input signal

will not have reached VIH[AC]/VIL[AC] at the time of the rising clock transition), a valid

input signal is still required to complete the transition and reach VIH(AC)/VIL(AC).

For slew rates in between the values listed in Tables 30 and 31 on page 56, the derating

values may obtained by linear interpolation.

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1Gb: x4, x8, x16 DDR2 SDRAM

Input Slew Rate Derating

Table 30: DDR2-400/533 Setup and Hold Time Derating Values (tIS and tIH)

Command/

Address Slew

Rate (V/ns)

CK, CK# Differential Slew Rate

Units

2.0 V/ns 1.5 V/ns 1.0 V/ns

ΔtIS ΔtIH ΔtIS ΔtIH ΔtIS ΔtIH

4.0 +187 +94 +217 +124 +247 +154 ps

3.5 +179 +89 +209 +119 +239 +149 ps

3.0 +167 +83 +197 +113 +227 +143 ps

2.5 +150 +75 +180 +105 +210 +135 ps

2.0 +125 +45 +155 +75 +185 +105 ps

1.5 +83 +21 +113 +51 +143 +81 ps

1.0 0 0 +30 +30 +60 +60 ps

0.9 –11 –14 +19 +16 +49 +46 ps

0.8 –25 –31 +5 –1 +35 +29 ps

0.7 –43 –54 –13 –24 +17 +6 ps

0.6 –67 –83 –37 –53 –7 –23 ps

0.5 –110 –125 –80 –95 –50 –65 ps

0.4 –175 –188 –145 –158 –115 –128 ps

0.3 –285 –292 –255 –262 –225 –232 ps

0.25 –350 –37 5 –320 –345 –290 –315 ps

0.2 –525 –500 –495 –470 –465 –440 ps

0.15 –800 –708 –770 –678 –740 –648 ps

0.1 –1,450 –1,125 –1,420 –1,095 –1,390 –1,065 ps

Table 31: DDR2-667/800/1066 Setup and Hold Time Derating Values (tIS and tIH)

Command/

Address Slew

Rate (V/ns)

CK, CK# Differential Slew Rate

Units

2.0 V/ns 1.5 V/ns 1.0 V/ns

ΔtIS ΔtIH ΔtIS ΔtIH ΔtIS ΔtIH

4.0 +150 +94 +180 +124 +210 +154 ps

3.5 +143 +89 +173 +119 +203 +149 ps

3.0 +133 +83 +163 +113 +193 +143 ps

2.5 +120 +75 +150 +105 +180 +135 ps

2.0 +100 +45 +160 +75 +160 +105 ps

1.5 +67 +21 +97 +51 +127 +81 ps

1.0 0 0 +30 +30 +60 +60 ps

0.9 –5 –14 +25 +16 +55 +46 ps

0.8 –13 –31 +17 –1 +47 +29 ps

0.7 –22 –54 +8 –24 +38 +6 ps

0.6 –34 –83 –4 –53 +36 –23 ps

0.5 –60 –125 –30 –95 0 –65 ps

0.4 –100 –188 –70 –158 –40 –128 ps

0.3 –168 –292 –138 –262 –108 –232 ps

0.25 –200 –375 –170 –345 –140 –315 ps

0.2 –325 –500 –295 –470 –265 –440 ps

0.15 –517 –708 –487 –678 –457 –648 ps

0.1 –1,000 –1,125 –970 –1,095 –940 –1,065 ps

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1Gb: x4, x8, x16 DDR2 SDRAM

Input Slew Rate Derating

Figure 25: Nominal Slew Rate for tIS

Figure 26: Tangent Line for tIS

CK#

tIH

tIStIH

Setup slew rate

rising signal

Setup slew rate

falling signal

DTF DTR

(

) MIN -

REF

(

)

tIS

Nominal

slew rate

REF

to AC

region

REF

to AC

region

REF

(

)

- V

(

) MAX

(

) MIN

REF

(

)

(

) MAX

(

) MAX

(

) MIN

Nominal

slew rate

Setup slew rate

rising signal

ΔTF ΔTR

Tangent line (V

[

] MIN - V

REF

[

])

ΔTR

Tangent

line

Tangent

line

REF

to AC

region

Nominal

line

tIH

tIStIH tIS

VSS

CK#

VDDQ

VIH(AC) MIN

VIH(DC) MIN

VREF(DC)

VIL(DC) MAX

VIL(AC) MAX

REF

to AC

region

Nominal

line

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1Gb: x4, x8, x16 DDR2 SDRAM

Input Slew Rate Derating

Figure 27: Nominal Slew Rate for tIH

Figure 28: Tangent Line for tIH

ΔTR ΔTF

Nominal

slew rate DC to V

REF

region

tIH

tIStIS

CK#

(

) MIN

REF

(

)

(

) MAX

(

) MAX

(

) MIN

DC to V

REF

region Nominal

slew rate

tIH

Tangent

line DC to V

REF

region

tIH

tIStIS

(

) MIN

REF

(

)

(

) MAX

(

) MAX

(

) MIN

DC to V

REF

region Tangent

line

tIH

CK#

Hold slew rate

falling signal

ΔTF

ΔTR

Tangent line (V

[

] MIN - V

REF

[

])

ΔTF

Nominal

line

Hold slew rate

rising signal

Tangent line (V

REF

[

] - V

[

] MAX)

ΔTR

Nominal

line

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1Gb: x4, x8, x16 DDR2 SDRAM

Input Slew Rate Derating

Notes: 1. For all input signals, the total tDS and tDH required is calculate d by adding the data sheet

value to the derating value listed in Table 32.

2. tDS nominal slew rate for a rising signal is defined as the slew rate between the last crossing

of VREF(DC) and the first crossing of VIH(AC) MIN. tDS nominal slew rate for a falling signal is

defined as the slew rate between the last crossing of VREF(DC) and the first crossing of

VIL(AC) MAX. If the actual signal is always earlier than the nominal slew rate line between

the shaded “VREF(DC) to AC region,” use the nominal slew rate for the derating value (see

Figure 29 on page 63). If the actual signal is later than the nominal slew rate line anywhere

between the shaded “VREF(DC) to AC region,” the slew rate of a tangent line to the actual

signal from the AC level to DC level is used for the derating value (see Figure 30 on

page 63).

3. tDH nominal slew rate for a rising signal is defined as the slew rate between the last cross-

ing of VIL(DC) MAX and the first crossing of V REF(DC). tDH nominal slew rate for a falling sig-

nal is d efined as the sle w rate b etween th e last cr ossing of VIH(DC) MIN and the first crossing

of VREF (DC). If the actual signal is always later than the no mina l slew rate li ne betw een the

shaded “DC level to VREF(DC) region,” use the nominal slew rate for the derating value (see

Figure 31 on page 64). If the actual signal is earlier than the nominal slew rate line any-

where between shaded “DC to VREF(DC) region,” the slew rate of a tangent line to the

actual signal from the DC level to V REF(DC) level is used for the derating value (see Figure 32

on page 64).

4. Although the total setup time might be negative for slow slew rates (a valid input signal

will not have reached VIH[AC]/VIL[AC] at the time of the rising clock transition), a valid input

signal is still required to complete the transition and reach VIH(AC)/VIL(AC).

5. For slew rates between the values listed in this table, the derating values may be obtained

by linear interpolation.

6. These values are typically not subject to production test. They are verified by design and

characterization.

7. Single-ended DQS requires special de rating. The values in Table 34 on page 61 are the DQS

single-ended slew rate derating with DQS referenced at VREF and DQ referenced at the

logic levels tDSb and tDHb. Converting the derated base values from DQs referenced to the

AC/DC trip points to DQs referenced to VREF is listed in Table 36 on page 62 and Table 37 on

page 62. Table 36 on page 62 provides the VREF-based fully derated values for the DQ (tDSa

and tDHa) for DDR2-533. Table 37 on page 62 provides the VREF-based fully derated values

for the DQ (tDSa and tDHa) for DDR2-400.

Table 32: DDR2-400/DDR2-533 tDS, tDH Derating Values with Differential Strobe

All units are shown in picoseconds

Slew

Rate

(V/ns)

DQS, DQS# Differential Slew Rate

4.0 V/ns 3.0 V/ns 2.0 V/ns 1.8 V/ns 1.6 V/ns 1.4 V/ns 1.2 V/ns 1.0 V/ns 0.8 V/ns

tDS Δ

tDH Δ

tDS Δ

tDH Δ

tDS Δ

tDH Δ

tDS Δ

tDH Δ

tDS Δ

tDH Δ

tDS Δ

tDH Δ

tDS Δ

tDH Δ

tDS Δ

tDH Δ

tDS Δ

tDH

2.0125451254512545––––––––––––

1.5 8321832183219533 – – – – – – – – – –

1.000000012122424––––––––

0.9 – – –11 –14 –11 –14 1 –2 13 10 25 22 – – – – – –

0.8 – – – – –25 –31 –13 –19 –1 –7 11 5 23 17 – – – –

0.7 – – – – – – –31 –42 –19 –30 –7 –18 5 –6 17 6 – –

0.6 – – – – – – – – –43 –59 –31 –47 –19 –35 –7 –23 5 –11

0.5 – – – – – – – – – – –74 –89 –62 –77 –50 –65 –38 –53

0.4 – – – – – – – – – – – – –127 –140 –115 –128 –103 –116

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1Gb: x4, x8, x16 DDR2 SDRAM

Input Slew Rate Derating

Notes: 1. For all input signals the total tDS and tDH required is calculated by adding the data sheet

value to the derating value listed in Table 33.

2. tDS nominal slew rate for a rising signal is defined as the slew rate between the last crossing

of VREF(DC) and the first crossing of VIH(AC) MIN. tDS nominal slew rate for a falling signal is

defined as the slew rate between the last crossing of VREF(DC) and the first crossing of

VIL(AC) MAX. If the actual signal is always earlier than the nominal slew rate line between

the shaded “VREF(DC) to AC region,” use the nominal slew rate for the derating value (see

Figure 29 on page 63). If the actual signal is later than the nominal slew rate line anywhere

between shaded “VREF(DC) to AC region,” the slew rate of a tangent line to the actual signal

from the AC level to DC level is used for the derating value (see Figure 30 on page 63).

3. tDH nominal slew rate for a rising signal is defined as the slew rate between the last cross-

ing of VIL(DC) MAX and the first crossing of V REF(DC). tDH nominal slew rate for a falling sig-

nal is d efined as the sle w rate b etween th e last cr ossing of VIH(DC) MIN and the first crossing

of VREF(DC). If the actual signal is always later than the nominal slew rate line between the

shaded “DC level to VREF(DC) region,” use the nominal slew rate for the derating value (see

Figure 31 on page 64). If the actual signal is earlier than the nominal slew rate line any-

where between the shaded “DC to VREF(DC) region,” the slew rate of a tangent line to the

actual signal from the DC level to V REF(DC) level is used for the derating value (see Figure 32

on page 64).

4. Although the total setup time might be negative for slow slew rates (a valid input signal

will not have reached VIH[AC]/VIL[AC] at the time of the rising clock transition), a valid input

signal is still required to complete the transition and reach VIH(AC)/VIL(AC).

5. For slew rates between the values listed in this table, the derating values may be obtained

by linear interpolation.

6. These values are typically not subject to production test. They are verified by design and

characterization.

7. Single-ended DQS requires special de rating. The values in Table 34 on page 61 are the DQS

single-ended slew rate derating with DQS referenced at VREF and DQ referenced at the

logic levels tDSb and tDHb. Converting the derated base values from DQs referened to the

AC/DC trip points to DQs referenced to VREF is listed in Table 35 on page 61. Table 35 on

page 61 provides the VREF-based fully derated values for the DQ (tDSa and tDHa) for DDR2-

667. It is not advised to operate DDR2-800 and DDR2-1066 devices with single-ended DQS;

however Table 34 on page 61 would be used with the base values.

Table 33: DDR2-667/DDR2-800/DDR2-1066 tDS, tDH Derating Values with Differential Strobe

All units are shown in picoseconds

Slew

Rate

(V/ns)

DQS, DQS# Differential Slew Rate

2.8 V/ns 2.4 V/ns 2.0 V/ns 1.8 V/ns 1.6 V/ns 1.4 V/ns 1.2 V/ns 1.0 V/ns 0.8 V/ns

tDS Δ

tDH Δ

tDS Δ

tDH Δ

tDS Δ

tDH Δ

tDS Δ

tDH Δ

tDS Δ

tDH Δ

tDS Δ

tDH Δ

tDS Δ

tDH Δ

tDS Δ

tDH Δ

tDS Δ

tDH

2.0 100 63 100 63 100 63 112 75 124 87 136 99 148 111 160 123 172 135

1.5 67 42 67 42 67 42 79 54 91 66 103 78 115 90 127 102 139 114

1.0 0 0 0 0 0 0 121224243636484860607272

0.9 –5–14–5–14–5–147 –219103122433455466758

0.8 –13 –31 –13 –31 –13 –31 –1 –19 11 –7 23 5 35 17 47 29 59 41

0.7 –22 –54 –22 –54 –22 –54 –10 –42 2 –30 14 –18 26 –6 38 6 50 18

0.6 –34 –83 –34 –83 –34 –83 –22 –71 –10 –59 2 –47 14 –35 26 –23 38 –11

0.5 –60 –125 –60 –125 –60 –125 –48 –113 –36 –101 –24 –89 –12 –77 0 –65 12 –53

0.4 –100 –188 –100 –188 –100 –188 –88 –176 –76 –164 –64 –152 –52 –140 –40 –128 –28 –116

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1Gb: x4, x8, x16 DDR2 SDRAM

Input Slew Rate Derating

Table 34: Single-Ended DQS Slew Rate Derating Values Using tDSb and tDHb

Reference points indicated i n bold; Derating values are to be used with base tDSb- and tDHb-specified values

(V/ns)

DQS Single-Ended Slew Rate Derated (at VREF)

2.0 V/ns 1.8 V/ns 1.6 V/ns 1.4 V/ns 1.2 V/ns 1.0 V/ns 0.8 V/ns 0.6 V/ns 0.4V/ns

tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH

2.0 130 53 130 53 130 53 130 53 130 53 145 48 155 45 165 41 175 38

1.5 97 32 97 32 97 32 97 32 97 32 112 27 122 24 132 20 142 17

1.0 30 –10 30 –10 30 –10 30 –10 30 –10 45 –15 55 –18 65 –22 75 –25

0.9 25 –24 25 –24 25 –24 25 –24 25 –24 40 –29 50 –32 60 –36 70 –39

0.8 17 –41 17 –41 17 –41 17 –41 17 –41 32 –46 42 –49 52 –53 61 –56

0.7 5 –64 5 –64 5 –64 5 –64 5 –64 20 –69 30 –72 40 –75 50 –79

0.6 –7 –93 –7 –93 –7 –93 –7 –93 –7 –93 8 –98 18 –102 28 –105 38 –108

0.5 –28 –135 –28 –135 –28 –135 –28 –135 –28 –135 –13 –140 –3 –143 7 –147 17 –150

0.4 –78 –198 –78 –198 –78 –198 –78 –198 –78 –198 –63 –203 –53 –206 –43 –210 –33 –213

Table 35: Single-Ended DQS Slew Rate Fully Derated (DQS, DQ at VREF) at DDR2-667

Reference points indicated in bold

(V/ns)

DQS Single-Ended Slew Rate Derated (at VREF)

2.0 V/ns 1.8 V/ns 1.6 V/ns 1.4 V/ns 1.2 V/ns 1.0 V/ns 0.8 V/ns 0.6 V/ns 0.4V/ns

tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH

2.0 330 291 330 291 330 291 330 291 330 291 345 286 355 282 365 29 375 276

1.5 330 290 330 290 330 290 330 290 330 290 345 285 355 282 365 279 375 275

1.0 330 290 330 290 330 290 330 290 330 290 345 285 355 282 365 278 375 275

0.9 347 290 347 290 347 290 347 290 347 290 362 285 372 282 382 278 392 275

0.8 367 290 367 290 367 290 367 290 367 290 382 285 392 282 402 278 412 275

0.7 391 290 391 290 391 290 391 290 391 290 406 285 416 281 426 278 436 275

0.6 426 290 426 290 426 290 426 290 426 290 441 285 451 282 461 278 471 275

0.5 472 290 472 290 472 290 472 290 472 290 487 285 497 282 507 278 517 275

0.4 522 289 522 289 522 289 522 289 522 289 537 284 547 281 557 278 567 274

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1Gb: x4, x8, x16 DDR2 SDRAM

Input Slew Rate Derating

Table 36: Single-Ended DQS Slew Rate Fully Derated (DQS, DQ at VREF) at DDR2-533

Reference points indicated in bold

(V/ns)

DQS Single-Ended Slew Rate Derated (at VREF)

2.0 V/ns 1.8 V/ns 1.6 V/ns 1.4 V/ns 1.2 V/ns 1.0 V/ns 0.8 V/ns 0.6 V/ns 0.4V/ns

tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH

2.0 355 341 355 341 355 341 355 341 355 341 370 336 380 332 390 329 400 326

1.5 364 340 364 340 364 340 364 340 364 340 379 335 389 332 399 329 409 325

1.0 380 340 380 340 380 340 380 340 380 340 395 335 405 332 415 328 425 325

0.9 402 340 402 340 402 340 402 340 402 340 417 335 427 332 437 328 447 325

0.8 429 340 429 340 429 340 429 340 429 340 444 335 454 332 464 328 474 325

0.7 463 340 463 340 463 340 463 340 463 340 478 335 488 331 498 328 508 325

0.6 510 340 510 340 510 340 510 340 510 340 525 335 535 332 545 328 555 325

0.5 572 340 572 340 572 340 572 340 572 340 587 335 597 332 607 328 617 325

0.4 647 339 647 339 647 339 647 339 647 339 662 334 672 331 682 328 692 324

Table 37: Single-Ended DQS Slew Rate Fully Derated (DQS, DQ at VREF) at DDR2-400

Reference points indicated in bold

(V/ns)

DQS Single-Ended Slew Rate Derated (at VREF)

2.0 V/ns 1.8 V/ns 1.6 V/ns 1.4 V/ns 1.2 V/ns 1.0 V/ns 0.8 V/ns 0.6 V/ns 0.4V/ns

tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH

2.0 405 391 405 391 405 391 405 391 405 391 420 386 430 382 440 379 450 376

1.5 414 390 414 390 414 390 414 390 414 390 429 385 439 382 449 379 459 375

1.0 430 390 430 390 430 390 430 390 430 390 445 385 455 382 465 378 475 375

0.9 452 390 452 390 452 390 452 390 452 390 467 385 477 382 487 378 497 375

0.8 479 390 479 390 479 390 479 390 479 390 494 385 504 382 514 378 524 375

0.7 513 390 513 390 513 390 513 390 513 390 528 385 538 381 548 378 558 375

0.6 560 390 560 390 560 390 560 390 560 390 575 385 585 382 595 378 605 375

0.5 622 390 622 390 622 390 622 390 622 390 637 385 647 382 657 378 667 375

0.4 697 389 697 389 697 389 697 389 697 389 712 384 722 381 732 378 742 374

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1Gb: x4, x8, x16 DDR2 SDRAM

Input Slew Rate Derating

Figure 29: Nominal Slew Rate for tDS

Notes: 1. DQS, DQS# signals must be monotonic between VIL(DC) MAX and VIH(DC) MIN.

Figure 30: Tangent Line for tDS

Notes: 1. DQS, DQS# signals must be monotonic between VIL(DC) MAX and VIH(DC) MIN.

REF

to AC

region

REF

to AC

region

Setup slew rate

rising signal

Setup slew rate

falling signal

REF

(

)

- V

(

) MAX

ΔTF

(

) MIN -

REF

(

)

ΔTR

Nominal

slew rate

DQS#1

DQS1

(

) MIN

REF

(

)

(

) MAX

(

) MAX

(

) MIN

tDH

tDS

Nominal

slew rate

tDH

tDS

Setup slew rate

rising signal

Setup slew rate

falling signal Tangent line (V

REF

[

] - V

[

] MAX)

ΔTF

=Tangent line (V

[

] MI N - V

REF

[

])

ΔTR

tDH

tDS

tDH

tDS

DQS#1

DQS1

(

) MIN

REF

(

)

(

) MAX

(

) MAX

(

) MIN

Nominal line

Tangent line

Nominal

line

Tangent line

REF

to AC

region

REF

to AC

region

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1Gb: x4, x8, x16 DDR2 SDRAM

Input Slew Rate Derating

Figure 31: Nominal Slew Rate for tDH

Notes: 1. DQS, DQS# signals must be monotonic between VIL(DC) MAX and VIH(DC) MIN.

Figure 32: Tangent Line for tDH

Notes: 1. DQS, DQS# signals must be monotonic between VIL(DC) MAX and VIH(DC) MIN.

Hold slew rate

falling signal

Hold slew rate

rising signal

REF

(

) -

(

) MAX

(

) MIN -

REF

(

)

ΔTR ΔTF

Nominal

slew rate DC to V

REF

region

tIH

tIStIS

DQS#1

DQS1

(

) MIN

REF

(

)

(

) MAX

(

) MAX

(

) MIN

DC to V

REF

region Nominal

slew rate

tIH

Tangent

line DC to V

REF

region

tIH

tIStIS

(

) MIN

REF

(

)

(

) MAX

(

) MAX

(

) MIN

DC to V

REF

region Tangent

line

tIH

DQS1

DQS#1

Hold slew rate

falling signal

ΔTF

ΔTR

Tangent line (V

[

] MIN - V

REF

[

])

ΔTF

Nominal

line

Hold slew rate

rising signal

Tangent line (V

REF

[

] - V

[

] MAX)

ΔTR

Nominal

line

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1Gb: x4, x8, x16 DDR2 SDRAM

Input Slew Rate Derating

Figure 33: AC Input Test Signal Waveform Command/Address Balls

Figure 34: AC Input Test Signal Waveform for Data with DQS, DQS# (Differential)

tISa

Logic levels

VREF levels

tIHatISatIHa

tISbtIHbtISbtIHb

CK#

VDDQ

VIH(AC) MIN

VIH(DC) MIN

VREF(DC)

VIL(DC) MIN

VIL(AC) MIN

VSSQ

VSWING (MAX)

DQS#

DQS

tDSatDHatDSatDHa

tDSbtDHbtDSbtDHb

Logic levels

REF

levels

REF

(

)

(

) MAX

(

) MAX

(

) MIN

(

) MIN

SWING

(MAX)

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1Gb: x4, x8, x16 DDR2 SDRAM

Input Slew Rate Derating

Figure 35: AC Input Test Signal Waveform for Data with DQS (Single-Ended)

Figure 36: AC Input Test Signal Waveform (Differential)

DQS

VREF

VREF(DC)

VIL(DC) MAX

VIL(AC) MAX

VSSQ

VIH(DC) MIN

VIH(AC) MIN

VDDQ

VSWING (MAX)

Logic levels

VREF levels tDSatDHatDSatDHa

tDSbtDHbtDSbtDHb

VTR

VSWING

VCP

VDDQ

VSSQ

VIX

Crossing point

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1Gb: x4, x8, x16 DDR2 SDRAM

Commands

Truth Tables

The following tables provide a quick reference of available DDR2 SDRAM commands,

including CKE power-down modes and bank-to-bank commands.

Notes: 1. All DDR2 SDRAM commands are defined by states of CS#, RAS#, CAS#, WE#, and CKE at the

rising edge of the clock.

2. The state of ODT does not affect the states described in this table. The ODT function is not

available during self refresh. See “ODT Timing” on page 120 for details.

3. “X” means “H or L” (but a defined logic level) for valid IDD measurements.

4. BA2 is only applicable for densities >1Gb.

5. An is the mos t si gnificant add re ss bit for a given density and conf ig ur ation. Some larger

address bits may be “Don’t Care” during column addressing, depending on density an d con-

figuration.

6. Bank addresses (BA) determin e which bank is to be operated upon. BA during a LOAD

MODE command selects which mode register is programmed.

7. SELF REFRESH exit is asynchronous.

8. Burst reads or writes at BL = 4 cannot be terminated or interrupted. See Figure 50 on

page 90 and Figure 63 on page 101 for other restrictions and details.

9. The power-down mode does not perform any RE FRESH operations. The duration of power-

down is limited by the refresh requirements outlined in the AC parametric section.

Table 38: Truth Table – DDR2 Commands

Notes: 1–3 apply to the entire table

Function

CKE

CS# RAS# CAS# WE# BA2–

BA0 An–A11 A10 A9–A0 Notes

Cycle Current

Cycle

LOAD MODE H H L L L L BA OP code 4, 6

REFRESH HHLLLHXXXX

SELF REFRESH entry HLLLLHXXXX

SELF REFRESH exit LHHXXXXXXX4, 7

LHHH

Single bank PRECHARGE HHLLHLBAXLX6

All banks PRECHARGE HHLLHLXXHX

Bank activate H H L L H H BA Row address 4

WRITE HHLHLLBAColumn

address L Column

address 4, 5, 6, 8

WRITE with auto

precharge HHLHLLBAColumn

address H Column

address 4, 5, 6, 8

READ HHLHLHBAColumn

address L Column

address 4, 5, 6, 8

READ with auto

precharge HHLHLHBAColumn

address H Column

address 4, 5, 6, 8

NO OPERATION HXLHHHXXXX

Device DESELECT HXHXXXXXXX

Power-down entry HLHXXXXXXX 9

LHHH

Power-dow n exit LHHXXXXXXX9

LHHH

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1Gb: x4, x8, x16 DDR2 SDRAM

Commands

Notes: 1. This table applies when CKEn - 1 was HIGH and CKEn is HIGH and after tXSNR has bee n met

(if the previous state was self refresh).

2. This table is bank-specific, except where noted (the current state is for a specific bank and

the commands shown are those allowed to be issued to that bank when in that state).

Exceptions ar e covered in the notes below.

3. Current state definitions:

4. The following states must not be interrupted by a command issued to the same bank. Issue

DESELECT or NOP commands, or allowable commands to the other bank, on any clock edge

occurring during these states. Allowable commands to the other bank are determined by its

current state and this table, and accordi ng to Table 40 on page 70.

Table 39: Truth Table – Current State Bank n – Command to Bank n

Notes: 1–6 apply to the entire table

Current

State CS# RAS# CAS# WE# Command/Action Notes

Any HXXX

DESELECT (NOP/continue previous operation)

LHHH

NO OPERATION (NOP /continue previous

operation)

Idle LLHH

ACTIVATE (select and activate row)

LLLH

REFRESH 7

LLLL

LOAD MODE 7

Row active LHLH

READ (select column and start READ burst) 8

LHLL

WRITE (select column and start WRITE burst) 8

LLHL

PRECHARGE (deactivate row in bank or banks) 9

Read (auto-

precharge

disabled)

LHLH

READ (select column and start new READ burst) 8

LHLL

WRITE (select column and start WRITE burst) 8, 10

LLHL

PRECHARGE (start PRECHARGE) 8

Write (auto-

precharge

disabled)

LHLH

READ (select column and start READ burst) 8

LHLL

WRITE (select column and start new WRITE burst) 8

LLHL

PRECHARGE (start PRECHARGE) 9

Idle: The bank has been precharged, tRP has been met, and any READ burst

is complete.

Row active: A row in the bank has been activated, and tRCD has been met. No

data bursts/accesses and no register accesses are in progress.

Read: A READ burst has been initiated, with auto precharge disabled and

has not yet terminated.

Write: A WRITE burst has been initiated with auto precharge disabled and

has not yet terminated.

Precharge: Starts with registration of a PRECHARGE command and ends when tRP

is met. After tRP is met, the bank will be in the idle state.

Read with auto

precharge enabled: Starts with registration of a READ command with auto precharge

enabled and ends when tRP has been met. After tRP is met, the bank

will be in the idle state.

Row activate: Starts with registra tion of an ACTIVATE command and ends when

tRCD is met. After tRCD is met, the bank will be in the row active state.

Write with auto

precharge enabled: Starts with registration of a WRITE command with auto precharge

enabled and ends when tRP has been met. After tRP is met, the bank

will be in the idle state.

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1Gb: x4, x8, x16 DDR2 SDRAM

Commands

5. The following states must not be interrupted by any executable command (DESELECT or

NOP commands must be applied on each positive clock edge during these states):

6. All stat e s and sequences not shown are illegal or reserved.

7. Not bank-specific; requires that all banks are idle and bursts are not in progress.

8. READs or WRITEs listed in the Command/Action column include READs or WRIT Es wit h auto

precharge enabled and READs or WRITEs with auto precharge disabled.

9. May or may not be bank-specific; if multiple banks are to be precharged, each must be in a

valid state for precharging.

10. A WRITE command may be applied after the completion of the READ burst.

Refresh: Starts with registration of a REFRESH command and ends when tRFC is

met. After tRFC is met, the DDR2 SDRAM will be in the all banks idle

state.

Accessing mode

tMRD has been met. After tMRD is met, the DDR2 SDRAM will be in

the all banks idle state.

Precharge all: Starts with registration of a PRECHARGE ALL command and ends

when tRP is met. After tRP is met, all banks will be in the idle state.

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1Gb: x4, x8, x16 DDR2 SDRAM

Commands

Notes: 1. This table applies when CKEn - 1 was HIGH and CKEn is HIGH and after tXSNR ha s been m et

(if the previous state was self refresh).

2. This table describes an alternate bank operation, except where noted (the current state is

for bank n and the commands shown are those allowed to be issued to bank m, assuming

that bank m is in such a state that the given command is allowable). Exceptions are covered

in the notes below.

3. Current state definitions:

Table 40: Truth Table – Current State Bank n – Command to Bank m

Notes: 1–6 apply to the entire table

Current State CS# RAS# CAS# WE# Command/Action Notes

Any HXXX

DESELECT (NOP/continue previous operation)

LHHH

NO OPERATION (NOP/continue previous operation)

Idle XXXX

Any command otherwise allowed to bank m

Row active, active,

or precharge LLHH

ACTIVATE (select and activate row)

LHLH

READ (select column and start READ burst) 7

LHLL

WRITE (select column and start WRITE burst) 7

LLHL

PRECHARGE

Read (auto

precharge

disabled)

LLHH

ACTIVATE (select and activate row)

LHLH

READ (select column and start new READ burst) 7

LHLL

WRITE (select column and start WRITE burst) 7, 8

LLHL

PRECHARGE

Write (auto

precharge

disabled)

LLHH

ACTIVATE (select and activate row)

LHLH

READ (select column and start READ burst) 7, 9, 10

LHLL

WRITE (select column and start new WRITE burst) 7

LLHL

PRECHARGE

Read (with auto-

precharge) LLHH

ACTIVATE (select and activate row)

LHLH

READ (select column and start new READ burst 7

LHLL

WRITE (select column and start WRITE burst) 7, 8

LLHL

PRECHARGE

Write (with auto-

precharge) LLHH

ACTIVATE (select and activate row)

LHLH

READ (select column and start READ burst) 7, 10

LHLL

WRITE (select column and start new WRITE burst) 7

LLHL

PRECHARGE

Idle: The bank has been precharged, tRP has been met, and any READ burst is

complete.

Row active: A row in the bank has been activated and tRCD has been met. No data bursts/

accesses and no register accesses are in progress.

Read: A READ burst has been initiated with auto precharge di sabled and has not

yet terminated.

Write: A WRITE burst has been initiated with auto precharge disabled and has not

yet terminated.

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1Gb: x4, x8, x16 DDR2 SDRAM

Commands

The minimum delay from a READ or WRITE command with auto precharge enabled to a

command to a different bank is summarized in Table 41:

4. REFRESH and LOAD MODE commands may only be issued when all banks are idle.

5. Not used.

6. All stat e s and sequences not shown are illegal or reserved.

7. READs or WRITEs listed in the Command/Action column include READs or WRITEs with auto

precharge enabled and READs or WRITEs with auto precharge disabled.

8. A WRITE command may be applied after the completion of the READ burst .

9. Requires appropria te DM.

10. The number of clock cycles required to meet tWTR is either two or tWTR/tCK, whichever is

greater.

DESELECT

The DESELECT function (CS# HIGH) prevents new commands from being executed by

the DDR2 SDRAM. The DDR2 SDRAM is effectively deselected. Oper ations already in

progress are not affected. DESELECT is also referred to as COMMAND INHIBIT.

READ with

auto

precharge

enabled/

WRITE with

auto

precharge

enabled:

The READ with auto precharge enabled or WRITE with auto precharge

enabled states can each be broken into two parts: the access period and the

precharge period. For READ with auto precha rge, the precharge period is

defined as if the same burst was executed with auto precharge disabled and

then followed with the earliest possible PRECHARGE command that still

accesses all of the data in the burst. For WRITE with auto precharge, the

precharge period begins when tWR ends, with tWR measured as if auto

precharge was disabled. The access period starts with re gistration of the

command and ends where the precharge period (or tRP) begins. This device

supports conc urrent auto precharge such that when a READ with auto

precharge is enabled or a WRITE with auto precharge is ena bled, any

command to other banks is allowed, as long as that command does not

interrupt the read or write data transfer already in process. In either case, all

other related limitations apply (contention between read data and write

data must be avoided).

Table 41: Minimum Delay with Auto Precharge Enabled

From Command

(Bank n)To Command (Bank m)

Minimum Delay

(with Concurrent

Auto Precharge) Units

WRITE with auto

precharge REA D or READ with auto

precharge (CL - 1) + (BL/2) + tWTR tCK

WRITE or WRITE with auto

precharge (BL/2) tCK

PRECHARGE or ACTIVATE 1 tCK

READ with auto

precharge REA D or READ with auto

precharge (BL/2) tCK

WRITE or WRITE with auto

precharge (BL/2) + 2 tCK

PRECHARGE or ACTIVATE 1 tCK

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1Gb: x4, x8, x16 DDR2 SDRAM

Commands

NO OPERATION (NOP)

The NO OPERATION (NOP) command is used to instruct the selected DDR2 SDRAM to

perform a NOP (CS# is LOW; RAS#, CAS#, and WE are HIGH). This prevents unwanted

commands from being registered during idle or wait states. Operations already in

progress are not affected.

LOAD MODE (LM)

The mode registers are loaded via bank address and address inputs. The bank address

balls determine which mode register will be programmed. See “Mode Register (MR)” on

page 76. The LM command can only be issued when all banks ar e idle , and a subsequent

executable command cannot be issued until tMRD is met.

ACTIVATE

The ACTIVATE command is used to open (or activate) a row in a particular bank for a

subsequent access. The value on the bank address inputs determines the bank, and the

address inputs select the row. This row remains active (or open) for accesses until a

PRECHARGE command is issued to that bank. A PR ECHARG E command must be issued

before opening a different row in the same bank.

READ

The READ command is used to initiate a burst r ead access to an activ e row. The value on

the bank address inputs determine the bank, and the address pro vided on address

inputs A0–Ai (where Ai is the most significant column address bit for a given configura-

tion) selects the starting column location. The value on input A10 determines whether or

not auto precharge is used. If auto precharge is selected, the row being accessed will be

precharged at the end of the READ burst; if auto precharge is not selected, the row will

remain open for subsequent accesses.

DDR2 SDRA M also supports the AL featur e , which allows a READ or WRITE command to

be issued prior to tRCD (MIN) by delaying the actual registration of the READ/WRITE

command to the internal device by AL clock cycles.

WRITE

The WRITE command is used to initiate a burst write access to an active row. The value

on the bank select input s sele cts the bank, and the address provided on inputs A0–Ai

(where Ai is the most significant column addre ss bit for a given configuration) selects

the starting column location. The value on input A10 determines whether or not auto

precharge is used. If auto precharge is selected, the row being accessed will be

precharged at the end of the WRITE burst; if auto precharge is not selected, the row will

remain open for subsequent accesses.

DDR2 SDRA M also supports the AL featur e , which allows a READ or WRITE command to

be issued prior to tRCD (MIN) by delaying the actual registration of the READ/WRITE

command to the internal device by AL clock cycles.

Input data appearing on the DQ is written to the memory array subject to the DM input

logic level appe aring coincident with the data. If a given DM signal is registered LOW,

the corresponding data will be written to memory; if the DM signal is registered HIGH,

the corresponding data inputs will be ignor ed, and a WRITE will not be executed to that

byte/column location (see Figure68 on page 106).

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1Gb: x4, x8, x16 DDR2 SDRAM

Commands

PRECHARGE

The PRECHARGE command is used to deactivate the open row in a particular bank or

the open row in all banks . The bank(s) will be available for a subsequent row activation a

specifie d time (tRP) after the PRECHARGE command is issued, except in the case of

concurrent auto precharge, where a READ or WRITE command to a different bank is

allowed as long as it does not interrupt the data transfer in the current bank and does

not violate any other timing parameters. After a bank has been precharged, it is in the

idle state and must be activated prior to any READ or WRITE commands being issued to

that bank. A PRECHARGE command is allowed if there is no open row in that bank (idle

state) or if the previously ope n r ow is already in the process of precharging. However,

the pr echarge period will be determined by the last PRECHARGE command issued to

the bank.

REFRESH

REFRESH is used during normal operation of the DDR2 SDRAM and is analogous to

CAS#-before-RAS# (CB R) REFRESH. All banks must be in the idle mode prior to issuing a

REFRESH command. This command is nonpersistent, so it must be issued each time a

refresh is required. The addressing is generated by the internal refresh controller. This

makes the address bits a “Don’t Care” during a REFRESH command.

SELF REFRESH

The SELF REFRESH command can be used to retain data in the DDR2 SDRAM, even if

the rest of the system is powered down. When in the self re fresh mode, the DDR2

SDRAM retains data without external clocking. All power supply inputs (including VREF)

must be maintained at valid levels upon entry/e x it and during SELF REFRESH opera-

tion.

The SELF REFRESH command is initiated like a REFRESH command except CKE is

LOW. The DLL is automatically disabled upon ente ring self refresh and is automatically

enabled upon exiting self refresh.

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1Gb: x4, x8, x16 DDR2 SDRAM

Operations

Initialization

DDR2 SDRAMs must be powered up and initia li zed in a predefin ed manner. Operational procedures other than

those specified may result in undefined operation. Figure37 illustrates the sequence required for power-up and

initialization.

Figure 37: DDR2 Power-Up and Initializ ation

LVCMOS

LOW LEVEL2

tVTD1

CKE

Power-up:

and stable

clock (CK, CK#)

T = 200µs (MIN)

High-Z

DM15

DQS15 High-Z

Address3

CK#

tCL

REF

Command3

NOP4

PRE

T0 Ta0

Don’t care

tCL

tCK

ODT

DQ15 High-Z

T = 400ns

(MIN)16

Tb0

200 cycles of CK are required before a READ command can be issued.

MR with

DLL RESET

tRFC

LM8PRE9

LM7REF10 REF LM11

Tg0 Th0 Ti0 Tj0

MR without

DLL RESET EMR with

OCD default

Tk0 Tl0 Tm0

Te0 Tf0

EMR(2) EMR(3)

tMRD

LM6

LM5

A10 = 1

tRPA

Tc0Td0

SSTL_18

LOW LEVEL2

Valid

Indicates a break in

time scale

LM12

EMR with

OCD exit

LM13

Normal

operation

See note 17

CodeCode

A10 = 1

CodeCode

CodeCodeCode

tMRD tMRD tMRD tMRD

tRPA tRFC

tMRD tMRD

EMR

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1Gb: x4, x8, x16 DDR2 SDRAM

Operations

Notes: 1.

Applying power; if CKE is maintained below 0.2 × V

outputs remain disabled. To guaran-

tee RTT (ODT resistance) is off, VREF must be valid and a low level must be applied to the

ODT ball (all other inputs may be undefined; I/Os and outputs must be less than VDDQ dur-

ing voltage ramp time to avoid DDR2 SDRAM device latch-up). VTT is not applied directly to

the device; however, tVTD should be ≥0 to avoid device latch-up. At least one of the follow-

ing two sets of conditions (A or B) must be met to obtain a stable supply state (stable supply

defined as VDD, VDDL, VDDQ, VREF, and VTT are between their minimum and maximum val-

ues as stated in Table 14 on page 42):

A. Single power source: The VDD voltage ramp from 300mV to VDD (MIN) must take no

longer than 200ms; during the VDD voltage ramp, |VDD - VDDQ| ≤ 0.3V. Once supply volt-

age ramping is complete (when VDDQ crosses VDD [MIN]), Table 14 on pa ge 42 specifica-

tions apply.

• VDD, VDDL, and VDDQ are driven from a single power converter output

• VTT is limited to 0.95V MAX

• VREF tracks VDDQ/2; VREF must be within ±0.3V with respect to VDDQ/2 during sup-

ply ramp time

• VDDQ ≥ V REF at all times

B. Multiple power sources: VDD ≥ VDDL ≥ VDDQ must be maintained during supply voltage

ramping, for both AC and DC levels, until supply voltage ramping completes (VDDQ

crosses VDD [MIN]). Once supply voltage ramping is complete, Table 14 on page 42 spec -

ifications apply.

• Apply VDD and VDDL before or at the same time as VDDQ; VDD/VDDL voltage ramp

time must be ≤200ms from when VDD ramps from 300mV to VDD (MIN)

• Apply VDDQ before or at the same time as VTT; the VDDQ voltage ramp tim e fr o m

when VDD (MIN) is achieved to when VDDQ (MIN) is achieved must be ≤500ms; while

VDD is ramping, current can be supplied from VDD through the device to VDDQ

• VREF must track VDDQ/2; VREF must be within ±0.3V with respect to VDDQ/2 du ring

supply ramp time; VDDQ ≥ VREF must be met at all times

• Apply VTT; the VTT voltage ramp time from when VDDQ (MIN) is achieved to when

VTT (MIN) is achieved must be no greater than 500ms

2. CKE requires LVCMOS input levels prior to state T0 to ens ure DQs are High-Z during de vice

power-up prior to VREF being stable. After state T0, CKE is required to have SSTL_18 input

levels. Once CKE transitions to a high level, it must stay HIGH for the duration of the initial-

ization sequence.

3. A10 = PRECHARGE ALL, CODE = desired values for mode registers (bank addresses are

required to be decoded).

4. For a minimum of 200µs after stable power and clock (CK, CK#), apply NOP or DESELECT

commands, then take CKE HIGH.

5. Issue a LOAD MODE command to the EMR(2). To issue an EMR(2) command, provide LOW

to BA0, and provide HIGH to BA1; set register E7 to “0” or “1” to select appropriate self

refresh rate; remaining EMR(2) bits must be “ 0” (see “Extended Mode Register 2 (EMR2)”

on page 84 for all EMR(2) requirements).

6. Issue a LOAD MODE command to the EMR(3). To issue an EMR(3) co mmand , provi de HIGH

to BA0 and BA1; remaining EMR(3) bits must be “0.” See “Extended Mode Register 3 (EMR

3)” on page 85 for all EMR(3) requirements.

7. Issue a LOAD MODE command to the EMR to en able DLL. To issue a DLL ENABLE command,

provide LOW to BA1 and A0; provide HIGH to BA0; bits E7, E8, and E9 can be set to “0” or

“1;” Micron recommends setting them to “0;” remaining EMR bits must be “0.” See

“Extended Mode Register (EMR)” on p age 80 for all EMR r equirements.

8. Issue a LOAD MODE command to the MR for DLL RESET. 200 cycles of clock input is required

to lock the DLL. To issue a DLL RESET, provide HIGH to A8 and provide LOW to BA1 and

BA0; CKE must be HIGH the entire time the DLL is resetting; remaining MR bits must be “0.”

See “Mode Register (MR)” on page 76 for all MR requirements.

9. Issue PRECHARGE ALL command.

10. Issue two or more REFRESH commands.

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1Gb: x4, x8, x16 DDR2 SDRAM

Operations

11. Issue a LOAD MODE command to the MR with LOW to A8 to initialize devic e operation

(that is, to program operating parameters without resetting the DLL). To access th e MR, se t

BA0 and BA1 LOW; remaining MR bits must be set to desired settings. See “Mode Register

(MR)” on page 76 for all MR requirements.

12. Issue a LOAD MODE command to the EMR to enable OCD default by setting bits E7, E8, and

E9 to “1,” and then setting all other desired parameters. To access the EMR, set BA0 LOW

and BA1 HIGH (see “Extended Mode Register (EMR)” on page 80 for all EMR requirements).

13. Issue a LOAD MODE command to the EMR to enable OCD exit by setting bits E7, E8, and E9

to “0,” and then setting all other desired parameters. To access the extended mode regis-

ters, EMR, set BA0 LOW an d BA 1 HIGH for all EMR requirements.

14. The DDR2 SDRAM is now initialized and ready for normal operation 200 clock cycles after

the DLL RESET at Tf0.

15. DM represents DM for the x4, x8 configurations and UDM, LDM for the x16 config uration;

DQS represents DQS, DQS#, UDQS, UDQS#, LDQS, LDQS#, RDQS, RDQS# fo r the ap propriate

configuration (x4, x8, x16); DQ represents DQ0–DQ3 for x4, DQ–DQ7 for x8 and DQ0–DQ15

for x16.

16. Wait a minimum of 400ns then issue a PRECHARGE ALL command.

Mode Register (MR)

The mode reg iste r is used to defi ne the sp ec ific mode of oper ati on of the DDR2 SDRAM.

This definition includes the selection of a burst length, burst type, CAS latency, oper-

ating mode, DLL RESET, write r ecovery, and pow er-down mode, as shown in Figure38

on page 77. Contents of the mode register can be altered by reexecuting the LOAD

MODE (LM) command. If the user chooses to modify only a subset of the MR variables,

all variables must be programmed when the command is issued.

The MR is programmed via the LM command and will retain the stored informati on

until it is programmed again or until the de vice loses power (except for bit M8, which is

self-clearing). Reprogramm ing the mode register will not alter the contents of the

memory array, provided it is per formed correctly.

The LM command can only be issued (or reissued) when all banks ar e in the precharged

state (idle state) and no bursts are in progress. The controller must wait the specifie d

time tMRD before initiating any subsequent operations such as an ACTIVATE

command. Violating either of these requirements will result in an unspecified operation.

Burst Length

Burst length is defined by bits M0–M2, as shown in F igure 38 on page 77. Read and write

accesses to the DDR2 SDRAM are burst-oriented, with the burst length being program-

mable to either four or eight. The burst length determines the maximum number of

column locations that can be accessed for a given READ or WRITE command.

When a READ or WRITE comm and is issu ed , a block of col u m n s eq ual to the bu rst

length is effectivel y selected. All accesses for that burst take place within this block,

meaning that the burst will wrap within the block if a boundary is reached. The block is

uniquely selected by A2–Ai when BL = 4 and by A3–Ai when BL = 8 (where Ai is the most

significant column address bit for a given configuration). The remaining (least signifi-

cant) address bit(s) is (are) used to select the starting location within the block. The

programmed burst length applies to both READ and WR IT E bursts.

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1Gb: x4, x8, x16 DDR2 SDRAM

Operations

Figure 38: Mode Register (MR) Definition

Notes: 1. M16 (BA2) is only applicable for densities >1Gb, reserved for future use, and must be pro-

grammed to “0.”

2. Mode bits (Mn) with corresponding address balls (An) gr ea t er than M12 (A12) ar e re se r v e d

for future use and must be programmed to “0.”

3. Not all listed WR and CL options are supported in any individual speed grade.

Burst Type

Accesse s within a given b urst may be progr ammed to be eithe r sequential or interleaved.

The burst type is selected via bit M3, as shown in Figure 38. The ordering of accesses

within a burst is de te rmined by the burst length, the burs t ty pe, and the starting column

address, as shown in Table 42 on page 78. DDR2 SDRAM supports 4-bit burst mode an d

8-bit burst mode only. For 8-bit burst mode, full interleaved address ordering is

supported; however, sequential address ordering is nibble-based.

Burst Length

CAS#

BT PD

A9 A7 A6 A5 A4 A3 A8 A2 A1 A0

Mode Register (Mx)

Address Bus

9 7 6 5 4 3 8 2 1 0

A10 A12 A11 BA0

BA1

10 11 12 n

Burst Length

Reserved

Burst Type

Sequential

Interleaved

CAS Latency (CL)

Reserved

Mode

Normal

Test

15 DLL TM

DLL Reset

Yes

Write Recovery

Reserved

M10

M11

An2

M16

Mode Register Definition

Mode register (MR)

Extended mode register (EMR)

Extended mode register (EMR2)

Extended mode register (EMR3)

M15

M12

PD Mode

Fast exit

(normal)

Slow exit

(low power)

Latency

BA21

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1Gb: x4, x8, x16 DDR2 SDRAM

Operations

Operating Mode

The normal operating mode is selected by issuing a command with bit M7 set to “0,” and

all other bits set to the desired values, as shown in Figure38 on page 77. When bit M7 is

“1,” no other bits of the mode register are programmed. Programming bit M7 to “1”

places the DDR2 SDRAM into a test mode that is only used by the manufacturer and

should not be used. No operation or functionality is guaranteed if M7 bit is “1.”

DLL RESET

DLL RESET is defined by bit M8, as shown in Figure 38 on page 77. Programming bit M8

to “1” will activate the DLL RESET function. Bit M8 is self-clearing, meaning it returns

back to a value of “0” after the DLL RESET function has been issued.

Anytime the DLL RESET function is used, 200 clock cycles must occur before a READ

command can be issued to allow time for the internal clock to be synchronized with the

external clock. Failing to wait for synchronization to occur may re sult in a violation of

the tAC or tDQSCK parameters.

Write Recovery

Write recovery (WR) time is defined by bits M9–M11, as shown in Figure 38 on page 77.

The WR register is used by the DDR2 SDRAM during WRITE with auto pr echarge opera-

tion. During WRITE with auto precharge operation, the DDR2 SDRAM delays the

internal auto prec harge oper ation b y WR clocks (programmed in bits M9–M11) from the

last data burst. An example of WRITE with auto precharge is shown in Figure 67 on

page 105.

WR values of 2, 3, 4, 5, 6, 7, or 8 clocks may be used for programming bits M9–M11. The

user is required to program the value of WR, which is calculated by dividing tWR (in

nanoseconds) by tCK (in nanoseconds) and rounding up a noninteger value to the next

integer; WR (cycles) = tWR (ns)/tCK (ns). Reserved states should not be used as an

unknown operation or incompatibilit y with future versions may result.

Table 42: Burst Definition

Burst Length

Starting Column

Address

(A2, A1, A0)

Order of Accesses Within a Burst

Burst Type = Sequential Burst Type = Interleaved

4 0 0 0, 1, 2, 3 0, 1, 2, 3

0 1 1, 2, 3, 0 1, 0, 3, 2

1 0 2, 3, 0, 1 2, 3, 0, 1

1 1 3, 0, 1, 2 3, 2, 1, 0

8 0 0 0 0, 1, 2, 3, 4, 5, 6, 7 0, 1, 2, 3, 4, 5, 6, 7

0 0 1 1, 2, 3, 0, 5, 6, 7, 4 1, 0, 3, 2, 5, 4, 7, 6

0 1 0 2, 3, 0, 1, 6, 7, 4, 5 2, 3, 0, 1, 6, 7, 4, 5

0 1 1 3, 0, 1, 2, 7, 4, 5, 6 3, 2, 1, 0, 7, 6, 5, 4

1 0 0 4, 5, 6, 7, 0, 1, 2, 3 4, 5, 6, 7, 0, 1, 2, 3

1 0 1 5, 6, 7, 4, 1, 2, 3, 0 5, 4, 7, 6, 1, 0, 3, 2

1 1 0 6, 7, 4, 5, 2, 3, 0, 1 6, 7, 4, 5, 2, 3, 0, 1

1 1 1 7, 4, 5, 6, 3, 0, 1, 2 7, 6, 5, 4, 3, 2, 1, 0

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1Gb: x4, x8, x16 DDR2 SDRAM

Operations

Power-Down Mode

Active power-down (PD) mode is defined by bit M12, as shown in Figure 38 on page 77.

PD mode allows the user to determine the active power-down mode, which determines

performance versus power savings. PD mode bit M12 does not apply to precharge PD

mode.

When bit M12 = 0, standard active PD mode, or “fast-exit” active PD mode, is enabled.

The tXARD parameter is used for fast-exit active PD exit timing. The DLL is expected to

be enabled and running during this mode.

When bit M12 = 1, a lower-power active PD mode, or “slow-exit” active PD mode, is

enabled. The tXARDS parameter is used for slo w-exit active PD exit timing. The DLL can

be enabled but “frozen” during active PD mode because the exit-to-READ command

timing is r elaxed. The power difference expected between IDD3P normal and IDD3P low-

power mode is defined in Table 11 on page 28.

CAS Latency (CL)

The CAS latency (CL) is defined by bits M4–M6, as shown in Figure38 on page 77. CL is

the delay, in clock cycles, between the registration of a READ command and the avail-

ability of the first bit of output data. The CL can be set to 3, 4, 5, 6, or 7 clocks, depending

on the speed grade option being used.

DDR2 SDRAM does not supp ort any half-clock latenc ie s. Reserved states should not be

used as an unknown operation otherwise incompatibility with future versions may

result.

DDR2 SDRAM also supports a feature called posted CAS additive latency (AL). This

feature allows the READ command to be issued prior to tRCD (MIN) by delaying the

internal command to the DDR2 SDRAM by AL clocks. The AL feature is described in

further detail in “ Posted CAS Additive Latency (AL)” on page83.

Examples of CL = 3 and CL = 4 are shown in Figure39 on page 80; both assume AL = 0. If

a READ command is registered at clock edge n, and the CL is m clocks, the data will be

available nominally coincident with clock edge n + m (this assumes AL = 0).

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1Gb: x4, x8, x16 DDR2 SDRAM

Operations

Figure 39: CAS Latency (CL)

Notes: 1. BL = 4.

2. Posted CAS# additive latency (AL) = 0.

3. Shown with nominal tAC, tDQSCK, and tDQSQ.

Extended Mode Register (EMR)

The extended mode register controls functions beyond those controlled by the mode

r egister; these additional functions ar e DLL enable/disable, output drive strength, on-

die termination (ODT), posted AL, off-chip driver impedance calibration (OCD), DQS#

enable/disable, RDQS/RDQS# enable/disable, and output disable/enable. These func-

tions are contr oll ed via the bits shown in Figure40 on page 81. The EMR is programme d

via the LM command and will retain the stor ed information until it is programmed again

or the device loses power. Reprogramming the EMR will not alter the contents of the

memory array, provided it is per formed correctly.

The EMR must be loaded when all banks are idle and no bursts are in progress, and the

controller mu st w a it the specif ie d time tMRD before initiating any subsequent opera-

tion. Violating either of these requirements could result in an unspecified operation.

n + 3

n + 2

n + 1

CK#

Command

DQS, DQS#

CL = 3 (AL = 0)

READ

T0 T1 T2

Don’t careTransitioning data

NOP NOP NOP

T3 T4 T5

NOP NOP

NOP

n + 3

n + 2

n + 1

CK#

Command

DQS, DQS#

CL = 4 (AL = 0)

READ

T0 T1 T2

NOP NOP NOP

T3 T4 T5

NOP NOP

NOP

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1Gb: x4, x8, x16 DDR2 SDRAM

Operations

Figure 40: Extended Mode Register Definition

Notes: 1. E16 (BA2) is only applicable for densities >1Gb, reserved for future use, and must be pro-

grammed to “0.”

2. Mode bits (En) with corresponding address balls (An) greater than E12 (A12) are reserved

for future use and must be programmed to “0.”

3. Not all listed AL options are supported in any individu al speed grade.

4. As detailed on page 75, during initialization of the ODC operation, all three bits must be set

to “1” for the OCD default state, then set to “0” before in itialization is finished.

DLL Enable/Disable

The DLL may be enabled or disabled by programming bit E0 during the LM command,

as shown in Figure 40. The DLL must be enabled for normal operation. DLL enable is

required during po wer-up initialization and upon returning to normal operation after

having disabled the DLL for the purpose of debugging or ev aluation. Enabling the DLL

should always be followed by resetting the DLL using the LM command.

The DLL is automatically disabled when entering SELF REFRESH operation and is auto-

matically reenabled and reset upon exit of SELF REFRESH operatio n.

Anytime the DLL is enabled (and subsequently reset), 200 clock cycles must occur

before a READ command can be issued to allow time for the internal clock to synchro-

nize with the external clock. Failing to wait for synchronization to occur may result in a

violation of the tAC or tDQSCK parameters.

DLL Posted CAS# R

Out

A9 A7 A6 A5 A4 A3 A8 A2 A1 A0

Extended mode

Address bus

9765438210

A10 A12 A11 BA0 BA1

101112n

Output Drive Strength

Full

Reduced

Posted CAS# Additive Latency (AL)

Reserved

DLL Enable

Enable (normal)

Disable (test/debug)

E11

RDQS Enable

Yes

OCD Program

An2

ODS

DQS#

E10

DQS# Enable

Enable

Disable

RDQS

(Nominal)

disabled

75Ω

150Ω

50Ω

Outputs

Enabled

Disabled

E12

Mode Register Set

Mode register (MR)

Extended mode register (EMR)

Extended mode register (EMR2)

Extended mode register (EMR3)

E15

E14

MRS

BA21

OCD Operation

OCD exit

Reserved

Enable OCD defaults

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1Gb: x4, x8, x16 DDR2 SDRAM

Operations

Output Drive Strength

The output drive strength is defined by bit E1, as shown in Figure40 on page 81. The

normal drive strength for all outputs is specified to be SSTL_18. Programming bit E1 = 0

selects normal (full str ength) drive strength for all outputs. Selecting a reduced drive

strength option (E1 = 1) will reduce all outputs to approximately 45 to 60 percent of the

SSTL_18 drive strength. This option is intended for the support of lighter load and/or

point-to-point environments.

DQS# En able/Disable

The DQS# ball is enabled by bit E10. When E10 = 0, DQS# is the complement of the

differential data strobe pair DQS/DQS#. When disabled (E10 = 1), DQS is used in a

single-ended mode and the DQS# ball is disabled. When disabled, DQS# should be left

floating. This function is also used to enable/disable RDQS#. If RDQS is enabled

(E11 = 1) and DQS# is enabled (E10 = 0), then both DQS# and RDQS# will be enabled.

RDQS Enable/Disable

The RDQS ball is enabled by bit E11, as shown in Figure 40 on page 81. This feature is

only applicable to the x8 configuration. When enabled (E11 = 1), RDQS is identical in

function and timing to data strobe DQS during a READ. During a WRITE operation,

RDQS is ignore d by the DDR2 SDRAM.

Output Enable/Disable

The OUTPUT ENABLE function is defined by bit E12, as shown in Figure 40 on page 81.

When enabled (E12 = 0), all outputs (DQ, DQS, DQS#, RDQS, RDQS#) function normally.

When disabled (E12 = 1), all outputs (DQ, DQS, DQS#, RDQS, RDQS#) are disabled, thus

removing output buffer current. The output disable feature is intende d to be used

during IDD characterization of read curr ent.

On-Die Termination (ODT)

ODT effective resistance, RTT (EFF), is defined by bits E2 and E6 of the EMR, as shown in

Figure 40 on page 81. The ODT feature is designed to improve signal integrity of the

memory channel by allowing the DDR2 SDRAM controller to independently turn on/ o ff

ODT for any or all devices. RTT effective resistance values of 50Ω, 75Ω, and 150Ω are

selectable and apply to each DQ, DQS/DQS#, RDQS/RDQS#, UDQS/UDQS#, LDQS/

LDQS#, DM, and UDM/LDM signals. Bits (E6, E2) determine what ODT resistance is

enabled by turning on/off “sw1 ,” “sw2,” or “sw3.” The ODT effective resistance value is

selected by enabling switch “sw1,” which enables all R1 values that are 150Ω each,

enabling an effective resistance of 75 Ω (RTT2 [EFF] = R2/2). Similarly, if “sw2” is enabled,

all R2 values that are 300Ω each, enable an effective ODT resistance of 150Ω

(RTT2[EFF]= R2/2). Switch “sw3” enables R1 values of 100Ω, enabling effective resi s-

tance of 50Ω. Reserved states should not be used, as an unknown operation or incom-

patibility with future versions may result.

The ODT control ball is used to determine when RTT (EFF) is turned on and off,

assuming ODT ha s be en enabled via bits E2 and E6 of the EMR. The ODT feature and

ODT input ball are only used during activ e, active power-down (both fast-exit and slow-

exit modes), and precharge power-down modes of operation.

ODT must be turned off prio r to entering self r efresh mode. During power-up and

initialization of the DDR2 SDRAM, ODT should be disabled until the EMR command is

issued. This will enable the ODT feature, at which point the ODT ball will determine the

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1Gb: x4, x8, x16 DDR2 SDRAM

Operations

RTT (EFF) value. Anytime the EMR enables the ODT function, ODT may not be driven

HIGH until eight clocks after the EMR has been enabled (see Figure 83 on page 121 for

ODT timing diagrams).

Off-Chip Driver (OCD) Impedance Calibration

The OFF-CHIP DRIVER function is an optional DDR2 JEDEC feature not supported by

Micron and thereby must be set to the default state. Enabling OCD beyond the default

settings will alter the I/O drive characteristics and the timing and output I/O specifica-

tions will no longer be valid (see “Initialization” on page 74 for proper setting of OCD

defaults).

Posted CAS Additive Latency (AL)

Posted CAS additive latency (AL) is supported to make the command and data bus effi-

cient for sustainable bandwidths in DDR2 SDRAM. Bits E3–E5 define the value of AL, as

shown in Figure 40 on page 81. Bits E3–E5 allow the user to program the DDR2 SDRAM

with an AL of 0, 1, 2, 3, 4, 5, or 6 clocks. R eserved states should not be used as an

unknown operation or incompatibilit y with future versions may result.

In this operation, the DDR2 SDRAM allows a READ or WRITE command to be issued

prior to tRCD (MIN) with the requirement that AL ≤ tR CD (MIN). A typical application

using this featur e would set AL = tRCD (MIN) - 1 × tCK. The READ or WRITE command is

held for the time of the AL before it is issued internally to the DDR2 SDRAM device. RL is

controlled by the sum of AL and CL; RL = AL + CL. Write latency (WL) is equal to RL

minus one clock; WL = AL + CL - 1 × tCK. An example of RL is shown in Figure 41 on

page 83 . An example of a WL is shown in Figure42 on page 84.

Figure 41: READ Latency

Notes: 1. BL = 4.

2. Shown with nominal tAC, tDQSCK, and tDQSQ.

3. RL = AL + CL = 5.

n + 3

n + 2

n + 1

CK#

Command

DQS, DQS#

AL = 2

ACTIVE n

T0 T1 T2

Don’t CareTransitioning Data

READ nNOP NOP

T3 T4 T5

NOP

T7 T8

NOP NOP

CL = 3

RL = 5

tRCD (MIN)

NOP

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1Gb: x4, x8, x16 DDR2 SDRAM

Operations

Figure 42: WRITE Latency

Notes: 1. BL = 4.

2. CL = 3.

3. WL = AL + CL - 1 = 4.

Extended Mode Register 2 (EMR2)

The extended mode r e gister 2 (EMR2) controls functions beyond those controlled by the

mode register. Currently all bits in EMR2 are reserved, except for E7, which is used in

commercial or high-tempera ture operations, as shown in Figure43. The EMR2 is

programmed via the LM command and will retain the stored information until it is

programmed again or until the devic e los es power. Repr ogramming the EMR will not

alter the contents of the memory array, provided it is performed correctly.

Bit E7 (A7) must be programmed as “1” to provide a faster refresh rate on IT and AT

devices if TC exceeds 85°C.

EMR2 must be loaded when all banks are idle and no bursts are in progre ss, and the

controller mu st w a it the specif ie d time tMRD before initiating any subsequent opera-

tion. Violating either of these requirements could result in an unspecified operation.

Figure 43: Extended Mode Register 2 (EMR2) Definition

Notes: 1. E16 (BA2) is only applicable for densities >1Gb, reserved for future use, and must be pro-

grammed to “0.”

2. Mode bits (En) with corresponding address balls (An) greater than E12 (A12) are reserved

for future use and must be programmed to “0.”

CK#

Command

DQS, DQS#

ACTIVE n

T0 T1 T2

Don’t CareTransitioning Data

NOP NOP

T3 T4 T5

NOP

n + 3

n + 2

n + 1

WL = AL + CL - 1 = 4

NOP

tRCD (MIN)

NOP

AL = 2 CL - 1 = 2

WRITE n

A9 A7 A6 A5 A4 A3 A8 A2 A1 A0

Extended mode

Address bus

9765438210

A10 A12 A11 BA0 BA1

101112n

1415

An2

E14

Mode Register Set

Mode register (MR)

Extended mode register (EMR)

Extended mode register (EMR2)

Extended mode register (EMR3)

E15

MRS 0 0 0 0 0

SRT 0 0 0 0 0 0 0

BA21

SRT Enable

1X refresh rate (0°C to 85°C)

2X refresh rate (>85°C)

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1Gb: x4, x8, x16 DDR2 SDRAM

Operations

Extended Mode Register 3 (EMR 3)

The extended mode r e gister 3 (EMR3) controls functions beyond those controlled by the

mode register. Currently all bits in EMR3 are re served, as shown in Figur e44 on page 85.

The EMR3 is programmed via the LM command and will retain the stored information

until it is programmed again or until the device loses power. Reprogramming the EMR

will not alter the contents of the memory array, provided it is performed correctly.

EMR3 must be loaded when all banks are idle and no bursts are in progre ss, and the

controller mu st w a it the specif ie d time tMRD before initiating any subsequent opera-

tion. Violating either of these requirements could result in an unspecified operation.

Figure 44: Extended Mode Register 3 (EMR3) Definition

Notes: 1. E16 (BA2) is only applicable for densities >1Gb, is reserved for future use, and must be pro-

grammed to “0.”

2. Mode bits (En) with corresponding address balls (An) greater than E12 (A12) are reserved

for future use and must be programmed to “0.”

ACTIVATE

Before any READ or WRITE commands can be issued to a bank within the DDR2

SDRAM, a row in that bank must be op e ned (activated), even w hen ad ditive latency is

used. This is accomplished via the ACTIVATE command, which selects both the bank

and the row to be activated.

After a ro w is opened with an A CTIVATE command, a READ or WRITE command may be

issued to that row subject to the tRCD speci fication. tRCD (MIN) should be divided by

the clock period and rounded up to the next whole number to determine the earliest

clock edge after the ACTIVATE command on which a READ or WRITE command can be

entered. The same procedure is used to convert other specification limits from time

units to clock cycles. For example, a tRCD (MIN) specification of 20ns with a 266 MHz

clock (tCK = 3.75ns) results in 5.3 clocks, rounded up to 6. This is shown in Figure45 on

page 86, which covers any case where 5 < tRCD (MIN )/tCK ≤ 6. Figure 45 also shows the

case for tRRD where 2 < tRRD (MIN)/tCK ≤ 3.

E14

Mode Register Set

Mode register (MR)

Extended mode register (EMR)

Extended mode register (EMR2)

Extended mode register (EMR3)

E15

A9 A7 A6 A5 A4 A3A8 A2 A1 A0

Extended mode

Address bus

9765438210

A10A12 A11

BA0BA1

101112n

1415

An2

MRS 0 0 0 0 0 0 0 0 0 0 00 0

BA21

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1Gb: x4, x8, x16 DDR2 SDRAM

Operations

Figure 45: Example: Meeting tRRD (MIN) and tRCD (MIN)

A subsequent ACTIVATE command to a different row in the same bank can only be

issued after the previous active row has been closed (precharged). The minimum time

interval between success ive ACTIVATE commands to the same bank is defined by tRC.

A subsequent ACTIVATE command to another bank can be issued while the first bank is

being accessed, which results in a reduction of total row-access overhead. The

minimum time interval betwee n succe ssive ACTIVATE commands to differ ent banks is

defined by tRRD.

DDR2 devices with 8-banks (1Gb or larger) have an additional requirement: tFAW. This

requires no more than four ACTIVATE commands may be issued in any given tFAW

(MIN) period, as shown in Figure 46.

Figure 46: Multi-Bank Activate Restriction

Notes: 1. DDR2-533 (-37E, x4 or x8), tCK = 3.75ns, BL = 4, AL = 3, CL = 4, tRRD (MIN) = 7.5ns,

tFAW (MIN) = 37.5ns.

Command

Don’t Care

T1T0 T2 T3 T4 T5 T6T7

tRRD tRRD

Row Row Col

Bank xBank y

Row

Bank zBank y

NOPACT NOP NOPACT NOP NOP RD/WR

tRCD

CK#

Address

Bank address

T8 T9

NOP NOP

Command

Don’t Care

T1T0 T2 T3 T4 T5 T6 T7

tRRD (MIN)

Row Row

READACT ACT NOP

tFAW (MIN)

Bank address

CK#

Address

T8 T9

Col

Bank a

ACTREAD READ READACT NOP

Row

Col Row

Col Col

Bank c

Bank bBank d

Bank cBank e

ACT

Row

T10

Bank d

Bank bBank a

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1Gb: x4, x8, x16 DDR2 SDRAM

Operations

READ

READ bursts are initiated with a READ command. The starting column and bank

addresses are provided with the READ command, and auto precharge is either enabled

or disabled for that burst access. If auto precharge is enabled, the row being accesse d is

automatically precharged at the completion of the burst. If auto precharge is disabled,

the row will be left open after the completion of the burst.

During READ bursts, the valid data-out element from the starting column address will

be available READ latency (RL) clocks later. RL is defined as the sum of AL and CL:

RL = AL+ CL. The value for AL and CL are programmable via the MR and EMR

commands, respectively. Each subse que nt dat a-out element will be valid nominally at

the next positive or negative clock edge (at the next crossing of CK and CK#). Figur e47

on page 88 shows examples of RL based on different AL and CL settings.

DQS/DQS# is driven by the DDR2 SDRAM along with output data. The initial LOW state

on DQS and the HIGH state on DQS# are known as the read preamble (tRPRE). The L OW

state on DQS and the HIGH state on DQS# coincident with the last data-out element are

known as the read postamble (tRPST).

Upon completion of a burst, assuming no other commands have been initiated, the DQ

will go High-Z. A detailed explanation of tDQSQ (valid data-out skew), tQH (data-out

window hold), and the valid data window are depicted in Figure 56 on page 95 and

Figur e57 on page 96. A detailed explanation of tDQSCK (DQS transition skew to CK) and

tAC (data-out transition skew to CK) is shown in Figure58 on page 97.

Data from any READ burst may be concatenated with data from a subsequent READ

command to provide a continuous flow of data. The first data element from the new

burst follo ws the last element of a completed burst. The new READ command should be

issued x cycles after the first READ command, where x equals BL/2 cycles (see Figure 48

on page 89) .

Nonconsecutive read data is illustrated in Figure 49 on page 90. Full-speed random read

accesses within a page (or pages) can be performed. DDR2 SDRAM supports the use of

concurrent auto precharge timing (see Table 43 on page 93).

DDR2 SDRAM does not allow interrupting or truncating of any READ burst using BL = 4

operations. Once the BL = 4 READ command is registered, it must be allowed to

complete th e entire READ burst. However, a READ (with auto prec harge disabled) using

BL = 8 operation may be interrupted and truncated only by another READ burst as long

as the interruption occurs on a 4-bit boundar y due to the 4n prefetch architecture of

DDR2 SDRAM. As sho wn in Figur e50 on page 90, READ burst BL = 8 operations may not

be interrupted or truncated with any other command except another READ command .

Data from any READ burst must be completed before a subsequent WRITE burst is

allowed. An example of a READ burst followed by a WRITE burst is shown in Figure 51

on page 91. The tDQSS (NOM) case is shown (tDQSS [MIN] and tDQSS [MAX] are

defined in Figure 59 on page 99.)

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1Gb: x4, x8, x16 DDR2 SDRAM

Operations

Figure 47: READ Latency

Notes: 1. DO n = data-out from column n.

2. BL = 4.

3. Three subsequent elements of data-out appear in the programmed order following DO n.

4. Shown with nominal tAC, tDQSCK, and tDQSQ.

READ NOP NOP NOP NOP NOP

Bank a,

Col n

CK#

Command

Address

DQS, DQS#

T0 T1 T2 T3 T4n T5nT4 T5

CK#

Command READ NOP NOP NOP NOP NOP

Address Bank a,

Col nRL = 3 (AL = 0, CL = 3)

DQS, DQS#

T0 T1 T2 T3 T3n T4nT4 T5

CK#

Command READ NOP NOP NOP NOP NOP

Address Bank a,

Col nRL = 4 (AL = 0, CL = 4)

DQS, DQS#

T0 T1 T2 T3 T3n T4nT4 T5

AL = 1 CL = 3

RL = 4 (AL = 1 + CL = 3)

DON’T CARE

Transitioning Data

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1Gb: x4, x8, x16 DDR2 SDRAM

Operations

Figure 48: Consecutive READ Bursts

Notes: 1. DO n (or b) = data-out from column n (or column b).

2. BL = 4.

3. Three subsequent elements of data-out appear in the programmed order following DO n.

4. Three subsequent elements of data-out appear in the programmed order following DO b.

5. Shown with nominal tAC, tDQSCK, and tDQSQ.

6. Example applies only when READ commands are issued to same device.

CK#

Command READ NOP READ NOP NOP NOP NOP

Address Bank,

Col nBank,

Col b

Command READ NOP READ NOP NOP NOP

Address Bank,

Col nBank,

Col b

RL = 3

CK#

DQS, DQS#

RL = 4

DQS, DQS#

nDO

T0 T1 T2 T3 T3n T4nT4 T5 T6

T5n T6n

T0 T1 T2 T3T2n

NOP

T3n T4nT4 T5 T6

T5n T6n

Don’t CareTransitioning Data

tCCD

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1Gb: x4, x8, x16 DDR2 SDRAM

Operations

Figure 49: Nonconsecutive READ Bursts

Notes: 1. DO n (or b) = data-out from column n (or column b).

2. BL = 4.

3. Three subsequent elements of data-out appear in the programmed order following DO n.

4. Three subsequent elements of data-out appear in the programmed order following DO b.

5. Shown with nominal tAC, tDQSCK, and tDQSQ.

6. Example applies when READ commands are issued to different devices or nonconsecutive

READs.

Figure 50: READ Interrupted by READ

Notes: 1. BL = 8 required; auto precharge must be disabled (A10 = LOW).

2. NOP or COMMAND INHIBIT commands are valid. PRECHARGE command cannot be issued to

banks used for READs at T0 and T2.

3. Interrupting READ command must be issued exactly 2 × tCK from previous READ.

4. READ command can be issued to any valid bank and row address (READ command at T0 and

T2 can be either same bank or different bank).

5. Auto precharge can be eithe r ena bled (A10 = HIGH) or disabled (A10 = LOW) by the inter-

rupting READ co mmand.

6. Example shown uses AL = 0; CL = 3, BL = 8, shown with nominal tAC, tDQSCK, and tDQSQ.

Command READ NOP NOP NOP NOP NOP NOP NOPREAD

T0 T1 T2 T3 T3n T4 T5 T7 T8T6T4n T6n T7n

CK#

T5 T7 T8T5n T6T4n T7n

Command NOP NOP NOP NOPREAD NOP NOP NOPREAD

T0 T1 T2 T3 T4

DQ DO

nDO

Don’t CareTransitioning Data

Address Bank,

Col nBank,

Col b

Address Bank,

Col nBank,

Col b

CK#

CL = 4

CL = 3

DQ DO

nDO

DQS, DQS#

T0 T1 T2

Don’t CareTransitioning Data

T3 T4 T5 T6

Command READ

NOP

Valid Valid Valid

READ

Valid Valid Valid

T7 T8 T9

CK#

CL = 3 (AL = 0)

tCCD

Address Valid

Valid

CL = 3 (AL = 0)

DQ DO DO DO DO DO DO DO DO DO DO DO DO

A10 Valid

DQS, DQS#

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1Gb: x4, x8, x16 DDR2 SDRAM

Operations

Figure 51: READ-to-WRITE

Notes: 1. BL = 4; CL = 3; AL = 2.

2. Shown with nominal tAC, tDQSCK, and tDQSQ.

READ with Precharge

A READ burst may be followed by a PRECHARGE command to the same bank, provided

auto precharge is not activated. The minimum READ-to-PRECHARGE command

spacing to the same bank has two requireme nts that must be satisfied: AL + BL/2 clocks

and tRTP. tRTP is the minimum time from the rising cloc k edge that initiates the last 4-

bit prefetch of a READ command to the PRECHARGE command. For BL = 4, this is the

time from the actual READ (AL after the READ command) to PRECHARGE command.

Fo r BL = 8, this is the time from AL + 2 × CK after the READ-to-PRECHARGE command.

Fo llowing the PRECHARGE command, a subsequent command to the same bank

cannot be issued until tRP is met. However, part of the row precharge time is hidden

during the ac ce ss of th e las t data elements.

Examples of READ-to-PRECHAR GE for BL = 4 ar e shown in Figur e 52 and in Figur e53 on

page 92 for BL = 8. The delay from READ-to-PRECHARGE period to the same bank is

AL + BL/2 - 2CK + MAX (tRTP/tCK or 2 × CK) where MAX means the larger of the two.

Figure 52: READ-to-PRECHARGE – BL = 4

Notes: 1. RL = 4 (AL = 1, CL = 3); BL = 4.

2. tRTP ≥ 2 clocks.

3. Shown with nominal tAC, tDQSCK, and tDQSQ.

CK# T0 T1 T2

Don’t careTransitioning data

T3 T4 T5 T6T7 T8 T9 T10 T11

AL = 2 CL = 3

RL = 5

WL = RL - 1 = 4

tRCD = 3

Command

ACT nNOP

NOP NOP NOP

NOP NOP NOP NOP NOP

READ n

NOP NOP NOPWRITE

DQS, DQS#

DQ DO

nDO

n + 1 DO

n + 2 DO

n + 3 DI

nDI

n + 1 DI

n + 2 DI

n + 3

CK#

T0 T1 T2

Don’t CareTransitioning Data

T3 T4 T5 T6 T7

Address Bank aBank aBank a

≥tRAS (MIN)

≥tRTP (MIN)

≥tRP (MIN)

AL + BL/2 - 2CK + MAX (tRTP/tCK or 2CK)

Command READ NOP

PRE

ACT

NOP NOP NOP NOP

4-bit

prefetch

DQ DO DO DO DO

A10 Valid Valid

CL = 3AL = 1

DQS, DQS#

≥tRC (MIN)

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1Gb: x4, x8, x16 DDR2 SDRAM

Operations

Figure 53: READ-to-PRECHARGE – BL = 8

Notes: 1. RL = 4 (AL = 1, CL = 3); BL = 8.

2. tRTP ≥ 2 clocks.

3. Shown with nominal tAC, tDQSCK, and tDQSQ.

READ with Auto Precharge

If A10 is HIGH when a READ command is iss ue d , th e READ with auto precharge func-

tion is engaged. The DDR2 SDRAM starts an auto precharge operation on the rising

clock edge that is AL + (BL/2) cycles late r than the READ with auto precharge command

provided tRAS (MIN) and tRTP are satisfied. If tRAS (MIN) is not satisfied at this rising

clock edge, the start point of the auto precharge operation will be delayed until tRAS

(MIN) is satisfied. If tR TP (MIN) is not satisfied at this rising clock edge , the s tart point of

the auto precharge operation will be delayed until tRTP (MIN) is satisfied. When the

internal precharge is pushed out by tRTP, tRP starts at the point where the internal

precharge happens (not at the next rising clock ed ge after this event).

When BL = 4, the minimum time from READ wi th auto precharge to the next ACTIVATE

command is AL + (tRTP + tRP)/tCK. When BL = 8, the minimum time from READ with

auto precharge to the next ACTIVATE command is AL + 2 clocks + (tRTP + tRP)/tCK. The

term (tRTP + tRP)/tCK is always rounded up to the next integer. A general purpose equa-

tion can also be used: AL + BL/2 - 2CK + (tRTP + tRP)/tCK. In any event, the internal

precharge does not start earlier than two clocks after the last 4-bit prefetch.

READ with auto precharge command may b e applied to one bank while another bank is

operational. This is referred to as concurrent auto precharge operation, as noted in

Table 43 on page 93. Examples of READ with precharge and READ with autoprecharge

with applicable timi ng r equir ements ar e s ho wn in F igur e54 on page 93 and Figure55 on

page 94, respectively.

CK# T0 T1 T2

Don’t CareTransitioning Data

T3 T4 T5 T6 T7 T8

CL = 3AL = 1

DQS, DQS#

First 4-bit

prefetch Second 4-bit

prefetch

≥tRTP (MIN) ≥tRP (MIN)

Address

Bank aBank aBank a

≥tRC (MIN)

≥tRAS (MIN)

A10

Valid Valid

AL + BL/2 - 2CK + MAX (tRTP/tCK or 2CK)

DO DO DO DO DO DO DO DO

Command

READ NOP NOP NOPNOP NOPNOP ACTPRE

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1Gb: x4, x8, x16 DDR2 SDRAM

Operations

Figure 54: Bank Read – Without Auto Precharge

Notes: 1. NOP commands are shown for ease of illustration; other commands may be valid at these

times.

2. BL = 4 and AL = 0 in the case shown.

3. The PRECHARGE command can only be applied at T6 if tRAS (MIN) is met.

4. READ-to-PRECHARGE = AL + BL/2 -2CK + MAX (tRTP/tCK or 2CK).

Table 43: READ Using Concurrent Auto Precharge

From

Command

(Bank n)To Command

(Bank m)Minimum Delay (with

Concurre nt Auto Precharge) Units

READ with

auto

precharge

READ or READ with auto pr echarge BL/2 tCK

WRITE or WRITE with auto precharge (BL/2) + 2 tCK

PRECHARGE or ACTIVATE 1 tCK

CK#

CKE

A10

Bank address

tCK tCH tCL

tRCD

tRAS3

tRC

tRP

CL = 3

T0 T1 T2 T3 T4 T5 T7n T8nT6 T7 T8

DQ8

DQS, DQS#

Case 1: tAC (MIN)

and tDQSCK (MIN)

Case 2: tAC (MAX)

and tDQSCK (MAX)

DQ8

DQS, DQS#

RPRE

tRPRE

tRPST

DQSCK (MIN)

LZ (MIN)

LZ (MAX)

AC (MIN)

LZ (MIN)

HZ (MAX)

AC (MAX)

LZ (MIN)

NOP1

Command ACT

RA Col n

PRE

Bank x

Bank xBank x6

ACT

Bank x

NOP1NOP1NOP1NOP1

HZ (MIN)

One bank

All banks

Don’t CareTransitioning Data

Address

tRTP4

tRPST

DQSCK (MAX)

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1Gb: x4, x8, x16 DDR2 SDRAM

Operations

5. Disable auto precharge.

6. “Don’t Care” if A10 is HIGH at T5.

7. I/O balls, when entering or exitin g High-Z, are not referenced to a specific voltage level, but

to when the device begins to drive or no longer drives, respectively.

8. DO n = data-out from column n; subsequent elements are applied in the programmed

order.

Figure 55: Bank Read – with Auto Precharge

Notes: 1. NOP commands are shown for ease of illustration; other commands may be valid at these

times.

2. BL = 4, RL = 4 (AL = 1, CL = 3) in the case shown.

3. The DDR2 SDRAM internally delays auto precharge until both tRAS (MIN) and tRTP (MIN)

have been satis fied.

4. Enable auto precharge.

4-bit

prefetch

CK#

CKE

A10

Bank address

tCK tCH tCL

tRCD

tRAS

tRC

tRP

CL = 3

T0 T1 T2 T3 T4 T5 T7n T8nT6 T7 T8

DQ6

DQS, DQS#

Case 1: tAC (MIN)

and tDQSCK (MIN)

Case 2: tAC (MAX)

and tDQSCK (MAX)

DQ6

DQS, DQS#

RPRE

tRPRE

tRPST

DQSCK (MIN)

DQSCK (MAX)

LZ (MIN)

LZ (MAX)

AC (MIN)

LZ (MIN)

HZ (MAX)

AC (MAX)

LZ (MAX)

NOP1

Command1

ACT

RA Col n

Bank x

ACT

Bank x

NOP1NOP1NOP1NOP1NOP1

HZ (MIN)

Don’t CareTransitioning Data

Address

AL = 1

tRTP

Internal

precharge

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1Gb: x4, x8, x16 DDR2 SDRAM

Operations

5. I/O balls, when entering or exiting HIGH-Z, are not referenced to a specific voltage level,

but to when the device begins to drive or no longer drives, respectively.

6. DO n = data-out from column n; subsequent elements are applied in the programmed

order.

Figure 56: x4, x8 Data Output Timing – tDQSQ, tQH, and Data Valid Window

Notes: 1. tHP is the lesser of tCL or tCH clock transitions collectively when a bank is active.

2. tDQSQ is derive d at each DQS clock edge, is not cumulative over time, begins with DQS

transitions, and ends with the last valid transition of DQ.

3. DQ transitioning after the DQS transition defines the tDQSQ window. DQS transitions at T2

and at T2n are “early DQS,” at T3 are “nominal DQS,” and at T3n ar e “late DQS.”

4. DQ0, DQ1, DQ2, DQ3 for x4 or DQ0–DQ7 for x8.

5. tQH is derived from tHP: tQH = tHP - tQHS.

6. The data valid window is derived for each DQS transition and is defined as tQH - tDQSQ.

DQ (last data valid)

DQ4

DQS#

DQS3

DQ (last data valid)

DQ (first data no longer valid)

All DQs and DQS collectively6

Earliest signal transition

Latest signal transition

T2n

T3n

CK# T1 T2 T3 T4 T2n T3n

tQH5

tHP1tHP1t

HP1

tQH5

tQHS

tQH5

tHP1tHP1tHP1

tQH5

tDQSQ2t

DQSQ2t

DQSQ2

Data

valid

window

Data

valid

window

Data

valid

window

Data

valid

window

tQHS

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1Gb: x4, x8, x16 DDR2 SDRAM

Operations

Figure 57: x16 Data Output Timing – tDQSQ, tQH, and Data Valid Window

Notes: 1. tHP is the lesser of tCL or tCH clock transitions collectively when a bank is active.

2. tDQSQ is derive d at each DQS clock edge, is not cumulative over time, begins with DQS

transitions, and ends with the last valid transition of DQ.

3. DQ transitioning after the DQS transitions define the tDQSQ window. LDQS defines the

lower byte, and UDQS defines the upper byte.

4. DQ0, DQ1, DQ2, DQ3, DQ4, DQ5, DQ6, or DQ7.

5. tQH is derived from tHP: tQH = tHP - tQHS.

6. The data valid window is derived for each DQS transition and is tQH - tDQSQ.

7. DQ8, DQ9, DQ10, D11, DQ12, DQ13, DQ14, or DQ15.

DQ (last data valid)4

DQ4

LDSQ#

LDQS3

DQ (last data valid)4

DQ (first data no longer valid)4

DQ0–DQ7 and LDQS collectively6T2

T2n

T3n

CK# T1 T2 T3 T4T2n T3n

tQH

tDQSQ

Data valid

window Data valid

window

DQ (last data valid)7

DQ7

UDQS#

UDQS3

DQ (last data valid)7

DQ (first data no longer valid)7

DQ8–DQ15 and UDQS collectively6T2

T2n

T3n

tQH

tDQSQ

tHP

tQH

Data valid

window

Data valid

window Data valid

window

Upper Byte

Lower Byte

Data valid

window

tQHS

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1Gb: x4, x8, x16 DDR2 SDRAM

Operations

Figure 58: Data Output Timing – tAC and tDQSCK

Notes: 1. READ command with CL = 3, AL = 0 issued at T0.

2. tDQSCK is the DQS output window relative to CK and is the long-term component of DQS

skew.

3. DQ transitioning after DQS transitions define tDQSQ window.

4. All DQ must transition by tDQSQ after DQS transitions, regardless of tAC.

5. tAC is the DQ output window relative to CK and is the “long term” component of DQ skew.

6. tLZ (MIN) and tAC (MIN) are the first valid signal transitions.

7. tHZ (MAX) and tAC (MAX) are the latest valid signal transitions.

8. I/O balls, when entering or exitin g High-Z, are not referenced to a specific voltage level, but

to when the device begins to drive or no longer drives, respectively.

WRITE

WRITE bursts are initiated with a WRITE command. DDR2 SDRAM uses WL equal to RL

minus one clock cycle (WL = RL - 1CK) (see “READ” on page 72). The starting column

and bank addresses are provided with the WRITE command, and auto precharge is

either enabled or disabled for that access. If auto precharge is enabled, the row being

accessed is precharged at the completion of the burst.

Note: For the WRITE commands used in the following illustrations, auto precharge is dis-

abled.

During WRITE bursts, the first valid data-in element will be registered on the first rising

edge of DQS following the WRITE command, and subsequent data elements will be

registered on successive edges of DQS. The LOW state on DQS between the WRITE

command and the first rising edge is known as the write preamble; the LOW state on

DQS following the last data-in element is known as the write postamble.

The time between the WRITE command and the first rising DQS edg e is WL ±tDQSS.

S ubsequent D QS positi v e rising edges are timed, relativ e to the ass ociated cloc k ed ge, as

±tDQSS. tDQSS is specified with a r elatively wide range (25 percent of one clock cycle).

All of the WRITE diagrams show the nominal case, and where the two extreme cases

(tDQSS [MIN] and tDQSS [MAX]) might not be intuitive, they have also been included.

Figure 59 on page 99 shows the nominal case and the extremes of tDQSS for BL = 4.

Upon completion of a burst, assuming no other commands have been initiated, the DQ

will remain High-Z and any additional input data wil l be ign ored.

CK#

DQS#/DQS or

LDQS#/LDQS/UDQ#/UDQS3

T01T1 T2 T3 T3n T4 T4n T5 T5n T6 T6n T7

tRPST

tDQSCK2 (MIN) tDQSCK2 (MAX)

DQ (last data valid)

DQ (first data valid)

All DQs collectively4

tAC5 (MIN) tAC5 (MAX)

tLZ (MIN) tHZ (MAX)

T3n T4n T5n T6n

T3n

T4n

T5n

T6n

T3 T4 T5 T6

tHZ (MAX)

tLZ (MIN) tRPRE

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1Gb: x4, x8, x16 DDR2 SDRAM

Operations

Data for any WRITE burst may be concatenated with a subsequent WRITE command to

provide continuous flow of input data. The first data elem ent from the new burst is

applied after the last element of a completed burst. The new WRITE command should

be issued x cycles after the first WRITE command, where x equals BL/2.

Figure 60 on page 100 shows concatenated bursts of BL = 4. An example of nonconsecu-

tive WRITEs is shown in F igure61 on page 100. Full-speed random write accesses within

a page or pages can be performed as shown in Figure 62 on page 101. DDR2 SDRAM

supports concurrent auto precharge options, as shown in Table 44 on page 98.

DDR2 SDRAM does not allow interrupting or truncating any WRITE burst using BL = 4

operation. Once the BL = 4 WRITE command is registered, it must be al lo wed to

complete th e ent ire WRITE burst cycle. However, a WRITE BL = 8 operation (with auto

precharge disabled) might be interrupted and truncated only by another WRITE burst as

long as the interruption occurs on a 4-bit boundary due to the 4n-prefetch architecture

of DDR2 SDRAM. WRITE burst BL = 8 operations may not be interrupted or truncated

with any command except another WRITE command, as shown in Figure 63 on

page 101.

Data for any WRITE burst may be followed by a subsequent READ command. To follow

a WRITE, tW TR should be met, as shown in Figure64 on page 102. The number of clock

cycles required to meet tWTR is either 2 or tWTR/tCK, whichever is greater. Data for any

WRITE burst may be followed by a subsequent PRECHARGE command. tWR must be

met, as shown in Figure 65 on page 103. tWR start s at the end of the data burst, regard-

less of the data mask condition.

Table 44: WRITE Using Concurrent Auto Precharge

From Command

(Bank n)To Command

(Bank m)Minimum Delay

(with Concurrent Auto Precharge) Units

WRITE with auto

precharge READ or READ with auto precharge (CL - 1) + (BL/2) + tWTR tCK

WRITE or WRITE with auto

precharge (BL/2) tCK

PRECHARGE or ACTIVATE 1 tCK

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1Gb: x4, x8, x16 DDR2 SDRAM

Operations

Figure 59: WRITE Burst

Notes: 1. Subsequent rising DQS signals must align to the clock within tDQSS.

2. DI b = data-in for column b.

3. Three subsequent elements of data-in are applied in the programmed order following DI b.

4. Shown with BL = 4, AL = 0, CL = 3; thus, WL = 2.

5. A10 is LOW with the WRITE command (auto precharge is disabled).

DQS, DQS#

tDQSS (MAX)

tDQSS (NOM)

tDQSS (MIN)

CK#

Command

WRITE NOP NOP

Address

Bank a,

Col b

NOP NOP

T0 T1 T2 T3T2n T4T3n

DQS, DQS#

Don’t CareTransitioning Data

tDQSS5

WL ± tDQSS

WL - tDQSS tDQSS5

WL + tDQSS

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1Gb: x4, x8, x16 DDR2 SDRAM

Operations

Figure 60: Consecutive WRITE-to-WRITE

Notes: 1. Subsequent rising DQS signals must align to the clock within tDQSS.

2. DI b, etc. = data-in for column b, et c.

3. Three subsequent elements of data-in are applied in the programmed order following DI b.

4. Three subsequent elements of data-in are applied in the programmed order following DI n.

5. Shown with BL = 4, AL = 0, CL = 3; thus, WL = 2.

6. Each WRITE command may be to any ba nk.

Figure 61: Nonconsecutive WRITE-to-WRITE

Notes: 1. Subsequent rising DQS signals must align to the clock within tDQSS.

2. DI b (or n), etc. = data-i n fo r column b (or column n).

3. Three subsequent elements of data-in are applied in the programmed order following DI b.

4. Three subsequent elements of data-in are applied in the programmed order following DI n.

5. Shown with BL = 4, AL = 0, CL = 3; thus, WL = 2.

6. Each WRITE command may be to any ba nk.

CK#

Command

WRITE NOP WRITE NOP NOP NOP

Address

Bank,

Col b

NOP

Bank,

Col n

T0 T1 T2 T3 T2n T4 T5 T4n T6 T5n T3n T1n

DQS, DQS#

Don’t CareTransitioning Data

WL ± tDQSS

tDQSS (NOM)

WL = 2

tCCD

WL = 2

CK#

Command

WRITE NOP NOP NOP NOP NOP

Address

Bank,

Col b

WRITE

Bank,

Col n

T1 T

n T4 T5 T4n T

n T5n T

DQS, DQS#

tDQSS (NOM) WL ± tDQSS

Don’t CareTransitioning Data

WL = 2 WL = 2

111

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1Gb: x4, x8, x16 DDR2 SDRAM

Operations

Figure 62: Random WRITE Cycles

Notes: 1. Subsequent rising DQS signals must align to the clock within tDQSS.

2. DI b (or n), etc. = data-i n fo r column b (or column n).

3. Three subsequent elements of data-in are applied in the programmed order following DI b.

4. Three subsequent elements of data-in are applied in the programmed order following DI n.

5. Shown with BL = 4, AL = 0, CL = 3; thus, WL = 2.

6. Each WRITE command may be to any ba nk.

Figure 63: WRITE Interrupted by WRITE

Notes: 1. BL = 8 required and auto precharg e must be disabled (A10 = LOW).

2. The NOP or COMMAND INHIBIT commands are valid. The PRECHARGE command cannot be

issued to banks used for WRITEs at T0 and T2.

3. The interrupting WRITE command must be issued exactly 2 × tCK from previous WRITE.

4. The earliest WRITE-to-PRECHARGE timing for WRITE at T0 is WL + BL/2 + tWR where tWR

starts with T7 and not T5 (because BL = 8 fr om MR and not the truncated length).

5. The WRITE command can be issued to any valid bank and row address (WRITE command at

T0 and T2 can be either same bank or different bank).

6. Auto precharge can be eithe r ena bled (A10 = HIGH) or disabled (A10 = LOW) by the inter-

rupting WRITE command.

7. Subsequent rising DQS signals must align to the clock within tDQSS.

8. Example shown uses AL = 0; CL = 4, BL = 8.

CK#

Command

WRITE NOP WRITE NOP NOP NOP

Address

Bank,

Col b

NOP

Bank,

Col n

T0 T1 T2 T3 T2n T4 T5 T4n T6 T5n T3n T1n

DQS, DQS#

Don’t CareTransitioning Data

WL ± tDQSS

tDQSS (NOM)

WL = 2

tCCD

WL = 2

CK#

Command

DQS, DQS#

WL = 3

WRITE1 a

T0 T1 T2

Don’t CareTransitioning Data

T3 T4 T5 T6

WRITE3 b

T7 T8 T9

WL = 32-clock requirement

Address

A10

Valid6

Valid5Valid5

Valid4Valid4

Valid

NOP2

7 7777

a + 1 DI

a + 3

a + 2 DI

b + 1 DI

b + 2 DI

b + 3 DI

b + 4 DI

b + 5 DI

b + 6 DI

b + 7

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1Gb: x4, x8, x16 DDR2 SDRAM

Operations

Figure 64: WRITE-to-READ

Notes: 1. tWTR is required for any R EAD following a WRITE to the same device, bu t it is no t r equired

between module ranks.

2. Subsequent rising DQS signals must align to the clock within tDQSS.

3. DI b = data-in for column b; DO n = data-out from column n.

4. BL = 4, AL = 0, CL = 3; thus, WL = 2.

5. One subsequent element of data-in is applied in the programmed order following DI b.

6. tWTR is referenced from the first positive CK edge after the last data-in pair.

7. A10 is LOW with the WRITE command (auto precharge is disabled).

8. The number of clock cycles required to meet tWTR is either 2 or tWTR/tCK, whichever is

greater.

tDQSS (NOM)

CK#

Command

WRITE NOP NOP NOP NOP NOP NOP NOP

Address

Bank a,

Col b Bank a,

Col n

READ

T0 T1 T2 T3T2n T4 T5 T9nT3n T6 T7 T8 T9

tWTR1

CL = 3

DQS, DQS#

tDQSS (MIN)

DQS, DQS#

tDQSS (MAX)

DQS, DQS#

bDI

Don’t CareTransitioning Data

WL ± tDQSS

WL - tDQSS

WL + tDQSS

NOP

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1Gb: x4, x8, x16 DDR2 SDRAM

Operations

Figure 65: WRITE-to-PRECHARGE

Notes: 1. Subsequent rising DQS signals must align to the clock within tDQSS.

2. DI b = data-in for column b.

3. Three subsequent elements of data-in are applied in the programmed order following DI b.

4. BL = 4, CL = 3, AL = 0; thus, WL = 2.

5. tWR is referenced from the first positive CK edge after the last data-in pair.

6. The PRECHARGE and WRITE com mands are to the same bank. However, the PRECHARGE

and WRITE commands may be to different banks, in which case tWR is not required and the

PRECHARGE command could be applied earlier.

7. A10 is LOW with the WRITE command (auto precharge is disabled).

tDQSS (NOM)

CK#

Command

WRITE NOP NOP NOP NOPNOP

Address

Bank a,

Col bBank,

(a or all)

NOP

T0 T1 T2 T3T2n T4 T5T3n T6 T7

tWR tRP

DQS#

DQS

tDQSS (MIN)

DQS#

DQS

tDQSS (MAX)

DQS#

DQS

Don’t CareTransitioning Data

WL + tDQSS

WL - tDQSS

WL + tDQSS

PRE

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1Gb: x4, x8, x16 DDR2 SDRAM

Operations

Figure 66: Bank Write – Without Auto Precharge

Notes: 1. NOP commands are shown for ease of illustration; other commands may be valid at these

times.

2. BL = 4 and AL = 0 in the case shown.

3. Disable auto precharge.

4. “Don’t Care” if A10 is HIGH at T9.

5. Subsequent rising DQS signals must align to the clock within tDQSS.

6. DI n = data-in for column n; subsequent elements are applied in the programmed order.

7. tDSH is applicable during tDQSS (MIN) and is referenced from CK T5 or T6.

8. tDSS is applicable during tDQSS (MAX) and is referenced from CK T6 or T7.

CK#

CKE

A10

tCK tCH tCL

tRCD tRAS tRP

tWR

T0 T1 T2 T3 T5 T6 T6n T7 T8 T9T5n

NOP1

Command

ACT

RA Col n

WRITE2NOP1

One bank

All banks

Bank x

PRE

Bank x

NOP1NOP1NOP1

tDQSL tDQSH tWPST

Bank x4

DQ6

Don’t CareTransitioning Data

WL ± tDQSS (NOM)

tWPRE

DQS, DQS#

Address

NOP1

WL = 2

Bank select

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1Gb: x4, x8, x16 DDR2 SDRAM

Operations

Figure 67: Bank Write – with Auto Precharge

Notes: 1. NOP commands are shown for ease of illustration; other commands may be valid at these

times.

2. BL = 4 and AL = 0 in the case shown.

3. Enable auto precharge.

4. WR is programmed via MR9–MR11 and is calculated by dividing tWR (in ns) by tCK and

rounding up to the next integer value.

5. Subsequent rising DQS signals must align to the clock within tDQSS.

6. DI n = data-in from column n; subsequent elements are applied in the programmed order.

7. tDSH is applicable during tDQSS (MIN) and is referenced from CK T5 or T6.

8. tDSS is applicable during tDQSS (MAX) and is referenced from CK T6 or T7.

CK#

CKE

A10

Bank select

tCK tCH t

tRCD tRAS tRP

T0 T1 T2 T3 T4 T5 T5n T6 T7 T8 T6n

NOP1

Command

ACT

RA Col n

WRITE2NOP1

Bank x

NOP1

Bank x

NOP1NOP1NOP1

tDQSL tDQSH tWPST

DQ6

WL ±tDQSS (NOM)

Don’t Care

Transitioning Data

tWPRE

DQS, DQS#

Address

NOP1

WL = 2

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1Gb: x4, x8, x16 DDR2 SDRAM

Operations

Figure 68: WRITE – DM Operation

Notes: 1. NOP commands are shown for ease of illustration; other commands may be valid at these

times.

2. BL = 4, AL = 1, and WL = 2 in the case shown.

3. Disable auto precharge.

4. “Don’t Care” if A10 is HIGH at T11.

5. tWR starts at the end of the data burst regardless of the da ta mask condition.

6. Subsequent rising DQS signals must align to the clock within tDQSS.

7. DI n = data-in for column n; subsequent elements are applied in the programmed order.

8. tDSH is applicable during tDQSS (MIN) and is referenced from CK T6 or T7.

9. tDSS is applicable during tDQSS (MAX) and is referenced from CK T7 or T8.

CK#

CKE

A10

Bank select

RCD

RAS tRPA

tWR5

T0 T1 T2 T3 T4 T5 T7n T6 T7 T8 T6n

NOP1

Command

ACT

RA Col n

WRITE2

NOP1

One bank

All banks

Bank x Bank x

NOP1NOP1NOP1NOP1NOP1NOP1

tDQSL tDQSH

tWPST

Bank x4

DQ7

Don’t CareTransitioning Data

WL ±

DQSS (NOM)

tWPRE

PRE

DQS, DQS#

Address

T9 T10 T11

AL = 1 WL = 2

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1Gb: x4, x8, x16 DDR2 SDRAM

Operations

Figure 69: Data Input Timing

Notes: 1. tDSH (MIN) generally occurs dur in g tDQSS (MIN).

2. tDSS (MIN) gener a lly occurs during tDQSS (MAX).

3. Subsequent rising DQS signals must align to the clock within tDQSS.

4. WRITE command issued at T0.

5. For x16, LDQS controls the lower byte and UDQS controls the upper byte.

6. WRITE command with WL = 2 (CL = 3, AL = 0) issued at T0.

PRECHARGE

PRECHARGE can be initiated by either a manual PRECHARGE command or by an auto-

precharge in conjunction with either a READ or WRITE comman d. PRECHARGE will

deactivate the open row in a particular bank or the open row in all banks. The

PRECHAR GE operation is shown in the previous READ and WRITE operation sections.

During a manual PRECHARGE command, the A10 input determines whether one or all

banks are to be precharged. In the case where only one bank is to be precharged, bank

address inputs determine the bank to be precharged. When all banks are to be

precharged, the bank address inputs are treated as “Don’t Care.”

Once a bank has been precharged, it is in the idle state and must be activated prior to

any READ or WRITE commands being issued to that bank. When a single-bank

PRECHARGE command is issued, tRP timing applies. When the PRECHARGE (ALL)

command is issued, tRPA timing applies, regardless of the number of banks opened.

DQS

DQS# tDQSH tWPST

tDQSL

tDSS 2tDSH 1

tDSH 1tDSS 2

CK# T1T0 T1n T2 T2n T3 T4T3n

Don’t CareTransitioning Data

WPRE

WL - tDQSS (NOM)

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1Gb: x4, x8, x16 DDR2 SDRAM

Operations

REFRESH

The commercial temperature DDR2 SDRAM requires REFRESH cycles at an average

interval of 7.8125µs (MAX) and all ro ws in all banks must be r efr eshed at least once every

64ms. The refresh period begins when the REFRESH command is registered and ends

tRFC (MIN) later. The average interval must be r educed to 3.9µs (MAX) when TC exceeds

+85°C.

Figure 70: Refresh Mode

Notes: 1. NOP commands are shown for ease of illustration; other valid commands may be possible at

these times. CKE must be active during clock positive transitions.

2. The second REFRESH is not required and is only shown as an example of two back-to - back

REFRESH commands.

3. “Don’t Care” if A10 is HIGH at this point; A10 must be HIGH if more than one bank is active

(must precharge all active banks).

4. DM, DQ, and DQS signals are all “Don’t Care”/High-Z for operations shown.

CK#

Command

NOP1

NOP1NOP1

PRE

CKE

Address

A10

Bank

Bank(s)

REF NOP1REF2NOP1ACT

NOP1

One bank

All banks

tCK tCH tCL

DQ4

DM4

DQS, DQS#4

tRFC2

tRP tRFC (MIN)

T0 T1 T2 T3 T4 Ta0 Tb0

Ta1 Tb1 Tb2

Don’t Care

Indicates a break in

time scale

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1Gb: x4, x8, x16 DDR2 SDRAM

Operations

SELF REFRESH

The SELF REFRESH command is initiated with CKE is LOW. The differential clock

should remain stable and meet tCKE specifications at least 1 × tCK after entering self

refresh mode. The procedure for exiting self refresh requires a sequence of commands.

First, the differential clock must be stable and meet tCK specifications at least 1 × tCK

prior to CKE going back to HIGH. Once CKE is HIGH (tCKE [MIN] has been satisfied with

three clock registrations), the DDR2 SDRA M must have NOP or DESELECT commands

issued for tXSNR. A simple algorithm for meeting both refresh and DLL requirements is

to apply NOP or DESELECT commands for 200 clock cycles befor e appl ying any other

command.

Figure 71: Self Refresh

Notes: 1. Clock must be stable and meeting tCK specifications at least 1 × tCK after entering self

refresh mode and at least 1 × tCK prior to exiting self refresh mode.

2. Self refresh exit is asynchronous; however, tXSNR and tXSRD timing starts at the first rising

clock edge where CKE HIGH satisfies tISXR.

3. CKE must stay HIGH until tXSRD is met; however, if self refresh is being reentered, CKE may

go back LOW after tXSNR is satisfied.

4. NOP or DESELECT commands are required prior to exiting self refresh until state Tc0, which

allows any nonREAD command.

5. tXSNR is required before any nonREAD command can be applied.

6. ODT must be disabled and RTT of f (tAOFD and tAOFPD have been satisfied) prior to entering

self refresh at state T1.

7. tXSRD (200 cycles of CK) is required before a READ command can be applied at state Td0.

8. Device must be in the all banks idle state prior to entering self refresh mode.

9. After self refres h has been entered, tCKE (MIN) must be satisfied prior to exiting self

refresh.

10. Upon exiting SELF REFRESH, ODT must remain LOW until tXSRD is satisfied.

CK1

CK#

Command

NOP REF

Address

CKE1

Valid

DQS#, DQS

NOP4

tRP

tCHtCLtCK

tCK

tXSNR

2, 5, 10

tISXR

Enter self refresh

mode (synchronous) Exit self refresh

mode (asynchronous)

T0 T1 Ta2Ta1

Don’t Care

Ta0 Tc0Tb0

tXSRD2,

Valid5

NOP4

tCKE (MIN)

ODT6

tAOFD/tAOFPD

Td0

Valid7

Valid5

Indicates a break in

time scale

tIH

tCKE3

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1Gb: x4, x8, x16 DDR2 SDRAM

Operations

Power-Down Mode

DDR2 SDRAMs support multiple power-down modes that allow significant power

savings over normal operating modes. CKE is used to enter and exit different po wer-

down modes. Power-down entry and exit timings are shown in Figure 72 on page 111.

Detailed power-down entry conditions are shown in Figure s73–80. The CKE Truth

Table, Table 45, is shown on page112.

DDR2 SDRAMs require CKE to be registered HIGH (active) at all times that an access is

in progress—from the issuing of a READ or WRITE command until completion of the

burst. Thus, a clock suspend is not supported. For READs, a burst completion is defined

when the re ad postamble is satisfied; for WRITEs, a burst completion is defined when

the write postamble and tWR (WRITE-to-PRECHARGE command) or tWTR (WRITE-to-

READ command) are satisfied, as shown in Figures75 and 76 on page 114. The number

of clock cycles required to meet tWTR is either two or tWTR/tCK, whichever is greater.

Power-down mode (see Figure72 on page 111) is entered when CKE is registered LOW

coincident with a NOP or DESELECT command. CKE is not allowed to go LOW during a

mode register or extend ed mode register command time, or while a READ or WRITE

operation is in progress. If power-down occurs when all banks are idle, this mode is

referred to as precharge power-down. If power-down occurs when there is a row active

in any bank, this mode is referred to as active power-down. Entering power-down deac-

tivates the input and output buffers, excluding CK, CK#, ODT, and CKE. For maximum

power savings, the DLL is frozen during precharge power-down. Exiting active power-

down re quires the device to be at the same voltage and frequency as when it entered

power-down. Exiting precharge power-down requires the device to be at the same

voltage as when it entered power-down; however, the clock frequency is allowed to

change (see “Precharge Power-Down Clock Frequency Change” on page 116).

The maximum duration for either active or precharge power-do wn is limited by the

refr esh r equir ements of the device tRFC (MAX). The minimum dura tion for power-down

entry and exit is limited by the tCKE (MIN) parameter. The follo wing must be main-

tained while in power-down mode: CKE LOW, a stable clock signal, and stable power

supply signals at the inputs of the DDR2 SDRAM. All other input signals ar e “ Don’t Car e”

except ODT. Detailed ODT timing diagrams for different po wer-down modes are shown

in Figure 83 on page 1 21– Figure 90 on page 125.

The power-down state is synchronously exited when CKE is registered HIGH (in

conjunction with a NOP or DESELECT command), as shown in Figure 72 on page 111.

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1Gb: x4, x8, x16 DDR2 SDRAM

Operations

Figure 72: Power-Down

Notes: 1. If this command is a PRECHARGE (or if the device is already in the idle state), then the

power-down mode shown is precharge power-down. If this command is an ACTIVATE (or if

at least one row is already active), then the power-down mode shown is active power-

down.

2. tCKE (MIN) of three clocks means CKE must be registered on three consecutive positive clock

edges. CKE must remain at the valid input level the entire time it takes to achieve the three

clocks of registration. Thus, after any CKE transition, CKE may not transition from its valid

level during the time period of tIS + 2 × tCK + tIH. CKE must not transition during its tIS and

tIH window.

3. tXP timing is used for exit precharge power-down and active power -d own to any nonR EAD

command.

4. tXARD timing is used for exit active power-down to READ command if fast exit is selected

via MR (bit 12 = 0).

5. tXARDS timing is used for exit active power-down to READ command if slow exit is selected

via MR (bit 12 = 1).

6. No column accesses are allowed to be in progress at the time power-down is entered. If the

DLL was not in a locked state when CKE went LOW, the DLL must be reset after exiting

power-do wn mode for proper READ operation.

CK#

Command

NOP NOP NOP

Address

CKE

DQS, DQS#

Valid

tCH tCL

Enter

power-down

mode6

Exit

power-down

mode Don’t Care

tCKE (MIN)2

tCKE (MIN)

Valid

Valid1

Valid

tXP3, tXARD4

tXARDS5

Valid Valid

tIS

tIH

T1 T2 T3 T4 T5 T6 T7 T8

tCK

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1Gb: x4, x8, x16 DDR2 SDRAM

Operations

Notes: 1. CKE (n) is the logic state of CKE at clock edge n; CKE (n - 1) was the state of CKE at the pre-

vious clock edge.

2. Current state is the state of the DDR2 SDRAM immediately prior to clock edge n.

3. Command (n) is the command registered at clock edge n, and action (n) is a result of com-

mand (n).

4. The state of ODT does not affect the states described in this table. The ODT function is not

available during self refresh (see “ODT Timing” on page 120 for more details and specific

restrictions).

5. Power-down modes do not perform any REFRESH operations. The duration of power-down

mode is therefore limited by the refresh requirements.

6. “X” means “Don’t Care” (including floating around VREF) in self refresh and power- down.

However, ODT must be driven HIGH or LOW in power-down if the ODT function is enabled

via EMR.

7. All state s an d se quences no t shown are ille ga l or reserved unless explicitly described else-

where in this document.

8. Va lid commands for power-down entry and exit are NOP and DESELECT only.

9. On self refresh exit, DESE LECT or NOP commands must be issued on every clock edge occur-

ring during the tXSNR per iod. READ commands may be issued only aft er tXSRD (200 clock s)

is satisfied.

10. Valid commands for self refresh exit are NOP and DESELECT only.

11. Power-down and self refresh can not be entered while READ or WRITE operations, LOAD

MODE operations, or PRECHARGE operations are in progress. See “SELF REFRESH” on

page 109 and “SELF REFRESH” on page 73 for a list of detaile d restrictions.

12. Minimum CKE HIGH time is tCKE = 3 × tCK. Minimum CKE LOW time is tCKE = 3 × tCK. This

requires a minimum of 3 clock cycles of registration.

13. Self refresh mode can only be entered from the all banks idle state.

14. Must be a legal command, as defined in Table 38 on page 67.

Table 45: Truth Table – CKE

Notes 1–4 apply to the entire table

Current State

CKE

Command (n) CS#,

RAS#, CAS#, WE# Action (n)Notes

Cycle

(n - 1) Current

Cycle (n)

Power-down L L X Maintain power-do wn 5, 6

L H DESELECT or NOP Power-down exit 7, 8

Self refresh L L X Maintain self refresh 6

L H DESELECT or NOP Self refresh exit 7, 9, 10

Bank(s) active H L DESELECT or NOP Active power-down entry 7, 8, 11, 12

All banks idle H L DESELECT or NOP Precharge power-down entry 7, 8, 11

H L REFRESH Self refresh entry 10, 12, 13

H H Sh own in Tab le 38 on page 67 14

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1Gb: x4, x8, x16 DDR2 SDRAM

Operations

Figure 73: READ-to-Power-Down or Self Refresh Entry

Notes: 1. In the exampl e s hown, READ burst completes at T5; earliest power-down or self refresh

entry is at T6.

2. Power-down or self refresh entry may occur after the READ burst completes.

Figure 74: READ with Auto Precharge-to-Power-Down or Self Refresh Entry

Notes: 1. In the exampl e s hown, READ burst completes at T5; earliest power-down or self refresh

entry is at T6.

2. Power-down or self refresh entry may occur after the READ burst completes.

CK#

Command

DQS, DQS#

RL = 3

T0 T1 T2

Don’t CareTransitioning Data

NOP NOP

T3 T4 T5

Valid

T6 T7

tCKE (MIN)

Address

A10

NOP

CKE

READ

Valid

Power-down

self refresh entry

NOP1

Valid

DODO DO

CK#

Command

DQS, DQS#

RL = 3

T0 T1 T2

Don’t CareTransitioning Data

NOP NOP

T3 T4 T5

Valid Valid

T6 T7

tCKE (MIN)

Address

A10

NOP

CKE

READ

Valid

Power-down or

self refresh

entry

NOP1

DO DODO DO

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1Gb: x4, x8, x16 DDR2 SDRAM

Operations

Figure 75: WRITE-to-Power-Down or Self-Refresh Entry

Notes: 1. Power-down or self refresh entry may occur after the WRITE burst completes.

Figure 76: WRITE with Auto Precharge-to-Power-Down or Self Refresh Entry

Notes: 1. Internal PRECHARGE occurs at Ta0 when WR has completed; power-down entry may occur

1xtCK later at Ta1, prior to tRP being satisfied.

2. WR is programmed through MR9–MR11 and represents (tWR [MIN]ns/tCK) rounded up to

next integer tCK.

CK#

Command

DQS, DQS#

WL = 3

T1 T

Don’t CareTransitioning Data

NOP NOP

T4 T5

Valid Valid

Valid

T7 T

tCKE (MIN)

Address

A10

NOP

WRITE

Valid

Power-down or

self refresh entry1

tWTR

NOP

DO DO DO

CKE

CK#

Command

DQS, DQS#

WL = 3

T1 T

Don’t CareTransitioning Data

NOP NOP

T4 T5

Valid Valid

Valid1NOP

Ta1 Ta

tCKE (MIN)

Address

A10

NOP

CKE

WRITE

Valid

Power-down or

self refresh entry

WR2

DO DO DO

Indicates a break in

time scale

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1Gb: x4, x8, x16 DDR2 SDRAM

Operations

Figure 77: REFRESH Command-to-Power-Down Entry

Notes: 1. The earliest precharge power-down entry may occur is at T2, which is 1 × tCK after the

REFRESH command. Precharge power-down entry occurs prior to tRFC (MIN) being satisfied.

Figure 78: ACTIVATE Command-to-Power-Down Entry

Notes: 1. The earliest active power-down entry may occur is at T2, which is 1 × tCK after the ACTI-

VATE command. Active power-down entry occurs prior to tRCD (MIN) being satisfied.

CK#

Command

Don’t Care

T0 T1

Valid

REFRESH

T2 T3

tCKE (MIN)

CKE

Power-down1

entry

1 x tCK

NOP

CK#

Command

Don’t Care

T0 T1

Valid ACT

NOP

tCKE (MIN)

CKE

Power-down1

entry

1 tCK

Address

VALID

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1Gb: x4, x8, x16 DDR2 SDRAM

Operations

Figure 79: PRECHARGE Command-to-Power-Down Entry

Notes: 1. The earliest precharge power-down entry may occur is at T2, which is 1 × tCK after the PRE-

CHARGE command. Precharge power-down entry occu rs prior to tRP (MIN) being satisfied.

Figure 80: LOAD MODE Command-to-Power-Down Entry

Notes: 1. Valid address for LM command includes MR, EMR, EMR(2), and EMR(3) registers.

2. All banks must be in the precharged state and tRP met prior to issuing LM command.

3. The earliest precharge power-down entry is at T3, which is after tMRD is satisfied.

Precharge Power-Down Clock Frequency Change

When the DDR2 SDRAM is in precharge power-down mode, ODT must be turned off

and CKE must be at a logic LOW level. A minimum of two differential clock cycles must

pass after CKE goes LOW before clock frequency may change. The device input clock

frequency is allowed to change only within minimum and maximum operating frequen-

cies specified for the particular speed grade. During input clock frequency change, ODT

and CKE must be held at stable LOW levels. When the in put clock frequency is changed,

CK#

Command

Don’t Care

T0 T1

Valid

PRE

NOP

CKE (MIN)

CKE

Power-down1

entry

1 x

Address

A10

Valid

All banks

Single bank

CK#

Command

Don’t Care

T0 T1

Valid LM

NOP

T3 T4

tCKE (MIN)

CKE

Power-down

entry

tMRD

Address

Valid1

tRP

NOP

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1Gb: x4, x8, x16 DDR2 SDRAM

Operations

new stable clocks must be provided to the device before precharge power-down may be

exited, and DLL must be reset via MR after precharge power-down exit. Depending on

the new clock frequency, addi ti onal LM commands might be required to adjust the CL,

WR, AL, and so forth. settings to account for the frequency change. Depending on the

new clock frequency, an additional LM command might be requir ed to appropriately set

the WR MR9, MR10, MR11. During the DLL relock period of 200 cycles, ODT must

remain off. After the DLL lock time, the DRAM is ready to operate with a new clock

frequency.

Figure 81: Input Clock Frequency Change During Precharge Power-Down Mode

Notes: 1. A minimum of 2 × tCK is required after entering precharge power-down prior to changing

clock frequencies.

2. When the new clock frequency has changed and is stable, a minimum of 1 × tCK is required

prior to exiting precharge power-down.

3. Minimum CKE HIGH time is tCKE = 3 × tCK. Minimum CKE LOW time is tCKE = 3 × tCK. This

requires a minimum of three clock cycles of registration.

4. If this command is a PRECHARGE (or if the device is already in the idle state), then the

power-down mode shown is precharge power-down, which is required prior to the clock

frequency chang e.

CK#

Command

Valid4NOP

Address

CKE

DQS, DQS#

NOP

tCK

Enter precharge

power-down mode Exit precharge

power-down mode

T0 T1 T3 Ta0T2

Don’t Care

Valid

tCKE (MIN)

tXP

DLL RESET

Valid

NOP

tCH tCL

Ta1 Ta2 Tb0Ta3

2 x tCK (MIN)

1 x tCK (MIN)

tCH tCL

tCK

ODT

200 x tCK

NOP

Ta4

Previous clock frequency New clock frequency

Frequency

change

Indicates a break in

time scale

High-Z

tCKE (MIN)

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1Gb: x4, x8, x16 DDR2 SDRAM

Operations

RESET

CKE LOW Anytime

DDR2 SDRAM applic ations may go into a reset state anytime during normal operation.

If an application enters a reset condition, CKE is used to ensure the DDR2 SDRAM

device resumes normal operation after reinitializing. All data will be lost during a reset

condition; however, the DDR2 SDRAM device will continue to operate properly if the

following conditions outlined in this section are satisf ied.

The reset condition defined here assumes all supp ly vol tag es (VDD, VDDQ, VDDL, and

VREF) are stable and meet all DC specifications prior to, during, and after the RESET

operation. All other input balls of the DDR2 SDRAM device are a “Don’t Care” during

RESET with the exception of CKE.

If CKE asynchronously drops LOW during any valid operation (including a READ or

WRITE burst), the memory controller must satisfy the timi ng parameter tDELAY before

turning off the clocks . Stable clocks must exist at the CK, CK# inputs of the DRAM before

CKE is raised HIGH, at which time the normal initialization sequence must occur (see

“I niti alization” on page 74). The DDR2 SDRA M device is now r eady for normal operation

after the initialization sequence. Figure 82 on page 119 shows the proper sequence for a

RESET operation.

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1Gb: x4, x8, x16 DDR2 SDRAM

Operations

Figure 82: RESET Function

Notes: 1. VDD, VDDL, VDDQ, VTT, and VREF must be valid at all times.

2. Either NOP or DESELECT command may be applied.

3. DM represents DM for x4/x8 configuration and UDM, LDM for x16 configuration. DQS rep-

resents DQ S, DQS#, UDQ S, UDQS #, LDQS, LDQS#, RDQS, RDQS# for the appropriate configu-

ration (x4, x8, x16).

4. In certain cases where a READ cycle is interrupted, CKE going HIGH may result in the com-

pletion of t he burst.

5. Initialization timing is shown in Figure 37 on page 74.

CKE

Bank address

High-Z

DM3

DQS3

High-Z

Address

A10

CK#

tCL

Command

NOP2PRE

All banks

Ta0

Don’t CareTransitioning Data

tRPA

tCL

tCK

ODT

DQ3

High-Z

T = 400ns (MIN)

Tb0

READ NOP2

T0 T1 T2

Col n

Bank a

tDELAY

DODO

READ NOP2

Col n

Bank b

High-Z

Unknown R

System

RESET

T3 T4 T5

Start of normal

initialization

sequence

NOP2

Indicates a break in

time scale

tCKE (MIN)

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1Gb: x4, x8, x16 DDR2 SDRAM

Operations

ODT Timing

Once a 12ns delay (tMOD) has been satisfied, and after the ODT function has been

enabled via the EMR LOAD MODE command, ODT can be accessed under two timi ng

categories. ODT will operate either in synchronous mode or asynchro nous mode,

depending on the state of CKE. ODT can switch anytime except during sel f refresh mode

and a few clocks after being enabled via EMR, as shown in Figure 83 on page 121.

There are two timing categories for ODT—turn-on and turn-off. During active mode

(CKE HIGH) and fast-exit power-down mode (any row of any bank open, CKE LOW,

MR[12 = 0]), tAOND, tAON, tAOFD, and tAOF timing parameters are applied, as shown in

Figure 85 on page 122.

During slow-exit power-down mode (any row of any bank open, CKE LOW, MR[12] = 1)

and precharge power-down mode (all banks/ rows precharged and idle, CKE LOW),

tA ONPD and tAOFPD timing par ameters are applied, as shown in Figur e86 on page 122.

ODT turn-off timing, prior to entering any power-down mode, is determined by the

parameter tANPD (MIN), as shown in Figur e87 on page 123. At state T2, the ODT HIGH

signal satis f i es tANPD (MIN) prior to entering power-down mode at T5. When tANPD

(MIN) is satisfied, tAOFD and tAOF timing parameters apply. Figure 87 on page 123 also

shows the example where tANPD (MIN) is not satisfied because ODT HIGH does not

occur until state T3. When tANPD (MIN) is not satisfied, tAOFPD timing parameters

apply.

ODT turn-on timing prior to entering any power-down mode is determined by the

parameter tANPD, as shown in Figure 88 on page 123. At state T2, the ODT HIGH signal

satisfies tANPD (MIN) prior to entering power-down mode at T5. When tANPD (MIN) is

satisfied, tAOND and tAON timing parameters apply. Figure 88 also shows the example

where tANPD (MIN) is not satisfied because ODT HIGH does not occur until state T3.

When tANPD (MIN) is not satisfied, tAONPD timing paramete rs apply.

ODT turn-off timing after exiting any power-down mode is determined by the param-

eter tAXPD (MIN), as shown in Figure 89 on page 124. At state Ta1, the ODT LOW signal

satisfies tAXPD (MIN) after exiting power-down mode at state T1. When tAXPD (MIN) is

satisfied, tAO FD a nd tAOF timing parameters apply. Figure89 also shows the example

where tAXPD (MIN) is not satisfied because ODT LOW occurs at state Ta0. When tAXPD

(MIN) is not satisfied, tAOFPD ti ming parameters apply.

ODT turn-on timing after exiting either slow-exit power-down mode or prechar ge

power-down mode is determined by the parameter tAXPD (MIN), as shown in Figure 90

on page 125. At state Ta1, the ODT HIGH signal satisfies tAXPD (MIN) after exiting

power-down mode at state T1. When tAXPD (MIN) is satisfied, tAOND and tAON timing

parameters apply. Figure90 also shows the example where tAXPD (MIN) is not satisfied

because ODT HIGH occurs at state Ta0. When tAXPD (MIN) is not satisfied, tAONPD

timing parameters apply.

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1Gb: x4, x8, x16 DDR2 SDRAM

Operations

Figure 83: ODT Timing for Entering and Exiting Power-Down Mode

MRS Command to ODT Update Delay

During normal operation, the value of the effective termination resistance can be

changed with an EMRS set command. tMOD (MAX) updates the RTT setting.

Figure 84: Timing for MRS Command to ODT Update Delay

Notes: 1. The LM command is directed to the mode register, which upda tes the information in EMR

(A6, A2), that is, RTT (nominal).

2. To prevent any impedance glitch on the channel, the following conditions must be met:

tAOFD must be met before issuing the LM command; ODT must remain LOW for the entire

duration of the tMOD window until tMOD is met.

ANPD (3

CKs)

First CKE latched LOW

AXPD (8

CKs)

First CKE latched HIGH

Synchronous

Applicable modes

Applicable timing parameters

SynchronousSynchronous or

Asynchronous

Any mode except

self refresh modeAny mode except

self refresh mode

Active power-down fast (synchronous)

Active power-down slow (asynchronous)

Precharge power-down (asynchronous)

AOND/

AOFD (synchronous)

AONPD/

AOFPD (asynchronous)

AOND/

AOFD

AOND/

AOFD

CKE

CK#

ODT2

Internal

setting

EMRS1NOP NOPNOP NOP NOP

COMMAND

tMOD

Old settingUndefinedNew setting

0ns

tIS

tAOFD

Indicates a break in

time scale

T0 Ta0 Ta1 Ta2 Ta3 Ta4 Ta5

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1Gb: x4, x8, x16 DDR2 SDRAM

Operations

Figure 85: ODT Timing for Active or Fast-Exit Power-Down Mode

Figure 86: ODT Timing for Slow-Exit or Precharge Power-Down Modes

T1T0 T2 T3 T4 T5 T6

Valid

ValidValidValid

CK#

ODT

tAOF (MAX)

tAON (MIN)

tAOND

Address

tAOFD

tAON (MAX) tAOF (MIN)

ValidValidValidValidValidValidValid

Command

tCHtCL

Don’t CareR

Unknown R

tCK

CKE

Don’t Care

T1T0 T2 T3 T4 T5 T6

ValidValidValidValidValidValidValid

CK#

CKE

ODT

Address

ValidValidValidValidValidValidValid

Command

tCL

tAONPD (MIN)

tAONPD (MAX)

tAOFPD (MIN) tAOFPD (MAX)

Transitioning R

Valid

Unknown R

tCK

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1Gb: x4, x8, x16 DDR2 SDRAM

Operations

Figure 87: ODT Turn-Off Timings When Entering Power-Down Mode

Figure 88: ODT Turn-On Timing When Entering Power-Down Mode

T1T0 T2 T3 T4 T5 T6

NOPNOP NOP NOPNOP NOP NOP

CK#

Command

CKE

ODT

RTT

tAOF (MIN)

tAOF (MAX)

tAOFD

ODT

RTT

tAOFPD (MIN)

Don’t Care

Transitioning RTT RTT Unknown RTT On

tAOFPD (MAX)

tANPD (MIN)

T1T0 T2 T3 T4 T5 T6

NOPNOP NOP NOPNOP NOP NOP

CK#

RTT

tAON (MIN)

tAON (MAX)

ODT

RTT

tAONPD (MIN)

tAONPD (MAX)

Don’t CareTransitioning RTT RTT Unknown RTT On

ODT

tANPD (MIN)

Command

tAOND

CKE

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1Gb: x4, x8, x16 DDR2 SDRAM

Operations

Figure 89: ODT Turn-Off Timing When Exiting Power-Down Mode

Transitioning R

T1T0 T2 T3 T4 Ta0 Ta1

NOPNOP NOP NOPNOP NOP NOP

CK#

CKE

tAXPD (MIN)

ODT

tAOF (MAX)

ODT

tAOFPD (MIN)

tAOFPD (MAX)

Command

Ta2 Ta3 Ta4 Ta5

NOPNOP NOP NOP

Don’t CareR

Unknown

tAOF (MIN)

Indicates A Break In

Time Scale R

tCKE (MIN)

tAOFD

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prodmktg@micron.com www.micron.com Customer Commen t Line: 800-932- 4992

Micron, the M logo, and the Micron logo are trademarks of Micron Technology, Inc. All other trademarks are the property of

their respective owners.

This data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth

herin. Although considered final, these specifications are subject to change, as further product development and data

characterization sometimes occur.

1Gb: x4, x8, x16 DDR2 SDRAM

Operations

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Figure 90: ODT Turn-On Timing When Exiting Power-Down Mode

T1 T0 T2 T3 T4 T a 0 T a 1

NOPNOP NOP NOPNOP NOP NOP

CK#

CKE

tAXPD (MIN)

Command

T a

T a 4 T a 5

NOPNOP NOP NOP

AON (MIN)

tAON (MAX)

tAONPD (MIN)

tAONPD (MAX)

Don’t Care

RTT Unknown RTT On

Indicates a break in

time scale

RANSITIONING

tAOND

tCKE (MIN)

ODT