Semiconductor Components Industries, LLC, 1999
March, 2000 – Rev. 7 1Publication Order Number:
MC74HC540A/D
MC74HC540A
Octal 3-State Inverting
Buffer/Line Driver/Line
Receiver
High–Performance Silicon–Gate CMOS
The MC74HC540A is identical in pinout to the LS540. The device
inputs are compatible with Standard CMOS outputs. External pullup
resistors make them compatible with LSTTL outputs.
The HC540A is an octal inverting buffer/line driver/line receiver
designed to be used with 3–state memory address drivers, clock
drivers, and other bus–oriented systems. This device features inputs
and outputs on opposite sides of the package and two ANDed
active–low output enables.
The HC540A is similar in function to the HC541A, which has
non–inverting outputs.
•Output Drive Capability: 15 LSTTL Loads
•Outputs Directly Interface to CMOS, NMOS and TTL
•Operating Voltage Range: 2 to 6V
•Low Input Current: 1µA
•High Noise Immunity Characteristic of CMOS Devices
•In Compliance With the JEDEC Standard No. 7A Requirements
•Chip Complexity: 124 FETs or 31 Equivalent Gates
18 Y1
2
A1
17 Y2
3
A2
16 Y3
4
A3
15 Y4
5
A4
14 Y5
6
A5
13 Y6
7
A6
12 Y7
8
A7
11 Y8
9
A8
OE1
OE2 1
19
Output
Enables
Data
Inputs Inverting
Outputs
PIN 20 = VCC
PIN 10 = GND
LOGIC DIAGRAM
Pinout: 20–Lead Packages (Top View)
1920 18 17 16 15 14
21 34567
VCC
13
8
12
9
11
10
OE2 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8
OE1 A1 A2 A3 A4 A5 A6 A7 A8 GND
L
L
H
X
L
L
X
H
L
H
X
X
FUNCTION TABLE
Inputs Output Y
OE1 OE2 A
H
L
Z
Z
Z = High Impedance
X = Don’t Care
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MARKING
DIAGRAMS
1
20
A = Assembly Location
WL = W afer Lot
YY = Year
WW = Work Week
SOIC WIDE–20
DW SUFFIX
CASE 751D
HC540A
AWLYYWW
PDIP–20
P SUFFIX
CASE 738 1
20
MC74HC540AN
AWLYYWW
1
20
1
20
Device Package Shipping
ORDERING INFORMATION
MC74HC540AN PDIP–20 1440 / Box
MC74HC540ADW SOIC–WIDE 38 / Rail
MC74HC540ADWR2 SOIC–WIDE 1000 / Reel
MC74HC540A
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2
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
MAXIMUM RATINGS*
ÎÎÎÎ
ÎÎÎÎ
Symbol
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Parameter
ÎÎÎÎÎ
ÎÎÎÎÎ
Value
ÎÎÎ
ÎÎÎ
Unit
ÎÎÎÎ
ÎÎÎÎ
VCC
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
DC Supply Voltage (Referenced to GND)
ÎÎÎÎÎ
ÎÎÎÎÎ
– 0.5 to + 7.0
ÎÎÎ
ÎÎÎ
V
ÎÎÎÎ
ÎÎÎÎ
Vin
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
DC Input Voltage (Referenced to GND)
ÎÎÎÎÎ
ÎÎÎÎÎ
– 0.5 to VCC + 0.5
ÎÎÎ
ÎÎÎ
V
ÎÎÎÎ
ÎÎÎÎ
Vout
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
DC Output Voltage (Referenced to GND)
ÎÎÎÎÎ
ÎÎÎÎÎ
– 0.5 to VCC + 0.5
ÎÎÎ
ÎÎÎ
V
ÎÎÎÎ
ÎÎÎÎ
Iin
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
DC Input Current, per Pin
ÎÎÎÎÎ
ÎÎÎÎÎ
±20
ÎÎÎ
ÎÎÎ
mA
ÎÎÎÎ
ÎÎÎÎ
Iout
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
DC Output Current, per Pin
ÎÎÎÎÎ
ÎÎÎÎÎ
±35
ÎÎÎ
ÎÎÎ
mA
ÎÎÎÎ
ÎÎÎÎ
ICC
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
DC Supply Current, VCC and GND Pins
ÎÎÎÎÎ
ÎÎÎÎÎ
±75
ÎÎÎ
ÎÎÎ
mA
ÎÎÎÎ
Î
ÎÎ
Î
ÎÎÎÎ
PD
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Î
ÎÎÎÎÎÎÎÎÎÎÎÎ
Î
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Power Dissipation in Still Air Plastic DIP†
SOIC Package†
ÎÎÎÎÎ
Î
ÎÎÎ
Î
ÎÎÎÎÎ
750
500
ÎÎÎ
Î
Î
Î
ÎÎÎ
mW
ÎÎÎÎ
ÎÎÎÎ
Tstg
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Storage Temperature Range
ÎÎÎÎÎ
ÎÎÎÎÎ
– 65 to + 150
ÎÎÎ
ÎÎÎ
_
C
ÎÎÎÎ
ÎÎÎÎ
TL
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Lead Temperature, 1 mm from Case for 10 Seconds
Plastic DIP or SOIC Package
ÎÎÎÎÎ
ÎÎÎÎÎ
260
ÎÎÎ
ÎÎÎ
_
C
*Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
†Derating — Plastic DIP: – 10 mW/
_
C from 65
_
to 125
_
C
SOIC Package: – 7 mW/
_
C from 65
_
to 125
_
C
For high frequency or heavy load considerations, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
RECOMMENDED OPERATING CONDITIONS
ÎÎÎÎ
ÎÎÎÎ
Symbol
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Parameter
ÎÎÎ
ÎÎÎ
Min
ÎÎ
ÎÎ
Max
ÎÎÎ
ÎÎÎ
Unit
ÎÎÎÎ
ÎÎÎÎ
VCC
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
DC Supply Voltage (Referenced to GND)
ÎÎÎ
ÎÎÎ
2.0
ÎÎ
ÎÎ
6.0
ÎÎÎ
ÎÎÎ
V
ÎÎÎÎ
ÎÎÎÎ
Vin, Vout
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
DC Input Voltage, Output Voltage (Referenced to GND)
ÎÎÎ
ÎÎÎ
0
ÎÎ
ÎÎ
VCC
ÎÎÎ
ÎÎÎ
V
ÎÎÎÎ
ÎÎÎÎ
TA
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Operating Temperature Range, All Package Types
ÎÎÎ
ÎÎÎ
– 55
ÎÎ
ÎÎ
+ 125
ÎÎÎ
ÎÎÎ
_
C
ÎÎÎÎ
Î
ÎÎ
Î
Î
ÎÎ
Î
ÎÎÎÎ
tr, tf
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Î
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
Î
Î
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
Î
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Input Rise/Fall T ime VCC = 2.0 V
(Figure 1) VCC = 4.5 V
VCC = 6.0 V
ÎÎÎ
Î
Î
Î
Î
Î
Î
ÎÎÎ
0
0
0
ÎÎ
ÎÎ
ÎÎ
ÎÎ
1000
500
400
ÎÎÎ
Î
Î
Î
Î
Î
Î
ÎÎÎ
ns
DC CHARACTERISTICS (Voltages Referenced to GND)
V
CC
Guaranteed Limit
Symbol Parameter Condition
VCC
V–55 to 25°C≤85°C≤125°C Unit
VIH Minimum High–Level Input
Voltage Vout = 0.1V
|Iout| ≤ 20µA2.0
3.0
4.5
6.0
1.50
2.10
3.15
4.20
1.50
2.10
3.15
4.20
1.50
2.10
3.15
4.20
V
VIL Maximum Low–Level Input
Voltage Vout = VCC – 0.1V
|Iout| ≤ 20µA2.0
3.0
4.5
6.0
0.50
0.90
1.35
1.80
0.50
0.90
1.35
1.80
0.50
0.90
1.35
1.80
V
VOH Minimum High–Level Output
Voltage Vin = VIL
|Iout| ≤ 20µA2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
Vin = VIL |Iout| ≤ 3.6mA
|Iout| ≤ 6.0mA
|Iout| ≤ 7.8mA
3.0
4.5
6.0
2.48
3.98
5.48
2.34
3.84
5.34
2.20
3.70
5.20
VOL Maximum Low–Level Output
Voltage Vin = VIH
|Iout| ≤ 20µA2.0
4.5
6.0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
Vin = VIH |Iout| ≤ 3.6mA
|Iout| ≤ 6.0mA
|Iout| ≤ 7.8mA
3.0
4.5
6.0
0.26
0.26
0.26
0.33
0.33
0.33
0.40
0.40
0.40
Iin Maximum Input Leakage Current Vin = VCC or GND 6.0 ±0.1 ±1.0 ±1.0 µA
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high–impedance cir-
cuit. For proper operation, Vin and
Vout should be constrained to the
range GND
v
(Vin or V out)
v
VCC.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.
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3
DC CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
VCC
V
Symbol Unit≤125°C≤85°C–55 to 25°C
VCC
V
ConditionParameter
IOZ Maximum Three–State Leakage
Current Output in High Impedance State
Vin = VIL or VIH
Vout = VCC or GND
6.0 ±0.5 ±5.0 ±10.0 µA
ICC Maximum Quiescent Supply
Current (per Package) Vin = VCC or GND
Iout = 0µA6.0 4 40 160 µA
NOTE:Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
AC CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6 ns)
VCC
Guaranteed Limit
Symbol Parameter
VCC
V–55 to 25°C≤85°C≤125°C Unit
tPLH,
tPHL Maximum Propagation Delay, Input A to Output Y
(Figures 1 and 3) 2.0
3.0
4.5
6.0
80
30
18
15
100
40
23
20
120
55
28
25
ns
tPLZ,
tPHZ Maximum Propagation Delay, Output Enable to Output Y
(Figures 2 and 4) 2.0
3.0
4.5
6.0
110
45
25
21
140
60
31
26
165
75
38
31
ns
tPZL,
tPZH Maximum Propagation Delay, Output Enable to Output Y
(Figures 2 and 4) 2.0
3.0
4.5
6.0
110
45
25
21
140
60
31
26
165
75
38
31
ns
tTLH,
tTHL Maximum Output T ransition Time, Any Output
(Figures 1 and 3) 2.0
3.0
4.5
6.0
60
22
12
10
75
28
15
13
90
34
18
15
ns
Cin Maximum Input Capacitance 10 10 10 pF
Cout Maximum Three–State Output Capacitance (Output in High
Impedance State) 15 15 15 pF
NOTE:For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the Motorola
High–Speed CMOS Data Book (DL129/D).
Typical @ 25°C, VCC = 5.0 V, VEE = 0 V
CPD Power Dissipation Capacitance (Per Buffer)* 35 pF
*Used to determine the no–load dynamic power consumption: PD = CPD VCC2f + ICC VCC. For load considerations, see Chapter 2 of the
Motorola High–Speed CMOS Data Book (DL129/D).
Figure 1.
VCC
GND
INPUT A
OUTPUT Y
tPHL
OE1 or OE2 50% VCC
GND
OUTPUT Y
tPZL
OUTPUT Y
tPZH
HIGH
IMPEDANCE
VOL
VOH
HIGH
IMPEDANCE
10%
90%
tPLZ
tPHZ
50%
50%
tPLH
90%
50%
10%
tr
tTHL
tf
tTLH
Figure 2.
SWITCHING WAVEFORMS
90%
50%
10%
50%
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4
CL*
*Includes all probe and jig capacitance
TEST
POINT
DEVICE
UNDER
TEST
OUTPUT
TEST CIRCUITS
Figure 3. Figure 4.
CL*
*Includes all probe and jig capacitance
TEST
POINT
DEVICE
UNDER
TEST
OUTPUT 1kΩCONNECT TO VCC WHEN
TESTING tPLZ AND tPZL.
CONNECT TO GND WHEN
TESTING tPHZ and tPZH.
PIN DESCRIPTIONS
INPUTS
A1, A2, A3, A4, A5, A6, A7, A8 (PINS 2, 3, 4, 5, 6, 7, 8,
9) — Data input pins. Data on these pins appear in inverted
form on the corresponding Y outputs, when the outputs are
enabled.
CONTROLS
OE1, OE2 (PINS 1, 19) — Output enables (active–low).
When a low voltage is applied to both of these pins, the
outputs are enabled and the device functions as an inverter.
When a hgih voltage is applied to either input, the outputs
assume the high impedance state.
OUTPUTS
Y1, Y2, Y3, Y4, Y5, Y6, Y7, Y8 (PINS 18, 17, 16, 15, 14,
13, 12, 11) — Device outputs. Depending upon the state of
the output enable pins, these outputs are either inverting
outputs or high–impedance outputs.
LOGIC DETAIL
One of Eight
Inverters
INPUT A
OE1
OE2
OUTPUT Y
VCC
To 7 Other
Inverters
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5
PACKAGE DIMENSIONS
SO–20
DW SUFFIX
CASE 751D–05
ISSUE F
PDIP–20
N SUFFIX
PLASTIC DIP PACKAGE
CASE 738–03
ISSUE E NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD
FLASH.
M
L
J20 PL M
B
M
0.25 (0.010) T
DIM MIN MAX MIN MAX
MILLIMETERSINCHES
A25.66 27.171.010 1.070
B6.10 6.600.240 0.260
C3.81 4.570.150 0.180
D0.39 0.550.015 0.022
G2.54 BSC0.100 BSC
J0.21 0.380.008 0.015
K2.80 3.550.110 0.140
L7.62 BSC0.300 BSC
M0 15 0 15
N0.51 1.010.020 0.040
____
E1.27 1.770.050 0.070
1
11
10
20
–A–
SEATING
PLANE
K
N
FG
D20 PL
–T–
M
A
M
0.25 (0.010) T
E
B
C
F1.27 BSC0.050 BSC
20
1
11
10
B20X
H10X
C
L
18X A1
A
SEATING
PLANE
q
hX 45
_
E
D
M
0.25 M
B
M
0.25 S
AS
B
T
eT
B
A
DIM MIN MAX
MILLIMETERS
A2.35 2.65
A1 0.10 0.25
B0.35 0.49
C0.23 0.32
D12.65 12.95
E7.40 7.60
e1.27 BSC
H10.05 10.55
h0.25 0.75
L0.50 0.90
q
0 7
NOTES:
1. DIMENSIONS ARE IN MILLIMETERS.
2. INTERPRET DIMENSIONS AND TOLERANCES
PER ASME Y14.5M, 1994.
3. DIMENSIONS D AND E DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.
5. DIMENSION B DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE PROTRUSION SHALL
BE 0.13 TOTAL IN EXCESS OF B DIMENSION AT
MAXIMUM MATERIAL CONDITION.
__
MC74HC540A
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6
PACKAGE DIMENSIONS
TSSOP–20
DT SUFFIX
CASE 948E–02
ISSUE A
DIM
AMIN MAX MIN MAX
INCHES
6.60 0.260
MILLIMETERS
B4.30 4.50 0.169 0.177
C1.20 0.047
D0.05 0.15 0.002 0.006
F0.50 0.75 0.020 0.030
G0.65 BSC 0.026 BSC
H0.27 0.37 0.011 0.015
J0.09 0.20 0.004 0.008
J1 0.09 0.16 0.004 0.006
K0.19 0.30 0.007 0.012
K1 0.19 0.25 0.007 0.010
L6.40 BSC 0.252 BSC
M0 8 0 8
____
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH, PROTRUSIONS OR GATE BURRS. MOLD
FLASH OR GATE BURRS SHALL NOT EXCEED
0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL NOT
EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN
EXCESS OF THE K DIMENSION AT MAXIMUM
MATERIAL CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE –W–.
ÍÍÍÍ
ÍÍÍÍ
ÍÍÍÍ
110
1120
PIN 1
IDENT
A
B
–T–0.100 (0.004)
C
DGH
SECTION N–N
K
K1
JJ1
N
N
M
F
–W–
SEATING
PLANE
–V–
–U–
S
U
M
0.10 (0.004) V S
T
20X REFK
L
L/2
2X
S
U0.15 (0.006) T
DETAIL E
0.25 (0.010)
DETAIL E
6.40 0.252
––– –––
S
U0.15 (0.006) T
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Notes
MC74HC540A
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8
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