2001 Microchip Technology Inc. DS21203G-page 1
M24AA256/24LC256/24FC256
DEVICE SELECTION TABLE
FEATURES
• Low power CMOS technology
- Maximum write current 3 mA at 5.5V
- Maximum read current 400 µA at 5.5V
- Standby current 100 nA typical at 5.5V
• 2-wire serial interface bus, I2C compatible
• Cascadable for up to eight devices
• Self-timed ERASE/WRITE cycle
• 64-byte page-write mode available
• 5 ms max write-cycle time
• Hardware write protect for entire array
• Output slope control to eliminate ground bounce
• Schmitt trigger inputs for noise suppression
• 1,000,000 erase/write cycles
• Electrostatic discharge protection > 4000V
• Data retention > 200 yea rs
• 8-pin PDIP, SOIC, TSSOP and MLF packages
• 14-lead TSSO P pa ckage
• Temperature ranges:
DESCRIPTION
The Microchip Technology Inc. 24AA256/24LC256/
24FC256 (24XX256*) is a 32K x 8 (256 Kbit) Serial
Electrically Erasable PROM, capable of operation
across a broad voltage range (1.8V to 5.5V). It has
been developed for advanced, low power applications
such as personal communications or data acquisition.
This dev ice al so has a pa ge-wri te cap abi lity of u p to 64
bytes of data. This device is capable of both random
and sequential reads up to the 256K boundary. Func-
tional address lines allow up to eight devices on the
same bus, for up to 2M bit address space. This device
is available in the standard 8-pin plastic DIP, SOIC,
TSSOP, MLF and 14-lead TSSOP packages.
BLOCK DIAGRAM
PACKAGE TYPE
Part
Number VCC
Range Max. Clock
Frequency Temp.
Ranges
24AA256 1.8-5.5V 400 kHz(1) I
24LC256 2.5-5.5V 400 kHz(2) I, E
24FC256 2.5-5.5V 1 MHz I
Note 1: 100 kHz for VCC < 2.5V.
2: 100 kHz for E temperature range.
- Industrial (I): -40°Cto +85°C
- Automotive (E): -40°C to +125°C
HV GENERATOR
EEPROM
ARRAY
PAGE LATCHES
YDEC
XDEC
SENSE AMP
R/W CONTROL
MEMORY
CONTROL
LOGIC
I/O
CONTROL
LOGIC
I/O
A0A1A2
SDA
SCL
VCC
VSS
WP
A0
A1
A2
VSS
VCC
WP
SCL
SDA
1
2
3
4
8
7
6
5
24XX256
PDIP/SOIC TSSOP
A0
A1
A2
VSS
1
2
3
4
8
7
6
5
VCC
WP
SCL
SDA
TSSOP
24XX256
MLF
A0
A1
A2
VSS
WP
SCL
SDA
24XX256
5
6
7
8
4
3
2
1VCC
NC
A0
A1
NC
A2
VSS
NC
NC
VCC
WP
NC
SCL
SDA
NC
24XX256
1
2
3
4
14
13
12
11
510
69
78
256K I2C™ CMOS Serial EEPROM
*24XX256 is used in this document as a generic part number for the 24AA256/24LC256/24FC256 devices.
I2C™ is a trademark of the Philips Corporation
24AA256/24LC256/24FC256
DS21203G-page 2 2001 Microchip Technology Inc.
1.0 ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings†
VCC.............................................................................................................................................................................6.5V
All inputs and outputs w.r.t. VSS ......................................................................................................... -0.6V to VCC +1.0V
Storage temperature ...............................................................................................................................-65°C to +150°C
Ambient temp. with powe r appli ed............................ ................. ................. ...... ................. .....................-65°C to +125°C
Soldering temperature of leads (10 seconds) .......................................................................................................+300°C
ESD protection on all pins .....................................................................................................................................................≥ 4KV
1.1 DC Characteristics
† NOTICE: Stresses above th ose listed under “Maximum Ratings” may c au se perm an ent da ma ge to the dev ic e. This
is a stres s ra tin g on ly a nd functio nal ope r ati on of the d evi ce at those or an y other cond iti ons abo ve thos e indica ted in
the opera tional listi ngs of this s pecificatio n is not implie d. Exposure to maximum ra ting conditi ons for extend ed periods
may affect device reliability.
DC CHARACTERISTICS Industrial (I): VCC = +1.8V to 5.5V TAMB = -40°C to +85°C
Automotive (E): VCC = +2.5V to 5.5V TAMB = -40°C to 125°C
Param.
No. Sym. Characteristic Min. Max. Units Conditions
D1 —A0, A1, A2, SCL, SDA
and WP pins: ————
D2 VIH High level input voltage 0.7 VCC —V—
D3 VIL Low level input voltage —0.3 VCC
0.2 VCC V
VVCC ≥ 2.5V
VCC < 2.5V
D4 VHYS Hysteresis of Schmitt
Trigger inputs
(SDA, SCL pins)
0.05 VCC —VVCC ≥ 2.5V (Note)
D5 VOL Low level output vol tage —0.40 V IOL = 3.0 mA @ VCC = 4.5V
IOL = 2.1 mA @ VCC = 2.5V
D6 ILI Input leakage current -10 10 µAVIN = VSS or VCC, WP = VSS
VIN = VSS or VCC, WP = VCC
D7 ILO Output leakage current -10 10 µAVOUT = VSS or VCC
D8 CIN,
COUT Pin capacitance
(all inputs/ou tpu t s) —10 pF VCC = 5.0V (Note)
TAMB = 25°C, fC= 1 MHz
D9 ICC Read Operati ng current —400 µAVCC = 5.5V, SCL = 400 kHz
ICC Write —3mAVCC = 5.5V
D10 ICCS Standby current —1 µA SCL = SDA = VCC = 5.5V
A0, A1, A2, WP = VSS
Note: This parameter is periodically sampled and not 100% tested.
2001 Microchip Technology Inc. DS21203G-page 3
24AA256/24LC256/24FC256
1.2 AC Characteristics
AC CHARACTERISTICS Industr ial (I): VCC = +1.8V to 5.5V TAMB = -40°C to +85°C
Automotive (E): VCC = +2.5V to 5.5V TAMB = -40°C to 125°C
Param.
No. Sym. Characteristic Min. Max. Units Conditions
1FCLK Clock frequency —
—
—
—
100
100
400
1000
kHz 2.5V ≤ VCC ≤ 5.5V (E Temp. range)
1.8V ≤ VCC ≤ 2.5V
2.5V ≤ VCC ≤ 5.5V
2.5V ≤ VCC ≤ 5.5V 24FC256
2THIGH Clock high time 4000
4000
600
500
—
—
—
—
ns 2.5V ≤ VCC ≤ 5.5V (E Temp. range)
1.8V ≤ VCC ≤ 2.5V
2.5V ≤ VCC ≤ 5.5V
2.5V ≤ VCC ≤ 5.5V 24FC256
3TLOW Clock low time 4700
4700
1300
500
—
—
—
—
ns 2.5V ≤ VCC ≤ 5.5V (E Temp. range)
1.8V ≤ VCC ≤ 2.5V
2.5V ≤ VCC ≤ 5.5V
2.5V ≤ VCC ≤ 5.5V 24FC256
4TRSDA and SCL rise time
(Note 1) —
—
—
—
1000
1000
300
300
ns 2.5V ≤ VCC ≤ 5.5V (E Temp. range)
1.8V ≤ VCC ≤ 2.5V
2.5V ≤ VCC ≤ 5.5V
2.5V ≤ VCC ≤ 5.5V 24FC256
5TFSDA and SCL fall time
(Note 1) —
—300
100 ns All except, 24FC256
2.5V ≤ VCC ≤ 5.5V 24FC256
6THD:STA START condition hold time 4000
4000
600
250
—
—
—
—
ns 2.5V ≤ VCC ≤ 5.5V (E Temp. range)
1.8V ≤ VCC ≤ 2.5V
2.5V ≤ VCC ≤ 5.5V
2.5V ≤ VCC ≤ 5.5V 24FC256
7TSU:STA START condition setup time 4700
4700
600
250
—
—
—
—
ns 2.5V ≤ VCC ≤ 5.5V (E Temp. range)
1.8V ≤ VCC ≤ 2.5V
2.5V ≤ VCC ≤ 5.5V
2.5V ≤ VCC ≤ 5.5V 24FC256
8THD:DAT Data input hold time 0 —ns (Note 2)
9TSU:DAT Data input setup time 250
250
100
100
—
—
—
—
ns 2.5V ≤ VCC ≤ 5.5V (E Temp. range)
1.8V ≤ VCC ≤ 2.5V
2.5V ≤ VCC ≤ 5.5V
2.5V ≤ VCC ≤ 5.5V 24FC256
10 TSU:STO STOP condition setup time 4000
4000
600
250
—
—
—
—
ns 2.5V ≤ VCC ≤ 5.5V (E Temp. range)
1.8V ≤ VCC ≤ 2.5V
2.5V ≤ VCC ≤ 5.5V
2.5V ≤ VCC ≤ 5.5V 24FC256
11 TSU:WP WP setup time 4000
4000
600
600
—
—
—
—
ns 2.5V ≤ VCC ≤ 5.5V (E Temp. range)
1.8V ≤ VCC ≤ 2.5V
2.5V ≤ VCC ≤ 5.5V
2.5V ≤ VCC ≤ 5.5V 24FC256
12 THD:WP WP hold time 4700
4700
1300
1300
—
—
—
—
ns 2.5V ≤ VCC ≤ 5.5V (E Temp. range)
1.8V ≤ VCC ≤ 2.5V
2.5V ≤ VCC ≤ 5.5V
2.5V ≤ VCC ≤ 5.5V 24FC256
Note 1: Not 100% tested. CB = total capacitance of one bus line in pF.
2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region (minimum
300 ns) of the falling edge of SCL to avoid unintended generation of STAR T or STOP conditions.
3: The combined TSP and VHYS specifications are due to new Schmitt trigger inputs which provide improved noise spike
suppression. This eliminates the need for a T I specification for standard operation.
4: This parameter is not tested but ensured by characterization. For endurance estimates in a specific application, please
consult the Total Endurance Model which can be obtained on Microchip’s website: www .microchip.com.
24AA256/24LC256/24FC256
DS21203G-page 4 2001 Microchip Technology Inc.
FIGURE 1-1: BUS TIMING DATA
13 TAA Output valid from clock
(Note 2) —
—
—
—
3500
3500
900
400
ns 2.5V ≤ VCC ≤ 5.5V (E Temp. range)
1.8V ≤ VCC ≤ 2.5V
2.5V ≤ VCC ≤ 5.5V
2.5V ≤ VCC ≤ 5.5V 24FC256
14 TBUF Bus free time: Time the bus
must be free before a new
transmission can start
4700
4700
1300
500
—
—
—
—
ns 2.5V ≤ VCC ≤ 5.5V (E Temp. range)
1.8V ≤ VCC ≤ 2.5V
2.5V ≤ VCC ≤ 5.5V
2.5V ≤ VCC ≤ 5.5V 24FC256
15 TOF Output fall time from V IH
minimum to VIL maximum
CB ≤ 100 pF
10 + 0.1CB250
250 ns All except, 24FC256 (Note 1)
24FC256 (Note 1)
16 TSP Input filter spike suppression
(SDA and SCL pins) —50 ns All except, 24FC256 (Notes 1 and 3)
17 TWC Write cycle time (byte or page) —5ms—
18 —Endurance 1,000,000 —cycles 25°C, VCC = 5.0V, Block Mode
(Note 4)
AC CHARACTERISTICS (Continued) I ndustrial (I): VCC = +1.8V to 5.5V TAMB = -40°C to +85°C
Automotive (E): VCC = +2.5V to 5.5V TAMB = -40°C to 125°C
Param.
No. Sym. Characteristic Min. Max. Units Conditions
Note 1: Not 100% tested. CB = total capacitance of one bus line in pF.
2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region (minimum
300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions.
3: The combined TSP and VHYS specifications are due to new Schmitt trigger inputs which provide improved noise spike
suppression. This eliminates the need for a T I specification for standard operation.
4: This parameter is not tested but ensured by characterization. For endurance estimates in a specific application, please
consult the Total Endurance Model which can be obtained on Microchip’s website: www .microchip.com.
(unprotected)
(protected)
SCL
SDA
IN
SDA
OUT
WP
5
7
6
16
3
2
89
13
D4 4
10
11 12
14
2001 Microchip Technology Inc. DS21203G-page 5
24AA256/24LC256/24FC256
2.0 PIN DESCRIPTIONS
The descriptions of the pins are listed in Table 2-1.
TABLE 2-1: PIN FUNCTION TABLE
2.1 A0, A1, A2 Chip Address Inputs
The A0, A1, A2 inputs are used by the 24XX256 for
multiple device operations. The levels on these inputs
are compared with the corresponding bits in the slave
address. The chip is selected if the compare is true.
Up to eigh t devi ces ma y be conn ected to th e sam e bu s
by using different chip select bit combinations. If left
unconnected, these inputs will be pulled down inter-
nal l y to VSS.
2.2 Serial Data (SDA)
This is a bi-directional pin used to transfer addresses
and data into and data out of the device. It is an open-
drain terminal, therefore, the SDA bus requires a pull-
up resistor to VCC (typical 10 KΩ for 100 kHz, 2 KΩ for
400kHz and 1MHz).
For norma l data trans fer SDA is all owed to change only
during SCL low. Changes during SCL high are
reserved for indicating the START and STOP condi-
tions.
2.3 Serial Clock (SCL)
This i nput is u sed t o sy nchron ize the d ata trans fer fro m
and to the device.
2.4 Write Protect (WP)
This pin can be connected to either VSS, VCC or left
floating. An internal pull-down resistor on this pin will
keep the device in the unprotected state if left floating.
If tied to VSS or le ft fl oat ing , no rmal mem ory ope rati on
is enabled (read/write the entire memory 0000-7FFF).
If tied to VCC, WRITE operations are inhibited. Read
operations are not affected.
3.0 FUNCTIONAL DESCRIPTION
The 24XX256 supports a bi-directional 2-wire bus and
data transmission protocol. A device that sends data
onto the bus is defined as a transmitter, and a device
receiving data as a receiver. The bus must be con-
trolled by a master device which generates the serial
clock (SCL), controls the bus access, and generates
the START and STOP conditions while the 24XX256
works as a slave. Both master and slave can operate
as a transmitter or receiver, but the master device
determines which mode is activated.
Name PDIP SOIC 8-pin
TSSOP 14-lead
TSSOP MLF Function
A0 1 1 1 1 1 User Configurable Chip Select
A1 2 2 2 2 2 User Configurable Chip Select
(NC) —— — 3, 4, 5 —Not Connec ted
A2 3 3 3 6 3 User Configurable Chip Select
VSS 4 4 4 7 4 Ground
SDA555 85Serial Data
SCL666 96Serial Clock
(NC) —— —10, 11, 12 —Not Conn ec ted
WP 7 7 7 13 7 Write P rot ect Input
VCC 8 8 8 14 8 +1.8 to 5.5V (24AA256)
+2.5 to 5.5V (24LC256)
+4.5 to 5.5V (24FC256)
24AA256/24LC256/24FC256
DS21203G-page 6 2001 Microchip Technology Inc.
4.0 BUS CHARACTERISTICS
The following bus protocol has been defined:
•Data transfer may be initiated only when the bus
is not busy.
•During data transfer, the data line must remain
stab le whe never th e cloc k line i s HIGH . Chang es
in th e dat a line w hi le the cl oc k line i s H IGH w ill be
interpreted as a START or STOP condition.
Accordingly, the following bus conditions have been
defined (Fi gure 4-1).
4.1 Bus not Busy (A)
Both data and clock lines remain HIGH.
4.2 Start Data Transfer (B)
A HIGH to LOW transition of the SDA line while the
clock (SCL) is HIGH determines a START condition.
All commands must be preceded by a START condi-
tion.
4.3 S top Data Transfer (C)
A LOW to HIGH transition of the SDA line while the
clock (SCL) is HIGH determines a STOP condition. All
operations must end with a STOP condition.
4.4 Data Valid (D)
The state of the data line represents valid data when,
after a START condition, the data line is stable for the
durat ion of the HIGH peri od of the clo ck sign al.
The data on the line must be changed during the LOW
period of the clock signal. There is one bit of data per
clock pulse.
Each data transfer is initiated with a START condition
and term ina ted w ith a ST O P c ond iti on. The n um ber of
the data bytes transferred between the START and
STOP conditions is determined by the master device.
4.5 Acknowledge
Each receiving device, when addressed, is obliged to
generate an acknowledge signal after the reception of
each byte. The master device must generate an extra
clock pulse which is associated with this acknowledge
bit.
A device that acknowledges must pull down the SDA
line during the acknowledge clock pulse in such a way
that the SD A line is st able LOW duri ng the HIGH p eriod
of the acknowledge related clock pulse. Of course,
setup and hold times must be taken into account. Dur-
ing reads, a master must signal an end of data to the
slave by NOT generating an acknowledge bit on the
last byte that has been clocked out of the slave. In this
case, the slave (24X X256) will leave the dat a line H IGH
to enable the master to generate the STOP condition.
FIGURE 4-1: DATA TRANSFER SEQUENCE ON THE SERIAL BUS
FIGURE 4-2: ACKNOWLEDGE TIMING
Note: The 24XX256 does not generate any
acknowledge bits if an internal program-
ming cycle is in prog res s.
ADDRESS OR
ACKNOWLEDGE
VALID
DATA
ALLOWED
TO CHANGE
STOP
CONDITION
START
CONDITION
SCL
SDA
(A) (B) (D) (D) (C) (A)
SCL 987654321123
Transmitter must release the SDA line at this point
allowing the Receiver to pull the SDA line low to
acknowledge the previous eight bits of data.
Receiver must release the SDA line
at this point so the Transmitter can
continue sending data.
Data from transmitter
SDA
Acknowledge
Bit
Data from transmitter
2001 Microchip Technology Inc. DS21203G-page 7
24AA256/24LC256/24FC256
5.0 DEVICE ADDRESSING
A control byte is the first byte received following the
start condition from the master device (Figure 5-1). The
control byte consists of a 4-bit control code; for the
24XX 256 t hi s i s se t as 1010 binary for read and write
operations. The next three bits of the control byte are
the chip select bits (A2, A1, A0). The chip select bits
allow the use of up to eight 24XX256 devices on the
same bus and are used to select which device is
accessed. The chip select bits in the control byte must
corresp ond to the logic lev els on the corresp onding A2,
A1 and A0 pins for the device to respond. These bits
are in effect the three most significant bits of the word
address.
The last bit of the control byte defines the operation to
be performed. When set to a one a read operation is
selected, and when set to a zero a write operation is
selected. The next two bytes received define the
address of the first data byte (Figure 5-2). Because
only A14…A0 are used, the upper address bits is a
don’t c are . Th e u pp er a ddre ss b it s a re t rans ferred firs t,
followed by the less significant bits.
Following the start co ndition, the 24XX256 monitors the
SDA bus checking the device type identifier being
transmitted. Upon receiving a 1010 code and appro-
priate device select bits, the slave device outputs an
acknowl edge signal on th e SDA line. Dependi ng on the
state of the R/W bit, the 24XX256 will select a read or
write operation.
FIGURE 5-1: CONTROL BYTE FORMAT
5.1 Contiguous Addressing Across
Multiple Devices
The chip select bits A2, A1, A0 can be used to expand
the contiguous address space for up to 2 Mbit by add-
ing up to eight 24XX256's on the same bus. In this
case, software can use A0 of the control byte as
address bit A15; A1, as address bit A16; and A2, as
address bit A17. It is not possible to sequentially read
across device boundaries.
FIGURE 5-2: ADDRESS SEQUENCE BIT ASSIGNMENTS
1 0 1 0 A2 A1 A0SACKR/W
Control Code Chip Select
Bits
Slave Address
Acknowledge Bit
Start Bit
Read/Write Bit
1010A
2A
1A
0R/W XA
11 A
10 A
9A
7A
0
A
8••••••
A
12
CONTROL BYTE ADDRESS HIGH BYTE ADDRESS LOW BYTE
CONTROL
CODE CHIP
SELECT
BITS
X = Don’t Care Bit
A
13
A
14
24AA256/24LC256/24FC256
DS21203G-page 8 2001 Microchip Technology Inc.
6.0 WRITE OPERATIONS
6.1 Byte Write
Following the start condition from the master, the
control code (four bits), t he c hi p s ele ct (thre e bits ), an d
the R/W bit (wh ich is a logi c lo w) a re clocke d on to the
bus by the master transmitter. This indicates to the
addressed slave receiver that the addre ss high byte will
follow after it has generate d an acknow ledge bit during
the ninth clock cycle. Therefore, the next byte
transmitted by the master is the high-order byte of the
word address and will be written into the address
pointer of the 24XX256. The next byte is the least sig-
nificant address byte. After receiving another acknowl-
edge signal from the 24XX256, the master device will
transmit the dat a word to be writt en in to th e ad dres se d
memory location. The 24XX256 acknowledges again
and the master generates a stop condition. This ini-
tiates the internal write cycle, and, during this time, the
24XX256 will not generate acknowledge signals
(Figure 6-1). If an attempt is made to write to the array
with the WP pin he ld high, the device wil l acknowl edg e
the command but no write cycle will occur, no data will
be written, and the device will immediately accept a
new command. After a byte write command, the inter-
nal address counter will point to the address location
following the one that was just written.
6.2 Page Write
The writ e co ntro l by te, w ord add res s, and th e firs t da ta
byte are transmitted to the 24XX256 in the same way
as in a byte write. But instea d of generatin g a stop con-
dition, the master transmits up to 63 additional bytes,
which are te mp orari ly stored in the on-chip p age buffer
and will be written into memory after the master has
transmitted a stop condi tion. After rec eipt of each wo rd,
the six lower address pointer bits are internally
increm ented by o ne. If the master s hould trans mit more
than 64 byt es prior to generati ng the stop cond ition, the
address counter will roll over and the previously
receive d dat a will be overwri tten. As w ith the byte w rite
operatio n, once the stop con dit ion i s receiv ed, a n int er-
nal write cycle will begin (Figure 6-2). If an attempt is
made to write to the array with the WP pin held high, the
device will acknowledge the command but no write
cycle will occur, no data will be written, and the device
will immediately accept a new command.
6.3 Write Protection
The W P pin a llows th e user t o writ e-prote ct the entire
array (00 00-7FFF) when the pin i s tied to VCC. I f tied to
VSS or left floating, the write protection is disabled. The
WP pin is sampled at the STOP bit for every write
command (Figure 1-1) Toggling the WP pin after the
STOP bit will have no effect on the execution of the
write cycle.
FIGURE 6-1: BYTE WRITE
FIGURE 6-2: PAGE WRITE
Note: Page write operations are limited to
writing bytes within a single physical
page, regardless of the number of
bytes actually being written. Physical
page boundaries start at addresses
that are integer multiples of the page
buffer size (or ‘page size’) and end at
addresses that are integer multiples of
[page size - 1]. If a page write com-
mand atte mp ts to wr ite a cro ss a phy si -
cal page boundary , the result is that the
data wraps around to the beginning of
the current page (overwriting data pre-
viously stored there), instead of being
written to the next page as might be
expected. It is therefore necessary for
the application software to prevent
page write operations that would
attempt to cross a page boundary.
X
BUS ACT IV IT Y
MASTER
SDA LINE
BUS ACT IV IT Y
S
T
A
R
T
CONTROL
BYTE ADDRESS
HIGH BYTE ADDRESS
LOW BYTE DATA
S
T
O
P
A
C
K
A
C
K
A
C
K
A
C
K
X = don’t care bit
S1010 0
A
2A
1A
0P
X
BUS ACTIVITY
MASTER
SDA LINE
BUS ACTIVITY
S
T
A
R
T
CONTROL
BYTE ADDRESS
HIGH BYTE ADDRESS
LOW BYTE DATA BYTE 0
S
T
O
P
A
C
K
A
C
K
A
C
K
A
C
K
DATA BYTE 63
A
C
K
X = don’t care b i t
S1010 0
A
2A
1A
0P
2001 Microchip Technology Inc. DS21203G-page 9
24AA256/24LC256/24FC256
7.0 ACKNOWLEDGE POLLING
Since the device will not acknowledge during a write
cycle, this can be used to determine when the cycle is
complete (This feature can be used to maximize bus
throughput.) Once the stop condition for a write com-
mand has been issued from the master, the device ini-
tiates the internally timed write cycle. ACK polling can
be initiated immediately. This involves the master
sending a start condition, followed by the control byte
for a write command (R/W = 0). If the devi ce is stil l busy
with th e wri te c yc le , th en n o ACK will be returned. If n o
ACK is returned, then the start bit and control byt e must
be resent. If the cycle is complete, then the device will
return the ACK, and the master can then proceed with
the next read or write command. See Figure 7-1 for
flow diagram.
FIGURE 7-1: ACKNOWLEDGE POLLING
FLOW
Send
Write Command
Send Stop
Condition to
Initiate Write Cycle
Send Start
Send Control Byte
with R/W = 0
Did Device
Acknowledge
(ACK = 0)?
Next
Operation
NO
YES
24AA256/24LC256/24FC256
DS21203G-page 10 2001 Microchip Technology Inc.
8.0 READ OPERATION
Read operations are initiated in the same way as write
operations with the exception that the R/W bit of the
control b yte is set to ‘1’. Th ere a re thre e ba si c ty pes of
read operations: current address read, random read
and sequential read.
8.1 Current Address Read
The 24XX256 contains an address counter that main-
tains the address of the last word accessed, internally
incremented by ‘1’. Therefore, if the previous read
access was to address n (n is any legal address), the
next curren t address read operati on would access dat a
from address n + 1.
Upon receipt of the control byte with R/W bit set to ‘1’,
the 24XX2 56 issu es an ac knowle dge and transmit s the
8-bit data word. The master will not acknowledge the
transfer but does generate a stop condition and the
24XX256 discontinues transmission (Figure 8-1).
FIGURE 8-1: CURRENT ADDRESS READ
8.2 Random Read
Random read operations allow the master to access
any memory location in a random manner. To perform
this typ e of re ad o peration, fi rst t he wo rd ad dres s m us t
be set. This is done b y sending the word address to the
24XX256 as part of a write operation (R/W bit set to
‘0’). After the word address is sent, the master gener-
ates a start condition following the acknowledge. This
terminat es the w ri te o pera tio n, but not be fore the int er-
nal address pointer is set. Then, the master issues the
control b yte again but with the R/W bit set to a on e. The
24XX256 will then issue an acknowledge and transmit
the 8-bit data word. The master will not acknowledge
the transfer but does generate a stop condition which
causes the 24XX256 to discontinue transmission
(Figure 8-2). After a random read command, the inter-
nal address counter will point to the address location
following the one that was just read.
8.3 Sequential Read
Sequential reads are initiated in the same way as a ran-
dom read except that after the 24XX256 transmits the
first data byte, the master issues an acknowledge as
opposed to the stop condition used in a random read.
This acknowledge directs the 24XX256 to transmit the
next sequentially addressed 8-bit word (Figure 8-3).
Following the final byte transmitted to the master, the
master w ill NOT gen erate an ackn owledge but w ill gen-
erate a st op condition. To provide seque ntial rea ds, the
24XX256 contains an internal address pointer which is
incremented by one at the completion of each opera-
tion. This address pointer allows the entire memory
contents to be serially read during one operation. The
internal address pointer will autom atically roll ov er from
address 7FFF to address 0000 if the master acknowl-
edges the byte received from the array address 7FFF.
FIGURE 8-2: RANDOM READ
FIGURE 8-3: SEQUENTIAL READ
BUS ACTIVITY
MASTER
SDA LINE
BUS ACTIVITY
PS
S
T
O
P
CONTROL
BYTE
S
T
A
R
T
DATA
A
C
K
N
O
A
C
K
1100
AAA1
BYTE
210
X
BUS ACTIVITY
MASTER
SDA LINE
BUS ACTIVITY A
C
K
N
O
A
C
A
C
K
A
C
K
A
C
K
S
T
O
P
S
T
A
R
T
CONTROL
BYTE ADDRESS
HIGH BYTE ADDRESS
LOW BYTE CONTROL
BYTE DATA
BYTE
S
T
A
R
T
X = Don’t Care Bit
S1010AAA0
210 S1010AAA1
210 P
BUS ACT IV IT Y
MASTER
SDA LINE
BUS ACT IV IT Y
CONTROL
BYTE DATA (n) DATA (n + 1) DATA (n + 2) DATA (n + X)
N
O
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
S
T
O
P
P
2001 Microchip Technology Inc. DS21203G-page 11
24AA256/24LC256/24FC256
9.0 PACKAGING INFORMATION
9.1 Package Marking Information
XXXXXXXX
XXXXXNNN
YYWW
8-Lead PDIP (300 mil) Example:
8-Lead TSSOP Example:
8-Lead SOIC (150 mil) Example:
XXXXXXXX
XXXXYYWW
NNN
XXXX
XYWW
NNN
8-Lead SOIC (208 mil) Example:
24LC256
YYWWNNN
I/SM
4LD
IYWW
NNN
24LC256
I/PNNN
YYWW
Legend: XX...X Customer specific information*
Y Year code (last digit of calendar year)
YY Year code (last 2 digits of calendar year)
WW Week code (week of January 1 is week ‘01’)
NNN Alphanum eric traceab il ity code
Note: In the event the full Mic rochi p part number cann ot be mark ed on on e line, it will
be carrie d ov er to th e nex t li ne th us l im itin g the num be r of av ail abl e characte rs
for customer specific information.
*Standard device marking consists of Microchip part number, year code, week code, and traceability
code. For device marking beyond this, certain price adders apply. Please check with your Microchip
Sales Office. For QTP devices, any special marking adders are included in QTP price.
XXXXXXXX
YYWWNNN
XXXXXXXX
24FC256
I/SNYYWW
NNN
24AA256/24LC256/24FC256
DS21203G-page 12 2001 Microchip Technology Inc.
Package Marking Information (Continue d)
14-Lead TSSOP Example:
XXXXXXXX
YYWW
NNN
24LC256I
YYWW
NNN
Legend: XX...X Customer specific information*
Y Year code (last digit of calendar year)
YY Year code (last 2 digits of calendar year)
WW Week code (week of January 1 is week ‘01’)
NNN Alphanum eri c trac eab ili ty code
Note: In the event the full Mic rochip part n umber c annot be marked on one line, it wil l
be carried over to the nex t lin e thus limi tin g the num be r of av ail abl e ch arac te rs
for customer specific information.
*Standard device marking consists of Microchip part number, year code, week code, and traceability
code. For device marking beyond this, certain price adders apply. Please check with your Microchip
Sales Office. For QTP devices, any special marking adders are included in QTP price.
8-Lead MLF Example:
24LC256
I/MFNNN
YYWWW
XXXXXXXX
XXXXNNN
YYWWW
2001 Microchip Technology Inc. DS21203G-page 13
24AA256/24LC256/24FC256
8-Lead Plastic Dual In-line (P) – 300 mil (PDIP)
B1
B
A1
A
L
A2
p
α
E
eB
β
c
E1
n
D
1
2
Units INCHES* MILLIMETERS
Dime nsio n Limits MIN NOM MAX MIN NOM MAX
Number of Pins n88
Pitch p.100 2.54
Top to Seating Plane A .140 .155 .170 3.56 3.94 4.32
Molded Package Thickness A2 .115 .130 .145 2.92 3.30 3.68
Base to Seating Plane A1 .015 0.38
Shoulder to S houlder Width E .300 .3 13 .325 7.62 7.94 8.26
Molded Package Width E1 .240 .250 .260 6.10 6.35 6.60
Overall Length D .360 .373 .385 9.14 9.46 9.78
Tip to Seating Plane L .125 .130 .135 3.18 3.30 3.43
Lead Thickness c.008 .012 .015 0.20 0.29 0.38
Upper Lead Width B1 .045 .058 .070 1.14 1.46 1.78
Lower Lead Width B .014 .018 .022 0.36 0.46 0.56
Overall Row S pacing §eB .310 .370 .430 7.87 9.40 10.92
Mold Draft Angle Top α51015 51015
Mold Draft Angle Bottom β51015 51015
* Controlling Parameter
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
JEDEC Equivalent: MS-001
Drawing No. C04-018
.010” (0.254mm) per side.
§ Significant Characteristic
24AA256/24LC256/24FC256
DS21203G-page 14 2001 Microchip Technology Inc.
8-Lead Plastic Small Outline (SN) –Narrow, 150 mil (SOIC)
Foot A ngle f048048
1512015120
β
Mold Draft Angle Bottom 1512015120
α
Mold Draft Angle Top 0.510.420.33.020.017.013BLead Width 0.250.230.20.010.009.008
c
Lead Thickness
0.760.620.48.030.025.019LFoot Length 0.510.380.25.020.015.010hChamfer Distance 5.004.904.80.197.193.189DOverall Length 3.993.913.71.157.154.146E1Molded Pa ckag e Width 6.206.025.79.244.237.228EOverall Width 0.250.180.10.010.007.004
A1
Standoff §1.551.421.32.061.056.052A2Molded Packag e Thickness 1.751.551.35.069.061.053AOverall Height 1.27.050
p
Pitch 88
n
Numb er of Pin s MAXNOMMINMAXNOMMINDimension Limits MILLIMETERSINCHES*Units
2
1
D
n
p
B
E
E1
h
L
β
c
45×
f
A2
α
A
A1
* Controlling Parameter
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MS-012
Drawing No. C04-057
§ Significant Characteristic
2001 Microchip Technology Inc. DS21203G-page 15
24AA256/24LC256/24FC256
8-Lead Plastic Small Outline (SM) – Medium, 208 mil (SOIC )
Foot A ngle f048048
1512015120
β
Mold Draft Angle Bottom 1512015120
α
Mold Draft Angle Top 0.510.430.36.020.017.014BLead Width 0.250.230.20.010.009.008
c
Lead Thickness
0.760.640.51.030.025.020LFoot Length 5.335.215.13.210.205.202DOverall Length 5.385.285.11.212.208.201E1Mold ed Pa ckag e Width 8.267.957.62.325.313.300EOverall Width 0.250.130.05.010.005.002A1Standoff §1.98.078A2Molded Package Thick ness 2.03.080AOverall Height 1.27.050
p
Pitch 88
n
Number of Pins MAXNOMMINMAXNOMMINDimension Limits MILLIMETERSINCHES*Units
α
A2
A
A1
L
c
β
f
2
1
D
n
p
B
E
E1
.070 .075
.069 .074 1.78
1.75 1.97
1.88
* Controlling Parameter
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
Drawing No. C04-056
§ Significant Characteristic
24AA256/24LC256/24FC256
DS21203G-page 16 2001 Microchip Technology Inc.
8-Lead Plastic Thin Shrink Small Outline (ST) – 4.4 mm (TSSOP)
10501050
β
Mold Draft Angle Bottom 10501050
α
Mold Draft Angle Top 0.300.250.19.012.010.007BLead Width 0.200.150.09.008.006.004
c
Lead Thickness
0.700.600.50.028.024.020LFoot Length 3.103.002.90.122.118.114DMolded Package Length 4.504.404.30.177.173.169E1M old ed Pa ckag e Width 6.506.386.25.256.251.246EOverall Width 0.150.100.05.006.004.002
A1
Standoff §0.950.900.85.037.035.033A2Molded Pa ckag e Thick ness 1.10.043AOverall Height 0.65.026
p
Pitch 88
n
Number of Pins MAXNOMMINMAXNOMMINDimension Limits MILLIMETERS*INCHESUnits
α
A2
A
A1
L
c
β
φ
1
2D
n
p
B
E
E1
Foot A ngle φ048048
* Controlling Parameter
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.005” (0.127mm) per s ide.
JEDEC Equivalent: MO-153
Drawing No. C04-086
§ Significant Characteristic
2001 Microchip Technology Inc. DS21203G-page 17
24AA256/24LC256/24FC256
8-Lead Micro Leadframe Package (ML) 6x5 mm Body (MLF-S)
NOM
.050 BSC
INCHES
.194 BSC
.184 BSC
.226 BSC
.236 BSC
.008 REF.
DOverall Width
JEDEC equivalent: pending
Notes:
Drawing No. C04-113
Molded Package Width
Lead Width
*Controlling Parameter
Mold Dr aft Angle Top
Tie Bar Width
Lead Length R
α
B
L
D1
.014
.020
Dimension Limits
Molded Package Thickness
Pitch
Overall Height
Overall Length
Molded Package Length
Base Thicknes s
Standoff
Number of Pins
A3
E1
E
A2
A1
A
.000
Units
n
p
MIN
TOP VIEW
12
A2
A
5.99 BSC
.019
12
.030
.014
.016
.024 0.35
0.50 .356
0.40
0.60
5.74 BSC
12
0.47
0.75
MILLIMETERS*
.039
.002
.031
.026
.0004
.033
0.00
8MAX MIN
1.27 BSC
0.20 REF.
4.92 BSC
4.67 BSC
0.85
0.01
0.65 0.80
0.05
1.00
MAXNOM 8
BOTTOM VIEW
n
E
E1
PIN 1
p
B
Exposed Pad Length E2
Exposed Pad Width D2 .085 .091 .097 2.16 2.31 2.46
.152 .158 .163 3.85 4.00 4.15
EXPOSED
METAL
PADS
D2
E2
A1
A3
α
L
ID
D1 D
R
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side.
24AA256/24LC256/24FC256
DS21203G-page 18 2001 Microchip Technology Inc.
8-Lead Micro Leadframe Package (ML) 6x5 mm Body (MLF-S) (Continued)
Pad Width
*Contr ol li ng Para meter
Drawing No. C04-2113
B .014 .016 .019 0.35 0.40 0.47
Pitch MAX
Units
Dimension Limits
p
INCHES
.050 BSC
MIN NOM MAX
MILLIMETERS*
MIN 1.27 BSC
NOM
Pad Length
Pad to Solder Mask L .020 .024 .030 0.50 0.60 0.75
M .005 .006 0.13 0.15
L
M
M
B
SOLDER
MASK
p
PACKAGE
EDGE
2001 Microchip Technology Inc. DS21203G-page 19
24AA256/24LC256/24FC256
14-Lead Plastic Thin Shrink Small Outline (ST) – 4.4 mm (TSSOP)
840840
f
Foot A ngle
10501050
β
Mold Draft Angle Bottom 10501050
α
Mold Draft Angle Top 0.300.250.19.012.010.007BLead W idth 0.200.150.09.008.006.004
c
Lead Thickness
0.700.600.50.028.024.020LFoot Length 5.105.004.90.201.197.193DMolded Package Length 4.504.404.30.177.173.169E1M olded Package Width 6.506.386.25.256.251.246EOverall Width 0.150.100.05.006.004.002A1Standoff §0.950.900.85.037.035.033
A2
Molded Pa ckag e Thick ness 1.10.043AOverall Height 0.65.026
p
Pitch 1414
n
Number of Pins MAXNOMMINMAXNOMMINDimension Limits MILLIMETERS*INCHESUnits
L
β
c
f
2
1
D
n
B
p
E1
E
α
A2A1
A
* Controlling Parameter
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.005” (0.127mm) per side.
JEDEC Equivalent: MO-153
Drawing No. C04-087
§ Significant Characteristic
24AA256/24LC256/24FC256
DS21203G-page 20 2001 Microchip Technology Inc.
ON-LINE SUPPORT
Microchip provides on-line support on the Microchip
World Wide Web (WWW) site.
The web site is used b y Micr ochip as a me ans to mak e
files and information easily available to customers. To
view t he site, the user must have acce ss to the In ternet
and a web browser, such as Netscape® or Microsoft®
Explorer. Files are also available for FTP download
from our FTP site.
Connecting to the Microchip Internet Web Site
The Microchip web site is available by using your
fa vorite Internet browser to attach to:
www.microchip.com
The file transfer site is available by using an FTP ser-
vice to connect to:
ftp://ftp.microchip.com
The web site and file transfer site provide a variety of
services. Users may download files for the latest
Development Tools, Data Sheets, Application Notes,
User’s Guides, Articles and Sample Programs. A vari-
ety of Microchip specific business information is also
available, including listings of Microchip sales offices,
distributors and factory representatives. Other data
available for consideration is:
•Latest Microchip Press Releases
•Technical Support Section with Frequently Asked
Questions
•Design Tips
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•Microchip Cons ultant Program Member Listing
•Links to other useful web sites related to
Microchip Products
•Confere nces for prod ucts, Dev elopment Systems,
technical information and more
•Listing of seminars and events
Systems Information and Upgrade Hot Line
The Systems Information and Upgrade Line provides
system users a listing of the latest versions of all of
Microchip's development systems software products.
Plus, this line provides information on how customers
can receive any currently available upgrade kits.The
Hot Line Numbers are:
1-800-755-2345 for U.S. and most of Canada, and
1-480-792-7302 for the rest of the world.
2001 Microchip Technology Inc. DS21203G-page 21
24AA256/24LC256/24FC256
READER RESPONSE
It is ou r intention to pro vi de you w it h th e best do cu mentation po ss ib le to ens ure suc c ess fu l u se of y ou r M icr oc hip pro d-
uct. If you wi sh to prov ide you r comment s on org anizatio n, clar ity, subj ect matte r , a nd ways i n which o ur docum entatio n
can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-7578.
Please list the following information, and use this outline to provide us with your comments about this Data Sheet.
To: Technical Publications Manager
RE: Reader Response Total Pages Sent
From: Name
Company
Address
City / State / ZIP / Country
Telephone: (_______) _________ - _________
Applicati on (opt ional):
Would you like a reply? Y N
Device: Literature Number:
Questions:
FAX: (______) _________ - _________
DS21203G
24AA256/24LC256/24FC256
1. Wha t are the be st fe atures of this document?
2. How does this document meet your hardware and software development needs?
3. Do you find the organization of this data sheet easy to follow? If not, why?
4. What additions to the data sheet do you think would enhance the structure and subject?
5. What deletions from the data sheet could be made without affecting the overall usefulness?
6. Is there any incorrect or misleading information (what and where)?
7. How would you improve this document?
8. How would you improve our software, systems, and silicon products?
24AA256/24LC256/24FC256
DS21203G-page 22 2001 Microchip Technology Inc.
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
Sales and Support
PART NO. X /XX
PackageTemperature
Range
Device
Device: 24AA256: = 256 Kbit 1.8V I2C Serial EEPROM
24AA256T:= 256 Kbit 1.8V I2C Serial EEPROM
(Tape and Reel)
24LC256: = 256 Kbit 2.5V I2C Serial EEPROM
24LC256T:= 256 Kbit 2.5V I2C Serial EEPROM
(Tape and Reel)
24FC256: = 256 Kbit 1 MHz I2C Serial EEPROM
24FC256T:= 256 Kbit 1 MHz I2C Serial EEPROM
(Tape and Reel)
Temperature
Range: I=-40°C to +85°C
E=-40°C to +125°C
Package: P = Plastic DIP (300 mil body), 8-lead
SN = Plastic SOIC (150 mil body), 8-lead
SM = Plastic SOIC (208 mil body), 8-lead
ST = Plastic TSSOP (4.4 mm), 8-lead
ST14= Plastic TSSOP (4.4 mm), 14-lead
MF = Micro Leadframe (6x5 mm body), 8-lead
Examples:
a) 24LC256-I/SN: Industrial Temp.,
SOIC package
b) 24LC256T-I/SN: Tape and Reel,
Industrial Temp., SOIC package
c) 24LC256-E/SM: Extended Temp.,
SOIC package
d) 24LC256T-E/SM: Tape and Reel,
Extended Temp., SOIC package
e) 24FC256-I/P: Industrial Temp.,
PDIP package
f) 24FC256-I/ SM: Indu strial Temp .,
SOIC package
g) 24FC256T-I/SM: Tape and Reel,
Industrial Temp., SOIC package
Data Sh eets
Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences
and recommended workarounds. To determine if an errata sheet exists for a particular device, please contact one of
the following:
1. Your local Microchip sales office
2. The Microchip Corporate Literature Center U.S. FAX: (480) 792-7277
3. The Microchip Worldwide Site (www.microchip.com)
Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using.
New Customer Notification System
Register on our web site (www.microchip.com/cn) to receive the most current information on our products.
2001 Microchip Technology Inc. DS21203G-page 23
24AA256/24LC256/24FC256
“All rights reserved. Copyright © 2001, Microchip
Technology Incorporated, USA. Information contained
in this publication regardin g device appl ications and th e
like is intended through suggestion only and may be
superse ded by updates . No repr esent ati on or warrant y
is given and no liabil ity is assume d by Microchip
Technology Incorporated with respect to the accuracy
or use of such information, or infringement of patent s or
other intellectual property rights arising from such use
or otherwise. Use of Microchip’s products as critical
components in life support systems is not authorized
except with express written approval by Microchip. No
licenses are conveyed, implicitly or otherwise, under
any int ell ectual pro per ty righ ts. The Mi croch ip log o and
name are registered trademarks of Microchip
Technology Inc. in the U.S.A. and other countries. All
rights rese rve d. Al l other tr ade ma rks m enti one d h erei n
are the property of their respective companies. No
licenses are conveyed, implicitly or otherwise, under
any intellectual property rights.”
Trademarks
The Microchip name, logo, PIC, PICmicro,
PICMASTER, PICSTART, PRO MATE, KEELOQ,
SEEVAL, MPLAB and The Embedd ed Control
Solutions Company are registered trademarks of
Microchip Technology Incorporated in the U.S.A. and
other countries.
Total Endurance, ICSP, In-Circuit Serial Programming,
FilterLab, MXDEV, microID, FlexROM, fuzzyLAB,
MPASM, MPLINK, MPLIB, PICDEM, ICEPIC,
Migratable Memory, FanSense, ECONOMONITOR,
Select Mode and microPort are trademarks of
Microchip Technology Incorporated in the U.S.A.
Serializ ed Q ui ck Term Programm in g (SQ TP) is a
service mark of Microchip Technology Incorporated in
the U.S.A.
All other trademarks mentioned herein are property of
their respec tiv e com p a ni es.
© 2001, M icr oc hip Tec hn olo gy Inco rpo rated, Printed in
the U.S.A., All Rights Reserved.
Microchip received QS-9000 quality system
certification for its worldwide headquarters,
design and wafer fabrication facilities in
Chandler and T empe, Arizona in July 1999. The
Company’s quality system processes and
procedures are QS-9000 compliant for its
PICmicro® 8- bi t MC Us , KEELOQ® code hopping
devices, Serial EEPROMs and microperipheral
products. In addition, Microchip’s quality
system for the design and manufacture of
development systems is ISO 9001 certified.
Information contained in this publication regarding device applications and the like is intended through suggestion only and may be superseded by
update s. It i s your respo nsibilit y to en sure t hat you r app licatio n mee ts with y our sp ecifica tions. N o re presen tation or warra nty is given and n o liability is
assumed by M icroc hip Techno log y Incor porate d with respe ct t o the accur acy or u se of such infor mation, or infrin gemen t of patents or other in tellectua l
property rights arising from such use or otherwise. Use of Microchip’s products as critical components in life support systems is not authorized except with
express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, except as maybe explicitly expressed herein, under any intellec-
tual p roperty rights. The M icrochip logo an d name are reg istered tradema rks of Microchip Technolo gy Inc. in the U.S.A. and other countries. All rig hts
reserved. All other trademarks mentioned herein are the property of their respective companies.
DS21203G-page 24 2001 Microchip Technology Inc.
All rights reserved. © 2001 Microchip Technology Incorporated. Printed in the USA. 5/01 Printed on recycled paper.
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18201 Von Karman, Suite 1090
Irvine, CA 92612
Tel : 949 -2 63- 188 8 Fax: 949- 263-1338
Mountain View
Analog Product Sales
1300 Terra Bella Avenue
Mountain View, CA 94043-1836
Tel : 650 -9 68- 924 1 Fax: 650- 967-1590
New York
150 Motor Parkway, Suite 202
Hauppauge, NY 11788
Tel: 631-273-5305 Fax: 631-273-5335
San Jose
Microchip Technology Inc.
2107 North First Street, Suite 590
San Jose, CA 95131
Tel: 408-436-7950 Fax: 408-436-7955
Toronto
6285 Northam Drive, Suite 108
Mississaug a, Ontario L4V 1X5, Canada
Tel: 905-673-0699 Fax: 905-673-6509
ASIA/PACIFIC
Australia
Microchip Technology Australia Pty Ltd
Suite 22, 41 Rawson Street
Epping 212 1, NSW
Australia
Tel: 61-2-9868-6733 Fax: 61-2-9868-6755
China - Be ijing
Microchip Technology Beijing Office
Unit 915
New China Hong Kong Manhattan Bldg.
No. 6 Chaoyangmen Beidajie
Beijing, 100027, No. China
Tel: 86-10-85282100 Fax: 86-10-85282104
China - Shanghai
Microchip Technology Shanghai Office
Room 701, Bldg. B
Far East Internationa l Plaza
No. 317 Xian Xia Road
Shanghai, 200051
Tel: 86-21-6275-5700 Fax: 86-21-6275-5060
Hong Kong
Microchip Asia Pacific
RM 2101, Tower 2, Metroplaza
223 Hing Fong Road
Kwai Fong, N.T., Hong Kong
Tel: 852-2401-1200 Fax: 852-2401-3431
India
Microchip Technology Inc.
India Liaiso n Office
Divyasree Chambers
1 Floor, Wing A (A3/A4)
No. 11, O’Shaugnessey Road
Bangalore, 560 025, India
Tel: 91-80-2290061 Fax: 91-80-2290062
Japan
Microchip Technology Intl. Inc.
Benex S-1 6F
3-18-20, Shinyokohama
Kohoku -Ku, Yokohama-shi
Kanaga wa, 222 -0 033 , Japan
Tel: 81-45-471- 6166 Fax: 81-45-471-6122
ASIA/PACIFIC (continued)
Korea
Microc hip Technol o gy Korea
168-1, Youngbo Bldg. 3 Floor
Samsung-Dong, Kangnam-Ku
Seoul, Ko re a
Tel: 82-2-554-7200 Fax: 82-2-558-5934
Singapore
Microchip Technology Singapore Pte Ltd.
200 Midd le Ro ad
#07-02 Prime Centre
Singapore, 188980
Tel: 65-334- 8870 Fax: 65-334-8850
Taiwan
Microc hip Technol o gy Taiwan
11F-3, No. 207
Tung Hua North Road
Taipei, 105, Taiwan
Tel: 886-2-2717-7175 Fax: 886-2-2545-0139
EUROPE
Denmark
Microchip Technology Denmark ApS
Regus Business Centre
Lautrup hoj 1-3
Ballerup DK-2750 Denmark
Tel: 45 4420 9895 Fax: 45 4420 9910
France
Arizona Microchip Technology SARL
Parc d’Activite du Moulin de Massy
43 Rue du Saule T rapu
Batiment A - ler Et age
91300 Massy, France
Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79
Germany
Arizona Microchip Technology GmbH
Gustav-Heinemann Ring 125
D-81739 Munich, Germany
Tel: 49-89-627-144 0 Fax: 49-89-627-144-44
Germany
Analog Product Sales
Lochhamer Strasse 13
D-82152 Martinsried, Germany
Tel: 49-89-895650-0 Fax: 49-89-895650-22
Italy
Arizona Microchip Technology SRL
Centro Direzionale Colleoni
Palazzo Taurus 1 V. Le Colleoni 1
20041 Agrate Brianza
Milan, Italy
Tel: 39-039-65791-1 Fax: 39-039-6899883
United Kingdom
Arizona Microchip Technology Ltd.
505 Eskdale Road
Winnersh Triangle
Wokingham
Berksh ire, E ngla nd RG 41 5TU
Tel: 44 118 921 5869 Fax: 44-118 921-5820
01/30/01
WORLDWIDE SALES AND SERVICE
