74LVX573MTCX_NL - Fairchild Semiconductor

June 1993

Revised April 2005

74LVX573 Low Voltage Octal Latch with 3-STATE Outputs

74LVX573

Low Voltage Octal Latch with 3-STATE Outputs

General Descript ion

The LVX573 is a h i gh -spe ed o cta l la tch with b uffere d com-

mon Latch Enable (LE) and buffered common Output

Enab l e (OE ) inpu ts. The LVX573 is fu nctio nally id entic al to

the LVX373 but with in puts and outp uts on opp osite sides

of the packa ge. The inp uts to lera te up to 7V al lowi n g inte r-

face of 5V systems to 3V systems.

Features

■Input voltage translation from 5V to 3V

■Ideal for low power/low noise 3.3V applications

■Guaranteed simultaneous switching noise level and

dynamic thresh ol d per for man ce

Ordering Code:

Devices also available in Tape and R eel. Specif y by append ing suffix lette r “X” to the ordering co de.

Pb-Free package per JEDEC J-STD-020B.

Logic Symbols

IEEE/IEC

Connection Diagram

Pin Descriptions

Order Number Package Number Package Description

74LVX573M M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide

74LVX573SJ M20D Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

74LVX573MTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide

Pin Names Description

D0–D7Data Inputs

LE La tch Enable Input

OE 3-STATE Output Enab le Input

O0–O73-STAT E Lat ch Outpu ts

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74LVX573

Functional Description

The LVX573 contains eight D-type latches. When the

enable (LE) input is HIGH, data on the Dn inputs enters the

latche s. In this conditi on the latches are tra nsparent , i.e., a

latch output will change state each time its D input

changes. When LE is LOW the latches store the infor ma-

tion that wa s pre sent o n the D in puts a se tup tim e pr eced-

ing the HIGH-to-LOW transition of LE. The 3-STATE

buffers are controlled by the Output Enable (OE) input.

When OE is LOW, the buffers are enabled. When OE is

HIGH th e buffers are in the high impedance mode but this

does not interfere with entering new data into the latches.

Truth Table

HIG H Voltage

LOW Voltage

High Impedance

Immaterial

Previ ous O0 be f ore HIGH-t o-LOW tr ans it ion of Lat ch Enable

Logic Diagram

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.

Inputs Outputs

OE LE D On

LHH H

LHL L

LLX O

HXX Z

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74LVX573

Absolute Maximum Ratings(Note 1) Recommended Operating

Conditions (Note 2)

Note 1: The “Absolute Maximum Ratings” are those val ues beyond w hich

the saf ety of the device cannot be guarante ed. The device s hould not be

operated at these limits. The parametric values defined in the Electrical

Char ac teristics t ables are not guar anteed at the absolute m aximum ratings.

The “R ecomm ended O peratin g Con ditions ” table will defin e the condition s

for actu al device operation.

Note 2: Unused inputs must b e held HIGH or LOW. Th ey may not float.

DC Electrical Characteristics

Noise Characteri stics (Note 3)

Note 3: (Input tr

3ns)

Supply Voltage (VCC)



0.5V to



7.0V

DC Input Diode Current (IIK)



0.5V



20 mA

DC Input Voltage (VI)



0.5V to 7V

DC Output Diode Current (IOK)



0.5V



20 mA

VCC



0.5V



20 mA

DC O utput Voltage (VO)



0.5V to VCC



0.5V

DC Output Source

or Sink Current (IO)

25 mA

DC VCC or Ground Current

(ICC or IGND)

75 mA

Storage Temperature (TSTG)



C to



150

Power Dissipation 180 mW

Supply Voltage (VCC) 2.0V to 3.6V

Input Voltage (VI) 0V to 5.5V

Output Voltage (VO)0V to V

Operating Temperature (TA)



C to



Input Rise and Fall Time (

V) 0 ns/V to 100 ns/V

Symbol Parameter VCC TA





C to



CUnits Conditions

Min Typ Max Min Max

VIH HIGH Level 2.0 1.5 1.5

Input Voltage 3.0 2.0 2.0 V

3.6 2.4 2.4

VIL LOW Level 2.0 0.5 0.5

Input Voltage 3.0 0.8 0.8 V

3.6 0.8 0.8

VOH HIGH Level 2.0 1.9 2.0 1.9 VIN

VIH or VIL IOH



Output Voltage 3.0 2.9 3.0 2.9 V IOH



3.0 2.58 2.48 IOH



4 mA

VOL LOW Level 2.0 0.0 0.1 0.1 VIN

VIH or VIL IOL

Output Voltage 3.0 0.0 0.1 0.1 V IOL

3.0 0.36 0.44 IOL

4 mA

IOZ 3-STATE Output 3.6

0.25

2.5

VIH or VIL

Off-State Current VOUT

VCC or GND

IIN Input Leakage Current 3.6

0.1

1.0

5.5V or GND

ICC Quiescent Supply Current 3.6 4.0 40.0

VCC or GND

Symbol Parameter VCC TA

CUnits CL (pF )

(V) Typ Limit

VOLP Quiet Output Maximum Dynamic VOL 3.3 0.5 0.8 V 50

VOLV Quiet Output Minimum Dynamic VOL 3.3



0.5



0.8 V 50

VIHD Minimum HIGH Level Dynamic Input Voltage 3.3 2.0 V 50

VILD Maximum LOW Level Dynamic Input Voltage 3.3 0.8 V 50

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74LVX573

AC Electrical Characteristics

Note 4: Parameter guaranteed by design. tOSLH

|tPLHm



tPLHn|, tOSHL

|tPHLm



tPHLn|.

Capacitance

Note 5: CPD is defined as the v alue of the internal equivalent capacita nc e which is c alc ulate d fr om t he operating current consum ption wi thout load .

Symbol Parameter VCC TA





C to



CUnits Conditions

(V) Min Typ Max Min Max

tPLH Propagation 2.7 7.6 14.5 1.0 17.5

15 pF

tPHL Delay Time 10.1 18.0 1.0 21.0 CL

50 pF

Dn to On3.3

0.3 5.9 9.3 1.0 11.0 CL

15 pF

8.4 12.8 1.0 14.5 CL

50 pF

tPLH Propagation 2.7 8.2 15.6 1.0 18.5

15 pF

tPHL Delay Time 10.7 19.1 1.0 22.0 CL

50 pF

LE to On3.3

0.3 6.4 10.1 1.0 12.0 CL

15 pF

8.9 13.6 1.0 15.5 CL

50 pF

tPZL 3-STAT E Output 2.7 7.8 15.0 1.0 18.5

15 pF, RL

1 k

tPZH Enable Time 10.3 18.5 1.0 22.0 CL

50 pF, RL

1 k

3.3

0.3 6.1 9.7 1.0 12.0 CL

15 pF, RL

1 k

8.6 13.2 1.0 15.5 CL

50 pF, RL

1 k

tPLZ 3-STATE Output 2.7 12.1 19.1 1.0 22.0 ns CL

50 pF, RL

1 k

tPHZ Disable Time 3.3

0.3 10.1 13.6 1.0 15.5 CL

50 pF, RL

1 k

tWLE Pulse 2.7 6.5 7.5 ns

Width 3.3

0.3 5.0 5.0

tSSetup Time 2.7 5.0 5.0 ns

Dn to LE 3.3

0.3 3.5 3.5

tHHold Time 2.7 1.5 1.5 ns

Dn to LE 3.3

0.3 1.5 1.5

tOSHL Output to Output 2.7 1.5 1.5 ns CL

50 pF

tOSLH Skew (Note 4) 2.3 1.5 1.5

Symbol Parameter TA





C to



CUnits

Min Typ Max Min Max

CIN Input Capaci tance 4 10 10 pF

COUT Output Capacitance 6 pF

CPD Power Dissipation 27 pF

Capacitance (Note 5)

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74LVX573

Physical Dimensions inches (millimeters) unless otherwise noted

20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide

Package Number M20B

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74LVX573

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

Package Number M20D

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74LVX573 Low Voltage Octal Latch with 3-STATE Outputs

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

20-Lea d Th in S hri nk Sm all Ou tlin e Pack age (TSSOP ), JED EC MO-1 53, 4.4mm Wide

Package Number MTC20

Fairchild does not assum e any responsibility for use of any circuitry described, no cir cuit patent licenses ar e implied and

Fairchild reserves the right at any time without notice to change said circuitry and specifications.

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