HEXFET® Power MOSFET
This Stripe Planar design of HEXFET® Power MOSFETs
utilizes the lastest processing techniques to achieve
extremely low on-resistance per silicon area. Additional
features of this HEXFET power MOSFET are a 175°C
junction operating temperature, fast switching speed and
improved repetitive avalanche rating. These benefits
combine to make this design an extremely efficient and
reliable device for use in a wide variety of applications.
S
D
G
VDSS = 30V
RDS(on) = 3.3mΩ
ID = 75A
Description
07/14/10
www.irf.com 1
Benefits
IRF1503SPbF
IRF1503LPbF
D2Pak
IRF1503SPbF
TO-262
IRF1503LPbF
Parameter Typ. Max. Units
RθJC Junction-to-Case ––– 0.75
RθCS Case-to-Sink, Flat, Greased Surface 0.50 ––– °C/W
RθJA Junction-to-Ambient ––– 62
Thermal Resistance
Parameter Max. Units
ID @ TC = 25°C Continuous Drain Current, VGS @ 10V (Silicon limited) 190
ID @ TC = 100°C Continuous Drain Current, VGS @ 10V (See Fig.9) 130 A
ID @ TC = 25°C Continuous Drain Current, VGS @ 10V (Package limited) 75
IDM Pulsed Drain Current 960
PD @TC = 25°C Power Dissipation 200 W
Linear Derating Factor 1.3 W/°C
VGS Gate-to-Source Voltage ± 20 V
EAS Single Pulse Avalanche Energy510 mJ
EAS (tested) Single Pulse Avalanche Energy Tested Value980
IAR Avalanche CurrentSee Fig.12a, 12b, 15, 16 A
EAR Repetitive Avalanche EnergymJ
TJOperating Junction and -55 to + 175 °C
TSTG Storage Temperature Range
Soldering Temperature, for 10 seconds 300 (1.6mm from case )
Mounting Torque, 6-32 or M3 screw 10 lbf•in (1.1N•m)
Absolute Maximum Ratings
lAdvanced Process Technology
lUltra Low On-Resistance
l175°C Operating Temperature
lFast Switching
lRepetitive Avalanche Allowed up to Tjmax
PD - 95432A
Typical Applications
l
Industrial Motor Drive
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Parameter Min. Typ. Max. Units Conditions
V(BR)DSS Drain-to-Source Breakdown Voltage 30 ––– ––– V VGS = 0V, ID = 250µA
∆V(BR)DSS/∆TJBreakdown Voltage Temp. Coefficient ––– 0.028 ––– V/°C Reference to 25°C, ID = 1mA
RDS(on) Static Drain-to-Source On-Resistance ––– 2.6 3.3 mΩVGS = 10V, ID = 140A
VGS(th) Gate Threshold Voltage 2.0 ––– 4.0 V VDS = 10V, ID = 250µA
gfs Forward Transconductance 75 ––– ––– S VDS = 25V, ID = 140A
––– ––– 20 µA VDS = 30V, VGS = 0V
––– ––– 250 VDS = 24V, VGS = 0V, TJ = 150°C
Gate-to-Source Forward Leakage ––– ––– 200 VGS = 20V
Gate-to-Source Reverse Leakage ––– ––– -200 nA VGS = -20V
QgTotal Gate Charge ––– 130 200 ID = 140A
Qgs Gate-to-Source Charge ––– 36 54 nC VDS = 24V
Qgd Gate-to-Drain ("Miller") Charge ––– 41 62 VGS = 10V
td(on) Turn-On Delay Time ––– 17 ––– VDD = 15V
trRise Time ––– 130 ––– ID = 140A
td(off) Turn-Off Delay Time ––– 59 ––– RG = 2.5Ω
tfFall Time ––– 48 ––– VGS = 10V
Between lead,
––– ––– 6mm (0.25in.)
from package
and center of die contact
Ciss Input Capacitance ––– 5730 ––– VGS = 0V
Coss Output Capacitance ––– 2250 ––– pF VDS = 25V
Crss Reverse Transfer Capacitance ––– 290 ––– ƒ = 1.0MHz, See Fig. 5
Coss Output Capacitance ––– 7580 ––– VGS = 0V, VDS = 1.0V, ƒ = 1.0MHz
Coss Output Capacitance ––– 2290 ––– VGS = 0V, VDS = 24V, ƒ = 1.0MHz
Coss eff. Effective Output Capacitance ––– 3420 ––– VGS = 0V, VDS = 0V to 24V
nH
Electrical Characteristics @ TJ = 25°C (unless otherwise specified)
LDInternal Drain Inductance
LSInternal Source Inductance ––– –––
S
D
G
IGSS
ns
5.0
13
IDSS Drain-to-Source Leakage Current
S
D
G
Parameter Min. Typ. Max. Units Conditions
ISContinuous Source Current MOSFET symbol
(Body Diode) ––– ––– showing the
ISM Pulsed Source Current integral reverse
(Body Diode) ––– ––– p-n junction diode.
VSD Diode Forward Voltage ––– ––– 1.3 V TJ = 25°C, IS = 140A, VGS = 0V
trr Reverse Recovery Time ––– 71 110 ns TJ = 25°C, IF = 140A
Qrr Reverse RecoveryCharge ––– 110 170 nC di/dt = 100A/µs
ton Forward Turn-On Time Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
Source-Drain Ratings and Characteristics
190
960
A
Repetitive rating; pulse width limited by
max. junction temperature. (See fig. 11).
Starting TJ = 25°C, L = 0.049mH
RG = 25Ω, IAS = 140A. (See Figure 12).
ISD ≤ 140A, di/dt ≤ 110A/µs, VDD ≤ V(BR)DSS,
TJ ≤ 175°C
Pulse width ≤ 400µs; duty cycle ≤ 2%.
Notes:
Coss eff. is a fixed capacitance that gives the same charging time
as Coss while VDS is rising from 0 to 80% VDSS .
Limited by TJmax , see Fig.12a, 12b, 15, 16 for typical repetitive
avalanche performance.
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Fig 2. Typical Output CharacteristicsFig 1. Typical Output Characteristics
Fig 3. Typical Transfer Characteristics
0.1 110 100
VDS, Drain-to-Source Voltage (V)
1
10
100
1000
ID, Drain-to-Source Current (A)
4.5V
20µs PULSE WIDTH
Tj = 25°C
VGS
TOP 15V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
BOTTOM 4.5V
0. 1 110 100
VDS, Drai n-to-Source Voltage (V)
10
100
1000
ID, Drain-to-Source Current (A)
4.5V
20µs PULSE WIDTH
Tj = 175°C
VGS
TOP 1 5V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
BOTTOM 4.5V
4.0 5.0 6.0 7.0 8.0 9.0 10.0
VGS, Gate-to-Source Voltage (V)
10
100
1000
ID, Drain-to-Source Current (Α)
TJ = 25°C
TJ = 175°C
VDS = 25V
20µs PULSE WIDTH
0 40 80 120 160 200
ID, Drain-to-Source Current (A)
0
40
80
120
160
200
Gfs, Forward Transconductance (S)
TJ = 25°C
TJ = 175°C
VDS = 25V
20µs PULSE WIDTH
Fig 4. Typical Forward Transconductance
Vs. Drain Current
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Fig 8. Maximum Safe Operating Area
Fig 6. Typical Gate Charge Vs.
Gate-to-Source Voltage
Fig 5. Typical Capacitance Vs.
Drain-to-Source Voltage
Fig 7. Typical Source-Drain Diode
Forward Voltage
0.0 0.4 0.8 1.2 1.6 2.0
VSD, Source-toDrain Voltage (V)
0.1
1.0
10.0
100.0
1000.0
ISD, Reverse Drain Current (A)
TJ = 25°C
TJ = 175°C
VGS = 0V
0 40 80 120 160 200
QG Total Gate Charge (nC)
0
4
8
12
16
20
VGS, Gate-to-Source Voltage (V)
VDS= 24V
ID= 140A
1 10 100
VDS , Drain-toSource Voltage (V)
1
10
100
1000
10000
ID, Drain-to-Source Current (A)
Tc = 25°C
Tj = 175°C
Single Pulse
1msec
10msec
OPERATION IN THIS AREA
LIMITED BY RDS(on)
100µsec
110 100
VDS, Drain-to-Source Voltage (V)
0
2000
4000
6000
8000
10000
C, Capacitance (pF)
Coss
Crss
Ciss
VGS = 0V, f = 1 MHZ
Ciss = C gs + C gd , C ds
SHORTED
Crss = C
gd
Coss = C
ds + C
gd
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Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
Fig 9. Maximum Drain Current Vs.
Case Temperature
0.01
0.1
1
0.00001 0.0001 0.001 0.01 0.1 1
Notes:
1. Duty factor D = t / t
2. Peak T = P x Z + T
1 2
JDM thJC C
P
t
t
DM
1
2
t , Rectangular Pulse Duration (sec)
Thermal Response (Z )
1
thJC
0.01
0.02
0.05
0.10
0.20
D = 0.50
SINGLE PULSE
(THERMAL RESPONSE)
25 50 75 100 125 150 175
0
40
80
120
160
200
T , Case Temperature ( C)
I , Drain Current (A)
°
C
D
LIMITED BY PACKAGE
Fig 10. Normalized On-Resistance
Vs. Temperature
-60 -40 -20 020 40 60 80 100 120 140 160 180
0.0
0.5
1.0
1.5
2.0
T , Junction Temperature ( C)
R , Drain-to-Source On Resistance
(Normalized)
J
DS(on)
°
V =
I =
GS
D
10V
240A
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Q
G
Q
GS
Q
GD
V
G
Charge
D.U.T. V
DS
I
D
I
G
3mA
V
GS
.3µF
50KΩ
.2µF
12V
Current Regulator
Same Type as D.U.T.
Current Sampling Resistors
+
-
10 V
Fig 13b. Gate Charge Test Circuit
Fig 13a. Basic Gate Charge Waveform
Fig 12c. Maximum Avalanche Energy
Vs. Drain Current
Fig 12b. Unclamped Inductive Waveforms
Fig 12a. Unclamped Inductive Test Circuit
tp
V
(BR)DSS
I
AS
Fig 14. Threshold Voltage Vs. Temperature
R
G
I
AS
0.01
Ω
t
p
D.U.T
L
VDS
+
-V
DD
DRIVER
A
15V
20V
VGS
-75 -50 -25 025 50 75 100 125 150 175 200
TJ , Temperature ( °C )
1.0
2.0
3.0
4.0
VGS(th) Gate threshold Voltage (V)
ID = 250µA
25 50 75 100 125 150 175
Starting TJ , Junction Temperature (°C)
0
200
400
600
800
1000
1200
1400
EAS , Single Pulse Avalanche Energy (mJ)
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Fig 15. Typical Avalanche Current Vs.Pulsewidth
Fig 16. Maximum Avalanche Energy
Vs. Temperature
Notes on Repetitive Avalanche Curves , Figures 15, 16:
(For further info, see AN-1005 at www.irf.com)
1. Avalanche failures assumption:
Purely a thermal phenomenon and failure occurs at a
temperature far in excess of Tjmax. This is validated for
every part type.
2. Safe operation in Avalanche is allowed as long asTjmax is
not exceeded.
3. Equation below based on circuit and waveforms shown in
Figures 12a, 12b.
4. PD (ave) = Average power dissipation per single
avalanche pulse.
5. BV = Rated breakdown voltage (1.3 factor accounts for
voltage increase during avalanche).
6. Iav = Allowable avalanche current.
7. ∆T = Allowable rise in junction temperature, not to exceed
Tjmax (assumed as 25°C in Figure 15, 16).
tav = Average time in avalanche.
D = Duty cycle in avalanche = tav ·f
ZthJC(D, tav) = Transient thermal resistance, see figure 11)
PD (ave) = 1/2 ( 1.3·BV·Iav) = DT/ ZthJC
Iav = 2DT/ [1.3·BV·Zth]
EAS (AR) = PD (ave)·tav
1.0E-07 1.0E-06 1.0E-05 1.0E-04 1.0E-03 1.0E-02 1.0E-01
tav (sec)
1
10
100
1000
10000
Avalanche Current (A)
0.05
Duty Cycle = Single Pulse
0.10
Allowed avalanche Current vs
avalanche pulsewidth, tav
assuming ∆Tj = 25°C due to
avalanche losses. Note: In no
case should Tj be allowed to
exceed Tjmax
0.01
25 50 75 100 125 150 175
Starting TJ , Junction Temperature (°C)
0
100
200
300
400
500
600
EAR , Avalanche Energy (mJ)
TOP Single Pulse
BOTTOM 50% Duty Cycle
ID = 140A
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Fig 17. Peak Diode Recovery dv/dt Test Circuit for N-Channel
HEXFET® Power MOSFETs
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
P.W. Period
di/dt
Diode Recovery
dv/dt
Ripple ≤5%
Body Diode Forward Drop
Re-Applied
Voltage
Reverse
Recovery
Current
Body Diode Forward
Current
V
GS
=10V
V
DD
I
SD
Driver Gate Drive
D.U.T. I
SD
Waveform
D.U.T. V
DS
Waveform
Inductor Curent
D = P. W .
Period
* VGS = 5V for Logic Level Devices
*
+
-
+
+
+
-
-
-
RGVDD
• dv/dt controlled by RG
• Driver same type as D.U.T.
• ISD controlled by Duty Factor "D"
• D.U.T. - Device Under Test
D.U.T
VDS
90%
10%
VGS
t
d(on)
t
r
t
d(off)
t
f
VDS
Pulse Width ≤ 1 µs
Duty Factor ≤ 0.1 %
RD
VGS
RG
D.U.T.
10V
+
-
VDD
Fig 18a. Switching Time Test Circuit
Fig 18b. Switching Time Waveforms
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D2Pak (TO-263AB) Part Marking Information
DAT E CODE
YEAR 0 = 2000
WE E K 02
A = AS S E MB L Y S I T E CODE
RECTIFIER
INTERNATIONAL PART NUMBER
P = DESIGNATES LEAD - FREE
PRODUCT (OPT IONAL)
F530S
IN THE ASS EMBLY LINE "L"
AS S E MBLED ON WW 02, 2000
T HIS IS AN IRF 530S WIT H
LOT CODE 8024 INTERNATIONAL
LOGO
RECT IFIER
LOT CODE
ASSEMBLY YEAR 0 = 2000
PART NUMBE R
DAT E CODE
LINE L
WE E K 02
OR
F530S
LOGO
ASSEMBLY
LOT CODE
D2Pak (TO-263AB) Package Outline
Dimensions are shown in millimeters (inches)
Notes:
1. For an Automotive Qualified version of this part please seehttp://www.irf.com/product-info/auto/
2. For the most current drawing please refer to IR website at http://www.irf.com/package/
IRF1503S/LPbF
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TO-262 Part Marking Information
TO-262 Package Outline
Dimensions are shown in millimeters (inches)
LOGO
RECTIFIER
INT ER NAT IONAL
LOT CODE
AS S E M B L Y
LOGO
RECTIFIER
INTERNATIONAL
DAT E CODE
WEEK 19
YEAR 7 = 1997
PART NUMBER
A = ASSEMBLY SITE CODE
OR
PRODUCT (OPT IONAL)
P = DE S I GN AT E S L E AD- F R E E
EXAMPLE: THIS IS AN IRL3103L
LOT CODE 1789
AS S E MB L Y
PART NUMBER
DATE CODE
WEEK 19
LINE C
LOT CODE
YEAR 7 = 1997
AS SEMBLED ON WW 19, 1997
IN THE AS SEMBLY LINE "C"
Notes:
1. For an Automotive Qualified version of this part please seehttp://www.irf.com/product-info/auto/
2. For the most current drawing please refer to IR website at http://www.irf.com/package/
IRF1503S/LPbF
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IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information. 07/2010
Data and specifications subject to change without notice.
This product has been designed and qualified for Industrial market.
Qualification Standards can be found on IR’s Web site.
D2Pak Tape & Reel Information
Dimensions are shown in millimeters (inches)
3
4
4
TRR
FEED DIRECTION
1.85 (.073)
1.65 (.065)
1.60 (.063)
1.50 (.059)
4.10 (.161)
3.90 (.153)
TRL
FEED DIRECTION
10.90 (.429)
10.70 (.421)
16.10 (.634)
15.90 (.626)
1.75 (.069)
1.25 (.049)
11.60 (.457)
11.40 (.449) 15.42 (.609)
15.22 (.601)
4.72 (.136)
4.52 (.178)
24.30 (.957)
23.90 (.941)
0.368 (.0145)
0.342 (.0135)
1.60 (.063)
1.50 (.059)
13.50 (.532)
12.80 (.504)
330.00
(14.173)
MAX.
27.40 (1.079)
23.90 (.941)
60.00 (2.362)
MIN.
30.40 (1.197)
MAX.
26.40 (1.039)
24.40 (.961)
NOTES :
1. COMFORMS TO EIA-418.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION MEASURED @ HUB.
4. INCLUDES FLANGE DISTORTION @ OUTER EDGE.
