General Description
The MAX1144/MAX1145 are 150ksps, 14-bit ADCs.
These serially interfaced ADCs connect directly to
SPI™, QSPI™, and MICROWIRE™ devices without
external logic. They combine an input scaling network,
internal track/hold, clock, and three general-purpose
digital output pins (for external multiplexer or PGA con-
trol) in a 20-pin SSOP package. The excellent dynamic
performance (THD ≥90dB), high speed (150ksps in
bipolar mode), and low power (8.0mA) of these ADCs
make them ideal for applications such as industrial
process control, instrumentation, and medical applica-
tions.
The MAX1144 accepts input signals of 0 to +6V (unipo-
lar) or ±6V (bipolar), while the MAX1145 accepts input
signals of 0 to +2.048V (unipolar) or ±2.048V (bipolar).
Operating from a single 3.135V to 3.465V analog digital
supply, powerdown modes reduce current consump-
tion to 0.15mA at 10ksps and further reduce supply
current to less than 20µA slower data rates.
A serial strobe output (SSTRB) allows direct connection
to the TMS320 family digital-signal processors. The
MAX1144/MAX1145 user can select either the internal
clock or an external serial-interface clock for the ADC to
perform analog-to-digital conversions.
The MAX1144/MAX1145 feature internal calibration cir-
cuitry to correct linearity and offset errors. On-demand
calibration allows the user to optimize performance.
Three user-programmable logic outputs are provided
for the control of an 8-channel mux or PGA.
The MAX1144/MAX1145 are available in a 20-pin SSOP
package and are fully specified over the -40°C to
+85°C temperature range.
Applications
Industrial Process Control
Industrial I/O Modules
Data-Acquisition Systems
Medical Instruments
Portable and Battery-Powered Equipment
Features
♦150ksps (Bipolar) and 125ksps (Unipolar)
Sampling ADC
♦14 Bits, No Missing Codes
♦1LSB INL Guaranteed
♦-100dB THD
♦3.3V Single-Supply Operation
♦Low-Power Operation
5mA typ (Unipolar Mode)
♦1.2µA Shutdown Mode
♦Software-Configurable Unipolar and Bipolar Input
Ranges
0 to +6V and ±6V (MAX1144)
0 to +2.048V and ±2.048V (MAX1145)
♦Internal or External Clock
♦SPI/QSPI/MICROWIRE TMS320-Compatible Serial
Interface
♦Three User-Programmable Logic Outputs
♦Small 20-Pin SSOP Package
MAX1144/MAX1145
14-Bit ADCs, 150ksps, 3.3V Single Supply
________________________________________________________________ Maxim Integrated Products 1
20
19
18
17
16
15
14
13
1
2
3
4
5
6
7
8
AIN
AGND
CREF
CSAVDD
AGND
AVDD
REF
TOP VIEW
DIN
DVDD
DGND
SCLKP1
P2
SHDN
DGND
12
11
9
10
RST
DOUTSSTRB
PO
MAX1144
MAX1145
SSOP
Pin Configuration
Ordering Information
19-2465; Rev 0; 4/02
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
Ordering Information continued at end of data sheet.
Functional Diagram and Typical Application Circuit appear
at end of data sheet.
PART TEMP
RANGE
PIN-
PACKAGE
INL
(LSB)
MAX1144ACAP 0°C to +70°C 20 SSOP ±1
MAX1144BCAP 0°C to +70°C 20 SSOP ±2
MAX1144AEAP -40°C to +85°C 20 SSOP ±1
MAX1144BEAP -40°C to +85°C 20 SSOP ±2
SPI and QSPI are trademarks of Motorola, Inc.
MICROWIRE is a trademark of National Semiconductor, Corp.
MAX1144/MAX1145
14-Bit ADCs, 150ksps, 3.3V Single Supply
2 _______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
(AVDD = DVDD = 3.3V ±5%, fSCLK = 3.6MHz, external clock (50% duty cycle), 24 clocks/conversion (150ksps), bipolar input, VREF =
2.048V, CREF = 4.7µF, CCREF = 1µF, TA= TMIN to TMAX, unless otherwise noted. Typical values are at TA= +25°C.)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
AVDD to AGND, DVDD to DGND ..............................-0.3V to +6V
AGND to DGND.....................................................-0.3V to +0.3V
AIN to AGND ....................................................................±16.5V
CREF, REF to AGND................................-0.3V to (AVDD + 0.3V)
Digital Inputs to DGND.............................................-0.3V to +6V
Digital Outputs to DGND .........................-0.3V to (DVDD + 0.3V)
Continuous Power Dissipation (TA= +70°C)
20-Pin SSOP (derate 8.00mW/°C above +70°C) .........640mW
Operating Temperature Ranges
MAX114_ _CAP...................................................0°C to +70°C
MAX114_ _EAP................................................-40°C to +85°C
Storage Temperature Range .............................-60°C to +150°C
Junction Temperature......................................................+150°C
Lead Temperature (soldering, 10s) .................................+300°C
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
DC ACCURACY (Note 1)
Resolution 14 Bits
MAX114_A ±1
Relative Accuracy INL Bipolar mode (Note 2) MAX114_B ±2LSB
No Missing Codes 14 Bits
MAX114_A -1 +1
Differential Nonlinearity DNL Bipolar mode MAX114_B -1.00 +1.75 LSB
Transition Noise 0.47 LSBRMS
Unipolar ±4
Offset Error Bipolar ±6mV
Unipolar ±0.2
Gain Error (Note 3) Bipolar ±0.3 %FSR
Offset Drift (Bipolar and Unipolar) Excluding reference drift ±1 ppm/°C
Gain Drift (Bipolar and Unipolar) Excluding reference drift ±4 ppm/°C
D YNA M IC SPEC IF IC A T IO N S ( 5 k Hz SINE- WAVE IN PU T, 1 50 k s ps , 3 .6M H Z C L O CK , BIPO LA R IN PU T M O DE. M A X1 14 4 , 1 2 VP-P. M A X1 14 5 ,
4 .09 6 VP-P.)
fIN = 5kHz 78 82
Signal-to-Noise Plus Distortion
(SINAD) fIN = 75kHz 81 dB
fIN = 5kHz 78 82
Signal-to-Noise Ratio
(SNR) fIN = 75kHz 81 dB
fIN = 5kHz -100 -90
Total Harmonic Distortion
(THD) fIN = 75kHz -94 dB
fIN = 5kHz 92 105
Spurious-Free-Dynamic Range
(SFDR) fIN = 75kHz 98 dB
ANALOG INPUT
Unipolar 0 +6
MAX1144 Bipolar -6 +6
Unipolar 0 +2.048
Input Range
MAX1145 Bipolar -2.048 +2.048
V
MAX1144/MAX1145
14-Bit ADCs, 150ksps, 3.3V Single Supply
_______________________________________________________________________________________ 3
ELECTRICAL CHARACTERISTICS (continued)
(AVDD = DVDD = 3.3V ±5%, fSCLK = 3.6MHz, external clock (50% duty cycle), 24 clocks/conversion (150ksps), bipolar input, VREF =
2.048V, CREF = 4.7µF, CCREF = 1µF, TA= TMIN to TMAX, unless otherwise noted. Typical values are at TA= +25°C.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Unipolar 7.5 10.5
MAX1144 Bipolar 5.9 8.4
Unipolar 100 1000
Input Impedance
MAX1145 Bipolar 3.4 5.3
kΩ
Input Capacitance 32 pF
CONVERSION RATE
Internal Clock Frequency 3 MHz
Aperture Delay tAD 10 ns
Aperture Jitter tAJ 50 ps
MODE 1 (24 EXTERNAL CLOCK CYCLES PER CONVERSION)
Unipolar 0.1 3.0
External Clock Frequency fSCLK Bipolar 0.1 3.6 MHz
Unipolar 4.17 125
Sample Rate fS =
fSCLK / 24 Bipolar 4.17 150 ksps
Unipolar 8 240
Conversion Time (Note 4) tCONV+ACQ
= 24 / fSCLK Bipolar 6.7 240
µs
MODE 2 (INTERNAL CLOCK)
External Clock Frequency
(Data Transfer Only) 4 MHz
Conversion Time (SSTRB low pulse width) 5.3 7 µs
Unipolar 1.67
Acquisition Time (Note 5) Bipolar 1.39 µs
MODE 3 (32 EXTERNAL CLOCK CYCLES PER CONVERSION)
External Clock Frequency fSCLK Unipolar or bipolar 0.1 3.6 MHz
Sample Rate fS =
fSCLK / 32 Unipolar or bipolar 3.125 112 ksps
Conversion Time (Note 4) tCONV+ACQ
= 32 / fSCLK Unipolar or bipolar 8.89 320 µs
EXTERNAL REFERENCE
Input Range (Notes 6, 7) 1.9 2.048 2.2 V
VREF = 2.048V, fSCLK = 3.6MHz 110
VREF = 2.048V, fSCLK = 0 100Input Current
In power-down, fSCLK = 0 0.1
µA
DIGITAL INPUTS
Input High Voltage VIH 2.4 V
Input Low Voltage VIL 0.8 V
Input Leakage IIN VIN = 0 or DVDD -1 +1 µA
MAX1144/MAX1145
14-Bit ADCs, 150ksps, 3.3V Single Supply
4 _______________________________________________________________________________________
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Input Hysteresis VHYST 0.2 V
Input Capacitance CIN 10 pF
DIGITAL OUTPUTS
Output High Voltage VOH ISOURCE = 0.5mA DVDD -
0.5 V
ISINK = 5mA 0.4
Output Low Voltage VOL ISINK = 16mA 0.8 V
Three-State Leakage Current ILCS = DVDD -10 +10 µA
Three-State Output Capacitance CS = DVDD 10 pF
POWER SUPPLIES
Analog Supply AVDD 3.135 3.3 3.465 V
Digital Supply DVDD 3.135 3.3 3.465 V
Unipolar mode 3.9 8
Bipolar mode 7 11 mA
Analog Supply Current IANALOG
SHDN = 0, or software power-down mode 0.1 10 µA
Unipolar or bipolar mode 1 2 mA
Digital Supply Current IDIGITAL SHDN = 0, or software power-down mode 1.1 10 µA
Power-Supply Rejection Ratio
(Note 8) PSRR AVDD = DVDD = 3.135V to 3.465V 65 dB
ELECTRICAL CHARACTERISTICS (continued)
(AVDD = DVDD = 3.3V ±5%, fSCLK = 3.6MHz, external clock (50% duty cycle), 24 clocks/conversion (150ksps), bipolar input, VREF =
2.048V, CREF = 4.7µF, CCREF = 1µF, TA= TMIN to TMAX, unless otherwise noted. Typical values are at TA= +25°C.)
TIMING CHARACTERISTICS (Figures 5 and 6)
(AVDD = DVDD = 3.3V ±5%, TA= TMIN to TMAX, unless otherwise noted.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
DIN to SCLK Setup tDS 50 ns
DIN to SCLK Hold tDH 0ns
SCLK to DOUT Valid tDO 70 ns
CS Fall to DOUT Enable tDV CLOAD = 50pF 80 ns
CS Rise to DOUT Disable tTR CLOAD = 50pF 80 ns
CS to SCLK Rise Setup tCSS 100 ns
CS to SCLK Rise Hold tCSH 0ns
SCLK High Pulse Width tCH 120 ns
SCLK Low Pulse Width tCL 120 ns
SCLK Fall to SSTRB tSSTRB CLOAD = 50pF 80 ns
CS Fall to SSTRB Enable tSDV CLOAD = 50pF, external clock mode 80 ns
CS Rise to SSTRB Disable tSTR CLOAD = 50pF, external clock mode 80 ns
SSTRB Rise to SCLK Rise tSCK Internal clock mode 0 ns
RST Pulse Width tRS 278 70 ns
MAX1144/MAX1145
14-Bit ADCs, 150ksps, 3.3V Single Supply
_______________________________________________________________________________________ 5
TIMING CHARACTERISTICS (Figures 5 and 6) (continued)
(AVDD = DVDD = 3.3V ±5%, TA= TMIN to TMAX, unless otherwise noted.)
Note 1: Tested at AVDD = DVDD = 3.3V, bipolar input mode.
Note 2: Relative accuracy is the deviation of the analog value at any code from its theoretical value after the gain error and offset
error have been nullified.
Note 3: Offset nullified.
Note 4: Conversion time is defined as the number of clock cycles multiplied by the clock period; clock has 50% duty cycle. Includes
the acquisition time.
Note 5: Acquisition time is 5 clock cycles in short acquisition mode and 13 clock cycles in long acquisition mode.
Note 6: Performance is limited by the converter’s noise floor, typically 300µVP-P.
Note 7: When an external reference has a different voltage than the specified typical value, the full scale of the ADC scales propor-
tionally.
Note 8: Defined as the change in positive full scale caused by a ±5% variation in the nominal supply voltage.
Typical Operating Characteristics
(MAX1144/MAX1145, AVDD = DVDD = 3.3V, fSCLK = 3.6MHz, external clock (50% duty cycle), 24 clocks/conversion (150ksps),
bipolar input, REF = 2.048V, 4.7µF on REF, 1µF on CREF, TA= +25°C, unless otherwise noted.)
INTEGRAL NONLINEARITY
vs. DIGITAL OUTPUT CODE
MAX1144/45 toc01
DIGITAL OUTPUT CODE
INTEGRAL NONLINEARITY (LSB)
13649
119438531
102373413
5119
6825
1707
-0.8
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0.8
1.0
-1.0
1
15355
DIFFERENTIAL NONLINEARITY
vs. DIGITAL OUTPUT CODE
MAX1144/45 toc02
DIGITAL OUTPUT CODE
DIFFERENTIAL NONLINEARITY (LSB)
13649
119438531
102373413
5119
6825
1707
-0.8
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0.8
1.0
-1.0
1
15355
TOTAL SUPPLY CURRENT
vs. TEMPERATURE
MAX1144/45 toc03
TEMPERATURE (°C)
TOTAL SUPPLY CURRENT (mA)
806020 400-20
8.1
8.2
8.3
8.4
8.5
8.6
8.7
8.8
8.9
9.0
8.0
-40
A: AVDD, DVDD = 3.135V
B: AVDD, DVDD = 3.3V
C: AVDD, DVDD = 3.465V
C
B
A
MAX1144/MAX1145
6 _______________________________________________________________________________________
Typical Operating Characteristics (continued)
(MAX1144/MAX1145, AVDD = DVDD = 3.3V, fSCLK = 3.6MHz, external clock (50% duty cycle), 24 clocks/conversion (150ksps),
bipolar input, REF = 2.048V, 4.7µF on REF, 1µF on CREF, TA= +25°C, unless otherwise noted.)
OFFSET VOLTAGE
vs. TEMPERATURE
MAX1144/45 toc04
TEMPERATURE (°C)
OFFSET ERROR (mV)
806020 400-20
-2.5
-2.0
-1.0
-0.5
0
-40
A: AVDD, DVDD = 3.135V
B: AVDD, DVDD = 3.3V
C: AVDD, DVDD = 3.465V
C
B
A
-1.5
GAIN ERROR
vs. TEMPERATURE
MAX1144/45 toc05
TEMPERATURE (°C)
GAIN ERROR (% FULL SCALE)
806020 400-20
0.01
0
0.03
0.02
0.04
0.05
0.06
-40
A: AVDD, DVDD = 3.135V
B: AVDD, DVDD = 3.3V
C: AVDD, DVDD = 3.465V
C
B
A
TOTAL SUPPLY CURRENT vs.
CONVERSION RATE (USING SHUTDOWN)
MAX1144/45 toc06
CONVERSION RATE (ksps)
TOTAL SUPPLY CURRENT (mA)
1000100101
0.01
100
10
1
0.1
0
FFT PLOT
MAX1144/45 toc07
FREQUENCY (kHz)
AMPLITUDE (dB)
605040302010
-100
-80
-60
-40
-20
0
-120
070
fSAMPLE = 150kHz
fIN = 5kHz
SINAD PLOT
MAX1144/45 toc08
FREQUENCY (kHz)
AMPLITUDE (dB)
101
10
20
30
40
50
60
70
80
90
100
0
0.1 100
fSAMPLE = 150kHz
SFDR PLOT
MAX1144/45 toc09
FREQUENCY (kHz)
AMPLITUDE (dB)
101
10
20
30
40
50
60
70
80
90
100
110
120
0
0.1 100
fSAMPLE = 150kHz
THD PLOT
MAX1144/45 toc10
FREQUENCY (kHz)
AMPLITUDE (dB)
101
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
-110
0.1 100
fSAMPLE = 150kHz
14-Bit ADCs, 150ksps, 3.3V Single Supply
MAX1144/MAX1145
14-Bit ADCs, 150ksps, 3.3V Single Supply
_______________________________________________________________________________________ 7
Pin Description
PIN NAME FUNCTION
1 REF ADC Reference Input. Connect a 2.048V voltage source to REF. Bypass REF to AGND with 4.7µF capacitor.
2AV
DD Analog Supply. Connect to pin 4.
3 AGND Analog Ground. This is the primary analog ground (star ground).
4AV
DD Analog Supply, 3.3V ±5%. Bypass AVDD to AGND (pin 3) with a 0.1µF capacitor.
5 DGND Digital Ground
6SHDN Shutdown Control Input. Drive SHDN low to put the ADC in shutdown mode.
7 P2 User-Programmable Output 2
8 P1 User-Programmable Output 1
9 P0 User-Programmable Output 0
10 SSTRB
Serial Strobe Output. In internal clock mode, SSTRB goes low when the ADC begins a conversion and goes
high when the conversion is finished. In external clock mode, SSTRB pulses high for one clock period before
the MSB decision. It is high impedance when CS is high in external clock mode.
11 DOUT Serial Data Output. MSB first, straight binary format for unipolar input, two’s complement for bipolar input.
Each bit is clocked out of DOUT at the falling edge of SCLK.
12 RST Reset Input. Drive RST low to put the device in the power-on default mode. See the Power-On Reset section.
13 SCLK Serial Data Clock Input. Serial data on DIN is loaded on the rising edge of SCLK, and serial data is updated
on DOUT on the falling edge of SCLK. In external clock mode SCLK sets the conversion speed.
14 DGND Digital Ground. Connect to pin 5.
15 DVDD Digital Supply, 3.3V ±5%. Bypass DVDD to DGND (pin 14) with a 0.1µF capacitor.
16 DIN Serial Data Input. Serial data on DIN is latched on the rising edge of SCLK.
17 CS Chip Select Input. Drive CS low to enable the serial interface. When CS is high DOUT is high impedance. In
external clock mode SSTRB is high impedance when CS is high.
18 CREF Reference Buffer Bypass. Bypass CREF to AGND (pin 3) with 1µF.
19 AGND Analog Ground. Connect to pin 3.
20 AIN Analog Input
MAX1144/MAX1145
Detailed Description
The MAX1144/MAX1145 ADCs use a successive-
approximation technique and input track/hold (T/H) cir-
cuitry to convert an analog signal to a 14-bit digital
output. The MAX1144/MAX1145 easily interface to
microprocessors (µPs). The data bits can be read
either during the conversion in external clock mode or
after the conversion in internal clock mode.
In addition to a 14-bit ADC, the MAX1144/MAX1145
include an input scaler, an internal digital microcontroller,
calibration circuitry, and an internal clock generator.
The input scaler for the MAX1144 enables conversion
of input signals ranging from 0 to +6V (unipolar input)
or ±6V (bipolar input). The MAX1145 accepts 0 to
+2.048V (unipolar input) or ±2.048V (bipolar input).
Input range is software selectable.
Calibration
To minimize linearity, offset, and gain errors, the
MAX1144/MAX1145 have on-demand software calibra-
tion. Initiate calibration by writing a control byte with bit
M1 = 0 and bit M0 = 1 (Table 1). Select internal or exter-
nal clock for calibration by setting the INT/EXT bit in the
control byte. Calibrate the MAX1144/MAX1145 with the
same clock mode used for performing conversions.
Offsets resulting from synchronous noise (such as the
conversion clock) are canceled by the MAX1144/
MAX1145’s calibration circuitry. However, because the
magnitude of the offset produced by a synchronous
signal depends on the signal’s shape, recalibration
may be appropriate if the shape or relative timing of the
clock, or other digital signals change, as may occur if
more than one clock signal or frequency is used.
Input Scaler
The MAX1144/MAX1145 have an input scaler, which
allows conversion of true bipolar input voltages while
operating from a single 3.3V supply. The input scaler
attenuates and shifts the input as necessary to map the
external input range to the input range of the internal
ADC. The MAX1144 analog input range is 0 to +6V
(unipolar) or ±6V (bipolar). The MAX1145 analog input
14-Bit ADCs, 150ksps, 3.3V Single Supply
8 _______________________________________________________________________________________
BIT NAME DESCRIPTION
7 (MSB) START The first logic “1” bit after CS goes low defines the beginning of the control byte.
6 UNI/BIP
1 = unipolar, 0 = bipolar. Selects unipolar or bipolar conversion mode. In unipolar mode, analog input
signals from 0 to +6V (MAX1144) or 0 to +VREF (MAX1145) can be converted. In bipolar mode, analog
input signals from –6V to +6V (MAX1144) or –VREF to +VREF (MAX1145) can be converted.
5 INT/EXT Selects the internal or external conversion clock. 1 = internal, 0 = external.
M1 M0 Mode
0 0 24 external clocks per conversion (short acquisition mode)4M1
0 1 Start calibration: starts internal calibration
1 0 Software power-down mode
3M0 1 1 32 external clocks per conversion (long acquisition mode)
2P2
1P1
0 (LSB) P0
These three bits are stored in a port register and output to pins P2, P1, P0 for use in addressing a mux
or PGA. These three bits are updated in the port register simultaneously when a new control byte is
written.
Table 1. Control Byte Format
Figure 1. Equivalent Input Circuit
VOLTAGE
REFERENCE
BIPOLAR
UNIPOLAR
TRACK
S2
S3
S1 = BIPOLAR/UNIPOLAR
S2, S3 = T/H SWITCH
R2 = 7.6kΩ (MAX1144)
OR 2.5kΩ (MAX1145)
R3 = 3.9kΩ (MAX1144)
OR INFINITY (MAX1145)
HOLD HOLD
T/H OUT
CHOLD
32pF
R1
2.5kΩ
R2
R3
AIN
TRACK
range is 0 to +2.048V (unipolar) or ±2.048V (bipolar).
Unipolar and bipolar mode selection is configured with
bit 6 of the serial control byte (Table 1).
Figure 1 shows the equivalent input circuit of the
MAX1144/MAX1145. The resistor network on the analog
input provides ±16.5V fault protection. This circuit limits
the current going into or out of the pin to less than 2mA.
The overvoltage protection is active even if the device
is in a power-down mode, or if AVDD = 0.
Digital Interface
The digital interface pins consist of SHDN, RST, SSTRB,
DOUT, SCLK, DIN, and CS. Bringing SHDN low places
the MAX1144/MAX1145 in its 1.2µA shutdown mode. A
logic low on RST halts the MAX1144/MAX1145 opera-
tion and returns the part to its power-on-reset state.
In external clock mode, SSTRB is low and pulses high
for one clock cycle at the start of conversion. In internal
clock mode, SSTRB goes low at the start of the conver-
sion, and goes high to indicate that the conversion is
finished.
The DIN input accepts control byte data, which is
clocked in on each rising edge of SCLK. After CS goes
low or after a conversion or calibration completes, the
first logic “1” clocked into DIN is interpreted as the
START bit, the MSB of the 8-bit control byte.
The SCLK input is the serial-data-transfer clock which
clocks data in and out of the MAX1144/MAX1145.
SCLK also drives the ADC conversion steps in external
clock mode (see the Internal and External Clock Modes
section).
DOUT is the serial output of the conversion result.
DOUT is updated on the falling edge of SCLK. DOUT is
high impedance when CS is high.
CS must be low for the MAX1144/MAX1145 to accept a
control byte. The serial interface is disabled when CS is
high.
User-Programmable Outputs
The MAX1144/MAX1145 have three user-programma-
ble outputs: P0, P1, and P2. The power-on default state
for the programmable outputs is zero. These are push-
pull CMOS outputs suitable for driving a multiplexer, a
PGA or other signal preconditioning circuitry. Bits 0, 1,
and 2 of the control byte control the user-programma-
ble outputs (Tables 1, 2).
MAX1144/MAX1145
14-Bit ADCs, 150ksps, 3.3V Single Supply
_______________________________________________________________________________________ 9
ACQUISITION CONVERSIONIDLE IDLE
SCLK
DOUT
A/D
STATE
DIN
SSTRB
CS
41812
START M1 M0
P2
P1 P0
15 21 24
B10 B9B12 B11
B8
B7 B2
B13
MSB
B0
LSB
FILLED WITH
ZEROS
B1 X X
tACQ
UNI/
BIP
INT/
EXT
Figure 2. Short Acquisition Mode (24 Clock Cycles) External Clock
OUTPUT PIN
PROGRAMMED
THROUGH CONTROL
BYTE
POWER-ON OR
RST DEFAULT DESCRIPTION
P2 Bit 2 0
P1 Bit 1 0
P0 Bit 0 0
User-programmable outputs follow the state of the control
byte’s three LSBs, and are updated simultaneously when a
new control byte is written. Outputs are push-pull. In hardware
and software shutdown, these outputs are unchanged and
remain low impedance.
Table 2. User-Programmable Outputs
MAX1144/MAX1145
The user-programmable outputs are set to zero during
power-on reset or when RST goes low. During hardware
or software shutdown, P0, P1, and P2 are unchanged
and remain low-impedance.
Starting a Conversion
Start a conversion by clocking a control byte into the
device’s internal shift register. With CS low, each rising
edge on SCLK clocks a bit from DIN into the
MAX1144/MAX1145’s internal shift register. After CS
goes low or after a conversion or calibration completes,
the first arriving logic “1” is defined as the start bit of
the control byte. Until this first start bit arrives, any num-
ber of logic “0” bits can be clocked into DIN with no
effect. If at any time during acquisition or conversion
CS is brought high and then low again, the part is
placed into a state where it can recognize a new start
bit. If a new start bit occurs before the current conver-
sion is complete, the conversion is aborted and a new
acquisition is initiated.
Internal and External Clock Modes
The MAX1144/MAX1145 use either the external serial
clock or the internal clock to perform the successive-
approximation conversion. In both clock modes, the
external clock shifts data in and out of the
MAX1144/MAX1145. Bit 5 (INT/EXT) of the control byte
programs the clock mode.
External Clock
In external clock mode, the external clock not only
shifts data in and out, but also drives the ADC conver-
sion steps.
In short acquisition mode, SSTRB pulses high for one
clock period after the seventh falling edge of SCLK fol-
lowing the start bit. The MSB of the conversion is avail-
able at DOUT on the eighth falling edge of SCLK
(Figure 2).
14-Bit ADCs, 150ksps, 3.3V Single Supply
10 ______________________________________________________________________________________
SCLK
DOUT
A/D
STATE
DIN
SSTRB
CS
418
START M1 M0
P2
P1 P0
14 29 32
B2B12
B13
MSB B11
B1
XX
B0
LSB
FILLED WITH
ZEROS
tACQ
ACQUISITION CONVERSIONIDLE IDLE
15
UNI/
BIP
INT/
EXT
Figure 3. Long Acquisition Mode (32 Clock Cycles) External Clock
tSDV
tSSTRB tSSTRB
tSTR
P1 CLOCKED IN
SSTRB
SCLK
CS
Figure 4. External Clock Mode SSTRB Detailed Timing
MAX1144/MAX1145
14-Bit ADCs, 150ksps, 3.3V Single Supply
______________________________________________________________________________________ 11
SCLK
DOUT
DIN
SSTRB
CS
418
START M1 M0
P2
P1 P0
921 24
B2B12
B13
MSB
B1
XX
B0
LSB
FILLED WITH
ZEROS
tACQ
tCONV
UNI/
BIP
INT/
EXT
Figure 5. Internal Clock Mode Timing, Short Acquisition, Bipolar Mode
In long acquisition mode, SSTRB pulses high for one
clock period after the 15th falling edge of SCLK follow-
ing the start bit. The MSB of the conversion is available
at DOUT on the 16th falling edge of SCLK (Figure 3).
In external clock mode, SSTRB is high impedance
when CS is high (Figure 4). In external clock mode, CS
is normally held low during the entire conversion. If CS
goes high during the conversion SCLK is ignored until
CS goes low. This allows external clock mode to be
used with 8-bit bytes.
Internal Clock
In internal clock mode, the MAX1144/MAX1145 generate
their own conversion clock. This frees the microprocessor
from the burden of running the SAR conversion clock,
and allows the conversion results to be read back at the
processor’s convenience, at any clock rate up to 4MHz.
SSTRB goes low at the start of the conversion and goes
high when the conversion is complete. SSTRB will be
low for a maximum of 7µs, during which time SCLK
should remain low for best noise performance. An inter-
nal register stores data when the conversion is in
progress. SCLK clocks the data out of the internal stor-
age register at any time after the conversion is complete.
The MSB of the conversion is available at DOUT when
SSTRB goes high. The subsequent 13 falling edges on
SCLK shift the remaining bits out of the internal storage
register (Figure 5). CS does not need to be held low
once a conversion is started.
P0 CLOCKED IN
tSSTRB
tCONV
tSCK
tCSS
SSTRB
SCLK
NOTE: FOR BEST NOISE PERFORMANCE, KEEP SCLK LOW DURING CONVERSION.
tCSH
CS
Figure 6. Internal Clock Mode SSTRB Detailed Timing
MAX1144/MAX1145
When internal clock mode is selected, SSTRB does not
go into a high-impedance state when CS goes high.
Figure 6 shows the SSTRB timing in internal clock
mode. In internal clock mode, data can be shifted into
the MAX1144/MAX1145 at clock rates up to 4MHz, pro-
vided the minimum acquisition time, tACQ, is kept
above 1.39µs in bipolar mode and 1.67µs in unipolar
mode. Data can be clocked out at 4MHz.
Output Data
The output data format is straight binary for unipolar
conversions and two’s complement in bipolar mode.
The MSB is shifted out of the MAX1144/MAX1145 first
in both modes.
Data Framing
The falling edge of CS does not start a conversion on the
MAX1144/MAX1145. The first logic high clocked into
DIN is interpreted as a start bit and defines the first bit of
the control byte. A conversion starts on the falling edge
of SCLK, after the seventh bit of the control byte (the P1
bit) is clocked into DIN. The start bit is defined as:
•The first high bit clocked into DIN with CS low any-
time the converter is idle, e.g. after AVDD is
applied.
•The first high bit clocked into DIN after CS is pulsed
high then low.
If a falling edge on CS forces a start bit before the con-
version or calibration is complete, then the current
operation terminates and a new one starts.
Applications Information
Power-On Reset
When power is first applied to the MAX1144/MAX1145,
or if RST is pulsed low, the internal calibration registers
are set to their default values. The user-programmable
registers (P0, P1, and P2) are low, and the device is
configured for bipolar mode with internal clocking.
Calibration
Periodically calibrate the MAX1144/MAX1145 to com-
pensate for temperature drift and other variations. After
any change in ambient temperature more than +10°C,
the device should be recalibrated. A 100mV change in
supply voltage or any change in the reference voltage
should be followed by a calibration. Calibration cor-
rects for errors in gain, offset, integral nonlinearity, and
differential nonlinearity.
The MAX1144/MAX1145 should be calibrated after
power-up or after the assertion of reset. Make sure the
power supplies and the reference voltage have fully
settled prior to initiating the calibration sequence.
Initiate calibration by setting M1 = 0 and M0 = 1 in the
control byte. In internal clock mode, SSTRB goes low at
the beginning of calibration and goes high to signal the
end of calibration, approximately 80,000 clock cycles
later. In external clock mode, SSTRB goes high at the
beginning of calibration and goes low to signal the end
of calibration. Calibration should be performed in the
same clock mode that is used for conversions.
Reference
The MAX1144/MAX1145 require an external reference.
The external reference must be bypassed with a 4.7µF
capacitor. The input impedance at REF is a minimum of
16kΩfor DC currents. During conversion, an external
reference at REF must deliver up to 150µA DC load
current and have an output impedance of 10Ωor less.
Analog Input
The MAX1144/MAX1145 use a capacitive DAC that
provides an inherent track/hold function. Drive AIN with
a source impedance less than 10Ω. Any signal condi-
tioning circuitry must settle with 14-bit accuracy in less
than 500ns. Limit the input bandwidth to less than half
the sampling frequency to eliminate aliasing. The
MAX1144/MAX1145 have a complex input impedance
that varies from unipolar to bipolar mode (Figure 1).
Input Range
The analog input range in unipolar mode is 0 to +6V for
the MAX1144, and 0 to +2.048V for the MAX1145. In
bipolar mode, the analog input can be -6V to +6V for
the MAX1144, or -2.048V to +2.048V for the MAX1145.
Unipolar or bipolar mode is programmed with the
UNI/BIP bit of the control byte. When using a reference
other than the suggested +2.048V, the full-scale input
range varies accordingly. The full-scale input range
depends on the voltage at REF and the sampling mode
selected (Tables 3 and 4).
14-Bit ADCs, 150ksps, 3.3V Single Supply
12 ______________________________________________________________________________________
PART ZERO SCALE FULL SCALE
MAX1144 0 6 (VREF/2.048)
MAX1145 0 VREF
PART NEGATIVE FULL
SCALE
ZERO
SCALE FULL SCALE
MAX1144 -6 (VREF/2.048) 0 +6 (VREF/2.048)
MAX1145 -VREF 0+V
REF
Table 3. Unipolar Full Scale and Zero
Scale
Table 4. Bipolar Full Scale, Zero Scale,
and Negative Scale
Input Acquisition and Settling
Clocking in a control byte starts input acquisition. The
main capacitor array starts acquiring the input as soon
as a start bit is recognized, using the same input range
as the previous conversion. If the opposite input range
is selected by the second DIN bit, the part immediately
switches to the new sampling mode. Acquisition time is
one-and-a-half clock cycles shorter when switching
from unipolar to bipolar or bipolar to unipolar modes
than when continuously converting in the same mode.
Acquisition can be extended by eight clock cycles by
setting M1 = 1 and M0 = 1 (long acquisition mode). The
sampling instant in short acquisition completes on the
falling edge of the sixth clock cycle after the start bit
(Figure 2). Acquisition is 5 clock cycles in short acquisi-
tion mode and 13 clock cycles in long acquisition
mode. Short acquisition mode is 24 clock cycles per
conversion. Using the external clock to run the conver-
sion process limits unipolar conversion speed to
125ksps instead of 150ksps as in bipolar mode. The
input resistance in unipolar mode is larger than that of
bipolar mode (Figure 1). The RC time constant in unipo-
lar mode is larger than that of bipolar mode, reducing
the maximum conversion rate in 24 external clock
mode. Long acquisition mode with external clock
allows both unipolar and bipolar sampling of 112ksps
as (3.6MHz / 32 clock cycles) by adding eight extra
clock cycles to the conversion.
Most applications require an input buffer amplifier. If
the input signal is multiplexed, the input channel should
be switched immediately after acquisition, rather than
near the end of or after a conversion. This allows more
time for the input buffer amplifier to respond to a large
step change in input signal. The input amplifier must
have a high enough slew rate to complete the required
output voltage change before the beginning of the
acquisition time.
At the beginning of acquisition, the capacitive DAC is
connected to the amplifier output, causing some output
disturbance. Ensure that the sampled voltage has set-
tled to within the required limits before the end of the
acquisition time. If the frequency of interest is low, AIN
can be bypassed with a large enough capacitor to
charge the capacitive DAC with very little change in
voltage. However, for AC use, AIN must be driven by a
wideband buffer (at least 10MHz), which must be sta-
ble with the DAC’s capacitive load (in parallel with any
AIN bypass capacitor used) and also must settle quickly
(Figure 7).
Digital Noise
Digital noise can couple to AIN and REF. The conver-
sion clock (SCLK) and other digital signals that are
active during input acquisition contribute noise to the
conversion result. If the noise signal is synchronous to
the sampling interval, an effective input offset is pro-
duced. Asynchronous signals produce random noise
on the input, whose high-frequency components may
be aliased into the frequency band of interest. Minimize
noise by presenting a low impedance (at the frequen-
cies contained in the noise signal) at the inputs. This
requires bypassing AIN to AGND, or buffering the input
with an amplifier that has a small-signal bandwidth of
several MHz, or preferably both. AIN has a bandwidth
of about 4MHz.
Offsets resulting from synchronous noise (such as the
conversion clock) are canceled by the MAX1144/
MAX1145’s calibration scheme. However, because the
MAX1144/MAX1145
14-Bit ADCs, 150ksps, 3.3V Single Supply
______________________________________________________________________________________ 13
4
7
6
2
3
IN
VCC
VEE
0.0033µF
0.1µF
0.1µF
100pF
1kΩ
1kΩ
AIN
Figure 7. AIN Buffer for AC/DC Use
MAX1144/MAX1145
magnitude of the offset produced by a synchronous
signal depends on the signal’s shape, recalibration
may be appropriate if the shape or relative timing of the
clock or other digital signals change, which can occur
if more than one clock signal or frequency is used.
Distortion
Avoid degrading dynamic performance by choosing an
amplifier with distortion much less than the
MAX1144/MAX1145’s THD (-90dB) at frequencies of
interest. If the chosen amplifier has insufficient com-
mon-mode rejection, which results in degraded THD
performance, use the inverting configuration to elimi-
nate errors from common-mode voltage. Low tempera-
ture-coefficient resistors reduce linearity errors caused
by resistance changes due to self-heating. Also, to
reduce linearity errors due to finite amplifier gain, use
an amplifier circuit with sufficient loop gain at the fre-
quencies of interest.
DC Accuracy
If DC accuracy is important, choose a buffer with an
offset much less than the MAX1144/MAX1145’s maxi-
mum offset (±6mV), or whose offset can be trimmed
while maintaining good stability over the required tem-
perature range.
Operating Modes and Serial Interfaces
The MAX1144/MAX1145 are fully compatible with
MICROWIRE and SPI/QSPI devices. MICROWIRE and
SPI/QSPI both transmit a byte and receive a byte at the
same time. The simplest software interface requires
only three 8-bit transfers to perform a conversion (one
8-bit transfer to configure the ADC, and two more 8-bit
transfers to clock out the 14-bit conversion result).
Short Acquisition Mode (24 SCLK)
Configure short acquisition by setting M1 = 0 and M0 =
0. In short acquisition mode, the acquisition time is 5
clock cycles. The total period is 24 clock cycles per
conversion.
Long Acquisition Mode (32 SCLK)
Configure long acquisition by setting M1 = 1 and M0 =
1. In long acquisition mode, the acquisition time is 13
clock cycles. The total period is 32 clock cycles per
conversion.
Calibration Mode
A calibration is initiated through the serial interface by
setting M1 = 0 and M0 = 1. Calibration can be done in
either internal or external clock mode, though it is desir-
able that the part be calibrated in the same mode in
which it will be used to do conversions. The part
remains in calibration mode for approximately 80,000
clock cycles unless the calibration is aborted. Calibr-
ation is halted if RST or SHDN goes low, or if a valid
start condition occurs.
Software Shutdown
A software power-down is initiated by setting M1 = 1
and M0 = 0. After the conversion completes, the part
shuts down. It reawakens upon receiving a new start
bit. Conversions initiated with M1 = 1 and M0 = 0 (shut-
down) use the acquisition mode selected for the previ-
ous conversion.
Shutdown Mode
The MAX1144/MAX1145 may be shut down by pulling
SHDN low or by asserting software shutdown. In addi-
tion to lowering power dissipation to 4µW, considerable
power can be saved by shutting down the conv-
erter for short periods between conversions. There is
no need to perform a calibration after the converter has
been shut down unless the time in shutdown is long
enough that the supply voltage or ambient temperature
may have changed.
Supplies, Layout, Grounding,
and Bypassing
For best system performance, use separate analog and
digital ground planes. The two ground planes should
be tied together at the MAX1144/MAX1145. Use pin 3
and pin 14 as the primary AGND and DGND, respec-
tively. If the analog and digital supplies come from the
same source, isolate the digital supply from the analog
with a low-value resistor (10Ω).
The MAX1144/MAX1145 are not sensitive to the order
of AVDD and DVDD sequencing. Either supply can be
present in the absence of the other. Do not apply an
external reference voltage until after both AVDD and
DVDD are present.
Be sure that digital return currents do not pass through
the analog ground. All return-current paths must be low
impedance. A 5mA current flowing through a PC board
ground trace impedance of only 0.05Ωcreates an error
voltage of about 250µV, or about 0.5LSBs error with a
±4V full-scale system. The board layout should ensure
that digital and analog signal lines are kept separate.
Do not run analog and digital lines parallel to one
another. If you must cross one with the other, do so at
right angles.
The ADC is sensitive to high-frequency noise on the
AVDD power supply. Bypass this supply to the analog
ground plane with 0.1µF. If the main supply is not ade-
quately bypassed, add an additional 1µF or 10µF low-
ESR capacitor in parallel with the primary bypass
capacitor.
14-Bit ADCs, 150ksps, 3.3V Single Supply
14 ______________________________________________________________________________________
Transfer Function
Figures 8 and 9 show the MAX1145’s transfer functions.
In unipolar mode the output data is in binary format and
in bipolar mode it is in two’s complement format.
Definitions
Integral Nonlinearity
Integral nonlinearity (INL) is the deviation of the values
on an actual transfer function from a straight line. This
straight line can be either a best-straight-line fit or a line
drawn between the end points of the transfer function,
once offset and gain errors have been nullified. INL for
the MAX1144/MAX1145 is measured using the end-
point method.
Differential Nonlinearity
Differential nonlinearity (DNL) is the difference between
an actual step width and the ideal value of 1LSB. A
DNL error specification of less than 1LSB guarantees
no missing codes and a monotonic transfer function.
Aperture Jitter
Aperture jitter (tAJ) is the sample-to-sample variation in
the time between the samples.
Aperture Delay
Aperture delay (tAD) is the time between the rising
edge of the sampling clock and the instant when an
actual sample is taken.
Signal-to-Noise Ratio
For a waveform perfectly reconstructed from digital
samples, signal-to-noise ratio (SNR) is the ratio of full-
scale analog input (RMS value) to the RMS quantization
error (residual error). The ideal, theoretical minimum
analog-to-digital noise is caused by quantization error
only and results directly from the ADC’s resolution
(N- bits):
SNR = (6.02 x N + 1.76) dB
In reality, there are other noise sources besides quanti-
zation noise, including thermal noise, reference noise,
clock jitter, etc. Therefore, SNR is calculated by taking
the ratio of the RMS signal to the RMS noise, which
includes all spectral components minus the fundamen-
tal, the first five harmonics, and the DC offset.
MAX1144/MAX1145
14-Bit ADCs, 150ksps, 3.3V Single Supply
______________________________________________________________________________________ 15
OUTPUT CODE
FULL-SCALE
TRANSITION
11 . . . 111
11 . . . 110
11 . . . 101
00 . . . 011
00 . . . 010
00 . . . 001
00 . . . 000
12 3
0FS
FS - 3/2LSB
FS = 2.048V
1LSB =
INPUT VOLTAGE (LSBs)
16384
FS
Figure 8. MAX1145 Unipolar Transfer Function, 2.048V = Full
Scale
011 . . . 111
011 . . . 110
000 . . . 010
000 . . . 001
000 . . . 000
111 . . . 111
111 . . . 110
111 . . . 101
100 . . . 001
100 . . . 000
-FS 0
INPUT VOLTAGE (LSBs)
+FS - 1LSB
+FS = +2.048V
-FS = -2.048V
1LSB = 16384
OUTPUT CODE
4.096V
Figure 9. MAX1145 Bipolar Transfer Function, 4.096V = Full
Scale
MAX1144/MAX1145
Signal-to-Noise Plus Distortion
Signal-to-noise plus distortion (SINAD) is the ratio of the
fundamental input frequency’s RMS amplitude to the
RMS equivalent of all other ADC output signals:
SINAD (dB) = 20 x log (SignalRMS / NoiseRMS)
Total Harmonic Distortion
Total harmonic distortion (THD) is the ratio of the RMS
sum of the first five harmonics of the input signal to the
fundamental itself. This is expressed as:
where V1 is the fundamental amplitude, and V2 through
V5 are the amplitudes of the 2nd- through 5th-order
harmonics.
Spurious-Free Dynamic Range
Spurious-free dynamic range (SFDR) is the ratio of RMS
amplitude of the fundamental (maximum signal compo-
nent) to the RMS value of the next largest distortion
component.
THD
VVVV
V
=×
+++
20
22324252
1
log
14-Bit ADCs, 150ksps, 3.3V Single Supply
16 ______________________________________________________________________________________
Functional Diagram
CREF
AVDD
AGND
REF
CS
RST
AIN
DVDD
DGND
SCLK
DIN
ANALOG TIMING CONTROL
INPUT
SCALING
NETWORK
SERIAL
OUTPUT
PORT
SERIAL
INPUT
PORT
MEMORY CALIBRATION
ENGINE
CLOCK
GENERATOR CONTROL
DAC COMPARATOR
P2
SSTRB
DOUT
P1
P0
SHDN
MAX1144
MAX1145
MAX1144/MAX1145
14-Bit ADCs, 150ksps, 3.3V Single Supply
______________________________________________________________________________________ 17
Ordering Information (continued)
PART TEMP
RANGE
PIN-
PACKAGE
INL
(LSB)
MAX1145ACAP 0°C to +70°C 20 SSOP ±1
MAX1145BCAP 0°C to +70°C 20 SSOP ±2
MAX1145AEAP -40°C to +85°C 20 SSOP ±1
MAX1145BEAP -40°C to +85°C 20 SSOP ±2
MAX1144/
MAX1145
AIN
AVDD
DVDD
REF
2.048V
4.7µF1µF
0.1µF
0.1µF
CREF
AGND
CS
SCLK
DIN
DOUT
RST
SSTRB
I/O
MC68HCXX
SCLK
MOSI
MISO
I/O
DGND
3.3V
3.3V
SHDN
Typical Application Circuit
Chip Information
TRANSISTOR COUNT: 21,807
PROCESS: BiCMOS
MAX1144/MAX1145
14-Bit ADCs, 150ksps, 3.3V Single Supply
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
18 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2002 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.
SSOP.EPS
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
