PMC-990147 (P2) PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
1999 PMC-Sierra, Inc.
PMC-Sierra,Inc.
Dual Serial Link, PHY Multiplexer
PM7350
S/UNI-DUPLEX
FEATURES
•Inte
rated analo
/di
ital device that
inter fac es a UTOPIA L2 bus to a se ria l
backplane with optional 1:1 protection
usin
hi
h speed Low Volta
e
Differential Si
nal
LVDS
serial links.
• For framers or modems without
UTOPIA bus interfaces: optionall
prov ides cell deline ation
I.432
across
16 clock and data
bit serial
interfaces.
• Interworks with PM7351
S/UNI-VORTEX devices to implement
a point-to-multipoint serial backplane
architecture, with optional 1:1
protection of the common card.
• Interfaces to another S/UNI-DUPLEX
device
via a sin
le LVDS link
to
create a simple point-to- point “UTOPIA
bus extension” capabilit
.
• Interfaces to two S/UNI-DUPLEX
devices to create a 1:1 protected bus
extension.
•Re
uires no ex ternal memor
devi ces.
• Low power 3.3V CMOS technolo
.
• Standard 5 pin P1149 JTAG port.
• 160 ball PBGA, 15mm x 15mm.
• In the LVDS receive direction: selects
traffic from the LVDS link marked
active and demultiplexes the individual
cell streams to the appropriate PHY
device.
• In the LVDS transmit direction: accepts
52-56 b
te cell streams from up to 32
UTOPIA L2 compatible PHY devices,
multiplexin
into a sin
le cell stream
carried over two hi
h speed LVDS
serial interfaces.
• Cell read/write to both LVDS links
available throu
h the processor port.
Provides optional hardware assisted
CRC32 calculation across cells to
support an embedded inter-processor
communication channel across the
LVDS links.
PHY/FRAM ER INTERFACES
One of three modes can be selected:
• 8/16 bit, 33 MHz UTOPIA L2 bus
master
also supports expanded len
th
cells
.
• 8/16 bit, 52 MH z ex ten de d U TO PIA L2
bus sla ve
compatible with PM7351
S/UNI-VORTEX
.
• 16 port, 4 pin clocked serial data
interface
Tx & Rx
, with inte
rated
I.432 ATM cell delineation.
LVDS INTERFACES
• Dual 4 wire LVDS serial transceivers
each operatin
at up to 200 Mb/s.
• Operates across PCB or backplane
traces, or across up to 10 meters of 4
wire twisted pair cablin
for inter-shelf
communications.
•Full
inte
rated LVDS clock s
nthesis
and recover
. No external analo
components are re
uired.
• Usable bandwidth
excludes s
stem
overhead
of 186 Mb/s.
LVDS TRANSMIT DIRECTION
• Simple round-robin multiplex of up to
32 PHYs
or 16 clock/data interfaces
plus the microprocesso r port ’s cell
transfer buffer.
• Multiplexed cell stream broadcast to
both LVDS simultaneousl
.
TXD1+
TXD1-
TX8K
RX8K
D[7:0]
RSTB
RDB
WRB
CSB
ALE
A[8:0]
INTB
IENB
JTAG Test Access
Port
TRSTB
TMS
TDI
TDO
IADDR[4:0]
IAVALID
IDAT[15:0]
IPRTY
ISOC
ISX
SCI-PHY
Receive
Master/
Transmit
Slave
OENB
OADDR[4:0]
OAVALID
ODAT[15:0]
OPRTY
OSOC
OSX
OMASTER
OFCLK
SCI-PHY
Transmit
Master/
Receive Slave
TCK
Per-PHY
Buffers
2 Cell
Buffer
4 Cell
FIFO
RXD1+
RXD1-
Clock
Synthesis
REFCLK
RCLK
RSTOB
TXD2+
TXD2-
RXD2+
RXD2-
4 Cell
FIFO
Per-PHY
Buffers
IMASTER
IANYPHY
IFCLK
ICA
OANYPHY
OCA
SCIANY
LTXD[15:0]
LTXC[15:0]
LRXC[15:0]
LRXD[15:0]
Elastic Store
Cell Processor
IBUS8
OBUS8
Time-Sliced ATM
Transmission
Convergence
Microprocessor Interface
BLOCK DIAGRAM