SPICE Device Model Si3445DV Vishay Siliconix P-Channel 1.8-V (G-S) MOSFET CHARACTERISTICS * P-Channel Vertical DMOS * Macro Model (Subcircuit Model) * Level 3 MOS * Apply for both Linear and Switching Application * Accurate over the -55 to 125C Temperature Range * Model the Gate Charge, Transient, and Diode Reverse Recovery Characteristics DESCRIPTION The attached spice model describes the typical electrical characteristics of the p-channel vertical DMOS. The subcircuit model schematic is extracted and optimized over the -55 to 125C temperature ranges under the pulsed 0-to-5V gate drive. The saturated output impedance is best fit at the gate bias near the threshold voltage. A novel gate-to-drain feedback capacitance network is used to model the gate charge characteristics while avoiding convergence difficulties of the switched Cgd model. All model parameter values are optimized to provide a best fit to the measured electrical data and are not intended as an exact physical interpretation of the device. SUBCIRCUIT MODEL SCHEMATIC This document is intended as a SPICE modeling guideline and does not constitute a commercial product data sheet. Designers should refer to the appropriate data sheet of the same number for guaranteed specification limits. Document Number: 71521 07-May-01 www.vishay.com 1 SPICE Device Model Si3445DV Vishay Siliconix SPECIFICATIONS (TJ = 25C UNLESS OTHERWISE NOTED) Parameter Symbol Test Conditions Typical Unit VGS(th) VDS = VGS, ID = -250 A 0.83 V ID(on) VDS -5 V, VGS = -4.5 V 105 A VGS = -4.5 V, ID = -5.6 A 0.033 VGS = -2.5 V, ID = -4.7 A 0.050 VGS = -1.8 V, ID = -2.0 A 0.077 Static Gate Threshold Voltage a On-State Drain Current a Drain-Source On-State Resistance a Forward Transconductance a Diode Forward Voltage Dynamic rDS(on) gfs VDS = -10 V, ID = -5.6 A 15 S VSD IS = -1.7 A, VGS = 0 V 0.80 V b Total Gate Charge Qg Gate-Source Charge Qgs Gate-Drain Charge Qgd 2 Turn-On Delay Time td(on) 36 Rise Time Turn-Off Delay Time tr td(off) Fall Time tf Source-Drain Reverse Recovery Time trr 13.5 VDS = -4 V, VGS = -4.5 V, ID = -5.6 A VDD = -4 V, RL = 4 ID -1 A, VGEN = -4.5 V, RG = 6 3 nC 24 132 ns 28 IF = -1.7 A, di/dt = 100 A/s 57 Notes a. Pulse test; pulse width 300 s, duty cycle 2%. b. Guaranteed by design, not subject to production testing. www.vishay.com 2 Document Number: 71521 07-May-01 SPICE Device Model Si3445DV Vishay Siliconix COMPARISON OF MODEL WITH MEASURED DATA (TJ=25C UNLESS OTHERWISE NOTED) Document Number: 71521 07-May-01 www.vishay.com 3