1. Product profile
1.1 General description
250 W LDMOS power transistor for base station applications at frequencies from
920MHz to 960MHz.
[1] Test signal: 3GPP; test model 1; 64 DPCH; PAR = 7.5 dB at 0.01 % probability on CCDF per carrier.
Carrier spacing 5 MHz.
1.2 Features and benefits
Excellent ruggedness
High efficiency
Low Rth providing excellent thermal stability
Designed for broadband operation (920 MHz to 960 MHz)
Lower output capacitance for improved performance in Doherty applications
Designed for low memory effects providing excellent pre-distortability
Internally matched for ease of use (input and output)
Integrated ESD protection
Compliant to Directive 2002/95/EC, rega rd in g Re stri ctio n of Hazard ou s Sub stances
(RoHS)
1.3 Applications
RF power amplifiers for W-CDMA base stations and multi carrier applications in the
920 MHz to 960 MHz frequency range
BLF7G10L-250;
BLF7G10LS-250
Power LDMOS transistor
Rev. 3 — 16 February 2012 Product data sheet
Table 1. Typical performance
Ty pical RF performance at Tcase = 25
C in a common source class-AB production test circuit.
Test signal f IDq VDS PL(AV) GpDACPR
(MHz) (mA) (V) (W) (dB) (%) (dBc)
2-carrier W-CDMA 920 to 960 1800 30 60 19.5 30.5 34 [1]
BLF7G10L-250_7G10LS-250 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 3 — 16 February 2012 2 of 13
NXP Semiconductors BLF7G10L-250; BLF7G10LS-250
Power LDMOS transistor
2. Pinning information
[1] Connected to flange
3. Ordering information
4. Limiting values
5. Thermal characteristics
Table 2. Pinning
Pin Description Simplified outline Graphic symbol
BLF7G10L-250 (SOT 502A)
1drain
2gate
3source [1]
BLF7G10LS-250 (SOT5 02B)
1drain
2gate
3source [1]
3
2
1
sym112
1
3
2
3
2
1
sym112
1
3
2
Table 3. Ordering information
Type number Package
Name Description Version
BLF7G10L-250 - f langed LDMOST ceramic package; 2 mounting holes;
2 leads SOT502A
BLF7G10LS-250 - earless flanged LDMOST ceramic package; 2 leads SOT502B
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter Conditions Min Max Unit
VDS drain-source voltage - 65 V
VGS gate-source voltage 0.5 +13 V
Tstg storage temperature 65 +150 C
Tjjunction temperature - 200 C
Table 5. Thermal characteristics
Symbol Parameter Conditions Typ Unit
Rth(j-c) thermal resistance from junction to case Tcase =80C; PL=60W (CW);
VDS =30V; I
Dq = 1800 mA 0.38 K/W
BLF7G10L-250_7G10LS-250 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 3 — 16 February 2012 3 of 13
NXP Semiconductors BLF7G10L-250; BLF7G10LS-250
Power LDMOS transistor
6. Characteristics
7. Test information
7.1 Ruggedness in class-AB operation
The BLF7G10L-250 and BLF7G10LS-250 are capable of withstanding a load mismatch
corresponding to VSWR = 10 : 1 through all phases under the following conditions:
VDS =30V; I
Dq =1800mA; P
L= 200 W (CW); f = 920 MHz to 960 MHz.
Table 6. Characteristics
Tj = 25
C unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
V(BR)DSS drain-source breakdown voltage VGS =0V; I
D=3.3mA 65 - - V
VGS(th) gate-source threshold voltage VDS =10 V; I
D= 330 mA 1.50 1.9 2.30 V
IDSS drain leakage current VGS =0V; V
DS =28V--5A
IDSX drain cut-off current VGS =V
GS(th) +3.75 V;
VDS =10V -56-A
IGSS gate leakage current VGS =11V; V
DS =0V--0.5mA
gfs forward transconductance VDS =10V; I
D= 11.55 A - 22 - S
RDS(on) drain-source on-state resistance VGS =V
GS(th) + 3.75 V;
ID= 11.55 A -57-m
Table 7. Functional test information
Test signal: 2-carrier W-CDMA; PAR = 7.5 dB at 0.01 % probabili ty on the CCDF;
3GPP test model 1; 64 DPCH; f1= 920 MHz; f2= 925 MHz; f3= 955 MHz; f4= 960 MHz;
RF performance at VDS =30V; I
Dq = 1800 mA; Tcase =25
C; unless otherwise specified; in a
class-AB production test circuit.
Symbol Parameter Conditions Min Typ Max Unit
Gppower gain PL(AV) =60W 18.5 19.5 - dB
RLin input return loss PL(AV) =60W - 15.5 10 dB
Ddrain efficiency PL(AV) =60W 27 30.5 - %
ACPR adjacent channel power ratio PL(AV) =60W - 34 31 dBc
BLF7G10L-250_7G10LS-250 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 3 — 16 February 2012 4 of 13
NXP Semiconductors BLF7G10L-250; BLF7G10LS-250
Power LDMOS transistor
7.2 Impedance information
7.3 CW pulsed
Table 8. Typical impedance in formation
IDq = 1800 mA; main transistor VDS =30V.
ZS and ZL defined in Figure 1.
f ZS ZL
(MHz) () ()
925 3.1 j3.3 1.0 j1.7
942 3.2 j3.3 1.0 j1.6
960 3.4 j3.5 0.9 j1.4
Fig 1. Definition of transistor impedance
001aaf059
drain
Z
L
Z
S
gate
VDS =30V; I
Dq = 1800 mA.
(1) f = 920 MHz
(2) f = 940 MHz
(3) f = 960 MHz
VDS =30V; I
Dq = 1800 mA.
(1) f = 920 MHz
(2) f = 940 MHz
(3) f = 960 MHz
Fig 2. Power gain and drain efficiency as function of
output power; typical values Fig 3. Power gain and drain efficiency as function of
output power; typical values
PL (dBm)
44 565248
aaa-001555
14
18
22
Gp
(dB)
10
20
40
60
ηD
(%)
0
(1)
(2)
(3)
(1)
(2)
(3)
Gp
ηD
PL (W)
0 360240120
aaa-001556
14
18
22
Gp
(dB)
10
20
40
60
ηD
(%)
0
(1)
(2)
(3)
Gp
ηD
(1)
(2)
(3)
BLF7G10L-250_7G10LS-250 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 3 — 16 February 2012 5 of 13
NXP Semiconductors BLF7G10L-250; BLF7G10LS-250
Power LDMOS transistor
7.4 2C-WCDMA
VDS =30V; I
Dq = 1800 mA.
(1) f = 920 MHz
(2) f = 940 MHz
(3) f = 960 MHz
Fig 4. Input return loss as a function of output power; typical values
aaa-001559
PL (dBm)
44 565248
-16
-18
-14
-12
RLin
(dB)
-20
(1)
(2)(2)
(3)
VDS =30V; I
Dq = 1800 mA.
(1) f = 920 MHz
(2) f = 940 MHz
(3) f = 960 MHz
VDS =30V; I
Dq = 1800 mA.
(1) f = 920 MHz
(2) f = 940 MHz
(3) f = 960 MHz
Fig 5. Power gain and drain efficiency as function of
output power; typical values Fig 6. Power gain and drain efficiency as function of
output power; typical values
aaa-001561
18
19
17
20
21
Gp
(dB)
16
20
30
10
40
50
ηD
(%)
0
PL (dBm)
38 42 46 50 52484440
(1)
(2)
(3)
(1)
(2)
(3)
Gp
ηD
aaa-001562
PL (W)
0 1208040
18
19
17
20
21
Gp
(dB)
ηD
(%)
16
20
30
10
40
50
0
(1)
(2)
(3)
(1)
(2)
(3)
Gp
ηD
BLF7G10L-250_7G10LS-250 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 3 — 16 February 2012 6 of 13
NXP Semiconductors BLF7G10L-250; BLF7G10LS-250
Power LDMOS transistor
VDS =30V; I
Dq = 1800 mA.
(1) f = 920 MHz
(2) f = 940 MHz
(3) f = 960 MHz
VDS =30V; I
Dq = 1800 mA.
(1) f = 920 MHz
(2) f = 940 MHz
(3) f = 960 MHz
Fig 7. Input return loss as a function of output
power; typical values Fig 8. Ad jacent channel power ratio (5 MHz and
10 MHz) as functi on of output power; typical
values
VDS =30V; I
Dq = 1800 mA.
(1) f = 920 MHz
(2) f = 940 MHz
(3) f = 960 MHz
Fig 9. Peak-to-average ratio as a fun ction of output power; typical value s
PL (dBm)
38 545042 46
aaa-001564
-18
-14
-10
RLin
(dB)
-22
(1)
(2)
(3)
PL (dBm)
38 545042 46
aaa-001566
-40
-50
-30
-20
ACPR
(dBc)
-60
(1)
(2)
(3)
(1)
(2)
(3)
ACPR5M
ACPR10M
PL (dBm)
38 545042 46
aaa-001568
7
6
8
9
PAR
(dB)
5
(1)
(2)
(3)
BLF7G10L-250_7G10LS-250 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 3 — 16 February 2012 7 of 13
NXP Semiconductors BLF7G10L-250; BLF7G10LS-250
Power LDMOS transistor
7.5 Circuit
Printed-Circuit Board (PCB): Rogers RO3006; r = 6.15 F/m; thickness = 0.635 mm; thickness copper plating = 35 m.
The vias can be used as a reference to place components.
The above layout shows the test circuit used to measure the devices in production. A more appropriate application
demonstration for specific customer needs can be provided.
See Table 9 for list of components.
Fig 10. Component lay ou t
aaa-001570
C15
C12C11C5
C4C1
C6 C13 C14 C16
C2C8C7
C3C10C9
BLF7G10L(S)-250
Table 9. List of components
See Figure 10 for component layout.
Component Description Value Remarks
C1, C2, C3, C4, C5, C6 multilayer ceramic chip capacitor 82 pF ATC800B
C7, C9, C12, C14 multilayer ceramic chip capacitor 10 F Murata
C8, C10, C11, C13 multilayer ceramic chip capacitor 1 F Murata
C15, C16 electrolytic capacitor 470 F; 63 V
BLF7G10L-250_7G10LS-250 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 3 — 16 February 2012 8 of 13
NXP Semiconductors BLF7G10L-250; BLF7G10LS-250
Power LDMOS transistor
8. Package outline
Fig 11. Package outline SOT502A
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
SOT502A 99-12-28
03-01-10
0 5 10 mm
scale
Flanged LDMOST ceramic package; 2 mounting holes; 2 leads SOT502A
p
L
AF
b
D
U2
H
Q
c
1
3
2
D1
E
A
C
q
U1
C
B
E1
M M
w2
UNIT A
mm
Db
12.83
12.57 0.15
0.08 20.02
19.61 9.53
9.25 19.94
18.92 9.91
9.65
4.72
3.43
cU2
0.25 0.5127.94
qw
2
w1
F
1.14
0.89
U1
34.16
33.91
L
5.33
4.32
p
3.38
3.12
Q
1.70
1.45
EE
1
9.50
9.30
inches 0.505
0.495 0.006
0.003 0.788
0.772
D1
19.96
19.66
0.786
0.774 0.375
0.364 0.785
0.745 0.390
0.380
0.186
0.135 0.01 0.021.100
0.045
0.035 1.345
1.335
0.210
0.170 0.133
0.123 0.067
0.057
0.374
0.366
H
DIMENSIONS (millimetre dimensions are derived from the original inch dimensions)
w1AB
M M M
BLF7G10L-250_7G10LS-250 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 3 — 16 February 2012 9 of 13
NXP Semiconductors BLF7G10L-250; BLF7G10LS-250
Power LDMOS transistor
Fig 12. Package outline SOT502B
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
SOT502B 03-01-10
07-05-09
0 5 10 mm
scale
Earless flanged LDMOST ceramic package; 2 leads SOT502B
AF
b
D
U2
L
H
Q
c
1
3
2
D1
E
D
U1
D
E1
M M
w2
UNIT A
mm
Db
12.83
12.57 0.15
0.08 20.02
19.61 9.53
9.25 19.94
18.92 9.91
9.65
4.72
3.43
cU2
0.25
w2
F
1.14
0.89
U1
20.70
20.45
L
5.33
4.32
Q
1.70
1.45
EE
1
9.50
9.30
inches 0.505
0.495 0.006
0.003 0.788
0.772
D1
19.96
19.66
0.786
0.774 0.375
0.364 0.785
0.745 0.390
0.380
0.186
0.135 0.010
0.045
0.035 0.815
0.805
0.210
0.170 0.067
0.057
0.374
0.366
H
DIMENSIONS (millimetre dimensions are derived from the original inch dimensions)
BLF7G10L-250_7G10LS-250 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 3 — 16 February 2012 10 of 13
NXP Semiconductors BLF7G10L-250; BLF7G10LS-250
Power LDMOS transistor
9. Abbreviations
10. Revision history
Table 10. Ab breviations
Acronym Description
3GPP Third Generation Partnership Project
CCDF Complementary Cumulative Distribution Function
CW Continuous Wave
DPCH Dedicated Physical CHannel
ESD ElectroStatic Discharge
LDMOS Laterally Diffused Metal Oxide Semiconductor
LDMOST Laterally Diffused Metal Oxide Semiconductor Transistor
PAR Peak-to-Average power Ratio
RF Radio Frequency
VSWR Voltage Standing Wave Ratio
W-CDMA Wideband Code Division Multiple Access
Table 11. Revision history
Document ID Release date Data sheet status Change
notice Supersedes
BLF7G10L-250_7G10LS-2 50 v.3 20120216 Product data sheet - BLF7G10L-250_7G10LS-250 v.2
Modifications: •The status of this data sheet has been changed to Product data sheet
•Table 6 on page 3: ID value changed to 3.3 mA at conditions of V(BR)DSS
•Table 8 on page 4: values rounded off to one decimal place
BLF7G10L-250_7G10LS-250 v.2 20111114 Preliminary data sheet - BLF7G10L-250_7G10LS-250 v.1
BLF7G10L-250_7G10LS-2 50 v.1 20110225 Objective data sheet - -
BLF7G10L-250_7G10LS-250 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 3 — 16 February 2012 11 of 13
NXP Semiconductors BLF7G10L-250; BLF7G10LS-250
Power LDMOS transistor
11. Legal information
11.1 Data sheet status
[1] Please consult the most recently issued document before initiating or completing a design.
[2] The term ‘short data sheet’ is explained in section “Definitions”.
[3] The product status of de vice(s) descr ibed in th is docume nt may have cha nged since this docume nt was publis hed and ma y dif fer in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
11.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
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information included herein and shall have no liab ility for the consequences of
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Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and tit le. A short data sh eet is intended
for quick reference only and shou ld not be rel ied u pon to cont ain det ailed and
full information. For detailed and full informatio n see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
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Applications — Applications that are described herein for any of these
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Customers are responsible for the design and ope ration of their applications
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Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanent ly and irreversibly affect
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Document status[1][2] Product status[3] Definition
Objective [short] data sheet Development This document contains data from the objective specification for product development.
Preliminary [short] dat a sheet Qualification This document contains data from the preliminary specification.
Product [short] dat a sheet Production This document contain s the product specification.
BLF7G10L-250_7G10LS-250 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 3 — 16 February 2012 12 of 13
NXP Semiconductors BLF7G10L-250; BLF7G10LS-250
Power LDMOS transistor
Export control — This document as well as the item(s) described herein
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Quick reference data — The Quick reference dat a is an extract of the
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Notice: All referenced b rands, produc t names, service names and trademarks
are the property of their respect i ve ow ners.
12. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
NXP Semiconductors BLF7G10L-250; BLF7G10LS-250
Power LDMOS transistor
© NXP B.V. 2012. All rights reserved.
For more information, please visit: http://www.nxp.co m
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 16 February 2012
Document identifier: BLF7G10L-250_7G10LS-250
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
13. Contents
1 Product profile. . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1 General description . . . . . . . . . . . . . . . . . . . . . 1
1.2 Features and benefits. . . . . . . . . . . . . . . . . . . . 1
1.3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2 Pinning information. . . . . . . . . . . . . . . . . . . . . . 2
3 Ordering information. . . . . . . . . . . . . . . . . . . . . 2
4 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 2
5 Thermal characteristics . . . . . . . . . . . . . . . . . . 2
6 Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 3
7 Test information. . . . . . . . . . . . . . . . . . . . . . . . . 3
7.1 Ruggedness in class-AB operation . . . . . . . . . 3
7.2 Impedance information. . . . . . . . . . . . . . . . . . . 4
7.3 CW pulsed . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
7.4 2C-WCDMA . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
7.5 Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
8 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 8
9 Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 10
10 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 10
11 Legal information. . . . . . . . . . . . . . . . . . . . . . . 11
11.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 11
11.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
11.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 11
11.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 12
12 Contact information. . . . . . . . . . . . . . . . . . . . . 12
13 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
