INNOVATIVE IM1386 SRAM + RTC + Watchdog FEATURES 8K OR 32K bytes of user NV SRAM. Real time quartz clock/calender keeps track of hunderedths of seconds, seconds, minutes, hours, days, date of the month, month, and years with leap year compensation valid up to 2100. Will operate in 32-pin JEDEC footprint Watchdog timer restarts an out-of-control processor. Alarm function schedules real-time related activities such as system wakeup. Embedded lithium energy cell maintains time,watchdog, user RAM, and alarm information. Programmable interrupts and square wave outputs. PIN CONFIGURATION INTA INTB NC A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 Vcc SQW Vcc WE NC A8 A9 A11 OE A10 CE I/O7 I/O6 I/O5 I/O4 I/O3 INTA INTB A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 GND IM1386 8K X 8 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 Vcc SQW Vcc WE A13 A8 A9 A11 OE A10 CE I/O7 I/O6 I/O5 I/O4 I/O3 IM1386 32K X 8 32-PIN ENCAPSULATED PACKAGE All registers are individually addressable via the address and data bus. Accuracy is better than +/- 1 minute/month at 25OC. Greater than 10 years of timekeeping in the absence of Vcc. Interrupt signals active in power-down mode. DESCRIPTION The IM1386 SRAM + RTC + Watchdog is self contained realtime clock,alaram, watchdog timer, and interval timer in 32-pin JEDEC DIP package. The IM1386 contains an embedded lithium energy source and a quartz crystal which eliminates the need for any external circuitry. Data contained within 8K or 32K by 8-bit memory and the timekeeping registers can be read or written in the same manner as bytewide static RAM. The timekeeping registers are located in the first 14 bytes of memory space. Data is maintained in the RAM + RTC + Watchdog by intelligent control circuitry which detects the status of Vcc and write protects memory when Vcc is out of tolerance. The lithium energy source can maintain data and real time for over ten years in the absence of Vcc. Timekeeper information includes hundredths of seconds, seconds, minutes, hours, day date, month, and year. The date at the end of the months with less than 31 days, including correction for leap year. PIN DESCRIPTION INTB(INTB) A0-A14 I/O0-I/O7 CE OE WE Vcc GND INTA SQW NC - Interrupt Output B(open drain) - Address Inputs - Data Input/Output - Chip Enable - Output Enable - Write Enable - +5 Volts - Ground - Interrupt Output A(Open drain) - Square Wave Output - No Connection ORDERING INFORMATION IM1386 - XX - XX RTC and NVRAM; 32 pin DIP 120 ns access 08 8K x 8 NVRAM 32 32K x 8 NVRAM INNOVATIVE MICRODEVICES INC.Phone/Fax-440-322-8083.Website:www.innovativemicrodevices.com INNOVATIVE IM1386 SRAM + RTC + Watchdog BLOCK DIAGRAM 1024 Hz SQW DIVIDE BY 4 Vcc (VBAT) + QUARTZ CRYSTAL (X1) OSCILLATOR POWER SWITCH DIVIDE COUNTER (X2) TD INT PF DELAY WD INT CE OE WE ADDRESS DECODE ADN COUNTROL RTC REGISTERS A0-A14 A0-A12 COMMAND REGISTER INTERNAL COUNTER USER RAM 32K X 8 OR 8K X 8 NVRAM DATA I/O BUFFERS DQ0 - DQ7 EXTERNAL REGISTER SWAP PINS INTA INTB(INTB) INNOVATIVE IM1386 SRAM + RTC + Watchdog OPERATION - READ REGISTERS The IM1386 executes a read cycle whenever WE is inactive(High) and CE (Chip Enable) and OE (Output Enable) are active (Low). The unique address specified by the address inputs(A0-A14) defines which of the registers is to be accessed. Valid data will be available to the eight data output drivers within tACC (Access Time) after the last address input signal is stable, providing that CE and OE access times are also satisfied. If OE and CE access times are not satisfied, then data access must be measured from the latter occuring signal(CE or OE) and the limiting parameter is either tCO for CE or tOE for OE rather than address access. OPERATION - WRITE REGISTERS The IM1386 is in the write mode whenever the WE(write enable) and CE(Chip enable) signals are in the active(Low) state after the address inputs are stable. The latter occuring falling edge of CE or WE will determine the start of the write cycle. The write cycle is terminated by the earlier rising edge of CE or WE. All address inputs must be kept valid throughout the write cycle. WE must return to the high state for a minimum recovery state(tWR) before another cycle can be initiated. Data must be valid on the databus with sufficient data set-up(tDS) and data hold time(tDH) with respect to the earlier rising edge of CE or WE. The OE control signal should be kept inactive(High) during write cycle to avoid bus contention. However, if the output bus has been enabled(CE and OE active), then WE will disable the outputs in tODW from its falling edge. DATA RETENTION The RAM + Timekeeper provides full functional capability when Vcc is greater than 4.5 volts and write-protects the register contents at 4.25 volts typical. Data is maintained in the absence of Vcc without any additional support circuitry. The IM1386 constantly monitors Vcc. Should the supply voltage decay, the RAM + Timekeeper wiil automatically write-protect itself and all inputs to the registers become "don't care". The two interrupts INTA and INTB(INTB) and the internal clock and timers continue to run regardless of the level of Vcc. However, it is important to insure that the pull-up resistors used with the interrupt pins are never pulled up to a value that is greater than Vcc + 0.3V. As Vcc falls below approximately 3.0 volts, a power switching circuit turns the internal lithium energy source on to maintain the clock and timer data and functionality. During power-up, when Vcc rises above approximately 3.0 volts, the power switching circuit connects external Vcc and disconnects the internal lithium energy source. Normal operation can resume after Vcc exceeds 4.5 volts for a period of 200ms. RAM + TIMEKEEPER REGISTERS The RAM + Timekeeper has 14 registers which are eight bits wide that contain all of the timekeeping, alarm, watchdog and control information. The clock calender, alarm and watchdog registers are memory locations which contain external(user-accessible) and internal copies of the data. The external copies are independent of internal functions except that they are updated periodically by the simultaneous transfer of the incremented internal copy. The command Register bits are affected by both internal and external functions. This registers will be discussed later. The 8K or 32K bytes of RAM and the 14 external timekeeping registers are accessed from the external address and data bus. Registers 0, 1, 2, 4, 6, 8, 9 and A contain time of day and date information. Time of day information is stored in BCD. Registers 3, 5, and 7 contain the Time of Day Alarm information. Time of Day Alarm information is stored in BCD. Register B is the Command Register and information in this register is binary. Registers Cand D are the Watchdog Alarm Registers and information which is stored in these two registers is in BCD. Register E through 1FFF or 7FFF are user bytes and can be used to maintain data at the user's discretion. TIME OF THE DAY REGISTERS Registers 0, 1, 2, 4, 6, 8, 9, and A contain Time of Day data in BCD. Ten bits within these eight registers are not used and will always read zero regardless of how they are written. Bits 6 and 7 in the Months Registers(9) are binary bits. When set to logic zero, EOSC (Bit 7) enables the real time clock oscillator. This bit is set to logic one as shipped from Innovative Microdevices to prevent lithium energy consumption during storage and shipment. This bit will normally be turned on by the user during device initialization.However, the oscillator can be turned on and off as necessary by setting this bit to the appropriate level. Bit 6 of this same byte controls the Square Wave Output (pin 31). INNOVATIVE IM1386 SRAM + RTC + Watchdog When set to logic 0 the output pin will output a 1024 Hz square wave siganl.When set to logic one the Square Wave Output pin is in high impedence state. Bit 6 of the Hours register is defined as the 12 or 24 Hour Select Bit. When set to logic one, the 12 hour format is selected. In the 12 hour format, bit 5 is the AM/PM bit with logic one being PM. In the 24 hour mode, bit 5 is the second 10 hour bit(20-23 hours). The Time of Day registers are updated every 0.01 seconds from the real time Clock, except when the TE bit (bit 7 of Register B) is set low or the clock oscillator is not running. The preferred method of synchronizing data access to and from the RAM + Timekeeper is to access the Command register by doing a write cycle to address location 0B and setting the TE bit (Transfer Enable bit) to a logic zero. This will freeze the External time of Day register at the present recorded time, allowing access to occur without danger of simultaneous update. When the watch registers have been read or written, a second write cycle to location 0B, setting the TE bit to a logic one, will put the Time of Day Registers back to being updated every 0.01 second. No time is lost in the real time clock because the internal copy of the time of day register buffer is continually incremented while the external memory registers are frozen. An alternate method of reading and writing Time of Day registers is to ignore synchronization. However, any singal read may give erroneous data as the real time clock may be in the process of updating the external memory registers as data is being read. The internal copies of seconds through years are incremented, and the Time of Day Alarm is checked during the period that hundreds of seconds read 99 and are transfered to the external register when hundredths of seconds roll from 99 to 00. A way of making sure data is valid is to do multiple reads and compare. Writing the registers can also produce erroneous results for the same reasons. A way of making sure that the write cycle has caused proper update is to do read verifies and re-execute the write cycle if data is not correct. While the possibility of erroneous results from reads and write cycle has been stated, it is worth nothing that the probability of an incorrect result is kept to a minimum due to the redudant structure of the RAM + Timekeeper. TIME OF DAY ALARM REGISTERS Registers 3, 5, and 7 contain the Time of Day Alarm Registers. Bits 3, 4, 5, and 6 of Register 7 will always read zero regardless of how they are written. Bit 7 of Registers 3, 5, and 7 are mask bits. When all of the mask bits are logic zero, a Time of Day Alarm will only occur when Registers 2, 4, and 6 match the values stored in Registers 3, 5, and 7. An alarm will be generated every day when bit 7 of Register 7 is set to a logic one. Similarly, an alarm is generated every hour when bit 7 of Registers 7 and 5 is set to a logic 1. When bit 7 of Registers 7, 5, and 3 is set to logic 1 an alarm will occur every minute when register 1 (seconds) rolls from 59 to 00. Time of Day Alarm Registers are written and read in the same format as the Time of Day Registers. The Time of Day Alarm Flag and Interrupt is always cleared when Alarm Registers are read or written. WATCHDOG ALARM REGISTERS Registers C and D contain the time for the Watchdog Alarm. The two registers contain a time count from 00.01 to 99.99 seconds in BCD. The value written into the Watchdog Alarm Registers can be written or read in any order. Any access to Register C or D will cause the Watchdog Alarm to reinitialize and clears the Watchdog flag Bit and the Watchdog Interrupt Output. When a new value is entered or the Watchdog Registers are read, the Watchdog Timer will start counting down from the entered value to zero. When zero is reached, the Watchdog Interrupt Output will go to the active state. The Watchdog Timer Countdown is interrupted and reinitialized back to the entered value every time either of the registers are accessed. In this manner, controlled periodic accesses to the Watchdog Timer can prevent the Watchdog Alarm from going to an active level. If access does not occur, countdown alarm will be repetitive. The Watchdog Alarm Registers always read the entered value. The actual count-down register is internal and is not readable. Writing registers C and D to zero will disable the Watchdog Alarm feature. INNOVATIVE IM1386 SRAM + RTC + Watchdog IM1386 RAM + TIMEKEEPER + WATCHDOG REGISTERS AD D R ESS B it 7 0 B it 6 B it 5 B it 4 B it 3 0.1 SECONDS B it 2 B it 1 B it 0 R an g e 0.01 SECONDS 00-99 1 0 10 SECONDS SECONDS 00-59 2 0 10 MINUTES MINUTES 00-59 3 M 10 MIN ALARM MIN ALARM 00-59 4 0 12 / 24 HOURS 01-12+A/P 00-23 5 M 12 / 24 HR ALARM 01-12+A/P 00-23 6 0 0 0 0 0 DAYS 01-07 7 M 0 0 0 0 DAY ALARM 01-07 8 0 0 9 EOSC ESQW A B 10 DATE 0 10 MO 10 YEARS TE IPSW WAM DATE 01-31 MONTHS 01-12 YEARS 00-99 TDM WAF TDF C 0.1 SECONDS 0.01 SECONDS 00-99 D 10 SECONDS SECONDS 00-99 E USER RAM AREA START 1F F F (7FFF) USER RAM AREA END INNOVATIVE IM1386 SRAM + RTC + Watchdog TIME OF DAY ALARM MASK BITS REMARKS REGISTERS (3) MINUTES (5) HOURS (7) D AYS 1 1 1 ALARM ONC E PER MINUTE 0 1 1 ALARM WHEN MINUTE MATC H 0 0 1 ALARM WHEN HOURS AND MINUTES MATC H 0 0 0 ALARM WHEN HOURS, MINUTES, AND D AYS MATC H NOTE: ANY OTHER BIT COMBINATIONS OF MASK BIT SETTING PRODUCE ILLOGICAL OPERATION COMMAND REGISTER Address location 0Bh is the Command register where mask bits, control bits and flag bits reside. The operation of each bit is as follows: TE - Bit 7 Transfer enable - This bit when set to a logic 0 will disable the transfer of data between internal and external clock registers. The contents in the external clock registers are now frozen and reads or writes will not be affected with updates. This bit must be set to a logic 1 to allow updates. IPSW - Bit 6 Interrupt switch - When set to a logic 1, INTA is the Time of day Alarm and INTB/(INTB) is the Watchdog Alarm. When set to logic 0, this bit reverses the output pins. INTA is now the Watchdog Alarm output and INTB(INTB) is the Time of Day Alarm output. IBH/LO - Bit 5 Interrupt B Sink or Source Current - When this bit is set to a logic 1 and Vcc is applied, INTB/(INTB) will source current (see DC characteristics IOH). When this bit is set to a logic 0, INTB will sink current (see DC characteristics IOL). PU/LVL - Bit 4 Interrupt pulse mode or level mode This bit determines whether both interrupts will output a pulse or level signal. When set to a logic 0, INTA and INTB/(INTB) will be in the level mode. When this bit is set to a logic 1, the pulse mode is selected and INTA will sink current for a minimum of 3 ms and then release. INTB/(INTB) will either sink or source current, depending on the condition of Bit 5, for a minimum of 3 ms and then release. WAM - Bit 3 Watchdog Alarm Mask - When this bit is set to a logic 0, the Watchdog Interrupt output will be activated. The activated state is determined by bits 1, 4, 5, and 6 of the COMMAND REGISTER. When this bit is set to a logic 1, the Watchdog interrupt output is deactivated. TDM - Bit 2 Time of Day Alarm Mask - when this bit is set to a logic 0, the Time of Day Alarm Interrupt output will be activated. The Activated state is determined by bits 0, 4, 5, and 6 of the COMMAND REGISTER. When this bit is set to a logic 1, the Time of Day Alarm interrupt output is deactivated. WAF - Bit 1 Watchdog Alarm Flag - This bit is set to a logic 1 when a watchdog alarm interrupt occurs. This bit is read only. The bit is reset when any of the Watchdog Alarm registers are accessed. When the interrupt is in the pulse mode (see bit 4 definition), this flag will be in the logic 1 state only during the time the interrupt is active. TDF - Bit 0 Time of Day Flag - This is a read only bit. This bit is set to a logic 1 when a Time of Day alarm has occured. The time the alarm occured can be determined by reading the Time of Day Alarm registers. This bit is reset to a logic 0 state when any of the Time of Day Alarm registers are accessed. When the interrupt is in the pulse mode (see bit 4 definition), this flag will be in the logic 1 state only during the time the interrupt is active. INNOVATIVE IM1386 SRAM + RTC + Watchdog ABSOLUTE MAXIMUM RATINGS* Voltage on any Pin Relative to Ground Operating Temperature Storage Temperature Soldering Temperature - 0.3 V to + 7.0 V 0OC to 70OC - 40OC to + 70OC 260OC for 10 seconds * This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability. O O RECOMMENDED DC OPERATING CONDITONS (0 C to 70 C) PARAMETER SYMB OL MIN TYP MAX UNITS Supply Voltage V cc 4.5 5.0 5.5 V Input Logic 1 VI H 2.2 Vcc + 0.3 V Input Logic 0 VI L -0.3 + 0.8 V All voltages are refered to ground. DC ELECTRICAL CHARACTERISTICS (0OC to 70OC; Vcc = 5V +/- 10%) PARAMETER SYMB OL MIN Input Leakage Current IIL Output leakage Current TYP MAX UNITS -1.0 +1.0 uA ILO -1.0 +1.0 uA I/O Leakage Current ILIO -1.0 +1.0 uA Output Current @ 2.4 V IOH -1.0 Output Current @ 0.4 V IOL mA 2.1 mA Standby Current CE = 2.2V ICCS1 3.0 7.0 mA Standby Current CE = Vcc-0.5 ICCS2 2.0 4.0 mA 85 mA Active Current ICC Write Protection Voltage VTP NOTES 4.25 V 13 INNOVATIVE IM1386 SRAM + RTC + Watchdog CAPACITANCE (tA = 25OC) SYMB OL PARAMETER TYP MAX. UNITS CIN Input Capacitance 7 15 COUT Output Capacitance 7 15 pF C DQ Input/Output Capacitance 7 15 pF pF AC ELECTRICAL CHARACTERISTICS (0OC to 70OC; Vcc = 5V +/- 10%) PARAMETERS SYMB OL MIN. Read Cycle TIme tRC 120 Access Time tACC 120 ns OE to Output Valid tOE 100 ns CE to Output Valid tCO 120 ns OE or CE to Output Active tCOE Output High Z from Deselection tOD Output Hold from Address Change tOH 10 ns Write Cycle Time tWC 120 ns Write Pulse Width tWP 110 ns Address Setup Time tAW 0 ns Write Recovery Time tWR 10 ns Output High Z from WE tODW Output Active from WE tOEW 10 ns Data Setup Time tDS 85 ns 4 Data Hold Time from WE tDH 10 ns 4,5 INTA, INTB Pulse Width tIPW 3 ms 11,12 AC TEST CONDITIONS Input Levels : 0V to 3V Transition Times : 5ns MAX. 10 UNITS NOTES ns 1 ns 40 40 ns 3 ns INNOVATIVE IM1386 SRAM + RTC + Watchdog READ CYCLE (Note 1) tRC VIH VIH Address VIL tAW CE VIL tACC tOH tCO VIH VIH VIL tOD tOE VIH OE VIH VIL tOD tCOE VOH VOH tCOE DOUT VOL OUTPUT DATA VALID WRITE CYCLE 1 (Notes 2, 6, 7) tWC ADDRESS VIH VIH VIL VIL tAW CE VIL VIL tWR tWP WE VIH VIL VIL tODW tOEW High Impedance DOUT tDS VIH DIN VIL tDH1 Data In Stable VIH VIL VOL INNOVATIVE IM1386 SRAM + RTC + Watchdog WRITE CYCLE 2 (Notes 2, 8) tWC ADDRESSES VIH VIH VIL VIL tWR tAW tWP CE VIH VIL VIL WE VIL VIL tCOE VIH tODW DOUT tDS VIH DIN VIL tDH Data In Stable VIH VIL POWER-UP / POWER-DOWN CONDITION CE VIH VIH tREC tPF 4.5V 4.25V 4.0V Vcc 4.5V 4.25V POWER FAIL TIMING DIAGRAM: INTERRUPT OUTPUTS PULSE MODE (NOTES 11, 12) INTB 4.0V tFB tR INTA, INTB tF tIPW VBAT INNOVATIVE IM1386 SRAM + RTC + Watchdog AC ELECTRICAL CHARACTERISTICS POWER-UP/POWER DOWN TIMING (0OC to 70OC) PARAMETER SYMB OL MIN MAX UNITS CE High to Power Fail tPF 0 ns Recovery at Power Up tREC 200 ms Vcc Slew Rate Power Down tF 4.0<Vcc<4.5V Vcc Slew Rate Power Down Vcc Slew Rate Power Down 300 us tFB 3.0<Vcc<4.25V 10 us tR 4.5>Vcc>4.0V 0 us tDR 10 years Expected Data Retention NOTES 9 WARNING : Under no circumstances are negative undershoots, of any amplitude, allowed when device is in battery backup mode. AC TEST CONDITONS Output Load : 50pF + 1TTL Gate Input Pulse Levels : 0 - 3.0V Timing Measurement Reference Levels Input : 1.5V Output : 1.5 V Input Pulse Rise and Fail Times : 5ns. NOTES : 1. WE is high for a read cycle. 2. OE = VI H or VIL . If OE = VI H during write cycle, the output buffers remain in a high impedance state. 3. tWP is specified as the logical AND of the CE and WE. tWP is measured from the latter of CE of WE going low to the earlier of CE or WE going high. 4. tDS or tDH are measured from the earlier of CE or WE going high. 5. tDH is measured from WE going high. If CE is used to terminate the write cycle, then t DH = 20 ns. 6. If the CE low transition occurs simultaneously with or later than the WE low transition Write Cycle 1, the ouput bufers remain in a high impedance state during this period. 7. If the CE high transition occurs prior to or simultaneously with the WE high transition, the output buffers remain in a high impedance state during this period. 8. If WE is low or the WE low transition occurs prior to or simultaneously with the CE low transiton, the output buffers remain in a high impedance state during this period. 9. Each IM1386 is marked with a four digit date code mm-yy. mm designates the month of manufacture. yy designates the year of manufacture. The expected tDR is defined as starting at the data of manufacture. 10. All voltages are referenced to ground. 11. Applies to both interrupts pins when the alarms are set to pulse. 12. Interrupt Output occurs within 100 ns on the alarm condition existing. 13. Both INTA and INTB (INTB) are open drain outputs. INNOVATIVE IM1386 SRAM + RTC + Watchdog INNOVATIVE IM1386 - 32 - 120 SRAM + RTC + WATCHDOG mm-yy B A C F G D J H E DIM IN INCHES MIN. MAX. A B C D E F G H J 1.740 0.740 0.415 0.120 0.021 0.160 0.110 0.630 0.012 1.720 0.720 0.395 0.090 0.015 0.120 0.090 0.590 0.008