ASDL-3023 IrDA Data Compliant Low Power 4Mbit/s with Remote Control Infrared Transceiver Data Sheet Description Features The ASDL-3023 is a new generation low profile high speed enhanced infrared (IR) transceiver module that provides the capability of (1) interface between logic and IR signals for through-air, serial, half-duplex IR data link, and (2) IR remote control transmission for universal remote control applications. The ASDL-3023 can be used for IrDA as well as remote control application without the need of any additional external components for multiplexing. General Features * Operating temperature from -25 C ~ 85C - Critical parameters are guaranteed over temperature and supply voltage * Vcc Supply 2.4 to 3.6 V * Interface to Various Super I/O and Controller Devices - Input/Output Interface Voltage of 1.5 V * Miniature Package Miniature Package (shielded) Height : 1.75 mm Height : 1.95 mm Width : 7.5 mm Width : 8.0 mm Depth : 2.75 mm Depth : 3.00 mm * Moisture Level 3 * Power Saving using 3 ILED range (SIR, MIR/FIR, RC mode) * LED stuck high protection * High EMI Performance * High ESD Performance * Designed to Accommodate Light Loss with Cosmetic Windows * IEC 825-Class 1 Eye Safe The ASDL-3023 is fully compliant to IrDA Physical Layer specification version 1.4 low power from 9.6 kbit/s to 4.0 Mbit/s (FIR) and IEC825 Class 1 eye safety standards. The ASDL-3023 can be shutdown completely to achieve very low power consumption. In the shutdown mode, the PIN diode will be inactive and thus producing very little photocurrent even under very bright ambient light. It is also designed to interface to input/output logic circuits as low as 1.5V. These features are ideal for battery operated mobile devices such as PDAs and mobile phones that require low power consumption. Applications Mobile data communication and universal remote control * Mobile Phones * PDAs * Digital Still Camera * Printer * Handy Terminal * Industrial and Medical Instrument Application Support Information The Application Engineering Group is available to assist you with the application design associated with ASDL3023 infrared transceiver module. You can contact them through your local sales representatives for additional details. IrDA Features * Fully Compliant to IrDA 1.4 Physical Layer Low Power Specifications from 9.6 kbit/s to 4.0 Mb/s - Link distance up to 30cm (minimum) * Complete shutdown * Low Power Consumption - Low shutdown current - Low idle current Remote Control Features * Wide angle and high radiant intensity * Spectrally suited to remote control transmission function * Minimum peak wavelength of 880nm * 2 RC Transmission Mode - Single TXD (Programmable Mode) - Dual TXD (Direct) Vdd R1 GND CX2 Vdd (7) CX1 GND (8) ASDL-3023 TRANSCEIVER MODULE IOVCC(5) CX5 TRANSCEIVER IC Regulated Voltage & Current Source SD(4) Photodetector RECEIVER VLED CX4 LEDA (1) TRANSMITTER TXD_RC Input TxD_IR(2) TXD_IR Input Figure 1a. Functional Block Diagram of ASDL-3023 Eye Safety-RC Eye Safety-IR Switched Current Source IR_Buffer TxD_RC(6) TRANSMIT TER AGC & Signal Reference Processor RC_Buffer CX3 R2 Amplifier Output Buffer RXD(3) Low Pass Filter LED Vdd R1 GND CX2 Vdd (7) CX1 GND (8) ASDL-3023 TRANSCEIVER MODULE IOVCC(5) CX5 SD(4) TRANSCEIVER IC Regulated Voltage & Current Source Photodetector RECEIVER CX4 LEDA (1) TRANSMITTER TXD_RC Input TxD_IR(2) TXD_IR Input Figure 1b. Functional Block Diagram of ASDL-3023-S21 Eye Safety-RC Eye Safety-IR Switched Current Source IR_Buffer TxD_RC(6) TRANSMIT TER AGC & Signal Reference Processor RC_Buffer CX3 R2 SHIELD VLED Amplifier Output Buffer RXD(3) Low Pass Filter LED Order Information Part Number Packaging Type Package Quantity ASDL-3023-021 Tape and Reel Front Option 2500 ASDL-3023-008 Tape and Reel Top Option 2500 ASDL-3023-S21 (Shielded) Tape and Reel Front Option 2500 Marking Information The unit is marked with `XYWLL' on the shield Y = year W = work week LL = lot number ASDL-3023-021, ASDL-3023-008 and ASDL-3023-S21 Pinout, Rear View I/O Pins Configuration Table Rear View 8 7 6 5 4 3 2 1 Figure 2a. Pin out for ASDL-3023-021 and ASDL-3023-008, Rear View 8 7 6 5 4 (Shielded) 3 2 Pin Symbol Description I/O Type Notes 1 LEDA LED Anode 2 TxD_IR IrDA transmitter data input. Input. Active High Note 2 3 RxD IrDA receive data Output. Active Low Note 3 4 SD Shutdown Input. Active High Note 4 5 IOVCC Input/Output ASIC voltage 6 TxD_RC RC transmitter data input. 7 VCC Supply Voltage Note 7 8 GND Ground Note 8 Note 1 Note 5 Input. Active High Note 6 1 Figure 2b. Pin out for ASDL-3023-S21 Notes: 1. Tied through external resistor, R2, to Vled. Refer to the table below for recommended series resistor value. 2. This pin is used to transmit serial data when SD pin is low. If held high for longer than 50 ms, the LED is turned off. Do NOT float this pin. 3. This pin is capable of driving a standard CMOS or TTL load. No external pull-up or pull-down resistor is required. The pin is in tri-state when the transceiver is in shutdown mode 4. Complete shutdown of IC and PIN diode. The pin is used for setting IR receiver bandwidth, range of IR LED current and RC drive programming mode. Refer to section on "Bandwidth Selection Timing" and "Remote Control Drive Modes" for more information. Do NOT float this pin. *** 5. Connect to ASIC logic controller supply voltage or Vcc. The voltage at this pin should be equal to or less than Vcc. 6. Logic high turns on the RC LED. If held high longer than 50 ms, the RC LED is turned off. Do NOT float the pin. 7. (i) Regulated, 2.4V to 3.6V (ii) This pin recommended to turn on before other pin. 8. Connect to system ground. Recommended Application Circuit Components Component Recommended Value Note R1 4.7W,5%, 0.25 watt for Vcc 3.0V R2 2.7W, for 2.4 VLED 2.7V; 3.3W, for 2.7 <VLED 3.0V 3.9W, for 3.0 <VLED 3.3V 4.7W, for 3.3 <VLED 3.6V 5.6W, for 3.6 <VLED 4.2V 10W, for 4.2 <VLED 5V CX1, CX3, CX5 100 nF, 20%, X7R Ceramic 1 CX2, CX4 4.7mF, 20%, Tantalum 1 Notes: CX1, CX2, CX3 & CX4 must be placed within 0.7cm of ASDL-3023 to obtain optimum noise immunity Absolute Maximum Ratings For implementations where case to ambient thermal resistance is 50C/W. Parameter Symbol Min. Max. Units Conditions Ref Storage Temperature TS -40 +100 C Operating Temperature TA -25 +85 C LED Anode Voltage VLEDA -0.3 6.5 V Supply Voltage VCC -0.3 6 V Input Voltage : TXD, SD/Mode VI -0.3 5.5 V Output Voltage : RXD VO -0.3 5.5 V Peak IR LED Current IIRLED (PK) 200 mA 25% duty cycle, 90 ms pulse width Fig 3 Peak RC LED Current IRCLED(PK) 300 mA 10% duty cycle, 90 ms pulse width Fig 4 CAUTION: The CMOS inherent to the design of this component increases the component's susceptibility to damage from electrostatic discharge (ESD). It is advised that normal static precautions be taken in handling and assembly of this component to prevent damage and/or degradation which may be induced by ESD Recommended Operating Conditions Parameter Symbol Min. Operating Temperature TA Supply Voltage VCC Input/Output Voltage Logic Input Voltage for TXD, SD/Mode Receiver Input Irradiance Max. Units -25 +85 C 2.4 3.6 V IOVCC 1.5 3.6 V Logic High VIH IOVcc-0.5 IOVcc V Logic Low VIL 0 0.4 V Logic High EIH 0.0090 500 mW/cm2 0.0225 500 For in-band signals 115.2kbit/s [3] 0.576 Mbit/s in-band signals 4.0 Mbit/s [3] mW/cm2 For in-band signals [3] Logic Low EIL IR LED (Logic High) Current Pulse Amplitude - SIR Mode ILEDA IR LED (Logic High) Current Pulse Amplitude - MIR/FIR Mode ILEDA RC LED (Logic High) Current Pulse Amplitude ILEDA Receiver Data Rate Ambient Light Typ. 0.3 65 Conditions mA mA 150 250 0.0096 mA 4.0 Mbit/s See IrDA Serial Infrared Physical Layer Link Specification, Appendix A for ambient levels Note : 3. An in-band optical signal is a pulse/sequence where the peak wavelength, lp, is defined as 850 lp 900 nm, and the pulse characteristics are compliant with the IrDA Serial Infrared Physical Layer Link Specification v1.4. Electrical and Optical Specifications Specifications (Min. & Max. values) hold over the recommended operating conditions unless otherwise noted. Unspecified test conditions may be anywhere in their operating range. All typical values (Typ.) are at 25C, Vcc set to 3.0V and IOVcc set to 1.5V unless otherwise noted. Receiver Parameter Viewing Angle Peak Sensitivity Wavelength RxD_IrDA Output Voltage Symbol 2q1/2 lP Logic High VOH Logic Low VOL [4, 5] RxD_IrDA Pulse Width (SIR) tRPW(SIR) RxD_IrDA Pulse Width (MIR) [4, 6] tRPW(MIR) [4, 7] RxD_IrDA Pulse Width (Single) (FIR) tRPW(FIR) RxD_IrDA Pulse Width (Double) (FIR) [4, 7] tRPW(FIR) RxD_IrDA Rise & Fall Times tr, tf [8] Receiver Latency Time tL Receiver Wake Up Time [9] tRW Min. 30 Typ. Max. 875 IOVcc - 0.5 0 1 100 80 200 IOVCC 0.4 4 500 175 290 60 100 200 Units nm V V ms ns ns ns ns ms ms Conditions Units mW/sr Conditions IR_ILEDA = 65mA, q1/2 15, TxD_IR VIH, TA = 25C IR_ILEDA = 150mA, q1/2 15, TxD_IR VIH, TA = 25C IOH = -200 mA, EI 0.3 mW/cm2 q1/2 15, CL=9pF q1/2 15, CL=9pF q1/2 15, CL=9pF q1/2 15, CL=9pF CL=9pF EI = 9.0 mW/cm2 EI = 10 mW/cm2 Infrared (IR) Transmitter Parameter IR Radiant Intensity (SIR Mode) IR Radiant Intensity (MIR/FIR Mode) Symbol IEH Min. 4 Typ. 20 IEH 10 50 IR Viewing Angle IR Peak Wavelength TxD_IrDA Logic Levels 2q1/2 lP VIH VIL IH IL tTW tPW(Max) tPW(SIR) tPW(MIR) tPW(FIR) tr, tf 30 850 IOVcc-0.5 0 TxD_IrDA Input Current Wake Up Time [10] Maximum Optical Pulse Width [11] TXD Pulse Width (SIR) TXD Pulse Width (MIR) TXD Pulse Width (FIR) TxD Rise & Fall Times (Optical) High Low High Low 885 0.02 -0.02 180 25 1.6 217 125 Max. mW/sr 60 900 IOVCC 0.5 120 600 40 IR LED Anode On-State Voltage (SIR Mode) VON IR LED Anode On-State Voltage (MIR/FIR Mode) VON nm V V mA mA ns ms ms ns ns ns 2.2 ns V 2.1 V (IR_LEDA) (IR_LEDA) VI VIH 0 VI VIL tPW(TXD_IR)=1.6ms at 115.2 kbit/s tPW(TXD_IR)=217ns at 1.152 Mbit/s tPW(TXD_IR)=125ns at 4.0 Mbit/s tPW(TXD_IR)=1.6ms at 115.2 kbit/s tPW(TXD_IR)=125ns at 4.0 Mbit/s IR_ILEDA=65mA, IR VLED = 3.6V, R = 4.7W, VI(TxD) VIH IR_ILEDA=150mA, IR VLED = 3.6V, R = 4.7W, VI(TxD_IR) VIH Remote Control (RC) Transmitter Parameter RC Radiant Intensity Symbol IEH Min. RC Viewing Angle RC Peak Wavelength TxD_RC Logic Levels 2q1/2 lP VIH VIL IH IL VON 30 880 IOVcc-0.5 0 TxD_RC Input Current RC LED Anode On-State Voltage High Low High Low Typ. 80 Max. Units mW/sr 60 900 IOVCC 0.5 1 1 nm V V mA mA V Typ. Max. Units Conditions 0.01 1 mA VI VIH -0.02 1 mA 0 VI VIL 1 mA VSD IOVCC-0.5, TA=25C 2.9 mA VI(TxD) VIL, EI=0 mA VI(TxD) VIL, EI=10mW/cm2 885 0.02 -0.02 2 Conditions RC_ILEDA = 250mA, q1/2 15, TxD_RC VIH, TA = 25 C VI VIH 0 VI VIL RC_ILEDA=250mA, RC VLED = 3.6V, R = 4.7W, VI(TxD_RC) VIH (RC_LEDA) Transceiver Parameters Symbol Input Current Supply Current Min. High IH Low IL Shutdown ICC1 Idle (Standby) ICC2 2.0 Active ICC3 3.5 -1 Note: [4] An in-band optical signal is a pulse/sequence where the peak wavelength, lP, is defined as 850 nm lP 900 nm, and the pulse characteristics are compliant with the IrDA Serial Infrared Physical Layer Link Specification version 1.4. [5] For in-band signals 115.2 kbit/s where 9 mW/cm2 EI 500 mW/cm2. [6] For in-band signals 1.152 Mbit/s where 22 mW/cm2 EI 500 mW/cm2. [7] For in-band signals 4 Mbit/s where 22 mW/cm2 EI 500 mW/cm2. [8] Latency is defined as the time from the last TxD_IrDA light output pulse until the receiver has recovered full sensitivity. [9] Receiver Wake Up Time is measured from Vcc power ON to valid RxD_IrDA output. [10] Transmitter Wake Up Time is measured from Vcc power ON to valid light output in response to a TxD_IrDA pulse. [11] The Max Optical PW is defined as the maximum time which the IR LED will turn on, this, is to prevent the long Turn On time for the IR LED. Max. Permissible Peak LED Current I LED(DC) , Maximum DC LED Current - mA ILED(PK) Maximum Peak LED Current - mA 350 300 250 200 150 100 50 0 -40 -20 0 20 40 60 TA - Ambient Temperature - oC 80 100 Figure 3. Maximum Peak IR LED current vs. ambient temperature. Derated based on TJMAX = 100C. Max. Permissible DC LED Current 70 60 50 40 Rja = 400degC/W 30 20 10 0 -40 -20 0 20 40 60 TA - Ambient Temperature - oC 80 100 Figure 4. Maximum Peak RC LED current vs. ambient temperature. Derated based on TJMAX = 100C. Figure 5a. Timing Waveform - RXD Output Waveform Figure 5b. Timing Waveform - LED Optical Waveform Figure 5c. Timing Waveform - TXD "Stuck-on" Protection Waveform Figure 5d. Timing Waveform - Receiver Wakeup Time Waveform Figure 5e. Timing Waveform - TXD Wakeup Time Waveform Package Dimension: ASDL-3023-021 (Shieldless, Front) and ASDL-3023-008 (Shieldless, Top) 10 Package Dimension: ASDL-3023-S21 (Shielded, Front) 11 Tape & Reel Dimensions ASDL-3023-021 (Shieldless, Front) ASDL-3023-008 (Shieldless, Top) 12 ASDL-3023-S21 (Shielded, Front) Progressive Direction Empty Parts Mounted Leader (400mm min) (40mm min) Empty (40mm min) Option # "B" "C" Quantity 021 330 80 2500 S21 330 2500 008 330 80 80 2500 Unit: mm Detail A 2.0 0.5 B C 13.0 0.5 R1.0 LABEL 21 0.8 Detail A 16.4 +2 0 2.0 0.5 13 ASDL-3023 Moisture Proof Packaging All ASDL-3023 options are shipped in moisture proof package. Once opened, moisture absorption begins. This part is compliant to JEDEC Level 3. UNITS IN A SEALED MOISTURE-PROOF PACKAGE PACKAGE IS OPENED (UNSEALED) PARTS ARE NOT RECOMMENDED TO BE USED ENVIRONMENT LESS THAN 30 oC AND LESS THAN 60% RH NO YES PACKAGE IS OPENED LESS THAN 168 HOURS YES NO BAKING IS NECESSARY NO NO PACKAGE IS OPENED LESS THAN 15 DAYS YES PERFORM RECOMMENDED BAKING CONDITIONS Figure 6. Baking Conditions Chart Recommended Storage Conditions Baking Conditions Storage Temperature 10C to 30C Package Temp Time Relative Humidity below 60% RH In reels 60 C 48hours In bulk 100 C 4hours Time from unsealing to soldering After removal from the bag, the parts should be soldered within 7 days if stored at the recommended storage conditions. When MBB (Moisture Barrier Bag) is opened and the parts are exposed to the recommended storage conditions more than 7 days but less than 15 days the parts must be baked before reflow to prevent damage to the parts. Note: To use the parts that exposed for more than 15 days is not recommended. 14 Baking should only be done once. Recommended Reflow Profile MAX 260C T - TEMPERATURE (C) 255 R3 230 217 200 180 R2 R4 60 sec to 90 sec Above 217C 150 R5 R1 120 80 25 0 P1 HEAT UP 50 100 P2 SOLDER PASTE DRY 150 200 250 P3 SOLDER REFLOW P4 COOL DOWN 300 t-TIME (SECONDS) Process Zone Symbol DT Maximum DT/Dtime or Duration Heat Up P1, R1 25C to 150C 3C/s Solder Paste Dry P2, R2 150C to 200C 100s to 180s Solder Reflow P3, R3 P3, R4 200C to 260C 260C to 200C 3C/s -6C/s Cool Down P4, R5 200C to 25C -6C/s Time maintained above liquidus point , 217C > 217C 60s to 90s Peak Temperature 260C - Time within 5C of actual Peak Temperature - 20s to 40s Time 25C to Peak Temperature 25C to 260C 8mins The reflow profile is a straight-line representation of a nominal temperature profile for a convective reflow solder process. The temperature profile is divided into four process zones, each with different DT/Dtime temperature change rates or duration. The DT/Dtime rates or duration are detailed in the above table. The temperatures are measured at the component to printed circuit board connections. In process zone P1, the PC board and ASDL-3023 pins are heated to a temperature of 150C to activate the flux in the solder paste. The temperature ramp up rate, R1, is limited to 3C per second to allow for even heating of both the PC board and ASDL-3023 pins. Process zone P2 should be of sufficient time duration (100 to 180 seconds) to dry the solder paste. The temperature is raised to a level just below the liquidus point of the solder. Process zone P3 is the solder reflow zone. In zone P3, the temperature is quickly raised above the liquidus point of solder to 260C (500F) for optimum results. The dwell time above the liquidus point of solder should be between 60 and 90 seconds. This is to assure proper coalescing of the solder paste into liquid solder and the formation of good solder connections. Beyond the recommended dwell time the intermetallic growth within the solder connections becomes excessive, resulting in the formation of weak and unreliable connections. The temperature is then rapidly reduced to a point below the solidus temperature of the solder to allow the solder within the connections to freeze solid. Process zone P4 is the cool down after solder freeze. The cool down rate, R5, from the liquidus point of the solder to 25C (77F) should not exceed 6C per second maximum. This limitation is necessary to allow the PC board and ASDL-3023 pins to change dimensions evenly, putting minimal stresses on the ASDL-3023. It is recommended to perform reflow soldering no more than twice. 15 Appendix A: ASDL-3023 SMT Assembly Application Note Solder Pad, Mask and Metal Stencil Figure A1. Stencil and PCBA Recommended land pattern for ASDL-3023- 008 Recommended land pattern for ASDL-3023-021 Mounting Centre Mounting Centre 0.44 1.74 1.55 0.4 1.05 0.17 0.1 0.7 0.775 FIDUCIAL 1.75 1.60 0.55 0.55 1.05 1.35 1.05 1.35 3.75 3.75 7.5 7.5 UNIT: mm Figure A2a. Recommended land pattern, ASDL-3023-021 UNIT: mm Figure A2c. Recommended land pattern, ASDL-3023-008 Recommended land pattern for ASDL-3023- S21 1.3 Mounting Centre 1.5 0.3 1.55 0.1 0.775 1.75 0.55 1.05 1.35 3.75 7.5 UNIT: mm Figure A2b. Recommended land pattern, ASDL-3023-S21 16 Recommended Metal solder Stencil Aperture Adjacent Land Keepout and Solder Mask Areas It is recommended that only a 0.11 mm (0.004 inch) or a 0.127 mm (0.005 inch) thick stencil be used for solder paste printing. This is to ensure adequate printed solder paste volume and no shorting. See the Table 1 below the drawing for combinations of metal stencil aperture and metal stencil thickness that should be used. Aperture opening for shield pad is 2.6 mm x 1.5 mm(for ASDL3023-S1) as per land pattern. Compared to 0.127mm stencil thickness 0.11mm stencil thickness has longer length in land pattern. It is extended outwardly from transceiver to capture more solder paste volume. Adjacent land keepout is the maximum space occupied by the unit relative to the land pattern. There should be no other SMD components within this area. The minimum solder resist strip width required to avoid solder bridging adjacent pads is 0.2mm.It is recommended that two fiducially crosses be placed at mid length of the pads for unit alignment. Note: Wet/Liquid Photo-imaginable solder resist/mask is recommended j k h l Solder Mask Figure A3. Solder stencil aperture Table 1. Dimension mm Width,w h 0.2 1.75+/-0.05 0.55+/-0.05 l 3.0 2.4+/-0.05 0.55+/-0.05 k 3.85 j 10.1 Stencil thickness, t(mm) Aperture size(mm) Length,l 0.127mm 0.11mm 17 Appendix B: PCB Layout Suggestion The effects of EMI and power supply noise can potentially reduce the sensitivity of the receiver, resulting in reduced link distance. The PCB layout played an important role to obtain a good PSRR and EM immunity resulting in good electrical performance. Things to note: 1. The ground plane should be continuous under the part, but should not extend under the shield trace. 2. The shield trace is a wide, low inductance trace back to the system ground. CX1, CX2, CX3, CX4 and CX5 are optional supply filter capacitors; they may be left out if a clean power supply is used. 3. VLED can be connected to either unfiltered or unregulated power supply. The bypass capacitors should be connection before the current limiting resistor R2 respectively. In a noisy environment, including capacitor CX3and CX4 can enhance supply rejection. CX3 that is generally a ceramic capacitor of low inductance providing a wide frequency response while CX4 is tantalum capacitor of big volume and fast frequency response. The use of a tantalum capacitor is more critical on the VLED line, which carries a high current. 4. VCC pin can be connected to either unfiltered or unregulated power supply. The Resistor, R1 together with the capacitors, CX 1and CX2 acts as the low pass filter. 5. IOVCC is connected to the ASIC voltage supply or the VCC supply. The capacitor, CX5 acts as the bypass capacitor. 6. Preferably a multi-layered board should be used to provide sufficient ground plane. Use the layer underneath and near the transceiver module as Vcc, and sandwich that layer between ground connected board layers. The diagram below demonstrate an example of a 4 layer board : * Top Layer: Connect the metal shield and module ground pin to bottom ground layer; Place the bypass capacitors within 0.5cm from the VCC and ground pin of the module. * Layer 2: Critical ground plane zone. 3 cm in all direction around the module. Connect to a clean, noiseless ground node (eg bottom layer). * Layer 3: Keep data bus away from critical ground plane zone. * Bottom layer: Ground layer. Ground noise <75 mVp-p. Should be separated from ground used by noisy sources. The area underneath the module at the second layer, and 3cm in all direction around the module is defined as the critical ground plane zone. The ground plane should be maximized in this zone. Refer to application note AN1114 or the Avago Technologies IrDA Data Link Design Guide for details. The layout below is based on a 2-layer PCB. Noise sources to be placed as far away from the transceiver as possible Top Layer R 1 CX1 CX2 CX5 R 2 CX3 CX4 Top Layer Layer 3 Layer 2 Legend: ground via Bottom Layer (GND) 18 Bottom Layer Appendix C: General Application Guide for the ASDL-3023 infrared IrDA Compliant 4 Mb/s Transceiver. Description Interface to the Recommended I/O chip The ASDL-3023, a wide-voltage operating range infrared transceiver is a low-cost and small form factor device that is designed to address the mobile computing market such as PDAs, as well as small embedded mobile products such as digital cameras and cellular phones. It is spectrally suited to universal remote control transmission function at 940 nm typically. It is fully compliant to IrDA 1.4 low power specification The ASDL-3023's TXD data input is buffered to allow for CMOS drive levels. No peaking circuit or capacitor is required. Data rate from 9.6kb/s to 4Mb/s is available at RXD pin. The TXD_RC, pin6 together with LEDA, pin1 is used to selected the remote control transmit mode. Alternatively, the TXD_IR, pin2 together with LEDA, pin1 is used for infrared transmit selection. up 4Mb/s and support most remote control codes The design of ASDL-3023 also includes the following unique features : * Spectrally suited to universal remote transmission function at 940nm typically; control * Low passive component count; * Shutdown mode for low power consumption requirement; * Direct interface with I/O logic circuit. Following shows the hardware reference design with ASDL-3023 *Detail configuration of ASDL-3023 with the controller chip is shown in Figure 3. The use of the infrared techniques for data communication has increase rapidly lately and almost all mobile application processors have built in the IR port. This does away with the external Endec and simplifies the interfacing to a direct connection between the processor and the transceiver. The next section discusses interfacing configuration with a general processor. Selection of Resistor R2 Resistor R2 should be selected to provide the appropriate peak pulse IR and RC LED current respectively at different ranges of Vcc as shown on page 3 under "Recommended Application circuit components". STN/TFT LCD Panel LCD Control Touch Panel Key Pad Peripherial interface PWM A/D LCD Backlight Contrast *ASDL-3023 Mobile Application chipset IrDA interface AC97 sound Logic Bus Driver Memory Expansion FLASH SDRAM Figure 2. Mobile Application Platform 19 Memory I/F Baseband I2S controller ROM PCM Sound Power Management Antenna Audio Input General mobile application processor Remote Control Operation The transceiver is directly interface with the microprocessor provided its support infrared communication commonly known as Infrared Communications Port (ICP). The ICP supports both SIR data rates up to 115.2kps and sometimes FIR data with data rates up to 4Mbps. The remote control commands can be sent one of the available General Purpose IO pins or the UART block with IrDA functionality. It should be should be observed that although both IrDA data transmission and Remote control transmission is possible simultaneously by the hardware, hence the software is required to resolve this issue to prevent the mixing and corruption of data while being transmitted over the free air. The above Figure 3 illustrates a reference interfacing to implement both IR and RC functionality with ASDL-3023. The ASDL-3023 is spectrally suited to universal remote control transmission function at 940nm typically. Remote control applications are not governed by any standards, owing to which there are numerous remote codes in market. Each of those standards results in receiver modules with different sensitivities, depending on the carries frequencies and responsively to the incident light wavelength. Remote control carrier frequencies are in the range of 30KHz to 60KHz (for details of some the frequently used carrier frequencies, please refer to AN1314). Some common carrier frequencies and the corresponding SA-1110 UART frequency and baud rate divisor are shown in Table 3. Table 3. Remote Control Carrier Frequency (KHz) SA-1110 UART Frequency (KHz) Baud Rate Divisor 30 28.8 8 32,33 32.9 7 36,36.7,38,39.2,40 38.4 6 56 57.6 4 VCC R1 CX1 IOVCC GND CX2 GND VCC IOVCC IOVCC CX5 GND GPIO TXD_RC IR_RXD RXD SD GPIO IR_TXD 100Kohm VLED TXD_IR R3 VLEDA 100Kohm HSDL3021 GND CX3 GND CX4 GND Figure 3. ASDL-3023 configuration with general mobile architecture processor 20 Appendix E: Window Design for ASDL-3023. OPAQUE MATERIAL IR TRANSPARENT WINDOW Y X Z OPAQUE WINDOW T IR TRANSPARENT WINDOW Z To ensure IrDA compliance, some constraints on the height and width of the window exist. The minimum dimensions ensure that the IrDA cones angles are met without vignetting. The maximum dimensions minimize the effects of stray light. The minimum size corresponds to a cone angle of 300 and the maximum size corresponds to a cone angle of 600. Depth(Z) Y(Min) X(Min) Y(Max) X(Max) 0 1.70+W1 7.20+W1 3.66+W2 9.26+W2 1 2.23+W1 7.73+W1 4.82+W2 10.32+W2 2 2.77+W1 8.27+W1 5.97+W2 11.47+W2 3 3.31+W1 8.81+W1 7.12+W2 12.62+W2 4 3.84+W1 9.34+W1 8.28+W2 13.78+W2 5 4.38+W1 9.88+W1 9.43+W2 14.93+W2 6 4.91+W1 10.41+W1 10.59+W2 16.09+W2 7 5.45+W1 10.95+W1 11.74+W2 17.24+W2 W1 = 0.3456*T, W2 = 0.6967*T, where T is the window thickness 8 5.99+W1 11.49+W1 12.90+W2 18.40+W2 9 6.52+W1 12.02+W1 14.05+W2 19.55+W2 For the modules depth values that are not shown on the tables above, the minimum X and Y values can be interpolated. 10 7.06+W1 12.56+W1 15.21+W2 20.71+W2 In the figure above, X is the width of the window, Y is the height of window, Z is the distance from the ASDL-3023 to the back of the window and T is the thickness of the IR transparent window. 21 Window Material Shape of the Window Almost any plastic material will work as a window material. Polycarbonate is recommended. The surface finish of the plastic should be smooth, without any texture. An IR filter dye may be used in the window to make it look black to the eye, but the total optical loss of the window should be 10% or less for best optical performance. Light loss should be measured at 875 nm. The recommended plastic materials for use as a cosmetic window are available from General Electric Plastics. From an optics standpoint, the window should be flat. This ensures that the window will not alter either the radiation pattern of the LED, or the receive pattern of the photodiode. If the window must be curved for mechanical or industrial design reasons, place the same curve on the backside of the window that has an identical radius as the front side. While this will not completely eliminate the lens effect of the front curved surface, it will significantly reduce the effects. The amount of change in the radiation pattern is dependent upon the material chosen for the window, the radius of the front and back curves, and the distance from the back surface to the transceiver. Once these items are known, a lens design can be made which will eliminate the effect of the front surface curve. The following drawings show the effects of a curved window on the radiation pattern. In all cases, the center thickness of the window is 1.5 mm, the window is made of polycarbonate plastic, and the distance from the transceiver to the back surface of the window is 3 mm. Recommended Plastic Materials: Material # Light Transmission Haze Refractive Index Lexan 141 88% 1% 1.586 Lexan 920A 85% 1% 1.586 Lexan 940A 85% 1% 1.586 Note: 920A and 940A are more flame retardant than 141. Recommended Dye: Violet #21051 (IR transmissant above 625mm) Flat Window, (First Choice) 22 Curved Front and Back, (Second Choice) Curved Front, Flat Back, (Do not use) Appendix F: General Application Guide for the ASDL-3023 Two-TxD Direct Transmission Mode Remote Control Drive Modes In the two-TxD direct transmission mode, the LED can be driven separately for IrDA and RC mode of operation through the TxD_IR and TxD_RC pins respectively. This mode can be used when the external controller utilizes separate transmit pins for IrDA and RC operation modes, thereby eliminating the need for external multiplexing. The ASDL-3023 can operate in the single-TxD programmable mode or the two-TxD direct transmission mode. Single-TxD Programmable Mode In the single-TxD programmable mode, only one input pin (TxD_IR input pin) is used to drive the LED in both IrDA mode as well as Remote Control mode of operation. This mode can be used when the external controller uses only one transmit pin for both IrDA as well RC mode of operation. Please refer to the Transceiver I/O truth table for more detail. Transceiver Control I/O Truth Table for Two-TxD Direct Transmission Mode transceiver is in default mode (IrDA-SIR) when powered up. The user needs to apply the following programming sequence to both the TxD_IR and SD inputs to enable the transceiver to operate in either the IrDA or remote control mode. SD TxIR TxRC LED Remarks 0 0 0 OFF IR Rx enabled. Idle mode 0 0 1 ON Remote control operation 0 1 0 ON IrDA Tx operation 0 1 1 - Not recommended (Both Transmitters off) 1 0 0 OFF Shutdown mode* * The shutdown condition will set the transceiver to the default mode (IrDA-SIR) tC tB tA tTL tC SHUTDOWN (ACTIVE HIGH) tH tH tH TxIR (ACTIVE HIGH) SHUTDOWN TxRC (GND) DRIVE IrDA LED DRIVE RC LED RC MODE DRIVE IrDA LED RESET Mode Programming Timing Table The following timings describe input constraints required using the active serial interface for mode programming with pins SD, TxIR, and TxRC: Parameter Symbol Min Typ Max Unit Notes Shutdown input pulse width, at pin SD tSDPW 30 - s Will activate complete shutdown SD mode setup time tA 200 - - Ns Setup for mode programming TxIR pulse width for RC mode tB 200 - - Ns RC drive enabled with pin TxIR SD programming pulse width Note: ( tA + tB ) < tC < tSDPW tC - - 5.0 s Pulse width mode programming TxIR setup time for SIR or MIR/FIR mode tS 50 - - Ns Setup time for IrDA bandwidth selection TxIR or SD hold time to latch SIR, MIR/FIR or RC mode tH 50 - - Ns Hold time for IrDA or RC modes 23 Bandwidth Selection Timing The power on state should be the IrDA SIR mode. The data transfer rate must be set by a programming sequence using the TxD_IR and SD inputs as described below. Note: SD should not exceed the maximum, tC 5s, to prevent shutdown. Setting to the High Bandwidth MIR/FIR Mode (0.576Mbits/s to 4Mbits/s) Setting to the LOW Bandwidth SIR Mode (2.4kbits/s to 115.2kbits/s) 1. Set SD input to logic "HIGH". 2. Set TxIR input to logic "LOW". Wait tS 50ns. 3. Set SD to logic "LOW" (this negative edge latches state of TxIR, which determines speed setting). 4. TxIR must be held for tS 50ns. TxIR is now re-enabled as normal IrDA transmit input for the Low Bandwidth SIR mode. 1. Set SD input to logic "HIGH". Wait tA 200ns 2. Set TxD_IR input to logic "HIGH". Wait tS 50ns. 3. Set SD to logic "LOW" (this negative edge latches state of TxD_IR, which determines speed setting). 4. After waiting tH 50ns TxD_IR can be set to logic "LOW". TxD_IR is now re-enabled as normal IrDA transmit input for the High Bandwidth MIR/FIR mode. 50% SD tA tS 50% TxI R 24 50% tC tH High: MIR/FIR 50% Low: SIR Power-Up Sequencing To have a proper operation for ASDL-3023, the following power-up sequencing must be followed. (a) It's strongly recommended that Vcc must come prior to IOVcc. V CC t IOVccDL >- 0us IOV CC t SDDL >- 30us SD t SDPW >- 30us (b) It is not recommended to turn on IOVcc before Vcc while SD is low. However, for application that IOVcc come prior to Vcc while SD is low, SD pin has to set high to assure proper functionality. V CC IOV CC t SDDL >- 30us SD t SDPW >- 30us (c) Setting IOVcc high before Vcc while SD is high is forbidden. V CC IOV CC SD For product information and a complete list of distributors, please go to our web site: Note: t IOVccDL : IOVcc delay time t SDDL : SD delay time t SDPW : Shutdown Input Pulse Width www.avagotech.com Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies, Limited in the United States and other countries. Data subject to change. Copyright (c) 2007 Avago Technologies Limited. All rights reserved. AV02-0054EN - May 17, 2007