© Semiconductor Components Industries, LLC, 2011
November, 2017 − Rev. 7 1Publication Order Number:
BS170/D
BS170
Small Signal MOSFET
500 mA, 60 Volts
N−Channel TO−92 (TO−226)
Features
•This is a Pb−Free Device*
MAXIMUM RATINGS
Rating Symbol Value Unit
Drain−Source Voltage VDS 60 Vdc
Gate−Source Voltage
− Continuous
− Non−repetitive (tp ≤ 50 ms) VGS
VGSM
±20
±40 Vdc
Vpk
Drain Current (Note) ID0.5 Adc
Total Device Dissipation @ TA = 25°C PD350 mW
Operating and Storage Junction
Temperature Range TJ, Tstg −55 to
+150 °C
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be af fected.
NOTE: The Power Dissipation of the package may result in a lower continuous
drain current.
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
BS170
AYWWG
G
A = Assembly Location
Y = Year
WW = Work Week
G= Pb−Free Package
MARKING DIAGRAM
& PIN ASSIGNMENT
D
G
TO−92 (TO−226)
CASE 29
STYLE 30
N−Channel
S
123
1
Drain 3
Source
2
Gate
500 mA, 60 Volts
RDS(on) = 5.0 W
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(Note: Microdot may be in either location)
BS170
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2
ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise noted)
Characteristic Symbol Min Typ Max Unit
OFF CHARACTERISTICS
Gate Reverse Current
(VGS = 15 Vdc, VDS = 0) IGSS − 0.01 10 nAdc
Drain−Source Breakdown Voltage
(VGS = 0, ID = 100 mAdc) V(BR)DSS 60 90 − Vdc
ON CHARACTERISTICS (Note 1)
Gate Threshold Voltage
(VDS = VGS, ID = 1.0 mAdc) VGS(Th) 0.8 2.0 3.0 Vdc
Static Drain−Source On Resistance
(VGS = 10 Vdc, ID = 200 mAdc) rDS(on) − 1.8 5.0 W
Drain Cutoff Current
(VDS = 25 Vdc, VGS = 0 Vdc) ID(off) − − 0.5 mA
Forward Transconductance
(VDS = 10 Vdc, ID = 250 mAdc) gfs − 200 − mmhos
SMALL−SIGNAL CHARACTERISTICS
Input Capacitance
(VDS = 10 Vdc, VGS = 0, f = 1.0 MHz) Ciss − − 60 pF
SWITCHING CHARACTERISTICS
T urn−On Time
(ID = 0.2 Adc) See Figure 1 ton − 4.0 10 ns
T urn−Off Time
(ID = 0.2 Adc) See Figure 1 toff − 4.0 10 ns
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
1. Pulse Test: Pulse Width v 300 ms, Duty Cycle v 2.0%.
ORDERING INFORMATION
Device Package Shipping†
BS170 TO−92 (TO−226)
(Pb−Free) 1000 Unit/Tube
BS170RLRAG TO−92 (TO−226)
(Pb−Free) 2000 Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
BS170
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3
, DRAIN CURRENT (AMPS)
D(on)
I
, DRAIN CURRENT (AMPS)
D(on)
I
Figure 1. Switching Test Circuit
20 dB
50 W ATTENUATOR
PULSE GENERATOR
+25 V
Vin
40 pF
1.0 MW
50 W
125 W
50 W
Vout
TO SAMPLING SCOPE
50 W INPUT
OUTPUT
INVERTED
INPUT PULSE
WIDTH
10%
50%
10%
90%
90%
toff
ton
Figure 2. Switching Waveforms
RESISTIVE SWITCHING
(Vin Amplitude 10 Volts)
Vin
Vout
2.0
1.6
1.2
0.8
0.4
0
, THRESHOLD VOLTAGE
50 150
050
100
TJ, JUNCTION TEMPERATURE (°C)
VGS(th)
VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)
0.8
0.4
1.2
2.0
1.6
1.0 2.0 3.0 4.00
VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)
0.8
0.4
1.2
1.6
2.0
01020 30
VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)
C, CAPACITANCE (pF)
0 10 2030 4050
60
40
20
80
100
40 60
Figure 3. VGS(th) Normalized versus Temperature Figure 4. On−Region Characteristics
Figure 5. Output Characteristics Figure 6. Capacitance versus
Drain−To−Source Voltage
VGS = 10 V
VGS = 0 V
Ciss
Coss
Crss
9.0 V
8.0 V
7.0 V
6.0 V
5.0 V
4.0 V
VDS = VGS
ID = 1.0 mA
VGS = 10 V
9.0 V
8.0 V
7.0 V
6.0 V
5.0 V
4.0 V
TO−92 (TO−226) 1 WATT
CASE 29−10
ISSUE A
DATE 08 MAY 2012
STYLES ON PAGE 2
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1994.
2. CONTROLLING DIMENSION: INCHES.
3. CONTOUR OF PACKAGE BEYOND DIMENSION R IS
UNCONTROLLED.
4. DIMENSION F APPLIES BETWEEN DIMENSIONS P
AND L. DIMENSIONS D AND J APPLY BETWEEN DI
MENSIONS L AND K MINIMUM. THE LEAD
DIMENSIONS ARE UNCONTROLLED IN DIMENSION
P AND BEYOND DIMENSION K MINIMUM.
R
A
P
J
L
B
K
G
H
SECTION X−X
C
V
D
N
N
XX
1
SCALE 1:1
123
12
BENT LEADSTRAIGHT LEAD
3
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. CONTROLLING DIMENSION: INCHES.
3. CONTOUR OF PACKAGE BEYOND DIMENSION R IS
UNCONTROLLED.
4. DIMENSION F APPLIES BETWEEN DIMENSIONS P
AND L. DIMENSIONS D AND J APPLY BETWEEN
DIMENSIONS L AND K MINIMUM. THE LEAD
DIMENSIONS ARE UNCONTROLLED IN DIMENSION
P AND BEYOND DIMENSION K MINIMUM.
R
A
P
J
B
K
G
SECTION X−X
C
V
D
N
XX
SEATING
PLANE
1
T
STRAIGHT LEAD
BENT LEAD
DIM MIN MAX MIN MAX
MILLIMETERSINCHES
A0.175 0.205 4.44 5.21
B0.290 0.310 7.37 7.87
C0.125 0.165 3.18 4.19
D0.018 0.021 0.46 0.53
F0.016 0.019 0.41 0.48
G0.045 0.055 1.15 1.39
H0.095 0.105 2.42 2.66
J0.018 0.024 0.46 0.61
K0.500 --- 12.70 ---
L0.250 --- 6.35 ---
N0.080 0.105 2.04 2.66
P--- 0.100 --- 2.54
R0.135 --- 3.43 ---
F
V0.135 --- 3.43 ---
DIM MIN MAX MIN MAX
MILLIMETERSINCHES
A0.175 0.205 4.44 5.21
B0.290 0.310 7.37 7.87
C0.125 0.165 3.18 4.19
D0.018 0.021 0.46 0.53
G0.094 0.102 2.40 2.80
J0.018 0.024 0.46 0.61
K0.500 --- 12.70 ---
N0.080 0.105 2.04 2.66
P--- 0.100 --- 2.54
R0.135 --- 3.43 ---
V0.135 --- 3.43 ---
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
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DOCUMENT NUMBER:
DESCRIPTION:
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Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 2
TO−92 (TO−226) 1 WATT
© Semiconductor Components Industries, LLC, 2019 www.onsemi.com
TO−92 (TO−226) 1 WATT
CASE 29−10
ISSUE A
DATE 08 MAY 2012
STYLE 1:
PIN 1. EMITTER
2. BASE
3. COLLECTOR
STYLE 6:
PIN 1. GATE
2. SOURCE & SUBSTRATE
3. DRAIN
STYLE 11:
PIN 1. ANODE
2. CATHODE & ANODE
3. CATHODE
STYLE 16:
PIN 1. ANODE
2. GATE
3. CATHODE
STYLE 21:
PIN 1. COLLECTOR
2. EMITTER
3. BASE
STYLE 26:
PIN 1. VCC
2. GROUND 2
3. OUTPUT
STYLE 31:
PIN 1. GATE
2. DRAIN
3. SOURCE
STYLE 2:
PIN 1. BASE
2. EMITTER
3. COLLECTOR
STYLE 7:
PIN 1. SOURCE
2. DRAIN
3. GATE
STYLE 12:
PIN 1. MAIN TERMINAL 1
2. GATE
3. MAIN TERMINAL 2
STYLE 17:
PIN 1. COLLECTOR
2. BASE
3. EMITTER
STYLE 22:
PIN 1. SOURCE
2. GATE
3. DRAIN
STYLE 27:
PIN 1. MT
2. SUBSTRATE
3. MT
STYLE 32:
PIN 1. BASE
2. COLLECTOR
3. EMITTER
STYLE 3:
PIN 1. ANODE
2. ANODE
3. CATHODE
STYLE 8:
PIN 1. DRAIN
2. GATE
3. SOURCE & SUBSTRATE
STYLE 13:
PIN 1. ANODE 1
2. GATE
3. CATHODE 2
STYLE 18:
PIN 1. ANODE
2. CATHODE
3. NOT CONNECTED
STYLE 23:
PIN 1. GATE
2. SOURCE
3. DRAIN
STYLE 28:
PIN 1. CATHODE
2. ANODE
3. GATE
STYLE 33:
PIN 1. RETURN
2. INPUT
3. OUTPUT
STYLE 4:
PIN 1. CATHODE
2. CATHODE
3. ANODE
STYLE 9:
PIN 1. BASE 1
2. EMITTER
3. BASE 2
STYLE 14:
PIN 1. EMITTER
2. COLLECTOR
3. BASE
STYLE 19:
PIN 1. GATE
2. ANODE
3. CATHODE
STYLE 24:
PIN 1. EMITTER
2. COLLECTOR/ANODE
3. CATHODE
STYLE 29:
PIN 1. NOT CONNECTED
2. ANODE
3. CATHODE
STYLE 34:
PIN 1. INPUT
2. GROUND
3. LOGIC
STYLE 5:
PIN 1. DRAIN
2. SOURCE
3. GATE
STYLE 10:
PIN 1. CATHODE
2. GATE
3. ANODE
STYLE 15:
PIN 1. ANODE 1
2. CATHODE
3. ANODE 2
STYLE 20:
PIN 1. NOT CONNECTED
2. CATHODE
3. ANODE
STYLE 25:
PIN 1. MT 1
2. GATE
3. MT 2
STYLE 30:
PIN 1. DRAIN
2. GATE
3. SOURCE
STYLE 35:
PIN 1. GATE
2. COLLECTOR
3. EMITTER
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
98AON52857E
DOCUMENT NUMBER:
DESCRIPTION:
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 2 OF 2
TO−92 (TO−226) 1 WATT
© Semiconductor Components Industries, LLC, 2019 www.onsemi.com
www.onsemi.com
1
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