ADS1216
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FEATURES DESCRIPTION
APPLICATIONS
ADS1216
SBAS171D – NOVEMBER 2000 – REVISED SEPTEMBER 2006
8-Channel, 24-BitANALOG-TO-DIGITAL CONVERTER
•24 BITS, NO MISSING CODES
The ADS1216 is a precision, wide dynamic range,delta-sigma, Analog-to-Digital (A/D) converter with•0.0015% INL
24-bit resolution operating from 2.7V to 5.25V•22 BITS EFFECTIVE RESOLUTION
supplies. The delta-sigma A/D converter provides up(PGA = 1), 19 BITS (PGA = 128)
to 24 bits of no-missing-code performance and an•PGA FROM 1 TO 128
effective resolution of 22 bits.•SINGLE-CYCLE SETTLING MODE
The eight input channels are multiplexed. Internal•PROGRAMMABLE DATA OUTPUT RATES:
buffering can be selected to provide a very high inputup to 1kHz
impedance for direct connection to transducers orlow-level voltage signals. Burnout current sources•ON-CHIP 1.25V/2.5V REFERENCE
are provided that allow for the detection of an open•EXTERNAL DIFFERENTIAL REFERENCE:
or shorted sensor. An 8-bit Digital-to-Analog0.1V to 2.5V
Converter (DAC) provides an offset correction with a•ON-CHIP CALIBRATION
range of 50% of the FSR (Full-Scale Range).•SPI™-COMPATIBLE
The PGA (Programmable Gain Amplifier) providesselectable gains of 1 to 128 with an effective•2.7V TO 5.25V
resolution of 19 bits at a gain of 128. The A/D•< 1mW POWER CONSUMPTION
conversion is accomplished with a second-orderdelta-sigma modulator and programmable sinc filter.The reference input is differential and can be used•INDUSTRIAL PROCESS CONTROL
for ratiometric cancellation. The onboard current•LIQUID/GAS CHROMATOGRAPHY
DACs operate independently with the maximumcurrent set by an external resistor.•BLOOD ANALYSIS•SMART TRANSMITTERS
The serial interface is SPI-compatible. Eight bits ofdigital I/O are also provided that can be used for•PORTABLE INSTRUMENTATION
input or output. The ADS1216 is designed for•WEIGHT SCALES
high-resolution measurement applications in smart•PRESSURE TRANSDUCERS
transmitters, industrial process control, weightscales, chromatography, and portableinstrumentation.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.SPI is a trademark of Motorola.All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Copyright © 2000–2006, Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.
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ORDERING INFORMATION
ABSOLUTE MAXIMUM RATINGS
(1)
ADS1216
SBAS171D – NOVEMBER 2000 – REVISED SEPTEMBER 2006
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled withappropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may bemore susceptible to damage because very small parametric changes could cause the device not to meet its publishedspecifications.
For the most current package and ordering information see the Package Option Addendum at the end of thisdocument, or see the TI web site at www.ti.com .
ADS1216 UNIT
AV
DD
to AGND –0.3 to +6 VDV
DD
to DGND –0.3 to +6 VInput Current 100, Momentary mAInput Current 10, Continuous mAA
IN
GND – 0.5 to AV
DD
+ 0.5 VAV
DD
to DV
DD
–6 to +6 VAGND to DGND –0.3 to +0.3 VDigital Input Voltage to GND –0.3 to DV
DD
+ 0.3 VDigital Output Voltage to GND –0.3 to DV
DD
+ 0.3 VMaximum Junction Temperature +150 °COperating Temperature Range –40 to +85 °CStorage Temperature Range –60 to +100 °C
(1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods maydegrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyondthose specified is not implied.
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ELECTRICAL CHARACTERISTICS: AV
DD
= +5V
ADS1216
SBAS171D – NOVEMBER 2000 – REVISED SEPTEMBER 2006
All specifications at T
MIN
to T
MAX
, AV
DD
= +5V, DV
DD
= +2.7V to +5.25V, f
MOD
= 19.2kHz, PGA = 1, Buffer ON, R
DAC
= 150k Ω,f
DATA
= 10Hz, and V
REF
= +2.5V, unless otherwise specified.
ADS1216
PARAMETER CONDITIONS MIN TYP MAX UNIT
ANALOG INPUT (A
IN
0–A
IN
7, A
INCOM
)
Analog input range Buffer OFF AGND – 0.1 AV
DD
+ 0.1 V
Buffer ON AGND + 0.05 AV
DD
– 1.5 V
Full-scale input voltage range (In+) – (In–); see Functional Block ±V
REF
/PGA VDiagram
Differential input impedance Buffer OFF 5/PGA M Ω
Input current Buffer ON 0.5 nA
Bandwidth
Fast-settling filter –3dB 0.469 ×f
DATA
Hz
–3dB 0.318 ×f
DATA
HzSinc
2
filter
–3dB 0.262 ×f
DATA
HzSinc
3
filter
Programmable gain amplifier User-selectable gain ranges 1 128
Input capacitance 9 pF
Input leakage current Modulator OFF, T
A
= +25 °C 5 pA
Burnout current sources 2 µA
OFFSET DAC
Offset DAC range ±V
REF
/(2 ×PGA) V
Offset DAC monotonicity 8 Bits
Offset DAC gain error ±10 %
Offset DAC gain error drift 1 ppm/ °C
SYSTEM PERFORMANCE
Resolution 24 Bits
No missing codes 24 BitsSinc
3
filter
Integral nonlinearity End-point fit ±0.0015 % of FS
Offset error
(1)
7.5 ppm of FS
Offset drift
(1)
0.02 ppm of FS/ °C
Gain error
(1)
0.005 %
Gain error drift
(1)
0.5 ppm/ °C
Common-mode rejection At DC 100 dB
f
CM
= 60Hz, f
DATA
= 10Hz 130 dB
f
CM
= 50Hz, f
DATA
= 50Hz 120 dB
f
CM
= 60Hz, f
DATA
= 60Hz 120 dB
Normal-mode rejection f
SIG
= 50Hz, f
DATA
= 50Hz 100 dB
f
SIG
= 60Hz, f
DATA
= 60Hz 100 dB
Output noise See Typical Characteristics
Power-supply rejection At DC, dB = –20 log( ∆V
OUT
/∆V
DD
)
(2)
80 95 dB
VOLTAGE REFERENCE INPUT
Reference input range REF IN+, REF IN– AGND AV
DD
V
V
REF
V
REF
≡(REF IN+) – (REF IN–) 0.1 2.5 2.6 V
Common-mode rejection at DC 120 dB
Common-mode rejection f
VREFCM
= 60Hz, f
DATA
= 60Hz 120 dB
Bias current
(3)
V
REF
= 2.5V 1.3 µA
(1) Calibration can minimize these errors.(2) ∆V
OUT
is change in digital result.(3) 12pF switched capacitor at f
SAMP
clock frequency.
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ADS1216
SBAS171D – NOVEMBER 2000 – REVISED SEPTEMBER 2006
ELECTRICAL CHARACTERISTICS: AV
DD
= +5V (continued)All specifications at T
MIN
to T
MAX
, AV
DD
= +5V, DV
DD
= +2.7V to +5.25V, f
MOD
= 19.2kHz, PGA = 1, Buffer ON, R
DAC
= 150k Ω,f
DATA
= 10Hz, and V
REF
= +2.5V, unless otherwise specified.
ADS1216
PARAMETER CONDITIONS MIN TYP MAX UNIT
ON-CHIP VOLTAGE REFERENCE
Output voltage REF HI = 1 2.4 2.5 2.6 V
REF HI = 0 1.25 V
Short-circuit current source 8 mA
Short-circuit current sink 50 µA
Short-circuit duration Sink or source Indefinite
Drift 15 ppm/ °C
Noise V
RCAP
= 0.1 µF, BW = 0.1Hz to 100Hz 10 µV
PP
Output impedance Sourcing 100 µA 3 Ω
Startup time 50 µs
IDAC
Full-scale output current R
DAC
= 150k Ω, range = 1 0.5 mA
R
DAC
= 150k Ω, range = 2 1 mA
R
DAC
= 150k Ω, range = 3 2 mA
R
DAC
= 15k Ω, range = 3 20 mA
Maximum short-circuit current duration R
DAC
= 10k ΩIndefinite
R
DAC
= 0k Ω10 Minute
Monotonicity R
DAC
= 150k Ω8 Bits
Compliance voltage 0 AV
DD
– 1 V
Output impedance See Typical Characteristics
Power-supply rejection ratio V
OUT
= AV
DD
/2 400 ppm/V
Absolute error Individual IDAC 5 %
Absolute drift Individual IDAC 75 ppm/ °C
Mismatch error Between IDACs, same range and code 0.25 %
Mismatch drift Between IDACs, same range and code 15 ppm/ °C
POWER-SUPPLY REQUIREMENTS
Power-supply voltage AV
DD
4.75 5.25 V
Analog current (I
ADC
+ I
VREF
+ IDAC) PDWN = 0 or SLEEP 1 nA
ADC current (I
ADC
) PGA = 1, buffer OFF 140 225 µA
PGA = 128, buffer OFF 430 650 µA
PGA = 1, buffer ON 180 275 µA
PGA = 128, buffer ON 800 1250 µA
V
REF
current (I
VREF
) 250 375 µA
IDAC current (IDAC) Excludes load current 480 675 µA
Digital current Normal mode, DV
DD
= 5V 180 275 µA
SLEEP mode, DV
DD
= 5V 150 µA
Read data continuous mode, DV
DD
= 5V 230 µA
PDWN 1 nA
PGA = 1, buffer OFF, REFEN = 0,Power dissipation 1.6 2.5 mWIDACS OFF, DV
DD
= 5V
TEMPERATURE RANGE
Operating –40 +85 °C
Storage –60 +100 °C
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ELECTRICAL CHARACTERISTICS: AV
DD
= +3V
ADS1216
SBAS171D – NOVEMBER 2000 – REVISED SEPTEMBER 2006
All specifications at T
MIN
to T
MAX
, AV
DD
= +3V, DV
DD
= +2.7V to +5.25V, f
MOD
= 19.2kHz, PGA = 1, Buffer ON, R
DAC
= 75k Ω,f
DATA
= 10Hz, and V
REF
= +1.25V, unless otherwise specified.
ADS1216
PARAMETER CONDITIONS MIN TYP MAX UNIT
ANALOG INPUT (A
IN
0–A
IN
7, A
INCOM
)
Analog input range Buffer OFF AGND – 0.1 AV
DD
+ 0.1 V
Buffer ON AGND + 0.05 AV
DD
– 1.5 V
Full-scale input voltage range (In+) – (In–); see Functional Block ±V
REF
/PGA VDiagram
Input impedance Buffer OFF 5/PGA M Ω
Input current Buffer ON 0.5 nA
Bandwidth
Fast-settling filter –3dB 0.469 ×f
DATA
Hz
–3dB 0.318 ×f
DATA
HzSinc
2
filter
–3dB 0.262 ×f
DATA
HzSinc
3
filter
Programmable gain amplifier User-selectable gain ranges 1 128
Input capacitance 9 pF
Input leakage current Modulator OFF, T
A
= +25 °C 5 pA
Burnout current sources 2 µA
OFFSET DAC
Offset DAC range ±V
REF
/(2 ×PGA) V
Offset DAC monotonicity 8 Bits
Offset DAC gain error ±10 %
Offset DAC gain error drift 2 ppm/ °C
SYSTEM PERFORMANCE
Resolution 24 Bits
No missing codes 24 BitsSinc
3
filter
Integral nonlinearity End-point fit ±0.0015 % of FS
Offset error
(1)
15 ppm of FS
Offset drift
(1)
0.04 ppm of FS/ °C
Gain error
(1)
0.010 %
Gain error drift
(1)
1.0 ppm/ °C
Common-mode rejection At DC 100 dB
f
CM
= 60Hz, f
DATA
= 10Hz 130 dB
f
CM
= 50Hz, f
DATA
= 50Hz 120 dB
f
CM
= 60Hz, f
DATA
= 60Hz 120 dB
Normal-mode rejection f
SIG
= 50Hz, f
DATA
= 50Hz 100 dB
f
SIG
= 60Hz, f
DATA
= 60Hz 100 dB
Output noise See Typical Characteristics
Power-supply rejection At DC, dB = –20 log( ∆V
OUT
/∆V
DD
)
(2)
75 90 dB
VOLTAGE REFERENCE INPUT
Reference input range REF IN+, REF IN– 0 AV
DD
V
V
REF
V
REF
≡(REF IN+) – (REF IN–) 0.1 1.25 1.3 V
Common-mode rejection at DC 120 dB
Common-mode rejection f
VREFCM
= 60Hz, f
DATA
= 60Hz 120 dB
Bias current
(3)
V
REF
= 1.25V 0.65 µA
(1) Calibration can minimize these errors.(2) ∆V
OUT
is change in digital result.(3) 12pF switched capacitor at f
SAMP
clock frequency.
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ADS1216
SBAS171D – NOVEMBER 2000 – REVISED SEPTEMBER 2006
ELECTRICAL CHARACTERISTICS: AV
DD
= +3V (continued)All specifications at T
MIN
to T
MAX
, AV
DD
= +3V, DV
DD
= +2.7V to +5.25V, f
MOD
= 19.2kHz, PGA = 1, Buffer ON, R
DAC
= 75k Ω,f
DATA
= 10Hz, and V
REF
= +1.25V, unless otherwise specified.
ADS1216
PARAMETER CONDITIONS MIN TYP MAX UNIT
ON-CHIP VOLTAGE REFERENCE
Output voltage REF HI = 0 1.2 1.25 1.3 V
Short-circuit current source 3 mA
Short-circuit current sink 50 µA
Short-circuit duration Sink or source Indefinite
Drift 15 ppm/ °C
Noise V
RCAP
= 0.1 µF, BW = 0.1Hz to 100Hz 10 µV
PP
Output impedance Sourcing 100 µA 3 Ω
Startup time 50 µs
IDAC
Full-scale output current R
DAC
= 75k Ω, range = 1 0.5 mA
R
DAC
= 75k Ω, range = 2 1 mA
R
DAC
= 75k Ω, range = 3 2 mA
R
DAC
= 15k Ω, range = 3 20 mA
Maximum short-circuit current duration R
DAC
= 10k ΩIndefinite
R
DAC
= 0k Ω10 Minute
Monotonicity R
DAC
= 75k Ω8 Bits
Compliance voltage 0 AV
DD
– 1 V
Output impedance See Typical Characteristics
Power-supply rejection ratio V
OUT
= AV
DD
/2 600 ppm/V
Absolute error Individual IDAC 5 %
Absolute drift Individual IDAC 75 ppm/ °C
Mismatch error Between IDACs, same range and code 0.25 %
Mismatch drift Between IDACs, same range and code 15 ppm/ °C
POWER-SUPPLY REQUIREMENTS
Power-supply voltage AV
DD
2.7 3.3 V
Analog current (I
ADC
+ I
VREF
+ IDAC) PDWN = 0 or SLEEP 1 nA
ADC current (I
ADC
) PGA = 1, buffer OFF 120 200 µA
PGA = 128, buffer OFF 370 600 µA
PGA = 1, buffer ON 170 250 µA
PGA = 128, buffer ON 750 1200 µA
V
REF
current (I
VREF
) 250 375 µA
IDAC current (IDAC) Excludes load current 480 675 µA
Digital current Normal mode, DV
DD
= 3V 90 200 µA
SLEEP mode, DV
DD
= 3V 75 µA
Read data continuous mode, DV
DD
= 3V 113 µA
PDWN = 0 1 nA
PGA = 1, buffer OFF, REFEN = 0,Power dissipation 0.6 1.2 mWIDACS OFF, DV
DD
= 3V
TEMPERATURE RANGE
Operating –40 +85 °C
Storage –60 +100 °C
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DIGITAL CHARACTERISTICS: T
MIN
to T
MAX
, DV
DD
+2.7V to +5.25V
FUNCTIONAL BLOCK DIAGRAM
BUF PGA
A=1:128
+
1.25Vor
2.5V
Reference
ClockGenerator
Registers
SerialInterface
2nd-Order
Modulator
RAM
DigitalI/O
Interface
AGND AVDD
IN+
IN-
RDAC VREFOUT VRCAP VREF+ VREF- XIN XOUT
DSYNCPDWN RESET DRDYD7BUFENDGNDDVDD ...D0
SCLK
POL
DIN
DOUT
CS
MUX
A 0
IN
A 1
IN
A 2
IN
A 3
IN
A 4
IN
A 5
IN
A 6
IN
A 7
IN
AINCOM
IDAC1
Controller
Programmable
Digital
Filter
8-Bit
IDAC
IDAC2 8-Bit
IDAC
Offset
DAC
AVDD
AGND
2 Am
2 Am
ADS1216
SBAS171D – NOVEMBER 2000 – REVISED SEPTEMBER 2006
ADS1216
PARAMETER CONDITIONS MIN TYP MAX UNIT
Digital input/output
Logic family CMOS
Logic level: V
IH
0.8 ×DV
DD
DV
DD
V
Logic level: V
IL
DGND 0.2 ×DV
DD
V
Logic level: V
OH
I
OH
= 1mA DV
DD
– 0.4 V
Logic level: V
OL
I
OL
= 1mA DGND DGND + 0.4 V
Input leakage: I
IH
V
I
= DV
DD
10 µA
Input leakage: I
IL
V
I
= 0 –10 µA
Master clock rate: f
OSC
1 5 MHz
Master clock period: t
OSC
1/f
OSC
200 1000 ns
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TIMING CHARACTERISTICS
t4
MSB
(CommandorCommandandData)
LSB
t5
t1
t3
CS
SCLK
(POL=0)
DIN
DOUT
NOTE:(1)BitOrder=0.
t7
MSB(1) LSB(1)
t8
t10
t2
t2t11
t6
t9
SCLK
(POL=1)
ADS1216
SBAS171D – NOVEMBER 2000 – REVISED SEPTEMBER 2006
SPEC DESCRIPTION MIN MAX UNITS
SCLK period 4 t
OSC
periodst
1
3 DRDY periodst
2
SCLK pulse width, HIGH and LOW 200 nst
3
CS LOW to first SCLK edge; setup time 0 nst
4
D
IN
valid to SCLK edge; setup time 50 nst
5
Valid D
IN
to SCLK edge; hold time 50 nsDelay between last SCLK edge for D
IN
and first SCLK edge for D
OUT
:RDATA, RDATAC, RREG, WREG, RRAM, WRAM 50 t
OSC
periodst
6
CSREG, CSRAMX, CSRAM 200 t
OSC
periodsCSARAM, CSARAMX 1100 t
OSC
periodst
7
SCLK edge to valid new D
OUT
50 nst
8
SCLK edge to D
OUT
, hold time 0 nsLast SCLK edge to D
OUT
tri-statet
9
6 10 t
OSC
periodsNOTE: D
OUT
goes tri-state immediately when CS goes HIGH.t
10
CS LOW time after final SCLK edge 16 t
OSC
periodsFinal SCLK edge of one op code until first edge SCLK of next command:RREG, WREG, RRAM, WRAM, CSRAMX, CSARAMX, CSRAM,
4 t
OSC
periodsCSARAM, CSREG, SLEEP, RDATA, RDATAC, STOPCCREG, CRAM 220 t
OSC
periodst
11
CREGA 1600 t
OSC
periodsSELFGCAL, SELFOCAL, SYSOCAL, SYSGCAL 7 DRDY periodsSELFCAL 14 DRDY periodsRESET (Command, SCLK or Pin), DSYNC 16 t
OSC
periods
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SCLKResetWaveform
t12 t14 t15
t13 t13
SCLK
t17A
DRDY
t16
RESETDSYNCPDWN, ,
ADS1216
ResetsOn
FallingEdge
t17B
DEVICE INFORMATION
24
23
22
21
20
19
18
17
16
15
14
13
RESET
BUFEN
DGND
DGND
DGND
DGND
DGND
RDAC
IDAC2
IDAC1
VRCAP
AVDD
DOUT
AVDD
DIN
AGND
SCLK
A 0
IN
CS
A 1
IN
DRDY
A 2
IN
DVDD
A3
IN
DGND
A4
IN
DSYNC
A 5
IN
POL
A 6
IN
PDWN
A 7
IN
XOUT
AINCOM
XIN
AGND
37
38
39
40
41
42
43
44
45
46
47
48
D0
D1
D2
D3
D4
D5
D6
D7
AGND
VREFOUT
VREF+
VREF-
36 35 34 33 32 31 30 29 28 27 26
1 2 3 4 5 6 7 8 9 10 11
25
12
ADS1216
ADS1216
SBAS171D – NOVEMBER 2000 – REVISED SEPTEMBER 2006
SPEC DESCRIPTION MIN MAX UNITS
t
12
300 500 t
OSC
periodst
13
5 t
OSC
periodst
14
550 750 t
OSC
periodst
15
1050 1250 t
OSC
periodst
16
Pulse width 4 t
OSC
periodst
17A
DOR data not valid during this update period 4 t
OSC
periodst
17B
DOR data not valid during this update period 12 t
OSC
periods
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ADS1216
SBAS171D – NOVEMBER 2000 – REVISED SEPTEMBER 2006
DEVICE INFORMATION (continued)TERMINAL FUNCTIONS
PIN NUMBER NAME DESCRIPTION
1, 13 AV
DD
Analog power supply2, 12, 45 AGND Analog ground3–10 A
IN
0–7 Analog input 0–711 A
INCOM
Analog input common14 V
RCAP
V
REF
bypass capcitor15 IDAC1 Current DAC1 output16 IDAC2 Current DAC2 output17 RDAC Current DAC resistor18–22, 30 DGND Digital ground23 BUFEN Buffer enable24 RESET Active LOW; resets the entire chip.25 X
IN
Clock input26 X
OUT
Clock output, used with crystal or resonator.27 PDWN Active LOW; power down. The power-down function shuts down the analog and digital circuits.28 POL Serial clock polarity29 DSYNC Active LOW; synchronization control31 DV
DD
Digital power supply32 DRDY Active LOW; data ready33 CS Active LOW; chip select34 SCLK Serial clock, Schmitt trigger35 D
IN
Serial data input, Schmitt trigger36 D
OUT
Serial data output37–44 D0–D7 Digital I/O 0–746 V
REFOUT
Voltage reference output47 V
REF+
Positive differential reference input48 V
REF–
Negative differential reference input
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TYPICAL CHARACTERISTICS
22
21
20
19
18
17
16
15
14
13
12
DecimationRatio=f /f
MOD DATA
0 500 1000 1500 2000
PGA4
ENOB(rms)
PGA1 PGA2
PGA16
PGA8
PGA32 PGA64 PGA128
Sinc Filter
3
22
21
20
19
18
17
16
15
14
13
12
0 500 1000 1500 2000
ENOB(rms)
PGA4 PGA8
PGA1
PGA2
PGA16
PGA32 PGA64 PGA128
DecimationRatio=f /f
MOD DATA
Sinc Filter,BufferON
3
22
21
20
19
18
17
16
15
14
13
12
DecimationRatio
0 500 1000 1500 2000
ENOB(rms)
PGA4 PGA8
PGA1
PGA2
PGA16 PGA32 PGA64 PGA128
Sinc Filter,VREF =1.25,BUFFERON
3
22
21
20
19
18
17
16
15
14
13
12
0 500 1000 1500 2000
ENOB(rms)
PGA4 PGA8
PGA1 PGA2
PGA16 PGA32 PGA64 PGA128
DecimationRatio=f /f
MOD DATA
Sinc Filter,VREF =1.25V,BUFFEROFF
3
22
21
20
19
18
17
16
15
14
13
12
0 500 1000 1500 2000
ENOB(rms)
PGA4 PGA8
PGA1
PGA2
PGA32 PGA128
PGA16 PGA64
DecimationRatio=f /f
MOD DATA
Sinc Filter
2
22
21
20
19
18
17
16
15
14
13
12
0 500 1000 1500 2000
ENOB(rms)
DecimationRatio=f /f
MOD DATA
Fast-SettlingFilter
ADS1216
SBAS171D – NOVEMBER 2000 – REVISED SEPTEMBER 2006
At AV
DD
= +5V, DV
DD
= +5V, f
OSC
= 2.4576MHz, PGA = 1, R
DAC
= 150k Ω, f
DATA
= 10Hz, and V
REF
= +2.5V, unless otherwise specified.
EFFECTIVE NUMBER OF BITS EFFECTIVE NUMBER OF BITSvs DECIMATION RATIO vs DECIMATION RATIO
Figure 1. Figure 2.
EFFECTIVE NUMBER OF BITS EFFECTIVE NUMBER OF BITSvs DECIMATION RATIO vs DECIMATION RATIO
Figure 3. Figure 4.
EFFECTIVE NUMBER OF BITS FAST-SETTLING FILTERvs DECIMATION RATIO EFFECTIVE NUMBER OF BITS vs DECIMATION RATIO
Figure 5. Figure 6.
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0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
V (V)
IN
-2.5 -1.5 0.5-0.5 1.5 2.5
Noise(rms,ppmofFS)
50
0
-50
-100
-150
-200
Offset(ppmofFS)
PGA1
PGA128
PGA64
Temperature( C)°
-50 -30 10-10 30 50 70 90
PGA16
1.00010
1.00006
1.00002
0.99998
0.99994
0.99990
0.99986
Temperature(°C)
-50 -30 10-10 30 50 70 90
Gain(Normalized)
ADS1216
SBAS171D – NOVEMBER 2000 – REVISED SEPTEMBER 2006
TYPICAL CHARACTERISTICS (continued)At AV
DD
= +5V, DV
DD
= +5V, f
OSC
= 2.4576MHz, PGA = 1, R
DAC
= 150k Ω, f
DATA
= 10Hz, and V
REF
= +2.5V, unless otherwise specified.
NOISE vs INPUT SIGNAL CMRR vs FREQUENCY
Figure 7. Figure 8.
PSRR vs FREQUENCY OFFSET vs TEMPERATURE
Figure 9. Figure 10.
GAIN vs TEMPERATURE INTEGRAL NONLINEARITY vs INPUT SIGNAL
Figure 11. Figure 12.
12
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250
200
150
100
50
0
Current( A)m
IDIGITAL
IANALOG
Temperature( C)°
-50 -30 10-10 30 50 70 90
4500
4000
3500
3000
2500
2000
1500
1000
500
0
ppmofFS
-2.0
NumberofOccurrences
-1.5 -1.0 -0.5 0 0.5 1.0 1.5 2.0
200
170
140
110
80
50
20
-10
-40
-70
-100
Offset(ppmofFSR)
Temperature( C)°
-50 -30 10-10 30 50 70 90
2.55
2.50
2.45
V CurrentLoad(mA)
REFOUT
-0.5 0 0.5 1.0 1.5 2.0 2.5
V (V)
REFOUT
ADS1216
SBAS171D – NOVEMBER 2000 – REVISED SEPTEMBER 2006
TYPICAL CHARACTERISTICS (continued)At AV
DD
= +5V, DV
DD
= +5V, f
OSC
= 2.4576MHz, PGA = 1, R
DAC
= 150k Ω, f
DATA
= 10Hz, and V
REF
= +2.5V, unless otherwise specified.
CURRENT vs TEMPERATURE ADC CURRENT vs PGA
Figure 13. Figure 14.
DIGITAL CURRENT HISTOGRAM OF OUTPUT DATA
Figure 15. Figure 16.
V
REFOUT
vs LOAD CURRENT OFFSET DAC – OFFSET vs TEMPERATURE
Figure 17. Figure 18.
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1.00020
1.00016
1.00012
1.00008
1.00004
1.00000
0.99996
0.99992
0.99988
0.99984
0.99980
0.99976
NormalizedGain
Temperature( C)°
-50 -30 10-10 30 50 70 90
1.000
1.000
0.999
0.999
0.998
V V-
DD OUT (V)
0 1 2 3 4 5
I (Normalized)
OUT
+85 C°
- °40 C
+25 C°
1.010
1.005
1.000
0.995
0.990
0.985
I(Normalized)
OUT
Temperature(°C)
-50 -30 10-10 30 50 70 90
3000
2000
1000
0
-1000
-2000
-3000
-4000
-5000
-6000
IDACMatch(ppm)
Temperature( C)°
-50 -30 10-10 30 50 70 90
0.5
0.4
0.3
0.2
0.1
0
-0.1
-0.2
-0.3
-0.4
-0.5
IDACCode
0 25532 64 96 128 160 192 224
DNL(LSB)
0.5
0.4
0.3
0.2
0.1
0
-0.1
-0.2
-0.3
-0.4
-0.5
IDACCode
0 25532 64 96 128 160 192 224
INL(LSB)
ADS1216
SBAS171D – NOVEMBER 2000 – REVISED SEPTEMBER 2006
TYPICAL CHARACTERISTICS (continued)At AV
DD
= +5V, DV
DD
= +5V, f
OSC
= 2.4576MHz, PGA = 1, R
DAC
= 150k Ω, f
DATA
= 10Hz, and V
REF
= +2.5V, unless otherwise specified.
OFFSET DAC – GAIN vs TEMPERATURE IDAC R
OUT
vs V
OUT
Figure 19. Figure 20.
IDAC NORMALIZED vs TEMPERATURE IDAC MATCHING vs TEMPERATURE
Figure 21. Figure 22.
IDAC DIFFERENTIAL NONLINEARITY IDAC INTEGRAL NONLINEARITY(Range = 1, R
DAC
= 150k Ω, V
REF
= 2.5V) (Range = 1, R
DAC
= 150k Ω, V
REF
= 2.5V)
Figure 23. Figure 24.
14
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OVERVIEW
INPUT MULTIPLEXER
BURNOUT CURRENT SOURCES
INPUT BUFFER
IDAC1 AND IDAC2
A 3
IN
A 4
IN
A 5
IN
A 6
IN
A 0
IN
A 1
IN
A 2
IN
A 7
IN
AINCOM
BurnoutCurrent
SourceOn
BurnoutCurrent
SourceOn
IDAC1
AGND
AVDD
TEMPERATURE SENSOR
ADS1216
SBAS171D – NOVEMBER 2000 – REVISED SEPTEMBER 2006
of the diode is connected to the negative input of theA/D converter. The output of IDAC1 is connected tothe anode to bias the diode and the cathode of theThe input multiplexer provides for any combination of
diode is also connected to ground to complete thedifferential inputs to be selected on any of the input
circuit.channels, as shown in Figure 25 . If channel 1 is
In this mode, the output of IDAC1 is also connectedselected as the positive differential input channel,
to the output pin, so some current may flow into anany other channel can be selected as the negative
external load from IDAC1, rather than the diode. Seedifferential input channel. With this method, it is
Application Report Measuring Temperature with thepossible to have up to eight fully-differential input
ADS1216, ADS1217, or ADS1216 (SBAA073 ),channels.
available for download at www.ti.com , for moreIn addition, current sources are supplied that will
information.source or sink current to detect open or short circuitson the pins.
When the Burnout bit is set in the ACR ConfigurationRegister (see the Register Map section), two currentsources are enabled. The current source on thepositive input channel sources approximately 2 µA ofcurrent. The current source on the negative inputchannel sinks approximately 2 µA. This sinking allowsfor the detection of an open circuit (full-scalereading) or short circuit (0V differential reading) onthe selected input differential pair.
The input impedance of the ADS1216 without thebuffer is 5M Ω/PGA. With the buffer enabled, theinput voltage range is reduced and the analogpower-supply current is higher. The buffer iscontrolled by ANDing the state of the buffer pin withthe state of the BUFFER bit in the ACR Register(see the Register Map section). See ApplicationReport Input Currents for High-Resolution ADCs(SBAA080 ), available for download at www.ti.com ,for more information.
The ADS1216 has two 8-bit current output DACs thatcan be controlled independently. The output currentis set with R
DAC
, the range select bits in the ACRregister, and the 8-bit digital value in the IDACregister. The output current equals V
REF
/(8 ×R
DAC
)(2
RANGE – 1
)(DAC CODE). With V
REFOUT
= 2.5Vand R
DAC
= 150k Ω, the full-scale output can beFigure 25. Input Multiplexer Configuration
selected to be 0.5, 1, or 2mA. The compliancevoltage range is 0 to within 1V of AV
DD
. When theinternal voltage reference of the ADS1216 is used, itis the reference for the IDAC. An external referenceAn on-chip diode provides temperature sensing
may be used for the IDACs by disabling the internalcapability. When the configuration register for the
reference and tying the external reference input toinput MUX is set to all 1s, the diode is connected to
the V
REFOUT
pin.the input of the A/D converter. All other channels areopen. The anode of the diode is connected to thepositive input of the A/D converter, and the cathode
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PROGRAMMABLE GAIN AMPLIFIER (PGA) ON-CHIP VOLTAGE REFERENCE
PGA OFFSET DAC
V
RCAP
PIN
CLOCK GENERATORMODULATOR
C1
Crystal
XIN
XOUT
C2
VOLTAGE REFERENCE INPUT
ADS1216
SBAS171D – NOVEMBER 2000 – REVISED SEPTEMBER 2006
The PGA can be set to gains of 1, 2, 4, 8, 16, 32, 64, A selectable voltage reference (1.25V or 2.5V) isor 128. Using the PGA can improve the effective available for supplying the voltage reference input.resolution of the A/D converter. For instance, with a To use, connect V
REF–
to AGND and V
REF+
toPGA of 1 on a 5V full-scale range, the A/D converter V
REFOUT
. The enabling and voltage selection arecan resolve to 1 µV. With a PGA of 128 on a 40mV controlled through bits REF EN and REF HI in thefull-scale range, the A/D converter can resolve to Setup Register (see the Register Map section). The75nV. 2.5V reference requires AV
DD
= +5V. When using theon-chip voltage reference, the V
REFOUT
pin should bebypassed with a 0.1 µF capacitor to AGND.
The input to the PGA can be shifted by half thefull-scale input range of the PGA by using the ODAC(Offset DAC) Register; see the Register Map section. This pin provides a bypass cap for noise filtering onThe ODAC register is an 8-bit value; the MSB is the internal V
REF
circuitry only. This pin is a sensitive pin;sign and the seven LSBs provide the magnitude of therefore place the capacitor as close as possiblethe offset. Using the ODAC does not reduce the and avoid any resistive loading. The recommendedperformance of the A/D converter. See Application capacitor is a 1000pF ceramic cap. If an externalReport The Offset DAC (SBAA077 ), available for V
REF
is used, this pin can be left unconnected.download at www.ti.com , for more information.
The clock source for the ADS1216 can be providedThe modulator is a single-loop, second-order system. from a crystal, oscillator, or external clock. When theThe modulator runs at a clock speed (f
MOD
) that is clock source is a crystal, external capacitors must bederived from the external clock (f
OSC
), as shown in provided to ensure startup and a stable clockTable 1 . The frequency division is determined by the frequency; this configuration is shown in Figure 26SPEED bit in the Setup Register (see the Register and Table 2 .Map section).
Table 1. Modulator Speed
SPEED BIT f
MOD
0 f
OSC
/1281 f
OSC
/256
Figure 26. Crystal Connection
The ADS1216 uses a differential voltage reference
Table 2. Typical Clock Sourcesinput. The input signal is measured against thedifferential voltage V
REF
≡(V
REF+
) – (V
REF–
). For AV
DD
CLOCK= +5V, V
REF
is typically +2.5V. For AV
DD
= +3V, V
REF
SOURCE FREQUENCY C
1
C
2
PART NUMBERis typically +1.25V. As a result of the sampling nature
Crystal 2.4576 0–20pF 0–20pF ECS, ECSD 2.45 – 32of the modulator, the reference input current
Crystal 4.9152 0–20pF 0–20pF ECS, ECSL 4.91increases with higher modulator clock frequency
Crystal 4.9152 0–20pF 0–20pF ECS, ECSD 4.91(f
MOD
) and higher PGA settings.
Crystal 4.9152 0–20pF 0–20pF CTS, MP 042 4M9182
16
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CALIBRATION
DIGITAL FILTER
AdjustableDigitalFilter
DataOut
Modulator
Output
Fast-Settling
Sinc2
Sinc3
FILTERSETTLINGTIME
NOTE:(1)WithSynchronizedChannelChanges.
FILTER
SETTLINGTIME
(ConversionCycles)
Sinc3
Sinc2
Fast
3(1)
2(1)
1(1)
AUTOMODEFILTERSELECTION
1 2 3 4
CONVERSIONCYCLE
Discard Sinc2Sinc3
Fast
ADS1216
SBAS171D – NOVEMBER 2000 – REVISED SEPTEMBER 2006
At the completion of calibration, the DRDY signalgoes low, which indicates the calibration is finishedThe offset and gain errors in the ADS1216, or the
and valid data is available. See Application Reportcomplete system, can be reduced with calibration.
Calibration Routine and Register Value GenerationInternal calibration of the ADS1216 is called
for the ADS121x Series (SBAA099 ), available forself-calibration. Self-calibration is handled with three
download at www.ti.com , for more information.commands. One command does both offset and gaincalibration. There is also a gain calibration commandand an offset calibration command. Each calibrationprocess takes seven t
DATA
periods to complete. It
The Digital Filter can use either the Fast-Settling,takes 14 t
DATA
periods to complete both an offset and
Sinc
2
, or Sinc
3
filter, as shown in Figure 27 . Ingain calibration. Self-gain calibration is optimized for
addition, the Auto mode changes the sinc filter afterPGA gains less than 8. When using higher gains,
the input channel or PGA is changed. Whensystem gain calibration is recommended.
switching to a new channel, it will use theFast-Settling filter for the next two conversions, theFor system calibration, the appropriate signal must
first of which should be discarded. It will then use thebe applied to the inputs. The system offset command
Sinc
2
followed by the Sinc
3
filter. This architecturerequires a zero differential input signal. It then
combines the low-noise advantage of the Sinc
3
filtercomputes an offset that will nullify offset in the
with the quick response of the Fast-Settling timesystem. The system gain command requires a
filter. See Figure 28 for the frequency response ofpositive full-scale differential input signal. It then
each filter.computes a value to nullify gain errors in the system.Each of these calibrations will take seven t
DATA
When using the Fast-Settling filter, select aperiods to complete.
decimation value set by the DEC0 and M/DEC1registers that is evenly divisible by four for the bestCalibration must be performed after power on, a
gain accuracy. For example, choose 260 rather thanchange in decimation ratio, or a change of the PGA.
261.For operation with a reference voltage greater than(AV
DD
– 1.5V), the buffer must also be turned offduring calibration.
Figure 27. Filter Step Responses
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SINC FILTERRESPONSE
3 (1)
( 3dB=0.262 f- ´ DATA =15.76Hz)
Frequency(Hz)
0
-20
-40
-60
-80
-100
-120
0 30 12060 90 150 180 210 240 270 300
Gain(dB)
SINC FILTERRESPONSE
2 (1)
( 3dB=0.318 f- ´ DATA =19.11Hz)
Frequency(Hz)
0
-20
-40
-60
-80
-100
-120
0 30 12060 90 150 180 210 240 270 300
Gain(dB)
FASTSETTLINGFILTERRESPONSE(1)
( 3dB=0.469 f- ´ DATA =28.125Hz)
Frequency(Hz)
0
-20
-40
-60
-80
-100
-120
0
NOTE:(1)f =60Hz.
DATA
30 12060 90 150 180 210 240 270 300
Gain(dB)
Chip Select ( CS)DIGITAL I/O INTERFACE
Serial Clock (SCLK)
SERIAL PERIPHERAL INTERFACE (SPI)
ADS1216
SBAS171D – NOVEMBER 2000 – REVISED SEPTEMBER 2006
Figure 28. Filter Frequency Responses
The chip select ( CS) input of the ADS1216 must beThe ADS1216 has eight pins dedicated for digital
externally asserted before a master device canI/O. The default power-up condition for the digital I/O
exchange data with the ADS1216. CS must be lowpins are as inputs. All of the digital I/O pins are
for the duration of the transaction. CS can be tiedindividually configurable as inputs or outputs. They
low.are configured through the DIR control register. TheDIR register defines whether the pin is an input oroutput, and the DIO register defines the state of thedigital output. When the digital I/O are configured as
SCLK, a Schmitt-Trigger input, clocks data transferinputs, DIO is used to read the state of the pin. If the
on the D
IN
input and D
OUT
output. When transferringdigital I/O are not used, either 1) configure as
data to or from the ADS1216, multiple bits of dataoutputs; or 2) leave as inputs and tie to ground; this
may be transferred back-to-back with no delay inconfiguration prevents excess power dissipation.
SCLKs or toggling of CS. Make sure to avoid glitcheson SCLK because they can cause extra shifting ofthe data.The SPI allows a controller to communicatesynchronously with the ADS1216. The ADS1216operates in slave-only mode.
18
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Polarity (POL)
DATA READY
DSYNC OPERATION
MEMORY
Configuration
Registers
16bytes
SETUP
MUX
ACR
IDAC1
IDAC2
ODAC
DIO
DIR
DEC0
M/DEC1
OCR0
OCR1
OCR2
FSR0
FSR1
FSR2
RAM
128Bytes
Bank2
16bytes
Bank7
16bytes
Bank0
16bytes
REGISTER BANK
ADS1216
SBAS171D – NOVEMBER 2000 – REVISED SEPTEMBER 2006
The serial clock polarity is specified by the POLinput. When SCLK is active high, set POL high.When SCLK is active low, set POL low.
The DRDY output is used as a status signal toindicate when data is ready to be read from theADS1216. DRDY goes low when new data isavailable. It is reset high when a read operation fromthe data register is complete. It also goes high priorto the updating of the output register to indicatewhen not to read from the device to ensure that adata read is not attempted while the register is beingupdated.
DSYNC is used to provide for synchronization of theA/D conversion with an external event.Synchronization can be achieved either through theDSYNC pin or the DSYNC command. When theDSYNC pin is used, the filter counter is reset on thefalling edge of DSYNC. The modulator is held inreset until DSYNC is taken high. Synchronizationoccurs on the next rising edge of the system clockafter DSYNC is taken high.
Two types of memory are used on the ADS1216:registers and RAM. 16 registers directly control thevarious functions (PGA, DAC value, DecimationRatio, etc.) and can be directly read or written to.Collectively, the registers contain all the informationneeded to configure the part, such as data format,mux settings, calibration settings, decimation ratio,etc. Additional registers, such as conversion data,
Figure 29. Memory Organizationare accessed through dedicated instructions.
The operation of the device is set up throughindividual registers. The set of the 16 registersrequired to configure the device is referred to as aRegister Bank, as shown in Figure 29 .
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RAM
ADS1216
SBAS171D – NOVEMBER 2000 – REVISED SEPTEMBER 2006
The RAM address space is linear; therefore,accessing RAM is done using an auto-incrementingReads and Writes to Registers and RAM occur on a
pointer. Access to RAM in the entire memory mapbyte basis. However, copies between registers and
can be done consecutively without having to addressRAM occur on a bank basis. The RAM is
each bank individually. For example, if you wereindependent of the Registers; for example, the RAM
currently accessing bank 0 at offset 0xF (the lastcan be used as general-purpose RAM.
location of bank 0), the next access would be bank 1and offset 0x0. Any access after bank 7 and offsetThe ADS1216 supports any combination of eight
0xF will wrap around to bank 0 and Offset 0x0.analog inputs. With this flexibility, the device caneasily support eight unique configurations—one per
Although the Register Bank memory is linear, theinput channel. In order to facilitate this type of usage,
concept of addressing the device can also beeight separate register banks are available.
thought of in terms of bank and offset addressing.Therefore, each configuration could be written once
Looking at linear and bank addressing syntax, weand recalled as needed without having to serially
have the following comparison: in the linear memoryretransmit all the configuration data. Checksum
map, the address 0x14 is equivalent to bank 1 andcommands are also included, which can be used to
offset 0x4. Simply stated, the most significant fourverify the integrity of RAM.
bits represent the bank, and the least significant fourbits represent the offset. The offset is equivalent toThe RAM provides eight banks, with a bank
the register address for that bank of memory.consisting of 16 bytes. The total size of the RAM is128 bytes. Copies between the registers and RAMare performed on a bank basis. Also, the RAM canbe directly read or written through the serial interfaceon power-up. The banks allow separate storage ofsettings for each input.
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REGISTER MAP
DETAILED REGISTER DEFINITIONS
ADS1216
SBAS171D – NOVEMBER 2000 – REVISED SEPTEMBER 2006
Table 3. RegistersADDRESS REGISTER BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
00h SETUP ID ID ID SPEED REF EN REF HI BUF EN BIT ORDER
01h MUX PSEL3 PSEL2 PSEL1 PSEL0 NSEL3 NSEL2 NSEL1 NSEL0
02h ACR BOCS IDAC2R1 IDAC2R0 IDAC1R1 IDAC1R0 PGA2 PGA1 PGA0
03h IDAC1 IDAC1_7 IDAC1_6 IDAC1_5 IDAC1_4 IDAC1_3 IDAC1_2 IDAC1_1 IDAC1_0
04h IDAC2 IDAC2_7 IDAC2_6 IDAC2_5 IDAC2_4 IDAC2_3 IDAC2_2 IDAC2_1 IDAC2_0
05h ODAC SIGN OSET_6 OSET_5 OSET_4 OSET_3 OSET_2 OSET_1 OSET_0
06h DIO DIO_7 DIO_6 DIO_5 DIO_4 DIO_3 DIO_2 DIO_1 DIO_0
07h DIR DIR_7 DIR_6 DIR_5 DIR_4 DIR_3 DIR_2 DIR_1 DIR_0
08h DEC0 DEC07 DEC06 DEC05 DEC04 DEC03 DEC02 DEC01 DEC00
09h M/DEC1 DRDY U/ B SMODE1 SMODE0 Reserved DEC10 DEC9 DEC8
0Ah OCR0 OCR07 OCR06 OCR05 OCR04 OCR03 OCR02 OCR01 OCR00
0Bh OCR1 OCR15 OCR14 OCR13 OCR12 OCR11 OCR10 OCR09 OCR08
0Ch OCR2 OCR23 OCR22 OCR21 OCR20 OCR19 OCR18 OCR17 OCR16
0Dh FSR0 FSR07 FSR06 FSR05 FSR04 FSR03 FSR02 FSR01 FSR00
0Eh FSR1 FSR15 FSR14 FSR13 FSR12 FSR11 FSR10 FSR09 FSR08
0Fh FSR2 FSR23 FSR22 FSR21 FSR20 FSR19 FSR18 FSR17 FSR16
SETUP (Address 00h) Setup Register
Reset value = iii01110.bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
ID ID ID SPEED REF EN REF HI BUF EN BIT ORDER
bits 7-5 Factory programmed bitsbit 4 SPEED: modulator clock speed0 : f
MOD
= f
OSC
/1281 : f
MOD
= f
OSC
/256bit 3 REF EN: Internal voltage reference enable0 = Internal voltage reference disabled1 = Internal voltage reference enabledbit 2 REF HI: internal reference voltage select0 = Internal reference voltage = 1.25V1 = Internal reference voltage = 2.5Vbit 1 BUF EN: buffer enable0 = Buffer disabled1 = Buffer enabledbit 0 BIT ORDER: set order bits are transmitted0 = Most significant bit transmitted first1 = Least significant bit transmitted first data is always shifted into the part most significant bit first.Data is always shifted out of the part most significant byte first. This configuration bit only controls thebit order within the byte of data that is shifted out.
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IDAC Current +ǒVREF
8RDACǓǒ2RANGE*1Ǔ(DAC CODE)
ADS1216
SBAS171D – NOVEMBER 2000 – REVISED SEPTEMBER 2006
MUX (Address 01h) Multiplexer Control Register
Reset value = 01h.bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
PSEL3 PSEL2 PSEL1 PSEL0 NSEL3 NSEL2 NSEL1 NSEL0
bits 7-4 PSEL3: PSEL2: PSEL1: PSEL0: Positive channel select0000 = A
IN
0 0100 = A
IN
40001 = A
IN
1 0101 = A
IN
50010 = A
IN
2 0110 = A
IN
60011 = A
IN
3 0111 = A
IN
71xxx = A
INCOM
(except when all bits are 1s)1111 = Temperature sensor diodebits 3-0 NSEL3: NSEL2: NSEL1: NSEL0: Negative channel select0000 = A
IN
0 0100 = A
IN
40001 = A
IN
1 0101 = A
IN
50010 = A
IN
2 0110 = A
IN
60011 = A
IN
3 0111 = A
IN
71xxx = A
INCOM
(except when all bits are 1s)1111 = Temperature sensor diode
ACR (Address 02h) Analog Control Register
Reset value = 00h.bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
BOCS IDAC2R1 IDAC2R0 IDAC1R1 IDAC1R0 PGA2 PGA1 PGA0
bit 7 BOCS: Burnout current source0 = Disabled
1 = Enabled
bits 6-5 IDAC2R1: IDAC2R0: Full-scale range select for IDAC200 = Off01 = Range 110 = Range 211 = Range 3bits 4-3 IDAC1R1: IDAC1R0: Full-scale range select for IDAC100 = Off01 = Range 110 = Range 211 = Range 3bits 2-0 PGA2: PGA1: PGA0: Programmable gain amplifier gain selection000 = 1 100 = 16001 = 2 101 = 32010 = 4 110 = 64011 = 8 111 = 128
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Offset +VREF
2PGA ǒCode
127 Ǔ
ADS1216
SBAS171D – NOVEMBER 2000 – REVISED SEPTEMBER 2006
IDAC1 (Address 03h) Current DAC 1
Reset value = 00h.bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
IDAC1_7 IDAC1_6 IDAC1_5 IDAC1_4 IDAC1_3 IDAC1_2 IDAC1_1 IDAC1_0
The DAC code bits set the output of DAC1 from 0 to full-scale. The value of the full-scale current is set by this byte, V
REF
, R
DAC
, and theDAC1 range bits in the ACR register.
IDAC2 (Address 04h) Current DAC 2
Reset value = 00h.bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
IDAC2_7 IDAC2_6 IDAC2_5 IDAC2_4 IDAC2_3 IDAC2_2 IDAC2_1 IDAC2_0
The DAC code bits set the output of DAC2 from 0 to full-scale. The value of the full-scale current is set by this byte, V
REF
, R
DAC
, and theDAC2 range bits in the ACR register.
ODAC (Address 05h) Offset DAC Setting
Reset value = 00h.bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
SIGN OSET6 OSET5 OSET4 OSET3 OSET2 OSET1 OSET0
bit 7 Offset sign0 = Positive
1 = Negativebits 6-0
NOTE: The offset must be used after calibration or the calibration will nullify the effects.
DIO (Address 06h) Digital I/O
Reset value = 00h.bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
DIO7 DIO6 DIO5 DIO4 DIO3 DIO2 DIO1 DIO0
A value written to this register will appear on the digital I/O pins if the pin is configured as an output in the DIR register. Reading thisregister will return the value of the digital I/O pins.
DIR (Address 07h) Direction control for digital I/O
Reset value = FFh.bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
DIR7 DIR6 DIR5 DIR4 DIR3 DIR2 DIR1 DIR0
Each bit controls whether the Digital I/O pin is an output (= 0) or input (= 1). The default power-up state is asinputs.
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ADS1216
SBAS171D – NOVEMBER 2000 – REVISED SEPTEMBER 2006
DEC0 (Address 08h) Decimation Register (least significant 8 bits)
Reset value = 80h.bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
DEC07 DEC06 DEC05 DEC04 DEC03 DEC02 DEC01 DEC00
The decimation value is defined with 11 bits for a range of 20 to 2047. This register is the least significant eight bits. The three mostsignificant bits are contained in the M/DEC1 register.
M/DEC1 (Address 09h) Mode and Decimation Register
Reset value = 07h.bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
DRDY U/ B SMODE1 SMODE0 Reserved DEC10 DEC09 DEC08
bit 7 DRDY: Data ready (read-only)This bit duplicates the state of the DRDY pin.bit 6 U/ B: Data format0 = Bipolar
1 = Unipolar
U/ B ANALOG INPUT DIGITAL OUTPUT
0 +FS 0x7FFFFFZero 0x000000–FS 0x8000001 +FS 0xFFFFFFZero 0x000000–FS 0x000000
bits 5-4 SMODE1: SMODE0: Settling mode00 = Auto01 = Fast-Settling filter10 = Sinc
2
filter11 = Sinc
3
filterbit 3 Reserved
This bit is not used in the ADS1216 and it is recommended that it be set to 0.bits 2-0 DEC10: DEC09: DEC08: Most significant bits of the decimation value
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ADS1216
SBAS171D – NOVEMBER 2000 – REVISED SEPTEMBER 2006
OCR0 (Address 0Ah) Offset Calibration Coefficient (least significant byte)
Reset value = 00h.bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
OCR07 OCR06 OCR05 OCR04 OCR03 OCR02 OCR01 OCR00
OCR1 (Address 0Bh) Offset Calibration Coefficient (middle byte)
Reset value = 00h.bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
OCR15 OCR14 OCR13 OCR12 OCR11 OCR10 OCR09 OCR08
OCR2 (Address 0Ch) Offset Calibration Coefficient (most significant byte)
Reset value = 00h.bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
OCR23 OCR22 OCR21 OCR20 OCR19 OCR18 OCR17 OCR16
FSR0 (Address 0Dh) Full-Scale Register (least significant byte)
Reset value = 24h.bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
FSR07 FSR06 FSR05 FSR04 FSR03 FSR02 FSR01 FSR00
FSR1 (Address 0Eh) Full-Scale Register (middle byte)
Reset value = 90h.bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
FSR15 FSR14 FSR13 FSR12 FSR11 FSR10 FSR09 FSR08
FSR2 (Address 0Fh) Full-Scale Register (most significant byte)
Reset value = 67h.bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
FSR23 FSR22 FSR21 FSR20 FSR19 FSR18 FSR17 FSR16
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COMMAND DEFINITIONS
ADS1216
SBAS171D – NOVEMBER 2000 – REVISED SEPTEMBER 2006
The commands summarized in Table 4 control the operation of the ADS1216. All of the commands arestand-alone except for the register reads and writes (RREG, WREG) which require a second command byteplus data. Additional command and data bytes may be shifted in without delay after the first command byte. TheORDER bit in the STATUS register (see the Register map section) sets the order of the bits within the outputdata. CS must stay low during the entire command sequence.
Table 4. Command Definitions
(1)
COMMAND DESCRIPTION 1ST COMMAND BYTE 2ND COMMAND BYTE
WAKEUP Completes SYNC and exits standby mode 0000 0000 (00h)RDATA Read data 0000 0001 (01h)RDATAC Read data continuously 0000 0011 (03h)SDATAC Stop read data continuously 0000 1111 (0Fh)RREG Read from REG rrr 0001 rrrr (1xh) 0000 nnnnRRAM Read from RAM bank aaa 0010 0 aaa (2xh) x nnn nnnn (number of bytes – 1)CREG Copy REG to RAM bank aaa 0100 0 aaa (4xh)CREGA Copy REG to all RAM banks 0100 1000 (48h)WREG Write to REG rrr 0101 rrrr (5xh) 0000 nnnnWRAM Write to RAM bank aaa 0110 0 aaa (6xh) x nnn nnnn (number of bytes – 1)CRAM Copy RAM bank aaa to REG 1100 0 aaa (Cxh)CSRAMX Calculate RAM bank aaa checksum 1101 0 aaa (Dxh)CSARAMX Calculate all RAM banks checksum 1101 1000 (D8h)CSREG Calculate REG checksum 1101 1111 (DFh)CSRAM Calculate RAM bank aaa checksum 1110 0 aaa (Exh)CSARAM Calculate all RAM banks checksum 1110 1000 (E8h)SELFCAL Offset and gain self-calibration 1111 0000 (F0h)SELFOCAL Offset self-calibration 1111 0001 (F1h)SELFGCAL Gain self-calibration 1111 0010 (F2h)SYSOCAL System offset calibration 1111 0011 (F3h)SYSGCAL System gain calibration 1111 0100 (F4h)DSYNC Synchronize the A/D conversion 1111 1100 (FCh)SLEEP Begin sleep mode 1111 1101 (FDh)RESET Reset to power-up values 1111 1110 (FEh)WAKEUP Completes SYNC and exits standby mode 1111 1111 (FFh)
(1) n = number of registers to be read/written – 1. For example, to read/write three registers, set nnnn = 2 (0010). r = starting registeraddress for read/write commands.
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DOUT
SCLK
DIN
MSB
t6
Mid-Byte LSB
DRDY
00000001
· · ·· · ·
DOUT
DIN
24Bits
DRDY
24Bits
00000011
t6
DOUT
DIN
DRDY
input_data input_data input_data
MSB Mid-Byte LSB
ADS1216
SBAS171D – NOVEMBER 2000 – REVISED SEPTEMBER 2006
RDATA Read Data
Description: Issue this command after DRDY goes low to read a single conversion result. After all 24 bits havebeen shifted out on D
OUT
, DRDY goes high. It is not necessary to read back all 24 bits, but DRDY will then notreturn high until new data is being updated. See the Timing Characteristics for the required delay between theend of the RDATA command and the beginning of shifting data on D
OUT
: t
6
.
Figure 30. RDATA Command Sequence
RDATAC Read Data Continuous
Description: Issue command after DRDY goes low to enter the Read Data Continuous mode. This modeenables the continuous output of new data on each DRDY without the need to issue subsequent readcommands. After all 24 bits have been read, DRDY goes high. It is not necessary to read back all 24 bits, butDRDY will then not return high until new data is being updated. This mode may be terminated by the Stop ReadData Continuous command (STOPC). Because D
IN
is constantly being monitored during the Read DataContinuous mode for the STOPC or RESET command, do not use this mode if D
IN
and D
OUT
are connectedtogether. See the Timing Characteristics for the required delay between the end of the RDATAC command andthe beginning of shifting data on D
OUT
: t
6
.
Figure 31. RDATAC Command Sequence
On the following DRDY, shift out data by applying SCLKs. The Read Data Continuous mode terminates ifinput_data equals the STOPC or RESET command in any of the three bytes on D
IN
.
Figure 32. D
IN
and D
OUT
Command Sequence During Read Continuous mode
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DIN
DRDY
0001111
DOUT
DIN 00010001 00000001
1stCommand
Byte
2ndCommand
Byte
MUX ADCON
Data
Byte
Data
Byte
t6
DOUT
DIN 00100001 00001111
Bank1,
Byte0
Bank1,
Byte1
t6
RAMData
ADS1216
SBAS171D – NOVEMBER 2000 – REVISED SEPTEMBER 2006
STOPC Stop Read Data Continuous
Description: Ends the continuous data output mode; refer to RDATAC in the Command Definitions section. Thecommand must be issued after DRDY goes low and completed before DRDY goes high.
Figure 33. STOPC Command Sequence
RREG Read from Registers
Description: Output the data from up to 16 registers starting with the register address specified as part of thecommand. The number of registers read will be one plus the second byte of the command. If the count exceedsthe remaining registers, the addresses will wrap back to the beginning.
1st Command Byte: 0001 rrrr where rrrr is the address of the first register to read.
2nd Command Byte: 0000 nnnn where nnnn is the number of bytes to read – 1. See the Timing Characteristicsfor the required delay between the end of the RREG command and the beginning of shifting data on D
OUT
: t
6
.
Figure 34. RREG Command Example: Read Two Registers Starting from Regiater 01h (multiplexer)
RRAM Read from RAM
Description:This command allows for the direct reading of the RAM contents. All reads begin at the specifiedstarting RAM bank. More than one bank can be read out in a single read operation. The reads will wrap aroundto the first bank if there is more data to be retrieved when the last bank is completely read. See the TimingCharacteristics for the required delay between the end of the RRAM command and the beginning of shifting dataon D
OUT
: t
6
.
1st Command Byte: 0010 0 aaa where aaa is the starting RAM bank for the read.
2nd Command Byte: 0 nnn nnnn where nnn nnnn is the number of bytes to be read – 1.
Figure 35. RRAM Command Example: Read 16 Bytes Starting from Bank 1
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DIN 01010011 00000001
1stCommand
Byte
2ndCommand
Byte
DRATEData
IOData
Data
Byte
Data
Byte
DIN 01100001 00001111 Bank1,
Byte0
RAMData
Bank1,
Byte1
tx
ADS1216
SBAS171D – NOVEMBER 2000 – REVISED SEPTEMBER 2006
CREG Copy Registers to RAM Bank
Description: This command copies the registers to the selected RAM bank. Do not issue additional commandswhile the copy operation is underway.
1st Command byte: 0100 0 aaa where aaa is the RAM bank that will be updated with a copy of the registers.
CREGA Copy Registers to All RAM Banks
Description: This command copies the registers to all RAM banks. Do not issue additional commands while thecopy operation is underway.
WREG Write to Register
Description: Write to the registers starting with the register specified as part of the command. The number ofregisters that will be written is one plus the value of the second byte in the command.
1st Command Byte: 0101 rrrr where rrrr is the address to the first register to be written.
2nd Command Byte: 0000 nnnn where nnnn is the number of bytes to be written – 1.
Data Byte(s): data to be written to the registers.
Figure 36. WREG Command Example: Write Two Registers Starting from 03h (DRATE)
WRAM Write to RAM
Description: This command allows for direct writing to the RAM. All writes begin at the specified starting RAMbank. More than one bank can be written in a single write operation. The writes will wrap around to the first bankif there is more data to be written when the last bank is completely written. See the Timing Characteristics forthe required delay between the end of the RRAM command and the beginning of shifting data on D
OUT
: t
6
.
1st Command Byte: 0010 0 aaa where aaa is the starting RAM bank for the write.
2nd Command Byte: 0 nnn nnnn where nnn nnnn is the number of bytes to be written – 1.
Figure 37. WRAM Command Example: Write 16 Bytes Starting at Bank 1
CRAM Copy Selected RAM Bank to Registers
Description: This command copies the selected RAM bank to the registers. This action will overwrite allprevious register settings. Do not issue additional commands while this copy operation is underway.
1st Command Byte: 1100 0 aaa where aaa is the selected RAM bank.
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DOUT
DIN
24Bits
00000011
t6
ADS1216
SBAS171D – NOVEMBER 2000 – REVISED SEPTEMBER 2006
CSRAM Calculate Checksum for Selected RAM Bank
Description: This command calculates the checksum for the selected RAM bank. The checksum is calculatedas the sum of all the bytes in the registers with the carry ignored. Do not issue any additional commands whilethe checksum is being calculated.
CSRAMX Calculate Checksum for Selected RAM Bank,Ignoring Certain Bits
Description: This command calculates the checksum of the selected RAM bank. The checksum is calculated asa sum of all the bytes in the RAM bank with the carry ignored. The ID, DRDY, and DIO bits are masked and arenot included in the checksum calculation. Do not issue any additional commands while the checksum is beingcalculated.
CSARAM Calculate Checksum for all RAM Banks
Description: This command calculates the checksum for all RAM banks. The checksum is calculated as a sumof all the bytes in the RAM bank with the carry ignored. Do not issue any additional commands while thechecksum is being calculated.
Calculate Checksum for all RAM Banks, IgnoringCSARAMX Certain Bits
Description: This command calculates the checksum for all RAM banks. The checksum is calculated as a sumof all the bytes in the RAM bank with the carry ignored. The ID, DRDY, and DIO bits are masked and are notincluded in the checksum calculation. Do not issue any additional commands while the checksum is beingcalculated.
CSREG Calculate Checksum for the Registers
Description: This command calculates the checksum for the registers. The checksum is calculated as a sum ofall the bytes in the registers with the carry ignored. The ID, DRDY, and DIO bits are masked and are notincluded in the checksum calculation. Do not issue any additional commands while the checksum is beingcalculated.
See the Timing Characteristics for the required delay between the end of the checksum commands and thebeginning of shifting data on D
OUT
: t
6
. Note that this time is dependent on the specific checksum command used.
Figure 38. Checksum Command Sequence
SYSOCAL System Offset Calibration
Description: Performs a system offset calibration. The Offset Calibration Register (OFC) is updated after thisoperation. DRDY goes high at the beginning of the calibration. It goes low after the calibration completes andsettled data is ready. Do not send additional commands after issuing this command until DRDY goes lowindicating that the calibration is complete.
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DIN
SCLK
CLKIN
··· ···
······
11111100
(SYNC)
00000000
(WAKEUP)
SynchronizationOccursHere
DIN
SCLK
11111101
(SLEEP)
NormalMode SleepMode NormalMode
00000000
(WAKEUP)
ADS1216
SBAS171D – NOVEMBER 2000 – REVISED SEPTEMBER 2006
SYSGCAL System Gain Calibration
Description: Performs a system gain calibration. The Full-Scale Calibration Register (FSC) is updated after thisoperation. DRDY goes high at the beginning of the calibration. It goes low after the calibration completes andsettled data is ready. Do not send additional commands after issuing this command until DRDY goes lowindicating that the calibration is complete.
DSYNC Synchronize the A/D Conversion
Description: This command synchronizes the A/D conversion. To use, first shift in the command. Then shift inthe WAKEUP command. Synchronization occurs on the first CLKIN rising edge after the first SCLK used to shiftin the WAKEUP command.
Figure 39. DSYNC Command Sequence
SLEEP Sleep Mode
Description: This command puts the ADS1216 into a Sleep mode. After issuing the SLEEP command, makesure there is no more activity on SCLK while CS is low because this will interrupt Sleep mode. If CS is high,SCLK activity is allowed during Sleep mode. To exit Sleep mode, issue the WAKEUP command.
Figure 40. SLEEP Command Sequence
WAKEUP Complete Synchronization or Exit Sleep Mode
Description: Used in conjunction with the SYNC and STANDBY commands. Two values (all zeros or all ones)are available for this command.
RESET Reset Registers to Default Values
Description: Returns all registers to their default values. This command will also stop the Read DataContinuous mode. While in the Read Data Continuous mode, the RESET command must be issued after DRDYgoes low and complete before DRDY returns high.
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DEFINITIONS
ENOB +−20 log(ppm)
6.02
ǒ2VREF
PGA Ǔ
10ǒ6.02ER
20 Ǔ
ǒVREF
PGA Ǔ
10ǒ6.02ER
20 Ǔ
fDATA +ǒfMOD
Decimation RatioǓ+ǒfOSC
mfactor Decimation RatioǓ
fSAMP +fOSC
mfactor
fSAMP +2fOSC
mfactor
fSAMP +8fOSC
mfactor
fSAMP +16fOSC
mfactor
fSAMP +16fOSC
mfactor
ADS1216
SBAS171D – NOVEMBER 2000 – REVISED SEPTEMBER 2006
Analog Input Voltage—the voltage at any one
The data from the A/D converter is output as codes,analog input relative to AGND.
which then can be easily converted to other units,Analog Input Differential Voltage—given by the such as ppm or volts. The equations and table belowfollowing equation: (A
IN+
) – (A
IN–
). Thus, a positive show the relationship between bits or codes, ppm,digital output is produced whenever the analog input and volts.differential voltage is positive, while a negative digitaloutput is produced whenever the differential isnegative.
BITS rms BIPOLAR V
RMS
UNIPOLAR V
RMSFor example, when the converter is configured with a2.5V reference and placed in a gain setting of 1, thepositive full-scale output is produced when theanalog input differential is 2.5V. The negativefull-scale output is produced when the differential is
24 298nV 149nV–2.5V. In each case, the actual input voltages mustremain within the AGND to AV
DD
range.
22 1.19 µV 597nV20 4.77 µV 2.39 µVConversion Cycle—the term conversion cycle
18 19.1 µV 9.55 µVusually refers to a discrete A/D conversion operation,such as that performed by a successive
16 76.4 µV 38.2 µVapproximation converter. As used here, a conversion
14 505 µV 152.7 µVcycle refers to the t
DATA
time period. However, each
12 1.22mV 610 µVdigital output is actually based on the modulatorresults from several t
DATA
time periods.
f
DATA
—the frequency of the digital output dataFILTER SETTING MODULATOR RESULTS
produced by the ADS1216. f
DATA
is also referred toas the data rate.Fast Settling 1 t
DATA
Time PeriodSinc
2
2 t
DATA
Time PeriodSinc
3
3 t
DATA
Time Period
f
MOD
—the frequency or speed at which the modulatorData Rate—the rate at which conversions are
of the ADS1216 is running. This rate depends on thecompleted. See definition for f
DATA
.
SPEED bit as shown below:Decimation Ratio—defines the ratio between the
SPEED BIT f
MODoutput of the modulator and the output Data Rate.
0 f
OSC
/128Valid values for the Decimation Ratio are from 20 to2047. Larger Decimation Ratios will have lower
1 f
OSC
/256noise.
f
OSC
—the frequency of the crystal input signal at theEffective Resolution—the effective resolution of the
X
IN
input of the ADS1216.ADS1216 in a particular configuration can beexpressed in two different units: bits rms (referenced
f
SAMP
—the frequency, or switching speed, of theto output) and V
RMS
(referenced to input). Computed
input sampling capacitor. The value is given by onedirectly from the converter output data, each is a
of the following equations:statistical calculation. The conversion from one to the
PGA SETTING SAMPLING FREQUENCYother is shown below.
1, 2, 4, 8Effective number of bits (ENOB) or effectiveresolution is commonly used to define the usableresolution of the A/D converter. It is calculated from
8empirical data taken directly from the device. It istypically determined by applying a fixed known signal
16source to the analog input and computing thestandard deviation of the data sample set. The rms
32noise defines the ± σ interval about the sample mean.
64, 128
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LSB Weight +Full−Scale Range
2N
(1)
2VREF
PGA
"VREF
PGA
"VREF
2PGA
ADS1216
SBAS171D – NOVEMBER 2000 – REVISED SEPTEMBER 2006
Filter Selection—the ADS1216 uses a (sinx/x) filter For example, when the converter is configured with aor sinc filter. There are three different sinc filters that 2.5V reference and is placed in a gain setting of 2,can be selected. A Fast-Settling filter will settle in the full-scale range is: [1.25V (positive full-scale) –one t
DATA
cycle. The Sinc
2
filter will settle in two (–1.25V (negative full-scale))] = 2.5V.cycles and have lower noise. The Sinc
3
will achieve
Least Significant Bit (LSB) Weight—this is thelowest noise and higher number of effective bits, but
theoretical amount of voltage that the differentialrequires three cycles to settle. The ADS1216 will
voltage at the analog input would have to change inoperate with any one of these filters, or it can
order to observe a change in the output data of oneoperate in an auto mode, where it will first select the
least significant bit. It is computed as shown inFast-Settling filter after a new channel is selected for
Equation 1 :two readings and will then switch to Sinc
2
for onereading, followed by Sinc
3
from then on.
Full-Scale Range (FSR)—as with most A/D
where Nis the number of bits in the digital output.converters, the full-scale range of the ADS1216 isdefined as the input, which produces the positive
t
DATA
—the inverse of f
DATA
, or the period betweenfull-scale digital output minus the input, which
each data output.produces the negative full-scale digital output. Thefull-scale range changes with gain setting; seeTable 5 .
Table 5. Full-Scale Range vs PGA Setting
5V SUPPLY ANALOG INPUT
(1)
GENERAL EQUATIONS
DIFFERENTIAL DIFFERENTIALGAIN FULL-SCALE INPUT PGA OFFSET FULL-SCALE INPUT PGA SHIFTSETTING RANGE VOLTAGES
(2)
RANGE RANGE VOLTAGES
(2)
RANGE
1 5V ±2.5V ±1.25V2 2.5V ±1.25V ±0.625V4 1.25V ±0.625V ±312.5mV8 0.625V ±312.5mV ±156.25mV16 312.5mV ±156.25mV ±78.125mV
34 156.25mV ±78.125mV ±39.0625mV64 78.125mV ±39.0625mV ±19.531mV128 39.0625mV ±19.531mV ±9.766mV
(1) With a 2.5V reference.(2) The ADS1216 allows common-mode voltage as long as the absolute input voltage on A
IN+
or A
IN–
does not go below AGND or aboveAV
DD
.
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ADS1216
SBAS171D – NOVEMBER 2000 – REVISED SEPTEMBER 2006
Changes from C Revision (May 2006) to D Revision ..................................................................................................... Page
•Added title for Table 1 ......................................................................................................................................................... 16•Changed 11 registers to 16 registers in Description text of RREG section in Command Definitions. ............................... 28
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PACKAGE OPTION ADDENDUM
www.ti.com 21-May-2010
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
ADS1216Y/250 ACTIVE TQFP PFB 48 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
ADS1216Y/250G4 ACTIVE TQFP PFB 48 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
ADS1216Y/2K ACTIVE TQFP PFB 48 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
ADS1216Y/2KG4 ACTIVE TQFP PFB 48 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
ADS1216Y/250 TQFP PFB 48 250 330.0 16.4 9.6 9.6 1.5 12.0 16.0 Q2
ADS1216Y/2K TQFP PFB 48 2000 330.0 16.4 9.6 9.6 1.5 12.0 16.0 Q2
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
ADS1216Y/250 TQFP PFB 48 250 367.0 367.0 38.0
ADS1216Y/2K TQFP PFB 48 2000 367.0 367.0 38.0
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 2
MECHANICAL DATA
MTQF019A – JANUARY 1995 – REVISED JANUARY 1998
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PFB (S-PQFP-G48) PLASTIC QUAD FLATPACK
4073176/B 10/96
Gage Plane
0,13 NOM
0,25
0,45
0,75
Seating Plane
0,05 MIN
0,17
0,27
24
25
13
12
SQ
36
37
7,20
6,80
48
1
5,50 TYP
SQ
8,80
9,20
1,05
0,95
1,20 MAX 0,08
0,50 M
0,08
0°–7°
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026
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