LPC408x/7x 32-bit ARM Cortex-M4 MCU; up to 512 kB flash, 96 kB SRAM; USB Device/Host/OTG; Ethernet; LCD; EMC; SPIFI Rev. 3.3 -- 16 October 2015 Product data sheet 1. General description The LPC408x/7x is an ARM Cortex-M4 based digital signal controller for embedded applications requiring a high level of integration and low power dissipation. The ARM Cortex-M4 is a next generation core that offers system enhancements such as low power consumption, enhanced debug features, and a high level of support block integration. The ARM Cortex-M4 CPU incorporates a 3-stage pipeline, uses a Harvard architecture with separate local instruction and data buses as well as a third bus for peripherals, and includes an internal prefetch unit that supports speculative branching. The ARM Cortex-M4 supports single-cycle digital signal processing and SIMD instructions. A hardware floating-point processor is integrated in the core for several versions of the part. The LPC408x/7x adds a specialized flash memory accelerator to accomplish optimal performance when executing code from flash. The LPC408x/7x is targeted to operate at up to 120 MHz CPU frequency. The peripheral complement of the LPC408x/7x includes up to 512 kB of flash program memory, up to 96 kB of SRAM data memory, up to 4032 byte of EEPROM data memory, External Memory controller (EMC), LCD, Ethernet, USB Device/Host/OTG, an SPI Flash Interface (SPIFI), a General Purpose DMA controller, five UARTs, three SSP controllers, three I2C-bus interfaces, a Quadrature Encoder Interface, four general purpose timers, two general purpose PWMs with six outputs each and one motor control PWM, an ultra-low power RTC with separate battery supply and event recorder, a windowed watchdog timer, a CRC calculation engine and up to 165 general purpose I/O pins. The analog peripherals include one eight-channel 12-bit ADC, two analog comparators, and a DAC. The pinout of LPC408x/7x is intended to allow pin function compatibility with the LPC24xx/23xx as well as the LPC178x/7x families. For additional documentation, see Section 17 "References". 2. Features and benefits Functional replacement for LPC23xx/24xx and LPC178x/7x family devices. ARM Cortex-M4 core: ARM Cortex-M4 processor, running at frequencies of up to 120 MHz. ARM Cortex-M4 built-in Memory Protection Unit (MPU) supporting eight regions. ARM Cortex-M4 built-in Nested Vectored Interrupt Controller (NVIC). LPC408x/7x NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller LPC408X_7X Product data sheet Hardware floating-point unit (not all versions). Non-maskable Interrupt (NMI) input. JTAG and Serial Wire Debug (SWD), serial trace, eight breakpoints, and four watch points. System tick timer. System: Multilayer AHB matrix interconnect provides a separate bus for each AHB master. AHB masters include the CPU, and General Purpose DMA controller. This interconnect provides communication with no arbitration delays unless two masters attempt to access the same slave at the same time. Split APB bus allows for higher throughput with fewer stalls between the CPU and DMA. A single level of write buffering allows the CPU to continue without waiting for completion of APB writes if the APB was not already busy. Embedded Trace Macrocell (ETM) module supports real-time trace. Boundary scan for simplified board testing. Memory: 512 kB on-chip flash program memory with In-System Programming (ISP) and In-Application Programming (IAP) capabilities. The combination of an enhanced flash memory accelerator and location of the flash memory on the CPU local code/data bus provides high code performance from flash. Up to 96 kB on-chip SRAM includes: 64 kB of main SRAM on the CPU with local code/data bus for high-performance CPU access. Two 16 kB peripheral SRAM blocks with separate access paths for higher throughput. These SRAM blocks may be used for DMA memory as well as for general purpose instruction and data storage. Up to 4032 byte on-chip EEPROM. LCD controller, supporting both Super-Twisted Nematic (STN) and Thin-Film Transistors (TFT) displays. Dedicated DMA controller. Selectable display resolution (up to 1024 768 pixels). Supports up to 24-bit true-color mode. External Memory Controller (EMC) provides support for asynchronous static memory devices such as RAM, ROM and flash, as well as dynamic memories such as single data rate SDRAM. Eight channel General Purpose DMA controller (GPDMA) on the AHB multilayer matrix that can be used with the SSP, I2S, UART, CRC engine, Analog-to-Digital and Digital-to-Analog converter peripherals, timer match signals, GPIO, and for memory-to-memory transfers. Serial interfaces: Quad SPI Flash Interface (SPIFI) with four lanes and up to 40 MB per second. Ethernet MAC with MII/RMII interface and associated DMA controller. These functions reside on an independent AHB. USB 2.0 full-speed dual port device/host/OTG controller with on-chip PHY and associated DMA controller. All information provided in this document is subject to legal disclaimers. Rev. 3.3 -- 16 October 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 2 of 138 LPC408x/7x NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller Five UARTs with fractional baud rate generation, internal FIFO, DMA support, and RS-485/EIA-485 support. One UART (UART1) has full modem control I/O, and one UART (USART4) supports IrDA, synchronous mode, and a smart card mode conforming to ISO7816-3. Three SSP controllers with FIFO and multi-protocol capabilities. The SSP interfaces can be used with the GPDMA controller. Three enhanced I2C-bus interfaces, one with a true open-drain output supporting the full I2C-bus specification and Fast-mode Plus with data rates of 1 Mbit/s, two with standard port pins. Enhancements include multiple address recognition and monitor mode. I2S (Inter-IC Sound) interface for digital audio input or output. It can be used with the GPDMA. CAN controller with two channels. Digital peripherals: SD/MMC memory card interface. Up to 165 General Purpose I/O (GPIO) pins depending on the packaging, with configurable pull-up/down resistors, open-drain mode, and repeater mode. All GPIOs are located on an AHB bus for fast access and support Cortex-M4 bit-banding. GPIOs can be accessed by the General Purpose DMA Controller. Any pin of ports 0 and 2 can be used to generate an interrupt. Two external interrupt inputs configurable as edge/level sensitive. All pins on port 0 and port 2 can be used as edge sensitive interrupt sources. Four general purpose timers/counters, with a total of eight capture inputs and ten compare outputs. Each timer block has an external count input. Specific timer events can be selected to generate DMA requests. Quadrature encoder interface that can monitor one external quadrature encoder. Two standard PWM/timer blocks with external count input option. One motor control PWM with support for three-phase motor control. Real-Time Clock (RTC) with a separate power domain. The RTC is clocked by a dedicated RTC oscillator. The RTC block includes 20 bytes of battery-powered backup registers, allowing system status to be stored when the rest of the chip is powered off. Battery power can be supplied from a standard 3 V lithium button cell. The RTC will continue working when the battery voltage drops to as low as 2.1 V. An RTC interrupt can wake up the CPU from any reduced power mode. Event Recorder that can capture the clock value when an event occurs on any of three inputs. The event identification and the time it occurred are stored in registers. The Event Recorder is located in the RTC power domain and can therefore operate as long as there is RTC power. Windowed Watchdog Timer (WWDT). Windowed operation, dedicated internal oscillator, watchdog warning interrupt, and safety features. CRC Engine block can calculate a CRC on supplied data using one of three standard polynomials. The CRC engine can be used in conjunction with the DMA controller to generate a CRC without CPU involvement in the data transfer. Analog peripherals: 12-bit Analog-to-Digital Converter (ADC) with input multiplexing among eight pins, conversion rates up to 400 kHz, and multiple result registers. The 12-bit ADC can be used with the GPDMA controller. LPC408X_7X Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3.3 -- 16 October 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 3 of 138 LPC408x/7x NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller 10-bit Digital-to-Analog Converter (DAC) with dedicated conversion timer and DMA support. Two analog comparators. Power control: Four reduced power modes: Sleep, Deep-sleep, Power-down, and Deep power-down. The Wake-up Interrupt Controller (WIC) allows the CPU to automatically wake up from any priority interrupt that can occur while the clocks are stopped in Deep-sleep, Power-down, and Deep power-down modes. Processor wake-up from Power-down mode via any interrupt able to operate during Power-down mode (includes external interrupts, RTC interrupt, PORT0/2 pin interrupt, and NMI). Brownout detect with separate threshold for interrupt and forced reset. On-chip Power-On Reset (POR). Clock generation: Clock output function that can reflect the main oscillator clock, IRC clock, RTC clock, CPU clock, USB clock, or the watchdog timer clock. On-chip crystal oscillator with an operating range of 1 MHz to 25 MHz. 12 MHz Internal RC oscillator (IRC) trimmed to 1 % accuracy that can optionally be used as a system clock. An on-chip PLL allows CPU operation up to the maximum CPU rate without the need for a high-frequency crystal. May be run from the main oscillator or the internal RC oscillator. A second, dedicated PLL may be used for USB interface in order to allow added flexibility for the Main PLL settings. Versatile pin function selection feature allows many possibilities for using on-chip peripheral functions. Unique device serial number for identification purposes. Single 3.3 V power supply (2.4 V to 3.6 V). Temperature range of 40 C to 85 C. Available as LQFP208, TFBGA208, TFBGA180, LQFP144, TFBGA80, and LQFP80 package. 3. Applications Communications: Point-of-sale terminals, web servers, multi-protocol bridges Industrial/Medical: Automation controllers, application control, robotics control, HVAC, PLC, inverters, circuit breakers, medical scanning, security monitoring, motor drive, video intercom Consumer/Appliance: Audio, MP3 decoders, alarm systems, displays, printers, scanners, small appliances, fitness equipment Automotive: After-market, car alarms, GPS/fleet monitors LPC408X_7X Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3.3 -- 16 October 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 4 of 138 LPC408x/7x NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller 4. Ordering information Table 1. Ordering information Type number Package Name Description Version LPC4088 LPC4088FBD208 LQFP208 plastic low profile quad flat package; 208 leads; body 28 28 1.4 mm SOT459-1 LPC4088FET208 TFBGA208 plastic thin fine-pitch ball grid array package; 208 balls; body 15 15 0.7 mm SOT950-1 LPC4088FET180 TFBGA180 thin fine-pitch ball grid array package; 180 balls SOT570-3 LPC4088FBD144 LQFP144 plastic low profile quad flat package; 144 leads; body 20 20 1.4 mm SOT486-1 LPC4078FBD208 LQFP208 plastic low profile quad flat package; 208 leads; body 28 28 1.4 mm SOT459-1 LPC4078FET208 TFBGA208 plastic thin fine-pitch ball grid array package; 208 balls; body 15 15 0.7 mm SOT950-1 LPC4078FET180 TFBGA180 thin fine-pitch ball grid array package; 180 balls SOT570-3 LPC4078FBD144 LQFP144 plastic low profile quad flat package; 144 leads; body 20 20 1.4 mm SOT486-1 LPC4078FBD80 LQFP80 plastic low-profile quad package; 80 leads; body 12 12 1.4 mm SOT315-1 LPC4078FBD100 LQFP100 plastic low profile quad flat package; 100 leads; body 14 14 1.4 mm SOT407-1 LPC4076FET180 TFBGA180 thin fine-pitch ball grid array package; 180 balls SOT570-3 LPC4076FBD144 LQFP144 plastic low profile quad flat package; 144 leads; body 20 20 1.4 mm SOT486-1 LPC4074FBD144 LQFP144 plastic low profile quad flat package; 144 leads; body 20 20 1.4 mm SOT486-1 LPC4074FBD80 LQFP80 plastic low-profile quad package; 80 leads; body 12 12 1.4 mm SOT315-1 LPC4078 LPC4076 LPC4074 LPC4072 LPC4072FET80 TFBGA80 plastic thin fine-pitch ball grid array package; 80 balls SOT1328-1 LPC4072FBD80 LQFP80 plastic low-profile quad package; 80 leads; body 12 12 1.4 mm SOT315-1 Package FPU Comparator SD/MMC QEI UART CAN USB Ethernet LCD EMC bus width (bit) Flash (kB) Type number EEPROM (B) Ordering options SRAM (kB) Table 2. LPC4088 LPC4088FBD208 512 96 4032 32 yes yes H/O/D 2 5 yes yes yes yes LQFP208 LPC4088FET208 512 96 4032 32 yes yes H/O/D 2 5 yes yes yes yes TFBGA208 LPC4088FET180 512 96 4032 16 yes yes H/O/D 2 5 yes yes yes yes TFBGA180 LPC4088FBD144 512 96 4032 8 yes yes H/O/D 2 5 yes yes yes yes LQFP144 LPC4078FBD208 512 96 4032 32 no yes H/O/D 2 5 yes yes yes yes LQFP208 LPC4078FET208 512 96 4032 32 no yes H/O/D 2 5 yes yes yes yes TFBGA208 LPC4078FET180 512 96 4032 16 no yes H/O/D 2 5 yes yes yes yes TFBGA180 LPC4078 LPC408X_7X Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3.3 -- 16 October 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 5 of 138 LPC408x/7x NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller Table 2. Ordering options ...continued EMC bus width (bit) LCD Ethernet USB UART QEI SD/MMC Comparator FPU Package 96 4032 8 no yes H/O/D 2 5 yes yes yes yes LQFP144 LPC4078FBD100 512 96 4032 - no yes H/O/D 2 5 yes yes yes yes LQFP100 LPC4078FBD80 96 4032 - no yes H/O/D 2 5 yes no yes yes LQFP80 512 CAN EEPROM (B) LPC4078FBD144 512 Flash (kB) SRAM (kB) Type number LPC4076 LPC4076FET180 256 80 2048 16 no yes H/O/D 2 5 yes yes yes yes TFBGA180 LPC4076FBD144 256 80 2048 8 no yes H/O/D 2 5 yes yes yes yes LQFP144 LPC4074FBD144 128 40 2048 - no no D 2 4 no no no no LQFP144 LPC4074FBD80 128 40 2048 - no no D 2 4 no no no no LQFP80 LPC4072FET80 64 24 2048 - no no D 2 4 no no no no TFBGA80 LPC4072FBD80 64 24 2048 - no no D 2 4 no no no no LQFP80 LPC4074 LPC4072 LPC408X_7X Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3.3 -- 16 October 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 6 of 138 LPC408x/7x NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller slave ARM CORTEX-M4 I-code bus LPC408x/7x FPU(1) TEST/DEBUG INTERFACE GPDMA CONTROLLER MPU EMULATION TRACE MODULE 5. Block diagram D-code bus system bus ETHERNET(1) master master USB DEVICE/ HOST(1)/OTG(1) CLOCK GENERATION, POWER CONTROL, SYSTEM FUNCTIONS clocks and controls master slave EMC(1) ROM slave slave LCD(1) MULTILAYER AHB MATRIX slave slave HIGH-SPEED GPIO SPIFI slave CRC APB slave group 0 slave slave AHB TO APB BRIDGE 0 SRAM 96/80/ 40/24 kB AHB TO APB BRIDGE 1 SSP1 slave FLASH ACCELERATOR FLASH 512/256/128/64 kB 4032 B/ 2048 B EEPROM APB slave group 1 SSP0/2 UART0/1 UART2/3 I2C0/1 USART4(1) CAN 0/1 I2C2 TIMER 0/1 SD/MMC(1) WINDOWED WDT TIMER2/3 PWM0/1 QUADRATURE ENCODER(1) 12-bit ADC DAC PIN CONNECT GPIO INTERRUPT CONTROL I2S MOTOR CONTROL PWM EVENT RECORDER 2 x ANALOG COMPARATOR(1) 32 kHz OSCILLATOR RTC SYSTEM CONTROL BACKUP REGISTERS = connected to GPDMA RTC POWER DOMAIN 002aag491 (1) Not available on all parts. Fig 1. Block diagram LPC408X_7X Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3.3 -- 16 October 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 7 of 138 LPC408x/7x NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller 6. Pinning information 156 105 6.1 Pinning 157 104 LPC408x/7x 53 1 52 208 Pin configuration (LQFP208) 73 108 Fig 2. 002aag732 109 72 LPC408x/7x 37 1 36 144 51 Pin configuration (LQFP144) 75 Fig 3. 002aag735 76 50 LPC407x Fig 4. LPC408X_7X Product data sheet 25 26 1 100 002aah638 Pin configuration (LQFP100) All information provided in this document is subject to legal disclaimers. Rev. 3.3 -- 16 October 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 8 of 138 LPC408x/7x NXP Semiconductors 41 60 32-bit ARM Cortex-M4 microcontroller 61 40 LPC408x/7x 21 1 20 80 Fig 5. 002aag865 Pin configuration (LQFP80) ball A1 index area 2 1 4 3 6 5 8 7 9 10 12 14 16 11 13 15 17 A B C D E F G H J LPC408x/7x K L M N P R T U 002aag733 Transparent top view Fig 6. LPC408X_7X Product data sheet Pin configuration (TFBGA208) All information provided in this document is subject to legal disclaimers. Rev. 3.3 -- 16 October 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 9 of 138 LPC408x/7x NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller ball A1 index area LPC408x/7x 1 2 3 4 5 6 7 8 9 10 11 12 13 14 A B C D E F G H J K L M N P 002aag734 Transparent top view Fig 7. Pin configuration (TFBGA180) ball A1 index area LPC4072FET80 1 2 3 4 5 6 7 8 9 10 A B C D E F G H J K 002aah684 Transparent top view Fig 8. Pin configuration (TFBGA80) 6.2 Pin description I/O pins on the LPC408x/7x are 5 V tolerant and have input hysteresis unless otherwise indicated in the table below. Crystal pins, power pins, and reference voltage pins are not 5 V tolerant. In addition, when pins are selected to be ADC inputs, they are no longer 5 V tolerant and the input voltage must be limited to the voltage at the ADC positive reference pin (VREFP). All port pins Pn[m] are multiplexed, and the multiplexed functions appear in Table 3 in the order defined by the FUNC bits of the corresponding IOCON register up to the highest used function number. Each port pin can support up to eight multiplexed functions. IOCON register FUNC values which are reserved are noted as "R" in the pin configuration table. LPC408X_7X Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3.3 -- 16 October 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 10 of 138 xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx NXP Semiconductors Reset state[1] P0[0] to P0[31] P0[0] Rev. 3.3 -- 16 October 2015 P0[2] P0[3] 96 202 204 U15 T14 C4 D6 M10 N11 D5 A3 66 67 141 142 46 47 98 99 37 38 79 80 J9 J10 A2 A1 [3] [3] [3] [3] I; PU I; PU I; PU I; PU Port 0: Port 0 is a 32-bit I/O port with individual direction controls for each bit. The operation of port 0 pins depends upon the pin function selected via the pin connect block. I/O P0[0] -- General purpose digital input/output pin. I CAN_RD1 -- CAN1 receiver input. O U3_TXD -- Transmitter output for UART3. I/O I2C1_SDA -- I2C1 data input/output (this pin does not use a specialized I2C pad). O U0_TXD -- Transmitter output for UART0. I/O P0[1] -- General purpose digital input/output pin. O CAN_TD1 -- CAN1 transmitter output. I U3_RXD -- Receiver input for UART3. I/O I2C1_SCL -- I2C1 clock input/output (this pin does not use a specialized I2C pad). I U0_RXD -- Receiver input for UART0. I/O P0[2] -- General purpose digital input/output pin. O U0_TXD -- Transmitter output for UART0. O U3_TXD -- Transmitter output for UART3. I/O P0[3] -- General purpose digital input/output pin. I U0_RXD -- Receiver input for UART0. I U3_RXD -- Receiver input for UART3. LPC408x/7x 11 of 138 (c) NXP Semiconductors N.V. 2015. All rights reserved. I/O 32-bit ARM Cortex-M4 microcontroller All information provided in this document is subject to legal disclaimers. P0[1] 94 Type[2] Description Pin TFBGA80 Pin LQFP80 Pin LQFP100 Pin LQFP144 Ball TFBGA180 Pin LQFP208 Symbol Ball TFBGA208 LPC408X_7X Product data sheet Table 3. Pin description Not all functions are available on all parts. See Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, comparator pins) and Table 5 (EMC pins). xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx Pin LQFP144 Pin LQFP100 Pin LQFP80 Pin TFBGA80 B12 A11 116 81 - - 166 C12 B11 115 80 - - [3] [3] I/O P0[4] -- General purpose digital input/output pin. I/O I2S_RX_SCK -- I2S Receive clock. It is driven by the master and received by the slave. Corresponds to the signal SCK in the I2S-bus specification. I CAN_RD2 -- CAN2 receiver input. I T2_CAP0 -- Capture input for Timer 2, channel 0. - R -- Function reserved. I/O CMP_ROSC -- Comparator relaxation oscillator for 555 timer applications. - R -- Function reserved. O LCD_VD[0] -- LCD data. I/O P0[5] -- General purpose digital input/output pin. I/O I2S_RX_WS -- I2S Receive word select. It is driven by the master and received by the slave. Corresponds to the signal WS in the I2S-bus specification. O CAN_TD2 -- CAN2 transmitter output. I T2_CAP1 -- Capture input for Timer 2, channel 1. - R -- Function reserved. I CMP_RESET -- Comparator reset. - R -- Function reserved. O LCD_VD[1] -- LCD data. I; PU LPC408x/7x I; PU 32-bit ARM Cortex-M4 microcontroller 12 of 138 (c) NXP Semiconductors N.V. 2015. All rights reserved. Type[2] Ball TFBGA180 168 Description Reset state[1] Rev. 3.3 -- 16 October 2015 All information provided in this document is subject to legal disclaimers. P0[5] Ball TFBGA208 P0[4] Pin LQFP208 Symbol NXP Semiconductors LPC408X_7X Product data sheet Table 3. Pin description ...continued Not all functions are available on all parts. See Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, comparator pins) and Table 5 (EMC pins). xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx Pin LQFP144 Pin LQFP100 Pin LQFP80 Pin TFBGA80 D13 D11 113 79 64 A7 162 C13 B12 112 78 63 A8 [3] [4] Type[2] Ball TFBGA180 164 Description Reset state[1] Rev. 3.3 -- 16 October 2015 I; PU I/O P0[6] -- General purpose digital input/output pin. I/O I2S_RX_SDA -- I2S Receive data. It is driven by the transmitter and read by the receiver. Corresponds to the signal SD in the I2S-bus specification. I/O SSP1_SSEL -- Slave Select for SSP1. O T2_MAT0 -- Match output for Timer 2, channel 0. O U1_RTS -- Request to Send output for UART1. Can also be configured to be an RS-485/EIA-485 output enable signal for UART1. I/O CMP_ROSC -- Comparator relaxation oscillator for 555 timer applications. - R -- Function reserved. O LCD_VD[8] -- LCD data. I; IA P0[7] -- General purpose digital input/output pin. I2S_TX_SCK -- I2S transmit clock. It is driven by the master and received by the slave. Corresponds to the signal SCK in the I2S-bus specification. I/O SSP1_SCK -- Serial Clock for SSP1. O T2_MAT1 -- Match output for Timer 2, channel 1. I RTC_EV0 -- Event input 0 to Event Monitor/Recorder. I CMP_VREF -- Comparator reference voltage. - R -- Function reserved. O LCD_VD[9] -- LCD data. LPC408x/7x 13 of 138 (c) NXP Semiconductors N.V. 2015. All rights reserved. I/O I/O 32-bit ARM Cortex-M4 microcontroller All information provided in this document is subject to legal disclaimers. P0[7] Ball TFBGA208 P0[6] Pin LQFP208 Symbol NXP Semiconductors LPC408X_7X Product data sheet Table 3. Pin description ...continued Not all functions are available on all parts. See Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, comparator pins) and Table 5 (EMC pins). xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx Pin LQFP144 Pin LQFP100 Pin LQFP80 Pin TFBGA80 A15 C12 111 77 62 A10 158 C14 A13 109 76 61 A9 [4] [4] Type[2] Ball TFBGA180 160 Description Reset state[1] Rev. 3.3 -- 16 October 2015 I; IA I/O P0[8] -- General purpose digital input/output pin. I/O I2S_TX_WS -- I2S Transmit word select. It is driven by the master and received by the slave. Corresponds to the signal WS in the I2S-bus specification. I/O SSP1_MISO -- Master In Slave Out for SSP1. O T2_MAT2 -- Match output for Timer 2, channel 2. I RTC_EV1 -- Event input 1 to Event Monitor/Recorder. I CMP1_IN[3] -- Comparator 1, input 3. - R -- Function reserved. I; IA O LCD_VD[16] -- LCD data. I/O P0[9] -- General purpose digital input/output pin. I/O I2S_TX_SDA -- I2S transmit data. It is driven by the transmitter and read by the receiver. Corresponds to the signal SD in the I2S-bus specification. I/O SSP1_MOSI -- Master Out Slave In for SSP1. O T2_MAT3 -- Match output for Timer 2, channel 3. I RTC_EV2 -- Event input 2 to Event Monitor/Recorder. I CMP1_IN[2] -- Comparator 1, input 2. - R -- Function reserved. O LCD_VD[17] -- LCD data. LPC408x/7x 14 of 138 (c) NXP Semiconductors N.V. 2015. All rights reserved. 32-bit ARM Cortex-M4 microcontroller All information provided in this document is subject to legal disclaimers. P0[9] Ball TFBGA208 P0[8] Pin LQFP208 Symbol NXP Semiconductors LPC408X_7X Product data sheet Table 3. Pin description ...continued Not all functions are available on all parts. See Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, comparator pins) and Table 5 (EMC pins). xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx Rev. 3.3 -- 16 October 2015 P0[12] Pin LQFP100 Pin LQFP80 Pin TFBGA80 L10 69 48 39 K9 100 41 R14 R1 P12 J4 70 29 49 - 40 - K10 - [3] [3] [5] Type[2] Pin LQFP144 T15 Reset state[1] Ball TFBGA180 98 Description I; PU I/O I; PU I; PU P0[10] -- General purpose digital input/output pin. U2_TXD -- Transmitter output for UART2. I/O I2C2_SDA -- I2C2 data input/output (this pin does not use a specialized I2C pad). O T3_MAT0 -- Match output for Timer 3, channel 0. - R -- Function reserved. - R -- Function reserved. - R -- Function reserved. O LCD_VD[5] -- LCD data. I/O P0[11] -- General purpose digital input/output pin. I U2_RXD -- Receiver input for UART2. I/O I2C2_SCL -- I2C2 clock input/output (this pin does not use a specialized I2C pad). O T3_MAT1 -- Match output for Timer 3, channel 1. - R -- Function reserved. - R -- Function reserved. - R -- Function reserved. O LCD_VD[10] -- LCD data. I/O P0[12] -- General purpose digital input/output pin. O USB_PPWR2 -- Port Power enable signal for USB port 2. I/O SSP1_MISO -- Master In Slave Out for SSP1. I ADC0_IN[6] -- A/D converter 0, input 6. When configured as an ADC input, the digital function of the pin must be disabled. LPC408x/7x 15 of 138 (c) NXP Semiconductors N.V. 2015. All rights reserved. O 32-bit ARM Cortex-M4 microcontroller All information provided in this document is subject to legal disclaimers. P0[11] Ball TFBGA208 P0[10] Pin LQFP208 Symbol NXP Semiconductors LPC408X_7X Product data sheet Table 3. Pin description ...continued Not all functions are available on all parts. See Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, comparator pins) and Table 5 (EMC pins). xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx Pin LQFP144 Pin LQFP100 Pin LQFP80 Pin TFBGA80 J5 32 - - - 69 128 T7 J16 M5 H13 48 89 - 62 - 47 - F9 [5] [3] [3] I; PU I/O P0[13] -- General purpose digital input/output pin. O USB_UP_LED2 -- USB port 2 GoodLink LED indicator. It is LOW when the device is configured (non-control endpoints enabled), or when the host is enabled and has detected a device on the bus. It is HIGH when the device is not configured, or when host is enabled and has not detected a device on the bus, or during global suspend. It transitions between LOW and HIGH (flashes) when the host is enabled and detects activity on the bus. I/O SSP1_MOSI -- Master Out Slave In for SSP1. I ADC0_IN[7] -- A/D converter 0, input 7. When configured as an ADC input, the digital function of the pin must be disabled. I/O P0[14] -- General purpose digital input/output pin. O USB_HSTEN2 -- Host Enabled status for USB port 2. I/O SSP1_SSEL -- Slave Select for SSP1. O USB_CONNECT2 -- SoftConnect control for USB port 2. Signal used to switch an external 1.5 k resistor under software control. Used with the SoftConnect USB feature. I/O P0[15] -- General purpose digital input/output pin. O U1_TXD -- Transmitter output for UART1. I/O SSP0_SCK -- Serial clock for SSP0. - R -- Function reserved. - R -- Function reserved. I/O SPIFI_IO[2] -- Data bit 0 for SPIFI. I; PU I; PU LPC408x/7x 16 of 138 (c) NXP Semiconductors N.V. 2015. All rights reserved. Type[2] Ball TFBGA180 R2 32-bit ARM Cortex-M4 microcontroller P0[15] 45 Description Reset state[1] Rev. 3.3 -- 16 October 2015 All information provided in this document is subject to legal disclaimers. P0[14] Ball TFBGA208 P0[13] Pin LQFP208 Symbol NXP Semiconductors LPC408X_7X Product data sheet Table 3. Pin description ...continued Not all functions are available on all parts. See Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, comparator pins) and Table 5 (EMC pins). xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx Rev. 3.3 -- 16 October 2015 P0[18] P0[19] Pin LQFP100 Pin LQFP80 Pin TFBGA80 H14 90 63 48 F8 126 124 122 K17 K15 L17 J12 J13 J10 87 86 85 61 60 59 46 45 - F10 G10 - [3] [3] [3] [3] Type[2] Pin LQFP144 J14 Reset state[1] Ball TFBGA180 130 Description I; PU I/O P0[16] -- General purpose digital input/output pin. I U1_RXD -- Receiver input for UART1. I/O SSP0_SSEL -- Slave Select for SSP0. - R -- Function reserved. - R -- Function reserved. I; PU I; PU I; PU I/O SPIFI_IO[3] -- Data bit 0 for SPIFI. I/O P0[17] -- General purpose digital input/output pin. I U1_CTS -- Clear to Send input for UART1. I/O SSP0_MISO -- Master In Slave Out for SSP0. - R -- Function reserved. - R -- Function reserved. I/O SPIFI_IO[1] -- Data bit 0 for SPIFI. I/O P0[18] -- General purpose digital input/output pin. I U1_DCD -- Data Carrier Detect input for UART1. I/O SSP0_MOSI -- Master Out Slave In for SSP0. - R -- Function reserved. - R -- Function reserved. SPIFI_IO[0] -- Data bit 0 for SPIFI. P0[19] -- General purpose digital input/output pin. I U1_DSR -- Data Set Ready input for UART1. O SD_CLK -- Clock output line for SD card interface. I/O I2C1_SDA -- I2C1 data input/output (this pin does not use a specialized I2C pad). - R -- Function reserved. - R -- Function reserved. - R -- Function reserved. O LCD_VD[13] -- LCD data. LPC408x/7x 17 of 138 (c) NXP Semiconductors N.V. 2015. All rights reserved. I/O I/O 32-bit ARM Cortex-M4 microcontroller All information provided in this document is subject to legal disclaimers. P0[17] Ball TFBGA208 P0[16] Pin LQFP208 Symbol NXP Semiconductors LPC408X_7X Product data sheet Table 3. Pin description ...continued Not all functions are available on all parts. See Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, comparator pins) and Table 5 (EMC pins). xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx Pin LQFP144 Pin LQFP100 Pin LQFP80 Pin TFBGA80 K14 83 58 - - 118 116 M16 N17 K11 L14 82 80 57 56 - 44 - H10 [3] [3] [6] I; PU I/O P0[20] -- General purpose digital input/output pin. O U1_DTR -- Data Terminal Ready output for UART1. Can also be configured to be an RS-485/EIA-485 output enable signal for UART1. I/O SD_CMD -- Command line for SD card interface. I/O I2C1_SCL -- I2C1 clock input/output (this pin does not use a specialized I2C pad). - R -- Function reserved. - R -- Function reserved. - R -- Function reserved. O LCD_VD[14] -- LCD data. I/O P0[21] -- General purpose digital input/output pin. I U1_RI -- Ring Indicator input for UART1. O SD_PWR -- Power Supply Enable for external SD card power supply. O U4_OE -- RS-485/EIA-485 output enable signal for UART4. I CAN_RD1 -- CAN1 receiver input. I/O U4_SCLK -- USART 4 clock input or output in synchronous mode. I/O P0[22] -- General purpose digital input/output pin. O U1_RTS -- Request to Send output for UART1. Can also be configured to be an RS-485/EIA-485 output enable signal for UART1. I/O SD_DAT[0] -- Data line 0 for SD card interface. O U4_TXD -- Transmitter output for USART4 (input/output in smart card mode). O CAN_TD1 -- CAN1 transmitter output. O SPIFI_CLK -- Clock output for SPIFI. I; PU I; PU LPC408x/7x Type[2] Ball TFBGA180 M17 32-bit ARM Cortex-M4 microcontroller 18 of 138 (c) NXP Semiconductors N.V. 2015. All rights reserved. P0[22] 120 Description Reset state[1] Rev. 3.3 -- 16 October 2015 All information provided in this document is subject to legal disclaimers. P0[21] Ball TFBGA208 P0[20] Pin LQFP208 Symbol NXP Semiconductors LPC408X_7X Product data sheet Table 3. Pin description ...continued Not all functions are available on all parts. See Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, comparator pins) and Table 5 (EMC pins). xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx Ball TFBGA180 Pin LQFP144 Pin LQFP100 Pin LQFP80 Pin TFBGA80 H1 F5 13 9 - - 16 14 G2 F1 E1 E4 11 10 8 7 - 7 - D1 [5] [5] [5] I/O P0[23] -- General purpose digital input/output pin. I ADC0_IN[0] -- A/D converter 0, input 0. When configured as an ADC input, the digital function of the pin must be disabled. I/O I2S_RX_SCK -- Receive Clock. It is driven by the master and received by the slave. Corresponds to the signal SCK in the I2S-bus specification. I T3_CAP0 -- Capture input for Timer 3, channel 0. I/O P0[24] -- General purpose digital input/output pin. I ADC0_IN[1] -- A/D converter 0, input 1. When configured as an ADC input, the digital function of the pin must be disabled. I/O I2S_RX_WS -- Receive Word Select. It is driven by the master and received by the slave. Corresponds to the signal WS in the I2S-bus specification. I T3_CAP1 -- Capture input for Timer 3, channel 1. I/O P0[25] -- General purpose digital input/output pin. I ADC0_IN[2] -- A/D converter 0, input 2. When configured as an ADC input, the digital function of the pin must be disabled. I/O I2S_RX_SDA -- Receive data. It is driven by the transmitter and read by the receiver. Corresponds to the signal SD in the I2S-bus specification. O U3_TXD -- Transmitter output for UART3. I; PU I; PU LPC408x/7x I; PU 32-bit ARM Cortex-M4 microcontroller 19 of 138 (c) NXP Semiconductors N.V. 2015. All rights reserved. Type[2] P0[25] 18 Description Reset state[1] Rev. 3.3 -- 16 October 2015 All information provided in this document is subject to legal disclaimers. P0[24] Ball TFBGA208 P0[23] Pin LQFP208 Symbol NXP Semiconductors LPC408X_7X Product data sheet Table 3. Pin description ...continued Not all functions are available on all parts. See Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, comparator pins) and Table 5 (EMC pins). xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx P0[31] P1[0] to P1[31] Ball TFBGA180 Pin LQFP144 Pin LQFP100 Pin LQFP80 Pin TFBGA80 8 6 6 D2 50 48 61 62 51 T1 R3 U4 R6 T2 L3 M1 K5 N4 N1 35 34 42 43 36 25 24 29 30 - - - 22 23 - - - J3 K3 - [7] [8] [8] [9] [9] [9] I; PU I/O P0[26] -- General purpose digital input/output pin. I ADC0_IN[3] -- A/D converter 0, input 3. When configured as an ADC input, the digital function of the pin must be disabled. O DAC_OUT -- D/A converter output. When configured as the DAC output, the digital function of the pin must be disabled. I U3_RXD -- Receiver input for UART3. I/O P0[27] -- General purpose digital input/output pin. I/O I2C0_SDA -- I2C0 data input/output. (This pin uses a specialized I2C pad). I/O USB_SDA1 -- I2C serial data for communication with an external USB transceiver. I/O P0[28] -- General purpose digital input/output pin. I/O I2C0_SCL -- I2C0 clock input/output (this pin uses a specialized I2C pad. I/O USB_SCL1 -- I2C serial clock for communication with an external USB transceiver. I/O P0[29] -- General purpose digital input/output pin. I/O USB_D+1 -- USB port 1 bidirectional D+ line. I EINT0 -- External interrupt 0 input. I/O P0[30] -- General purpose digital input/output pin. I/O USB_D1 -- USB port 1 bidirectional D line. I EINT1 -- External interrupt 1 input. I/O P0[31] -- General purpose digital input/output pin. I/O USB_D+2 -- USB port 2 bidirectional D+ line. I/O Port 1: Port 1 is a 32 bit I/O port with individual direction controls for each bit. The operation of port 1 pins depends upon the pin function selected via the pin connect block I I I I I LPC408x/7x 20 of 138 (c) NXP Semiconductors N.V. 2015. All rights reserved. P0[30] D1 32-bit ARM Cortex-M4 microcontroller P0[29] E1 Type[2] P0[28] 12 Description Reset state[1] Rev. 3.3 -- 16 October 2015 All information provided in this document is subject to legal disclaimers. P0[27] Ball TFBGA208 P0[26] Pin LQFP208 Symbol NXP Semiconductors LPC408X_7X Product data sheet Table 3. Pin description ...continued Not all functions are available on all parts. See Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, comparator pins) and Table 5 (EMC pins). xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx Rev. 3.3 -- 16 October 2015 P1[2] P1[3] Pin LQFP100 Pin LQFP80 Pin TFBGA80 136 95 76 A3 194 185 177 192 B5 D9 A10 A5 A5 B7 A9 C6 135 - - 133 94 - - 93 75 - - 74 B4 - - B5 [3] [3] [3] [3] [3] Type[2] Pin LQFP144 B5 Reset state[1] Ball TFBGA180 A3 I; PU I/O P1[0] -- General purpose digital input/output pin. O ENET_TXD0 -- Ethernet transmit data 0 (RMII/MII interface). - R -- Function reserved. I T3_CAP1 -- Capture input for Timer 3, channel 1. I; PU I; PU I; PU I; PU I/O SSP2_SCK -- Serial clock for SSP2. I/O P1[1] -- General purpose digital input/output pin. O ENET_TXD1 -- Ethernet transmit data 1 (RMII/MII interface). - R -- Function reserved. O T3_MAT3 -- Match output for Timer 3, channel 3. I/O SSP2_MOSI -- Master Out Slave In for SSP2. I/O P1[2] -- General purpose digital input/output pin. O ENET_TXD2 -- Ethernet transmit data 2 (MII interface). O SD_CLK -- Clock output line for SD card interface. O PWM0[1] -- Pulse Width Modulator 0, output 1. I/O P1[3] -- General purpose digital input/output pin. O ENET_TXD3 -- Ethernet transmit data 3 (MII interface). I/O SD_CMD -- Command line for SD card interface. O PWM0[2] -- Pulse Width Modulator 0, output 2. I/O P1[4] -- General purpose digital input/output pin. O ENET_TX_EN -- Ethernet transmit data enable (RMII/MII interface). - R -- Function reserved. O T3_MAT2 -- Match output for Timer 3, channel 2. I/O SSP2_MISO -- Master In Slave Out for SSP2. LPC408x/7x 21 of 138 (c) NXP Semiconductors N.V. 2015. All rights reserved. P1[4] 196 Description 32-bit ARM Cortex-M4 microcontroller All information provided in this document is subject to legal disclaimers. P1[1] Ball TFBGA208 P1[0] Pin LQFP208 Symbol NXP Semiconductors LPC408X_7X Product data sheet Table 3. Pin description ...continued Not all functions are available on all parts. See Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, comparator pins) and Table 5 (EMC pins). xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx P1[7] Pin LQFP144 Pin LQFP100 Pin LQFP80 Pin TFBGA80 B13 - - - - 171 153 D14 C7 B10 C13 B6 - - 132 - - 92 - - 73 - - C5 [3] [3] [3] I; PU I/O P1[5] -- General purpose digital input/output pin. O ENET_TX_ER -- Ethernet Transmit Error (MII interface). O SD_PWR -- Power Supply Enable for external SD card power supply. O PWM0[3] -- Pulse Width Modulator 0, output 3. - R -- Function reserved. I CMP1_IN[1] -- Comparator 1, input 1. I/O P1[6] -- General purpose digital input/output pin. I ENET_TX_CLK -- Ethernet Transmit Clock (MII interface). I/O SD_DAT[0] -- Data line 0 for SD card interface. O PWM0[4] -- Pulse Width Modulator 0, output 4. - R -- Function reserved. I; PU I; PU I; PU I CMP0_IN[3] -- Comparator 0, input 3. I/O P1[7] -- General purpose digital input/output pin. I ENET_COL -- Ethernet Collision detect (MII interface). I/O SD_DAT[1] -- Data line 1 for SD card interface. O PWM0[5] -- Pulse Width Modulator 0, output 5. - R -- Function reserved. I CMP1_IN[0] -- Comparator 1, input 0. I/O P1[8] -- General purpose digital input/output pin. I ENET_CRS (ENET_CRS_DV) -- Ethernet Carrier Sense (MII interface) or Ethernet Carrier Sense/Data Valid (RMII interface). - R -- Function reserved. O T3_MAT1 -- Match output for Timer 3, channel 1. I/O SSP2_SSEL -- Slave Select for SSP2. LPC408x/7x 190 B11 [3] Type[2] Ball TFBGA180 A17 32-bit ARM Cortex-M4 microcontroller 22 of 138 (c) NXP Semiconductors N.V. 2015. All rights reserved. P1[8] 156 Description Reset state[1] Rev. 3.3 -- 16 October 2015 All information provided in this document is subject to legal disclaimers. P1[6] Ball TFBGA208 P1[5] Pin LQFP208 Symbol NXP Semiconductors LPC408X_7X Product data sheet Table 3. Pin description ...continued Not all functions are available on all parts. See Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, comparator pins) and Table 5 (EMC pins). xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx P1[11] P1[12] Pin LQFP144 Pin LQFP100 Pin LQFP80 Pin TFBGA80 D7 131 91 72 A4 186 163 157 A14 A16 D16 A7 A12 A14 D14 129 - - - 90 - - - 71 - - - A5 - - - [3] [3] [3] [3] I; PU I/O P1[9] -- General purpose digital input/output pin. I ENET_RXD0 -- Ethernet receive data 0 (RMII/MII interface). - R -- Function reserved. O T3_MAT0 -- Match output for Timer 3, channel 0. I/O P1[10] -- General purpose digital input/output pin. I ENET_RXD1 -- Ethernet receive data 1 (RMII/MII interface). - R -- Function reserved. I; PU I; PU I; PU I; PU I T3_CAP0 -- Capture input for Timer 3, channel 0. I/O P1[11] -- General purpose digital input/output pin. I ENET_RXD2 -- Ethernet Receive Data 2 (MII interface). I/O SD_DAT[2] -- Data line 2 for SD card interface. O PWM0[6] -- Pulse Width Modulator 0, output 6. I/O P1[12] -- General purpose digital input/output pin. I ENET_RXD3 -- Ethernet Receive Data (MII interface). I/O SD_DAT[3] -- Data line 3 for SD card interface. I PWM0_CAP0 -- Capture input for PWM0, channel 0. - R -- Function reserved. O CMP1_OUT -- Comparator 1, output. I/O P1[13] -- General purpose digital input/output pin. I ENET_RX_DV -- Ethernet Receive Data Valid (MII interface). LPC408x/7x 147 C8 [3] Type[2] Ball TFBGA180 A6 32-bit ARM Cortex-M4 microcontroller 23 of 138 (c) NXP Semiconductors N.V. 2015. All rights reserved. P1[13] 188 Description Reset state[1] Rev. 3.3 -- 16 October 2015 All information provided in this document is subject to legal disclaimers. P1[10] Ball TFBGA208 P1[9] Pin LQFP208 Symbol NXP Semiconductors LPC408X_7X Product data sheet Table 3. Pin description ...continued Not all functions are available on all parts. See Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, comparator pins) and Table 5 (EMC pins). xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx Ball TFBGA180 Pin LQFP144 Pin LQFP100 Pin LQFP80 Pin TFBGA80 D8 128 89 70 C6 182 180 D10 A9 A8 B8 C9 126 125 123 88 87 86 69 - - B6 - - [3] [3] [3] I; PU I/O P1[14] -- General purpose digital input/output pin. I ENET_RX_ER -- Ethernet receive error (RMII/MII interface). - R -- Function reserved. I T2_CAP0 -- Capture input for Timer 2, channel 0. - R -- Function reserved. I CMP0_IN[0] -- Comparator 0, input 0. I/O P1[15] -- General purpose digital input/output pin. I ENET_RX_CLK (ENET_REF_CLK) -- Ethernet Receive Clock (MII interface) or Ethernet Reference Clock (RMII interface). - R -- Function reserved. I/O I2C2_SDA -- I2C2 data input/output (this pin does not use a specialized I2C pad). I/O P1[16] -- General purpose digital input/output pin. O ENET_MDC -- Ethernet MIIM clock. O I2S_TX_MCLK -- I2S transmit master clock. - R -- Function reserved. - R -- Function reserved. I CMP0_IN[1] -- Comparator 0, input 1. I/O P1[17] -- General purpose digital input/output pin. I; PU I; PU I; PU I/O ENET_MDIO -- Ethernet MIIM data input and output. O I2S_RX_MCLK -- I2S receive master clock. - R -- Function reserved. - R -- Function reserved. I CMP0_IN[2] -- Comparator 0, input 2. LPC408x/7x 178 A8 [3] 32-bit ARM Cortex-M4 microcontroller 24 of 138 (c) NXP Semiconductors N.V. 2015. All rights reserved. P1[17] A7 Type[2] P1[16] 184 Description Reset state[1] Rev. 3.3 -- 16 October 2015 All information provided in this document is subject to legal disclaimers. P1[15] Ball TFBGA208 P1[14] Pin LQFP208 Symbol NXP Semiconductors LPC408X_7X Product data sheet Table 3. Pin description ...continued Not all functions are available on all parts. See Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, comparator pins) and Table 5 (EMC pins). xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx Pin LQFP144 Pin LQFP100 Pin LQFP80 Pin TFBGA80 P7 L5 46 32 25 K4 68 U6 P5 47 33 26 J4 [3] [3] I/O P1[18] -- General purpose digital input/output pin. O USB_UP_LED1 -- It is LOW when the device is configured (non-control endpoints enabled), or when the host is enabled and has detected a device on the bus. It is HIGH when the device is not configured, or when host is enabled and has not detected a device on the bus, or during global suspend. It transitions between LOW and HIGH (flashes) when the host is enabled and detects activity on the bus. O PWM1[1] -- Pulse Width Modulator 1, channel 1 output. I T1_CAP0 -- Capture input for Timer 1, channel 0. - R -- Function reserved. I/O SSP1_MISO -- Master In Slave Out for SSP1. I/O P1[19] -- General purpose digital input/output pin. O USB_TX_E1 -- Transmit Enable signal for USB port 1 (OTG transceiver). O USB_PPWR1 -- Port Power enable signal for USB port 1. I T1_CAP1 -- Capture input for Timer 1, channel 1. O MC_0A -- Motor control PWM channel 0, output A. I/O SSP1_SCK -- Serial clock for SSP1. O U2_OE -- RS-485/EIA-485 output enable signal for UART2. I; PU LPC408x/7x I; PU 32-bit ARM Cortex-M4 microcontroller 25 of 138 (c) NXP Semiconductors N.V. 2015. All rights reserved. Type[2] Ball TFBGA180 66 Description Reset state[1] Rev. 3.3 -- 16 October 2015 All information provided in this document is subject to legal disclaimers. P1[19] Ball TFBGA208 P1[18] Pin LQFP208 Symbol NXP Semiconductors LPC408X_7X Product data sheet Table 3. Pin description ...continued Not all functions are available on all parts. See Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, comparator pins) and Table 5 (EMC pins). xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx Pin LQFP144 Pin LQFP100 Pin LQFP80 Pin TFBGA80 U7 K6 49 34 27 J5 72 R8 N6 50 35 - - [3] [3] I; PU I/O P1[20] -- General purpose digital input/output pin. O USB_TX_DP1 -- D+ transmit data for USB port 1 (OTG transceiver). O PWM1[2] -- Pulse Width Modulator 1, channel 2 output. I QEI_PHA -- Quadrature Encoder Interface PHA input. I MC_FB0 -- Motor control PWM channel 0 feedback input. I/O SSP0_SCK -- Serial clock for SSP0. O LCD_VD[6] -- LCD data. O LCD_VD[10] -- LCD data. I/O P1[21] -- General purpose digital input/output pin. O USB_TX_DM1 -- D transmit data for USB port 1 (OTG transceiver). O PWM1[3] -- Pulse Width Modulator 1, channel 3 output. I/O SSP0_SSEL -- Slave Select for SSP0. I MC_ABORT -- Motor control PWM, active low fast abort. - R -- Function reserved. O LCD_VD[7] -- LCD data. O LCD_VD[11] -- LCD data. I; PU LPC408x/7x 26 of 138 (c) NXP Semiconductors N.V. 2015. All rights reserved. 32-bit ARM Cortex-M4 microcontroller Type[2] Ball TFBGA180 70 Description Reset state[1] Rev. 3.3 -- 16 October 2015 All information provided in this document is subject to legal disclaimers. P1[21] Ball TFBGA208 P1[20] Pin LQFP208 Symbol NXP Semiconductors LPC408X_7X Product data sheet Table 3. Pin description ...continued Not all functions are available on all parts. See Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, comparator pins) and Table 5 (EMC pins). xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx Pin LQFP144 Pin LQFP100 Pin LQFP80 Pin TFBGA80 U8 M6 51 36 28 K5 76 P9 N7 53 37 29 H5 [3] [3] Type[2] Ball TFBGA180 74 Description Reset state[1] Rev. 3.3 -- 16 October 2015 I; PU I/O P1[22] -- General purpose digital input/output pin. I USB_RCV1 -- Differential receive data for USB port 1 (OTG transceiver). I USB_PWRD1 -- Power Status for USB port 1 (host power switch). O T1_MAT0 -- Match output for Timer 1, channel 0. O MC_0B -- Motor control PWM channel 0, output B. I/O SSP1_MOSI -- Master Out Slave In for SSP1. O LCD_VD[8] -- LCD data. I; PU O LCD_VD[12] -- LCD data. I/O P1[23] -- General purpose digital input/output pin. I USB_RX_DP1 -- D+ receive data for USB port 1 (OTG transceiver). O PWM1[4] -- Pulse Width Modulator 1, channel 4 output. I QEI_PHB -- Quadrature Encoder Interface PHB input. I MC_FB1 -- Motor control PWM channel 1 feedback input. I/O SSP0_MISO -- Master In Slave Out for SSP0. O LCD_VD[9] -- LCD data. O LCD_VD[13] -- LCD data. LPC408x/7x 27 of 138 (c) NXP Semiconductors N.V. 2015. All rights reserved. 32-bit ARM Cortex-M4 microcontroller All information provided in this document is subject to legal disclaimers. P1[23] Ball TFBGA208 P1[22] Pin LQFP208 Symbol NXP Semiconductors LPC408X_7X Product data sheet Table 3. Pin description ...continued Not all functions are available on all parts. See Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, comparator pins) and Table 5 (EMC pins). xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx Pin LQFP144 Pin LQFP100 Pin LQFP80 Pin TFBGA80 P7 54 38 30 J6 80 82 T10 R10 L7 P8 56 57 39 40 31 32 K6 H6 [3] [3] [3] Type[2] Ball TFBGA180 T9 I; PU I/O P1[24] -- General purpose digital input/output pin. I USB_RX_DM1 -- D receive data for USB port 1 (OTG transceiver). O PWM1[5] -- Pulse Width Modulator 1, channel 5 output. I QEI_IDX -- Quadrature Encoder Interface INDEX input. I MC_FB2 -- Motor control PWM channel 2 feedback input. I/O SSP0_MOSI -- Master Out Slave in for SSP0. O LCD_VD[10] -- LCD data. O LCD_VD[14] -- LCD data. I/O P1[25] -- General purpose digital input/output pin. O USB_LS1 -- Low Speed status for USB port 1 (OTG transceiver). O USB_HSTEN1 -- Host Enabled status for USB port 1. O T1_MAT1 -- Match output for Timer 1, channel 1. O MC_1A -- Motor control PWM channel 1, output A. O CLKOUT -- Selectable clock output. O LCD_VD[11] -- LCD data. I; PU I; PU LCD_VD[15] -- LCD data. P1[26] -- General purpose digital input/output pin. O USB_SSPND1 -- USB port 1 Bus Suspend status (OTG transceiver). O PWM1[6] -- Pulse Width Modulator 1, channel 6 output. I T0_CAP0 -- Capture input for Timer 0, channel 0. O MC_1B -- Motor control PWM channel 1, output B. I/O SSP1_SSEL -- Slave Select for SSP1. O LCD_VD[12] -- LCD data. O LCD_VD[20] -- LCD data. LPC408x/7x 28 of 138 (c) NXP Semiconductors N.V. 2015. All rights reserved. O I/O 32-bit ARM Cortex-M4 microcontroller P1[26] 78 Description Reset state[1] Rev. 3.3 -- 16 October 2015 All information provided in this document is subject to legal disclaimers. P1[25] Ball TFBGA208 P1[24] Pin LQFP208 Symbol NXP Semiconductors LPC408X_7X Product data sheet Table 3. Pin description ...continued Not all functions are available on all parts. See Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, comparator pins) and Table 5 (EMC pins). xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx Pin LQFP144 Pin LQFP100 Pin LQFP80 Pin TFBGA80 T12 M9 61 43 - - 90 T13 P10 63 44 35 J8 [3] [3] I; PU I/O P1[27] -- General purpose digital input/output pin. I USB_INT1 -- USB port 1 OTG transceiver interrupt (OTG transceiver). I USB_OVRCR1 -- USB port 1 Over-Current status. I T0_CAP1 -- Capture input for Timer 0, channel 1. O CLKOUT -- Selectable clock output. - R -- Function reserved. O LCD_VD[13] -- LCD data. O LCD_VD[21] -- LCD data. I/O P1[28] -- General purpose digital input/output pin. I/O USB_SCL1 -- USB port 1 I2C serial clock (OTG transceiver). I PWM1_CAP0 -- Capture input for PWM1, channel 0. O T0_MAT0 -- Match output for Timer 0, channel 0. O MC_2A -- Motor control PWM channel 2, output A. I/O SSP0_SSEL -- Slave Select for SSP0. O LCD_VD[14] -- LCD data. O LCD_VD[22] -- LCD data. I; PU LPC408x/7x 29 of 138 (c) NXP Semiconductors N.V. 2015. All rights reserved. 32-bit ARM Cortex-M4 microcontroller Type[2] Ball TFBGA180 88 Description Reset state[1] Rev. 3.3 -- 16 October 2015 All information provided in this document is subject to legal disclaimers. P1[28] Ball TFBGA208 P1[27] Pin LQFP208 Symbol NXP Semiconductors LPC408X_7X Product data sheet Table 3. Pin description ...continued Not all functions are available on all parts. See Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, comparator pins) and Table 5 (EMC pins). xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx Pin LQFP144 Pin LQFP100 Pin LQFP80 Pin TFBGA80 U14 N10 64 45 36 K8 42 P2 K3 30 21 18 J2 [3] [5] Type[2] Ball TFBGA180 92 Description Reset state[1] Rev. 3.3 -- 16 October 2015 I; PU I/O P1[29] -- General purpose digital input/output pin. I/O USB_SDA1 -- USB port 1 I2C serial data (OTG transceiver). I PWM1_CAP1 -- Capture input for PWM1, channel 1. O T0_MAT1 -- Match output for Timer 0, channel 1. O MC_2B -- Motor control PWM channel 2, output B. O U4_TXD -- Transmitter output for USART4 (input/output in smart card mode). O LCD_VD[15] -- LCD data. I; PU O LCD_VD[23] -- LCD data. I/O P1[30] -- General purpose digital input/output pin. I USB_PWRD2 -- Power Status for USB port 2. I USB_VBUS -- Monitors the presence of USB bus power. This signal must be HIGH for USB reset to occur. 40 P1 K2 28 20 17 H2 [5] I; PU ADC0_IN[4] -- A/D converter 0, input 4. When configured as an ADC input, the digital function of the pin must be disabled. I/O I2C0_SDA -- I2C0 data input/output (this pin does not use a specialized I2C pad. O U3_OE -- RS-485/EIA-485 output enable signal for UART3. I/O P1[31] -- General purpose digital input/output pin. I USB_OVRCR2 -- Over-Current status for USB port 2. I/O SSP1_SCK -- Serial Clock for SSP1. I ADC0_IN[5] -- A/D converter 0, input 5. When configured as an ADC input, the digital function of the pin must be disabled. I/O I2C0_SCL -- I2C0 clock input/output (this pin does not use a specialized I2C pad. LPC408x/7x 30 of 138 (c) NXP Semiconductors N.V. 2015. All rights reserved. P1[31] I 32-bit ARM Cortex-M4 microcontroller All information provided in this document is subject to legal disclaimers. P1[30] Ball TFBGA208 P1[29] Pin LQFP208 Symbol NXP Semiconductors LPC408X_7X Product data sheet Table 3. Pin description ...continued Not all functions are available on all parts. See Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, comparator pins) and Table 5 (EMC pins). xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx Reset state[1] P2[0] to P2[31] P2[0] Rev. 3.3 -- 16 October 2015 150 E14 D15 D12 C14 E11 107 106 105 75 74 73 60 59 58 B10 B8 B9 [3] [3] [3] I; PU I; PU I; PU Port 2: Port 2 is a 32 bit I/O port with individual direction controls for each bit. The operation of port 1 pins depends upon the pin function selected via the pin connect block. I/O P2[0] -- General purpose digital input/output pin. O PWM1[1] -- Pulse Width Modulator 1, channel 1 output. O U1_TXD -- Transmitter output for UART1. - R -- Function reserved. - R -- Function reserved. - R -- Function reserved. - R -- Function reserved. O LCD_PWR -- LCD panel power enable. I/O P2[1] -- General purpose digital input/output pin. O PWM1[2] -- Pulse Width Modulator 1, channel 2 output. I U1_RXD -- Receiver input for UART1. - R -- Function reserved. - R -- Function reserved. - R -- Function reserved. - R -- Function reserved. O LCD_LE -- Line end signal. I/O P2[2] -- General purpose digital input/output pin. O PWM1[3] -- Pulse Width Modulator 1, channel 3 output. I U1_CTS -- Clear to Send input for UART1. O T2_MAT3 -- Match output for Timer 2, channel 3. - R -- Function reserved. O TRACEDATA[3] -- Trace data, bit 3. - R -- Function reserved. O LCD_DCLK -- LCD panel clock. LPC408x/7x 31 of 138 (c) NXP Semiconductors N.V. 2015. All rights reserved. P2[2] 152 B17 I/O 32-bit ARM Cortex-M4 microcontroller All information provided in this document is subject to legal disclaimers. P2[1] 154 Type[2] Description Pin TFBGA80 Pin LQFP80 Pin LQFP100 Pin LQFP144 Ball TFBGA180 Ball TFBGA208 Pin LQFP208 Symbol NXP Semiconductors LPC408X_7X Product data sheet Table 3. Pin description ...continued Not all functions are available on all parts. See Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, comparator pins) and Table 5 (EMC pins). xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx Pin LQFP144 Pin LQFP100 Pin LQFP80 Pin TFBGA80 E16 E13 100 70 55 C10 142 D17 E14 99 69 54 C9 [3] [3] I; PU I/O P2[3] -- General purpose digital input/output pin. O PWM1[4] -- Pulse Width Modulator 1, channel 4 output. I U1_DCD -- Data Carrier Detect input for UART1. O T2_MAT2 -- Match output for Timer 2, channel 2. - R -- Function reserved. O TRACEDATA[2] -- Trace data, bit 2. - R -- Function reserved. O LCD_FP -- Frame pulse (STN). Vertical synchronization pulse (TFT). I/O P2[4] -- General purpose digital input/output pin. O PWM1[5] -- Pulse Width Modulator 1, channel 5 output. I U1_DSR -- Data Set Ready input for UART1. O T2_MAT1 -- Match output for Timer 2, channel 1. - R -- Function reserved. O TRACEDATA[1] -- Trace data, bit 1. - R -- Function reserved. O LCD_ENAB_M -- STN AC bias drive or TFT data enable output. I; PU LPC408x/7x 32 of 138 (c) NXP Semiconductors N.V. 2015. All rights reserved. 32-bit ARM Cortex-M4 microcontroller Type[2] Ball TFBGA180 144 Description Reset state[1] Rev. 3.3 -- 16 October 2015 All information provided in this document is subject to legal disclaimers. P2[4] Ball TFBGA208 P2[3] Pin LQFP208 Symbol NXP Semiconductors LPC408X_7X Product data sheet Table 3. Pin description ...continued Not all functions are available on all parts. See Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, comparator pins) and Table 5 (EMC pins). xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx Pin LQFP144 Pin LQFP100 Pin LQFP80 Pin TFBGA80 F16 F12 97 68 53 D10 138 E17 F13 96 67 52 E8 [3] [3] I; PU I/O P2[5] -- General purpose digital input/output pin. O PWM1[6] -- Pulse Width Modulator 1, channel 6 output. O U1_DTR -- Data Terminal Ready output for UART1. Can also be configured to be an RS-485/EIA-485 output enable signal for UART1. O T2_MAT0 -- Match output for Timer 2, channel 0. - R -- Function reserved. O TRACEDATA[0] -- Trace data, bit 0. - R -- Function reserved. O LCD_LP -- Line synchronization pulse (STN). Horizontal synchronization pulse (TFT). I/O P2[6] -- General purpose digital input/output pin. I PWM1_CAP0 -- Capture input for PWM1, channel 0. I U1_RI -- Ring Indicator input for UART1. I T2_CAP0 -- Capture input for Timer 2, channel 0. O U2_OE -- RS-485/EIA-485 output enable signal for UART2. O TRACECLK -- Trace clock. O LCD_VD[0] -- LCD data. O LCD_VD[4] -- LCD data. I; PU LPC408x/7x 33 of 138 (c) NXP Semiconductors N.V. 2015. All rights reserved. 32-bit ARM Cortex-M4 microcontroller Type[2] Ball TFBGA180 140 Description Reset state[1] Rev. 3.3 -- 16 October 2015 All information provided in this document is subject to legal disclaimers. P2[6] Ball TFBGA208 P2[5] Pin LQFP208 Symbol NXP Semiconductors LPC408X_7X Product data sheet Table 3. Pin description ...continued Not all functions are available on all parts. See Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, comparator pins) and Table 5 (EMC pins). xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx Pin LQFP144 Pin LQFP100 Pin LQFP80 Pin TFBGA80 G16 G11 95 66 51 D9 134 H15 G14 93 65 50 E9 [3] [3] Type[2] Ball TFBGA180 136 Description Reset state[1] Rev. 3.3 -- 16 October 2015 I; PU I/O P2[7] -- General purpose digital input/output pin. I CAN_RD2 -- CAN2 receiver input. O U1_RTS -- Request to Send output for UART1. Can also be configured to be an RS-485/EIA-485 output enable signal for UART1. - R -- Function reserved. - R -- Function reserved. O SPIFI_CS -- Chip select output for SPIFI. O LCD_VD[1] -- LCD data. I; PU O LCD_VD[5] -- LCD data. I/O P2[8] -- General purpose digital input/output pin. O CAN_TD2 -- CAN2 transmitter output. O U2_TXD -- Transmitter output for UART2. I U1_CTS -- Clear to Send input for UART1. O ENET_MDC -- Ethernet MIIM clock. - R -- Function reserved. O LCD_VD[2] -- LCD data. O LCD_VD[6] -- LCD data. LPC408x/7x 34 of 138 (c) NXP Semiconductors N.V. 2015. All rights reserved. 32-bit ARM Cortex-M4 microcontroller All information provided in this document is subject to legal disclaimers. P2[8] Ball TFBGA208 P2[7] Pin LQFP208 Symbol NXP Semiconductors LPC408X_7X Product data sheet Table 3. Pin description ...continued Not all functions are available on all parts. See Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, comparator pins) and Table 5 (EMC pins). xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx Pin LQFP144 Pin LQFP100 Pin LQFP80 Pin TFBGA80 H16 H11 92 64 49 E10 110 N15 M13 76 53 41 H9 [3] [10] Type[2] Ball TFBGA180 132 Description Reset state[1] Rev. 3.3 -- 16 October 2015 I; PU I/O P2[9] -- General purpose digital input/output pin. O USB_CONNECT1 -- USB1 SoftConnect control. Signal used to switch an external 1.5 k resistor under the software control. Used with the SoftConnect USB feature. I U2_RXD -- Receiver input for UART2. I U4_RXD -- Receiver input for USART4. I/O ENET_MDIO -- Ethernet MIIM data input and output. - R -- Function reserved. I LCD_VD[3] -- LCD data. I; PU I LCD_VD[7] -- LCD data. I/O P2[10] -- General purpose digital input/output pin. This pin includes a 10 ns input glitch filter. A LOW on this pin while RESET is LOW forces the on-chip boot loader to take over control of the part after a reset and go into ISP mode. P2[11] 108 T17 M12 75 52 - - [10] I; PU EINT0 -- External interrupt 0 input. I NMI -- Non-maskable interrupt input. I/O P2[11] -- General purpose digital input/output pin. This pin includes a 10 ns input glitch filter. I EINT1 -- External interrupt 1 input. I/O SD_DAT[1] -- Data line 1 for SD card interface. I/O I2S_TX_SCK -- Transmit Clock. It is driven by the master and received by the slave. Corresponds to the signal SCK in the I2S-bus specification. - R -- Function reserved. - R -- Function reserved. - R -- Function reserved. O LCD_CLKIN -- LCD clock. LPC408x/7x 35 of 138 (c) NXP Semiconductors N.V. 2015. All rights reserved. I 32-bit ARM Cortex-M4 microcontroller All information provided in this document is subject to legal disclaimers. P2[10] Ball TFBGA208 P2[9] Pin LQFP208 Symbol NXP Semiconductors LPC408X_7X Product data sheet Table 3. Pin description ...continued Not all functions are available on all parts. See Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, comparator pins) and Table 5 (EMC pins). xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx Pin LQFP144 Pin LQFP100 Pin LQFP80 Pin TFBGA80 N14 73 51 - - 102 R12 M11 - 71 - 50 - - - - - [10] [3] I; PU I/O P2[12] -- General purpose digital input/output pin. This pin includes a 10 ns input glitch filter. I EINT2 -- External interrupt 2 input. I/O SD_DAT[2] -- Data line 2 for SD card interface. I/O I2S_TX_WS -- Transmit Word Select. It is driven by the master and received by the slave. Corresponds to the signal WS in the I2S-bus specification. O LCD_VD[4] -- LCD data. O LCD_VD[3] -- LCD data. O LCD_VD[8] -- LCD data. O LCD_VD[18] -- LCD data. I/O P2[13] -- General purpose digital input/output pin. This pin includes a 10 ns input glitch filter. I; PU I; PU I EINT3 -- External interrupt 3 input. I/O SD_DAT[3] -- Data line 3 for SD card interface. I/O I2S_TX_SDA -- Transmit data. It is driven by the transmitter and read by the receiver. Corresponds to the signal SD in the I2S-bus specification. - R -- Function reserved. O LCD_VD[5] -- LCD data. O LCD_VD[9] -- LCD data. O LCD_VD[19] -- LCD data. I/O P2[14] -- General purpose digital input/output pin. O EMC_CS2 -- LOW active Chip Select 2 signal. I/O I2C1_SDA -- I2C1 data input/output (this pin does not use a specialized I2C pad). I T2_CAP0 -- Capture input for Timer 2, channel 0. LPC408x/7x 91 T16 [10] Type[2] Ball TFBGA180 N14 32-bit ARM Cortex-M4 microcontroller 36 of 138 (c) NXP Semiconductors N.V. 2015. All rights reserved. P2[14] 106 Description Reset state[1] Rev. 3.3 -- 16 October 2015 All information provided in this document is subject to legal disclaimers. P2[13] Ball TFBGA208 P2[12] Pin LQFP208 Symbol NXP Semiconductors LPC408X_7X Product data sheet Table 3. Pin description ...continued Not all functions are available on all parts. See Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, comparator pins) and Table 5 (EMC pins). xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx Rev. 3.3 -- 16 October 2015 Pin LQFP100 Pin LQFP80 Pin TFBGA80 - - - - - 87 R11 P9 - - - - [3] [3] Type[2] Pin LQFP144 P13 Reset state[1] Ball TFBGA180 99 Description I; PU I/O I; PU P2[15] -- General purpose digital input/output pin. O EMC_CS3 -- LOW active Chip Select 3 signal. I/O I2C1_SCL -- I2C1 clock input/output (this pin does not use a specialized I2C pad). I T2_CAP1 -- Capture input for Timer 2, channel 1. I/O P2[16] -- General purpose digital input/output pin. O EMC_CAS -- LOW active SDRAM Column Address Strobe. P2[17] -- General purpose digital input/output pin. P2[17] 95 R13 P11 - - - - [3] I; PU I/O O EMC_RAS -- LOW active SDRAM Row Address Strobe. P2[18] 59 U3 P3 - - - - [6] I; PU I/O P2[18] -- General purpose digital input/output pin. O EMC_CLK[0] -- SDRAM clock 0. I; PU I/O P2[19] -- General purpose digital input/output pin. O EMC_CLK[1] -- SDRAM clock 1. I; PU I/O P2[20] -- General purpose digital input/output pin. O EMC_DYCS0 -- SDRAM chip select 0. P2[21] -- General purpose digital input/output pin. 67 R7 N5 - - - - P2[20] 73 T8 P6 - - - - [3] I; PU I/O O EMC_DYCS1 -- SDRAM chip select 1. I; PU I/O P2[22] -- General purpose digital input/output pin. O EMC_DYCS2 -- SDRAM chip select 2. I/O SSP0_SCK -- Serial clock for SSP0. P2[21] 81 U11 N8 - - - - [3] P2[22] 85 U12 - - - - - [3] P2[23] 64 U5 - - - - - [3] I; PU I T3_CAP0 -- Capture input for Timer 3, channel 0. I/O P2[23] -- General purpose digital input/output pin. O EMC_DYCS3 -- SDRAM chip select 3. I/O SSP0_SSEL -- Slave Select for SSP0. I T3_CAP1 -- Capture input for Timer 3, channel 1. LPC408x/7x 37 of 138 (c) NXP Semiconductors N.V. 2015. All rights reserved. P2[19] [6] 32-bit ARM Cortex-M4 microcontroller All information provided in this document is subject to legal disclaimers. P2[16] Ball TFBGA208 P2[15] Pin LQFP208 Symbol NXP Semiconductors LPC408X_7X Product data sheet Table 3. Pin description ...continued Not all functions are available on all parts. See Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, comparator pins) and Table 5 (EMC pins). xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx Ball TFBGA180 Pin LQFP144 Pin LQFP100 Pin LQFP80 Pin TFBGA80 Reset state[1] Type[2] P2[24] 53 P5 P1 - - - - [3] I; PU I/O O EMC_CKE0 -- SDRAM clock enable 0. P2[25] 54 R4 P2 - - - - [3] I; PU I/O P2[25] -- General purpose digital input/output pin. O EMC_CKE1 -- SDRAM clock enable 1. - [3] I/O P2[26] -- General purpose digital input/output pin. O EMC_CKE2 -- SDRAM clock enable 2. I/O SSP0_MISO -- Master In Slave Out for SSP0. O T3_MAT0 -- Match output for Timer 3, channel 0. I/O P2[27] -- General purpose digital input/output pin. O EMC_CKE3 -- SDRAM clock enable 3. I/O SSP0_MOSI -- Master Out Slave In for SSP0. O T3_MAT1 -- Match output for Timer 3, channel 1. I/O P2[28] -- General purpose digital input/output pin. O EMC_DQM0 -- Data mask 0 used with SDRAM and static devices. I/O P2[29] -- General purpose digital input/output pin. O EMC_DQM1 -- Data mask 1 used with SDRAM and static devices. I/O P2[30] -- General purpose digital input/output pin. O EMC_DQM2 -- Data mask 2 used with SDRAM and static devices. I/O I2C2_SDA -- I2C2 data input/output (this pin does not use a specialized I2C pad). O T3_MAT2 -- Match output for Timer 3, channel 2. P2[26] Rev. 3.3 -- 16 October 2015 P2[28] P2[29] P2[30] 47 49 43 31 T4 P3 P4 N3 L4 - - M2 L1 - - - - - - - - - - - - - - - - - - - - [3] [3] [3] [3] I; PU I; PU I; PU I; PU I; PU 38 of 138 (c) NXP Semiconductors N.V. 2015. All rights reserved. 32-bit ARM Cortex-M4 microcontroller All information provided in this document is subject to legal disclaimers. P2[27] 57 P2[24] -- General purpose digital input/output pin. LPC408x/7x Ball TFBGA208 Description Pin LQFP208 Symbol NXP Semiconductors LPC408X_7X Product data sheet Table 3. Pin description ...continued Not all functions are available on all parts. See Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, comparator pins) and Table 5 (EMC pins). xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx Pin LQFP144 Pin LQFP100 Pin LQFP80 Pin TFBGA80 N2 - - - - - [3] Type[2] Ball TFBGA180 39 Description Reset state[1] Ball TFBGA208 P2[31] Pin LQFP208 Symbol I; PU I/O P2[31] -- General purpose digital input/output pin. O EMC_DQM3 -- Data mask 3 used with SDRAM and static devices. I/O I2C2_SCL -- I2C2 clock input/output (this pin does not use a specialized I2C pad). Rev. 3.3 -- 16 October 2015 P3[1] P3[2] P3[3] P3[4] P3[5] P3[7] P3[8] 201 207 3 13 17 23 27 191 B4 B3 B1 E4 F2 G1 J1 L1 D8 D6 E6 A2 G5 D3 E3 F4 G3 A6 137 140 144 2 9 12 16 19 - - - - [3] - [3] - [3] - [3] - [3] - [3] - [3] - [3] - [3] I; PU I; PU I; PU I; PU I; PU I; PU I; PU I; PU I; PU T3_MAT3 -- Match output for Timer 3, channel 3. Port 3: Port 3 is a 32-bit I/O port with individual direction controls for each bit. The operation of port 3 pins depends upon the pin function selected via the pin connect block. I/O P3[0] -- General purpose digital input/output pin. I/O EMC_D[0] -- External memory data line 0. I/O P3[1] -- General purpose digital input/output pin. I/O EMC_D[1] -- External memory data line 1. I/O P3[2] -- General purpose digital input/output pin. I/O EMC_D[2] -- External memory data line 2. I/O P3[3] -- General purpose digital input/output pin. I/O EMC_D[3] -- External memory data line 3. I/O P3[4] -- General purpose digital input/output pin. I/O EMC_D[4] -- External memory data line 4. I/O P3[5] -- General purpose digital input/output pin. I/O EMC_D[5] -- External memory data line 5. I/O P3[6] -- General purpose digital input/output pin. I/O EMC_D[6] -- External memory data line 6. I/O P3[7] -- General purpose digital input/output pin. I/O EMC_D[7] -- External memory data line 7. I/O P3[8] -- General purpose digital input/output pin. I/O EMC_D[8] -- External memory data line 8. LPC408x/7x 39 of 138 (c) NXP Semiconductors N.V. 2015. All rights reserved. P3[6] 197 O I/O 32-bit ARM Cortex-M4 microcontroller All information provided in this document is subject to legal disclaimers. P3[0] to P3[31] P3[0] NXP Semiconductors LPC408X_7X Product data sheet Table 3. Pin description ...continued Not all functions are available on all parts. See Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, comparator pins) and Table 5 (EMC pins). xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx Ball TFBGA180 Pin LQFP144 Pin LQFP100 Pin LQFP80 Pin TFBGA80 Reset state[1] Type[2] Rev. 3.3 -- 16 October 2015 P3[9] 199 C5 A4 - - - - [3] I; PU I/O P3[9] -- General purpose digital input/output pin. I/O EMC_D[9] -- External memory data line 9. P3[10] 205 B2 B3 - - - - [3] I; PU I/O P3[10] -- General purpose digital input/output pin. I/O EMC_D[10] -- External memory data line 10. I; PU I/O P3[11] -- General purpose digital input/output pin. I/O EMC_D[11] -- External memory data line 11. I; PU I/O P3[12] -- General purpose digital input/output pin. I/O EMC_D[12] -- External memory data line 12. P3[13] -- General purpose digital input/output pin. P3[11] 208 D5 B2 - - - - [3] P3[12] 1 D4 A1 - - - - [3] I; PU I/O I/O EMC_D[13] -- External memory data line 13. I; PU I/O P3[14] -- General purpose digital input/output pin. I/O EMC_D[14] -- External memory data line 14. P3[15] -- General purpose digital input/output pin. P3[13] 7 C1 C1 - - - - [3] P3[14] 21 H2 F1 - - - - [3] I; PU I/O I/O EMC_D[15] -- External memory data line 15. I; PU I/O P3[16] -- General purpose digital input/output pin. I/O EMC_D[16] -- External memory data line 16. O PWM0[1] -- Pulse Width Modulator 0, output 1. P3[15] 28 M1 G4 - - - - [3] P3[16] 137 F17 - - - - - [3] P3[17] 151 F15 C15 - - - - - - - - - - [3] [3] I; PU I; PU O U1_TXD -- Transmitter output for UART1. I/O P3[17] -- General purpose digital input/output pin. I/O EMC_D[17] -- External memory data line 17. O PWM0[2] -- Pulse Width Modulator 0, output 2. I U1_RXD -- Receiver input for UART1. I/O P3[18] -- General purpose digital input/output pin. I/O EMC_D[18] -- External memory data line 18. O PWM0[3] -- Pulse Width Modulator 0, output 3. I U1_CTS -- Clear to Send input for UART1. LPC408x/7x 40 of 138 (c) NXP Semiconductors N.V. 2015. All rights reserved. P3[18] 143 32-bit ARM Cortex-M4 microcontroller All information provided in this document is subject to legal disclaimers. Ball TFBGA208 Description Pin LQFP208 Symbol NXP Semiconductors LPC408X_7X Product data sheet Table 3. Pin description ...continued Not all functions are available on all parts. See Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, comparator pins) and Table 5 (EMC pins). xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx P3[22] Ball TFBGA180 Pin LQFP144 Pin LQFP100 Pin LQFP80 Pin TFBGA80 - - - - 167 175 195 65 58 A13 C10 C6 T6 R5 - - - M4 N3 - - - 45 40 - - - - - - - - - - - - - - - [3] [3] [3] [3] [3] [3] I; PU I/O P3[19] -- General purpose digital input/output pin. I/O EMC_D[19] -- External memory data line 19. O PWM0[4] -- Pulse Width Modulator 0, output 4. I U1_DCD -- Data Carrier Detect input for UART1. I/O P3[20] -- General purpose digital input/output pin. I/O EMC_D[20] -- External memory data line 20. O PWM0[5] -- Pulse Width Modulator 0, output 5. I U1_DSR -- Data Set Ready input for UART1. I/O P3[21] -- General purpose digital input/output pin. I/O EMC_D[21] -- External memory data line 21. O PWM0[6] -- Pulse Width Modulator 0, output 6. O U1_DTR -- Data Terminal Ready output for UART1. Can also be configured to be an RS-485/EIA-485 output enable signal for UART1. I/O P3[22] -- General purpose digital input/output pin. I/O EMC_D[22] -- External memory data line 22. I PWM0_CAP0 -- Capture input for PWM0, channel 0. I; PU I; PU I; PU I; PU I; PU I U1_RI -- Ring Indicator input for UART1. I/O P3[23] -- General purpose digital input/output pin. I/O EMC_D[23] -- External memory data line 23. I PWM1_CAP0 -- Capture input for PWM1, channel 0. I T0_CAP0 -- Capture input for Timer 0, channel 0. I/O P3[24] -- General purpose digital input/output pin. I/O EMC_D[24] -- External memory data line 24. O PWM1[1] -- Pulse Width Modulator 1, output 1. I T0_CAP1 -- Capture input for Timer 0, channel 1. LPC408x/7x 41 of 138 (c) NXP Semiconductors N.V. 2015. All rights reserved. P3[24] - 32-bit ARM Cortex-M4 microcontroller P3[23] B14 Type[2] Rev. 3.3 -- 16 October 2015 All information provided in this document is subject to legal disclaimers. P3[21] 161 Description Reset state[1] P3[20] Ball TFBGA208 P3[19] Pin LQFP208 Symbol NXP Semiconductors LPC408X_7X Product data sheet Table 3. Pin description ...continued Not all functions are available on all parts. See Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, comparator pins) and Table 5 (EMC pins). xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx Ball TFBGA180 Pin LQFP144 Pin LQFP100 Pin LQFP80 Pin TFBGA80 39 27 - - 55 203 5 11 T3 A1 D2 F3 K7 - - - 38 - - - 26 - - - - - - - - - - - [3] [3] [3] [3] [3] I; PU I/O P3[25] -- General purpose digital input/output pin. I/O EMC_D[25] -- External memory data line 25. O PWM1[2] -- Pulse Width Modulator 1, output 2. O T0_MAT0 -- Match output for Timer 0, channel 0. I/O P3[26] -- General purpose digital input/output pin. I/O EMC_D[26] -- External memory data line 26. O PWM1[3] -- Pulse Width Modulator 1, output 3. O T0_MAT1 -- Match output for Timer 0, channel 1. I STCLK -- System tick timer clock input. The maximum STCLK frequency is 1/4 of the ARM processor clock frequency CCLK. I/O P3[27] -- General purpose digital input/output pin. I/O EMC_D[27] -- External memory data line 27. O PWM1[4] -- Pulse Width Modulator 1, output 4. I T1_CAP0 -- Capture input for Timer 1, channel 0. I/O P3[28] -- General purpose digital input/output pin. I/O EMC_D[28] -- External memory data line 28. O PWM1[5] -- Pulse Width Modulator 1, output 5. I T1_CAP1 -- Capture input for Timer 1, channel 1. I/O P3[29] -- General purpose digital input/output pin. I/O EMC_D[29] -- External memory data line 29. O PWM1[6] -- Pulse Width Modulator 1, output 6. O T1_MAT0 -- Match output for Timer 1, channel 0. I; PU I; PU I; PU I; PU LPC408x/7x 42 of 138 (c) NXP Semiconductors N.V. 2015. All rights reserved. P3[29] M3 32-bit ARM Cortex-M4 microcontroller P3[28] U2 Type[2] Rev. 3.3 -- 16 October 2015 All information provided in this document is subject to legal disclaimers. P3[27] 56 Description Reset state[1] P3[26] Ball TFBGA208 P3[25] Pin LQFP208 Symbol NXP Semiconductors LPC408X_7X Product data sheet Table 3. Pin description ...continued Not all functions are available on all parts. See Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, comparator pins) and Table 5 (EMC pins). xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx Rev. 3.3 -- 16 October 2015 Pin LQFP100 Pin LQFP80 Pin TFBGA80 - - - - - 25 J3 - - - - P4[0] to P4[31] P4[0] P4[1] P4[2] P4[3] P4[5] P4[6] [3] I; PU I/O P3[30] -- General purpose digital input/output pin. I/O EMC_D[30] -- External memory data line 30. O U1_RTS -- Request to Send output for UART1. Can also be configured to be an RS-485/EIA-485 output enable signal for UART1. I; PU - 75 79 83 97 103 107 113 U9 U10 T11 U16 R15 R16 M14 L6 M7 M8 K9 P13 H10 K10 52 55 58 68 72 74 78 - - - [3] - [3] - [3] - [3] - [3] - [3] - [3] I; PU I; PU I; PU I; PU I; PU I; PU I; PU O T1_MAT1 -- Match output for Timer 1, channel 1. I/O P3[31] -- General purpose digital input/output pin. I/O EMC_D[31] -- External memory data line 31. - R -- Function reserved. O T1_MAT2 -- Match output for Timer 1, channel 2. I/O Port 4: Port 4 is a 32-bit I/O port with individual direction controls for each bit. The operation of port 4 pins depends upon the pin function selected via the pin connect block. I/O P4[0] -- General purpose digital input/output pin. I/O EMC_A[0] -- External memory address line 0. I/O P4[1] -- General purpose digital input/output pin. I/O EMC_A[1] -- External memory address line 1. I/O P4[2] -- General purpose digital input/output pin. I/O EMC_A[2] -- External memory address line 2. I/O P4[3] -- General purpose digital input/output pin. I/O EMC_A[3] -- External memory address line 3. I/O P4[4] -- General purpose digital input/output pin. I/O EMC_A[4] -- External memory address line 4. I/O P4[5] -- General purpose digital input/output pin. I/O EMC_A[5] -- External memory address line 5. I/O P4[6] -- General purpose digital input/output pin. I/O EMC_A[6] -- External memory address line 6. LPC408x/7x 43 of 138 (c) NXP Semiconductors N.V. 2015. All rights reserved. P4[4] - [3] Type[2] Pin LQFP144 H3 Reset state[1] Ball TFBGA180 19 Description 32-bit ARM Cortex-M4 microcontroller All information provided in this document is subject to legal disclaimers. P3[31] Ball TFBGA208 P3[30] Pin LQFP208 Symbol NXP Semiconductors LPC408X_7X Product data sheet Table 3. Pin description ...continued Not all functions are available on all parts. See Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, comparator pins) and Table 5 (EMC pins). xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx Ball TFBGA180 Pin LQFP144 Pin LQFP100 Pin LQFP80 Pin TFBGA80 Reset state[1] Type[2] Rev. 3.3 -- 16 October 2015 P4[7] 121 L16 K12 84 - - - [3] I; PU I/O P4[7] -- General purpose digital input/output pin. I/O EMC_A[7] -- External memory address line 7. P4[8] 127 J17 J11 88 - - - [3] I; PU I/O P4[8] -- General purpose digital input/output pin. I/O EMC_A[8] -- External memory address line 8. I; PU I/O P4[9] -- General purpose digital input/output pin. I/O EMC_A[9] -- External memory address line 9. I; PU I/O P4[10] -- General purpose digital input/output pin. I/O EMC_A[10] -- External memory address line 10. P4[9] 131 H17 H12 91 - - - [3] P4[10] 135 G17 G12 94 - - - [3] I; PU I/O P4[11] -- General purpose digital input/output pin. I/O EMC_A[11] -- External memory address line 11. I; PU I/O P4[12] -- General purpose digital input/output pin. I/O EMC_A[12] -- External memory address line 12. P4[13] -- General purpose digital input/output pin. P4[11] 145 F14 F11 101 - - - [3] P4[12] 149 C16 F10 104 - - - [3] I; PU I/O I/O EMC_A[13] -- External memory address line 13. I; PU I/O P4[14] -- General purpose digital input/output pin. I/O EMC_A[14] -- External memory address line 14. P4[15] -- General purpose digital input/output pin. 155 B16 B14 108 - - - P4[14] 159 B15 E8 110 - - - [3] I; PU I/O I/O EMC_A[15] -- External memory address line 15. I; PU I/O P4[16] -- General purpose digital input/output pin. I/O EMC_A[16] -- External memory address line 16. P4[17] -- General purpose digital input/output pin. P4[15] 173 A11 C10 120 - - - [3] P4[16] 101 U17 N12 - - - - [3] I; PU I/O I/O EMC_A[17] -- External memory address line 17. I; PU I/O P4[18] -- General purpose digital input/output pin. I/O EMC_A[18] -- External memory address line 18. I/O P4[19] -- General purpose digital input/output pin. I/O EMC_A[19] -- External memory address line 19. P4[17] 104 P14 N13 - - - - [3] P4[18] 105 P15 P14 - - - - [3] - [3] P4[19] 111 P16 M14 - - - I; PU LPC408x/7x 44 of 138 (c) NXP Semiconductors N.V. 2015. All rights reserved. P4[13] [3] 32-bit ARM Cortex-M4 microcontroller All information provided in this document is subject to legal disclaimers. Ball TFBGA208 Description Pin LQFP208 Symbol NXP Semiconductors LPC408X_7X Product data sheet Table 3. Pin description ...continued Not all functions are available on all parts. See Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, comparator pins) and Table 5 (EMC pins). xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx P4[23] Ball TFBGA180 Pin LQFP144 Pin LQFP100 Pin LQFP80 Pin TFBGA80 - - - - - 115 123 129 183 M15 K14 J15 B8 - - - C8 - - - 127 - - - - - - - - - - - [3] [3] [3] [3] - [3] 179 B9 D9 124 - - - P4[26] 119 L15 K13 - - - - [3] - [3] P4[27] 139 G15 F14 - - - I/O P4[20] -- General purpose digital input/output pin. I/O EMC_A[20] -- External memory address line 20. I/O I2C2_SDA -- I2C2 data input/output (this pin does not use a specialized I2C pad). I/O SSP1_SCK -- Serial Clock for SSP1. I/O P4[21] -- General purpose digital input/output pin. I/O EMC_A[21] -- External memory address line 21. I/O I2C2_SCL -- I2C2 clock input/output (this pin does not use a specialized I2C pad). I/O SSP1_SSEL -- Slave Select for SSP1. I/O P4[22] -- General purpose digital input/output pin. I/O EMC_A[22] -- External memory address line 22. O U2_TXD -- Transmitter output for UART2. I; PU I; PU I; PU I/O SSP1_MISO -- Master In Slave Out for SSP1. I/O P4[23] -- General purpose digital input/output pin. I/O EMC_A[23] -- External memory address line 23. I U2_RXD -- Receiver input for UART2. I/O SSP1_MOSI -- Master Out Slave In for SSP1. I/O P4[24] -- General purpose digital input/output pin. O EMC_OE -- LOW active Output Enable signal. I; PU I/O P4[25] -- General purpose digital input/output pin. O EMC_WE -- LOW active Write Enable signal. I; PU I/O P4[26] -- General purpose digital input/output pin. O EMC_BLS0 -- LOW active Byte Lane select signal 0. I/O P4[27] -- General purpose digital input/output pin. O EMC_BLS1 -- LOW active Byte Lane select signal 1. I; PU I; PU LPC408x/7x 45 of 138 (c) NXP Semiconductors N.V. 2015. All rights reserved. P4[25] [3] I; PU 32-bit ARM Cortex-M4 microcontroller P4[24] R17 Type[2] P4[22] 109 Description Reset state[1] Rev. 3.3 -- 16 October 2015 All information provided in this document is subject to legal disclaimers. P4[21] Ball TFBGA208 P4[20] Pin LQFP208 Symbol NXP Semiconductors LPC408X_7X Product data sheet Table 3. Pin description ...continued Not all functions are available on all parts. See Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, comparator pins) and Table 5 (EMC pins). xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx Rev. 3.3 -- 16 October 2015 P4[30] Pin LQFP100 Pin LQFP80 Pin TFBGA80 118 82 65 B7 176 187 193 B10 B7 A4 B9 C7 E7 122 130 134 85 - - 68 - - A6 - - [3] [3] [3] [3] Type[2] Pin LQFP144 D10 Reset state[1] Ball TFBGA180 C11 I; PU I/O I; PU I; PU I; PU P4[28] -- General purpose digital input/output pin. O EMC_BLS2 -- LOW active Byte Lane select signal 2. O U3_TXD -- Transmitter output for UART3. O T2_MAT0 -- Match output for Timer 2, channel 0. - R -- Function reserved. O LCD_VD[6] -- LCD data. O LCD_VD[10] -- LCD data. O LCD_VD[2] -- LCD data. I/O P4[29] -- General purpose digital input/output pin. O EMC_BLS3 -- LOW active Byte Lane select signal 3. I U3_RXD -- Receiver input for UART3. O T2_MAT1 -- Match output for Timer 2, channel 1. I/O I2C2_SCL -- I2C2 clock input/output (this pin does not use a specialized I2C pad). O LCD_VD[7] -- LCD data. O LCD_VD[11] -- LCD data. O LCD_VD[3] -- LCD data. I/O P4[30] -- General purpose digital input/output pin. O EMC_CS0 -- LOW active Chip Select 0 signal. - R -- Function reserved. - R -- Function reserved. - R -- Function reserved. O CMP0_OUT -- Comparator 0, output. I/O P4[31] -- General purpose digital input/output pin. O EMC_CS1 -- LOW active Chip Select 1 signal. LPC408x/7x 46 of 138 (c) NXP Semiconductors N.V. 2015. All rights reserved. P4[31] 170 Description 32-bit ARM Cortex-M4 microcontroller All information provided in this document is subject to legal disclaimers. P4[29] Ball TFBGA208 P4[28] Pin LQFP208 Symbol NXP Semiconductors LPC408X_7X Product data sheet Table 3. Pin description ...continued Not all functions are available on all parts. See Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, comparator pins) and Table 5 (EMC pins). xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx Reset state[1] P5[0] to P5[4] P5[0] Rev. 3.3 -- 16 October 2015 P5[2] P5[3] 30 117 141 F4 J4 L14 G14 E5 H1 L12 G10 6 21 81 98 - - - - - - - - - G1 - - [3] [3] [11] [11] I; PU I; PU I I Port 5: Port 5 is a 5-bit I/O port with individual direction controls for each bit. The operation of port 5 pins depends upon the pin function selected via the pin connect block. I/O P5[0] -- General purpose digital input/output pin. I/O EMC_A[24] -- External memory address line 24. I/O SSP2_MOSI -- Master Out Slave In for SSP2. O T2_MAT2 -- Match output for Timer 2, channel 2. I/O P5[1] -- General purpose digital input/output pin. I/O EMC_A[25] -- External memory address line 25. I/O SSP2_MISO -- Master In Slave Out for SSP2. O T2_MAT3 -- Match output for Timer 2, channel 3. I/O P5[2] -- General purpose digital input/output pin. - R -- Function reserved. I/O SSP2_SCK -- Serial clock for SSP2. When using this pin, the SSP2 bit rate is limited to 1 MHz. O T3_MAT2 -- Match output for Timer 3, channel 2. - R -- Function reserved. I/O I2C0_SDA -- I2C0 data input/output (this pin uses a specialized I2C pad that supports I2C Fast Mode Plus). I/O P5[3] -- General purpose digital input/output pin. - R -- Function reserved. I/O SSP2_SSEL -- Slave select for SSP2. When using this pin, the SSP2 bit rate is limited to 1 MHz. - R -- Function reserved. I U4_RXD -- Receiver input for USART4. I/O I2C0_SCL -- I2C0 clock input/output (this pin uses a specialized I2C pad that supports I2C Fast Mode Plus. LPC408x/7x 47 of 138 (c) NXP Semiconductors N.V. 2015. All rights reserved. I/O 32-bit ARM Cortex-M4 microcontroller All information provided in this document is subject to legal disclaimers. P5[1] 9 Type[2] Description Pin TFBGA80 Pin LQFP80 Pin LQFP100 Pin LQFP144 Ball TFBGA180 Ball TFBGA208 Pin LQFP208 Symbol NXP Semiconductors LPC408X_7X Product data sheet Table 3. Pin description ...continued Not all functions are available on all parts. See Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, comparator pins) and Table 5 (EMC pins). xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx Pin LQFP144 Pin LQFP100 Pin LQFP80 Pin TFBGA80 C3 C4 143 100 - - [3] Rev. 3.3 -- 16 October 2015 I; PU I/O P5[4] -- General purpose digital input/output pin. O U0_OE -- RS-485/EIA-485 output enable signal for UART0. - R -- Function reserved. O T3_MAT3 -- Match output for Timer 3, channel 3. O U4_TXD -- Transmitter output for USART4 (input/output in smart card mode). Test Data Out for JTAG interface. Also used as Serial wire trace output. JTAG_TDO (SWO) 2 D3 B1 1 1 1 B2 [3] O JTAG_TDI 4 C2 C3 3 2 2 B1 [3] I Test Data In for JTAG interface. JTAG_TMS (SWDIO) 6 E3 C2 4 3 3 C2 [3] I Test Mode Select for JTAG interface. Also used as Serial wire debug data input/output. JTAG_TRST 8 D1 D4 5 4 4 C1 [3] I Test Reset for JTAG interface. I Test Clock for JTAG interface. This clock must be slower than 1 /6 of the CPU clock (CCLK) for the JTAG interface to operate. Also used as serial wire clock. 10 E2 D2 7 5 5 D3 RESET 35 M2 J1 24 17 14 G3 [12] I External reset input with 20 ns glitch filter. A LOW-going pulse as short as 50 ns on this pin resets the device, causing I/O ports and peripherals to take on their default states, and processor execution to begin at address 0. This pin also serves as the debug select input. LOW level selects the JTAG boundary scan. HIGH level selects the ARM SWD debug mode. RSTOUT 29 K3 H2 20 14 11 F1 [3] O Reset status output. A LOW output on this pin indicates that the device is in the reset state for any reason. This reflects the RESET input pin and all internal reset sources. RTC_ALARM 37 N1 H5 26 - - - [13] O RTC controlled output. This is a 1.8 V pin. It goes HIGH when a RTC alarm is generated. RTCX1 34 K2 J2 23 16 13 F2 [14] I Input to the RTC 32 kHz ultra-low power oscillator circuit. [15] LPC408x/7x 48 of 138 (c) NXP Semiconductors N.V. 2015. All rights reserved. JTAG_TCK (SWDCLK) [3] 32-bit ARM Cortex-M4 microcontroller All information provided in this document is subject to legal disclaimers. Type[2] Ball TFBGA180 206 Description Reset state[1] Ball TFBGA208 P5[4] Pin LQFP208 Symbol NXP Semiconductors LPC408X_7X Product data sheet Table 3. Pin description ...continued Not all functions are available on all parts. See Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, comparator pins) and Table 5 (EMC pins). xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx Pin LQFP144 Pin LQFP100 Pin LQFP80 Pin TFBGA80 L2 J3 25 18 15 G2 [14] Type[2] Ball TFBGA180 36 Description Reset state[1] Ball TFBGA208 RTCX2 Pin LQFP208 Symbol O Output from the RTC 32 kHz ultra-low power oscillator circuit. I/O USB port 2 bidirectional D line. I RTC power supply: 3.3 V on this pin supplies power to the RTC. [15] [9] Rev. 3.3 -- 16 October 2015 U1 N2 37 - - - VBAT 38 M3 K1 27 19 16 H1 VDD(REG)(3V3) 26, 86, 174 H4, P11, D11 G1, 18, N9, E9 60, 121 13, 42, 34, 67 K7, C7 84 S 3.3 V regulator supply voltage: This is the power supply for the on-chip voltage regulator that supplies internal logic. VDDA 20 G4 F2 14 10 S Analog 3.3 V pad supply voltage: This can be connected to the same supply as VDD(3V3) but should be isolated to minimize noise and error. This voltage is used to power the ADC and DAC. Tie this pin to 3.3 V if the ADC and DAC are not used. VDD(3V3) 15, 60, 71, 89, 112, 125, 146, 165, 181, 198 G3, P6, P8, U13, P17, K16, C17, B13, C9, D7 E2, L4, K8, L11, J14, E12, E10, C5 41, 62, 77, 102, 114, 138 28, 54, 21, 42, K2, 71, 96 56, 77 H7, D8, C4 S 3.3 V supply voltage: This is the power supply voltage for I/O other than pins in the VBAT domain. VREFP 24 K1 G2 17 12 S ADC positive reference voltage: This should be the same voltage as VDDA, but should be isolated to minimize noise and error. The voltage level on this pin is used as a reference for ADC and DAC. Tie this pin to 3.3 V if the ADC and DAC are not used. 10 E3 E1 LPC408x/7x 49 of 138 (c) NXP Semiconductors N.V. 2015. All rights reserved. 52 32-bit ARM Cortex-M4 microcontroller All information provided in this document is subject to legal disclaimers. USB_D2 8 NXP Semiconductors LPC408X_7X Product data sheet Table 3. Pin description ...continued Not all functions are available on all parts. See Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, comparator pins) and Table 5 (EMC pins). xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx 44, 65, 79, 103, 117, 139 31, 55, 24, 43, H4, 72, 97 57, 78 G8, G9, B3 G Ground: 0 V reference for digital IO pins. VSSREG 32, 84, 172 D12, K4, P10 H3, L8, A10 22, 59, 119 15, 41, 33, 66 J7, F3 83 G Ground: 0 V reference for internal logic. VSSA 22 J2 F3 15 11 9 E2 G Analog ground: 0 V power supply and reference for the ADC and DAC. This should be the same voltage as VSS, but should be isolated to minimize noise and error. XTAL1 44 M4 L2 31 22 19 J1 I Input to the oscillator circuit and internal clock generator circuits. O Output from the oscillator amplifier. Reset state[1] [14] Type[2] H4, P4, L9, L13, G13, D13, C11, B4 Pin TFBGA80 Pin LQFP100 L3, T5, R9, P12, N16, H14, E15, A12, B6, A2 Pin LQFP80 Pin LQFP144 33, 63, 77, 93, 114, 133, 148, 169, 189, 200 Pin LQFP208 VSS [16] XTAL2 46 N4 K4 33 23 20 K1 [14] [16] DNC [1] - - - - - 12 - Do not connect. PU = internal pull-up enabled (for VDD(REG)(3V3) = 3.3 V, pulled up to 3.3 V); IA = inactive, no pull-up/down enabled; F = floating; floating pins, if not used, should be tied to ground or power to minimize power consumption. I = Input; O = Output; G = Ground; S = Supply. [3] 5 V tolerant pad providing digital I/O functions with TTL levels and hysteresis. [4] 5 V tolerant standard pad (5 V tolerant if VDD(3V3) present; if VDD(3V3) not present, do not exceed 3.6 V) providing digital I/O functions with TTL levels and hysteresis. This pad can be powered by VBAT. [5] 5 V tolerant pad providing digital I/O functions with TTL levels and hysteresis and analog input. When configured as a ADC input, digital section of the pad is disabled. [6] 5 V tolerant fast pad (5 V tolerant if VDD(3V3) present; if VDD(3V3) not present, do not exceed 3.6 V) providing digital I/O functions with TTL levels and hysteresis. [7] 5 V tolerant pad providing digital I/O with TTL levels and hysteresis and analog output function. When configured as the DAC output, digital section of the pad is disabled. [8] Open-drain 5 V tolerant digital I/O pad, compatible with I2C-bus 400 kHz specification. It requires an external pull-up to provide output functionality. When power is switched off, this pin connected to the I2C-bus is floating and does not disturb the I2C lines. Open-drain configuration applies to all functions on this pin. LPC408x/7x 50 of 138 (c) NXP Semiconductors N.V. 2015. All rights reserved. [2] 32-bit ARM Cortex-M4 microcontroller All information provided in this document is subject to legal disclaimers. Rev. 3.3 -- 16 October 2015 Ball TFBGA180 Description Ball TFBGA208 Symbol NXP Semiconductors LPC408X_7X Product data sheet Table 3. Pin description ...continued Not all functions are available on all parts. See Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, comparator pins) and Table 5 (EMC pins). LPC408x/7x NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller [9] Not 5 V tolerant. Pad provides digital I/O and USB functions. It is designed in accordance with the USB specification, revision 2.0 (Full-speed and Low-speed mode only). [10] 5 V tolerant pad with 5 ns glitch filter providing digital I/O functions with TTL levels and hysteresis. [11] Open-drain 5 V tolerant digital I/O pad, compatible with I2C-bus 1 MHz specification. It requires an external pull-up to provide output functionality. When power is switched off, this pin connected to the I2C-bus is floating and does not disturb the I2C lines. Open-drain configuration applies to all functions on this pin. [12] 5 V tolerant pad with 20 ns glitch filter providing digital I/O function with TTL levels and hysteresis. [13] This pad can be powered from VBAT. [14] Pad provides special analog functionality. A 32 kHz crystal oscillator must be used with the RTC. An external clock (32 kHz) can't be used to drive the RTCX1 pin. [15] If the RTC is not used, these pins can be left floating. [16] When the main oscillator is not used, connect XTAL1 and XTAL2 as follows: XTAL1 can be left floating or can be grounded (grounding is preferred to reduce susceptibility to noise). XTAL2 should be left floating. 7. Functional description 7.1 Architectural overview The ARM Cortex-M4 includes three AHB-Lite buses: the system bus, the I-code bus, and the D-code bus. The I-code and D-code core buses are faster than the system bus and are used similarly to Tightly Coupled Memory (TCM) interfaces: one bus dedicated for instruction fetch (I-code) and one bus for data access (D-code). The use of two core buses allows for simultaneous operations if concurrent operations target different devices. The LPC408x/7x use a multi-layer AHB matrix to connect the ARM Cortex-M4 buses and other bus masters to peripherals in a flexible manner that optimizes performance by allowing peripherals that are on different slaves ports of the matrix to be accessed simultaneously by different bus masters. 7.2 ARM Cortex-M4 processor The ARM Cortex-M4 processor is running at frequencies of up to 120 MHz. The processor executes the Thumb-2 instruction set for optimal performance and code size, including hardware division, single-cycle multiply, and bit-field manipulation. A Memory Protection Unit (MPU) supporting eight regions is included. 7.3 ARM Cortex-M4 Floating Point Unit (FPU) Remark: The FPU is available on parts LP4088/78/76. The FPU supports single-precision floating-point computation functionality in compliance with the ANSI/IEEE Standard 754-2008. The FPU provides add, subtract, multiply, divide, multiply and accumulate, and square root operations. It also performs a variety of conversions between fixed-point, floating-point, and integer data formats. 7.4 On-chip flash program memory The LPC408x/7x contain up to 512 kB of on-chip flash program memory. A new two-port flash accelerator maximizes performance for use with the two fast AHB-Lite buses. LPC408X_7X Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3.3 -- 16 October 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 51 of 138 LPC408x/7x NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller 7.5 EEPROM The LPC408x/7x contains up to 4032 byte of on-chip byte-erasable and byte-programmable EEPROM data memory. 7.6 On-chip SRAM The LPC408x/7x contain a total of up to 96 kB on-chip SRAM data memory. This includes 64 kB main SRAM, accessible by the CPU and DMA controller on a higher-speed bus, and up to two additional 16 kB peripheral SRAM blocks situated on a separate slave port on the AHB multilayer matrix. This architecture allows CPU and DMA accesses to be spread over three separate RAMs that can be accessed simultaneously. 7.7 Memory Protection Unit (MPU) The LPC408x/7x have a Memory Protection Unit (MPU) which can be used to improve the reliability of an embedded system by protecting critical data within the user application. The MPU allows separating processing tasks by disallowing access to each other's data, disabling access to memory regions, allowing memory regions to be defined as read-only and detecting unexpected memory accesses that could potentially break the system. The MPU separates the memory into distinct regions and implements protection by preventing disallowed accesses. The MPU supports up to eight regions each of which can be divided into eight subregions. Accesses to memory locations that are not defined in the MPU regions, or not permitted by the region setting, will cause the Memory Management Fault exception to take place. 7.8 Memory map Table 4. LPC408x/7x memory usage and details Address range General Use Address range details and description 0x0000 0000 to 0x1FFF FFFF On-chip non-volatile memory 0x0000 0000 to 0x0007 FFFF For devices with 512 kB of flash memory. 0x0000 0000 to 0x0003 FFFF For devices with 256 kB of flash memory. 0x0000 0000 to 0x0001 FFFF For devices with 128 kB of flash memory. 0x0000 0000 to 0x0000 FFFF For devices with 64 kB of flash memory. On-chip SRAM 0x2000 0000 to 0x3FFF FFFF 0x4000 0000 to 0x7FFF FFFF LPC408X_7X Product data sheet 0x1000 0000 to 0x1000 FFFF For devices with 64 kB of main SRAM. 0x1000 0000 to 0x1000 7FFF For devices with 32 kB of main SRAM. 0x1000 0000 to 0x1000 3FFF For devices with 16 kB of main SRAM. Boot ROM 0x1FFF 0000 to 0x1FFF 1FFF 8 kB Boot ROM with flash services. On-chip SRAM (typically used for peripheral data) 0x2000 0000 to 0x2000 1FFF Peripheral SRAM - bank 0 (first 8 kB) 0x2000 2000 to 0x2000 3FFF Peripheral SRAM - bank 0 (second 8 kB) 0x2000 4000 to 0x2000 7FFF Peripheral SRAM - bank 1 (16 kB) AHB peripherals 0x2008 0000 to 0x200B FFFF See Figure 9 for details APB Peripherals 0x4000 0000 to 0x4007 FFFF APB0 Peripherals, up to 32 peripheral blocks of 16 kB each. 0x4008 0000 to 0x400F FFFF APB1 Peripherals, up to 32 peripheral blocks of 16 kB each. All information provided in this document is subject to legal disclaimers. Rev. 3.3 -- 16 October 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 52 of 138 LPC408x/7x NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller Table 4. LPC408x/7x memory usage and details Address range General Use Address range details and description 0x8000 0000 to 0xDFFF FFFF Off-chip Memory via the External Memory Controller Four static memory chip selects: 0x8000 0000 to 0x83FF FFFF Static memory chip select 0 (up to 64 MB) 0x9000 0000 to 0x93FF FFFF Static memory chip select 1 (up to 64 MB) 0x9800 0000 to 0x9BFF FFFF Static memory chip select 2 (up to 64 MB) 0x9C00 0000 to 0x9FFF FFFF Static memory chip select 3 (up to 64 MB) Four dynamic memory chip selects: 0xA000 0000 to 0xAFFF FFFF Dynamic memory chip select 0 (up to 256 MB) 0xB000 0000 to 0xBFFF FFFF Dynamic memory chip select 1 (up to 256 MB) 0xC000 0000 to 0xCFFF FFFF Dynamic memory chip select 2 (up to 256 MB) 0xD000 0000 to 0xDFFF FFFF Dynamic memory chip select 3 (up to 256 MB) 0xE000 0000 to 0xE00F FFFF Cortex-M4 Private Peripheral Bus 0xE000 0000 to 0xE00F FFFF Cortex-M4 related functions, includes the NVIC and System Tick Timer. The LPC408x/7x incorporate several distinct memory regions, shown in the following figures. Figure 9 shows the overall map of the entire address space from the user program viewpoint following reset. The interrupt vector area supports address remapping. The AHB peripheral area is 2 MB in size, and is divided to allow for up to 128 peripherals. The APB peripheral area is 1 MB in size and is divided to allow for up to 64 peripherals. Each peripheral of either type is allocated 16 kB of space. This allows simplifying the address decoding for each peripheral. 7.9 Nested Vectored Interrupt Controller (NVIC) The NVIC is an integral part of the Cortex-M4. The tight coupling to the CPU allows for low interrupt latency and efficient processing of late arriving interrupts. 7.9.1 Features * * * * * * Controls system exceptions and peripheral interrupts. On the LPC408x/7x, the NVIC supports 40 vectored interrupts. 32 programmable interrupt priority levels, with hardware priority level masking. Relocatable vector table. Non-Maskable Interrupt (NMI). Software interrupt generation. 7.9.2 Interrupt sources Each peripheral device has one interrupt line connected to the NVIC but may have several interrupt flags. Individual interrupt flags may also represent more than one interrupt source. Any pin on port 0 and port 2 regardless of the selected function can be programmed to generate an interrupt on a rising edge, a falling edge, or both. LPC408X_7X Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3.3 -- 16 October 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 53 of 138 LPC408x/7x NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller 7.10 Pin connect block The pin connect block allows selected pins of the microcontroller to have more than one function. Configuration registers control the multiplexers to allow connection between the pin and the on-chip peripherals. Peripherals should be connected to the appropriate pins prior to being activated and prior to any related interrupts being enabled. Activity of any enabled peripheral function that is not mapped to a related pin should be considered undefined. Most pins can also be configured as open-drain outputs or to have a pull-up, pull-down, or no resistor enabled. 7.11 External Memory Controller (EMC) Remark: The EMC is available for parts LPC4088/78/76. Supported memory size and type and EMC bus width vary for different packages (see Table 2). The EMC pin configuration for each part is shown in Table 5. Table 5. External memory controller pin configuration Parts Data bus pins Address bus pins Control pins SRAM SDRAM LPC4088FBD208 EMC_D[31:0] LPC4088FET208 LPC4078FBD208 LPC4078FET208 EMC_A[25:0] EMC_BLS[3:0], EMC_CS[3:0], EMC_OE, EMC_WE EMC_RAS, EMC_CAS, EMC_DYCS[3:0], EMC_CLK[1:0], EMC_CKE[3:0], EMC_DQM[3:0] LPC4088FET180 LPC4078FET180 LPC4076FET180 EMC_A[19:0] EMC_BLS[1:0], EMC_CS[1:0], EMC_OE, EMC_WE EMC_RAS, EMC_CAS, EMC_DYCS[1:0], EMC_CLK[1:0], EMC_CKE[1:0], EMC_DQM[1:0] EMC_A[15:0] EMC_BLS[3:2], EMC_CS[1:0], EMC_OE, EMC_WE not available EMC_D[15:0] LPC4088FBD144 EMC_D[7:0] LPC4078FBD144 LPC4076FBD144 The LPC408x/7x EMC is an ARM PrimeCell MultiPort Memory Controller peripheral offering support for asynchronous static memory devices such as RAM, ROM, and flash. In addition, it can be used as an interface with off-chip memory-mapped devices and peripherals. The EMC is an Advanced Microcontroller Bus Architecture (AMBA) compliant peripheral. LPC408X_7X Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3.3 -- 16 October 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 54 of 138 xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx 4 GB LPC408x/7x system control reserved 30 - 17 reserved private peripheral bus 16 SD/MMC(1) reserved 15 QEI(1) 0x400B 8000 14 0x400B 4000 13 motor control PWM reserved 0x400B 0000 12 reserved 0x400A C000 11 SSP2 0x400A 8000 10 I2S 9 USART4(1) 0x400A 0000 8 I2C2 0x4009 C000 7 UART3 0x4009 8000 6 UART2 0x4009 4000 5 timer 3 0x4009 0000 4 timer 2 0x4008 C000 3 DAC 0x4008 8000 2 SSP0 0x400F C000 0x400C 0000 0x400B C000 0x400A 4000 Rev. 3.3 -- 16 October 2015 0x4004 4000 CAN common 0x4004 0000 15 CAN AF registers 14 CAN AF RAM 13 ADC 0x4003 4000 12 SSP1 0x4003 0000 11 pin connect 0x4002 C000 10 GPIO interrupts 0x4002 8000 9 RTC/event recorder + backup registers 0x4002 4000 8 reserved 7 I2C0 0x4001 C000 6 PWM1 0x4001 8000 5 PWM0 0x4001 4000 0x200A 0000 4 UART1 0x4001 0000 0x2008 0000 3 UART0 0x4000 C000 2 timer 1 0x4000 8000 0x4000 4000 8 kB peripheral SRAM0 (LPC4074/72) 1 0 timer 0 16 kB peripheral SRAM0 (LPC4088/78/76) 0x2000 8000 0x2000 4000 0x2000 2000 WWDT 0x4000 0000 0x2000 0000 reserved APB1 peripherals APB0 peripherals reserved SPIFI data reserved peripheral SRAM bit-band alias addressing reserved 16 kB peripheral SRAM1 (LPC4088/78) reserved 8 kB boot ROM reserved 64 kB main SRAM (LPC4088/78/76) 0x8000 0000 (1) Not available on all parts. See Table 2 and Table 4. LPC408x/7x memory map 32 kB main SRAM (LPC4074) 16 kB main SRAM (LPC4072) reserved 512 kB on-chip flash (LPC4078) 256 kB on-chip flash (LPC4076) 128 kB on- chip flash (LPC4074) 64 kB on- chip flash (LPC4072) 0x4200 0000 0x4010 0000 0x4008 0000 0x4000 0000 0x2900 0000 0x2800 0000 0x2400 0000 0x2200 0000 AHB peripherals 0x1FFF 2000 7 EMC registers 0x1FFF 0000 6 GPIO 0x1001 0000 0x1000 8000 0x1000 4000 0x1000 0000 0x0008 0000 0x0004 0000 0x0002 0000 0x0001 0000 0x0000 0000 5 reserved 4 CRC engine 3 USB(1) 2 LCD(1) 1 Ethernet(1) 0 GPDMA controller 0x4004 8000 0x4003 C000 0x4003 8000 0x4002 0000 0x200A 0000 0x2009 C000 0x2009 8000 0x2009 4000 0x2009 0000 0x2008 C000 0x2008 8000 0x2008 4000 0x2008 0000 002aag736 LPC408x/7x 55 of 138 (c) NXP Semiconductors N.V. 2015. All rights reserved. 0 GB 0x4004 C000 16 peripheral bit-band alias addressing active interrupt vectors 0x4005 C000 CAN1 0x4400 0000 + 256 words 0x4006 0000 17 reserved Fig 9. 0xE000 0000 reserved I-code/D-code memory space I2C1 22 - 19 reserved 0xA000 0000 0.5 GB 23 CAN2 AHB peripherals 0x0000 0000 0xE004 0000 0x4008 0000 18 EMC 4 x static chip select(1) 1 GB 31 - 24 reserved 0xE010 0000 EMC 4 x dynamic chip select(1) 1 - 0 reserved 0x0000 0400 APB0 peripherals 0xFFFF FFFF 32-bit ARM Cortex-M4 microcontroller All information provided in this document is subject to legal disclaimers. 0x4008 0000 31 NXP Semiconductors LPC408X_7X Product data sheet APB1 peripherals 0x4010 0000 LPC408x/7x NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller 7.11.1 Features * Dynamic memory interface support including single data rate SDRAM. * Asynchronous static memory device support including RAM, ROM, and flash, with or without asynchronous page mode. * * * * * Low transaction latency. Read and write buffers to reduce latency and to improve performance. 8/16/32 data and 16/20/26 address lines wide static memory support. 16 bit and 32 bit wide chip select SDRAM memory support. Static memory features include: - Asynchronous page mode read. - Programmable Wait States. - Bus turnaround delay. - Output enable and write enable delays. - Extended wait. * Four chip selects for synchronous memory and four chip selects for static memory devices. * Power-saving modes dynamically control EMC_CKE and EMC_CLK outputs to SDRAMs. * Dynamic memory self-refresh mode controlled by software. * Controller supports 2048 (A0 to A10), 4096 (A0 to A11), and 8192 (A0 to A12) row address synchronous memory parts. That is typical 512 MB, 256 MB, and 128 MB parts, with 4, 8, 16, or 32 data bits per device. * Separate reset domains allow the for auto-refresh through a chip reset if desired. Note: Synchronous static memory devices (synchronous burst mode) are not supported. 7.12 General purpose DMA controller The GPDMA is an AMBA AHB compliant peripheral allowing selected peripherals to have DMA support. The GPDMA enables peripheral-to-memory, memory-to-peripheral, peripheral-to-peripheral, and memory-to-memory transactions. The source and destination areas can each be either a memory region or a peripheral and can be accessed through the AHB master. The GPDMA controller allows data transfers between the various on-chip SRAM areas and supports the SD/MMC card interface, all SSPs, the I2S, all UARTs, the A/D Converter, and the D/A Converter peripherals. DMA can also be triggered by selected timer match conditions. Memory-to-memory transfers and transfers to or from GPIO are supported. 7.12.1 Features * Eight DMA channels. Each channel can support an unidirectional transfer. * 16 DMA request lines. LPC408X_7X Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3.3 -- 16 October 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 56 of 138 LPC408x/7x NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller * Single DMA and burst DMA request signals. Each peripheral connected to the DMA Controller can assert either a burst DMA request or a single DMA request. The DMA burst size is set by programming the DMA Controller. * Memory-to-memory, memory-to-peripheral, peripheral-to-memory, and peripheral-to-peripheral transfers are supported. * Scatter or gather DMA is supported through the use of linked lists. This means that the source and destination areas do not have to occupy contiguous areas of memory. * Hardware DMA channel priority. * AHB slave DMA programming interface. The DMA Controller is programmed by writing to the DMA control registers over the AHB slave interface. * One AHB bus master for transferring data. The interface transfers data when a DMA request goes active. * 32-bit AHB master bus width. * Incrementing or non-incrementing addressing for source and destination. * Programmable DMA burst size. The DMA burst size can be programmed to more efficiently transfer data. * Internal four-word FIFO per channel. * Supports 8, 16, and 32-bit wide transactions. * Big-endian and little-endian support. The DMA Controller defaults to little-endian mode on reset. * An interrupt to the processor can be generated on a DMA completion or when a DMA error has occurred. * Raw interrupt status. The DMA error and DMA count raw interrupt status can be read prior to masking. 7.13 CRC engine The Cyclic Redundancy Check (CRC) generator with programmable polynomial settings supports several CRC standards commonly used. To save system power and bus bandwidth, the CRC engine supports DMA transfers. 7.13.1 Features * Supports three common polynomials CRC-CCITT, CRC-16, and CRC-32. - CRC-CCITT: x16 + x12 + x5 + 1 - CRC-16: x16 + x15 + x2 + 1 - CRC-32: x32 + x26 + x23 + x22 + x16 + x12 + x11 + x10 + x8 + x7 + x5 + x4 + x2 + x + 1 * Bit order reverse and 1's complement programmable setting for input data and CRC sum. * Programmable seed number setting. * Supports CPU PIO or DMA back-to-back transfer. * Accept any size of data width per write: 8, 16 or 32-bit. - 8-bit write: 1-cycle operation. - 16-bit write: 2-cycle operation (8-bit x 2-cycle). - 32-bit write: 4-cycle operation (8-bit x 4-cycle). LPC408X_7X Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3.3 -- 16 October 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 57 of 138 LPC408x/7x NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller 7.14 LCD controller Remark: The LCD controller is available on parts LPC4088. The LCD controller provides all of the necessary control signals to interface directly to a variety of color and monochrome LCD panels. Both STN (single and dual panel) and TFT panels can be operated. The display resolution is selectable and can be up to 1024 768 pixels. Several color modes are provided, up to a 24-bit true-color non-palettized mode. An on-chip 512-byte color palette allows reducing bus utilization (i.e. memory size of the displayed data) while still supporting a large number of colors. The LCD interface includes its own DMA controller to allow it to operate independently of the CPU and other system functions. A built-in FIFO acts as a buffer for display data, providing flexibility for system timing. Hardware cursor support can further reduce the amount of CPU time needed to operate the display. 7.14.1 Features * * * * AHB master interface to access frame buffer. Setup and control via a separate AHB slave interface. Dual 16-deep programmable 64-bit wide FIFOs for buffering incoming display data. Supports single and dual-panel monochrome Super Twisted Nematic (STN) displays with 4-bit or 8-bit interfaces. * Supports single and dual-panel color STN displays. * Supports Thin Film Transistor (TFT) color displays. * Programmable display resolution including, but not limited to: 320 200, 320 240, 640 200, 640 240, 640 480, 800 600, and 1024 768. * * * * * * * * * * * * Hardware cursor support for single-panel displays. 15 gray-level monochrome, 3375 color STN, and 32 K color palettized TFT support. 1, 2, or 4 bits-per-pixel (bpp) palettized displays for monochrome STN. 1, 2, 4, or 8 bpp palettized color displays for color STN and TFT. 16 bpp true-color non-palettized, for color STN and TFT. 24 bpp true-color non-palettized, for color TFT. Programmable timing for different display panels. 256 entry, 16-bit palette RAM, arranged as a 128 32-bit RAM. Frame, line, and pixel clock signals. AC bias signal for STN, data enable signal for TFT panels. Supports little and big-endian, and Windows CE data formats. LCD panel clock may be generated from the peripheral clock, or from a clock input pin. 7.15 Ethernet Remark: The Ethernet block is available on parts LPC4088/78/76. The Ethernet block contains a full featured 10 Mbit/s or 100 Mbit/s Ethernet MAC designed to provide optimized performance through the use of DMA hardware acceleration. Features include a generous suite of control registers, half or full duplex LPC408X_7X Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3.3 -- 16 October 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 58 of 138 LPC408x/7x NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller operation, flow control, control frames, hardware acceleration for transmit retry, receive packet filtering and wake-up on LAN activity. Automatic frame transmission and reception with scatter-gather DMA off-loads many operations from the CPU. The Ethernet block and the CPU share the ARM Cortex-M4 D-code and system bus through the AHB-multilayer matrix to access the various on-chip SRAM blocks for Ethernet data, control, and status information. The Ethernet block interfaces between an off-chip Ethernet PHY using the Media Independent Interface (MII) or Reduced MII (RMII) protocol and the on-chip Media Independent Interface Management (MIIM) serial bus. 7.15.1 Features * Ethernet standards support: - Supports 10 Mbit/s or 100 Mbit/s PHY devices including 10 Base-T, 100 Base-TX, 100 Base-FX, and 100 Base-T4. - Fully compliant with IEEE standard 802.3. - Fully compliant with 802.3x Full Duplex Flow Control and Half Duplex back pressure. - Flexible transmit and receive frame options. - Virtual Local Area Network (VLAN) frame support. * Memory management: - Independent transmit and receive buffers memory mapped to shared SRAM. - DMA managers with scatter/gather DMA and arrays of frame descriptors. - Memory traffic optimized by buffering and pre-fetching. * Enhanced Ethernet features: - Receive filtering. - Multicast and broadcast frame support for both transmit and receive. - Optional automatic Frame Check Sequence (FCS) insertion with Circular Redundancy Check (CRC) for transmit. - Selectable automatic transmit frame padding. - Over-length frame support for both transmit and receive allows any length frames. - Promiscuous receive mode. - Automatic collision back-off and frame retransmission. - Includes power management by clock switching. - Wake-on-LAN power management support allows system wake-up: using the receive filters or a magic frame detection filter. * Physical interface: - Attachment of external PHY chip through standard MII or RMII interface. - PHY register access is available via the MIIM interface. LPC408X_7X Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3.3 -- 16 October 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 59 of 138 LPC408x/7x NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller 7.16 USB interface Remark: The USB Device/Host/OTG controller is available on parts LPC4088/78/76. The USB Device-only controller is available on part LPC4074/72. The Universal Serial Bus (USB) is a 4-wire bus that supports communication between a host and one or more (up to 127) peripherals. The host controller allocates the USB bandwidth to attached devices through a token-based protocol. The bus supports hot plugging and dynamic configuration of the devices. All transactions are initiated by the host controller. See Section 13.1 for details on typical USB interfacing solutions. 7.16.1 USB device controller The device controller enables 12 Mbit/s data exchange with a USB host controller. It consists of a register interface, serial interface engine, endpoint buffer memory, and a DMA controller. The serial interface engine decodes the USB data stream and writes data to the appropriate endpoint buffer. The status of a completed USB transfer or error condition is indicated via status registers. An interrupt is also generated if enabled. When enabled, the DMA controller transfers data between the endpoint buffer and the USB RAM. 7.16.1.1 Features * * * * * Fully compliant with USB 2.0 Specification (full speed). Supports 32 physical (16 logical) endpoints with a 4 kB endpoint buffer RAM. Supports Control, Bulk, Interrupt and Isochronous endpoints. Scalable realization of endpoints at run time. Endpoint Maximum packet size selection (up to USB maximum specification) by software at run time. * Supports SoftConnect and GoodLink features. * While USB is in the Suspend mode, the LPC408x/7x can enter one of the reduced power modes and wake up on USB activity. * Supports DMA transfers with all on-chip SRAM blocks on all non-control endpoints. * Allows dynamic switching between CPU-controlled and DMA modes. * Double buffer implementation for Bulk and Isochronous endpoints. 7.16.2 USB host controller The host controller enables full- and low-speed data exchange with USB devices attached to the bus. It consists of register interface, serial interface engine and DMA controller. The register interface complies with the Open Host Controller Interface (OHCI) specification. 7.16.2.1 Features * OHCI compliant. * Two downstream ports. * Supports per-port power switching. LPC408X_7X Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3.3 -- 16 October 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 60 of 138 LPC408x/7x NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller 7.16.3 USB OTG controller USB OTG is a supplement to the USB 2.0 Specification that augments the capability of existing mobile devices and USB peripherals by adding host functionality for connection to USB peripherals. The OTG Controller integrates the host controller, device controller, and a master-only I2C interface to implement OTG dual-role device functionality. The dedicated I2C interface controls an external OTG transceiver. 7.16.3.1 Features * Fully compliant with On-The-Go supplement to the USB 2.0 Specification, Revision 1.0a. * Hardware support for Host Negotiation Protocol (HNP). * Includes a programmable timer required for HNP and Session Request Protocol (SRP). * Supports any OTG transceiver compliant with the OTG Transceiver Specification (CEA-2011), Rev. 1.0. 7.17 SD/MMC card interface Remark: The SD/MMC card interface is available on parts LPC4088/78/76. The Secure Digital and Multimedia Card Interface (MCI) allows access to external SD memory cards. The SD card interface conforms to the SD Multimedia Card Specification Version 2.11. 7.17.1 Features * The MCI provides all functions specific to the SD/MMC memory card. These include the clock generation unit, power management control, and command and data transfer. * Conforms to Multimedia Card Specification v2.11. * Conforms to Secure Digital Memory Card Physical Layer Specification, v0.96. * Can be used as a multimedia card bus or a secure digital memory card bus host. The SD/MMC can be connected to several multimedia cards or a single secure digital memory card. * DMA supported through the GPDMA controller. 7.18 Fast general purpose parallel I/O Device pins that are not connected to a specific peripheral function are controlled by the GPIO registers. Pins may be dynamically configured as inputs or outputs. Separate registers allow setting or clearing any number of outputs simultaneously. The value of the output register may be read back as well as the current state of the port pins. LPC408x/7x use accelerated GPIO functions: * GPIO registers are accessed through the AHB multilayer bus so that the fastest possible I/O timing can be achieved. LPC408X_7X Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3.3 -- 16 October 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 61 of 138 LPC408x/7x NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller * Mask registers allow treating sets of port bits as a group, leaving other bits unchanged. * * * * All GPIO registers are byte and half-word addressable. Entire port value can be written in one instruction. Support for Cortex-M4 bit banding. Support for use with the GPDMA controller. Additionally, any pin on Port 0 and Port 2 providing a digital function can be programmed to generate an interrupt on a rising edge, a falling edge, or both. The edge detection is asynchronous, so it may operate when clocks are not present such as during Power-down mode. Each enabled interrupt can be used to wake up the chip from Power-down mode. 7.18.1 Features * Bit level set and clear registers allow a single instruction to set or clear any number of bits in one port. * Direction control of individual bits. * All I/O default to inputs after reset. * Pull-up/pull-down resistor configuration and open-drain configuration can be programmed through the pin connect block for each GPIO pin. 7.19 12-bit ADC The LPC408x/7x contain one ADC. It is a single 12-bit successive approximation ADC with eight channels and DMA support. 7.19.1 Features * * * * * * * * * * 12-bit successive approximation ADC. Input multiplexing among eight pins. Power-down mode. Measurement range VSS to VREFP. 12-bit conversion rate: up to 400 kHz. Individual channels can be selected for conversion. Burst conversion mode for single or multiple inputs. Optional conversion on transition of input pin or Timer Match signal. Individual result registers for each ADC channel to reduce interrupt overhead. DMA support. 7.20 10-bit DAC The LPC408x/7x contain one DAC. The DAC allows to generate a variable analog output. The maximum output value of the DAC is VREFP. 7.20.1 Features * 10-bit DAC. * Resistor string architecture. LPC408X_7X Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3.3 -- 16 October 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 62 of 138 LPC408x/7x NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller * * * * * Buffered output. Power-down mode. Selectable output drive. Dedicated conversion timer. DMA support. 7.21 Comparator Remark: The comparator is available on parts LPC4088/7876. Two embedded comparators are available to compare the voltage levels on external pins or against internal voltages. Up to four voltages on external pins and several internal reference voltages are selectable on each comparator. Additionally, two of the external inputs can be selected to drive an input common on both comparators. 7.21.1 Features * Up to five selectable external sources per comparator; fully configurable on either positive or negative comparator input channels. * 0.9 V internal band gap reference voltage selectable as either positive or negative input on each comparator. * 32-stage voltage ladder internal reference for selectable voltages on each comparator; configurable on either positive or negative comparator input. * Voltage ladder source voltage is selectable from an external pin or the 3.3 V analog voltage supply. * Voltage ladder can be separately powered down for applications only requiring the comparator function. * * * * Relaxation oscillator circuitry output, for a 555 style timer operation. Individual comparator outputs can be connected to I/O pins. Separate interrupt for each comparator. Edge and level comparator outputs connect to two timers allowing edge counting while a level match has been asserted or measuring the time between two voltage trip points. 7.22 UART0/1/2/3 and USART4 Remark: UART0/1/2/3 are available on all parts. USART4 is available on parts LPC4088/78/76. The LPC408x/7x contain five UARTs. In addition to standard transmit and receive data lines, UART1 also provides a full modem control handshake interface and support for RS-485/9-bit mode allowing both software address detection and automatic address detection using 9-bit mode. The UARTs include a fractional baud rate generator. Standard baud rates such as 115200 Bd can be achieved with any crystal frequency above 2 MHz. 7.22.1 Features * Maximum UART data bit rate of 7.5 MBit/s. LPC408X_7X Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3.3 -- 16 October 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 63 of 138 LPC408x/7x NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller * * * * 16 B Receive and Transmit FIFOs. Register locations conform to 16C550 industry standard. Receiver FIFO trigger points at 1 B, 4 B, 8 B, and 14 B. Built-in fractional baud rate generator covering wide range of baud rates without a need for external crystals of particular values. * Auto-baud capability. * Fractional divider for baud rate control, auto baud capabilities and FIFO control mechanism that enables software flow control implementation. * Support for RS-485/9-bit/EIA-485 mode and multiprocessor addressing. * All UARTs have DMA support for both transmit and receive. * UART1 equipped with standard modem interface signals. This module also provides full support for hardware flow control (auto-CTS/RTS). * USART4 includes an IrDA mode to support infrared communication. * USART4 supports synchronous mode and a smart card mode conforming to ISO7816-3. 7.23 SPIFI The SPI Flash Interface allows low-cost serial flash memories to be connected to the ARM Cortex-M4 processor with little performance penalty compared to parallel flash devices with higher pin count. The entire flash content is accessible as normal memory using byte, halfword, and word accesses by the processor and/or DMA channels. SPIFI provides sufficient flexibility to be compatible with common flash devices and includes extensions to help insure compatibility with future devices. 7.23.1 Features * Quad SPI Flash Interface (SPIFI) interface to external flash. * Transfer rates of up to SPIFI_CLK/2 bytes per second. * Code in the serial flash memory can be executed as if it was in the CPU's internal memory space. This is accomplished by mapping the external flash memory directly into the CPU memory space. * Supports 1-, 2-, and 4-bit bidirectional serial protocols. * Half-duplex protocol compatible with various vendors and devices. * Supported by a driver library available from NXP Semiconductors. 7.24 SSP serial I/O controller The LPC408x/7x contain three SSP controllers. The SSP controller is capable of operation on a SPI, 4-wire SSI, or Microwire bus. It can interact with multiple masters and slaves on the bus. Only a single master and a single slave can communicate on the bus during a given data transfer. The SSP supports full duplex transfers, with frames of 4 bits to 16 bits of data flowing from the master to the slave and from the slave to the master. In practice, often only one of these data flows carries meaningful data. LPC408X_7X Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3.3 -- 16 October 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 64 of 138 LPC408x/7x NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller 7.24.1 Features * Maximum SSP speed of 33 Mbit/s (master) or 10 Mbit/s (slave). * Compatible with Motorola SPI, 4-wire Texas Instruments SSI, and National Semiconductor Microwire buses. * * * * * Synchronous serial communication. Master or slave operation. 8-frame FIFOs for both transmit and receive. 4-bit to 16-bit frame. DMA transfers supported by GPDMA. 7.25 I2C-bus serial I/O controllers The LPC408x/7x contain three I2C-bus controllers. The I2C-bus is bidirectional for inter-IC control using only two wires: a Serial Clock Line (SCL) and a Serial Data Line (SDA). Each device is recognized by a unique address and can operate as either a receiver-only device (e.g., an LCD driver) or a transmitter with the capability to both receive and send information (such as memory). Transmitters and/or receivers can operate in either master or slave mode, depending on whether the chip has to initiate a data transfer or is only addressed. The I2C is a multi-master bus and can be controlled by more than one bus master connected to it. 7.25.1 Features * All I2C-bus controllers can use standard GPIO pins with bit rates of up to 400 kbit/s (Fast I2C-bus). The I2C0-bus interface uses special open-drain pins with bit rates of up to 400 kbit/s. * The I2C-bus interface supports Fast-mode Plus with bit rates up to 1 Mbit/s for I2C0 using pins P5[2] and P5[3]. * * * * * Easy to configure as master, slave, or master/slave. Programmable clocks allow versatile rate control. Bidirectional data transfer between masters and slaves. Multi-master bus (no central master). Arbitration between simultaneously transmitting masters without corruption of serial data on the bus. * Serial clock synchronization allows devices with different bit rates to communicate via one serial bus. * Serial clock synchronization can be used as a handshake mechanism to suspend and resume serial transfer. * The I2C-bus can be used for test and diagnostic purposes. * Both I2C-bus controllers support multiple address recognition and a bus monitor mode. 7.26 I2S-bus serial I/O controllers The LPC408x/7x contain one I2S-bus interface. The I2S-bus provides a standard communication interface for digital audio applications. LPC408X_7X Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3.3 -- 16 October 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 65 of 138 LPC408x/7x NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller The I2S-bus specification defines a 3-wire serial bus using one data line, one clock line, and one word select signal. The basic I2S connection has one master, which is always the master, and one slave. The I2S interface on the LPC408x/7x provides a separate transmit and receive channel, each of which can operate as either a master or a slave. 7.26.1 Features * The interface has separate input/output channels each of which can operate in master or slave mode. * Capable of handling 8-bit, 16-bit, and 32-bit word sizes. * Mono and stereo audio data supported. * The sampling frequency can range from 16 kHz to 48 kHz (16, 22.05, 32, 44.1, 48) kHz. * * * * Configurable word select period in master mode (separately for I2S input and output). Two 8 word FIFO data buffers are provided, one for transmit and one for receive. Generates interrupt requests when buffer levels cross a programmable boundary. Two DMA requests, controlled by programmable buffer levels. These are connected to the GPDMA block. * Controls include reset, stop and mute options separately for I2S input and I2S output. 7.27 CAN controller and acceptance filters The LPC408x/7x contain one CAN controller with two channels. The Controller Area Network (CAN) is a serial communications protocol which efficiently supports distributed real-time control with a very high level of security. Its domain of application ranges from high-speed networks to low cost multiplex wiring. The CAN block is intended to support multiple CAN buses simultaneously, allowing the device to be used as a gateway, switch, or router between two of CAN buses in industrial or automotive applications. Each CAN controller has a register structure similar to the NXP SJA1000 and the PeliCAN Library block, but the 8-bit registers of those devices have been combined in 32-bit words to allow simultaneous access in the ARM environment. The main operational difference is that the recognition of received Identifiers, known in CAN terminology as Acceptance Filtering, has been removed from the CAN controllers and centralized in a global Acceptance Filter. 7.27.1 Features * * * * * Dual-channel CAN controller and bus. Data rates to 1 Mbit/s on each bus. 32-bit register and RAM access. Compatible with CAN specification 2.0B, ISO 11898-1. Global Acceptance Filter recognizes 11-bit and 29-bit receive identifiers for all CAN buses. * Acceptance Filter can provide FullCAN-style automatic reception for selected Standard Identifiers. LPC408X_7X Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3.3 -- 16 October 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 66 of 138 LPC408x/7x NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller * FullCAN messages can generate interrupts. 7.28 General purpose 32-bit timers/external event counters The LPC408x/7x include four 32-bit timer/counters. The timer/counter is designed to count cycles of the system derived clock or an externally-supplied clock. It can optionally generate interrupts, generate timed DMA requests, or perform other actions at specified timer values, based on four match registers. Each timer/counter also includes two capture inputs to trap the timer value when an input signal transitions, optionally generating an interrupt. 7.28.1 Features * A 32-bit timer/counter with a programmable 32-bit prescaler. * Counter or timer operation. * Two 32-bit capture channels per timer, that can take a snapshot of the timer value when an input signal transitions. A capture event may also generate an interrupt. * Four 32-bit match registers that allow: - Continuous operation with optional interrupt generation on match. - Stop timer on match with optional interrupt generation. - Reset timer on match with optional interrupt generation. * Up to four external outputs corresponding to match registers, with the following capabilities: - Set LOW on match. - Set HIGH on match. - Toggle on match. - Do nothing on match. * Up to two match registers can be used to generate timed DMA requests. 7.29 Pulse Width Modulator (PWM) The LPC408x/7x contain two standard PWMs. The PWM is based on the standard Timer block and inherits all of its features, although only the PWM function is pinned out on the LPC408x/7x. The Timer is designed to count cycles of the system derived clock and optionally switch pins, generate interrupts or perform other actions when specified timer values occur, based on seven match registers. The PWM function is in addition to these features, and is based on match register events. The ability to separately control rising and falling edge locations allows the PWM to be used for more applications. For instance, multi-phase motor control typically requires three non-overlapping PWM outputs with individual control of all three pulse widths and positions. Two match registers can be used to provide a single edge controlled PWM output. One match register (PWMMR0) controls the PWM cycle rate, by resetting the count upon match. The other match register controls the PWM edge position. Additional single edge LPC408X_7X Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3.3 -- 16 October 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 67 of 138 LPC408x/7x NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller controlled PWM outputs require only one match register each, since the repetition rate is the same for all PWM outputs. Multiple single edge controlled PWM outputs will all have a rising edge at the beginning of each PWM cycle, when an PWMMR0 match occurs. Three match registers can be used to provide a PWM output with both edges controlled. Again, the PWMMR0 match register controls the PWM cycle rate. The other match registers control the two PWM edge positions. Additional double edge controlled PWM outputs require only two match registers each, since the repetition rate is the same for all PWM outputs. With double edge controlled PWM outputs, specific match registers control the rising and falling edge of the output. This allows both positive going PWM pulses (when the rising edge occurs prior to the falling edge), and negative going PWM pulses (when the falling edge occurs prior to the rising edge). 7.29.1 Features * LPC408x/7x has two PWM blocks with Counter or Timer operation (may use the peripheral clock or one of the capture inputs as the clock source). * Seven match registers allow up to 6 single edge controlled or 3 double edge controlled PWM outputs, or a mix of both types. The match registers also allow: - Continuous operation with optional interrupt generation on match. - Stop timer on match with optional interrupt generation. - Reset timer on match with optional interrupt generation. * Supports single edge controlled and/or double edge controlled PWM outputs. Single edge controlled PWM outputs all go high at the beginning of each cycle unless the output is a constant low. Double edge controlled PWM outputs can have either edge occur at any position within a cycle. This allows for both positive going and negative going pulses. * Pulse period and width can be any number of timer counts. This allows complete flexibility in the trade-off between resolution and repetition rate. All PWM outputs will occur at the same repetition rate. * Double edge controlled PWM outputs can be programmed to be either positive going or negative going pulses. * Match register updates are synchronized with pulse outputs to prevent generation of erroneous pulses. Software must `release' new match values before they can become effective. * May be used as a standard 32-bit timer/counter with a programmable 32-bit prescaler if the PWM mode is not enabled. 7.30 Motor control PWM The LPC408x/7x contain one motor control PWM. The motor control PWM is a specialized PWM supporting 3-phase motors and other combinations. Feedback inputs are provided to automatically sense rotor position and use that information to ramp speed up or down. An abort input is also provided that causes the PWM to immediately release all motor drive outputs. At the same time, the motor control PWM is highly configurable for other generalized timing, counting, capture, and compare applications. LPC408X_7X Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3.3 -- 16 October 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 68 of 138 LPC408x/7x NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller The maximum PWM speed is determined by the PWM resolution (n) and the operating frequency f: PWM speed = f/2n (see Table 6). Table 6. PWM speed at operating frequency 120 MHz PWM resolution PWM speed 6 bit 1.875 MHz 8 bit 0.468 MHz 10 bit 0.117 MHz 7.31 Quadrature Encoder Interface (QEI) Remark: The QEI is available on parts LPC4088/78/76. A quadrature encoder, also known as a 2-channel incremental encoder, converts angular displacement into two pulse signals. By monitoring both the number of pulses and the relative phase of the two signals, the user can track the position, direction of rotation, and velocity. In addition, a third channel, or index signal, can be used to reset the position counter. The quadrature encoder interface decodes the digital pulses from a quadrature encoder wheel to integrate position over time and determine direction of rotation. In addition, the QEI can capture the velocity of the encoder wheel. 7.31.1 Features * * * * * * * * * * Tracks encoder position. Increments/decrements depending on direction. Programmable for 2 or 4 position counting. Velocity capture using built-in timer. Velocity compare function with "less than" interrupt. Uses 32-bit registers for position and velocity. Three position compare registers with interrupts. Index counter for revolution counting. Index compare register with interrupts. Can combine index and position interrupts to produce an interrupt for whole and partial revolution displacement. * Digital filter with programmable delays for encoder input signals. * Can accept decoded signal inputs (clk and direction). * Connected to APB. 7.32 ARM Cortex-M4 system tick timer The ARM Cortex-M4 includes a system tick timer (SYSTICK) that is intended to generate a dedicated SYSTICK exception at a 10 ms interval. In the LPC408x/7x, this timer can be clocked from the internal AHB clock or from a device pin. 7.33 Windowed WatchDog Timer (WWDT) The purpose of the watchdog is to reset the controller if software fails to periodically service it within a programmable time window. LPC408X_7X Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3.3 -- 16 October 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 69 of 138 LPC408x/7x NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller 7.33.1 Features * Internally resets chip if not periodically reloaded during the programmable time-out period. * Optional windowed operation requires reload to occur between a minimum and maximum time period, both programmable. * Optional warning interrupt can be generated at a programmable time prior to watchdog time-out. * Enabled by software but requires a hardware reset or a watchdog reset/interrupt to be disabled. * * * * Incorrect feed sequence causes reset or interrupt if enabled. Flag to indicate watchdog reset. Programmable 24-bit timer with internal prescaler. Selectable time period from (Tcy(WDCLK) 256 4) to (Tcy(WDCLK) 224 4) in multiples of Tcy(WDCLK) 4. * The Watchdog Clock (WDCLK) source is a dedicated watchdog oscillator, which is always running if the watchdog timer is enabled. 7.34 RTC and backup registers The RTC is a set of counters for measuring time when system power is on, and optionally when it is off. The RTC on the LPC408x/7x is designed to have extremely low power consumption, i.e. less than 1 A. The RTC will typically run from the main chip power supply conserving battery power while the rest of the device is powered up. When operating from a battery, the RTC will continue working down to 2.1 V. Battery power can be provided from a standard 3 V lithium button cell. An ultra-low power 32 kHz oscillator will provide a 1 Hz clock to the time counting portion of the RTC, moving most of the power consumption out of the time counting function. The RTC includes a calibration mechanism to allow fine-tuning the count rate in a way that will provide less than 1 second per day error when operated at a constant voltage and temperature. The RTC contains a small set of backup registers (20 bytes) for holding data while the main part of the LPC408x/7x is powered off. The RTC includes an alarm function that can wake up the LPC408x/7x from all reduced power modes with a time resolution of 1 s. 7.34.1 Features * Measures the passage of time to maintain a calendar and clock. * Ultra low power design to support battery powered systems. * Provides Seconds, Minutes, Hours, Day of Month, Month, Year, Day of Week, and Day of Year. * Dedicated power supply pin can be connected to a battery or to the main 3.3 V. * Periodic interrupts can be generated from increments of any field of the time registers. * Backup registers (20 bytes) powered by VBAT. LPC408X_7X Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3.3 -- 16 October 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 70 of 138 LPC408x/7x NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller * RTC power supply is isolated from the rest of the chip. 7.35 Event monitor/recorder The event monitor/recorder allows recording of tampering events in sealed product enclosures. Sensors report any attempt to open the enclosure, or to tamper with the device in any other way. The event monitor/recorder stores records of such events when the device is powered only by the backup battery. 7.35.1 Features * Supports three digital event inputs in the VBAT power domain. * An event is defined as a level change at the digital event inputs. * For each event channel, two timestamps mark the first and the last occurrence of an event. Each channel also has a dedicated counter tracking the total number of events. Timestamp values are taken from the RTC. * Runs in VBAT power domain, independent of system power supply. The event/recorder/monitor can therefore operate in Deep power-down mode. * * * * Very low power consumption. Interrupt available if system is running. A qualified event can be used as a wake-up trigger. State of event interrupts accessible by software through GPIO. 7.36 Clocking and power control 7.36.1 Crystal oscillators The LPC408x/7x include four independent oscillators. These are the main oscillator, the IRC oscillator, the watchdog oscillator, and the RTC oscillator. Following reset, the LPC408x/7x will operate from the Internal RC oscillator until switched by software. This allows systems to operate without any external crystal and the boot loader code to operate at a known frequency. See Figure 10 for an overview of the LPC408x/7x clock generation. LPC408X_7X Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3.3 -- 16 October 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 71 of 138 LPC408x/7x NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller LPC408x/7x IRC oscillator MAIN PLL0 main oscillator (osc_clk) pll_clk sysclk CLKSRCSEL (system clock select) ALT PLL1 alt_pll_clk sysclk pll_clk CCLKSEL (CPU clock select) CPU CLOCK DIVIDER cclk PERIPHERAL CLOCK DIVIDER pclk EMC CLOCK DIVIDER emc_clk USB CLOCK DIVIDER usb_clk sysclk pll_clk alt_pll_clk USBCLKSEL (USB clock select) 002aag737 Fig 10. LPC408x/7x clock generation block diagram 7.36.1.1 Internal RC oscillator The IRC may be used as the clock that drives the PLL and subsequently the CPU. The nominal IRC frequency is 12 MHz. The IRC is trimmed to 1 % accuracy over the entire voltage and temperature range. Upon power-up or any chip reset, the LPC408x/7x use the IRC as the clock source. Software may later switch to one of the other available clock sources. 7.36.1.2 Main oscillator The main oscillator can be used as the clock source for the CPU, with or without using the PLL. The main oscillator also provides the clock source for the alternate PLL1. The main oscillator operates at frequencies of 1 MHz to 25 MHz. This frequency can be boosted to a higher frequency, up to the maximum CPU operating frequency, by the main PLL. The clock selected as the PLL input is PLLCLKIN. The ARM processor clock frequency is referred to as CCLK elsewhere in this document. The frequencies of PLLCLKIN and CCLK are the same value unless the PLL is active and connected. The clock frequency for each peripheral can be selected individually and is referred to as PCLK. Refer to Section 7.36.2 for additional information. LPC408X_7X Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3.3 -- 16 October 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 72 of 138 LPC408x/7x NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller 7.36.1.3 RTC oscillator The RTC oscillator provides a 1 Hz clock to the RTC and a 32 kHz clock output that can be output on the CLKOUT pin in order to allow trimming the RTC oscillator without interference from a probe. 7.36.1.4 Watchdog oscillator The Watchdog Timer has a dedicated oscillator that provides a 500 kHz clock to the Watchdog Timer that is always running if the Watchdog Timer is enabled. The Watchdog oscillator clock can be output on the CLKOUT pin in order to allow observe its frequency. In order to allow Watchdog Timer operation with minimum power consumption, which can be important in reduced power modes, the Watchdog oscillator frequency is not tightly controlled. The Watchdog oscillator frequency will vary over temperature and power supply within a particular part, and may vary by processing across different parts. This variation should be taken into account when determining Watchdog reload values. Within a particular part, temperature and power supply variations can produce up to a 17 % frequency variation. Frequency variation between devices under the same operating conditions can be up to 30 %. 7.36.2 Main PLL (PLL0) and Alternate PLL (PLL1) PLL0 (also called the Main PLL) and PLL1 (also called the Alternate PLL) are functionally identical but have somewhat different input possibilities and output connections. These possibilities are shown in Figure 10. The Main PLL can receive its input from either the IRC or the main oscillator and can potentially be used to provide the clocks to nearly everything on the device. The Alternate PLL receives its input only from the main oscillator and is intended to be used as an alternate source of clocking to the USB. The USB has timing needs that may not always be filled by the Main PLL. Both PLLs are disabled and powered off on reset. If the Alternate PLL is left disabled, the USB clock can be supplied by PLL0 if everything is set up to provide 48 MHz to the USB clock through that route. The source for each clock must be selected via the CLKSEL registers and can be further reduced by clock dividers as needed. PLL0 accepts an input clock frequency from either the IRC or the main oscillator. If only the Main PLL is used, then its output frequency must be an integer multiple of all other clocks needed in the system. PLL1 takes its input only from the main oscillator, requiring an external crystal in the range of 10 to 25 MHz. In each PLL, the Current Controlled Oscillator (CCO) operates in the range of 156 MHz to 320 MHz, so there are additional dividers to bring the output down to the desired frequencies. The minimum output divider value is 2, insuring that the output of the PLLs have a 50 % duty cycle. If the USB is used, the possibilities for the CPU clock and other clocks will be limited by the requirements that the frequency be precise and very low jitter, and that the PLL0 output must be a multiple of 48 MHz. Even multiples of 48 MHz that are within the operating range of the PLL are 192 MHz and 288 MHz. Also, only the main oscillator in conjunction with the PLL can meet the precision and jitter specifications for USB. It is due to these limitations that the Alternate PLL is provided. The alternate PLL accepts an input clock frequency from the main oscillator in the range of 10 MHz to 25 MHz only. When used as the USB clock, the input frequency is multiplied up to a multiple of 48 MHz (192 MHz or 288 MHz as described above). LPC408X_7X Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3.3 -- 16 October 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 73 of 138 LPC408x/7x NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller 7.36.3 Wake-up timer The LPC408x/7x begin operation at power-up and when awakened from Power-down mode by using the 12 MHz IRC oscillator as the clock source. This allows chip operation to resume quickly. If the main oscillator or the PLL is needed by the application, software will need to enable these features and wait for them to stabilize before they are used as a clock source. When the main oscillator is initially activated, the wake-up timer allows software to ensure that the main oscillator is fully functional before the processor uses it as a clock source and starts to execute instructions. This is important at power on, all types of reset, and whenever any of the aforementioned functions are turned off for any reason. Since the oscillator and other functions are turned off during Power-down mode, any wake-up of the processor from Power-down mode makes use of the wake-up Timer. The wake-up timer monitors the crystal oscillator to check whether it is safe to begin code execution. When power is applied to the chip, or when some event caused the chip to exit Power-down mode, some time is required for the oscillator to produce a signal of sufficient amplitude to drive the clock logic. The amount of time depends on many factors, including the rate of VDD(3V3) ramp (in the case of power on), the type of crystal and its electrical characteristics (if a quartz crystal is used), as well as any other external circuitry (e.g., capacitors), and the characteristics of the oscillator itself under the existing ambient conditions. 7.36.4 Power control The LPC408x/7x support a variety of power control features. There are four special modes of processor power reduction: Sleep mode, Deep-sleep mode, Power-down mode, and Deep power-down mode. The CPU clock rate may also be controlled as needed by changing clock sources, reconfiguring PLL values, and/or altering the CPU clock divider value. This allows a trade-off of power versus processing speed based on application requirements. In addition, the peripheral power control allows shutting down the clocks to individual on-chip peripherals, allowing fine tuning of power consumption by eliminating all dynamic power use in any peripherals that are not required for the application. Each of the peripherals has its own clock divider which provides even better power control. The integrated PMU (Power Management Unit) automatically adjusts internal regulators to minimize power consumption during Sleep, Deep-sleep, Power-down, and Deep power-down modes. The LPC408x/7x also implement a separate power domain to allow turning off power to the bulk of the device while maintaining operation of the RTC and a small set of registers for storing data during any of the power-down modes. 7.36.4.1 Sleep mode When Sleep mode is entered, the clock to the core is stopped. Resumption from the Sleep mode does not need any special sequence other than re-enabling the clock to the ARM core. In Sleep mode, execution of instructions is suspended until either a Reset or interrupt occurs. Peripheral functions continue operation during Sleep mode and may generate interrupts to cause the processor to resume execution. Sleep mode eliminates dynamic power used by the processor itself, memory systems and related controllers, and internal buses. LPC408X_7X Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3.3 -- 16 October 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 74 of 138 LPC408x/7x NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller The DMA controller can continue to work in Sleep mode and has access to the peripheral RAMs and all peripheral registers. The flash memory and the main SRAM are not available in Sleep mode, they are disabled in order to save power. Wake-up from Sleep mode will occur whenever any enabled interrupt occurs. 7.36.4.2 Deep-sleep mode In Deep-sleep mode, the oscillator is shut down and the chip receives no internal clocks. The processor state and registers, peripheral registers, and internal SRAM values are preserved throughout Deep-sleep mode and the logic levels of chip pins remain static. The output of the IRC is disabled but the IRC is not powered down to allow fast wake-up. The RTC oscillator is not stopped because the RTC interrupts may be used as the wake-up source. The PLL is automatically turned off and disconnected. The clock divider registers are automatically reset to zero. The Deep-sleep mode can be terminated and normal operation resumed by either a Reset or certain specific interrupts that are able to function without clocks. Since all dynamic operation of the chip is suspended, Deep-sleep mode reduces chip power consumption to a very low value. Power to the flash memory is left on in Deep-sleep mode, allowing a very quick wake-up. Wake-up from Deep-sleep mode can initiated by the NMI, External Interrupts EINT0 through EINT3, GPIO interrupts, the Ethernet Wake-on-LAN interrupt, Brownout Detect, an RTC Alarm interrupt, a USB input pin transition (USB activity interrupt), a CAN input pin transition, or a Watchdog Timer time-out, when the related interrupt is enabled. Wake-up will occur whenever any enabled interrupt occurs. On wake-up from Deep-sleep mode, the code execution and peripherals activities will resume after four cycles expire if the IRC was used before entering Deep-sleep mode. If the main external oscillator was used, the code execution will resume when 4096 cycles expire. PLL and clock dividers need to be reconfigured accordingly. 7.36.4.3 Power-down mode Power-down mode does everything that Deep-sleep mode does but also turns off the power to the IRC oscillator and the flash memory. This saves more power but requires waiting for resumption of flash operation before execution of code or data access in the flash memory can be accomplished. When the chip enters Power-down mode, the IRC, the main oscillator, and all clocks are stopped. The RTC remains running if it has been enabled and RTC interrupts may be used to wake up the CPU. The flash is forced into Power-down mode. The PLLs are automatically turned off and the clock selection multiplexers are set to use the system clock sysclk (the reset state). The clock divider control registers are automatically reset to zero. If the Watchdog timer is running, it will continue running in Power-down mode. On the wake-up of Power-down mode, if the IRC was used before entering Power-down mode, it will take IRC 60 s to start-up. After this four IRC cycles will expire before the code execution can then be resumed if the code was running from SRAM. In the meantime, the flash wake-up timer then counts 12 MHz IRC clock cycles to make the 100 s flash start-up time. When it times out, access to the flash will be allowed. Users need to reconfigure the PLL and clock dividers accordingly. LPC408X_7X Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3.3 -- 16 October 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 75 of 138 LPC408x/7x NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller 7.36.4.4 Deep power-down mode The Deep power-down mode can only be entered from the RTC block. In Deep power-down mode, power is shut off to the entire chip with the exception of the RTC module and the RESET pin. To optimize power conservation, the user has the additional option of turning off or retaining power to the 32 kHz oscillator. It is also possible to use external circuitry to turn off power to the on-chip regulator via the VDD(REG)(3V3) pins and/or the I/O power via the VDD(3V3) pins after entering Deep Power-down mode. Power must be restored before device operation can be restarted. The LPC408x/7x can wake up from Deep power-down mode via the RESET pin or an alarm match event of the RTC. 7.36.4.5 Wake-up Interrupt Controller (WIC) The WIC allows the CPU to automatically wake up from any enabled priority interrupt that can occur while the clocks are stopped in Deep-sleep, Power-down, and Deep power-down modes. The WIC works in connection with the Nested Vectored Interrupt Controller (NVIC). When the CPU enters Deep-sleep, Power-down, or Deep power-down mode, the NVIC sends a mask of the current interrupt situation to the WIC. This mask includes all of the interrupts that are both enabled and of sufficient priority to be serviced immediately. With this information, the WIC simply notices when one of the interrupts has occurred and then it wakes up the CPU. The WIC eliminates the need to periodically wake up the CPU and poll the interrupts resulting in additional power savings. 7.36.5 Peripheral power control A power control for peripherals feature allows individual peripherals to be turned off if they are not needed in the application, resulting in additional power savings. 7.36.6 Power domains The LPC408x/7x provide two independent power domains that allow the bulk of the device to have power removed while maintaining operation of the RTC and the backup registers. On the LPC408x/7x, I/O pads are powered by VDD(3V3), while VDD(REG)(3V3) powers the on-chip voltage regulator which in turn provides power to the CPU and most of the peripherals. Depending on the LPC408x/7x application, a design can use two power options to manage power consumption. The first option assumes that power consumption is not a concern and the design ties the VDD(3V3) and VDD(REG)(3V3) pins together. This approach requires only one 3.3 V power supply for both pads, the CPU, and peripherals. While this solution is simple, it does not support powering down the I/O pad ring "on the fly" while keeping the CPU and peripherals alive. LPC408X_7X Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3.3 -- 16 October 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 76 of 138 LPC408x/7x NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller The second option uses two power supplies; a 3.3 V supply for the I/O pads (VDD(3V3)) and a dedicated 3.3 V supply for the CPU (VDD(REG)(3V3)). Having the on-chip voltage regulator powered independently from the I/O pad ring enables shutting down of the I/O pad power supply "on the fly" while the CPU and peripherals stay active. The VBAT pin supplies power only to the RTC domain. The RTC requires a minimum of power to operate, which can be supplied by an external battery. The device core power (VDD(REG)(3V3)) is used to operate the RTC whenever VDD(REG)(3V3) is present. There is no power drain from the RTC battery when VDD(REG)(3V3) is available and VDD(REG)(3V3) > VBAT. LPC408x/7x VDD(3V3) to I/O pads to core VSS VDD(REG)(3V3) (typical 3.3 V) REGULATOR to memories, peripherals, oscillators, PLLs MAIN POWER DOMAIN VBAT (typical 3.0 V) POWER SELECTOR ULTRA-LOW POWER REGULATOR BACKUP REGISTERS RTCX1 RTCX2 32 kHz OSCILLATOR REAL-TIME CLOCK RTC POWER DOMAIN DAC VDDA VREFP ADC VSSA ADC POWER DOMAIN 002aag738 Fig 11. Power distribution LPC408X_7X Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3.3 -- 16 October 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 77 of 138 LPC408x/7x NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller 7.37 System control 7.37.1 Reset Reset has four sources on the LPC408x/7x: the RESET pin, the Watchdog reset, Power-On Reset (POR), and the BrownOut Detection (BOD) circuit. The RESET pin is a Schmitt trigger input pin. Assertion of chip Reset by any source, once the operating voltage attains a usable level, starts the Wake-up timer (see description in Section 7.36.3), causing reset to remain asserted until the external Reset is de-asserted, the oscillator is running, a fixed number of clocks have passed, and the flash controller has completed its initialization. When the internal Reset is removed, the processor begins executing at address 0, which is initially the Reset vector mapped from the boot block. At that point, all of the processor and peripheral registers have been initialized to predetermined values. 7.37.2 Brownout detection The LPC408x/7x include 2-stage monitoring of the voltage on the VDD(REG)(3V3) pins. If this voltage falls below 2.2 V (typical), the BOD asserts an interrupt signal to the Vectored Interrupt Controller. This signal can be enabled for interrupt in the Interrupt Enable Register in the NVIC in order to cause a CPU interrupt; if not, software can monitor the signal by reading a dedicated status register. The second stage of low-voltage detection asserts reset to inactivate the LPC408x/7x when the voltage on the VDD(REG)(3V3) pins falls below 1.85 V (typical). This reset prevents alteration of the flash as operation of the various elements of the chip would otherwise become unreliable due to low voltage. The BOD circuit maintains this reset down below 1 V, at which point the power-on reset circuitry maintains the overall reset. Both the 2.2 V and 1.85 V thresholds include some hysteresis. In normal operation, this hysteresis allows the 2.2 V detection to reliably interrupt, or a regularly executed event loop to sense the condition. 7.37.3 Code security (Code Read Protection - CRP) This feature of the LPC408x/7x allows user to enable different levels of security in the system so that access to the on-chip flash and use of the JTAG and ISP can be restricted. When needed, CRP is invoked by programming a specific pattern into a dedicated flash location. IAP commands are not affected by the CRP. There are three levels of the Code Read Protection. CRP1 disables access to chip via the JTAG and allows partial flash update (excluding flash sector 0) using a limited set of the ISP commands. This mode is useful when CRP is required and flash field updates are needed but all sectors can not be erased. CRP2 disables access to chip via the JTAG and only allows full flash erase and update using a reduced set of the ISP commands. Running an application with level CRP3 selected fully disables any access to chip via the JTAG pins and the ISP. This mode effectively disables ISP override using P2[10] pin, too. It is up to the user's application to provide (if needed) flash update mechanism using IAP calls or call reinvoke ISP command to enable flash update via UART0. LPC408X_7X Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3.3 -- 16 October 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 78 of 138 LPC408x/7x NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller CAUTION If level three Code Read Protection (CRP3) is selected, no future factory testing can be performed on the device. 7.37.4 APB interface The APB peripherals are split into two separate APB buses in order to distribute the bus bandwidth and thereby reducing stalls caused by contention between the CPU and the GPDMA controller. 7.37.5 AHB multilayer matrix The LPC408x/7x use an AHB multilayer matrix. This matrix connects the instruction (I-code) and data (D-code) CPU buses of the ARM Cortex-M4 to the flash memory, the main (32 kB) static RAM, and the Boot ROM. The GPDMA can also access all of these memories. Additionally, the matrix connects the CPU system bus and all of the DMA controllers to the various peripheral functions. 7.37.6 External interrupt inputs The LPC408x/7x include up to 30 edge sensitive interrupt inputs combined with one level sensitive external interrupt input as selectable pin function. The external interrupt input can optionally be used to wake up the processor from Power-down mode. 7.37.7 Memory mapping control The Cortex-M4 incorporates a mechanism that allows remapping the interrupt vector table to alternate locations in the memory map. This is controlled via the Vector Table Offset Register contained in the NVIC. The vector table may be located anywhere within the bottom 1 GB of Cortex-M4 address space. The vector table must be located on a 128 word (512 byte) boundary because the NVIC on the LPC408x/7x is configured for 128 total interrupts. 7.38 Debug control Debug and trace functions are integrated into the ARM Cortex-M4. Serial wire debug and trace functions are supported in addition to a standard JTAG debug and parallel trace functions. The ARM Cortex-M4 is configured to support up to eight breakpoints and four watch points. 8. Limiting values Table 7. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134).[1] Symbol Parameter Conditions Min Max Unit VDD(3V3) supply voltage (3.3 V) external rail 2.4 3.6 V VDD(REG)(3V3) regulator supply voltage (3.3 V) 2.4 3.6 V VDDA analog 3.3 V pad supply voltage 0.5 +4.6 V Vi(VBAT) input voltage on pin VBAT 0.5 +4.6 V LPC408X_7X Product data sheet for the RTC All information provided in this document is subject to legal disclaimers. Rev. 3.3 -- 16 October 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 79 of 138 LPC408x/7x NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller Table 7. Limiting values ...continued In accordance with the Absolute Maximum Rating System (IEC 60134).[1] Symbol Parameter Conditions Vi(VREFP) input voltage on pin VREFP VIA analog input voltage on ADC related pins VI input voltage 5 V tolerant digital I/O pins; [2] Min Max Unit 0.5 +4.6 V 0.5 +5.1 V 0.5 +5.5 V 0.5 +3.6 V 0.5 VDD(3V3) + 0.5 V VDD(3V3) 2.4V VDD(3V3) 0 V other I/O pins [2][3] IDD supply current per supply pin - 100 mA ISS ground current per ground pin - 100 mA Ilatch I/O latch-up current (0.5VDD(3V3)) < VI < (1.5VDD(3V3)); - 100 mA 65 +150 C - 1.5 W - 4000 V Tj < 125 C Tstg storage temperature non-operating Ptot(pack) total power dissipation (per package) based on package heat transfer, not device power consumption VESD electrostatic discharge voltage human body model; all pins [1] [4] [5] The following applies to the limiting values: a) This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maximum. b) Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to VSS unless otherwise noted. [2] Including voltage on outputs in 3-state mode. [3] Not to exceed 4.6 V. [4] The maximum non-operating storage temperature is different than the temperature for required shelf life which should be determined based on the required shelf lifetime. Please refer to the JEDEC spec for further details. [5] Human body model: equivalent to discharging a 100 pF capacitor through a 1.5 k series resistor. 9. Thermal characteristics The average chip junction temperature, Tj (C), can be calculated using the following equation: T j = T amb + P D R th j - a (1) * Tamb = ambient temperature (C), * Rth(j-a) = the package junction-to-ambient thermal resistance (C/W) * PD = sum of internal and I/O power dissipation LPC408X_7X Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3.3 -- 16 October 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 80 of 138 LPC408x/7x NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller Table 8. Thermal characteristics VDD = 3.0 V to 3.6 V; Tamb = 40 C to +85 C unless otherwise specified; Symbol Parameter Conditions Tj(max) maximum junction temperature Min Typ Max Unit - - 125 C Table 9. Thermal resistance (LQFP packages) Tamb = 40 C to +85 C unless otherwise specified. Thermal resistance value (C/W): 15 % LQFP80 LQFP144 LQFP208 0 m/s 41 31 27 1 m/s 35 28 25 2.5 m/s 32 26 24 0 m/s 61 43 35 1 m/s 47 35 31 2.5 m/s 43 33 29 jc 7.8 9.2 10.5 jb 11.6 13.5 15.2 ja JEDEC (4.5 in 4 in) Single-layer (4.5 in 3 in) Table 10. Thermal resistance value (TFBGA packages) Tamb = 40 C to +85 C unless otherwise specified. Thermal resistance value (C/W): 15 % TFBGA180 TFBGA208 47 43 ja JEDEC (4.5 in 4 in) 0 m/s 1 m/s 39 37 2.5 m/s 35 33 39 37 8-layer (4.5 in 3 in) 0 m/s LPC408X_7X Product data sheet 1 m/s 35 33 2.5 m/s 31 30 jc 8.5 7.4 jb 13 16 All information provided in this document is subject to legal disclaimers. Rev. 3.3 -- 16 October 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 81 of 138 LPC408x/7x NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller 10. Static characteristics Table 11. Static characteristics Tamb = 40 C to +85 C, unless otherwise specified. Min Typ[1] Max Unit 2.4 3.3 3.6 V 2.4 3.3 3.6 V [3] 2.7 3.3 3.6 V input voltage on pin VBAT [4] 2.1 3.0 3.6 V Vi(VREFP) input voltage on pin VREFP [3] 2.7 3.3 VDDA V IDD(REG)(3V3) regulator supply current active mode; code (3.3 V) while(1){} Symbol Parameter Conditions VDD(3V3) supply voltage (3.3 V) external rail VDD(REG)(3V3) regulator supply voltage (3.3 V) VDDA analog 3.3 V pad supply voltage Vi(VBAT) Supply pins [2] executed from flash; all peripherals disabled PCLK = CCLK/4 CCLK = 12 MHz; PLL disabled [5][6] - 7.5 - mA CCLK = 120 MHz; PLL enabled [5][7] - 56 - mA active mode; code while(1){} executed from flash; all peripherals enabled; PCLK = CCLK/4 IBAT battery supply current CCLK = 12 MHz; PLL disabled [5][6] 14 - - CCLK = 120 MHz; PLL enabled [5][7] 120 - mA Sleep mode [5][8] - 5.5 - mA Deep-sleep mode [5][9] - 550 1200 A Power-down mode [5][9] - 280 600 A [10] - 1 9 A RTC running; part powered down; VDD(REG)(3V3) =0 V; Vi(VBAT) = 3.0 V; VDD(3V3) = 0 V. part powered; VDD(REG)(3V3) = 3.3 V; Vi(VBAT) = 3.0 V LPC408X_7X Product data sheet [11] All information provided in this document is subject to legal disclaimers. Rev. 3.3 -- 16 October 2015 <10 nA (c) NXP Semiconductors N.V. 2015. All rights reserved. 82 of 138 LPC408x/7x NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller Table 11. Static characteristics ...continued Tamb = 40 C to +85 C, unless otherwise specified. Symbol Parameter Conditions Min Typ[1] Max Unit Standard port pins, RESET IIL LOW-level input current VI = 0 V; on-chip pull-up resistor disabled - 0.5 10 nA IIH HIGH-level input current VI = VDD(3V3); on-chip pull-down resistor disabled - 0.5 10 nA VI input voltage pin configured to provide a digital function 0 - 5.0 V 0 - VDD(3V3) V V [15][16] [17] VO output voltage VIH HIGH-level input voltage 0.7VDD(3V3) - - VIL LOW-level input voltage - - 0.3VDD(3V3) V Vhys hysteresis voltage 0.4 - - V VOH HIGH-level output voltage IOH = 4 mA VDD(3V3) 0.45 - - V VOL LOW-level output voltage IOL = 4 mA - - 0.45 V IOH HIGH-level output current VOH = VDD(3V3) 0.4 V 4 - - mA IOL LOW-level output current VOL = 0.4 V 4 - - mA IOHS HIGH-level short-circuit VOH = 0 V output current [18] - - 50 mA IOLS LOW-level short-circuit output current VOL = VDD(3V3) [18] - - 60 mA Ipd pull-down current VI = 5 V 10 50 150 A Ipu pull-up current VI = 0 V 15 50 85 A VDD(3V3) < VI < 5 V 0 0 0 A V I2C-bus output active pins (P0[27] and P0[28]) VIH HIGH-level input voltage 0.7VDD(3V3) - - VIL LOW-level input voltage - - 0.3VDD(3V3) V Vhys hysteresis voltage - 0.05 VDD(3V3) - V VOL LOW-level output voltage IOLS = 3 mA - - 0.4 V ILI input leakage current VI = VDD(3V3) - 2 4 A - 10 22 A [20] - - 10 A [20] - - 5.25 V [20] 0.2 - - V [19] VI = 5 V USB pins IOZ OFF-state output current VBUS bus supply voltage VDI LPC408X_7X Product data sheet differential input sensitivity voltage 0 V < VI < 3.3 V (D+) (D) All information provided in this document is subject to legal disclaimers. Rev. 3.3 -- 16 October 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 83 of 138 LPC408x/7x NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller Table 11. Static characteristics ...continued Tamb = 40 C to +85 C, unless otherwise specified. Symbol Parameter Min Typ[1] Max Unit [20] 0.8 - 2.5 V [20] 0.8 - 2.0 V Conditions VCM differential common mode voltage range includes VDI range Vth(rs)se single-ended receiver switching threshold voltage VOL LOW-level output voltage for low-/full-speed RL of 1.5 k to 3.6 V [20] - - 0.18 V VOH HIGH-level output voltage (driven) for low-/full-speed RL of 15 k to GND [20] 2.8 - 3.5 V Ctrans transceiver capacitance pin to GND [20] - - 20 pF Oscillator pins (see Section 13.2) Vi(XTAL1) input voltage on pin XTAL1 0.5 1.8 1.95 V Vo(XTAL2) output voltage on pin XTAL2 0.5 1.8 1.95 V Vi(RTCX1) input voltage on pin RTCX1 0.5 - 3.6 V Vo(RTCX2) output voltage on pin RTCX2 0.5 - 3.6 V [1] Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply voltages. [2] For USB operation 3.0 V VDD((3V3) 3.6 V. Guaranteed by design. [3] VDDA and VREFP should be tied to VDD(3V3) if the ADC and DAC are not used. [4] The RTC typically fails when Vi(VBAT) drops below 1.6 V. [5] VDD(REG)(3V3) = 3.3 V; Tamb = 25 C for all power consumption measurements. [6] Boost control bits in the PBOOST register set to 0x0 (see LPC408x/7x User manual). [7] Boost control bits in the PBOOST register set to 0x3 (see LPC408x/7x User manual). [8] IRC running at 12 MHz; main oscillator and PLL disabled; PCLK = CCLK/4. [9] BOD disabled. [10] On pin VBAT; VDD(REG)(3V3) = VDD(3V3) = VDDA = 0; Tamb = 25 C. [11] On pin VBAT; VDD(REG)(3V3) = VDD(3V3) = VDDA = 3.3 V; Tamb = 25 C. [12] All internal pull-ups disabled. All pins configured as output and driven LOW. VDD(3V3) = 3.3 V; Tamb = 25 C. [13] VDDA = 3.3 V; Tamb = 25 C. [14] Vi(VREFP) = 3.3 V; Tamb = 25 C. [15] Including voltage on outputs in 3-state mode. [16] VDD(3V3) supply voltages must be present. [17] 3-state outputs go into 3-state mode in Deep power-down mode. [18] Allowed as long as the current limit does not exceed the maximum current allowed by the device. [19] To VSS. [20] 3.0 V VDD(3V3) 3.6 V. LPC408X_7X Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3.3 -- 16 October 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 84 of 138 LPC408x/7x NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller 10.1 Power consumption 002aah051 1.5 IDD(REG)(3V3) (mA) VDD(REG)(3V3) = 3.6 V 3.3 V 3.0 V 2.4 V 1.1 0.7 0.3 -40 -15 10 35 60 85 temperature (C) Conditions: BOD disabled. Fig 12. Deep-sleep mode: Typical regulator supply current IDD(REG)(3V3) versus temperature 002aah052 900 IDD(REG)(3V3) (A) 600 300 0 -40 VDD(REG)(3V3) = 3.6 V 3.3 V 3.0 V 2.4 V -15 10 35 60 85 temperature (C) Conditions: BOD disabled. Fig 13. Power-down mode: Typical regulator supply current IDD(REG)(3V3) versus temperature LPC408X_7X Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3.3 -- 16 October 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 85 of 138 LPC408x/7x NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller 002aah074 2.0 IBAT (A) 1.6 1.2 0.8 0.4 0 -40 -15 10 35 60 85 temperature (C) Conditions: VDD(REG)(3V3) = VDDA = VDD(3V3) = 0; VBAT = 3.0 V. Fig 14. Part powered off: Typical battery supply current (IBAT) versus temperature 10.2 Peripheral power consumption The supply current per peripheral is measured as the difference in supply current between the peripheral block enabled and the peripheral block disabled in the PCONP register. All other blocks are disabled and no code is executed. Measured on a typical sample at Tamb = 25 C. The peripheral clock was set to PCLK = CCLK/4 with CCLK = 12 MHz, 48 MHz, and 120 MHz. The combined current of several peripherals running at the same time can be less than the sum of each individual peripheral current measured separately. Table 12. Power consumption for individual analog and digital blocks Tamb = 25 C; VDD(REG)(3V3) = VDD(3V3) = VDDA = 3.3 V; PCLK = CCLK/4. Peripheral Conditions Typical supply current in mA 12 MHz[1] 48 MHz[1] 120 MHz[2] LPC408X_7X Product data sheet Timer0 0.01 0.06 0.15 Timer1 0.02 0.07 0.16 Timer2 0.02 0.07 0.17 Timer3 0.01 0.07 0.16 Timer0 + Timer1 + Timer2 + Timer3 0.07 0.28 0.67 UART0 0.05 0.19 0.45 UART1 0.06 0.24 0.56 UART2 0.05 0.2 0.47 UART3 0.06 0.23 0.56 USART4 0.07 0.27 0.66 UART0 + UART1 + UART2 + UART3 + USART4 0.29 1.13 2.74 PWM0 + PWM1 0.08 0.31 0.75 All information provided in this document is subject to legal disclaimers. Rev. 3.3 -- 16 October 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 86 of 138 LPC408x/7x NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller Table 12. Power consumption for individual analog and digital blocks ...continued Tamb = 25 C; VDD(REG)(3V3) = VDD(3V3) = VDDA = 3.3 V; PCLK = CCLK/4. Peripheral Conditions Typical supply current in mA 12 MHz[1] 48 MHz[1] 120 MHz[2] Motor control PWM 0.04 0.15 0.36 I2C0 0.01 0.03 0.08 I2C1 0.01 0.03 0.1 I2C2 0.01 0.03 0.08 I2C0 + I2C1 + I2C2 0.02 0.1 0.26 SSP0 0.03 0.1 0.26 SSP1 0.02 0.11 0.27 DAC 0.3 0.31 0.33 ADC (12 MHz clock) 1.51 1.61 1.7 Comparator 0.01 0.03 0.06 CAN1 0.11 0.44 1.08 CAN2 0.1 0.4 0.98 0.15 0.59 1.44 1.1 4.27 10.27 QEI 0.02 0.11 0.28 GPIO 0.4 1.72 4.16 LCD 0.99 3.84 9.25 I2S 0.04 0.18 0.46 EMC 0.82 3.17 7.63 RTC 0.01 0.01 0.05 CAN1 + CAN2 DMA PCLK = CCLK USB + PLL1 LPC408X_7X Product data sheet 0.62 0.97 1.67 Ethernet PCENET bit set 0.54 to 1 in the PCONP register 2.08 5.03 SPIFI SPIFICLKSEL register is set to 0x1 3.44 8.15 0.89 [1] Boost control bits in the PBOOST register set to 0x0 (see LPC178x/7x User manual UM10470). [2] Boost control bits in the PBOOST register set to 0x3 (see LPC178x/7x User manual UM10470). All information provided in this document is subject to legal disclaimers. Rev. 3.3 -- 16 October 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 87 of 138 LPC408x/7x NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller 10.3 Electrical pin characteristics 002aaf112 3.6 VOH (V) T = 85 C 25 C -40 C 3.2 2.8 2.4 2.0 0 8 16 24 IOH (mA) Conditions: VDD(REG)(3V3) = VDD(3V3) = 3.3 V; standard port pins. Fig 15. Typical HIGH-level output voltage VOH versus HIGH-level output source current IOH 002aaf111 15 IOL (mA) T = 85 C 25 C -40 C 10 5 0 0 0.2 0.4 0.6 VOL (V) Conditions: VDD(REG)(3V3) = VDD(3V3) = 3.3 V; standard port pins. Fig 16. Typical LOW-level output current IOL versus LOW-level output voltage VOL LPC408X_7X Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3.3 -- 16 October 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 88 of 138 LPC408x/7x NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller 002aaf108 10 Ipu (A) -10 -30 T = 85 C 25 C -40 C -50 -70 0 1 2 3 4 5 VI (V) Conditions: VDD(REG)(3V3) = VDD(3V3) = 3.3 V; standard port pins. Fig 17. Typical pull-up current Ipu versus input voltage VI 002aaf109 90 Ipd (A) 70 T = 85 C 25 C -40 C 50 30 10 -10 0 1 2 3 4 5 VI (V) Conditions: VDD(REG)(3V3) = VDD(3V3) = 3.3 V; standard port pins. Fig 18. Typical pull-down current Ipd versus input voltage VI LPC408X_7X Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3.3 -- 16 October 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 89 of 138 LPC408x/7x NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller 11. Dynamic characteristics 11.1 Flash memory Table 13. Flash characteristics Tamb = 40 C to +85 C, unless otherwise specified. Symbol Parameter Nendu endurance tret retention time ter erase time tprog programming time Conditions Min [1] Typ Max Unit 10000 100000 - cycles powered 10 - - years unpowered 20 - - years sector or multiple consecutive sectors 95 100 105 ms 0.95 1 1.05 ms [2] [1] Number of program/erase cycles. [2] Programming times are given for writing 256 bytes from RAM to the flash. Data must be written to the flash in blocks of 256 bytes. Table 14. EEPROM characteristics Tamb = 40 C to +85 C; VDD(REG)(3V3) = 2.7 V to 3.6 V. Symbol Parameter fclk Min Typ Max Unit clock frequency 200 375 400 kHz Nendu endurance 100000 500000 - cycles tret retention time powered 10 - - years unpowered 10 - - years 64 bytes [1] - 1.8 - ms 64 bytes [1] - 1.1 - ms erase time ter programming time tprog [1] Conditions EEPROM clock frequency = 375 kHz. Programming/erase times increase with decreasing EEPROM clock frequency. 11.2 External memory interface Table 15. Dynamic characteristics: Static external memory interface CL = 30 pF, Tamb = 40 C to 85 C, VDD(3V3) = 3.0 V to 3.6 V. Values guaranteed by design. Symbol Parameter[1] Read cycle Conditions[1] Min Typ Max Unit 3.3 4.3 6.1 ns parameters[2] tCSLAV CS LOW to address RD1 valid time tCSLOEL CS LOW to OE LOW time RD2 [3] 2.4 + Tcy(clk) WAITOEN 3.1 + Tcy(clk) WAITOEN 4.2 + Tcy(clk) WAITOEN ns tCSLBLSL CS LOW to BLS LOW time RD3; PB = 1 [3] 2.7 3.5 4.9 ns tOELOEH OE LOW to OE HIGH time RD4 [3] (WAITRD WAITOEN + 1) Tcy(clk) 2.2 (WAITRD WAITOEN + 1) Tcy(clk) 2.8 (WAITRD WAITOEN + 1) Tcy(clk) 3.8 ns LPC408X_7X Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3.3 -- 16 October 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 90 of 138 LPC408x/7x NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller Table 15. Dynamic characteristics: Static external memory interface ...continued CL = 30 pF, Tamb = 40 C to 85 C, VDD(3V3) = 3.0 V to 3.6 V. Values guaranteed by design. Symbol Parameter[1] Conditions[1] Min Typ Max Unit (WAITRD WAITOEN + 1) Tcy(clk) 9.6 (WAITRD WAITOEN + 1) Tcy(clk) 13.2 (WAITRD WAITOEN + 1) Tcy(clk) 20.2 ns 5.0 7.2 ns 2.7 3.4 4.9 ns tam memory access time RD5 [4][3] th(D) data input hold time RD6 [5][3] tCSHBLSH CS HIGH to BLS HIGH time PB = 1 tCSHOEH CS HIGH to OE HIGH time [3] 2.4 3.1 4.2 ns tOEHANV OE HIGH to address invalid time [3] 0.77 1.2 1.86 ns tdeact deactivation time [3] - 4.3 6.1 ns RD7 Write cycle parameters[2] tCSLAV CS LOW to address WR1 valid time 3.3 4.3 6.1 ns tCSLDV CS LOW to data valid time WR2 3.4 4.8 6.6 ns tCSLWEL CS LOW to WE LOW time WR3; PB =1 [3] 2.6 + Tcy(clk) (1 + WAITWEN) 3.3 + Tcy(clk) (1 + WAITWEN) 4.6 + Tcy(clk) (1 + WAITWEN) ns tCSLBLSL CS LOW to BLS LOW time WR4; PB = 1 [3] 2.7 3.5 4.9 ns tWELWEH WE LOW to WE HIGH time WR5; PB =1 [3] (WAITWR (WAITWR ns (WAITWR WAITWEN + 1) WAITWEN + 1) WAITWEN + 1) Tcy(clk) 2.8 Tcy(clk) 3.8 Tcy(clk) 2.3 [3] (WAITWR (WAITWR (WAITWR ns WAITWEN + 3) WAITWEN + 3) WAITWEN + 3) Tcy(clk) 2.8 Tcy(clk) 3.5 Tcy(clk) 5.0 [3] 3.1 + Tcy(clk) 4.3 + Tcy(clk) 5.8 + Tcy(clk) ns [6][3] Tcy(clk) 2.6 Tcy(clk) 3.4 Tcy(clk) 4.6 ns 3.4 4.8 6.6 ns tBLSLBLSH BLS LOW to BLS HIGH time PB = 1 tWEHDNV WE HIGH to data invalid time WR6; PB =1 tWEHEOW WE HIGH to end of write time WR7; PB = 1 tBLSHDNV BLS HIGH to data invalid time PB = 1 tWEHANV WE HIGH to PB = 1 address invalid time [3] 3.0 + Tcy(clk) 3.8 + Tcy(clk) 5.3 + Tcy(clk) ns tdeact deactivation time WR8; PB = 0; PB = 1 [3] 3.3 4.3 6.1 ns tCSLBLSL CS LOW to BLS LOW WR9; PB = 0 [3] 2.7 + Tcy(clk) (1 + WAITWEN) 3.5 + Tcy(clk) (1 + WAITWEN) 4.9 + Tcy(clk) (1 + WAITWEN) ns WR10; PB = 0 [3] (WAITWR (WAITWR ns (WAITWR WAITWEN + 3) WAITWEN + 3) WAITWEN + 3) Tcy(clk) 3.5 Tcy(clk) 5.0 Tcy(clk) 2.8 tBLSHEOW BLS HIGH to end of WR11; PB = 0 write time [6][3] 3.3 + Tcy(clk) 4.4 + Tcy(clk) 6.1 + Tcy(clk) ns [3] 3.4 + Tcy(clk) 4.8 + Tcy(clk) 6.6 + Tcy(clk) ns tBLSLBLSH BLS LOW to BLS HIGH time tBLSHDNV [1] BLS HIGH to data invalid time WR12; PB = 0 Parameters are shown as RDn or WDn in Figure 19 as indicated in the Conditions column. LPC408X_7X Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3.3 -- 16 October 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 91 of 138 LPC408x/7x NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller [2] Parameters specified for 40 % of VDD(3V3) for rising edges and 60 % of VDD(3V3) for falling edges. [3] Tcy(clk) = 1/EMC_CLK (see LPC408x/7x User manual). [4] Latest of address valid, EMC_CSx LOW, EMC_OE LOW, EMC_BLSx LOW (PB = 1). [5] After End Of Read (EOR): Earliest of EMC_CSx HIGH, EMC_OE HIGH, EMC_BLSx HIGH (PB = 1), address invalid. [6] End Of Write (EOW): Earliest of address invalid, EMC_CSx HIGH, EMC_BLSx HIGH (PB = 1). EMC_Ax RD1 WR1 EMC_CSx WR8 RD2 RD4 EMC_OE RD7 WR9 WR10 WR11 EMC_BLSx EMC_WE RD5 RD5 RD5 RD6 WR2 WR12 EMC_Dx EOW EOR 002aag214 Fig 19. External static memory read/write access (PB = 0) EMC_Ax RD1 WR1 EMC_CSx WR8 RD2 RD4 EMC_OE RD3 WR4 RD7 EMC_BLSx WR8 RD7 WR3 WR5 WR7 EMC_WE RD5 RD5 RD5 RD6 RD5 WR2 WR6 EMC_Dx EOR EOW 002aag215 Fig 20. External static memory read/write access (PB =1) LPC408X_7X Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3.3 -- 16 October 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 92 of 138 LPC408x/7x NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller EMC_Ax EMC_CSx EMC_OE EMC_BLSx EMC_WE RD5 RD5 RD5 RD5 EMC_Dx 002aag216 Fig 21. External static memory burst read cycle Table 16. Dynamic characteristics: Dynamic external memory interface, read strategy bits (RD bits) = 00 CL = 30 pF, Tamb = 40 C to 85 C, VDD(3V3) = 3.0 V to 3.6 V. Values guaranteed by design. Symbol Parameter Min Typ Max Unit - - ns Common to read and write cycles clock cycle time [1] 12.5 td(SV) chip select valid delay time [2] (CLKDLY + 1) (CLKDLY + 1) (CLKDLY + 1) ns 0.25 + 2.8 0.25 + 3.5 0.25 + 5.1 th(S) chip select hold time [2] (CLKDLY + 1) (CLKDLY + 1) (CLKDLY + 1) ns 0.25 1.0 0.25 1.1 0.25 1.5 td(RASV) row address strobe valid delay time [2] (CLKDLY + 1) (CLKDLY + 1) (CLKDLY + 1) ns 0.25 + 2.8 0.25 + 3.6 0.25 + 5.1 th(RAS) row address strobe hold time [2] (CLKDLY + 1) (CLKDLY + 1) (CLKDLY + 1) ns 0.25 0.8 0.25 0.9 0.25 1.0 td(CASV) column address strobe valid delay time [2] (CLKDLY + 1) (CLKDLY + 1) (CLKDLY + 1) ns 0.25 + 2.7 0.25 + 3.4 0.25 + 4.9 th(CAS) column address strobe hold time [2] (CLKDLY + 1) (CLKDLY + 1) (CLKDLY + 1) ns 0.25 0.8 0.25 1.0 0.25 1.2 td(WV) write valid delay time [2] (CLKDLY + 1) (CLKDLY + 1) (CLKDLY + 1) ns 0.25 + 3.2 0.25 + 4.1 0.25 + 6.0 th(W) write hold time [2] (CLKDLY + 1) (CLKDLY + 1) (CLKDLY + 1) ns 0.25 0.6 0.25 0.67 0.25 0.7 td(AV) address valid delay time [2] (CLKDLY + 1) (CLKDLY + 1) (CLKDLY + 1) ns 0.25 + 3.4 0.25 + 4.6 0.25 + 6.8 th(A) address hold time [2] (CLKDLY + 1) (CLKDLY + 1) (CLKDLY + 1) ns 0.25 1.1 0.25 1.4 0.25 1.8 Tcy(clk) Read cycle parameters tsu(D) data input set-up time [3] (FBCLKDLY + 1) 0.25 - 0.9 (FBCLKDLY + 1) 0.25 + 2.3 - ns th(D) data input hold time [4] (FBCLKDLY + 1) 0.25 + 4.0 (FBCLKDLY + 1) 0.25 + 4.7 (FBCLKDLY + 1) 0.25 + 5.8 ns LPC408X_7X Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3.3 -- 16 October 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 93 of 138 LPC408x/7x NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller Table 16. Dynamic characteristics: Dynamic external memory interface, read strategy bits (RD bits) = 00 ...continued CL = 30 pF, Tamb = 40 C to 85 C, VDD(3V3) = 3.0 V to 3.6 V. Values guaranteed by design. Symbol Parameter Min Typ Max Unit Write cycle parameters td(QV) data output valid delay time [2] (CLKDLY + 1) (CLKDLY + 1) (CLKDLY + 1) ns 0.25 + 3.9 0.25 + 5.4 0.25 + 7.8 th(Q) data output hold time [2] (CLKDLY + 1) (CLKDLY + 1) (CLKDLY + 1) ns 0.25 1.1 0.25 1.2 0.25 1.4 [1] Refers to SDRAM clock signal EMC_CLKx. [2] CLKDLY = CLKOUTnDLY, where n = 0, 1. [3] The data input set-up time has to be selected with the following margin: tsu(D) + delay time of feedback clock SDRAM access time board delay time 0. [4] The data input hold time has to be selected with the following margin: th(D) + SDRAM access time board delay time delay time of feedback clock 0. Table 17. Dynamic characteristics: Dynamic external memory interface, read strategy bits (RD bits) = 01 CL = 30 pF, Tamb = 40 C to 85 C, VDD(3V3) = 3.0 V to 3.6 V. Values guaranteed by design. Symbol Parameter Min Typ Max Unit 12.5 - - ns Common to read and write cycles [1] Tcy(clk) clock cycle time td(SV) chip select valid delay time (CMDDLY + 1) 0.25 + 4.9 (CMDDLY + 1) 0.25 + 6.7 (CMDDLY + 1) 0.25 + 10.4 ns th(S) chip select hold time (CMDDLY + 1) 0.25 + 1.2 (CMDDLY + 1) 0.25 + 2.1 (CMDDLY + 1) 0.25 + 3.8 ns td(RASV) row address strobe valid delay time (CMDDLY + 1) 0.25 + 4.9 (CMDDLY + 1) 0.25 + 6.8 (CMDDLY + 1) 0.25 + 10.4 ns th(RAS) row address strobe hold time (CMDDLY + 1) 0.25 + 1.3 (CMDDLY + 1) 0.25 + 2.3 (CMDDLY + 1) 0.25 + 4.3 ns td(CASV) column address strobe valid delay time (CMDDLY + 1) 0.25 + 4.8 (CMDDLY + 1) 0.25 + 6.7 (CMDDLY + 1) 0.25 + 10.2 ns th(CAS) column address strobe hold time (CMDDLY + 1) 0.25 + 1.2 (CMDDLY + 1) 0.25 + 2.2 (CMDDLY + 1) 0.25 + 4.1 ns td(WV) write valid delay time (CMDDLY + 1) 0.25 + 5.1 (CMDDLY + 1) 0.25 + 7.1 (CMDDLY + 1) 0.25 + 10.9 ns th(W) write hold time (CMDDLY + 1) 0.25 + 1.5 (CMDDLY + 1) 0.25 + 2.6 (CMDDLY + 1) 0.25 + 4.8 ns td(AV) address valid delay time (CMDDLY + 1) 0.25 + 5.5 (CMDDLY + 1) 0.25 + 7.7 (CMDDLY + 1) 0.25 + 11.9 ns th(A) address hold time (CMDDLY + 1) 0.25 + 1.0 (CMDDLY + 1) 0.25 + 1.8 (CMDDLY + 1) 0.25 + 3.5 ns Read cycle parameters tsu(D) data input set-up time [2] (FBCLKDLY + 1) 0.25 + 4.1 (FBCLKDLY + 1) 0.25 + 2.3 (FBCLKDLY + 1) 0.25 0.9 ns th(D) data input hold time [3] (FBCLKDLY + 1) 0.25 + 4.0 (FBCLKDLY + 1) 0.25 + 4.7 (FBCLKDLY + 1) 0.25 + 5.8 ns LPC408X_7X Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3.3 -- 16 October 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 94 of 138 LPC408x/7x NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller Table 17. Dynamic characteristics: Dynamic external memory interface, read strategy bits (RD bits) = 01 ...continued CL = 30 pF, Tamb = 40 C to 85 C, VDD(3V3) = 3.0 V to 3.6 V. Values guaranteed by design. Symbol Parameter Min Typ Max Unit Write cycle parameters td(QV) data output valid delay time (CMDDLY + 1) 0.25 + 5.9 (CMDDLY + 1) 0.25 + 8.7 (CMDDLY + 1) 0.25 + 13.1 ns th(Q) data output hold time (CMDDLY + 1) 0.25 + 1.0 (CMDDLY + 1) 0.25 + 2.0 (CMDDLY + 1) 0.25 + 3.9 ns [1] Refers to SDRAM clock signal EMC_CLKx. [2] The data input set-up time has to be selected with the following margin: tsu(D) + delay time of feedback clock SDRAM access time board delay time 0. [3] The data input hold time has to be selected with the following margin: th(D) + SDRAM access time - board delay time - delay time of feedback clock 0. Tcy(clk) EMC_CLKn delay = 0 EMC_DYCSn, EMC_RAS, EMC_CAS, EMC_WE, EMC_CKEOUTn, EMC_A[22:0], EMC_DQMOUTn td(xV) th(x) td(QV) th(Q) EMC_D[31:0] write tsu(D) th(D) EMC_D[31:0] read 002aah129 Fig 22. Dynamic external memory interface signal timing LPC408X_7X Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3.3 -- 16 October 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 95 of 138 LPC408x/7x NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller Table 18. Dynamic characteristics: Dynamic external memory interface programmable clock delays CL = 30 pF, Tamb = 40 C to 85 C, VDD(3V3) = 3.0 V to 3.6 V.Values guaranteed by design. Symbol Parameter Conditions Min Max Unit td delay time Programmable delay block 0 (CMDDLY or CLKOUTnDLY bit 0 = 1) [1] 0.1 0.2 ns Programmable delay block 1 (CMDDLY or CLKOUTnDLY bit 1 = 1) [1] 0.2 0.5 ns Programmable delay block 2 (CMDDLY or CLKOUTnDLY bit 2 = 1) [1] 0.5 1.3 ns Programmable delay block 3 (CMDDLY or CLKOUTnDLY bit 3 = 1) [1] 1.2 2.9 ns Programmable delay block 4 (CMDDLY or CLKOUTnDLY bit 4 = 1) [1] 2.4 6.0 ns [1] The programmable delay blocks are controlled by the EMCDLYCTL register in the EMC register block. All delay times are incremental delays for each element starting from delay block 0. See the LPC408x/7x user manual for details. 11.3 External clock Table 19. Dynamic characteristic: external clock (see Figure 40) Tamb = 40 C to +85 C; VDD(3V3) over specified ranges.[1] Symbol Parameter Min Typ[2] Max Unit fosc oscillator frequency 1 - 25 MHz Tcy(clk) clock cycle time 40 - 1000 ns tCHCX clock HIGH time Tcy(clk) 0.4 - - ns tCLCX clock LOW time Tcy(clk) 0.4 - - ns tCLCH clock rise time - - 5 ns tCHCL clock fall time - - 5 ns [1] Parameters are valid over operating temperature range unless otherwise specified. [2] Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply voltages. tCHCL tCHCX tCLCH tCLCX Tcy(clk) 002aaa907 Fig 23. External clock timing (with an amplitude of at least Vi(RMS) = 200 mV) LPC408X_7X Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3.3 -- 16 October 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 96 of 138 LPC408x/7x NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller 11.4 Internal oscillators Table 20. Dynamic characteristic: internal oscillators Tamb = 40 C to +85 C; 2.7 V VDD(3V3) 3.6 V.[1] Typ[2] Max Unit internal RC oscillator frequency 11.88 12 12.12 MHz RTC input frequency 32.768 - kHz Symbol Parameter fosc(RC) fi(RTC) Min - [1] Parameters are valid over operating temperature range unless otherwise specified. [2] Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply voltages. 11.5 I/O pins Table 21. Dynamic characteristic: I/O pins[1] Tamb = 40 C to +85 C; VDD(3V3) over specified ranges. Symbol Parameter Conditions Min Typ Max Unit tr rise time pin configured as output 3.0 - 5.0 ns tf fall time pin configured as output 2.5 - 5.0 ns [1] Applies to standard port pin. For details, see the LPC408x/7x IBIS model available on the NXP website. 11.6 SSP interface Table 22. Dynamic characteristics: SSP pins in SPI mode CL = 10 pF, Tamb = 40 C to 85 C, VDD(3V3) = 3.0 V to 3.6 V. Values guaranteed by design. Symbol Parameter Conditions clock cycle time full-duplex mode Min Max Unit 30 - ns 30 - ns SSP master Tcy(clk) [1] when only transmitting tDS data set-up time in SPI mode [2] 14.8 - ns tDH data hold time in SPI mode [2] 2 - ns - 6.3 ns tv(Q) data output valid time in SPI mode [2] th(Q) data output hold time in SPI mode [2] 2.4 - ns clock cycle time [3] 100 - ns data set-up time in SPI mode [3][4] 14.8 - ns SSP slave Tcy(clk) tDS LPC408X_7X Product data sheet tDH data hold time in SPI mode [3][4] 2 - ns tv(Q) data output valid time in SPI mode [3][4] - 3*Tcy(PCLK) + 6.3 ns th(Q) data output hold time in SPI mode [3][4] 2.4 - ns All information provided in this document is subject to legal disclaimers. Rev. 3.3 -- 16 October 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 97 of 138 LPC408x/7x NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller [1] The minimum clock cycle time, and therefore the maximum frequency of the SSP in master mode, is limited by the pin electronics to the value given. The SSP block should not be configured to generate a clock faster than that. At and below the maximum frequency, Tcy(clk) = (SSPCLKDIV (1 + SCR) CPSDVSR) / fmain. The clock cycle time derived from the SPI bit rate Tcy(clk) is a function of the main clock frequency fmain, the SSP peripheral clock divider (SSPCLKDIV), the SSP SCR parameter (specified in the SSP0CR0 register), and the SSP CPSDVSR parameter (specified in the SSP clock prescale register). [2] Tamb = 40 C to 85 C; VDD(3V3) = 3.0 V to 3.6 V. [3] Tcy(clk) = 12 Tcy(PCLK). The maximum clock rate in slave mode is 1/12th of the PCLK rate. [4] Tamb = 25 C; VDD(3V3) = 3.3 V. Tcy(clk) SCK (CPOL = 0) SCK (CPOL = 1) tv(Q) th(Q) DATA VALID MOSI DATA VALID tDS DATA VALID MISO tDH DATA VALID tv(Q) MOSI th(Q) DATA VALID DATA VALID tDH tDS MISO CPHA = 1 DATA VALID CPHA = 0 DATA VALID 002aae829 Fig 24. SSP master timing in SPI mode LPC408X_7X Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3.3 -- 16 October 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 98 of 138 LPC408x/7x NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller Tcy(clk) SCK (CPOL = 0) SCK (CPOL = 1) tDS MOSI DATA VALID tDH DATA VALID tv(Q) MISO th(Q) DATA VALID tDS MOSI DATA VALID tDH DATA VALID tv(Q) MISO CPHA = 1 DATA VALID th(Q) DATA VALID CPHA = 0 DATA VALID 002aae830 Fig 25. SSP slave timing in SPI mode 11.7 I2C-bus Table 23. Dynamic characteristic: I2C-bus pins[1] Tamb = 40 C to +85 C.[2] Symbol Parameter Conditions Min Max Unit fSCL SCL clock frequency Standard-mode 0 100 kHz Fast-mode 0 400 kHz Fast-mode Plus 0 1 MHz of both SDA and SCL signals - 300 ns 20 + 0.1 Cb 300 ns tf [4][5][6][7] fall time Standard-mode Fast-mode Fast-mode Plus tLOW tHIGH LPC408X_7X Product data sheet LOW period of the SCL clock HIGH period of the SCL clock - 120 ns Standard-mode 4.7 - s Fast-mode 1.3 - s Fast-mode Plus 0.5 - s Standard-mode 4.0 - s Fast-mode 0.6 - s Fast-mode Plus 0.26 - s All information provided in this document is subject to legal disclaimers. Rev. 3.3 -- 16 October 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 99 of 138 LPC408x/7x NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller Table 23. Dynamic characteristic: I2C-bus pins[1] Tamb = 40 C to +85 C.[2] Symbol Parameter tHD;DAT data hold time data set-up time tSU;DAT [3][4][8] [9][10] Conditions Min Max Unit Standard-mode 0 - s Fast-mode 0 - s Fast-mode Plus 0 - s Standard-mode 250 - ns Fast-mode 100 - ns Fast-mode Plus 50 - ns [1] See the I2C-bus specification UM10204 for details. [2] Parameters are valid over operating temperature range unless otherwise specified. [3] tHD;DAT is the data hold time that is measured from the falling edge of SCL; applies to data in transmission and the acknowledge. [4] A device must internally provide a hold time of at least 300 ns for the SDA signal (with respect to the VIH(min) of the SCL signal) to bridge the undefined region of the falling edge of SCL. [5] Cb = total capacitance of one bus line in pF. [6] The maximum tf for the SDA and SCL bus lines is specified at 300 ns. The maximum fall time for the SDA output stage tf is specified at 250 ns. This allows series protection resistors to be connected in between the SDA and the SCL pins and the SDA/SCL bus lines without exceeding the maximum specified tf. [7] In Fast-mode Plus, fall time is specified the same for both output stage and bus timing. If series resistors are used, designers should allow for this when considering bus timing. [8] The maximum tHD;DAT could be 3.45 s and 0.9 s for Standard-mode and Fast-mode but must be less than the maximum of tVD;DAT or tVD;ACK by a transition time (see UM10204). This maximum must only be met if the device does not stretch the LOW period (tLOW) of the SCL signal. If the clock stretches the SCL, the data must be valid by the set-up time before it releases the clock. [9] tSU;DAT is the data set-up time that is measured with respect to the rising edge of SCL; applies to data in transmission and the acknowledge. [10] A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system but the requirement tSU;DAT = 250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line tr(max) + tSU;DAT = 1000 + 250 = 1250 ns (according to the Standard-mode I2C-bus specification) before the SCL line is released. Also the acknowledge timing must meet this set-up time. tf SDA tSU;DAT 70 % 30 % 70 % 30 % tHD;DAT tf 70 % 30 % SCL tVD;DAT tHIGH 70 % 30 % 70 % 30 % 70 % 30 % tLOW S 1 / fSCL 002aaf425 Fig 26. I2C-bus pins clock timing LPC408X_7X Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3.3 -- 16 October 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 100 of 138 LPC408x/7x NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller 11.8 I2S-bus interface Table 24. Dynamic characteristics: I2S-bus interface pins CL = 10 pF, Tamb = 40 C to 85 C, VDD(3V3) = 3.0 V to 3.6 V. Values guaranteed by design. Symbol Parameter Conditions Min Max Unit common to input and output tr rise time [1] - 6.7 ns tf fall time [1] - 8.0 ns tWH pulse width HIGH on pins I2S_TX_SCK and I2S_RX_SCK [1] 25 - - tWL pulse width LOW on pins I2S_TX_SCK and I2S_RX_SCK [1] - 25 ns data output valid time on pin I2S_TX_SDA; [1] - 6 ns data input set-up time on pin I2S_RX_SDA [1] 5 - ns on pin I2S_RX_SDA [1] 2 - ns output tv(Q) input tsu(D) th(D) [1] data input hold time CCLK = 100 MHz; peripheral clock to the I2S-bus interface PCLK = CCLK / 4. I2S clock cycle time Tcy(clk) = 1600 ns, corresponds to the SCK signal in the I2S-bus specification. Tcy(clk) tf tr I2S_TX_SCK tWH tWL I2S_TX_SDA tv(Q) I2S_TX_WS tv(Q) 002aag202 Fig 27. I2S-bus timing (transmit) LPC408X_7X Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3.3 -- 16 October 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 101 of 138 LPC408x/7x NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller Tcy(clk) tf tr I2S_RX_SCK tWH tWL I2S_RX_SDA tsu(D) th(D) I2S_RX_WS tsu(D) 002aag203 tsu(D) Fig 28. I2S-bus timing (receive) 11.9 LCD Remark: The LCD controller is available on parts LPC4088. Table 25. Dynamic characteristics: LCD CL = 10 pF, Tamb = 40 C to 85 C, VDD(3V3) = 3.0 V to 3.6 V. Values guaranteed by design. Symbol Parameter Conditions Min Max Unit fclk clock frequency on pin LCD_DCLK - 50 MHz td(QV) data output valid delay time - 12 ns th(Q) data output hold time 0.5 - ns Tcy(clk) LCD_DCLK td(QV) th(Q) LCD_VD[n] 002aah325 The LCD panel clock is shown with the default polarity. The clock can be inverted via the IPC bit in the LCD_POL register. Typically, the LCD panel uses the falling edge of the LCD_DCLK to sample the data. Fig 29. LCD timing 11.10 SD/MMC Remark: The SD/MMC card interface is available on parts LPC4088/78/76. LPC408X_7X Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3.3 -- 16 October 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 102 of 138 LPC408x/7x NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller Table 26. Dynamic characteristics: SD/MMC CL = 10 pF, Tamb = 40 C to 85 C, VDD(3V3) = 3.0 V to 3.6 V. Values guaranteed by design. Symbol Parameter Conditions Min fclk clock frequency on pin SD_CLK; data transfer mode - on pin SD_CLK; identification mode Max Unit 25 MHz 25 MHz tsu(D) data input set-up time on pins SD_CMD, SD_DAT[3:0] as inputs 6 - ns th(D) data input hold time on pins SD_CMD, SD_DAT[3:0] as inputs 6 - ns td(QV) data output valid delay time on pins SD_CMD, SD_DAT[3:0] as outputs - 23 ns th(Q) data output hold time on pins SD_CMD, SD_DAT[3:0] as outputs 3.5 - ns Tcy(clk) SD_CLK td(QV) th(Q) SD_CMD (O) SD_DATn (O) tsu(D) th(D) SD_CMD (I) SD_DATn (I) 002aag204 Fig 30. SD/MMC timing 11.11 SPIFI Table 27. Dynamic characteristics: SPIFI Tamb = 40 C to 85 C; 3.0 V VDD(3V3) 3.6 V; CL = 30 pF. Values guaranteed by design. LPC408X_7X Product data sheet Symbol Parameter Min Tcy(clk) clock cycle time 11.8 - ns tDS data set-up time 4.8 - ns tDH data hold time 0 - ns tv(Q) data output valid time - 8.8 ns th(Q) data output hold time 3 - ns All information provided in this document is subject to legal disclaimers. Rev. 3.3 -- 16 October 2015 Max Unit (c) NXP Semiconductors N.V. 2015. All rights reserved. 103 of 138 LPC408x/7x NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller Tcy(clk) SPIFI_SCK tv(Q) th(Q) DATA VALID SPIFI data out DATA VALID tDS DATA VALID SPIFI data in tDH DATA VALID 002aah409 Fig 31. SPIFI timing (Mode 0) 12. Characteristics of the analog peripherals 12.1 ADC electrical characteristics Table 28. 12-bit ADC characteristics VDDA = 2.7 V to 3.6 V; Tamb = 40 C to +85 C unless otherwise specified.[1] Symbol Parameter VIA analog input voltage Conditions Min Typ Max Unit 0 - VDDA V - - 1 LSB 12-bit resolution ED [2][3][4 differential linearity error ] EL(adj) integral non-linearity [2][5] - - 6 LSB EO offset error [2][6] - - 5 LSB EG gain error [2][7] - - 5 LSB ET absolute error [2][8] - - <8 LSB fclk(ADC) ADC clock frequency - - 12.4 MHz fc(ADC) ADC conversion frequency single conversion mode - - 400 kSamples/s burst mode - - 375 kSamples/s - - 5 pF [10] - - 1 k [2][3][4 - 1 - LSB Cia analog input capacitance Rvsi voltage source interface resistance 8-bit resolution[11] ED LPC408X_7X Product data sheet differential linearity error ] All information provided in this document is subject to legal disclaimers. Rev. 3.3 -- 16 October 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 104 of 138 LPC408x/7x NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller Table 28. 12-bit ADC characteristics ...continued VDDA = 2.7 V to 3.6 V; Tamb = 40 C to +85 C unless otherwise specified.[1] Symbol Parameter Conditions Min Typ Max Unit - 1 - LSB EL(adj) integral non-linearity [2][5] EO offset error [2][6] - 1 - LSB EG gain error [2][7] - 1 - LSB ET absolute error [2][8] - - <1.5 LSB fclk(ADC) ADC clock frequency - - 36 MHz fc(ADC) ADC conversion frequency - - 1.16 MSamples/s Cia analog input capacitance - - 5 pF Rvsi voltage source interface resistance - - 1 k [1] [9] [10] VDDA and VREFP should be tied to VDD(3V3) if the ADC and DAC are not used. [2] Conditions: VSSA = 0 V, VDDA = 3.3 V. [3] The ADC is monotonic, there are no missing codes. [4] The differential linearity error (ED) is the difference between the actual step width and the ideal step width. See Figure 32. [5] The integral non-linearity (EL(adj)) is the peak difference between the center of the steps of the actual and the ideal transfer curve after appropriate adjustment of gain and offset errors. See Figure 32. [6] The offset error (EO) is the absolute difference between the straight line which fits the actual curve and the straight line which fits the ideal curve. See Figure 32. [7] The gain error (EG) is the relative difference in percent between the straight line fitting the actual transfer curve after removing offset error, and the straight line which fits the ideal transfer curve. See Figure 32. [8] The absolute error (ET) is the maximum difference between the center of the steps of the actual transfer curve of the non-calibrated ADC and the ideal transfer curve. See Figure 32. [9] In single-conversion mode. [10] See Figure 33. [11] 8-bit resolution is achieved by ignoring the lower four bits of the ADC conversion result. LPC408X_7X Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3.3 -- 16 October 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 105 of 138 LPC408x/7x NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller offset error EO gain error EG 4095 4094 4093 4092 4091 4090 (2) 7 code out (1) 6 5 (5) 4 (4) 3 (3) 2 1 LSB (ideal) 1 0 1 2 3 4 5 6 7 4090 4091 4092 4093 4094 4095 4096 VIA (LSBideal) offset error EO 1 LSB = VREFP - VSS 4096 002aaf436 (1) Example of an actual transfer curve. (2) The ideal transfer curve. (3) Differential linearity error (ED). (4) Integral non-linearity (EL(adj)). (5) Center of a step of the actual transfer curve. Fig 32. 12-bit ADC characteristics LPC408X_7X Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3.3 -- 16 October 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 106 of 138 LPC408x/7x NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller LPC408x/7x C3 Rcmp 90 - 300 1.6 pF ADC COMPARATOR BLOCK Rsw 500 - 2 k C1 110 fF AD0[n] C2 80 fF Cia Rvsi VSS VEXT 002aah275 The values of resistor components Rcmp and Rsw vary with temperature and input voltage and are process-dependent. Fig 33. ADC interface to pins ADC0_IN[n] Table 29. ADC interface components Component Range Description Rcmp 90 to 300 Switch-on resistance for the comparator input switch. Varies with temperature, input voltage, and process. Rsw 500 to 2 k Switch-on resistance for channel selection switch. Varies with temperature, input voltage, and process. C1 110 fF Parasitic capacitance from the ADC block level. C2 80 fF Parasitic capacitance from the ADC block level. C3 1.6 pF Sampling capacitor. 12.2 DAC electrical characteristics Table 30. 10-bit DAC electrical characteristics VDDA = 2.7 V to 3.6 V; Tamb = 40 C to +85 C unless otherwise specified Symbol Parameter Min Typ Max Unit ED differential linearity error - 1 - LSB EL(adj) integral non-linearity - 1.5 - LSB EO offset error - 0.6 - % EG gain error - 0.6 - % CL load capacitance - - 200 pF RL load resistance 1 - - k 12.3 Comparator electrical characteristics Table 31. Comparator characteristics VDDA= 3.0 V and Tamb = 25 C unless noted otherwise. Symbol Parameter Conditions Min Typ Max Unit Static characteristics IDD supply current - 55 - A VIC common-mode input voltage 0 - VDDA V LPC408X_7X Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3.3 -- 16 October 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 107 of 138 LPC408x/7x NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller Table 31. Comparator characteristics ...continued VDDA= 3.0 V and Tamb = 25 C unless noted otherwise. Symbol Parameter Conditions DVO output voltage variation Voffset offset voltage Min Typ Max Unit 0 - VDDA V VIC = 0.1 V - 4 to +4.2 - mV VIC = 1.5 V - 2 mV VIC = 2.8 V - 2.5 - 4 - s - mV Dynamic characteristics tstartup start-up time nominal process tPD propagation delay HIGH to LOW; VDDA = 3.3 V; propagation delay tPD VIC = 0.1 V; 50 mV overdrive input [1] 122 130 142 ns VIC = 0.1 V; rail-to-rail input [1] 173 189 233 ns VIC = 1.5 V; 50 mV overdrive input [1] 101 108 119 ns VIC = 1.5 V; rail-to-rail input [1] 114 127 162 ns VIC = 2.9 V; 50 mV overdrive input [1] 123 134 143 ns VIC = 2.9 V; rail-to-rail input [1] 79 91 120 ns VIC = 0.1 V; 50 mV overdrive input [1] 221 232 254 ns VIC = 0.1 V; rail-to-rail input [1] 59 63 68 ns VIC = 1.5 V; 50 mV overdrive input [1] 183 229 249 ns VIC = 1.5 V; rail-to-rail input [1] 147 174 213 ns VIC = 2.9 V; 50 mV overdrive input [1] 171 192 216 ns VIC = 2.9 V; rail-to-rail input [1] 235 305 450 ns - 5, 10, 20 - mV - 5, 10, 20 - mV - 1.034 - M LOW to HIGH; VDDA = 3.3 V; Vhys hysteresis voltage positive hysteresis; VDDA = 3.0 V; VIC = 1.5 V [2] Vhys hysteresis voltage negative hysteresis; VDDA = 3.0 V; VIC = 1.5 V [2] Rlad ladder resistance - [1] CL = 10 pF; results from measurements on silicon samples over process corners and over the full temperature range Tamb = -40 C to +85 C. [2] Input hysteresis is relative to the reference input channel and is software programmable. Table 32. LPC408X_7X Product data sheet Comparator voltage ladder dynamic characteristics Symbol Parameter Conditions Min Typ Max Unit ts(pu) power-up settling time to 99% of voltage ladder output value [1] - - 30 s ts(sw) switching settling time to 99% of voltage ladder output value [1] - - 15 s [2] [1] Maximum values are derived from worst case simulation (VDDA = 2.6 V; Tamb = 85 C; slow process models). [2] Settling time applies to switching between comparator and ADC channels. All information provided in this document is subject to legal disclaimers. Rev. 3.3 -- 16 October 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 108 of 138 LPC408x/7x NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller Table 33. Comparator voltage ladder reference static characteristics VDDA = 3.3 V; Tamb = -40 C to + 85C. Symbol Parameter Conditions EV(O) output voltage error Internal VDDA supply EV(O) [1] output voltage error Min Typ Max[1] Unit decimal code = 00 0 0 0 % decimal code = 08 0.45 0.5 0.55 % decimal code = 16 0.99 1.1 1.21 % decimal code = 24 1.26 1.4 1.54 % decimal code = 30 1.35 1.5 1.65 % decimal code = 31 1.35 1.5 1.65 % decimal code = 00 0 0 0 % decimal code = 08 0.44 0.4 0.36 % decimal code = 16 0.18 0.2 0.22 % decimal code = 24 0.45 0.5 0.55 % decimal code = 30 0.54 0.6 0.66 % decimal code = 31 0.45 0.5 0.55 % External VDDCMP supply Measured on typical silicon samples with a 2 kHz input signal and overdrive < 100 V. Power switched off to all analog peripherals except the comparator. 13. Application information 13.1 Suggested USB interface solutions Remark: The USB controller is available as a device/Host/OTG controller on parts LPC4088 and LPC4078/76 and as device-only controller on parts LPC4074/72. LPC408X_7X Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3.3 -- 16 October 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 109 of 138 LPC408x/7x NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller VDD(3V3) USB_UP_LED USB_CONNECT LPC40xx SoftConnect switch R1 1.5 k VBUS USB_D+ RS = 33 USB_D- USB-B connector RS = 33 VSS 002aah267 Fig 34. USB interface on a self-powered device VDD(3V3) R2 LPC40xx USB_UP_LED R1 1.5 k VBUS USB_D+ RS = 33 USB_D- RS = 33 USB-B connector VSS 002aah268 Fig 35. USB interface on a bus-powered device LPC408X_7X Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3.3 -- 16 October 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 110 of 138 LPC408x/7x NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller VDD R1 R2 R3 R4 RSTOUT RESET_N VBUS ADR/PSW ID OE_N/INT_N VDD SPEED SUSPEND R4 R5 ISP1302 DP 33 DM 33 R6 USB_SCL1 SCL USB_SDA1 SDA USB_INT1 Mini-AB connector VSSIO, VSSCORE INT_N USB_D+1 USB_D-1 VDD USB_UP_LED1 LPC408x/7x R7 5V VDD IN USB_PPWR2 ENA LM3526-L OUTA FLAGA USB_OVRCR2 VBUS USB_PWRD2 USB_D+2 33 D+ USB_D-2 33 D15 k 15 k USB-A connector VSSIO, VSSCORE VDD USB_UP_LED2 R8 002aah269 Fig 36. USB OTG port configuration: port 1 OTG dual-role device, port 2 host LPC408X_7X Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3.3 -- 16 October 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 111 of 138 LPC408x/7x NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller VDD RSTOUT RESET_N OE_N/INT_N USB_TX_E1 USB_TX_DP1 DAT_VP USB_TX_DM1 SE0_VM RCV USB_RCV1 USB_RX_DP1 USB_RX_DM1 VP VBUS VM ID VDD ISP1302 LPC408x/7x ADR/PSW SPEED DP 33 DM 33 USB MINI-AB connector VSSIO, VSSCORE SUSPEND USB_SCL1 SCL SDA USB_SDA1 INT_N USB_INT1 VDD USB_UP_LED1 002aah270 Fig 37. USB OTG port configuration: VP_VM mode LPC408X_7X Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3.3 -- 16 October 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 112 of 138 LPC408x/7x NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller VDD USB_UP_LED1 VSSIO, VSSCORE USB_D+1 33 D+ USB_D-1 33 D15 k USB-A connector 15 k VDD VBUS USB_PWRD1 USB_OVRCR1 USB_PPWR1 FLAGA ENA OUTA 5V IN LPC408x/7x USB_PPWR2 LM3526-L ENB VDD OUTB FLAGB USB_OVRCR2 VBUS USB_PWRD2 USB_D+2 33 USB_D-2 33 D+ USB-A connector D15 k VSSIO, 15 k VSSCORE VDD USB_UP_LED2 002aah271 Fig 38. USB host port configuration: port 1 and port 2 as hosts LPC408X_7X Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3.3 -- 16 October 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 113 of 138 LPC408x/7x NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller VDD USB_UP_LED1 VSSIO, VSSCORE USB_D+1 33 D+ USB_D-1 33 D15 k USB-A connector 15 k VDD VBUS USB_PWRD1 USB_OVRCR1 USB_PPWR1 FLAGA ENA 5V IN LM3526-L OUTA LPC408x/7x VDD USB_UP_LED2 VDD USB_CONNECT2 VSSIO, VSSCORE USB_D+2 33 D+ USB_D-2 33 D- VBUS USB-B connector VBUS 002aah272 Fig 39. USB device port configuration: port 1 host and port 2 device 13.2 Crystal oscillator XTAL input and component selection The input voltage to the on-chip oscillators is limited to 1.8 V. If the oscillator is driven by a clock in slave mode, it is recommended that the input be coupled through a capacitor with Ci = 100 pF. To limit the input voltage to the specified range, choose an additional capacitor to ground Cg which attenuates the input voltage by a factor Ci/(Ci + Cg). In slave mode, a minimum of 200 mV(RMS) is needed. LPC40xx XTAL1 Ci 100 pF Cg 002aah273 Fig 40. Slave mode operation of the on-chip oscillator LPC408X_7X Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3.3 -- 16 October 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 114 of 138 LPC408x/7x NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller In slave mode the input clock signal should be coupled by means of a capacitor of 100 pF (Figure 40), with an amplitude between 200 mV(RMS) and 1000 mV(RMS). This corresponds to a square wave signal with a signal swing of between 280 mV and 1.4 V. The XTALOUT pin in this configuration can be left unconnected. External components and models used in oscillation mode are shown in Figure 41 and in Table 34 and Table 35. Since the feedback resistance is integrated on chip, only a crystal and the capacitances CX1 and CX2 need to be connected externally in case of fundamental mode oscillation (the fundamental frequency is represented by L, CL and RS). Capacitance CP in Figure 41 represents the parallel package capacitance and should not be larger than 7 pF. Parameters FOSC, CL, RS and CP are supplied by the crystal manufacturer. LPC40xx L XTALIN XTALOUT CL = CP XTAL RS CX2 CX1 002aah274 Fig 41. Oscillator modes and models: oscillation mode of operation and external crystal model used for CX1/CX2 evaluation Table 34. Recommended values for CX1/CX2 in oscillation mode (crystal and external components parameters): low frequency mode Fundamental oscillation frequency FOSC Crystal load capacitance CL Maximum crystal series resistance RS External load capacitors CX1/CX2 1 MHz to 5 MHz 10 pF < 300 18 pF, 18 pF 20 pF < 300 39 pF, 39 pF 30 pF < 300 57 pF, 57 pF 10 pF < 300 18 pF, 18 pF 20 pF < 200 39 pF, 39 pF 30 pF < 100 57 pF, 57 pF 10 MHz to 15 MHz 10 pF < 160 18 pF, 18 pF 20 pF < 60 39 pF, 39 pF 15 MHz to 20 MHz 10 pF < 80 18 pF, 18 pF 5 MHz to 10 MHz LPC408X_7X Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3.3 -- 16 October 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 115 of 138 LPC408x/7x NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller Table 35. Recommended values for CX1/CX2 in oscillation mode (crystal and external components parameters): high frequency mode Fundamental oscillation frequency FOSC Crystal load capacitance CL Maximum crystal series resistance RS External load capacitors CX1, CX2 15 MHz to 20 MHz 10 pF < 180 18 pF, 18 pF 20 pF < 100 39 pF, 39 pF 10 pF < 160 18 pF, 18 pF 20 pF < 80 39 pF, 39 pF 20 MHz to 25 MHz 13.3 XTAL Printed-Circuit Board (PCB) layout guidelines The crystal should be connected on the PCB as close as possible to the oscillator input and output pins of the chip. Take care that the load capacitors Cx1, Cx2, and Cx3 in case of third overtone crystal usage have a common ground plane. The external components must also be connected to the ground plane. Loops must be made as small as possible in order to keep the noise coupled in via the PCB as small as possible. Also parasitics should stay as small as possible. Smaller values of Cx1 and Cx2 should be chosen according to the increase in parasitics of the PCB layout. 13.4 Standard I/O pin configuration Figure 42 shows the possible pin modes for standard I/O pins with analog input function: * * * * * Digital output driver: Open-drain mode enabled/disabled. Digital input: Pull-up enabled/disabled. Digital input: Pull-down enabled/disabled. Digital input: Repeater mode enabled/disabled. Analog input. The default configuration for standard I/O pins is input with pull-up enabled. The weak MOS devices provide a drive capability equivalent to pull-up and pull-down resistors. LPC408X_7X Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3.3 -- 16 October 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 116 of 138 LPC408x/7x NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller VDD VDD open-drain enable pin configured as digital output driver strong pull-up output enable ESD data output PIN strong pull-down ESD VSS VDD weak pull-up pull-up enable pin configured as digital input weak pull-down repeater mode enable pull-down enable data input select analog input pin configured as analog input analog input 002aaf272 Fig 42. Standard I/O pin configuration with analog input 13.5 Reset pin configuration VDD VDD VDD Rpu reset ESD 20 ns RC GLITCH FILTER PIN ESD VSS 002aaf274 Fig 43. Reset pin configuration 13.6 Reset pin configuration for RTC operation Under certain circumstances, the RTC may temporarily pause and lose fractions of a second during the rising and falling edges of the RESET signal. LPC408X_7X Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3.3 -- 16 October 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 117 of 138 LPC408x/7x NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller To eliminate the loss of time counts in the RTC due to voltage swing or ramp rate of the RESET signal, connect an RC filter between the RESET pin and the external reset input. 10 k RESET pin 0.1 F External RESET input 002aag552 Fig 44. Reset input with RC filter LPC408X_7X Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3.3 -- 16 October 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 118 of 138 LPC408x/7x NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller 14. Package outline LQFP208; plastic low profile quad flat package; 208 leads; body 28 x 28 x 1.4 mm SOT459-1 c y X A 105 156 157 104 ZE e E HE (A 3) A A2 A1 wM Lp bp L detail X pin 1 index 208 53 1 52 v M A ZD wM bp e D B HD v M B 0 5 10 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e mm 1.6 0.15 0.05 1.45 1.35 0.25 0.27 0.17 0.20 0.09 28.1 27.9 28.1 27.9 0.5 HD HE 30.15 30.15 29.85 29.85 L Lp v w y ZD ZE 1 0.75 0.45 0.12 0.08 0.08 1.43 1.08 1.43 1.08 7o o 0 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT459-1 136E30 MS-026 JEITA EUROPEAN PROJECTION ISSUE DATE 00-02-06 03-02-20 Fig 45. Package outline SOT459-1 (LQFP208) LPC408X_7X Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3.3 -- 16 October 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 119 of 138 LPC408x/7x NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller TFBGA208: plastic thin fine-pitch ball grid array package; 208 balls; body 15 x 15 x 0.7 mm B D SOT950-1 A ball A1 index area A2 A E A1 detail X e1 v w b e M M C C A B C y y1 C U T R P N M L K J H G F E D C B A e e2 ball A1 index area 1 3 2 4 5 6 7 8 9 10 11 12 13 14 15 16 17 X 0 5 10 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max A1 A2 b D E e e1 e2 v w y y1 mm 1.2 0.4 0.3 0.8 0.6 0.5 0.4 15.1 14.9 15.1 14.9 0.8 12.8 12.8 0.15 0.08 0.12 0.1 OUTLINE VERSION SOT950-1 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 06-06-01 06-06-14 --- Fig 46. Package outline SOT950-1 (TFBGA208) LPC408X_7X Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3.3 -- 16 October 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 120 of 138 LPC408x/7x NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller TFBGA180: thin fine-pitch ball grid array package; 180 balls SOT570-3 A B D ball A1 index area E A2 A A1 detail X e1 e 1/2 e v w b M M C C A B C y y1 C P N M L K J H G F E D C B A ball A1 index area e e2 1/2 e 1 2 3 4 5 6 7 8 9 10 11 12 13 X 14 0 5 10 mm scale DIMENSIONS (mm are the original dimensions) UNIT mm max nom min A A1 A2 b D E e e1 e2 v w y y1 1.20 1.06 0.95 0.40 0.35 0.30 0.80 0.71 0.65 0.50 0.45 0.40 12.1 12.0 11.9 12.1 12.0 11.9 0.8 10.4 10.4 0.15 0.05 0.12 0.1 OUTLINE VERSION REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 08-07-09 10-04-15 SOT570-3 Fig 47. Package outline SOT570-3 (TFBGA180) LPC408X_7X Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3.3 -- 16 October 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 121 of 138 LPC408x/7x NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller LQFP144: plastic low profile quad flat package; 144 leads; body 20 x 20 x 1.4 mm SOT486-1 c y X A 73 72 108 109 ZE e E HE A A2 (A 3) A1 wM Lp bp L pin 1 index detail X 37 144 1 36 v M A ZD wM bp e D B HD v M B 0 5 10 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e mm 1.6 0.15 0.05 1.45 1.35 0.25 0.27 0.17 0.20 0.09 20.1 19.9 20.1 19.9 0.5 HD HE 22.15 22.15 21.85 21.85 L Lp v w y 1 0.75 0.45 0.2 0.08 0.08 Z D(1) Z E(1) 1.4 1.1 1.4 1.1 7o o 0 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT486-1 136E23 MS-026 JEITA EUROPEAN PROJECTION ISSUE DATE 00-03-14 03-02-20 Fig 48. Package outline SOT486-1 (LQFP144) LPC408X_7X Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3.3 -- 16 October 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 122 of 138 LPC408x/7x NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller LQFP100: plastic low profile quad flat package; 100 leads; body 14 x 14 x 1.4 mm SOT407-1 c y X A 51 75 50 76 ZE e E HE A A2 (A 3) A1 w M bp Lp pin 1 index L 100 detail X 26 1 25 ZD e v M A w M bp D B HD v M B 0 5 10 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e mm 1.6 0.15 0.05 1.45 1.35 0.25 0.27 0.17 0.20 0.09 14.1 13.9 14.1 13.9 0.5 HD HE 16.25 16.25 15.75 15.75 L Lp v w y 1 0.75 0.45 0.2 0.08 0.08 Z D (1) Z E (1) 1.15 0.85 1.15 0.85 7o o 0 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT407-1 136E20 MS-026 JEITA EUROPEAN PROJECTION ISSUE DATE 00-02-01 03-02-20 Fig 49. Package outline SOT407-1 (LQFP100) LPC408X_7X Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3.3 -- 16 October 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 123 of 138 LPC408x/7x NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller LQFP80: plastic low profile quad flat package; 80 leads; body 12 x 12 x 1.4 mm SOT315-1 c y X A 60 41 40 Z E 61 e E HE A A2 (A 3) A1 w M bp Lp L pin 1 index 80 21 detail X 20 1 ZD e v M A w M bp D B HD v M B 0 5 10 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e mm 1.6 0.16 0.04 1.5 1.3 0.25 0.27 0.13 0.18 0.12 12.1 11.9 12.1 11.9 0.5 HD HE 14.15 14.15 13.85 13.85 L Lp v w y 1 0.75 0.30 0.2 0.15 0.1 Z D (1) Z E (1) 1.45 1.05 7o o 0 1.45 1.05 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT315-1 136E15 MS-026 JEITA EUROPEAN PROJECTION ISSUE DATE 00-01-19 03-02-25 Fig 50. Package outline SOT315-1 (LQFP80) LPC408X_7X Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3.3 -- 16 October 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 124 of 138 LPC408x/7x NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller TFBGA80: plastic thin fine-pitch ball grid array package; 80 balls A B D SOT1328-1 ball A1 index area A A2 E A1 detail X e1 C e 1/2 e C A B C Ov Ow b y y1 C K J e H G F e2 E D 1/2 e C B A ball A1 index area 1 2 3 4 5 6 7 8 9 10 X 0 5 mm scale Dimensions (mm are the original dimensions) Unit mm A A1 A2 b max 1.15 0.35 0.80 0.45 nom 1.00 0.30 0.70 0.40 min 0.90 0.25 0.65 0.35 D E 7.1 7.0 6.9 7.1 7.0 6.9 e e1 e2 v w y 0.65 5.85 5.85 0.15 0.05 0.08 y1 0.1 sot1328-1_po Outline version References IEC JEDEC JEITA European projection Issue date 12-05-07 12-06-14 SOT1328-1 Fig 51. Package outline SOT1328-1 (TFBGA80) LPC408X_7X Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3.3 -- 16 October 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 125 of 138 LPC408x/7x NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller 15. Soldering Footprint information for reflow soldering of LQFP208 package SOT459-1 Hx Gx P2 Hy (0.125) P1 Gy By Ay C D2 (8x) D1 Bx Ax Generic footprint pattern Refer to the package outline drawing for actual layout solder land occupied area DIMENSIONS in mm P1 0.500 P2 Ax Ay Bx By 0.560 31.300 31.300 28.300 28.300 C D1 D2 1.500 0.280 0.400 Gx Gy Hx Hy 28.500 28.500 31.550 31.550 sot459-1_fr Fig 52. Reflow soldering of the LQFP208 package LPC408X_7X Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3.3 -- 16 October 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 126 of 138 LPC408x/7x NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller Footprint information for reflow soldering of TFBGA180 package SOT570-3 Hx P P Hy see detail X solder land (SL) solder paste deposit (SP) solder land plus solder paste SL = SP solder resist opening (SR) SR occupied area detail X Dimensions in mm P SL SP SR Hx Hy 0.80 0.40 0.40 0.50 12.30 12.30 Issue date Recommend stencil thickness: 0.1 mm 14-01-30 15-08-27 sot570-3_fr Fig 53. Reflow soldering of the TFBGA180 package LPC408X_7X Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3.3 -- 16 October 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 127 of 138 LPC408x/7x NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller Footprint information for reflow soldering of LQFP144 package SOT486-1 Hx Gx P2 Hy (0.125) P1 Gy By Ay C D2 (8x) D1 Bx Ax Generic footprint pattern Refer to the package outline drawing for actual layout solder land occupied area DIMENSIONS in mm P1 0.500 P2 Ax Ay Bx By 0.560 23.300 23.300 20.300 20.300 C D1 D2 1.500 0.280 0.400 Gx Gy Hx Hy 20.500 20.500 23.550 23.550 sot486-1_fr Fig 54. Reflow soldering of the LQFP144 package LPC408X_7X Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3.3 -- 16 October 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 128 of 138 LPC408x/7x NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller Footprint information for reflow soldering of LQFP100 package SOT407-1 Hx Gx P2 Hy (0.125) P1 Gy By Ay C D2 (8x) D1 Bx Ax Generic footprint pattern Refer to the package outline drawing for actual layout solder land occupied area DIMENSIONS in mm P1 0.500 P2 Ax Ay Bx By 0.560 17.300 17.300 14.300 14.300 C D1 D2 1.500 0.280 0.400 Gx Gy Hx Hy 14.500 14.500 17.550 17.550 sot407-1 Fig 55. Reflow soldering of the LQFP100 package LPC408X_7X Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3.3 -- 16 October 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 129 of 138 LPC408x/7x NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller Footprint information for reflow soldering of LQFP80 package SOT315-1 Hx Gx P2 Hy (0.125) P1 Gy By Ay C D2 (8x) D1 Bx Ax Generic footprint pattern Refer to the package outline drawing for actual layout solder land occupied area DIMENSIONS in mm P1 0.500 P2 Ax Ay Bx By 0.560 15.300 15.300 12.300 12.300 C D1 D2 1.500 0.280 0.400 Gx Gy Hx Hy 12.500 12.500 15.550 15.550 sot315-1_fr Fig 56. Reflow soldering of the LQFP80 package LPC408X_7X Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3.3 -- 16 October 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 130 of 138 LPC408x/7x NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller 16. Abbreviations Table 36. LPC408X_7X Product data sheet Abbreviations Acronym Description ADC Analog-to-Digital Converter AHB Advanced High-performance Bus AMBA Advanced Microcontroller Bus Architecture APB Advanced Peripheral Bus BOD BrownOut Detection CAN Controller Area Network DAC Digital-to-Analog Converter DMA Direct Memory Access EOP End Of Packet ETM Embedded Trace Macrocell GPIO General Purpose Input/Output GPS Global Positioning System HVAC Heating, Venting, and Air Conditioning IRC Internal RC IrDA Infrared Data Association JTAG Joint Test Action Group MAC Media Access Control MIIM Media Independent Interface Management OHCI Open Host Controller Interface OTG On-The-Go PHY Physical Layer PLC Programmable Logic Controller PLL Phase-Locked Loop PWM Pulse Width Modulator RMII Reduced Media Independent Interface SE0 Single Ended Zero SPI Serial Peripheral Interface SSI Serial Synchronous Interface SSP Synchronous Serial Port TCM Tightly Coupled Memory TTL Transistor-Transistor Logic UART Universal Asynchronous Receiver/Transmitter USB Universal Serial Bus All information provided in this document is subject to legal disclaimers. Rev. 3.3 -- 16 October 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 131 of 138 LPC408x/7x NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller 17. References LPC408X_7X Product data sheet [1] LPC408x/7x User manual UM10562: http://www.nxp.com/documents/user_manual/UM10562.pdf [2] LPC407x/8x Errata sheet: http://www.nxp.com/documents/errata_sheet/ES_LPC407X_8X.pdf [3] Technical note ADC design guidelines: http://www.nxp.com/documents/technical_note/TN00009.pdf All information provided in this document is subject to legal disclaimers. Rev. 3.3 -- 16 October 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 132 of 138 LPC408x/7x NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller 18. Revision history Table 37. Revision history Document ID Release date Data sheet status LPC408X_7X v.3.3 20151016 Product data sheet Modifications: LPC408X_7X v.3.2 Modifications: LPC408X_7X v.3.1 Modifications: LPC408X_7X v.3 Modifications: * Change notice Supersedes LPC408X_7X v.3.2 Corrected max value of tv(Q) (data output valid time) in SPI mode to 3*Tcy(PCLK) + 6.3 ns. Was: 3*Tcy(PCLK) + 2.5 ns. See Table 22 "Dynamic characteristics: SSP pins in SPI mode". 20150818 Product data sheet LPC408X_7X v.3.1 * Updated max value of tv(Q) (data output valid time) in SPI mode to 3*Tcy(PCLK) + 2.5 ns. See Table 22 "Dynamic characteristics: SSP pins in SPI mode". * Updated the ordering options table: Type number LPC4078FBD80, LQFP80 package does not support SD/MMC. See Table 2 "Ordering options". 20140901 Product data sheet CIN 201404014I LPC408X_7X v.3 * * * SPIFI timing diagram corrected and specified for mode 0. See Table 27. * * * ADC conversion rate in burst mode added to Table 28 "12-bit ADC characteristics". Added values for power consumption on SPIFI. See Table 12. Parameter tsu(D) updated in Table 16 "Dynamic characteristics: Dynamic external memory interface, read strategy bits (RD bits) = 00": Minimum value changed to (FBCLKDLY + 1) 0.25 - 0.9. Maximum value removed. Removed max value from parameter th(D) in Table 15. Removed min value from parameter tdeact in Table 15. 20140501 * * * Product data sheet CIN 201404014I LPC408X_7X v.2 Added TFBGA80 to features list. Added Section 11.11 "SPIFI". Table 3: - Added function SSP2_SCK to pin P5[2]. - Added function SSP2_SSEL to pin P5[3]. - Updated pin description of STCLK. - 5 ns glitch filter changed to 10 ns for EINTx pins. - LQFP80 pin 12 changed from P2[30] to DNC. * Table 11: Added Table note 3 "VDDA and VREFP should be tied to VDD(3V3) if the ADC and DAC are not used.". * Table 28: Added Table note 1 "VDDA and VREFP should be tied to VDD(3V3) if the ADC and DAC are not used.". * * * Section 7.37.2 "Brownout detection": Updated BOD interrupt and reset values. Table 15: Added typical specs. Table 16: - Added typical specs - Removed "All programmable delays EMCDLYCTL are bypassed" from table title. * Table 17: - Added typical specs - Removed "All programmable delays EMCDLYCTL are bypassed" from table title. * LPC408X_7X Product data sheet Table note 9 added in Table 28 "12-bit ADC characteristics". All information provided in this document is subject to legal disclaimers. Rev. 3.3 -- 16 October 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 133 of 138 LPC408x/7x NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller Table 37. Revision history ...continued Document ID Release date Data sheet status Change notice Supersedes LPC408X_7X v.2 20130703 Product data sheet - LPC408X_7X v.1.1 * * Added LQFP100 and TFBGA80. Table 3: - Removed overbar from NMI. - Added minimum reset pulse width of 50 ns to RESET pin. - Updated Table note 14 for RTCX pins (32 kHz crystal must be used to operate RTC). - Added boundary scan information to description for RESET pin. * Table 11: - Updated typ numbers for IDD(REG)(3V3) and IBAT. - Added max values for deep sleep, power down, and deep PD for IBAT. * * * Table 15, Table note 3: Changed Tcy(clk) = 1/CCLK to Tcy(clk) = 1/EMC_CLK. Table 21: Removed reference to RESET pin from Table note 1. Table 22: - Removed Tcy(PCLK) spec; already given by the maximum chip frequency. - Changed min clock cycle time for SSP slave from 120 to 100. - Updated Table note 1 and Table note 3. * * * LPC408X_7X v.1.1 Modifications: LPC408X_7X v.1 LPC408X_7X Product data sheet Section 7.24.1 "Features": Changed max speed for SSP master from 60 to 33. Updated EMC timing specs to CL = 30 pF in Table 15, Table 16, Table 17, and Table 18. SOT570-2 obsolete; replaced with SOT570-3. 20121114 * Product data sheet - LPC408X_7X v.1 - - Changed data sheet status to Product. 20120917 Objective data sheet All information provided in this document is subject to legal disclaimers. Rev. 3.3 -- 16 October 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 134 of 138 LPC408x/7x NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller 19. Legal information 19.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term `short data sheet' is explained in section "Definitions". [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 19.2 Definitions Draft -- The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet -- A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification -- The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet. 19.3 Disclaimers Limited warranty and liability -- Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. NXP Semiconductors takes no responsibility for the content in this document if provided by an information source outside of NXP Semiconductors. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors' aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes -- NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. LPC408X_7X Product data sheet Suitability for use -- NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors and its suppliers accept no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. Applications -- Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer's sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer's applications and products planned, as well as for the planned application and use of customer's third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer's applications or products, or the application or use by customer's third party customer(s). Customer is responsible for doing all necessary testing for the customer's applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer's third party customer(s). NXP does not accept any liability in this respect. Limiting values -- Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale -- NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer's general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. No offer to sell or license -- Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. All information provided in this document is subject to legal disclaimers. Rev. 3.3 -- 16 October 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 135 of 138 LPC408x/7x NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller Export control -- This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Non-automotive qualified products -- Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors' warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond NXP Semiconductors' specifications such use shall be solely at customer's own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors' standard warranty and NXP Semiconductors' product specifications. 19.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. I2C-bus -- logo is a trademark of NXP B.V. 20. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com LPC408X_7X Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3.3 -- 16 October 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 136 of 138 LPC408x/7x NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller 21. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 4 Ordering information . . . . . . . . . . . . . . . . . . . . . 5 5 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 7 6 Pinning information . . . . . . . . . . . . . . . . . . . . . . 8 6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . 10 7 Functional description . . . . . . . . . . . . . . . . . . 51 7.1 Architectural overview . . . . . . . . . . . . . . . . . . 51 7.2 ARM Cortex-M4 processor . . . . . . . . . . . . . . . 51 7.3 ARM Cortex-M4 Floating Point Unit (FPU) . . . 51 7.4 On-chip flash program memory . . . . . . . . . . . 51 7.5 EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 7.6 On-chip SRAM . . . . . . . . . . . . . . . . . . . . . . . . 52 7.7 Memory Protection Unit (MPU). . . . . . . . . . . . 52 7.8 Memory map. . . . . . . . . . . . . . . . . . . . . . . . . . 52 7.9 Nested Vectored Interrupt Controller (NVIC) . 53 7.9.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 7.9.2 Interrupt sources. . . . . . . . . . . . . . . . . . . . . . . 53 7.10 Pin connect block . . . . . . . . . . . . . . . . . . . . . . 54 7.11 External Memory Controller (EMC). . . . . . . . . 54 7.11.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 7.12 General purpose DMA controller . . . . . . . . . . 56 7.12.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 7.13 CRC engine . . . . . . . . . . . . . . . . . . . . . . . . . . 57 7.13.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 7.14 LCD controller. . . . . . . . . . . . . . . . . . . . . . . . . 58 7.14.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 7.15 Ethernet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 7.15.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 7.16 USB interface . . . . . . . . . . . . . . . . . . . . . . . . . 60 7.16.1 USB device controller . . . . . . . . . . . . . . . . . . . 60 7.16.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 7.16.2 USB host controller. . . . . . . . . . . . . . . . . . . . . 60 7.16.2.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 7.16.3 USB OTG controller . . . . . . . . . . . . . . . . . . . . 61 7.16.3.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 7.17 SD/MMC card interface . . . . . . . . . . . . . . . . . 61 7.17.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 7.18 Fast general purpose parallel I/O . . . . . . . . . . 61 7.18.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 7.19 12-bit ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 7.19.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 7.20 10-bit DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 7.20.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 7.21 Comparator. . . . . . . . . . . . . . . . . . . . . . . . . . . 63 7.21.1 7.22 7.22.1 7.23 7.23.1 7.24 7.24.1 7.25 7.25.1 7.26 7.26.1 7.27 7.27.1 7.28 7.28.1 7.29 7.29.1 7.30 7.31 7.31.1 7.32 7.33 7.33.1 7.34 7.34.1 7.35 7.35.1 7.36 7.36.1 7.36.1.1 7.36.1.2 7.36.1.3 7.36.1.4 7.36.2 7.36.3 7.36.4 7.36.4.1 7.36.4.2 7.36.4.3 7.36.4.4 7.36.4.5 7.36.5 7.36.6 7.37 7.37.1 7.37.2 7.37.3 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . UART0/1/2/3 and USART4 . . . . . . . . . . . . . . Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . SPIFI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . SSP serial I/O controller. . . . . . . . . . . . . . . . . Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . I2C-bus serial I/O controllers . . . . . . . . . . . . . Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . I2S-bus serial I/O controllers . . . . . . . . . . . . . Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . CAN controller and acceptance filters . . . . . . Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . General purpose 32-bit timers/external event counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pulse Width Modulator (PWM). . . . . . . . . . . . Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . Motor control PWM . . . . . . . . . . . . . . . . . . . . Quadrature Encoder Interface (QEI) . . . . . . . Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . ARM Cortex-M4 system tick timer . . . . . . . . . Windowed WatchDog Timer (WWDT) . . . . . . Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . RTC and backup registers . . . . . . . . . . . . . . . Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . Event monitor/recorder . . . . . . . . . . . . . . . . . Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clocking and power control . . . . . . . . . . . . . . Crystal oscillators . . . . . . . . . . . . . . . . . . . . . . Internal RC oscillator . . . . . . . . . . . . . . . . . . . Main oscillator . . . . . . . . . . . . . . . . . . . . . . . . RTC oscillator . . . . . . . . . . . . . . . . . . . . . . . . Watchdog oscillator . . . . . . . . . . . . . . . . . . . . Main PLL (PLL0) and Alternate PLL (PLL1) . Wake-up timer . . . . . . . . . . . . . . . . . . . . . . . . Power control . . . . . . . . . . . . . . . . . . . . . . . . . Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . Deep-sleep mode. . . . . . . . . . . . . . . . . . . . . . Power-down mode . . . . . . . . . . . . . . . . . . . . . Deep power-down mode . . . . . . . . . . . . . . . . Wake-up Interrupt Controller (WIC) . . . . . . . . Peripheral power control . . . . . . . . . . . . . . . . Power domains . . . . . . . . . . . . . . . . . . . . . . . System control . . . . . . . . . . . . . . . . . . . . . . . . Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Brownout detection . . . . . . . . . . . . . . . . . . . . Code security (Code Read Protection - CRP) 63 63 63 64 64 64 65 65 65 65 66 66 66 67 67 67 68 68 69 69 69 69 70 70 70 71 71 71 71 72 72 73 73 73 74 74 74 75 75 76 76 76 76 78 78 78 78 continued >> LPC408X_7X Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3.3 -- 16 October 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 137 of 138 LPC408x/7x NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller 7.37.4 7.37.5 7.37.6 7.37.7 7.38 8 9 10 10.1 10.2 10.3 11 11.1 11.2 11.3 11.4 11.5 11.6 11.7 11.8 11.9 11.10 11.11 12 12.1 12.2 12.3 13 13.1 13.2 13.3 13.4 13.5 13.6 14 15 16 17 18 19 19.1 19.2 19.3 19.4 20 21 APB interface . . . . . . . . . . . . . . . . . . . . . . . . . 79 AHB multilayer matrix . . . . . . . . . . . . . . . . . . . 79 External interrupt inputs . . . . . . . . . . . . . . . . . 79 Memory mapping control . . . . . . . . . . . . . . . . 79 Debug control . . . . . . . . . . . . . . . . . . . . . . . . . 79 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 79 Thermal characteristics . . . . . . . . . . . . . . . . . 80 Static characteristics. . . . . . . . . . . . . . . . . . . . 82 Power consumption . . . . . . . . . . . . . . . . . . . . 85 Peripheral power consumption . . . . . . . . . . . . 86 Electrical pin characteristics . . . . . . . . . . . . . . 88 Dynamic characteristics . . . . . . . . . . . . . . . . . 90 Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . 90 External memory interface . . . . . . . . . . . . . . . 90 External clock . . . . . . . . . . . . . . . . . . . . . . . . . 96 Internal oscillators. . . . . . . . . . . . . . . . . . . . . . 97 I/O pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 SSP interface . . . . . . . . . . . . . . . . . . . . . . . . . 97 I2C-bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 I2S-bus interface . . . . . . . . . . . . . . . . . . . . . . 101 LCD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 SD/MMC . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 SPIFI. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 Characteristics of the analog peripherals . . 104 ADC electrical characteristics . . . . . . . . . . . . 104 DAC electrical characteristics . . . . . . . . . . . 107 Comparator electrical characteristics . . . . . . 107 Application information. . . . . . . . . . . . . . . . . 109 Suggested USB interface solutions . . . . . . . 109 Crystal oscillator XTAL input and component selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 XTAL Printed-Circuit Board (PCB) layout guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 Standard I/O pin configuration . . . . . . . . . . . 116 Reset pin configuration . . . . . . . . . . . . . . . . . 117 Reset pin configuration for RTC operation . . 117 Package outline . . . . . . . . . . . . . . . . . . . . . . . 119 Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 131 References . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 Revision history . . . . . . . . . . . . . . . . . . . . . . . 133 Legal information. . . . . . . . . . . . . . . . . . . . . . 135 Data sheet status . . . . . . . . . . . . . . . . . . . . . 135 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 135 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . 136 Contact information. . . . . . . . . . . . . . . . . . . . 136 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section `Legal information'. (c) NXP Semiconductors N.V. 2015. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 16 October 2015 Document identifier: LPC408X_7X Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: NXP: LPC4078FBD208,551 LPC4078FET208,551 LPC4088FET208,551 LPC4088FBD208,551 LPC4074FBD80,551 LPC4078FBD100E LPC4078FBD144,551 LPC4076FBD144E LPC4088FET180,551 LPC4088FBD144,551 LPC4078FBD80,551 LPC4076FET180,551 LPC4072FBD80E LPC4074FBD144,551 LPC4078FET180,551 LPC4076FET180K