19-2887; Rav. 3 11/92 General Description The MAX900-903 high-speed, low-power, single/dual/ quad voltage comparators feature differential analog inputs and TTL logic outputs with active internal pull-ups. Fast propagation delay (8ns typ at 5mV overdrive) makes the MAX900-903 ideal for fast A/D converters and sampling circuits, line recaivers, V/F converters, and many other data-dis- crimination applications. All comparators can be powered from separate analog and digital power supplies or from a single MA AAI/VI High-Speed, Low-Power Voltage Comparators Features 8ns Typ Propagation Delay 4 18mW/Comparator Power Consumption (Typ at +5V) @ Separate Analog and Digital Supplies + Flexible Analog Supply: +5V to +10V or t5V Input Range Includes Negative Supply Rail 4 TTL Compatible Outputs TTL Compatible Latch Inputs (Except MAX901) combined supply voltage. The anafog input Ordering Information common-mode range Includes the negative rail, al- lowing ground sensing when powered from a single PART TEMP. RANGE PIN-PACKAGE supply, The MAX900-903 consume 18mW per com- MAXS00ACPP O'S to +70C 20 Plastic DIP parater when powered from +5V. MAXS00BCPP O'Cto+70C -20 Plastic DIP The MAX900-903 are equipped with independent MAX9COACWR OC to +70C 20 Wide SO TTL compatible latch inputs. The comparator output MAXOOOBCWP OCto+70C 20 Wide SO states are held when the latch inputs are driven low. - : : The MAX901 provides the same performance as the MAX900BC/D O'C to +70C Dice MAX900, MAX902, and MAX903 with the exception MAX9O0AEPP -40C to +85C 20 Plastic DIP of the latches. MAXS00BEPP -40C to +85C 20 Plastic DIP App fications MAXSOQAEWP 40C to +85C 20 Wide SO High-Si dAIDC rt MAXSOQOBEWP -40C to +85C 20 Wide SO igh-pee onveriers MAX00AMJP S5Cto+125C _ 20CERDIP High-Speed V/F Converters MAXS00BMJP BSCto +125 20CERDIP Line Receivers Ordering information continued at end of data sheet. Threshold Detectors Contact factory for dice specifications. Input Trigger Circuitry High-Speed Data Sampling PWM Circuits Pin Configurations TOP VIEW ncn MAX901 aU VS rd MAX903 IN-fA) Fr Fg] IN-(0) -(a) [1] ha] Vec** 7 Ne (A) [2 2h Fg] IN+(0) ine (a [2 3} NC. Veo" U1 [a] Yoo" eno [3] 7X Ai ha] Vec** cno [SYN 7 2] OUT.) me (2 [7] out our [a 3} out (D) carcnay [41 a B Tra) LaTcH @) N- [3] |. re} exo out te) [BIg Fra] Our(c) outta) [5 / \\ fio] vo" ve [4] Ps) vation ve" al si Noo" ne. [6 Pa) (8 IN+ (8) [7] Clio} (Cc) ve" [7, 8 IN-(B) DIP/SO in- (8) [a] Ja] iN-(C) PISO DIFISO *. ANALOG V- AND SUBSTRATE Pin Gonfigurations continued on page 12 TAL ve PA AXLAA Maxim integrated Products 1 For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800 06/206/106/006XVNMAX900/90 1/902/903 High-Speed, Low-Power Voltage Comparators ABSOLUTE MAXIMUM RATINGS (Note 1) Analog Supply Voltage (Vcc to VEE) 6.66. ee +12V Digita! Supply Voltage (VoD to GND}.................. +7V Differantial Input Voltage .......... [VEE-0.2V ] to [Vec+0.2V] Common-Mode Input Voltages ...... [VeE-0.2V } to (Vec+0.2V) Latch Input Voltage (MAX900/902/903 only} -9.2V to [(Von+0.2V) Output Short-Circuit Duration toGND...... ce eee ete eee eens Indefinite TOVDD 0 cece eee een ete ttt eeae 1 min Internal Power Dissipation ..................00000e 500mW Derata ahova +100C 2... 10mWwFC Operating Temperature Ranges: MAXSO00-S03_C_ wee 0'C to +70C MAXS00-903_EF eee -40C to +85'C. MAXS00-GO3_M_ 0 we eee -55C to +125'C Junction Temperature (Tj). ..............-- 65C to +160C Storage Temperature Range .............. -65C to +150C Laad Tamperature (soldering, 10sec).............. +300C Note 1: Absolute maximum ratings apply to both packaged parts and dice, unless otherwise noted. Stresses be d those listed under Absolute Maximum Ratings" may cause permanent damage to the device. Thesa are stress ratings only. and functional operation of the devica at these or any other conditions beyond those indicatsd in the operational sections of the specifications is not imp. ied, Exposure to absolute maximum rating conditions for extended pariods may affect device reliability. ELECTRICAL CHARACTERISTICS (Veco = +5V, Vee = -5V, Vop = +5V, LE1-LE4 = Logic High, Ta = +25C, unless otherwise noted.) MAXSO0A/01A MAX9S00B/901B/902/903 PARAMETER SYMBOL] CONDITIONS UNITS MIN TYP MAX MIN TYP MAX Input Offset Voltage Vos vee 5 oN; 0.5 2.0 1.0 4.0 mv Input Bias Currant IB liN+ oF FN. 3 6 4 10 pA Input Offset Current los VOM = OV. 50 250 100 500 na Vo = 1.4V Input Voltage Range VCM (Note 2) VEE-0.1 Vec-2.25| VeE-0.1 Vec-2.25| V -6V<VomM<+2.75, Common-Mode _ Rejection Ratio CMRA Note 3) 50 150 75 250 Wyn FPower-Supply Rejection Ratio PSRR {Note 3) 50 150 100 250 pV Output High Voltage VoH Neen 24 35 24 35 V Output Low Voltage Vo. | (Ne 03 04 03 04 | Vv Latch Input Voltage High VLH (Note 4) 1.4 2.0 1.4 2.0 V Latch Input Voltage Low Vu (Note 4} 0.8 14 08 1.4 V Latch Input Current High LH (Note a 1 20 1 20 pA Latch Input Current Low ILL Note is 1 20 1 20 pA MA AXLAAHi: Low-Power Voltage Comparators ELECTRICAL CHARACTERISTICS (continued) (Vcc = +5V, VEE = -5V, Vop = +5, LE1-LE4 = Logic High, Ta = +25C, unless otherwise noted.) nA| aaxoo2 MAX03 PARAMETER SYMBOL | CONDITIONS UNITS MIN TYP MAX |MIN TYP MAX) MIN TYP MAX Positive Analog Supply Current Icc (Note 8) 10 15 5 8 25 4 mA Negative Analog Supply Current IEE (Note 8) 7 12 3.5 6 2 3 mA, Digital Supply Current IDD (Note 8) 4 6 2 3 1 1.5) mA Power Dissipation Pp | YOC=VDb= +S, 70 105 35 55 18 28. | mw VEE = OV TIMING CHARACTERISTICS (Voc = +5V, Vee = -5V, Vop = +5V, LE1-LE4 = Logie High, Ta = +25C, unless otherwise noted.) MAXSODA/MAXSO1A MAX902 MAX903 PARAMETER SYMBOL, CONDITIONS |MAXS00B/MAx901B UNITS MIN TYP MAX | MIN TYP MAX| MIN TYP MAX Vob = Smv, Input-to-Qutput High CL = 15pF, Response Time tod+ lo = 2mA 8 10 8 10 8 10 ns {Note 5) Vop = 5mvV, Input-to-Output Low _ C_ = 15pF, Response Time toc lo = 2mA 8 10 5 10 $1 ns (Note 5) Difference inResponse | 4.44 | (Notes 5, 6) 05 20 05 20 05 20| ns Time Between Outputs P ' , HenDeka toOutput | ipg+(D) | (Notes 4, 7) 10 10 10 ns Lae bee to Output | t54-(D) | (Notes 4, 7) 12 12 12 ns Minimum Setup Time ts (Notes 4, 7) 2 2 2 ns Minimum Hold Time th (Notes 4, 7) 1 1 1 ns Minimum Latch Disable Pulse Width tow(D) | (Notes 4, 7) 10 10 10 ns Note 2: The input common-mode valtage and input signal voltages should not be allowed to go negative by more than 0.2V below VEE The upper end of the common-mode voltage range is typically Voc-2V, but either or both inputs can go to a maximum of Voc+0.2 without damage. Note 3: Note 4: Note 5: Note 6: Note 7: Note &: Tested for +4.75V<Vcc<+5.25V, and -5.25V<VeEE<-4.75 with Vop = +5V, although permissible analog power-supply range is +4.78V<Voc<+ 10.5V for single-supply operation with VEE grounded. Specification does not apply to MAX901. Guaranteed by design. Times are for 100mV step inputs (see propagation delay characteristics in Figures 2 and 3). Maximum difference in propagation delay between any of the four comparators in the MAX900/90 1/982/903, See Timing Diagram (Figure 2). Owing to the difficult and critical nature of switching measurements involving the latch, these parameters cannot be tested in a production environment. Typical specifications listed are taken from measurements using a high-speed test-jig. los tested for i eVeVeCe+10.5V with VEE grounded. lee tested for -5.25V<VEE<-4,75V with Vcc = +5V. lbp tested for +4.75V<Vpp<+5.25V with the worst-case condition of all four comparator outputs at logic low. AA AXLAA 3 06/Z06/1 0G/O06XVNMAX900/901/902/903 High-Speed, Low-Power Voltage Comparators ELECTRICAL CHARACTERISTICS (Vcc = +5V, Vee = -5V, Vop = +5V, LE1-LE4 = Logic High; Ta = Full Operating Temperature, unless otherwise noted.) MAXS00A/901 A MAX800B/901 8/902/903 PARAMETER SYMBOL; CONDITIONS UNITS MIN TYP MAX MIN TYP MAX Input Offset Voltage Vos vee m 1 3 2 6 mv Input Bias Current 1B line or liN- 4 10 6 15 pA Vom = OV, Input Offset Current los Vo=14V 100 500 200 800 nA Input Voltage Range VcM (Note 2) Vee-0.1 Voc-2.25 | Vee-0.1 Voc-2.25| V 5V<Vom<+2.75V, : Common-Mode ~ Rejection Ratio CMRR toes) BO 250 120 500 | BVA Power-Supply Rejection Ratio PSRR | (Note 3} 100 250 150 500 py Output High Voltage VoH ema 24 38 24 35 Vv Output Low Voltage VOL baba li 0.3 0.4 03 0.4 V Latch Input Voltage High VLH (Note 8} 1.4 2.0 1.4 2.0 Vv Latch Input Voltage Law VEL (Note 8) 0.8 1.4 0.8 1.4 Vv Latch Input Current High | the a 2 20 { 20 | BA Latch Input Current Low Ile (Note 3. 2 20 1 20 pA MAXSO00A/MAX301A MAX802 MAX903 PARAMETER SyMBoL| cONDmoNs | MAX@00B/MAX9016 UNITS MIN TYP MAX |MIN TYP MAX] MIN TYP MAX Positive Analog Supply Current lec (Note 8) 10 25 5 12 25 6 mA, Negative Analog Supply Current IEE (Note 8) 7 20 3.5 10 2 5 mA Digital Supply Curent IDD (Note 8) 4 10 2 5 1 25] mA Power Dissipation Po | yet ype = *8 70 105 as 55 18 28 | mw 4 MAAXLAAHigh-Speed, Low-Power Voltage Comparators TIMING CHARACTERISTICS (Voc = +5V, VEE = -5V, Vpp = +5V, LE1-LE4 = Logie High, Ta = TmIN to TMAX, unless otherwise noted.) MAXS00A/901A MAX900B/901B/902/903 PARAMETER SYMBOL; CONDITIONS UNITS MIN TYP MAX MIN TYP MAX Vop = 5mV Input-to-Output High CL = 15pF Response Time tod+ lo = 2mA 10 15 10 15 ns (Note 5} Yobo = 5mV Input-to-Output Low - CL = 15pF Response Time oa lo = 2mA 10 15 10 18 ns (Note 5) Difference in Response Time Atoa (Notes 5, 8) { 3 { 3 ns Between Outputs p Note 2: The input common-mode voltage or either input signal voltage should not be allowed to go negative by more than 0.2V below VEE. The upper end af the common-mode voltage range is typically Cc-2.0V, but either or both inputs can go to a maximum of Voc +0.2V without damage, ; Note 3: Tested for +4.75V<Voco<+5.26V, and -6.25V<VeE<-4.75V with Vop = +5V, although permissible analog power-supply range is +4.75V<Voc<+10.5 for Single SOR operation with VEE grounded. Note 4: Specification does not apply to M 1, Note 5: Guaranteed by design. Times are for 100mV step inputs (see propagation delay characteristics in Figures 2 and 3). Note 6: Maximum difference in propagation delay between any of the four comparators in the MAX900/90 1/902/903. Note 7: See Timing Diagram (Figure 2). Owing to the difficult and critical nature of switching measurements involving the latch, these parameters cannot be tested in a production environment. Typical specifications listed are taken from measurements using a high-speed test4ig. Note 8: Icc tested for +4.75V<Voc<+10.5V with VEE grounded. lee tested for -5.25V<Vee<-4.78V with Voc = +5V. lop tested for +4.75V<Vpp<+5.25V with the worst-case condition of all four comparator outouls al logic low. Typical Operating Characteristics INPUT OFFSET VOLTAGE (mv} INPUT OFFSET VOLTAGE INPUT BIAS CURRENT OUTPUT LOW VOLTAGE vs. TEMPERATURE vs. TEMPERATURE (VoL) vs. LOAD CURRENT < 40 = os 3 wi E35 2 0.4 Wi all = g Ta = -55C = 3.0 x 03 vb ., g < 25 F 0.2 Ye Ta=+25C @ i. z a FE F 20 Pe B OF Ta=+128C . | | -40-20 0 20 40 60 30 100 120 40-20 0 20 40 60 80 190120 2 4 +6 10 TEMPERATURE (C) TEMPERATURE (C) LOAD CURRENT (mA) MAXUM 5 06/206/106/006X VNMAX900/90 1/902/903 Migh-Speed, Low-Power Vottage Comparators Typical Operating Characteristics (continued) Icc SUPPLY CURRENT INPUT OVERDRIVE vs. INPUT OVERDRIVE vs. (PER COMPARATOR) vs. Vec : v SUPPLY VOLTAGE (Vp = +5) tpd+ RESPONSE TIME tod- RESPONSE TIME wi Ww g g z 30 Ta = +126C eo x 4 28 Ss 3 Ss 3 z 26 Ta = +25C z 2 - # = 5 5 ll = 24 ol 5 2 22 wo w o -_ & 20 FE 100 . 5 > S o 1.8 $2 0 g a 16 5 -100 5 -190 z = 4 5 6 7 @ 9 1 02 4 6 8 0 12 14 o 2 4 6 8 0 1 14 Voc SUPPLY VOLTAGE () lod RESPONSE TIME (ns) tpa- RESPONSE TIME (ns) RESPONSE TIME RESPONSE TIME vs. vs. TEMPERATURE LOAD CAPACITANCE (5mV (5mV OVERDRIVE) OVERDRIVE, Rioap = 2.4kQ) 2 z = 2 = 4 F F Ww va a = w 5 z a o aw a uw t e id pd = -40-20 0 20 40 60 BO 100120 10 20 30 4D 50 60 70 80 TEMPERATURE (C) LOAD CAPACITANCE (pF) 6 MA AXIAAHigh-Speed, Low-Power Voltage Comparators Pin Descriptions MAXS00 MAX901 PIN NAME FUNCTION PIN NAME FUNCTION 1,10, 11,20] IN-(4,B,C,D) | Negative Input 1,8,9,16 | IN-(A,B,C,D) | Negative Input roses co (Channels A, B, C, D) ue ao (Channels A, B. , D) 29.1219] IN+(A,B,C.D) | Positive Input 2.7,10,15| IN+(A,B,C,D) | Positive Input =o ca (Channels A,B, C, D) cos a (Channels A, B, C, D) 3 GND Ground Terminal 3 GNO Ground Terminal Latch Input Output 4,7, 14,17 | LATCH (A, B, C, B} (Channels A, B, C, D) 4,5,12,13 | GUT(A,B,C,D) (Channels A, B, C.D) Outout Negative Analog Supply 5,6,15,16 | OUT(A,B.C.D) | (Channels A, B,C, D) 6 VEE and Substrate 8 V Negative Analog Supply 11 Vpb Positive Digital Supply EE and Substrate 14 Voc Positive Analog Supply 13 Vop Positive Digital Supply 18 Voc Positive Analog Supply MAX902 MAX903 PIN NAME FUNCTION PIN NAME FUNCTION _ Negative Input 1 Veo Positive Analog Supply 1.8 IN- (A.B) (Channels A, B) 2 IN+ Positive Input Positive Input 2,9 IN+ (A, B) (Channels A, 8) 4 IN- Negative Input 3 GND Ground Terminal 4 VEE Negative Analog Supply and Substrate Latch Input 41 LATCH {A.B} | (Channels A. 8) 5 LATCH Latch Inout Output 6 GND Ground Terminal 5,12 OUT (A. B) (Channels A, B) 7 OUT Output 6, 13 NLC, No Connect 8 VoD Positive Digital Supply 7 V Negative Analog Supply ce and Substrate 10 VoD Positive Digital Supply 14 Vec Positive Analog Supply MA AXIS 06/206/106/006XVWMAX900/901/902/803 Migh-Speed, Low-Power Voltage Comparators Applications information Circuit Layout Because of the large gain-bandwidth transter function of thea MAX900-903, special precautions must be taken to realize their full high-speed capability. A printed circuit beard with a good, low-inductance ground plane is man- datory. Ail decoupling capacitors (the small 100nF ce- ramic type is a good choice} should be mounted as close as possible to the power-supply pins. Separate decou- pling capacitors for analog Voc and for digital Voo are also recommended. Close attention should be paid to the bandwidth of the decoupling and terminating components. Short lead lengths on the inputs and outputs are essential to avoid unwanted parasitic feedback around the compa- raters. Solder the device directly to the printed circuit board instead of using a socket. input Siew-Rate Requirements As with all high-speed comparators, the high gain- bandwidth product of the MAX900-903 can create oscil- lation problems when the input traverses the linear region. For clean output switching without oscillation or steps in the output waveform, the input must meet minimum slew- rate requirements. Oscillation is largely a function of board layout and of coupled source impedance and stray input capacitance. Both poor layout and large source impedance will cause the part to oscillate and increase the minimum siew-rate requirement. In some applica- tions, it may be helpful to apely some positive feedback between the output and + input. This pushes the output through the transition region cleanly, but applies a hys- teresis in threshold seen at the input terminals. TTL Output and Latch inputs The comparator TTL output stages are optimized for driving low-power Schottky TTL with a fan-out of four. When the latch is connected to a logic high level or left floating, the comparator is transparent and immediately responds to changes at the input terminals. When the latch is connected to a TTL low level, the comparator output latches in the same state as at the instant that the latch command is applied, and will not respond to sub- sequent changes at the input. No latch is provided on the MAX901. Power Supplies The MAX&00-903 can be powered from separate analog and digital supplies or from a single +8V supply. The analog supply can range from +5V to +10V with Vee grounded for single-supply operation (Figures 1A and 1B} or from a split+5V supply (Figure 1C). The Von digital supply always requires +5V. In high-speed, mixed-signal applications where a com- men ground is shared, a noisy digital environment can adversely affect the analag input signal. When set up with separate supplies (Figure 1C), the MAX900-903 isolate analog and digital signals by providing a separate AGND(VEE) and DGND. Typical Power-Supply Alternatives +10 OUT +54 ~ ol +hV OUT OUT GND Figure 14. Separate Analog Supply, Common Ground Figure 18. Single +5 Supply, Common Ground Figure 1C. SplittSV Supply, Separate Ground MAXIMALow-Power Voltage Definition of Terme Vos VIN Vop tpd+ tpd- tpd+ (D) MAXLAA Input Offset Voltage: Voltage applied be- tween the two input terminals to obtain TTL lagic threshold (+1.4) at the output. input Voliage Pulse Amplitude: Usually set to 100mV for comparator specifications. Input Voltage Overdrive: Usually set to 5mvV and in opposite polarity to Vin for cam- parator specifications. Input to Output High Delay: The propagation delay measured from the time the input signal crosses the input offset voltage to the TTL logic threshold of an output low to high transistion. Input to Output Low Delay: The propagation delay measured from the time the input signal crosses the input offset voltage to the TTL logic threshold of an output high to low transition. Latch Disable to Output High Delay: The propagation delay measured from the latch signal crossing the TTL threshold in a low to high transition to the point of the output cross- ing TTL threshold in a low to high transition. tpa- (D) Latch Disable to Output Low Delay: The tpw (D) propagation delay measured from the latch signal crossing the TTL threshold in a low to high transition to the point of the output crossing TTL threshold in a high to low tran- sition. Minimum Setup Time: The minimum time before the negative transition of the latch sig- nal that an input signal change must be pres- ent in order to be acquired and held at the outputs. Minimum Hold Time: The minimum time after the negative transition of the latch sig- nal that an input signal must remain un- changed in order to bs acquired and held at the output. Minimum Latch Disable Phuse Width: The minimum time that the latch signal must re- main high in order to acquire and hold an input signal change. 06/Z0G6/1 0G/OOEX VMEMAX900/901/902/903 Hig Voltage Comparators |, Low-Power LATCH = COMPARE COMPARE ENABLE INPUT LATCH Lf LATCH j LATCH DIFFERENTAL INPUT VOLTAGE Vin Yoo COMPARATOR OUTPUT OUTPUT INPUT 5ns/DIV Figure 2. MAX900/962/903 Timing Diagram Figure 3. lbat Response Time to 5mV Overdrive SV OUTPUT Ov INPUT 100m Vos. +5mV Sns/DV INPUT 70 10% SCOPE PROBE (10M&2, 14pF} Von +5 VCC +5 PRECISION ik STEP GENERATOR OUTPUT TO 10x SCOPE PROBE (10Mf2, 14pF) Voe OFFSET ADJUST _ [toon [0 Figure 4. tog Response Time ta 5mV Overdrive 10 Figure 5. Response-Time Setup MA AXIMHigh-Speed, Low-Power Voltage Comparators oh FU syetyy OUTPUT Wily full aoe NPUT (in Gly Thr weft ma onssDly Pgure 6 Respanse to 40a Sine Wave Figure 7 Hesooise to TOO sine wave nania Typical Application Wey Programmed, Variable-Alarm Limits REF By somrbining two quac analog comparalars wilh ar mAaAxLa ih UNDER octal, B-bit DIA converter (the MX?7??8) several alarnr 724 macy peru HNL and limit-defect functions can be perforned simiulta- M7228 yoaci *y . p . . neously without external adjustments ol WTR sone: octal | mot Co Tan The MX7228's irternal latc ~es allow the system processur a | Ne to set the imi, porrls ar each corr paraler independently : Nery UNDEF and updace thern at any time Set the upoer ancl lower pa . 7 IMT thresholds tor a single transducer by pairing tae MA . Nee cae canverler and comoaralor sections. . me USDIR NSB . . Qo MT a MANGE a-BI gel Pe DATA . | * INGER (HPL . IMIT [3h -| 5 - tH INDIR IIT Ts curr . ___ 20 IMIT Ad * AC o4ER Me .7 VMI MAAN Figura 8 Alarm Orcul fevelMundors egal Separate tnouts fbi sic) svi 11 06/Z206/1 06/O0O6XVINNMAX900/901/902/903 High-Speed, Low-Power Voltage Comparators _ Ordering Information (continued) Pin Configurations (continued) PART TEMP. RANGE PIN-PACKAGE MAXS01ACPE Orc to +70C 16 Plastic DIP MAX901BCPE OC to +70C 16 Plastic DIP MAX901ACSE OC to +70C 16 Narrow SO MAXS01BCSE OC to +70C 16 Narrow SO MAX901BC/D OC to +70C Dice | MAX301AEPE -40C to +85C 16 Plastic DIP MAX901BEPE -40C to +85C 16 Plastic DIP MAX901AESE -40C to +85C 16 Narrow SO MAX901BESE -40C to +85C 16 Narrow SO | MAX90 1AMJE 59C to +1 25C 16 CERDIP MAX901BMJE -55C to +126'C 16 CERDIP MAX3902CPD OC ta +70C 14 Plastic DIP MAxX902CSD O'S to +70C 14 Narrow SO MAX902C/D O'C to +70C Dice* MAX902EPD -40C to +85C 14 Plastic DIP MAX902ESD -40C to +85C: 14 Narrow SO MAX302MJD -55C to +125C 14 CERDIP MAXS03CPA OC to +70C 8 Plastic DIP MAXS303CSA OC to +70C 8soO MAX903C/D OC to +70C Dice MAX903EPA -40C to +86C 8 Plastic DIP MAX903ESA -40C to +85C 850 MAXS03MJA -58C to +125C 8 CERDIP Contact factory for dice specifications. TOP VIEW ; IN (4) [4 | _ IN- 1D) IN+ (Al [2 FP 9] IN+ (0) GNO [3 | < pial voor LATCH [4] p [17] LATCH (0) OUT (A) | 5 | aneocian 16] OUT(D) our 8) | 6 | AX908 Ie) uric) B re LATCH (By [7 | 4 LATCH (C) VEE" [a] 3, Voo*** IN- (B){ 9 | 12] IN+(C) IN- 4B) [1/ H4] IN-{C) DIP/SO - _ayyal.0G V- AND SUBSTRATE ** ANALOG Vs ** DIGITAL + Chip Topography OUT = LATCH (D) (C) HN{D) -IN(D) (73mm) -IN(A) -IN(B) +IN(A) +IN(B)} GND OUT LATCH (A) (B) 0.086" (2.18mm) Note: Substrate connected to VEE. MAx900/30 1/902/903 Maxim cannot assume responsibility for use of any circuitry offer than circuitry entirely embodied in a Maxim product No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specitications without notice at any time. 12 Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 (408) 737-7600 1991 Maxim Integrated Products Printed USA AAAMLAA j5 4 registered tradernark of Maxim Integrated Products.