2009-2013 Microchip Technology Inc. DS22143D-page 1
MCP6566/6R/6U/7/9
Features:
• Propagation Delay at 1.8 VDD:
- 56 ns (typical) High-to-Low
• Low Quiescent Current: 100 µA (typical)
• Input Offset Voltage: ±3 mV (typical)
• Rail-to-Rail Input: VSS - 0.3V to VDD + 0.3V
• Open-Drain Output
• Wide Supply Voltage Range: 1.8V to 5.5V
• Available in Single, Dual and Quad
• Packages: SC70, SOT-23-5, SOIC, MSOP,
TSSOP
Typical Applications:
• Laptop Computers
• Mobile Phones
• Hand-held Electronic s
• RC Timers
• Alarm and Monitoring Circuits
• Window Comparators
• Multivibrators
Design Aids:
• Microchip Advanced Part Selector (MAPS)
• Analog Demonstration and Evaluation Boards
• Application Notes
Related Device:
• Push-Pull Output: MCP6561/1R/1U/2/4
Typical Application
Description:
The Microchip Technology, Inc. MCP6566/6R/6U/7/9
families of open-drain output comparators are offered
in single, dual and quad configurations.
These comparators are optimized for low-power 1.8V,
single-supply applications with greater than rail-to-rail
input operation. The internal input hysteresis eliminates
output switching due to internal input noise voltage,
reducing current draw. The open-drain output of the
MCP6566/6R/6U/7/9 family requires a pull-up resistor
and it supports pull-up voltages above and below VDD,
which can be used to level shift. The output toggle
frequency can reach a typical of 4 MHz (typical) while
limiting supply current surges and dynamic power
consumption during switching.
This family operates with single supply voltage of 1.8V
to 5.5V while drawing less than 100 µA/comparator of
quiescent current (typical).
Package Types
VIN
VOUT
+5VDD
R2
RF
R3
VDD
+3VPU
MCP656X
MCP6567
+INA
-INA
VSS
1
2
3
4
8
7
6
5
-
OUTA
+-
+
VDD
OUTB
-INB
+INB
MCP6569
+INA
-INA
VSS
1
2
3
4
14
13
12
11
-
OUTA
+-
+
VDD
OUTD
-IND
+IND
10
9
8
5
6
7
OUTB
-INB
+INB
+INC
-INC
OUTC
+
--
+
5
4
MCP6566
1
2
3
-
+
5
4
MCP6566R
1
2
3
-
+
+IN
VSS
OUT
-IN
VDD
+IN
VDD
OUT
-IN
VSS
SOT-23-5, SC70-5 SOIC, MSOP
SOT-23-5 SOIC, TSSOP
4
1
2
3
5
SOT-23-5
VSS
VIN+
VIN–
VDD
OUT
MCP6566U
-
+
1.8V Low-Power Open-Drain Output Comparator
MCP6566/6R/6U/7/9
DS22143D-page 2 2009-2013 Microchip Technology Inc.
NOTES:
2009-2013 Microchip Technology Inc. DS22143D-page 3
MCP6566/6R/6U/7/9
1.0 ELECTRICAL
CHARACTERISTICS
1.1 Maximum Ratings †
VDD - VSS .......................................................................6.5V
Open-Drain Output.............................................VSS + 10.5V
All other inputs and outputs...........VSS – 0.3V to VDD + 0.3V
Analog Input (VIN) ††............ .........VSS - 1.0V to VDD + 1.0V
Difference Input voltage ......................................|VDD - VSS|
Output Sh o rt Circui t Cur r e n t ....................................±25 mA
Current at Input Pins ..................................................±2 mA
Current at Output and Supply Pins ..........................±50 mA
Storage temperature ........... .. .. .... .. .. ....... .. .. .-65°C to +150°C
Ambient temp. with power applied..............-40°C to +125°C
Junction temp.......................... .. .. .... ..... .. .. .. .. .... .. .. .....+150°C
ESD protection on all pins (HBM/MM)4 kV/300V
† Notice: Stresses above those listed under “Maximum
Ratings” may cause permanent damage to the device. This is
a stress rating only and functional operation of the device at
those or any other conditions above those indicated in the
operational listings of this specification is not implied. Expo-
sure to max imum rati ng conditions for extended periods may
affect device reliability.
†† See Section 4.1.2 “Input Voltage and Current Limits”
DC CHARACTERISTICS
Electrical Characteristics: Unless otherwise indicated: VDD = +1.8V to +5.5V, VSS = GND, TA = +25°C, VIN+ = VDD/2, VIN- = VSS,
and RPull-Up = 20 k to VPU = VDD (see Figure 1-1).
Parameters Symbol Min Typ Max Units Conditions
Power Supply
Supply Voltage VDD 1.8 — 5.5 V
Quiescent Current per comparator IQ60 100 130 µA IOUT = 0
Power Supply Rejection Ratio PSRR 63 70 — dB VCM = VSS
Input
Input Offset Voltage VOS -10 3+10mVV
CM = VSS (Note 1)
Input Offset Drift VOS/T— 2—µV/°CV
CM = VSS
Input Offset Current IOS — 1— pAV
CM = VSS
Input Bias Current IB—1—pAT
A = +25°C, VIN- = VDD/2
—60— pAT
A = +85°C, VIN- = VDD/2
— 1500 5000 pA TA = +125°C, VIN- = VDD/2
Input Hysteresis Volt age VHYST 1.0 — 5.0 mV VCM = VSS (Notes 1,2)
Input Hysteresis Linear Temp. Co. TC1—10—µV/°C
Input Hysteresis Quadratic Temp. Co. TC2—0.3—µV/°C
2
Common-Mode Input Voltage Range VCMR VSS0.2 — VDD+0.2 V VDD = 1.8V
VSS0.3 — VDD+0.3 V VDD = 5.5V
Common-Mode Rejection Ratio CMRR 54 66 — dB VCM= -0.3V to V DD+0.3V, VDD = 5.5V
50 63 — dB VCM= VDD/2 to VDD+0.3V, VDD = 5.5V
54 65 — dB VCM= - 0 . 3 V to V DD/2, VDD = 5.5V
Common Mode Input Impedance ZCM —10
13||4 — ||pF
Differential Input Impedance ZDIFF —10
13||2 — ||pF
Note 1: The input offset voltage is the center of the input-referred trip points. The input hysteresis is the difference between the
input-referred trip points.
2: VHYST at different temperatures is estimated using VHYST (TA) = V HYST @ +25°C + (TA - 25°C ) TC1 + (TA - 25°C)2 TC2.
3: Limit the output current to Absolute Maximum Rating of 50 mA .
4: The pull-up voltage for the open drain output VPULL_UP can be as high as the absolute maximum rating of 10.5V. In this
case, IOH_leak can be higher than 1 µA (see Figure 2-30).
MCP6566/6R/6U/7/9
DS22143D-page 4 2009-2013 Microchip Technology Inc.
Push-Pull Output
Pull-up Voltage VPULL_UP 1.6 — 5.5 V
High-Level Output Voltage VOH ——V
PULL_UP V (see Figure 1-1) (Notes 3,4)
High-Level Output Current Leakage IOH_leak —— 1 µANote 4
Low-Level Output Voltage VOL ——0.6 VI
OUT = 3mA/8mA @ V
DD = 1.8V/5.5V
Short Circuit Current (Notes 3) ISC — ±30 — mA Not to exceed Absolute Max. Rating
Output Pin Capacitance COUT —8—pF
DC CHARACTERISTICS (CONTINUED)
Electrical Characteristics: Unless otherwise indicated: VDD = +1.8V to +5.5V, VSS = GND, TA = +25°C, VIN+ = VDD/2, VIN- = VSS,
and RPull-Up = 20 k to VPU = VDD (see Figure 1-1).
Parameters Symbol Min Typ Max Units Conditions
Note 1: The input offset voltage is the center of the input-referred trip points. The input hysteresis is the difference between the
input-referred trip points.
2: VHYST at different temperatures is estimated using VHYST (TA) = V HYST @ +25°C + (TA - 25°C) TC1 + (TA - 25°C)2 TC 2.
3: Limit the output current to Absolute Maximum Rating of 50 mA .
4: The pull-up voltage for the open drain output VPULL_UP can be as high as the absolute maximum rating of 10.5V. In this
case, IOH_leak can be higher than 1 µA (see Figure 2-30).
AC CHARACTERISTICS
Electrical Characteristics: Unless otherwise indicated,: Unless otherwise indicated,: VDD = +1.8V to +5.5V, VSS = GND,
TA = +25°C, VIN+ = VDD/2, VIN- = VSS, RPull-Up = 20 k to VPU = VDD, and CL = 25 pf (see Figure 1-1).
Parameters Symbol Min Typ Max Units Conditions
Propagation Delay
High-to-Low,100 m V Overdr ive tPHL —5680 nsV
CM= VDD/2, VDD = 1.8V
—3480 nsV
CM= VDD/2, VDD = 5.5V
Output
Fall Time tF—20— ns
Maximum Toggle Frequency fTG —4—MHzV
DD = 5.5V
—2—MHzV
DD = 1.8V
Input Voltage Noise ENI —350—µV
P-P10 Hz to 10 MHz (Note 1)
Note 1: ENI is based on SPICE simulation.
2: Rise time tR and tPLH depend on the load (RL and CL). These specification are valid for the specified load only.
TEMPERATURE SPECIFICATIONS
Electrical Characteristics: Unless otherwise indicated: VDD = +1.8V to +5.5V and VSS = GND.
Parameters Symbol Min Typ Max Units Conditions
Temperature Ranges
Specif ied Temperature Range TA-40 — +125 °C
Operati ng Temperature Range TA-40 — +125 °C
Storage Temperature Range TA-65 — +150 °C
Thermal Package Resistances
Thermal Resistance, SC70-5 JA — 331 — °C/W
Thermal Resistance, SOT-23-5 JA —220.7— °C/W
Thermal Resistance, 8L-MSOP JA —211—°C/W
Thermal Resistance, 8L-SOIC JA —149.5— °C/W
Thermal Resistance, 14L-SOIC JA —95.3— °C/W
Thermal Resistance, 14L-TSSOP JA — 100 — °C/W
2009-2013 Microchip Technology Inc. DS22143D-page 5
MCP6566/6R/6U/7/9
1.2 Test Circuit Configuration
This test circuit configuration is used to determine the
AC and DC speci fic ati on s.
FIGURE 1-1: AC and DC Test Circuit for
the Open-Drain Output Comparators.
VDD
VSS = 0V
200 k
200 k
RPU
VOUT
VIN = VSS
25 pF
VPU = VDD
20 k
IOUT
MCP656X
MCP6566/6R/6U/7/9
DS22143D-page 6 2009-2013 Microchip Technology Inc.
NOTES:
2009-2013 Microchip Technology Inc. DS22143D-page 7
MCP6566/6R/6U/7/9
2.0 TYPICAL PERFORMANCE CURVES
Note: Unless otherwise indicated, VDD = +1.8V to +5.5V, VSS = GND, TA = +25°C, VIN+ = VDD/2, VIN– = GND,
RL = 20 k to VPU = VDD, and CL = 25 pF.
FIGURE 2-1: Input Offset Voltage.
FIGURE 2-2: Input Offset Voltage Drift.
FIGURE 2-3: Input vs. Output Signal, No
Phase Reversal.
FIGURE 2-4: Input Hysteresis Voltage.
FIGURE 2-5: Input Hysteresis Voltage
Drift - Linear Temp. Co. (TC1).
FIGURE 2-6: Input Hysteresis Voltage
Drift - Quadratic Temp. Co. (TC2).
Note: The g r ap hs and t ables prov id ed fol low i ng thi s n ote are a st a tis tic al s umm ary bas ed on a limite d n um ber of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore outside the warranted range.
0%
10%
20%
30%
40%
50%
-10 -8 -6 -4 -2 0 2 4 6 8 10
VOS (mV)
Occurrences (%)
VDD = 1.8V
VCM = VSS
Avg. = -0.1 mV
StDev = 2.1 mV
3588 units
VDD = 5.5V
VCM = VSS
Avg. = -0.9 mV
StDev = 2.1 mV
3588 units
0%
10%
20%
30%
40%
50%
60%
-60 -48 -36 -24 -12 0 12 24 36 48 60
VOS Drift (µV/°C)
Occurrences (%)
VCM = VSS
Avg. = 0.9 µV/°C
StDev = 6.6 µV/°C
1380 Units
TA = -40°C to +125°C
-1.0
0.0
1.0
2.0
3.0
4.0
5.0
6.0
7.0
Time (3 µs/div)
VOUT (V)
V
IN
-V
OUT
VDD = 5.5V V
IN
+ = V
DD
/2
0%
5%
10%
15%
20%
25%
30%
1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
VHYST (mV)
Occurrences (%)
VDD = 1.8V
Avg. = 3.4 mV
StDev = 0.2 mV
3588 units
VDD = 5.5V
Avg. = 3.6 mV
StDev = 0.1 mV
3588 units
0%
10%
20%
30%
40%
50%
60%
02468101214161820
VHYST Drift, TC1 (µV/°C)
Occurrences (%)
1380 Units
TA = -40°C to 125°C
VCM = VSS
VDD = 5.5V
Avg. = 10.4 µV/°C
StDev = 0.6 µV/°C
VDD = 1.8V
Avg. = 12 µV/°C
StDev = 0.6 µV/°C
0%
10%
20%
30%
-0.50 -0.25 0.00 0.25 0.50 0.75 1.00
VHYST Drift, TC2 (µV/°C2)
Occurrences (%)
VDD = 5.5V
Avg. = 0.25 µV/°C2
StDev = 0.1 µV/°C2
VDD = 1.8V
Avg. = 0.3 µV/°C2
StDev = 0.2 µV/°C2
1380 Units
TA = -40°C to +125°C
VCM = VSS
MCP6566/6R/6U/7/9
DS22143D-page 8 2009-2013 Microchip Technology Inc.
Note: Unless otherwise indicated, VDD = +1.8V to +5.5V, VSS = GND, TA = +25°C, VIN+ = VDD/2, VIN– = GND,
RL = 20 k to VPU = VDD, and CL = 25 pF.
FIGURE 2-7: Input Offset Voltage vs.
Temperature.
FIGURE 2-8: Input Offset Voltage vs.
Common-mode Input Voltage.
FIGURE 2-9: Input Offset Voltage vs.
Common-mode Input Voltage.
FIGURE 2-10: Input Hysteresis Voltage vs.
Temperature.
FIGURE 2-11: Input Hysteresis Voltage vs.
Common-mode Input Voltage.
FIGURE 2-12: Input Hysteresis Voltage vs.
Common-mode Input Voltage.
-3.0
-2.0
-1.0
0.0
1.0
2.0
3.0
-50 -25 0 25 50 75 100 125
Temperature (°C)
VOS (mV)
VDD= 1.8V
VDD= 5.5V
VCM = VSS
-4.0
-2.0
0.0
2.0
4.0
-0.3 0.0 0.3 0.6 0.9 1.2 1.5 1.8 2.1
VCM (V)
VOS (mV)
VDD = 1.8V
TA= +25°C
T
A= +125°C
T
A= +85°C
TA= -40°C
-3.0
-2.0
-1.0
0.0
1.0
2.0
3.0
-1.0 0.0 1.0 2.0 3.0 4.0 5.0 6.0
VCM (V)
VOS (mV)
VDD = 5.5V
TA= -40°C
TA= +25°C
T
A= +125°C
T
A= +85°C
1.0
2.0
3.0
4.0
5.0
-50 -25 0 25 50 75 100 125
Temperature (°C)
VHYST (mV)
VDD= 5.0V
VDD= 1.8V
VCM = VSS
1.0
2.0
3.0
4.0
5.0
-0.3 0.0 0.3 0.6 0.9 1.2 1.5 1.8 2.1
VCM (V)
VHYST (mV)
V
DD = 1.8V
TA= +25°C
TA= +125°C
TA= +85°C
TA= -40°C
1.0
2.0
3.0
4.0
5.0
-0.5 0.5 1.5 2.5 3.5 4.5 5.5
VCM (V)
VHYST (mV)
VDD = 5.5V
TA= -40°C
TA= +85°C
TA= +25°C
TA= +125°C
2009-2013 Microchip Technology Inc. DS22143D-page 9
MCP6566/6R/6U/7/9
Note: Unless otherwise indicated, VDD = +1.8V to +5.5V, VSS = GND, TA = +25°C, VIN+ = VDD/2, VIN– = GND,
RL = 20 k to VPU = VDD, and CL = 25 pF.
FIGURE 2-13: Input Offset Volt age vs.
Supply Voltage vs. Temp eratu re .
FIGURE 2-14: Quiescent Current.
FIGURE 2-15: Quiescent Current vs.
Common-mode Input Voltage.
FIGURE 2-16: Input Hysteresis Voltage vs.
Supply Voltage vs. Tem per atu re.
FIGURE 2-17: Quiescent Current vs.
Supply Voltage vs Temperature.
FIGURE 2-18: Quiescent Current vs.
Common-mode Input Voltage.
-3.0
-2.0
-1.0
0.0
1.0
2.0
3.0
1.5 2.5 3.5 4.5 5.5
VDD (V)
VOS (mV)
TA= -40°C
TA= +85°C
TA= +25°C
TA= +125°C
0%
10%
20%
30%
40%
50%
60 70 80 90 100 110 120 130
IQ (µA)
Occurrences (%)
VDD = 5.5V
Avg. = 97 µA
StDev= 4 µA
1794 units
VDD = 1.8V
Avg. = 88 µA
StDev= 4 µA
1794 units
60
70
80
90
100
110
120
130
-0.5 0.0 0.5 1.0 1.5 2.0 2.5
VCM (V)
IQ (µA)
VDD = 1.8V
Sweep VIN+ ,VIN- = VDD/2
Sweep VIN- ,VIN+ =
V
/2
Sweep VIN+ ,VIN- = VDD/2
Sweep VIN- ,VIN+ = VDD/2
1.0
2.0
3.0
4.0
5.0
1.5 2.5 3.5 4.5 5.5
VDD (V)
VHYST (mV)
TA= +85°C
TA= +125°C
TA= +25°C
TA= -40°C
0.0
20.0
40.0
60.0
80.0
100.0
120.0
140.0
0.0 1.0 2.0 3.0 4.0 5.0 6.0
VDD (V)
IQ (µA)
TA= -40°C
TA= +85°C
TA= +125°C
TA= +25°C
60
70
80
90
100
110
120
130
-1.0 0.0 1.0 2.0 3.0 4.0 5.0 6.0
VCM (V)
IQ (µA)
VDD = 5.5V
Sweep VIN+ ,VIN- = VDD/2
Sweep VIN- ,VIN+ = VDD/2
MCP6566/6R/6U/7/9
DS22143D-page 10 2009-2013 Microchip Technology Inc.
Note: Unless otherwise indicated, VDD = +1.8V to +5.5V, VSS = GND, TA = +25°C, VIN+ = VDD/2, VIN– = GND,
RL = 20 k to VPU = VDD, and CL = 25 pF.
FIGURE 2-19: Quiescent Current vs.
Pull-up Voltage.
FIGURE 2-20: Quiescent Current vs.
Toggle Frequency.
FIGURE 2-21: Output Headroom vs Output
Current.
FIGURE 2-22: Quiescent Current vs.
Pull-up to Supply Voltage Difference.
FIGURE 2-23: Output Leakage Current vs.
Pull-up Voltage.
FIGURE 2-24: Output Headroom Vs Output
Current.
50
75
100
125
150
0.5 1.5 2.5 3.5 4.5 5.5 6.5 7.5 8.5 9.5 10.5
VPU (V)
IQ (µA)
IDD Spike near VPU = 0.9V
VDD = 5.5V
VDD = 4.5V
VDD = 3.5V
VDD = 2.5V
VDD = 2.0V
VDD = 1.8V
50
100
150
200
250
300
350
400
10 100 1000 10000 100000 100000
0
1E+07
Toggle Frequency (Hz)
IQ (µA)
VDD = 1.8V
VDD = 5.5V
10 100 1k 10k 100k 1M 10M
100 mV Over-Drive
VCM = VDD/2
RL = Open
0dB Output Attenuation
0
200
400
600
800
1000
0.0 3.0 6.0 9.0 12.0 15.0
IOUT (mA)
VOL (mV)
VDD= 1.8V
TA = +125°C
TA = +85°C
TA = +25°C
TA = -40°C
50
75
100
125
150
-4.5 -2.5 -0.5 1.5 3.5 5.5 7.5 9.5
VPU - VDD (V)
IQ (µA)
VDD = 3.5 V
VDD = 1.8 V
VDD = 2.5 V
VDD = 2.0 V
VDD = 4.5 V
VDD = 5.5 V
1
10
100
1,000
10,000
100,000
1.5 2.5 3.5 4.5 5.5 6.5 7.5 8.5 9.5 10.5
VPU (V)
IOH_leak (pA)
TA = +25°C
TA = +85°C
TA =
0
200
400
600
800
1000
0 5 10 15 20 25
IOUT (mA)
VOL (mV)
VDD= 5.5V
TA = 125°C TA = 125°C
TA = +85°C
TA = -40°C
TA = +25°C
TA = +125°C
2009-2013 Microchip Technology Inc. DS22143D-page 11
MCP6566/6R/6U/7/9
Note: Unless otherwise indicated, VDD = +1.8V to +5.5V, VSS = GND, TA = +25°C, VIN+ = VDD/2, VIN– = GND,
RL = 20 k to VPU = VDD, and CL = 25 pF.
FIGURE 2-25: High-to-Low Propagation
Delays.
FIGURE 2-26: Propagation Delay vs. Input
Over-Drive.
FIGURE 2-27: Propagation Delay vs.
Supply Voltage.
FIGURE 2-28: High-to-Low Propagation
Delays.
FIGURE 2-29: Propagation Delay vs.
Temperature.
FIGURE 2-30: Short Circuit Current vs.
Supply Voltage vs. Tem per atu re.
0%
10%
20%
30%
40%
50%
30 35 40 45 50 55 60 65 70 75 80
Prop. Delay (ns)
Occurrences (%)
VDD= 1.8V
100 mV Over-Drive
VCM = VDD/2
tPHL
Avg. = 54.4 ns
StDev= 2 ns
198 units
10
60
110
160
210
260
1 10 100 1000
Over-Drive (mV)
Prop. Delay (ns)
tPHL , VDD = 1.8V
tPHL , VDD = 5.5V
VCM = VDD/2
20
40
60
80
100
120
140
1.5 2.5 3.5 4.5 5.5
VDD (V)
Prop. Delay (ns)
tPHL , 10 mV Over-Drive
tPHL , 100 mV Over-Drive
VCM = VDD/2
0%
10%
20%
30%
40%
50%
30 35 40 45 50 55 60 65 70 75 80
Prop. Delay (ns)
Occurrences (%)
VDD
= 5.5
V
100mV Over-Drive
VCM = VDD
/
2
tPHL
Avg. = 33 ns
StDev= 1 ns
198 units
20
30
40
50
60
70
80
-50 -25 0 25 50 75 100 125
Temperature (°C)
Prop. Delay (ns)
tPHL , VDD = 1.8V
100 mV Over-Drive
VCM = VDD/2
tPHL , VDD = 5.5V
-120
-80
-40
0
40
80
120
0.0 1.0 2.0 3.0 4.0 5.0 6.0
VDD (V)
ISC (mA)
TA= -40°C
TA= +85°C
TA= +125°C
TA= +25°C
TA= -40°C
TA= +85°C
TA= +25°C
TA= +125°C
MCP6566/6R/6U/7/9
DS22143D-page 12 2009-2013 Microchip Technology Inc.
Note: Unless otherwise indicated, VDD = +1.8V to +5.5V, VSS = GND, TA = +25°C, VIN+ = VDD/2, VIN– = GND,
RL = 20 k to VPU = VDD, and CL = 25 pF.
FIGURE 2-31: Propagation Delay vs.
Common-mode Input Voltage.
FIGURE 2-32: Propagation Delay vs.
Capacitive Load .
FIGURE 2-33: Input Bias Current vs. Input
Voltage vs Temperature.
FIGURE 2-34: Propagation Delay vs.
Common-mode Input Voltage.
FIGURE 2-35: Propagation Delay vs.
Pull-up Resistor.
FIGURE 2-36: Propagation Delay vs.
Pull-up Voltage.
20
30
40
50
60
70
80
0.00 0.50 1.00 1.50 2.00
VCM (V)
Prop. Delay (ns)
tPHL
VDD= 1.8V
100 mV Over-Drive
0.01
0.1
1
10
100
1000
1 10 100 1000 10000 100000 1E+06
Capacitive Load (nf)
Prop. Delay (µs)
0.001 0.01 0.1 1 10
100
1000
V
DD = 5.5V, tPHL
100mV Over-Drive
VCM = VDD /2
VDD = 1.8V, tPHL
1E-01
1E+01
1E+03
1E+05
1E+07
1E+09
1E+11
-0.8 -0.6 -0.4 -0.2 0
Input Voltage (V)
Input Current (A)
TA= -40°C
TA= +85°C
TA= +125°C
TA= +25°C
0.1p
10p
1n
100n
10µ
1m
10m
20
30
40
50
60
70
80
0.0 1.0 2.0 3.0 4.0 5.0 6.0
VCM (V)
Prop. Delay (ns)
tPHL
VDD= 5.5V
100 mV Over-Drive
10
100
1000
10000
0.1 1.0 10.0 100.0
RPU (kΩ)
Prop. Delay (ns)
tPLH
tPHL
100 mV Over-Drive
VCM = VDD/2
10
100
1000
10000
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VPU (V)
Prop. Delay (ns)
tPLH, VDD = 5.5V
100 mV Over-Drive
VCM = VDD/2
tPLH, VDD = 1.8V
tPHL, VDD = 1.8V
tPLH, VDD = 5.5V
2009-2013 Microchip Technology Inc. DS22143D-page 13
MCP6566/6R/6U/7/9
Note: Unless otherwise indicated, VDD = +1.8V to +5.5V, VSS = GND, TA = +25°C, VIN+ = VDD/2, VIN– = GND,
RL = 20 k to VPU = VDD, and CL = 25 pF.
FIGURE 2-37: Common-mode Rejection
Ratio and Power Supply Rejection Ratio vs.
Temperature.
FIGURE 2-38: Power Supply Rejection
Ratio (PSRR).
FIGURE 2-39: Input Offset Current and
Input Bias Current vs. Temperature.
FIGURE 2-40: Common-mode Rejection
Ratio (CMRR).
FIGURE 2-41: Common-mode Rejection
Ratio (CMRR).
FIGURE 2-42: Input Offset Current and
Input Bias Current vs. Common-mode Input
Voltage vs. Temperature.
70
72
74
76
78
80
-50 -25 0 25 50 75 100 125
Temperature (°C)
CMRR/PSRR (dB)
VCM = -0.3V to VDD + 0.3V
VDD = 5.5V
CMRR
VCM = VSS
VDD = 1.8V to 5.5V
PSRR
Input Referred
0%
5%
10%
15%
20%
25%
30%
-600 -400 -200 0 200 400 600
PSRR (µV/V)
Occurrences (%)
VCM = VSS
Avg. = 200 µV/V
StDev= 94 µV/V
3588 units
0.1
1
10
100
1000
25 50 75 100 125
Temperature (°C)
IOS and IB (pA)
IB
|IOS|
0%
10%
20%
30%
-5 -4 -3 -2 -1 0 1 2 3 4 5
CMRR (mV/V)
Occurrences (%)
VDD= 1.8V
3588 units
VCM = -0.2V to VDD/2
Avg. = 0.5 mV
StDev= 0.1 mV
VCM = VDD/2 to VDD+ 0.2V
Avg. = 0.7 mV
StDev= 1 mV
VCM = -0.2V to VDD + 0.2V
Avg. = 0.6 mV
StDev= 0.1 mV
0%
10%
20%
30%
-2.5 -2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0 1.5 2.0 2.5
CMRR (mV/V)
Occurrences (%)
VDD= 5.5V
3588 units
VCM = -0.3V to VDD/2
Avg. = 0.2 mV
StDev= 0.4 mV
VCM = VDD/2 to VDD+ 0.3V
Avg. = 0.03 mV
StDev= 0.7 mV
VCM = -0.3V to VDD + 0.3V
Avg. = 0.1 mV
StDev= 0.4 mV
0.001
0.01
0.1
1
10
100
1000
10000
0123456
VCM (V)
IOS and IB (pA)
IB @ TA= +125°C
IB @ TA= +85°C
|IOS| @ TA= +125°C
|IOS|@ TA= +85°C
VDD = 5.5V
MCP6566/6R/6U/7/9
DS22143D-page 14 2009-2013 Microchip Technology Inc.
Note: Unless otherwise indicated, VDD = +1.8V to +5.5V, VSS = GND, TA = +25°C, VIN+ = VDD/2, VIN– = GND,
RL = 20 k to VPU = VDD, and CL = 25 pF.
FIGURE 2-43: Output Jitter vs. Input
Frequency.
0.1
1
10
100
1000
10000
100 1000 10000 100000 100000
0
1E+07
Input Frequency (Hz)
Output Jitter pk-pk (ns)
VDD = 5.5V
100 1k 10k 100k 1M
10M
VIN + = 2Vpp (sine)
2009-2013 Microchip Technology Inc. DS22143D-page 15
MCP6566/6R/6U/7/9
3.0 PIN DESCRIPTIONS
Descriptions of the pins are lis ted in Table 3-1.
TABLE 3-1: PIN FUNCTION TABLE
3.1 Analog Inputs
The comparator non-inverting and inverting inputs are
high-impedance CMOS inputs with low bias currents.
3.2 Digital Outputs
The co mparator outputs are CM OS, open -drai n digi tal
outputs. They are designed to make level shifting and
wired-OR easy to implement.
3.3 Power Supply (VSS and VDD)
The positive power supply pin (VDD) is 1.8V to 5.5V
higher than the negative power supply pin (VSS). For
normal operation, the other pins are at voltages
between VSS and VDD.
Typically, these parts are used in a single (positive)
supply configuration. In this case, VSS is connected to
ground and VDD is connected to the supply. VDD will
need a local bypass capacitor (typically 0.01 µF to
0.1µF) within 2mm of the V
DD pi n. These can s hare a
bulk capacitor with nearby analog parts (within
100 mm), but it is not required.
MCP6566 MCP6566R MCP6566U MCP6567 MCP6569
Symbol Description
SC70-5,
SOT-23-5 SOT-23-5 SOT-23-5 MSOP,
SOIC
SOIC,
TSSOP
1 1 5 1 1 OUT, OUTA Digital Output (comparator A)
44 322V
IN–, VINA– Inverting Input (comparator A)
33 133V
IN+, VINA+ Non-inverting Input (comparator A)
52 484V
DD Positive Power Supply
—— — 5 5V
INB+ Non-inverting Input (comparator B)
—— — 6 6V
INB– Inverting Input (comparator B)
— — — 7 7 OUTB Digital Output (comparator B)
— — — — 8 OUTC Digital Output (comparator C)
—— ——9V
INC– Inverting Input (comparator C)
—— ——10V
INC+ Non-inverting Input (comparator C)
25 2411V
SS Negative Power Supply
—— ——12V
IND+ Non-inverting Input (comparator D)
—— ——13V
IND– Inverting Input (comparator D)
— — — — 14 OUTD Digital Ou tput (comparator D)
MCP6566/6R/6U/7/9
DS22143D-page 16 2009-2013 Microchip Technology Inc.
NOTES:
2009-2013 Microchip Technology Inc. DS22143D-page 17
MCP6566/6R/6U/7/9
4.0 APPLICATIONS INFORMATION
The MCP6566/6R/6U/7/9 family of open-drain output
comparators are fabricated on Microchip’s
stat e-of-the-art CMOS process . They are su itabl e for a
wide range of high speed applications requiring low-
power consumption.
4.1 Comparator Inputs
4.1.1 NORMAL OPERATION
The input stage of this family of devices uses two
differential input stages in parallel. This configuration
provides three regions of operation, one operates at
low input voltages, one at high input voltages, and one
at mid input voltage. With this topology, the input
voltage range is 0.3V above VDD and 0.3V below VSS,
while providing low offset voltage throughout the
common mode range. The input offset voltage is
measur ed at both V SS - 0.3V and VDD + 0.3V to en sure
proper operation.
The MCP6566/6R/6U/7/9 family has internally-set
hysteresis VHYST that is small enough to maintain input
offset accuracy and large enough to eliminate output
chatteri ng caus ed by th e comp arat or’s own inp ut nois e
voltage ENI. Figure 4-1 depicts this behavior. Input
offset voltage (VOS) is the center (average) of the
(input-referred) low-high and high-low trip points. Input
hysteresis voltage (VHYST) is the difference between
the same trip points.
FIGURE 4-1: The MCP6566/6R/6U/7/9
comparators’ internal hysteresis el iminates
output chatter caused by input noise voltage.
4.1.2 INPUT VOLTAGE AND CURRENT
LIMITS
The ESD protection on the inputs can be depicted as
shown in Figure 4-2. This structure was chosen to
protect the in pu t tra ns is tors , and to m in imi ze i npu t b ia s
current (IB). The input ESD diodes clamp the inputs
when they try to go more than one diode drop below
VSS. They also clamp any voltages that go too far
above VDD; their breakdown voltage is high enough to
allow normal operation, and low enough to bypass ESD
events within the specified limits.
FIGURE 4-2: Simplified Analog Input ESD
Structures.
In order to prevent damage and/or improper operation
of these amplifiers, t he circuit s they are in mus t limit the
currents (and voltages) at the VIN+ and VIN– pins (see
Section 1.1 “Maximum Ratings †” at the beginning of
Section 1.0 “Electrical Characteristics”). Figure 4-3
shows the reco mm en ded ap proach to pro tec tin g these
inputs. The internal ESD diodes prevent the input pins
(VIN+ and VIN–) from going too far below ground, and
the resistors R1 and R2 limit the possible current drawn
out of the input p in. Diodes D1 and D2 pr event the i nput
pin (VIN+ and VIN–) from going too far above VDD.
When im plement ed as s hown, res istors R1 and R2 also
limit the current through D1 and D2.
FIGURE 4-3: Protecting the Analog
Inputs.
-3
-2
-1
0
1
2
3
4
5
6
7
8
Time (100 ms/div)
Output Voltage (V)
-30
-25
-20
-15
-10
-5
0
5
10
15
20
25
Input Voltage (10 mV/div)
VOUT
VIN–
VDD = 5.0V
Hysteresis
Bond
Pad
Bond
Pad
Bond
Pad
VDD
VIN+
VSS
Input
Stage Bond
Pad VIN–
V1R1
VDD
D1
R2
VSS – (minimum expected V2)
2mA
VOUT
V2R2R3
D2
+
–
R1
VSS – (minimum expected V1)
2mA
VPU
R4
MCP656X
MCP6566/6R/6U/7/9
DS22143D-page 18 2009-2013 Microchip Technology Inc.
It is a lso pos sible to c onnect th e diodes to the lef t of the
resistors R1 and R2. In this case, the currents through
the diodes D1 and D2 nee d to be limi ted by som e other
mechanism. The resistor then se rves as in-rush current
limiter; the DC current into the input pins (VIN+ and
VIN–) shoul d be ve ry small.
A significant amount of current can flow out of the
inputs when th e c om mo n mo de vol t ag e (VCM) is be low
ground (VSS); see Figure 4-3. Applications that are
high-impedance may need to limit the usable voltage
range.
4.1.3 PHASE REVERSAL
The MCP6566/6R/6U/7/9 comparator family uses
CMOS transistors at the input. They are designed to
prevent phase inversion when the input pins exceed
the supp ly v oltag es. Figure 2-3 shows an in pu t vol tage
exceeding both supplies with no resulting phase
inversion.
4.2 Open-Drain Output
The open-drain output is designed to make
level-shifting a nd w ired-OR lo gic easy to implement .
The output stage minimizes switching current
(shoot-through current from supply-to-supply) when
the output changes state. See Figures 2-15,2-18,
2-35 and 2-36, for more inform ation.
4.3 Externally Set Hysteresis
Greater flexibility in selecting hysteresis (or input trip
points) is achieved by using external resistors.
Hyste resis redu ces outpu t chatterin g when one input is
slowly moving past the other. It also helps in systems
where it is best not to cycle between high and low
states too frequently (e.g., air conditioner thermostatic
control). Output chatter also increases the dynamic
supply current.
4.3.1 NON-INVERTING CIRCUIT
Figure 4-4 shows a non-inverting circuit for
single-supply applications using just two resistors. The
resulting hysteresis diagram is shown in Figure 4-5.
FIGURE 4-4: Non-Inverting Circuit with
Hysteresis for Single-Supply.
FIGURE 4-5: Hysteresis D iagram for the
Non-Inverting Circuit.
The trip points for Figures 4-4 and 4-5 are:
EQUATION 4-1:
VREF
VIN
VOUT
VDD
R1RF
+
-
VPU
RPU
MCP656X
VOUT
High-to-Low Low-to-High
VDD
VOH
VOL
VSSVSS VDD
VTHL VTLH
VIN
VTLH VREF 1R1
RF
-------+
VOL
R1
RF
-------
–=
VTHL VREF 1R1
RF
-------+
VOH
R1
RF
-------
–=
Where:
VTLH = trip voltage from low-to-high
VTHL = trip voltage from high-to-low
2009-2013 Microchip Technology Inc. DS22143D-page 19
MCP6566/6R/6U/7/9
4.3.2 INVERTING CIRCUIT
Figure 4-6 shows an inverting circuit for single-supply
using three resistors. The resulting hysteresis diagram
is shown in Figure 4-7.
FIGURE 4-6: Inverting Circuit with
Hysteresis.
FIGURE 4-7: Hysteresis Diagram for the
Inverting Circuit.
In order to d ete rmi ne the trip v oltages (VTHL and VTLH)
for the circuit shown in Figure 4-6, R2 and R3 can be
simplified to the Thevenin equivalent circuit with
respect to VDD, as shown in Figure 4-8.
FIGURE 4-8: Thev en in Equ iv al ent Circ uit .
Where:
Using this simplified circuit, the trip voltage can be
calculated using the following equation:
EQUATION 4-2:
Figure 2-21 and Figure 2-24 can be used to determine
typical values for VOH and VOL.
4.4 Bypass Capacitors
With this family of comparators, the power supply pin
(VDD for single supply) should have a local bypass
capa ci tor (i. e., 0. 01 µF to 0.1 µF) within 2 mm for good
edge rate performance.
4.5 Capacitive Loads
Reasonable capacitive loads (e.g., logic gates) have
little impact on propagation delay (see Figure 2-32).
The supply current increases with increasing toggle
frequency (Figure 2-20), especially with higher
capacitive loads. The output slew rate and propagation
delay performance will be reduced with higher
capacitive loads.
VIN
VOUT
VDD
R2
RF
R3
VDD
VPU
RPU
MCP656X
VOUT
High-to-LowLow-to-High
VDD
VOH
VOL
VSSVSS VDD
VTLH VTHL
VIN
V23
VOUT
VDD
R23 RF
+
-
VSS
VPU
RPU
MCP656X
R23 R2R3
R2R3
+
-------------------=
V23 R3
R2R3
+
-------------------V
DD
=
VTHL VOH R23
R23 RF
+
-----------------------
V23 RF
R23 RF
+
----------------------
+=
VTLH VOL R23
R23 RF
+
-----------------------
V23 RF
R23 RF
+
----------------------
+=
Where:
VTLH = trip voltage from low-to-high
VTHL = trip voltage from high-to-low
MCP6566/6R/6U/7/9
DS22143D-page 20 2009-2013 Microchip Technology Inc.
4.6 PCB Surface Leakage
In applications where low input bias current is critical,
PCB (Printed Circuit Board) surface leakage effects
need to be considered. Surface leakage is caused by
humidity, dust or other contamination on the board.
Under low humidity conditions, a typical resistance
betwee n nearby traces is 1012. A 5 V dif ference would
cause 5 pA of current to flow. This is greater than the
MCP6566/6R/6U/7/9 family’s bias current at +25°C
(1 pA, typical).
The easiest way to reduce surface leakage is to use a
guard ring around se ns itiv e p ins (or t rac es). The gua rd
ring is biased at the same voltage as the sensitive pin.
An example of this type of layout is shown in
Figure 4-9.
FIGURE 4-9: Example Guard Ring Layout
for Inverting Circuit.
1. Inverting Configuration (Figures 4-6 and 4-9):
a) Connect the guard ring to the non-inverting
input pin (VIN+). This biases the guard ring
to the same reference voltage as the
comparator (e.g., VDD/2 or ground).
b) Connect the inverting pin (VIN–) to the input
pad without touching the guard ring.
2. Non-inverting Configuration (Figure 4-4):
a) Connect the non-inverting pin (VIN+) to the
input pad without touching the guard ring.
b) Connect the guard ring to the inverting input
pin (VIN–).
4.7 PCB Layout Technique
When des igning the PCB layout, it is critical to note that
analog and digital signal traces are adequately
sepa rate d to preven t signal coup ling. If the co mp arat or
output trace is at close proximity to the input traces,
then large output voltage changes from, VSS to VDD or
visa versa, may couple to the inputs and cause the
device output to oscillate. To prevent such oscillation,
the output traces must be routed away from the input
pins. Th e SC70-5 and S OT-23-5 are rel ativ el y i mmun e
becaus e the out put pi n OUT (pin 1 ) is s ep arated by th e
power pin VDD/VSS (pin 2) from the input pin +IN (as
long as the analog and digital traces remain separated
througho ut the PCB). However, the pinout s for the dual
and quad p ackage s (SOIC, MSOP, TSSOP) have OUT
and -IN pins (pin 1 and 2) close to each other. The
recommended layout for these packages is shown in
Figure 4-10.
FIGURE 4-10: Recommended Layout.
4.8 Unused Comparators
An unused amplifier in a quad package (MCP6569)
should be configured as shown in Figure 4-11. This
circuit prevents the output from toggling and causing
crosstalk. It uses the minimum number of components
and draws minimal current (see Figure 2-15 and
Figure 2-15).
FIGURE 4-11: Unused Comparators.
Guard Ring
VSS
IN- IN+
-INA
+INA -INB
+INB
OUTB
OUTA
VSS
VDD
VDD
–
+
¼ MCP6569
2009-2013 Microchip Technology Inc. DS22143D-page 21
MCP6566/6R/6U/7/9
4.9 Typical Applications
4.9.1 PRECISE COMPARATOR
Some applications require higher DC precision. An
easy way to solve this problem is to use an amplifier
(such as the MCP6291) to gain-up the input signal
before it reaches the comparator. Figure 4-12 shows
an example of this approach.
FIGURE 4-12: Precise Inverting
Comparator.
4.9.2 WINDOWED COMPARATOR
Figure 4-13 shows one approach to designing a
windo wed comp arat or. The AND gate prod uces a logic
‘1’ when the input voltage is between VRB and VRT
(where VRT > VRB).
FIGURE 4-13: Windowed Comparator.
4.9.3 BISTABLE MULTIVIBRATOR
A simple bistable multivibrator design is shown in
Figure 4-14. VREF needs to be between the power
supplies (VSS = GND and VDD) to achieve oscillation.
The output duty cycle changes with VREF.
FIGURE 4-14: Bistable Multivibrator.
VREF
VDD
VDD
R1R2VOUT
VIN
VREF
MCP6291 VPU
RPU
MCP656X
VRT
VRB
VIN
VPU
RPU VOUT
1/2
MCP6567
1/2
MCP6567
VDD
R1R2
R3
VREF
C1
VOUT
VPU
RPU
MCP656X
MCP6566/6R/6U/7/9
DS22143D-page 22 2009-2013 Microchip Technology Inc.
NOTES:
2009-2013 Microchip Technology Inc. DS22143D-page 23
MCP6566/6R/6U/7/9
5.0 DESIGN AIDS
5.1 Microchip Advanced Part Selector
(MAPS)
MAPS is a software tool that helps semiconductor
professionals efficiently identify Microchip devices that
fit a particular design requirement. Available at no cost
from the Microchip web site at www.microchip.com/
maps, the MAPS is an overall selection tool for
Microchip’s product portfolio that includes Analog,
Memory, MCUs and DSCs. Using this tool you can
define a filte r to sort fea tures for a p aram etric searc h of
devices and export side-by-side technical comparison
reports. Help f ul l ink s are a ls o pro vided for data she et s ,
purchase, and sampling of Microchip parts.
5.2 Analog Demonstration and
Evaluation Boards
Microchip offers a broad spectrum of Analog
Demonstration and Evaluation Boards that are
design ed to help you ach ieve fas ter time to market. F or
a complete listing of these boards and their
corresp onding u ser’s gui des and t echni cal i nfo rmatio n,
visit the Microchip web site at www.microchip.com/
analogtools. Three of our boards that are especially
useful are:
• 8-Pin SOIC/MSOP/TSSOP/DIP Evaluation Board,
P/N SOIC8EV
• 14-Pin SOIC/TSSOP/DIP Evaluation Board, P/N
SOIC14EV
• 5/6-Pin SOT23 Evaluation Board, P/N VSUPEV2
5.3 Application Notes
The following Microchip Application Note is available
on the M icrochip web site at www.microchip.com and is
recommended as a supplemental reference resource:
•AN895, “Oscillator Circu it For R TD Tem peratu r e
Sensors”, DS00895.
MCP6566/6R/6U/7/9
DS22143D-page 24 2009-2013 Microchip Technology Inc.
NOTES:
2009-2013 Microchip Technology Inc. DS22143D-page 25
MCP6566/6R/6U/7/9
6.0 PACKAGING INFORMATION
6.1 Package Marking Information
Legend: XX...X Customer-specific information
Y Year code (last digit of calendar year)
YY Year code (last 2 digits of calendar year)
WW Week code (week of January 1 is week ‘01’)
NNN Alphanume ric trac ea bil ity code
Pb-free JEDEC designator for Matte Tin (Sn)
*This package is P b-free. The Pb-free JEDEC designa tor ( )
can be found on the outer packaging for this package.
Note: In the event the full M icroc hip p art numb er cann ot be mark ed on one line, it w ill
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
3
e
3
e
5-Lead SC70 (MCP6566) Example:
XXNN
5-Lead SOT-23 (MCP6566, MCP6566R) Example:
XXNN JY25
BJ25
8-Lead SOIC (150 mil) (MCP6567) Example:
XXXXXXXX
XXXXYYWW
NNN
MCP6567E
SN^^1302
256
3
e
8-Lead MSOP (MCP6567) Example:
XXXXXX
YWWNNN
6567E
302256
Device Code
MCP6566T JYNN
MCP6566RT JZNN
MCP6566UT WLNN
Note: Applies to 5-Lead SOT-23.
MCP6566/6R/6U/7/9
DS22143D-page 26 2009-2013 Microchip Technology Inc.
Package Marking Information (Continued)
14-Lead TSSOP (MCP6569)
XXXXXXXX
YYWW
NNN
Example:
MCP6569E
1302
256
14-Lead SOIC (150 mil) (MCP6569) Example:
XXXXXXXXXX
YYWWNNN
XXXXXXXXXX MCP6569
1302256
E/SL^^
3
e
2009-2013 Microchip Technology Inc. DS22143D-page 27
MCP6566/6R/6U/7/9
D
b
1
23
E1
E
45
ee
c
L
A1
AA2
MCP6566/6R/6U/7/9
DS22143D-page 28 2009-2013 Microchip Technology Inc.
2009-2013 Microchip Technology Inc. DS22143D-page 29
MCP6566/6R/6U/7/9
!
φ
N
b
E
E1
D
123
e
e1
A
A1
A2 c
L
L1
MCP6566/6R/6U/7/9
DS22143D-page 30 2009-2013 Microchip Technology Inc.
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2009-2013 Microchip Technology Inc. DS22143D-page 31
MCP6566/6R/6U/7/9
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
MCP6566/6R/6U/7/9
DS22143D-page 32 2009-2013 Microchip Technology Inc.
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2009-2013 Microchip Technology Inc. DS22143D-page 33
MCP6566/6R/6U/7/9
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
MCP6566/6R/6U/7/9
DS22143D-page 34 2009-2013 Microchip Technology Inc.
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2009-2013 Microchip Technology Inc. DS22143D-page 35
MCP6566/6R/6U/7/9
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
MCP6566/6R/6U/7/9
DS22143D-page 36 2009-2013 Microchip Technology Inc.
"#$%!&'()*
2009-2013 Microchip Technology Inc. DS22143D-page 37
MCP6566/6R/6U/7/9
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
MCP6566/6R/6U/7/9
DS22143D-page 38 2009-2013 Microchip Technology Inc.
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2009-2013 Microchip Technology Inc. DS22143D-page 39
MCP6566/6R/6U/7/9
MCP6566/6R/6U/7/9
DS22143D-page 40 2009-2013 Microchip Technology Inc.
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2009-2013 Microchip Technology Inc. DS22143D-page 41
MCP6566/6R/6U/7/9
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
MCP6566/6R/6U/7/9
DS22143D-page 42 2009-2013 Microchip Technology Inc.
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2009-2013 Microchip Technology Inc. DS22143D-page 43
MCP6566/6R/6U/7/9
APPENDIX A: REVISION HISTORY
Revision D (February 2013)
The following is the list of modifications:
1. Added the Analog Input (VIN) parameter in
Section 1.0 “Electrical Characteristics”.
Revision C (February 2011)
The following is the list of modifications:
1. Rep laced the MCP54 68 p ackag e name with th e
correct M CP6567 pac kage name on p age 1 and
in Table 3-1.
Revision B (August 2009)
The following is the list of modifications:
1. Added MCP6566U throughout the document.
2. Updated package outline drawings.
Revision A (March 2009)
• Original Release of thi s Document.
MCP6566/6R/6U/7/9
DS22143D-page 44 2009-2013 Microchip Technology Inc.
NOTES:
2009-2013 Microchip Technology Inc. DS22143D-page 45
MCP6566/6R/6U/7/9
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
Device: MCP6566T: Single Com para tor (Ta pe and Reel )
(SC 70, SOT-23)
MCP6566 R T: Single Compara tor (Tape and Reel)
(SOT-23 only)
MCP6566 U T: Single Compara tor (Tape and Reel)
(SOT-23 only)
MCP6567: Dual Comparator
MCP6567T: Dual Comparator (Tape and Reel)
MCP6569: Quad Comparator
MCP6569T: Quad Comparator (Tape and Reel)
Temperature
Range: E= -40
C to +125C
Package: LT = Plastic Small Outline Transistor (SC70), 5-lead
OT = Plastic Small Outline Transistor (SOT -23), 5-lead
MS = Plastic Micro Small Outline Transistor, 8-lead
SN = Plastic Small Outline Transistor, 8-lead
ST = Plastic Thin Shrink Small Outline Transistor, 14-lead
SL = Plastic Small Outline Transistor, 14-lead
Examples:
a) MCP6566T-E/LT: Tape and Reel,
Extended Temper ature,
5LD SC70 package.
b) MCP6566T-E/OT: Tape and Reel
Extended Temper ature,
5LD SOT-23 package.
a) MCP6566RT-E/OT: Tape and Reel
Extended Temper ature,
5LD SOT-23 package.
a) MCP6566UT-E/OT: Tape and Reel
Extended Temper ature,
5LD SOT-23 package.
a) MCP6567-E/MS: Extended Temperature
8LD MSOP package.
b) MCP6567-E/SN: Extended Temperature
8LD SOIC package.
a) MCP6569T-E/SL: Tape and Reel
Extended Temper ature
14LD SOIC package.
b) MCP6569T-E/ST: Tape and Reel
Extended Temper ature
14LD TSSOP package.
PART NO. X/XX
PackageTemperature
Range
Device
–
MCP6566/6R/6U/7/9
DS22143D-page 46 2009-2013 Microchip Technology Inc.
NOTES:
2009-2013 Microchip Technology Inc. DS22143D-page 47
Information contained in this publication regarding device
applications a nd the lik e is provid ed only for your convenien ce
and may be supers ed ed by u pdates. I t is y our responsibil it y to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights.
Trademarks
The Microchip name and logo, the Microchip logo, dsPIC,
FlashFlex, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro,
PICSTART, PIC32 logo, rfPIC, SST, SST Logo, SuperFlash
and UNI/O are registered trademarks of Microchip T echnology
Incorporated in the U.S.A. and other countries.
FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor,
MTP, SEEVAL and The Embedded Control Solutions
Company are registered trademarks of Microchip Technology
Incorporated in the U.S.A.
Silicon Storage Technology is a registered trademark of
Microchip Technology Inc. in other countries.
Analog-for-the-Digital Age, Application Maestro, BodyCom,
chipKIT, chipKIT logo, CodeGuard, dsPICDEM ,
dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,
ECONOMONIT OR, FanSense, HI- TIDE , In - Circuit Seria l
Programm ing, ICSP, Mindi, MiWi, MPASM, MPF, MPLAB
Certified logo, MPLIB, MPLINK, mTouch, Omniscient Code
Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit,
PICtail, REAL ICE, rfLAB, Select Mode, SQI, Serial Quad I/O,
Total Endurance, TSHARC, UniWinDriver, WiperLock, ZENA
and Z-Scale are trademarks of Microchip Technology
Incorporated in the U.S.A. and other countries.
SQTP is a service mark of Microchip T echnology Incorporated
in the U.S.A.
GestIC and ULPP are registered trademarks of Microchip
Technology Germany II GmbH & Co. & KG, a subsidiary of
Microchip Technology Inc., in other countries.
All other trademarks mentioned herein are property of their
respective companies.
© 2009-2013, Microchip Technology Incorporated, Printed in
the U.S.A., All Rights Reserved.
Printed on recycled paper.
ISBN: 978-1-62077-030-6
Note the following details of the code protection feature on Microchip devices:
• Microchip products meet the specification contained in their particular Microchip Data Sheet.
• Microchip believes that it s family of products is one of the most secure families of it s kind on the market today, when used in the
intended manner and under normal conditions.
• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
• Microchip is willing to work with the customer who is concerned about the integrity of their code.
• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is c onstantly evolving. We a t Microc hip are co m mitted to continuously improving the code prot ect ion featur es of our
products. Attempts to break Microchip’ s code protection feature may be a violation of the Digital Millennium Copyright Act. If such act s
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Microchip received ISO/TS-16949:2009 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperiph erals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
QUALITY MANAGEMENT S
YSTEM
CERTIFIED BY DNV
== ISO/TS 16949 ==
DS22143D-page 48 2009-2013 Microchip Technology Inc.
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