1
Data sheet acquired from Harris Semiconductor
SCHS243A
CD54AC191,
CD54ACT191
Presettable Synchronous 4-Bit Binary
Up/Down Counter
Features
• Buffered Inputs
• Typical Propagation Delay
- 12.8ns at VCC = 5V, TA = 25oC, CL = 50pF
• Exceeds 2kV ESD Protection MIL-STD-883, Method
3015
• SCR-Latchup-Resistant CMOS Process and Circuit
Design
• Speed of Bipolar FAST™/AS/S with Significantly
Reduced Power Consumption
• Balanced Propagation Delays
• AC Types Feature 1.5V to 5.5V Operation and
Balanced Noise Immunity at 30% of the Supply
•±24mA Output Drive Current
- Fanout to 15 FAST™ ICs
- Drives 50Ω Transmission Lines
Description
The CD54AC191 and CD54ACT191 are asynchronously
presettable binary up/down synchronous counters that utilize
Advanced CMOS Logic technology. Presetting the counter to
the number on preset data inputs (P0-P3) is accomplished
by setting LOW the asynchronous parallel load input (PL).
Counting occurs when PL is HIGH, Count Enable (CE) is
LOW, and the Up/Down (U/D) input is either LOW for up-
counting or HIGH for down-counting. The counter is incre-
mented or decremented synchronously with the LOW-to-
HIGH transition of the clock.
When an overflow or underflow of the counter occurs, the
Terminal Count (TC) output, which is LOW during counting,
goes HIGH and remains HIGH for one clock cycle. This out-
put can be used for look-ahead carry in high-speed cascad-
ing (see Figure 12). The TC output also initiates the Ripple
Clock (RC) output which, normally HIGH, goes LOW and
remains LOW for the low-level cascaded using the Ripple
Count output.
Pinout
CD54AC191, CD54ACT191
(CERDIP)
TOP VIEW
Ordering Information
PART
NUMBER TEMP.
RANGE (oC) PACKAGE
CD54AC191F3A -55 to 125 16 Ld CERDIP
CD54ACT191F3A -55 to 125 16 Ld CERDIP
NOTES:
1. When ordering, use the entire part number. Add the suffix 96 to
obtain the variant in the tape and reel.
2. Wafer and die for this part number is available which meets all elec-
trical specifications. Please contact your local TI sales office or cus-
tomer service for ordering information.
14
15
16
9
13
12
11
10
1
2
3
4
5
7
6
8
P1
Q1
Q0
CE
U/D
Q2
GND
Q3
VCC
CP
RC
TC
PL
P2
P3
P0
October 1998 - Revised May 2000
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
FAST™ is a Trademark of Fairchild Semiconductor.
Copyright © 2000, Texas Instruments Incorporated
2
Functional Diagram
TRUTH TABLE
INPUTS
FUNCTIONPL CE U/D CP
HLL ↑Count Up
HLH ↑Count Down
L X X X Asynchronous Preset
H H X X No Change
U/D or CE should be changed only when clock is high.
X = Don’t Care
↑ = Low-to-High clock transition.
ASYN. PARALLEL
CLOCK
UP/DOWN
11
14
5
15 1 10 9
3
2
6
7
12
Q0
Q1
Q2
Q3
TERMINAL
P0 P1 P2 P3
BINARY
PRESET
COUNT 413 RIPPLE CLOCK
ENABLE
LOAD ENABLE
COUNT
BINARY
OUTPUTS
CD54AC191, CD54ACT191
3
Absolute Maximum Ratings Thermal Information
DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 6V
DC Input Diode Current, IIK
For VI < -0.5V or VI > VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA
DC Output Diode Current, IOK
For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±50mA
DC Output Source or Sink Current per Output Pin, IO
For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±50mA
DC VCC or Ground Current, ICC or IGND (Note 3) . . . . . . . . .±100mA
Operating Conditions
Temperature Range, TA . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC
Supply Voltage Range, VCC (Note 4)
AC Types. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1.5V to 5.5V
ACT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V
DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC
Input Rise and Fall Slew Rate, dt/dv
AC Types, 1.5V to 3V . . . . . . . . . . . . . . . . . . . . . . . . . 50ns (Max)
AC Types, 3.6V to 5.5V. . . . . . . . . . . . . . . . . . . . . . . . 20ns (Max)
ACT Types, 4.5V to 5.5V. . . . . . . . . . . . . . . . . . . . . . . 10ns (Max)
Thermal Resistance (Typical, Note 5) θJA (oC/W)
PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ___
SOIC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . ___
Maximum Junction Temperature (Hermetic P ac kage or Die) . . . 175oC
Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC
Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . . 300oC
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
3. For up to 4 outputs per device, add ±25mA for each additional output.
4. Unless otherwise specified, all voltages are referenced to ground.
5. θJA is measured with the component mounted on an evaluation PC board in free air.
DC Electrical Specifications
PARAMETER SYMBOL
TEST
CONDITIONS VCC
(V)
25oC-40oC TO
85oC-55oC TO
125oC
UNITSVI(V) IO(mA) MIN MAX MIN MAX MIN MAX
AC TYPES
High Level Input Voltage VIH - - 1.5 1.2 - 1.2 - 1.2 - V
3 2.1 - 2.1 - 2.1 - V
5.5 3.85 - 3.85 - 3.85 - V
Low Level Input Voltage VIL - - 1.5 - 0.3 - 0.3 - 0.3 V
3 - 0.9 - 0.9 - 0.9 V
5.5 - 1.65 - 1.65 - 1.65 V
High Level Output Voltage VOH VIH or VIL -0.05 1.5 1.4 - 1.4 - 1.4 - V
-0.05 3 2.9 - 2.9 - 2.9 - V
-0.05 4.5 4.4 - 4.4 - 4.4 - V
-4 3 2.58 - 2.48 - 2.4 - V
-24 4.5 3.94 - 3.8 - 3.7 - V
-75
(Note 6, 7) 5.5 - - 3.85 - - - V
-50
(Note 6, 7) 5.5----3.85 - V
CD54AC191, CD54ACT191
4
Low Level Output Voltage VOL VIH or VIL 0.05 1.5 - 0.1 - 0.1 - 0.1 V
0.05 3 - 0.1 - 0.1 - 0.1 V
0.05 4.5 - 0.1 - 0.1 - 0.1 V
12 3 - 0.36 - 0.44 - 0.5 V
24 4.5 - 0.36 - 0.44 - 0.5 V
75
(Note 6, 7) 5.5 - - - 1.65 - - V
50
(Note 6, 7) 5.5-----1.65 V
Input Leakage Current IIVCC or
GND - 5.5 - ±0.1 - ±1-±1µA
Quiescent Supply Current
MSI ICC VCC or
GND 0 5.5 - 8 - 80 - 160 µA
ACT TYPES
High Level Input Voltage VIH - - 4.5 to
5.5 2-2-2-V
Low Level Input Voltage VIL - - 4.5 to
5.5 - 0.8 - 0.8 - 0.8 V
High Level Output Voltage VOH VIH or VIL -0.05 4.5 4.4 - 4.4 - 4.4 - V
-24 4.5 3.94 - 3.8 - 3.7 - V
-75
(Note 6, 7) 5.5 - - 3.85 - - - V
-50
(Note 6, 7) 5.5----3.85 - V
Low Level Output Voltage VOL VIH or VIL 0.05 4.5 - 0.1 - 0.1 - 0.1 V
24 4.5 - 0.36 - 0.44 - 0.5 V
75
(Note 6, 7) 5.5 - - - 1.65 - - V
50
(Note 6, 7) 5.5-----1.65 V
Input Leakage Current IIVCC or
GND - 5.5 - ±0.1 - ±1-±1µA
Quiescent Supply Current
MSI ICC VCC or
GND 0 5.5 - 8 - 80 - 160 µA
AdditionalSupplyCurrent per
Input Pin TTL Inputs High
1 Unit Load
∆ICC VCC
-2.1 - 4.5 to
5.5 - 2.4 - 2.8 - 3 mA
NOTES:
6. Test one output at a time for a 1-second maximum duration. Measurement is made by forcing current and measuring voltage to minimize
power dissipation.
7. Test verifies a minimum 50Ω transmission-line-drive capability at 85oC, 75Ω at 125oC.
ACT Input Load Table
INPUT UNIT LOAD
P0-P3, PL 0.75
CL, U/D, CE 0.85
NOTE: Unit load is ∆ICC limit specified in DC Electrical Specifications
Table, e.g., 2.4mA max at 25oC.
DC Electrical Specifications (Continued)
PARAMETER SYMBOL
TEST
CONDITIONS VCC
(V)
25oC-40oC TO
85oC-55oC TO
125oC
UNITSVI(V) IO(mA) MIN MAX MIN MAX MIN MAX
CD54AC191, CD54ACT191
5
Prerequisite For Switching Function
PARAMETER SYMBOL VCC (V)
-40oC TO 85oC -55oC TO 125oC
UNITSMIN MAX MIN MAX
AC TYPES
Max. Frequency fMAX
(Note 10) 1.5 5.5 - 4.8 - MHz
3.3
(Note 8) 49 - 43 - MHz
5
(Note 9) 68 - 60 - MHz
CP Pulse Width tW1.5 91 - 104 - ns
3.3 10.5 - 11.6 - ns
5 7.3 - 8.3 - ns
PL Pulse Width tW1.5 66 - 75 - ns
3.3 7.4 - 8.4 - ns
5 5.3 - 6 - ns
Recovery Time tREC 1.5 71 - 81 - ns
3.3 8 - 9.1 - ns
5 5.7 - 6.5 - ns
Set-Up Time, Pn to PL tSU 1.5 44 - 50 - ns
3.3 4.9 - 5.6 - ns
5 3.5 - 4 - ns
Set-Up Time, CE to CP tSU 1.5 115 - 131 - ns
3.3 12.9 - 14.7 - ns
5 9.2 - 10.5 - ns
Set-Up Time, U/D to CP tSU 1.5 132 - 150 - ns
3.3 14.7 - 16.8 - ns
5 10.5 - 12 - ns
Hold Time, Pn to PL tH1.5 22 - 25 - ns
3.3 2.5 - 2.8 - ns
52-2-ns
Hold Time, CE to CP tH1.5 0 - 0 - ns
3.3 0 - 0 - ns
50-0-ns
Hold Time, U/D to CP tH1.5 0 - 0 - ns
3.3 0 - 0 - ns
50-0-ns
ACT TYPES
Max. Frequency fMAX
(Note 10) 5
(Note 9) 68 - 60 - MHz
CP Pulse Width tW5 7.3 - 8.3 - ns
PL Pulse Width tW5 5.3 - 6 - ns
Recovery Time tREC 5 5.7 - 6.5 - ns
Set-Up Time, Pn to PL tSU 5 3.5 - 4 - ns
CD54AC191, CD54ACT191
6
Set-Up Time, CE to CP tSU 5 9.2 - 10.5 - ns
Set-Up Time, U/D to CP tSU 5 10.5 - 12 - ns
Hold Time, Pn to PL tH52-2-ns
Hold Time, CE to CP tH50-0-ns
Hold Time, U/D to CP tH50-0-ns
NOTES:
8. 3.3V Min is at 3V.
9. 5V Min is at 4.5V.
10. Applies to non-cascaded operation only. With cascaded counters clock-to-terminal count propagation delays, count enable (CE)-to-clock
set-up times, and count enable (CE)-to-clock hold times determine max clock frequency. For example, with these AC devices at 85oC
and VCC = 5V:.
Switching Specifications Input tr, tf = 3ns, CL= 50pF (Worst Case)
PARAMETER SYMBOL VCC (V)
-40oC TO 85oC -55oC TO 125oC
UNITSMIN TYP MAX MIN TYP MAX
AC TYPES
Propagation Delay
PL to Qn tPLH, tPHL 1.5 - - 171 - - 188 ns
3.3
(Note 12) 5.4 - 19.1 5.3 - 21 ns
5
(Note 13) 3.9 - 13.6 3.8 - 15 ns
Propagation Delay
Pn to Qn tPLH, tPHL 1.5 - - 173 - - 190 ns
3.3 5.4 - 19.4 5.3 - 21.3 ns
5 3.9 - 13.8 3.8 - 15.2 ns
Propagation Delay
CP to Qn tPLH, tPHL 1.5 - - 182 - - 200 ns
3.3 5.8 - 20.4 5.6 - 22.4 ns
5 4.1 - 14.5 4 - 16 ns
Propagation Delay
CP to RC tPLH, tPHL 1.5 - - 136 - - 150 ns
3.3 4.3 - 15.3 4.2 - 16.8 ns
5 3.1 -113 -12ns
Propagation Delay
CP to TC tPLH, tPHL 1.5 - - 227 - - 250 ns
3.3 7.2 - 25.5 7 - 28 ns
5 5.2 - 18.2 5 - 20 ns
Propagation Delay
U/D to RC tPLH, tPHL 1.5 - - 246 - - 271 ns
3.3 7.8 - 27.6 7.6 - 30.4 ns
5 5.6 - 19.7 5.4 - 21.7 ns
Propagation Delay
U/D to TC tPLH, tPHL 1.5 - - 160 - - 176 ns
3.3 5.1 - 17.9 4.9 - 19.7 ns
5 3.6 - 12.8 3.5 - 14.1 ns
Prerequisite For Switching Function (Continued)
PARAMETER SYMBOL VCC (V)
-40oC TO 85oC -55oC TO 125oC
UNITSMIN MAX MIN MAX
fMAX CP() 1
CP-to-TC prop. delay + CE-to-CP setup + CE-to-CP Hold
--------------------------------------------------------------------------------------------------------------------------------------------------------1
18.2 9.2 0++
------------------------------------36MHz≈==
CD54AC191, CD54ACT191
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Propagation Delay
CE to RC tPLH, tPHL 1.5 - - 137 - - 151 ns
3.3 4.4 - 15.4 4.2 - 16.9 ns
5 3.1 - 11 3 - 12.1 ns
Input Capacitance CI- - -10- -10pF
Power Dissipation Capacitance CPD
(Note 14) - - 96 - - 96 - pF
ACT TYPES
Propagation Delay
PL to Qn tPLH, tPHL 5
(Note 13) 4.2 - 14.8 4.1 - 16.3 ns
Propagation Delay
Pn to Qn tPLH, tPHL 5 3.9 - 13.8 3.8 - 15.2 ns
Propagation Delay
CP to Qn tPLH, tPHL 5 4.1 - 14.5 4 - 16 ns
Propagation Delay
CP to RC tPLH, tPHL 5 3.1 - 10.9 3 - 12 ns
Propagation Delay
CP to TC tPLH, tPHL 5 5.2 - 18.2 5 - 20 ns
Propagation Delay
U/D to RC tPLH, tPHL 5 5.6 - 19.7 5.4 - 21.7 ns
Propagation Delay
U/D to TC tPLH, tPHL 5 3.8 - 13.5 3.7 - 14.9 ns
Propagation Delay
CE to RC tPLH, tPHL 5 3.3 - 11.5 3.2 - 12.7 ns
Input Capacitance CI- - -10- -10pF
Power Dissipation Capacitance CPD
(Note 14) - - 96 - - 96 - pF
NOTES:
11. Limits tested 100%.
12. 3.3V Min is at 3.6V, Max is at 3V.
13. 5V Min is at 5.5V, Max is at 4.5V
14. CPD is used to determine the dynamic power consumption per package.
PD=C
PDVCC2fi+(C
L+V
CC2f
o) where fi= input frequency, fo= output frequency, CL= output load capacitance, VCC = supply voltage.
FIGURE 1. FIGURE 2.
Switching Specifications Input tr, tf = 3ns, CL= 50pF (Worst Case) (Continued)
PARAMETER SYMBOL VCC (V)
-40oC TO 85oC -55oC TO 125oC
UNITSMIN TYP MAX MIN TYP MAX
1/fMAX
CP
Qn OR TC
VS
tPHL
tW
tPLH
INPUT LEVEL
VSVS
VSCP OR CE
RC
tPHL
INPUT LEVEL
tPLH
VS
VS
VS
VS
CD54AC191, CD54ACT191
8
FIGURE 3. FIGURE 4.
FIGURE 5.
The shaded areas indicate when the input is permitted to change for
predictable output performance.
FIGURE 6.
FIGURE 7. FIGURE 8.
Pn INPUT LEVEL
VS
Qn
tPHL tPLH
VS
VS
VS
INPUT LEVEL
Pn tW
PL VS
tPLH
Qn
tPHL
VS
VSVS
INPUT LEVEL
PL
CP
Qn
tW
VS
tREC
INPUT LEVEL
INPUT LEVEL
Pn
PL
Qn
tSU(H)
VStH(H) tSU(L) tH(L)
INPUT LEVEL
INPUT LEVEL
VS
VS
VS
U/D VS
tPLH
TC
tPHL
RC
INPUT LEVEL
tPHL
tPLH
VS
VS
VSVS
VS
CP VS
CE CE MAY
CHANGE
tSU(L)
(H-L)
ONLY
tH(L)
CE MAY
CHANGE
VS
VS
VS
tSU(H)
INPUT
LEVEL
INPUT
LEVEL
DUT
OUTPUT
RL (NOTE)
OUTPUT
LOAD
500Ω
CL
50pF
NOTE: For AC Series Only: When VCC = 1.5V, RL = 1kΩ.
FIGURE 9. PROPAGATION DELAY TIMES
AC ACT
Input Level VCC 3V
Input Switching Voltage, VS0.5 VCC 1.5V
Output Switching Voltage, VS0.5 VCC 0.5 VCC
CD54AC191, CD54ACT191
9
Sequence:
1. Load (preset) to binary thirteen.
2. Count up to fourteen, fifteen, zero, one, and two.
3. Inhibit.
4. Count down to one, zero, fifteen, fourteen, and thirteen.
FIGURE 10. CD54AC191 DECODE COUNTERS TYPICAL LOAD, COUNT, AND INHIBIT SEQUENCES
FIGURE 11. SYNCHRONOUS N-STAGE COUNTER WITH PARALLEL GATED TC/RC
FIGURE 12. SYNCHRONOUS N-STAGE COUNTER USING RIPPLE TC/RC
LOAD
PRESET
INPUTS
P0
P1
P2
P3
CLOCK
DOWN/UP
ENABLE
Q0
Q1
Q2
Q3
TERMINAL COUNT
RIPPLE CLOCK
LOAD
H
L
13 14 15 0 1 2
COUNT UP INHIBIT COUNT DOWN
2 2 1 0 15 14 13
L
L
L
L
L
H
H
H
H
H
H
U/D
CE
CP TC
U/D
CE
CP TC
U/D
CE
CP TC
DIRECTION
CONTROL
ENABLE
CLOCK
U/D
CE
CP
RC U/D
CE
CP
RC U/D
CE
CP
RC
DIRECTION
CONTROL
ENABLE
CLOCK
CD54AC191, CD54ACT191
IMPORTANT NOTICE
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any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty . Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
Customers are responsible for their applications using TI components.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
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party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.
Copyright 2000, Texas Instruments Incorporated
