MT48LC2M32B2TG-6:G - Micron Technology

Products and specifications discussed herein are subject to change by Micron without notice.

64Mb: x32 SDRAM

Features

PDF: 09005aef811ce1fe/Source: 09005aef811ce1d5 Micron Technology, Inc., reserves the right to change products or specifica tions without notice.

Synchronous DRAM

MT48LC2M32B2 – 512K x 32 x 4 banks

For the latest data sheet, refer to Micr on’s Web site

Features

• PC100 functionality

• Fully synchronous; all signals registere d on positi ve

edge of system clock

• Internal pipe lined operatio n; column addres s can be

changed every clock cycle

• Internal banks for hiding row access/pr echarge

• Programmable burst lengths: 1, 2, 4, 8, or full page

• A uto prechar ge, includes concurr ent auto precharge ,

and auto refresh modes

• Self refresh mode (not available on AT devices)

•Refresh

–64ms, 4,096-cycle refresh (15.6µs/row)

(commercial, industrial)

–16ms, 4,096-cycle refresh (3.9µs/row)

(automotive)

• LVTTL-compatible inputs and outputs

• Single +3.3V ±0.3V power supply

• Supports CAS latency (CL) of 1, 2, and 3

Notes: 1. Off-center parting line.

2. Available on -6 and -7.

3. Contact Micron for product availability.

Options Marking

•Configuration

–2 Meg x 32 (512K x 32 x 4 banks) 2M32B2

•Plastic package – OCPL

–86-pin TSOP II (400 mil) TG

–86-pin TSOP II (400 mil) Pb-free P

–90-ball VFBGA (8mm x 13mm ) P b-free B5

• Timing (cycle time)

–5ns (200 MHz) -5

–5.5ns (183 MHz) -55

–6ns (166 MHz) -6

–7ns (143 MHz) -7

•Die revision :G

• Operating temperature range

–Commercial (0° to +70°C) None

–Industrial (–40°C to +85°C) IT2

–Au tomotive (–40°C to +105°C) AT3

Notes: 1. FBGA Device Decode: http://

www.micron.com/support/FBGA/FBGA.asp

Part Num ber Example:

MT48LC2M32B2P-7:G

Table 1: Address Table

2 Meg x 32

Configuration 512K x 32 x 4 banks

Refresh count 4K

Row addressing 2K (A0–A10)

Bank addressing 4 (BA0, BA1)

Column addressing 256 (A0–A7)

Table 2: Key Timing Parameters

CL = CAS (READ) latency

Speed

Grade Clock

Frequency

Access

Time Setup

Time Hold

TimeCL = 3

-5 200 MHz 4.5ns 1.5ns 1ns

-55 183 MHz 5ns 1.5ns 1ns

-6 166 MHz 5.5ns 1.5ns 1ns

-7 143 MHz 5.5ns 2ns 1ns

Table 3: 64Mb (x32) SDRAM Part Number

Part Number Architecture

MT48LC2M32B2TG 2 Meg x 32

MT48LC2M32B2P 2 Meg x 32

MT48LC2M32B2B512 Meg x 32

PDF: 09005aef811ce1fe/Source: 09005aef811ce1d5 Micron Technology, Inc., reserves the right to change products or specifica tions without notice.

64Mb: x32 SDRAM

General Description

The Micron® 64Mb SDRAM is a high-speed CMOS, dynamic random-access memory

containing 67,108,864 bits. It is internally configured as a quad-bank DRAM with a

synchronous inte rface (all signals are register ed on the positive edge of the clock signal,

CLK). Each of the 16,777,216-bit banks is organized as 2,048 rows by 256 columns by 32

bits.

Read and write accesses to the SDRAM are burst oriented; accesses start at a selected

location and continue for a programmed number of locations in a programmed

sequence. Accesses beg in with the registration of an ACTIVE command, which is then

followed by a READ or WRITE command. The address bits registered coincident with the

ACTIVE command are used to select the bank and row to be accessed (BA0, BA1 select

the bank, A0–A10 select the row). The address bits registered coincident with the READ

or WRITE command are used to select the starting column location for the burst access.

The SDRAM provides for programmable read or write burst lengths (BL) of 1, 2, 4, or 8

locations, or the full page, with a burst terminate option. An auto precharge function

may be enabled to provide a self-timed row precharge that is initiated at the end of the

burst sequence.

The 64Mb SDRAM uses an internal pipelined architecture to achieve high-speed opera-

tion. This architecture is compatible with the 2n rule of prefetch architectures, but it also

allows the column address to be changed on every clock cycle to achieve a high-speed,

fully random access. Precharging one bank while accessing one of the other three banks

will hide the PRECHARGE cycles and pr ovide seamless, hig h-speed, random-access

operation.

The 64Mb SDRAM is designed to operate in 3.3V, low-power memory sy st ems. An auto

refresh mode is provided, along with a power-s aving, power-down mode . All inp uts a nd

outputs are LVTTL-compatible.

SDRAMs offer substantial advances in DRAM operating performance, including the

ability to synchronously burst data at a high data rate with automatic column-address

generation, the ability to interleave be tween internal banks to hide precharge time and

the capability to randomly change column addresses on each clock cycl e during a burst

access.

Automotive Temperature

The automotive temperature (AT) option adheres to the following specifications:

• 16ms refresh rate

• Self refresh not supported

• Ambient and case temperatures cannot be less than –40°C or greater than 105°C

PDF: 09005aef811ce1fe/Source: 09005aef811ce1d5 Micron Technology, Inc., reserves the right to change products or specifica tions without notice.

64Mb: x32 SDRAM

Table of Contents

Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1

Options. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1

General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2

Automotive Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2

Functional Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6

Pin/Ball Assignments and Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7

Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

Register Definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

Mode Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

Burst Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

Burst Type. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

CAS Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14

Operating Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

Write Burst Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

COMMAND INHIBIT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

NO OPERATION (NOP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

LOAD MODE REGISTER. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

ACTIVE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

READ. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

WRITE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

PRECHARGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

BURST TERMINATE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

AUTO REFRESH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

SELF REFRESH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

Bank/Row Activation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

READs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

WRITEs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29

PRECHARGE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32

Power-Down. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33

Clock Suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34

Burst Read/Single Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35

Concurrent Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36

Electrical Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43

Temperature and Thermal Impedance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43

Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49

Timing Diagrams. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51

Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68

PDF: 09005aef811ce1fe/Source: 09005aef811ce1d5 Micron Technology, Inc., reserves the right to change products or specifica tions without notice.

64Mb: x32 SDRAM

List of Figur es

List of Figures

Figure 1: 2 Meg x 32 SDRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6

Figure 2: 86-Pin TSOP (Top View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7

Figure 3: 90-Ball VFBGA (Top View, Ball Down) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8

Figure 4: Mode Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

Figure 5: CAS Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

Figure 6: Acti vating a Specific Row in a Specific Bank . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

Figure 7: Example: Meeting tRCD (MIN) when 2 < tRCD (MIN)/tCK - 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

Figure 8: READ Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

Figure 9: CAS Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22

Figure 10: Consecutive READ Bursts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

Figure 11: Random READ Accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24

Figure 12: READ-to-WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25

Figure 13: READ-to-WRITE With Extra Clock Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

Figure 14: READ-to-PRECHARGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27

Figure 15: Terminating a READ Burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

Figure 16: WRITE Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29

Figure 17: WRITE Burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30

Figure 18: WRITE-to-WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30

Figure 19: Random WRITE Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31

Figure 20: WRITE-to-READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31

Figure 21: WRITE-to-PRECHARGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32

Figure 22: Terminating a WRITE Burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33

Figure 23: PRECHARGE Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34

Figure 24: Power-Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34

Figure 25: Clock Suspend During WRITE Burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35

Figure 26: Clock Suspend During READ Burs t . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35

Figure 27: READ with Auto Precharge Interrupted by a READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36

Figure 28: READ with Auto Precharge Interrupted by a WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37

Figure 29: WRITE with Auto Precharge Interrupted by a READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37

Figure 30: WRITE with Auto Precharge Interrupted by a WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38

Figure 31: Example Tem pe r ature Test Point Location, 86-Pin TSOP (Top View) . . . . . . . . . . . . . . . . . . . . . . . . . .45

Figure 32: Example Temperature Test Point Location, 90-Ball FBGA (Top View) . . . . . . . . . . . . . . . . . . . . . . . . .45

Figure 33: Initial ize a nd Load Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51

Figure 34: Power-Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52

Figure 35: Clock Suspend Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53

Figure 36: Auto Refresh Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54

Figure 37: Self Refresh Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55

Figure 38: Single READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56

Figure 39: Single READ – Without Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57

Figure 40: READ – with Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58

Figure 41: Alternating Bank Read Accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59

Figure 42: READ – Full-Page Burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60

Figure 43: READ – DQM Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61

Figure 44: Single WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62

Figure 45: WRITE – Without Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63

Figure 46: WRITE – with Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64

Figure 47: Alternating Write Access es . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65

Figure 48: WRITE – Full-Page Burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66

Figure 49: WRITE – DQM Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67

Figure 50: 86-Pin Plastic TSOP II (400 mil) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68

Figure 51: 90-Ball VFBGA (8mm x 13mm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69

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64Mb: x32 SDRAM

List of Tables

Table 1: Address Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1

Table 2: Key Timing Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1

Table 3: 64Mb (x32) SDRAM Part Number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1

Table 4: Pin/Ball Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9

Table 5: Burst Definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14

Table 6: CAS Latency. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

Table 7: Truth Table 1 – Commands and DQM Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

Table 8: Truth Table 2 – CKE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38

Table 9: Truth Table 3 – Current State Bank n, Command to Bank n. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39

Table 10: Truth Table 4 – Current State Bank n, Command to Bank m . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41

Table 11: Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43

Table 12: Temperature Limits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44

Table 13: Thermal Impedance Simulated Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44

Table 14: DC Electrical Characteristics and Operating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46

Table 15: IDD Specifications and Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46

Table 16: TSOP Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46

Table 17: VFBGA Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46

Table 18: Electrical Characteristics and Recommended AC Operating Conditions . . . . . . . . . . . . . . . . . . . . . . .47

Table 19: AC Functional Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48

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64Mb: x32 SDRAM

Functional Block Diagram

Figure 1: 2 Meg x 32 SDRAM

RAS#

CAS#

CLK

CS#

WE#

CKE

A0–A10,

BA0, BA1

DQM0–

DQM3

256

(x32)

8192

I/O GATING

DQM MASK LOGIC

READ DATA LATCH

WRITE DRIVERS

COLUMN

DECODER

BANK0

MEMORY

ARRAY

(2,048 x 256 x 32)

BANK 0

ROW-

ADDRESS

LATCH

DECODER

2048

SENSE AMPLIFIERS

BANK

CONTROL

LOGIC

DQ0–

DQ31

32 DATA

INPUT

DATA

OUTPUT

BANK 1

BANK 0

BANK 2BANK 3

4 4

REFRESH

COUNTER

MODE REGISTER

CONTROL

LOGIC

COMMAND

DECODE

ROW-

ADDRESS

MUX

ADDRESS

COLUMN-

ADDRESS

COUNTER/

LATCH

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64Mb: x32 SDRAM

Pin/Ball Assignments and Descriptions

Figure 2: 86-Pin TSOP (Top View)

Note: The # symbol indicates signal is active LOW.

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

DQM0

WE#

CAS#

RAS#

CS#

BA0

BA1

A10

DQM2

DQ16

DQ17

DQ18

DQ19

DQ20

DQ21

DQ22

DQ23

DQ15

DQ14

DQ13

DQ12

DQ11

DQ10

DQ9

DQ8

DQM1

CLK

CKE

DQM3

DQ31

DQ30

DQ29

DQ28

DQ27

DQ26

DQ25

DQ24

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64Mb: x32 SDRAM

Pin/Ball Assignments and Descriptions

Figure 3: 90-Ball VFBGA (Top View, Ball Down)

1234 67895

DQ26

DQ28

VSSQ

VDDQ

VSS

CLK

DQM1

VDDQ

VSSQ

DQ11

DQ13

DQ24

VDDQ

DQ27

DQ29

DQ31

DQM3

CKE

DQ8

DQ10

DQ12

VDDQ

DQ15

VSS

VSSQ

DQ25

DQ30

VSS

DQ9

DQ14

VSSQ

VSS

VDD

VDDQ

DQ22

DQ17

A10

BA0

CAS#

VDD

DQ6

DQ1

VDDQ

VDD

DQ21

DQ19

VDDQ

VSSQ

VDD

RAS#

DQM0

VSSQ

VDDQ

DQ4

DQ2

DQ23

VSSQ

DQ20

DQ18

DQ16

DQM2

BA1

CS#

WE#

DQ7

DQ5

DQ3

VSSQ

DQ0

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64Mb: x32 SDRAM

Pin/Ball Assignments and Descriptions

Table 4: Pin/Ball Descriptions

86-Pin TSOP

Numbers 90-Ball VFBGA

Numbers Symbol Type Description

68 J1 CLK Input Clock: CLK is driven by the system clock. All SDRAM input signals

are sampled on the positive edge of CLK. CLK also increments

the internal burst counter and controls the output registers.

67 J2 CKE Input Clock enable: CKE activates (HIGH) and deactivates (LOW) the

CLK signal. Deactivatin g the cloc k provides PRECHARGE power-

down and SELF REFRESH operation (all banks idle), ACTIVE

power-down (row active in any bank), or CLOCK SUSPEND

operation (burst/access in progress). CKE is synchronous exc ept

after the device enters power-down and self refresh modes,

where CKE becomes asynchronous until after exiting the same

mode. The input buffers, including CLK, are disabled during

power-down and self refresh modes, providing low standby

power. CKE may be tied HIGH.

20 J8 CS# Input Chip select: CS# enables (registered LOW) and disables

(registered HIGH) the command decoder. All commands are

masked when CS# is registered HIGH, but READ/WRITE bursts

already in progress will continue and DQM operation will retain

its DQ mask capability while CS# is HIGH. CS# provides for

external bank selection on systems with multiple banks. CS# is

considered part of the command code.

17, 18, 19 K8, K7, J9 WE#,

CAS#,

RAS#

Input Command inputs: WE#, CAS#, and RAS# (along with CS#)

define the command being entered.

16, 71, 28, 59 K9, K1, F8, F2 DQM0–

DQM3 Input Input/output mask: DQM is sampled HIGH and is an input

mask signal for write accesses and an output enable signal for

read accesses. Input data is masked during a WRITE cycle. The

output buffers are placed in a High-Z state (2-clock latency)

during a READ cycle. DQM0 corresponds to DQ0–DQ7; DQM1

corresponds to DQ8–DQ15; DQM2 corresponds to DQ16–DQ23;

and DQM3 corresponds to DQ24–DQ31. DQM0–DQM3 are

considered same state when referenced as DQM.

22, 23 J7, H8 BA0, BA1 Input Bank address input(s): BA0 and BA1 define to which bank the

ACTIVE, READ, WRITE, or PRECHARGE command is being

applied.

25–27, 60–66,

24 G8, G9, F7, F3,

G1, G2, G3, H1,

H2, J3, G7

A0–A10 Input Address inputs: A0–A10 are sampled during the ACTIVE

command (row-address A0–A10) and READ/WRITE command

(column-addr ess A0–A7 with A10 defining auto precharge) to

select one location out of the memory array in the respective

bank. A10 is sampled during a PRECHARGE command to

determine whether all banks are to be precharged (A10 HIGH)

or bank selected by BA0, BA1 (LOW). The address inputs also

provide the op-code during a LOAD MODE REGISTER command.

2, 4, 5, 7 , 8, 1 0,

11, 13, 74, 76,

77, 79, 80, 82,

83, 85, 31, 33,

34, 36, 37, 39,

40, 42, 45, 47,

48, 50, 51, 53,

54, 56

R8, N7, R9, N8,

P9, M8, M7, L8,

L2, M3, M2, P1,

N2, R1, N3, R2,

E8, D7, D8, B9,

C8, A9, C7, A8,

A2, C3, A1, C2,

B1, D2, D3, E2

DQ0–

DQ31 Input/

Output Data I/Os: Data bus.

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64Mb: x32 SDRAM

Functional Description

In general, this 64Mb SDRAM (512K x 32 x 4 banks) is a 4-bank DRAM that operates at

3.3V and includes a synchronous interface (all signals ar e r egistered on the positive edge

of the clock signal, CLK). Each of the 16,777,216-bit banks is organized as 2,048 rows by

256 columns by 32 bits .

Read and write accesses to the SDRAM are burst oriented; accesses start at a selected

location and continue for a programmed number of locations in a programmed

sequence. Accesses beg in with the registration of an ACTIVE command, which is then

followed by a READ or WRITE command. The address bits registered coincident with the

ACTIVE command are used to select the bank and row to be accessed (BA0 and BA1

select the bank, A0–A10 select the row). The address bits (A0–A7) registered coincident

with the READ or WRITE command are used to select the starting column location for

the burst access.

Prior to normal ope ration, the SDR AM must be initialized . The fo ll owing sections

provide detailed information covering device initialization, register definition,

command descriptions, and device operation.

Initialization

SDRAMs must be powered up and initialized in a predefined manner. Operational

procedures other than those specified may r esult in undefined operation. After power is

applied to VDD and VDDQ (simultaneously) and the clock is stable (stable clock is

defined as a signal cycling within timing constraints specified for the clock pin), the

SDRAM requires a 100µs delay prior to issuing any command other than a COMMAND

INHIBIT or NOP. St arting at some point during this 100µs period, and continuing at least

through the end of this pe riod, C O MMAND INHIBIT or NOP commands must be

applied.

When the 100µs delay has been satisfied with at le ast one COMMAND INHIBIT or NOP

command having been applied, a PRECHARGE command should be applied. All banks

must then be pr echarged, thereby placing the device in the all banks idle state.

3, 9, 35, 4 1, 49,

55, 75, 81 B2, B7, C9, D9,

E1, L1, M9, N9,

P2, P7

VDDQ Supply DQ power supply: Isolated on the die for improved noise

immunity.

6, 12, 32, 38,

46, 52, 78, 84 B8, B3, C1, D1,

E9, L9, M1, N1,

P3, P8

VSSQ Supply DQ ground: Provide isolated ground to DQs for impr oved noise

immunity.

1, 15, 29, 43 A7, F9, L7, R7 VDD Supply Power supply: +3.3V ±0.3V. (See note 27 on page 50.)

44, 58, 72, 86 A3, F1, L3, R3 VSS Supply Ground.

14, 21, 30, 57,

69, 70, 73 E3, E7, H3, H7,

K2, K3, H9 NC – No connect: These pins/balls should be left unconnected. Pin 70

is reserved for SSTL reference voltage supply. H7 is a no connect

for this part but may be used as A12 in future designs. H9 is used

as A11 in 128Mb, 256Mb, and 512Mb x32 FBGAs. PCB designs

that accommodate dif ferent densities must account for A11 with

stuffing options .

Table 4: Pin/Ball Descriptions (continued)

86-Pin TSOP

Numbers 90-Ball VFBGA

Numbers Symbol Type Description

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64Mb: x32 SDRAM

Functional Description

When in the idle state, at least two AUTO REFRESH cycles must be performed. After the

AUTO REFRESH cycles are complete, the SDRAM is ready for mode register program-

ming. Because the mode register will pow er up in an unknow n state, it must be loaded

prior to applying any operational command. If desired, the two AUTO REFRESH

commands can be issued after the LOAD MODE REGISTER command.

The recommended power-up sequence for SDRAMs:

1. Simultaneously apply power to VDD and VDDQ.

2. Assert and hold CKE at a LVTTL logic LOW since all inputs and outputs are LVTTL-

compatible.

3. Provide stable CLOCK signal. Stable clock is defined as a signal cycling within timing

constraints speci fie d for th e c loc k pin.

4. Wa it at le as t 1 00µs prior to issuing any command other than a COMMAND INHIBIT

or NOP.

5. Starting at some point during this 100µs period, bring CKE HIGH. Continuing at least

through the end of this period, 1 or more COMMAND INHIBIT or NOP commands

must be applied.

6. Perfor m a PRECHARGE ALL command.

7. Wait at least tRP time; during this time,0 NOPs or DESELECT commands must be

given. All banks will complete their precharge, thereby placing the device in the all

banks idle state.

8. Issue an AUTO REFRESH command.

9. Wait at least tRFC time, during which only NOPs or COMMAND INHIBIT commands

are allowed.

10. Issue an AUTO REFRESH command.

11. Wait at least tRFC time, during which only NOPs or COMMAND INHIBIT commands

are allowed.

12. The SDRAM is no w ready for mode register programming. Because the mode register

will power up in an unknown state, it should be loaded with desired bit values prior to

applying any operational command. Using the LMR command, program the mode

with BA1 = 0, BA0 = 0 and retains the stored information until it is programmed again

or the device loses power. N ot programming the mode register upon initi alization will

result in default settings which may not be desired. Outputs are guaranteed High-Z

after the LMR command is issued. Outputs should be High-Z already before the LMR

command is issued.

13. Wait at least tMRD time, during which only NOP or DESELECT commands are

allowed.

At this point the DRAM is ready for any valid command.

Note: If desired, more than two AUTO REFRESH commands can be issue d in th e se que n c e.

After steps 9 and 10 are complete, repeat them until the desired number of AUTO

REFRESH + tRFC loops is achieved.

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64Mb: x32 SDRAM

Functional Description

Mode Register

The mode register is used to define the specific mode of operation of the SDRAM. This

definition includes the selection of a burst length, a burst type, a CL, an operating mode

and a write burst mode, as shown in Figure 4 on page 13. The mode register is

programmed via the LOAD MODE REGISTER command and will retain the stored infor-

mation until it is progra mmed again or the device loses power.

Mode r egister bits M0–M2 specify the burst length, M3 specifies the type of burst

(sequential or int erl eave d ), M4–M6 specify the CL, M7, and M8 specify the operating

mode, M9 specifies the write burst mode, and M10 is reserved for future use.

The mode regi ster must be loaded when all banks are idle, and the controller must wait

the specified time before initiating the subsequent operation. Violating either of these

requirements will result in unspecified operation.

Burst Length

Read and write accesses to the SDRAM are burst oriented, with the burst le ng th being

programm able, as shown in Figure 4. The burst length det ermines the maximum

number of column locations that can be accessed for a given READ or WRITE command.

Burst lengths of 1, 2, 4, or 8 locations are available for both the sequential and the inter-

leaved burst types, and a full-page burst is avai lable for the sequential type. The full-

page burst is used in conjunction with the BURST TERMINATE command to generate

arbitrary burst lengths.

Reserved states should not be used, as unknown operation or incompatibility with

future versions may result.

When a READ or WRITE comm and is issu ed , a block of col u m n s eq ual to the bu rst

length is effectivel y selected. All accesses for that burst take place within this block,

meaning that the burst will wrap within the block if a boundary is reached. The block is

uniquely selected by A1–A7 when BL = 2; by A2–A7 when BL = 4; and by A3–A 7 when the

BL = 8. The remaining (least significant) address bit(s) is (are) used to select the starting

location within the block. Full-page bursts wrap within the page if the boundary is

reached.

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64Mb: x32 SDRAM

Functional Description

Figure 4: Mode Register Definition

Burst Type

Accesse s within a given b urst may be progr ammed to be eithe r sequential or interleaved;

this is referred to as the burst type and is selected via bit M3.

The ordering of accesses within a burst is determined b y the burst lengt h, the burst t ype ,

and the starting column address, as shown in Table 5 on page 14.

M3 = 0

Reserved

Full Page

M3 = 1

Reserved

Operating Mode

Standard Operation

All other states reserved

–

Defined

–

Burst Type

Sequential

Interleaved

CAS Latency

Reserved

Burst Length

Burst LengthCAS Latency BT

A9 A7 A6 A5 A4 A3

A8 A2 A1 A0

Mode Register (Mx)

Address Bus

976543

8210

M6–M0

M8 M7

Op Mode

A10

Reserved WB

Write Burst Mode

Programmed Burst Length

Single Location Access

Program

A10, BA0, and BA1 = “0”

to ensure compatibility

with future devices.

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64Mb: x32 SDRAM

Functional Description

Notes: 1. For BL = 2, A1–A7 select the block-of-two burst; A0 selects the starting column within the

block.

2. For BL = 4, A2–A7 select the block-of-four burst; A0–A1 select the starting column within

the block.

3. For BL = 8, A3–A7 select the block-of-eight burst; A0–A2 select the starting column within

the block.

4. For a full-page burst, the full row is selected and A0–A7 select the starting column.

5. Whenever a boundary of the block is reached within a given sequence above, the following

access wraps within the block.

6. For BL = 1, A0–A7 select the unique column to be accessed, and mode register bit M3 is

ignored.

CAS Latency

The CAS latency is the delay, in clock cycles, between the registration of a READ

command and the availability of the fi rs t piece of output data. The latency can be set to

1, 2, or 3 clocks.

If a READ command is registered at clock edge n, and the late ncy is m clocks, the data

will be available by clock edge n + m. The DQs will start driving as a result of the clock

edge one cycle earlier (n + m - 1), and provided that the relevant access times are met,

the data will be valid by clock edge n + m. For example, assuming that the clock cycle

time is such that all relevant access times ar e met, if a READ command is r egister ed at T0

and the latency is programmed to 2 clocks, the DQs will start driving after T1 and the

data will be valid b y T2, as sho wn in F igure5 on page 15. Table 6 on page 15 indicates the

operating frequencies at which each CAS latency setting can be used.

Re served states should not be used because unknown operation or incom patibility with

future versions may result.

Table 5: Burst Definition

Burst

Length Starting Column Address

Order of Accesses Within a Burst

Type = Sequential Type = Interleaved

2A0

00-1 0-1

11-0 1-0

4A1 A0

0 0 0-1-2-3 0-1-2-3

0 1 1-2-3-0 1-0-3-2

1 0 2-3-0-1 2-3-0-1

1 1 3-0-1-2 3-2-1-0

8A2 A1 A0

0 0 0 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7

0 0 1 1-2-3-4-5-6-7-0 1-0-3-2-5-4-7-6

0 1 0 2-3-4-5-6-7-0-1 2-3-0-1-6-7-4-5

0 1 1 3-4-5-6-7-0-1-2 3-2-1-0-7-6-5-4

1 0 0 4-5-6-7-0-1-2-3 4-5-6-7-0-1-2-3

1 0 1 5-6-7-0-1-2-3-4 5-4-7-6-1-0-3-2

1 1 0 6-7-0-1-2-3-4-5 6-7-4-5-2-3-0-1

1 1 1 7-0-1-2-3-4-5-6 7-6-5-4-3-2-1-0

Full page

(256) n = A0–A10

(location 0–256) Cn, Cn + 1, Cn + 2,

Cn + 3, Cn + 4...

…Cn - 1, Cn…

Not supported

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64Mb: x32 SDRAM

Functional Description

Figure 5: CAS Laten cy

Table 6: CAS Latency

Speed

Allowable Operating Frequency (MHz)

CL = 1 CL = 2 CL = 3

-5 – – ≤ 200

-55 – – ≤ 183

-6 ≤ 50 ≤ 10 0 ≤ 166

-7 ≤ 50 ≤ 10 0 ≤ 143

CLK

T2T1 T3T0

CL = 3

OUT

tOH

COMMAND NOPREAD

tAC

NOP

DON’T CARE

UNDEFINED

CLK

T2T1T0

CL = 1

OUT

tOH

COMMAND NOPREAD

tAC

CLK

T2T1 T3T0

CL = 2

OUT

tOH

COMMAND NOPREAD

tAC

NOP

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64Mb: x32 SDRAM

Commands

Operating Mode

The normal operating mode is selected by setting M7 and M8 to zero; other combina-

tions of values for M7 and M8 are reser ved for future use and/or test modes. The

programmed burst length applies to both read and write bursts.

Test modes and reserved states should not be used because unknow n operation or

incompatibility with future versions may result.

Write Burst Mode

When M9 = 0, the burst length programmed via M0–M 2 applies to both read and write

bursts; when M9 = 1, the programmed burst length applies to read bursts, but write

accesses are single-location (nonburst) accesses.

Commands Truth Table 1 pro v ides a quick r eference of available commands. This is followed by a

written desc ription of each co mm and . Three additional Truth Tables appear following

“Operations” on page 19; these tables provide current state/next state information.

Notes: 1. A0–A10 provide row address, BA0 and BA1 determine which bank is made active.

2. A0–A7 provide column address; A10 HIGH enables the auto precharge feature (nonpersis-

tent), while A10 LOW disables the auto precharge feature; BA0 and BA1 determine which

bank is being read from or written to.

3. A10 LOW: BA0 and BA1 determine the bank being precharged. A10 HIGH: all banks pre-

charged and BA0 and BA1 are “Don’t Care.”

4. This comm and is AUTO REFRESH if CKE is HIGH; SELF REFRESH if CKE is LOW.

5. Internal refresh counter controls row addressing; all inputs and I/Os are “Don’t Care” except

for CKE.

6. A0–A10 define the op-code written to the mode register.

7. Activates or dea ctivates the DQs during WRITEs (zero-clock delay) and READs (two-clock

delay). DQM0 controls DQ0–DQ7; DQM1 controls DQ8–DQ15; DQM2 controls DQ16–DQ23;

and DQM3 controls DQ24–DQ31.

Table 7: Truth Table 1 – Commands and DQM Operation

CKE is HIGH for all commands shown except SELF REFRESH

Name (Function) CS# RAS# CAS# WE# DQM ADDR DQs Notes

COMMAND INHIBIT (NOP) HXXXX X X

NO OPERATION (NOP) LHHHX X X

ACTIVE (Select bank and act iva t e ro w) LLHHXBank/rowX 1

READ (Select bank and column, and start READ

burst) LHLHL/H

7Bank/col X 2

WRITE (Select bank and column, and start WRITE

burst) L H L L L/H7Bank/col Valid 2

BURST TERMINATE LHHLX XActive

PRECHARGE (Deactivate row in bank or banks) LLHLXCode X 3

AUTO REFRESH or SELF REFRESH (Enter self refresh

mode) LLLHX X X4, 5

LOAD MODE REGISTER LLLLXOp-codeX 6

WRITE ENABLE/OUTPUT ENABLE ––––L –Active7

WRITE INHIBIT/OUTPUT HIGH-Z ––––H –High-Z7

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64Mb: x32 SDRAM

Commands

COMMAND INHIBIT

The COMMAND INHIBIT function pr ev ents new commands from being executed b y the

SDRAM, regardless of whether the CLK signal is enabled. The SDRAM is effectiv ely dese-

lected. Operations already in progress are not affected.

NO OPERATION (NOP)

The NO OPERATION (NOP) command is used to perform an NOP to an SDRAM that is

selected (CS# is L O W). This pr events unwanted commands fr om being r eg ister ed during

idle or wait states. Operations already in progress are not affected.

LOAD MODE REGISTER

The mode register is loaded via inputs A0–A10. See “Mode Register” on page 12. The

LOAD MODE REGISTER command can only be issued when all banks are idle, and a

subsequent executable command cannot be issued until tMRD is met.

ACTIVE

The ACTIVE command is used to open (or activate) a row in a particular bank for a

subsequent access. The value on the BA0, BA1 inputs selects the bank, and the addr ess

provided on inputs A0–A10 s elec ts the row. This row rema ins acti ve (or ope n) for

accesses until a PRECHARGE command is issued to that bank. A PRECHARGE

command must be issued before opening a different row in the same bank.

READ

The READ command is used to initiate a burst r ead access to an activ e row. The value on

the BA0 and BA1 (B1) inputs selects the bank, and the address provided on inputs A0–A7

selects the starting column location. The va lue on input A10 determines whether auto

precharge is used. If auto precharge is selected, the row being accessed will be

precharged at the end of the read burst; if auto precharge is not selected, the row will

remai n open for subsequent ac cesses . Read data appears on the DQs subject to the logic

level on the DQM inputs two clocks earlier . If a given DQMx signal was regis ter ed HIGH,

the corr esponding DQs will be H igh-Z two clocks later; if the DQMx signal was registered

LOW, the co rrespondin g D Q s w il l provide valid data. DQM0 corresponds to DQ 0–D Q 7,

DQM1 corresponds to DQ8–DQ15, DQM2 corresponds to DQ16–DQ23, and DQM3

corresponds to DQ24–DQ31.

WRITE

The WRITE command is used to initiate a burst write access to an active row. The value

on the BA0 and BA1 inputs selects the bank, and the address provided on inputs A0–A7

selects the starting column location. The value on input A10 determines whether or not

auto precharge is used. If auto precharge is selected, the row being accessed will be

precharged at the end of the writ e burs t; if auto precharge is not selec te d , th e row will

remai n open for subsequent accesses. Input data appearing on the DQs is written to the

memor y array subject to the DQM input logic le ve l appe aring coincide nt with the data.

If a given DQM signal is registered LOW, the corresponding data will be written to

memory; if the DQM signal is registered HIGH, the corresponding data inputs will be

ignored, and a write will not be executed to that byte/column location.

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64Mb: x32 SDRAM

Commands

PRECHARGE

The PRECHARGE command is used to deactivate the open row in a particular bank or

the open row in all banks. The bank(s) will be available for a subsequent row access a

specifie d time (tRP) after the PRECHARGE command is issued. Input A10 determines

whether one or all banks ar e to be precharged, and in the case where only one bank is to

be precharged, inputs BA0 and BA1 select the bank. Otherwise BA0 and BA1 are treated

as “Don’t Care.” After a bank has been precharged, it is in the idle state and must be acti-

vated prior to any READ or WRITE commands being issued to that bank.

Auto Precharge

Auto precharge is a feature that performs the same individua l-b ank precharge function

described above, without r e quiring an explic it command. This is accomplished by using

A10 to enable auto precharge in conjunction with a specific READ or WRITE command.

A prechar ge of the bank/row that is addressed with the READ or WRITE command is

automatically performed upon completion of the READ or WRITE burst, except in the

full-page burst mode, where AUTO PRECHARGE does not apply. Auto precharge is

nonpersistent in that it is either enabled or disabled for each READ or WRITE command.

Auto precharge ensures that the precharge is initiated at the earliest valid stage within a

burst. The user must not issue another command to the same bank until the precharge

time (tRP) is completed. This is determined as if an explicit PRECHARGE command was

issued at the earliest possible time, as described for each burst type in “O perations” on

page 19.

BURST TERMINATE

The BURST TERMINATE command is used to truncate either fixed-length or full-page

bursts. The most recently re gistered READ or WRITE command prior to the BURST

TERMINATE command will be truncated, as shown in “Operations” on page 19. The

BURST TERMI NATE command does not prec harge the row; the row will remain open

until a PRECHARGE command is issued.

AUTO REFRESH

AUTO REFRESH is used during normal operation of the SDRAM and is analogous to

CAS#-BEFORE-RAS# (CBR) refresh in conv entional DRAMs. This command is nonper -

sistent, so it must be issued each time a re fresh is required.

The addressing is generated by the internal refresh controller. This makes the address

bits “Don’t Care” during an AUTO REFRESH command. Regardless of device width, the

64Mb SDRAM requires 4,096 AUTO REFRESH cycles every 64ms (commercial and indus-

trial) or 16ms (automotive). Providing a distributed AUTO REFRESH command every

15.625µs (commercial and industrial) or 3.906µs (automotive) will meet the refresh

require m ent and ensure that each row is refreshed. Alternatively, 4,096 AUTO REFRESH

commands can be issued in a burst at the minimum cycle rate (tRFC), once every 64ms

(commercial and industrial) or 16ms (automotive).

SELF REFRESH

The SELF REFRESH co mm and can be use d to retain data in the SDRAM, even if the rest

of the system is powered down. When in the self r efresh mode, the SDRAM retains data

without external clo ck ing. The SELF REF RESH com m and is initiated like an AUTO

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64Mb: x32 SDRAM

Commands

REFRESH command except CKE is disabled (L O W). When the SELF REFRESH command

is registered, all the inputs to the SDRAM become “Don’t Care” with the exception of

CKE, which must remain LOW.

After self refr esh mode is engaged, the SDRAM provides its own internal clocking,

causing it to perform its own AUTO REFRESH cycles. The SDRAM must remain in self

refresh mode for a minimum period equal to tRAS and may remain in self refresh mode

for an indefinite period beyond that.

The procedur e for exit ing self r efresh requir e s a sequen ce of commands. First, CLK must

be stable (stable clock is defined as a signal cycling within timing constraints specified

for the clock pin) prior to CKE going back HIGH. After CKE is HIGH, the SD RA M mus t

have NOP commands issued (a minimum of two clocks ) for tXSR because time is

required for the completion of any internal refresh in progress.

Upon exi ting self refresh mode, AUTO REFRESH commands mu st be is sue d every

15.625µs or less as both SELF REFRESH and A UTO REFRESH utilize the row refresh

counter.

Self refresh is not supported on automotive temperature devices.

Operations

Bank/Row Activation

Before any READ or WRITE commands can be issued to a bank within the SDRAM, a row

in that bank must be “opened.” This is accomplished via the ACTIVE command, which

selects both the bank and the row to be activated. See Fi gure 6 on page 20.

After opening a ro w (issuing an A CTIVE command), a RE AD or WRITE command may be

issued to that row, subject to the tRCD specifi cation. tRCD (MIN) should be divided by

the clock period and rounded up to the next whole number to determine the earliest

clock edge after the ACTIVE command on which a READ or WRITE command can be

issued. For example, a tRCD specification of 20ns with a 125 MHz clock (8ns period)

results in 2.5 clocks, rounded to 3. This is reflected in Figur e7 on page 20, which covers

any case where 2 < tRCD (MIN)/tCK - 3 (the same procedure is used to convert other

specificati o n lim i ts from tim e units to clock cycles).

A subsequent ACTIVE command to a differ ent row in the same bank can only be issued

after the previous active row has been “closed” (precharged). The minimum time

interval between successive ACTIVE commands to the same bank is defined by tRC.

A subsequent ACTIVE command to another bank can be issued while the first bank is

being accessed, which resul ts in a r eduction of total r o w-access o verhead. The minimum

time interval between successive ACTIVE commands to different banks is defined by

tRRD.

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64Mb: x32 SDRAM

Commands

Figure 6: Activating a Specific Row in a Specific Bank

Figure 7: Example: Meeting tRCD (MIN) when 2 < tRCD (MIN)/tCK - 3

Notes: 1. tRCD (MIN) = 20ns, tCK = 8ns.

2. tRCD (MIN) x tCK where x = number of clocks for equation to be true.

READs

READ bursts are initiated with a READ command, as shown in Figure8 on page 21.

The starting column and bank addresses are pr ovided with the READ command, and

auto precharg e either i s enabled or disabled for that burst access. If auto precharge is

enabled, the row being accessed is precharged at the completion of the burst. For the

generic READ commands used in the following illustrations, auto precharge is disabled.

During READ bursts, the valid data-out element from the starting column address will

be available following the CAS latency after the READ command. Each subsequent data-

out element will be valid by the next positive clock edge. Figure 9 on page 22 shows

general timing for each possible CAS latency setting.

CS#

WE#

CAS#

RAS#

CKE

CLK

A0–A10 ROW

ADDRESS

DON´T CARE

HIGH

BA0, BA1 BANK

ADDRESS

CLK

T2T1 T3T0

COMMAND NOPACTIVE READ or

WRITE

NOP

RCD (MIN)

tRCD (MIN) +0.5 tCK

tCK tCK tCK

DON’T CARE

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64Mb: x32 SDRAM

Commands

Upon completion of a burst, assuming no other commands have been initiated, the DQs

will go High-Z . A full-page burst will continue until terminated. (At the end of the page , it

will wrap to column 0 and continue.)

Data from any READ burst may be truncated with a subsequent READ com ma nd, and

data from a fixed-length READ burst may be immediately followed by data from a READ

command. In either case, a continuous flow of data can be maintained. The first data

element from the new burst either follows the last element of a completed burst or the

last desired data element of a longer burst that is being truncated. The new READ

command should be issued x cy cles before the clock edge at which the last desired data

element is valid, where x equals CL - 1. This is shown in Figure10 on page 23 for CL = 1,

CL = 2, and CL = 3; data element n + 3 is either the last of a burst of four or the last desired

of a longer burst. This 64Mb SDRAM uses a pipelined architecture and therefore does

not requir e the 2n rule associated with a prefetch architecture . A READ command can be

initiated on any clock cycle following a previous READ command. Full-speed random

read accesses can be performed to the same bank, as shown in Figur e11 on page 24, or

each subsequent READ may be performed to a different bank.

Figure 8: READ Command

DON’T CARE

CS#

WE#

CAS#

RAS#

CKE

CLK

COLUMN

ADDRESS

A0–A7

A10

BA0, 1

HIGH

ENABLE AUTO PRECHARGE

DISABLE AUTO PRECHARGE

BANK

ADDRESS

A8, A9

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64Mb: x32 SDRAM

Commands

Figure 9: CAS Laten cy

CLK

T2T1 T3T0

CL = 3

OUT

tOH

COMMAND NOPREAD

tAC

NOP

DON’T CARE

UNDEFINED

CLK

T2T1T0

CL = 1

OUT

tOH

COMMAND NOPREAD

tAC

CLK

T2T1 T3T0

CL = 2

OUT

tOH

COMMAND NOPREAD

tAC

NOP

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64Mb: x32 SDRAM

Commands

Figure 10: Consecutive READ Bursts

Note: Each READ command may be to any bank. DQM is LOW.

CLK

DQ D

OUT

T2 T1 T4 T3 T5 T0

COMMAND

ADDRESS

READ NOP NOP NOP

BANK,

COL n

NOP

BANK,

COL b

OUT

n + 1 D

OUT

n + 2 D

OUT

n + 3 D

OUT

READ

X = 0 cycles

CL = 1

CLK

DQ D

OUT

T2 T1 T4 T3 T6 T5 T0

COMMAND

ADDRESS

READ NOP NOP NOP NOP

BANK,

COL n

NOP

BANK,

COL b

OUT

n + 1 D

OUT

n + 2 D

OUT

n + 3 D

OUT

READ

X = 1 cycle

CL = 2

CLK

DQ D

OUT

T2 T1 T4 T3 T6 T5 T0

COMMAND

ADDRESS

READ NOP NOP NOP NOP

BANK,

COL n

NOP

BANK,

COL b

OUT

n + 1 D

OUT

n + 2 D

OUT

n + 3 D

OUT

READ NOP

X = 2 cycles

CL = 3 DON’T CARE

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64Mb: x32 SDRAM

Commands

Figure 11: Random READ Accesses

Note: Each READ command may be to any bank. DQM is LOW.

Data from any READ burst may be truncated with a subsequent WRITE command, and

data from a fixed-length READ burs t may be immediately followed by data from a

WRITE command (subject to bus turnaround limitations). Th e WRI TE burst may be

initiated on the clock edge immediately following the last (or last desired) data element

from the READ burst, provided that I/O contention can be avoided. In a given system

CLK

T2T1 T4T3 T6T5T0

COMMAND

ADDRESS

READ NOP NOP

BANK,

COL n

DON’T CARE

OUT

READ READ READ NOP

BANK,

COL aBANK,

COL xBANK,

COL m

CLK

DQ D

OUT

T2T1 T4T3 T5T0

COMMAND

ADDRESS

READ NOP

BANK,

COL n

OUT

READ READ READ NOP

BANK,

COL aBANK,

COL xBANK,

COL m

CLK

DQ D

OUT

T2T1 T4T3T0

COMMAND

ADDRESS

READ NOP

BANK,

COL n

OUT

READ READ READ

BANK,

COL aBANK,

COL xBANK,

COL m

CL = 1

CL = 2

CL = 3

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64Mb: x32 SDRAM

Commands

design, ther e may be a possibility that the device driving the input data will go Low-Z

before the SDRAM DQs go High-Z. In this case, at least a single-cycle delay should occur

between the last read data and the WRITE command.

The DQM input is used to avoid I/O contention, as shown in Figure12 and in Figure13

on page 26. The DQM signal must be asserted (HIGH) at least two clocks prior to the

WRITE command (DQM latency is two clocks for output buffers) to suppress data-out

from the READ. After the WRITE command is registered, the DQs will go High-Z (or

remai n High-Z), regardless of the state of the DQM signal; provided the DQM was active

on the clock just prior to the WRITE command that truncated the READ command. If

not, the second WRITE will be an invalid WRITE. For example, if DQM was LOW during

T4 in Figure 13, then the WRITEs at T5 and T7 would be valid, while the WRITE at T6

would be invalid.

The DQM signal must be de-asserted prior to the WRITE command (DQM latency is

zero clocks for input buffers) to ensure that the written data is not masked. Figure 12

shows the case where the clock frequency allows for bus contention to be avoided

without adding an NOP cycle, and Figure13 sho ws the case where the additional NOP is

needed.

Figure 12: READ-to-WRITE

Note: CL = 3 is used for illustration. The READ command may be to any bank, and the WRITE

command may be to any bank.

DON’T CARE

READ NOP NOP WRITE

NOP

CLK

T2T1 T4T3T0

DQM

DQ DOUT n

COMMAND

DIN b

ADDRESS BANK,

COL nBANK,

COL b

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64Mb: x32 SDRAM

Commands

Figure 13: READ-to-WRITE With Extra Clock Cycle

Note: CL = 3 is used for illustration. The READ command may be to any bank, and the WRITE

command may be to any bank.

A fixed-length READ burst may be followed by, or truncated with, a PRECHARGE

command to the same bank (provided that auto precharge was not activated), and a full-

page burst may be truncated with a PRECHARGE command to the same bank. The

PRECHAR GE command should be issued x cycles be for e the c lock edge at which the l ast

desired data element is valid, where x equals CL - 1. This is shown in Figure14 on

page 27 for each possible CAS latency; data element n + 3 is either the last of a burst of

four or the last desired of a longer burst. Following the PRECHARGE command, a subse-

quent command to the same bank cannot be issued until tRP is met. No te that part of

the row precharge time is hidden during the access of the last data element(s).

In the case of a fixed-length burst being executed to completion, a PRECHARG E

command issued at the optimum time (as desc ribed abov e) provi des the same operation

that would result from the same fixed-length burst with auto precharge. The disadvan-

tage of the PRECHARGE command is that it requires that the command and address

buses be available at the appropriate time to issue the command; the advantage of the

PRECHARG E command is that it can be used to truncate fixed-leng th or full-page bursts .

Full-page READ bursts can be truncated with the BURST TERMINATE command, and

fixed-length READ bursts may be truncated with a BURST TERMINATE command,

provided that auto precharge was not activated. The BURST TERMINATE command

should be issued x cycles before the clock edge at which the last desired data element is

valid, where x equals CL - 1. This is shown in Figure 15 on page 28 for each possible CAS

latency; data element n + 3 is the last desired data element of a longer burst.

DON’T CARE

READ NOP NOPNOP NOP

DQM

CLK

DQ DOUT n

T2T1 T4T3T0

COMMAND

ADDRESS BANK,

COL n

WRITE

DIN b

BANK,

COL b

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64Mb: x32 SDRAM

Commands

Figure 14: READ-to-PRECHARGE

Note: DQM is LOW.

CLK

DQ D

OUT

T2T1 T4T3 T6T5T0

COMMAND

ADDRESS

READ NOP NOP NOP NOPNOP

OUT

n + 1 D

OUT

n + 2 D

OUT

n + 3

PRECHARGE ACTIVE

tRP

CLK

DQ D

OUT

T2T1 T4T3 T6T5T0

COMMAND

ADDRESS

READ NOP NOP NOP NOPNOP

OUT

n + 1 D

OUT

n + 2 D

OUT

n + 3

PRECHARGE ACTIVE

tRP

CLK

DQ D

OUT

T2T1 T4T3 T6T5T0

COMMAND

ADDRESS

READ NOP NOP NOP NOP

BANK a,

COL n

NOP

OUT

n + 1 D

OUT

n + 2 D

OUT

n + 3

PRECHARGE ACTIVE

tRP

BANK a,

ROW

BANK

(a or all)

DON’T CARE

X = 0 cycles

CL = 1

X = 1 cycle

CL = 2

CL = 3

BANK a,

COL

BANK a,

ROW

BANK

(a or all)

BANK a,

COL

BANK a,

ROW

BANK

(a or all)

X = 2 cycles

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64Mb: x32 SDRAM

Commands

Figure 15: Terminating a READ Burst

Note: DQM is LOW.

DON’T CARE

CLK

DQ D

OUT

T2T1 T4T3 T6T5T0

COMMAND

ADDRESS

READ NOP NOP NOP NOP

BANK,

COL n

NOP

OUT

n + 1 D

OUT

n + 2 D

OUT

n + 3

BURST

TERMINATE NOP

CLK

DQ D

OUT

T2T1 T4T3 T6T5T0

COMMAND

ADDRESS

READ NOP NOP NOP

BANK,

COL n

NOP

OUT

n + 1 D

OUT

n + 2 D

OUT

n + 3

BURST

TERMINATE NOP

CLK

DQ D

OUT

T2T1 T4T3 T6T5T0

COMMAND

ADDRESS

READ NOP NOP NOP

BANK,

COL n

NOP

OUT

n + 1 D

OUT

n + 2 D

OUT

n + 3

BURST

TERMINATE NOP

X = 0 cycles

CL = 1

X = 1 cycle

CL = 2

CL = 3

X = 2 cycles

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64Mb: x32 SDRAM

Commands

WRITEs

WRITE bursts are initiated with a WRITE command, as shown in Figure 16.

The starting column and bank addresses are pro vided with the WRITE command, and

auto prec harge i s either enabled or disabled for that acc ess . If auto pr e charge is enab led,

the row being accessed is precharged at the completion of the burst. For the generic

WRITE commands us ed in the fol lowing illustrations, auto precharge is disabled.

During WRITE bursts, the first valid data-in element will be registered coincident with

the WRITE command. Subsequent data elements will be registered on each successive

positive clock edge. Upon completion of a fixed-length burst, ass uming no other

commands have been initiated, the DQs will remain High-Z and any additional input

data will be ignored (see Figure17 on page 30). A full-page burst will continue until

terminated (at the end of the page, it will wrap to column 0 and continue).

Data for any WRITE burst may be truncated with a subsequent WRITE command, and

data for a fixed-length WRI TE burst may be immediately followed by data for a WRITE

command. The new WRITE command can b e issued on any c lock follo wi ng the pr evious

WRITE command, and the data provided coincident with the new command applies to

the new command. An example is shown in Figure18 on page 30. Data n + 1 is either the

last of a burst of two or the last desired of a longer burst. This 64Mb SDRAM uses a pipe-

lined architecture and therefore does not require the 2n rule associated with a prefetch

architec tur e. A WRITE com mand can be initiated on any clock cycle fol lo wing a pr evious

WRITE command. Full-speed random write accesses within a page can be performed to

the same bank, as shown in Figure19 on page 31, or each subsequent WRITE may be

performed to a different bank.

Figure 16: WRITE Command

CS#

WE#

CAS#

RAS#

CKE

CLK

COLUMN

ADDRESS

DON’T CARE

HIGH

ENABLE AUTO PRECHARGE

DISABLE AUTO PRECHARGE

BANK

ADDRESS

A0–A7

A10

BA0, 1

A8, A9

VALID ADDRESS

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64Mb: x32 SDRAM

Commands

Figure 17: WRITE Burst

Figure 18: WRITE-to-WRITE

Note: DQM is LOW. Each WRITE command may be to any bank.

Data for any WRITE burst may be truncated with a subsequent READ command, and

data for a fixed -length WRITE burst m ay be imme diately fol lowed b y a REA D command.

Once the READ command is registered, the data inputs will be ignored, and writes will

not be executed. An example is shown in Figure 20 on page 31. Data n + 1 is either the

last of a burst of two or the last desired of a longer burst.

Data for a fixed-length WRITE burst may be followed by, or truncated with, a

PRECHARGE command to the same bank (provided that auto pr echarge was not acti-

vated), and a full-page WRITE burst may be truncated with a PRECHARGE command to

the same bank. The PRECHARGE command should be issued tWR after the clock edge at

which the last desired input data element is registered. The “two-clock” write-back

requires at least one clock plus time, regardless of fr e quency, in auto precharge mode . I n

addition, when truncating a WRITE burst, the DQM signal must be used to mask input

data for the clock edge prior to, and the clock edge coincident with, the PRECHARGE

command. An example is show n in Figure 21 on page 32. Data n + 1 is either the last of a

burst of two or the last desired of a longer burst. Follo wing the PRECHAR GE command, a

subsequent command to the same bank cannot be issued until tRP is met. The

precharge will actually begin coincident with the clock-edge (T2 in Figure 21) on a “one-

clock” tWR and sometime between the first and second clock on a “two-clock” tWR

(between T2 and T3 in Figure 21).

CLK

T2T1 T3T0

COMMAND

ADDRESS

NOP NOP

DON’T CARE

WRITE

n + 1

NOP

BANK,

COL n

CLK

T2T1T0

COMMAND

ADDRESS

NOPWRITE WRITE

BANK,

COL nBANK,

COL b

DIN

nDIN

n + 1 DIN

DON’T CARE

TRANSITIONING DATA

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64Mb: x32 SDRAM

Commands

In the case of a fixed-length burst being executed to completion, a PRECHARG E

command issued at the optimum time (as desc ribed abov e) provi des the same operation

that would result from the same fixed-length burst with auto precharge. The disadvan-

tage of the PRECHARGE command is that it requires that the command and address

buses be available at the appropriate time to issue the command; the advantage of the

PRECHAR GE command is that it can be used to truncate fixed-length or full-page bursts.

Figure 19: Random WRITE Cycles

Note: Each WRITE command may be to any bank. DQM is LOW.

Figure 20: WRITE-to-READ

DON’T CARE

CLK

DQ DIN

T2T1 T3T0

COMMAND

ADDRESS

WRITE

BANK,

COL n

DIN

aDIN

xDIN

WRITE WRITE WRITE

BANK,

COL aBANK,

COL xBANK,

COL m

DON’T CARE

CLK

T2T1 T3T0

COMMAND

ADDRESS

NOPWRITE

BANK,

COL n

n + 1 D

OUT

READ NOP NOP

BANK,

COL b

NOP

OUT

b + 1

T4 T5

TRANSITIONING DATA

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64Mb: x32 SDRAM

Commands

Figure 21: WRITE-to-PRECHARGE

Note: DQM could remain LOW in this example if the WRITE burst is a fixed length of two.

Fixed-length or full-page WRITE bursts can be truncated with the BURST TERMINATE

command. When truncating a WRITE burst, the inpu t data applied coincident with the

BURST TERMINATE command will be ignored. The last data written (provided that

DQM is LOW at that time) will be the input data applied one clock previous to the

BURST TERMINATE command. This is shown in F igure 22 on page 33, where data n is

the last desired data element of a longer burst.

PRECHARGE

The PRECHAR GE command (Figur e23 on page 34) is used to deactivate the open row in

a particular bank or the open row in all banks. The bank(s) will be available for a subse-

quent row access some specified time (tRP) after the PRECHARGE command is issued.

Input A10 determines whether one or all banks are to be precharged, and in the case

where only one bank is to be precharged, inputs BA0 and BA1 select the bank. When all

banks are to be precharged, inputs BA0 and BA1 are treated as “Don’t Care.” Aftera bank

has been precharged, it is in the idle state and must be activated prior to any READ or

WRITE commands b ei ng is s u ed to that bank.

DON’T CARE

DQM

CLK

T2T1 T4T3T0

COMMAND

ADDRESS

BANK a,

COL n

NOPWRITE

PRECHARGE

NOPNOP

n + 1

ACTIVE

tRP

BANK

(a or all)

BANK a,

ROW

DQM

COMMAND

ADDRESS

BANK a,

COL n

NOPWRITE

PRECHARGE

NOPNOP

n D

n + 1

ACTIVE

tRP

BANK

(a or all)

BANK a,

ROW

NOP

tWR = 2 CLK (when tWR > tCK)

tWR = 1 CLK (tCK > tWR)

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64Mb: x32 SDRAM

Commands

Power-Down

Power-down occurs if CKE is registered LOW coincident with a NOP or COMMAND

INHIBIT when no accesses are in progress (see Figure 24 on page 34). If power-down

occurs when all banks are idle, this mode is referred to as precharge power-do wn; if

power-dow n oc curs when there is a row a ct ive in eit h er bank, this mode is referred to as

active power-down. Entering power-down deactivates the input and output buffers,

excluding CKE, for maximum power savings while in standby. The device may not

remain in the power-down state longer than the r efresh period (tREF or tREFAT) since no

refresh operations are performed in this mode.

The power-down state is exited by registering an NOP or COMMAND INHIBIT and CKE

HIGH at the desired clock edge (meeting tCKS).

Figure 22: Terminating a WRITE Burst

Note: DQMs are LOW.

DON’T CARE

CLK

T2T1T0

COMMAND

ADDRESS

BANK,

COL n

WRITE BURST

TERMINATE NEXT

COMMAND

(ADDRESS)

(DATA)

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64Mb: x32 SDRAM

Commands

Figure 23: PRECHARGE Command

Figure 24: Power-Down

Clock Suspend

The clock suspend mode occurs when a column access/burst is in progress and CKE is

registered LOW. In the clock suspend mode, the internal clock is deactivated, “freezing”

the synchronous logic.

For each positive clock edge on which CKE is sampled LOW, the next internal positive

clock edge is suspended. Any command or data pr esent on the input pins at the time of a

suspended internal clock edge is ignored; any data present on the DQ pins remains

driven; and burst counters are not incremented, as long as the clock is suspended (see

examples in Figures25 and 26 on page 35).

CS#

WE#

CAS#

RAS#

CKE

CLK

A10

DON’T CARE

HIGH

All Banks

Bank Selected

A0–A9

BA0, 1 BANK

ADDRESS

DON’T CARE

tRAS

tRCD

tRC

All banks idle Input buffers gated off

Exit power-down mode.

()()

tCKS > tCKS

COMMAND NOP ACTIVE

Enter power-down mode.

NOP

CLK

CKE

()()

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64Mb: x32 SDRAM

Commands

Clock suspend mode is exited by registering CKE HIGH; the internal clock and related

operation will resume on the subsequent positive clock edge.

Burst Read/Single Write

The burst read/single write mode is entered by progr a mming the write burst mode bit

(M9) in the mode register to a logic 1. In this mode, all WRITE commands result in the

access of a single column location (burst of one), regardless of the programmed burst

length. READ commands access columns according to the programmed burst length

and sequence, just as in the normal mode of operation (M9 = 0).

Figure 25: Clock Suspend During WRITE Burst

Figure 26: Clock Suspend During READ Burst

Note: For this example, CL = 2, BL = 4 or greater, and DQM is LOW.

DON’T CARE

DIN

COMMAND

ADDRESS

WRITE

BANK,

COL n

NOPNOP

CLK

T2T1 T4T3 T5T0

CKE

INTERNAL

CLOCK

NOP

n + 1 D

n + 2

DON’T CARE

CLK

OUT

T2T1 T4T3 T6T5T0

COMMAND

ADDRESS

READ NOP NOP NOP

BANK,

COL n

NOP

OUT

n + 1 D

OUT

n + 2 D

OUT

n + 3

CKE

INTERNAL

CLOCK

NOP

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64Mb: x32 SDRAM

Commands

Concurrent Auto Precharge

An access command (READ or WRITE) to another bank while an access command with

auto precharge enabled is executing is not allowed by SDRAMs, unle ss the SDRAM

supports con current auto precharge. Micron SDRAMs support concurrent auto

precharge. Fo ur cas es where concurrent auto precharge occurs are defined below.

READ with Auto Precharge

• Int errupted by a READ (with or without auto prechar ge): A READ to bank m will inter-

rupt a READ on bank n, CL later. The precharge to bank n will begin when the READ

to bank m is registered (Figure 27).

• Interrupted by a WRITE (with or without auto precharge): A WRITE to bank m will

interrupt a READ on bank n when register ed. DQM s hould be us ed two clocks prior to

the WRITE command to prevent bus conten tion. The precharge to bank n will begin

when the WRITE to bank m is registered (Figure28 on page 37).

WRITE with Auto Precharge

• Int errupted by a READ (with or without auto prechar ge): A READ to bank m will inter-

rupt a WRITE on bank n when registered, with the data-out appearing CL later. The

precharge to bank n will begin after tWR is met, where tWR begins when the READ to

bank m is registered. The last valid WRITE to bank n will be data-in registered one

clock prior to the READ to bank m (Figure29 on page 37).

• Interrupted by a WRITE (with or without auto precharge): A WRITE to bank m will

interrupt a WRITE on bank n when registered. The precharge to bank n will begin

after tWR is met, where tWR begins when the WRITE to bank m is registered. The last

valid data WRITE to bank n will be data registered one clock prior to a WRITE to bank

m (Figure 30 on page 38).

Figure 27: READ with Auto Precharge Interrupted by a READ

Note: DQM is LOW.

DON’T CARE

CLK

DQ DOUT

T2T1 T4T3 T6T5T0

COMMAND READ - AP

BANK nNOP NOPNOPNOP

DOUT

a + 1 DOUT

dDOUT

d + 1

NOP

BANK n

CL = 3 (BANK m)

BANK m

ADDRESS

Idle

NOP

BANK n,

COL aBANK m,

COL d

READ - AP

BANK m

Internal

States t

Page Active READ with Burst of 4 Interrupt Burst, Precharge

Page Active READ with Burst of 4 Precharge

RP - BANK ntRP - BANK m

CL = 3 (BANK n)

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64Mb: x32 SDRAM

Commands

Figure 28: READ with Auto Precharge Interrupted by a WRITE

Notes: 1. DQM is HIGH at T2 to prevent DOUT a + 1 from contending with DIN d at T4.

Figure 29: WRITE with Auto Precharge Interrupted by a READ

Note: DQM is LOW.

CLK

DQ DOUT

T2T1 T4T3 T6T5T0

COMMAND NOPNOPNOPNOP

DIN

d + 1

DIN

dDIN

d + 2 DIN

d + 3

NOP

BANK n

BANK m

ADDRESS

Idle

NOP

DQM

BANK n,

COL aBANK m,

COL d

WRITE - AP

BANK m

Internal

States t

Page

Active READ with Burst of 4 Interrupt Burst, Precharge

Page Active WRITE with Burst of 4 Write-Back

RP -

BANK

ntWR -

BANK

CL = 3 (BANK n)

READ - AP

BANK n

DON’T CARE

CLK

T2T1 T4T3 T6T5T0

COMMAND WRITE - AP

BANK nNOPNOPNOPNOP

DIN

a + 1

DIN

NOP NOP

BANK n

BANK m

ADDRESS

BANK n,

COL aBANK m,

COL d

READ - AP

BANK m

Internal

States t

Page Active WRITE with Burst of 4 Interrupt Burst, Write-Back Precharge

Page Active READ with Burst of 4

ttRP - BANK m

DOUT

dDOUT

d + 1

CL = 3 (BANK m)

RP - BANK n

WR - BANK n

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64Mb: x32 SDRAM

Commands

Figure 30: WRITE with Auto Precharge Interrupted by a WRITE

Note: DQM is LOW.

Notes: 1. CKEn is the logic state of CKE at clock edge n; CKEn - 1 was the state of CKE at the previous

clock edge.

2. Current state is the state of the SDRAM immediately prior to clock edge n.

3. COMMANDn is the command registered at clock edge n, and ACTIONn is a result of

COMMANDn.

4. All states and sequences not shown are illegal or reserved.

5. Exiting power-down at clock edge n will put the device in the all banks idle state in time for

clock edge n + 1 (provided that tCKS is met).

6. Exiting self refresh at clock edge n will put the device in the all banks idle state after tXSR is

met. COMMAND INHIBIT or NOP commands should be issued on any clock edges occurring

during the tXSR period. A minimum of two NOP commands must be provided during tXSR

period.

7. After exiting clock suspend at clock edge n, the device will resume op eration and reco gnize

the next command at clock edge n + 1.

Table 8: Truth Table 2 – CKE

Notes: 1–4 apply to entire table

CKEn - 1 CKEnCurrent State COMMANDnACTIONnNotes

L L Power-do wn X Maintain po wer-down

Self refresh X Maintain self refresh

Clock suspend X Maintain clock suspend

L H Power-down COMMAND INHIBIT or NOP Exit power-down 5

Self refresh COMMAND INHIBIT or NOP Exit self refresh 6

Clock suspend X Exit clock suspend 7

H L All banks idle COMMAND INHIBIT or NOP Power-down entry

All banks idle AUTO REFRESH Self refresh entry

Reading or writing WRITE or NOP Clock suspend entry

H H See Table 9 on page 39

DON’T CARE

CLK

T2T1 T4T3 T6T5T0

COMMAND

WRITE - AP

BANK nNOPNOPNOPNOP

d + 1

a + 1 D

a + 2

d + 2 D

d + 3

NOP

BANK n

BANK m

ADDRESS

NOP

BANK n,

COL aBANK m,

COL d

WRITE - AP

BANK m

Internal

States

Page Active WRITE with Burst of 4 Interrupt Burst, Write-Back Precharge

Page Active WRITE with Burst of 4 Write-Back

WR - BANK ntRP - BANK ntWR - BANK m

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64Mb: x32 SDRAM

Commands

Notes: 1. This table applies when CKEn - 1 was HIGH and CKEn is HIGH (see Table 8 on page 38) and

after tXSR has been met (if the previous state was self refresh).

2. This table is bank-specific, except where noted; that is, the current state is for a specific

bank and the commands shown are those allowed to be issued to that bank when in that

state. Exceptions are covered in the notes below.

3. Current state definitions:

4. The following states must not be interrupted by a command issued to the same bank. COM-

MAND INHIBIT or NOP commands or allowable commands to the other bank should be

issued on any clock edge occurring during these states. Allowable commands to the other

bank are determi ned by its current st ate and Ta ble 9 and according to Table 10 on page 41.

Table 9: Truth Table 3 – Current State Bank n, Command to Bank n

Notes 1–6 apply to entire table; notes appear below and on next page

Current State CS# RAS# CAS# WE# Command (Action) Notes

Any HXXX

COMMAND INHIBIT (NOP/continue pr evious operation)

LHHH

NO OPERATION (NOP/continue pre vious operation )

Idle L L H H ACTIVE (Select and activate row)

LLLH

AUTO REFRESH 7

LLLL

LOAD MODE REGISTER 7

LLHL

PRECHARGE 11

Row activeLHLH

READ (Select column and start READ burst) 10

LHLL

WRITE (Select column and start WRITE burst) 10

LLHL

PRECHARGE (Deactivate row in bank or banks) 8

Read

(auto

precharge

disabled)

LHLH

READ (Select column and start new READ burst) 10

LHLL

WRITE (Select column and start WRITE burst) 10

LLHL

PRECHARGE (Truncate READ burst, st art PRECHARGE) 8

LHHL

BURST TER MINATE 9

Write

(auto

precharge

disabled)

LHLH

READ (Select column and start READ burst) 10

LHLL

WRITE (Select column and start new WRITE burst) 10

LLHL

PRECHARGE (Truncate WRITE burst, start PRECHARGE) 8

LHHL

BURST TER MINATE 9

Idle: The bank has been precharged , and tRP has been met.

Row active: A row in the bank has been activa ted, and tRCD has been met. No da ta bursts/

accesses and no register accesses are in progress.

Read: A READ burst has been initiated, with auto precharge disabled, and has not

yet terminated or been terminated.

Write: A WRITE burst has been initiated, with auto precharge disabled, and has not

yet terminated or been terminated.

Precharging: Starts with registration of a PRECHARGE command and ends when

tRP is met. After tRP is met, the bank will be in the idle state.

Row activating: Starts with registration of an ACTIVE command and ends when tRCD

is met. After tRCD is met, the bank will be in the row active state.

Read with auto

precharge enabled: Starts with registration of a READ command with auto precharge

enabled and ends when tRP has been met. After tRP is met, the bank

will be in the idle state.

Write w /au to

precharge enabled: Starts with registration of a WRITE command with auto precharge

enabled and ends when tRP has been met. After tRP is met, the bank

will be in the idle state.

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64Mb: x32 SDRAM

Commands

5. The following states must not be interrupted by any executable command; COMMAND

INHIBIT or NOP commands must be applied on each positive clock edge during these states.

6. All states and sequences not shown are illegal or reserved.

7. Not bank-specific; requires that all banks are idle.

8. Ma y or may not be bank-specific; if all banks are to be precharged, all must be in a valid

state for precharging.

9. Not bank-specific; BURST TE RMINATE affects the most recent READ or WRITE burst, regard-

less of bank.

10. READs or WRITEs listed in the Command (Action) column in clude READs or WRITEs with

auto precharge enabled and READs or WRITEs with auto precharge disabled.

11. Does not affect the state of the bank and acts as a NOP to that bank.

Refreshing: Starts with registration of an AUTO REFRESH command and ends

when tRC is met. After tRC is met, the SDRAM will be in the all banks

idle state.

Accessing mode

ends when tMRD has been met. After tMRD is met, the SDRAM will

be in the all banks idle state.

Precharging all: Starts with registration of a PRECHARGE ALL command and ends

when tRP is met. After tRP is met, all banks will be in the idle state.

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64Mb: x32 SDRAM

Commands

Notes: 1. This table applies when CKEn - 1 was HIGH and CKEn is HIGH (see Table 8 on page 38) and

after tXSR has been met (if the previous state was self refresh).

2. This table describes an alternate bank operations, except where noted; that is, the current

state is for bank n and the commands shown are those allowed to be issued to bank m

(assuming that bank m is in such a state that the given command is allowable). Exceptions

are covered in the notes below.

3. Current state definitions:

4. AUTO REFRESH, SELF REFRESH, and LOAD MODE REGISTER commands may only be issued

when all banks are idle.

Table 10: Truth Table 4 – Current State Bank n, Command to Bank m

Notes 1–6 apply to entire table; notes appear below and on next page

Current State CS# RAS# CAS# WE# Command (Action) Notes

Any HXXX

COMMAND INHIBIT (NOP/continue pr evious operation)

LHHH

NO OPERATION (NOP/continue pre vious operation )

Idle XXXX

Any command otherw ise allowed to Bank m

Row

activating,

active, or

precharging

LLHH

ACTIVE (Select and activate row)

LHLH

READ (Select column and start READ burst) 7

LHLL

WRITE (Select column and start WRITE burst) 7

LLHL

PRECHARGE

Read

(auto

precharge

disabled)

LLHH

ACTIVE (Select and activate row)

LHLH

READ (Select column and start new READ burst) 7, 10

LHLL

WRITE (Select column and start WRITE burst) 7, 11

LLHL

PRECHARGE 9

Write

(auto

precharge

disabled)

LLHH

ACTIVE (Select and activate row)

LHLH

READ (Select column and start READ burst) 7, 12

LHLL

WRITE (Select column and start new WRITE burst) 7, 13

LLHL

PRECHARGE 9

Read

(with auto

precharge)

LLHH

ACTIVE (Select and activate row)

LHLH

READ (Select column and start new READ burst) 7, 8, 14

LHLL

WRITE (Select column and start WRITE burst) 7, 8, 15

LLHL

PRECHARGE 9

Write

(with auto

precharge)

LLHH

ACTIVE (Select and activate row)

LHLH

READ (Select column and start READ burst) 7, 8, 16

LHLL

WRITE (Select column and start new WRITE burst) 7, 8, 17

LLHL

PRECHARGE 9

Idle: The bank has bee n precharged, and tRP has been met.

Row active: A row in the bank has been activated, and tRCD has been met . No

data bursts/accesses and no register accesse s are in progress.

Read: A READ burst has been initiated, with auto precharge disabled and

has not yet terminated or been terminated.

Write: A WRITE burst has been initiated, with auto precharge disabled and

has not yet terminated or been terminated.

Read w/auto

precharge enabled: Starts with registration of a READ command with auto precharge

enabled and ends when tRP has been met. After tRP is met, the bank

will be in the idle state.

Write w /au to

precharge enabled: Starts with registration of a WRITE command with auto precharge

enabled and ends when tRP has been met. After tRP is met, the bank

will be in the idle state.

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64Mb: x32 SDRAM

Commands

5. A BURST TERMINATE command cannot be issued to another bank; it applies to the bank

represented by the current state only.

6. All states and sequences not shown are illegal or reserved.

7. READs or WRITEs to bank m listed in the Command (Action) column include READs or

WRITEs with auto precharge enabled and READs or WRITEs with auto precharge disabled.

8. Concurrent auto precharge: bank n will in itiate the AUTO PRECHARGE command when its

burst has been interrupted by bank m’s burst.

9. Burst in bank n continues as initiated.

10. For a READ without auto precharge interrupted by a READ (with or without auto pre-

charge), the READ to bank m will interrupt the READ on bank n, CL later (Figure 10 on

page 23).

11. For a READ without auto precharge interrupted by a WRITE (with or without auto pre-

charge), th e WRITE to bank m will interrupt the READ on bank n when registered (Figure 12

on page 25 and Figure 13 on page 26). DQM should be used one clock prior to the WRITE

command to prevent bus contention.

12. For a WRITE without auto precharge interrupted by a READ (with or without auto pre-

charge), the READ to bank m will interrupt the WRITE on bank n when registered (Figure 20

on page 31), with the data-out appearing CL later. The last valid WRITE to bank n will be

data-in registered one clock prior to the READ to bank m.

13. For a WRITE without auto precharge interrupted by a WRITE (with or with out auto pre-

charge), th e WR ITE to bank m will in terru pt the WRITE on bank n when registered

(Figure 18 on page 30). The last valid WRITE to bank n will be data-in registered one clock

prior to the READ to bank m.

14. For a READ with auto precharge interrupted by a READ (with or without auto precharge),

the READ to bank m will interrupt the READ on bank n, CL later. The precharge to bank n

will begin when the READ to bank m is registered (Figure 27 on page 36).

15. For a READ with auto precharge interrupted by a WRITE (with or wit hout auto precharge),

the WRITE to bank m will interrupt the READ on bank n when registered. DQM should be

used two clocks prior to the WRITE command to prevent bus contention. The precharg e to

bank n will begin when the WRITE to bank m is registered (Figure 28 on page 37).

16. For a WRITE with auto precharge interrupted by a READ (with or without auto precharge),

the READ to bank m will interrupt the WRITE on bank n when registered, with the data-out

appearing CL later. The precharge to bank n will begin after tWR is met, where tWR begins

when the READ to bank m is registered. The last valid WRITE to bank n will be data-in regis-

tered one clock prior to the READ to bank m (Figure 29 on page 37).

17. For a WRITE with auto precharge interrupted by a WRITE (with or without auto precharge) ,

the WRITE to bank m will interrupt the WRITE on bank n when registered. The precharge to

bank n will begin after tWR is met, where tWR begins when the WRITE to bank m is regis-

tered. The last valid WRITE to bank n will be data registered one clock prior to the WRITE to

bank m (Figure 30 on page 38).

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Electrical Specifications

Stresses greater than those listed in Table 11 may cause permanent damage to the

device. This is a stress rating only, and functional operation of the device at these or any

other conditions above those indicated in the operational sections of this specification is

not implied. Exposure to absolute maximum rating condi tions for extended periods may

affect reli ability.

Temperature and Thermal Impedance

It is imper ative that the SDRAM device’s temperature specifications, shown in Table 12

on page 44, be maintained in order to ensure the junction temperature is in the proper

operating range to meet data sheet specifications. An important step in maintaining the

proper junction temperature is using the device’s thermal impedances correctly. The

thermal im pe d ance s are listed in Table 13 on page 44 for the appl ic ab le die revision and

packages. These thermal impedance values v a ry according to the density, package, and

particular design used for each device.

Incorr ectly using thermal impedances can produce significant errors. Read Micron tech-

nical note TN-00-08, Thermal Applications prior to using the thermal impedances liste d

in Table 13 on page 44. To ensure the compatibility of current and future designs,

contact Micron Applications Engineering to confirm thermal impedance values.

The SDRAM device’s safe junction temperature range can be maintained when the TC

specification is not exceeded. In applications where the device’s ambient temperature is

too high, use of forced air and/or heat sinks may be required in order to satisfy the case

temperature specifications.

Table 11: Absolute Maximum Ratings

Parameter Min Max Units

Voltage on VDD, VDDQ supply rela tive to VSS –1V +4.6 V

Voltage on inputs, NC or I/O pins relative to VSS –1V +4.6 V

Operating temperature

TA (commercial)

TA (industrial)

TA (automotive)

–40

+85

+105

°C

Storage temperature (plastic) –55 +150 °C

Power dissipation –1W

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Electrical Specifications

Notes: 1. MAX operating case temperature, TC, is measured in the center of the package on the top

side of the device, as shown in Figures 31 and 32 on page 45.

2. Device functionality is not guaranteed if the device exceeds maximum TC during operation.

3. All temperature specificatio ns must be satisfied.

4. The case tempera ture should be measur ed by gluing a thermocouple to the top center of

the component. This should be done with a 1mm bead of conductive epoxy, as defined by

the JEDEC EIA/JESD51 standards. Care should be taken to ensure the thermocouple bead is

touching the case.

5. Operating ambient temperature surrounding the package.

Notes: 1. For designs expected to last beyond the die revision listed, contact Micron Applications

Engineering to confirm thermal impedance values.

2. Thermal resistance data is sampled from multiple lots and the values should be viewed as

typical.

3. These are estimates; actual results may vary.

Table 12: Temperature Limits

Parameter Symbol Min Max Units Notes

Operating case temperature:

Commercial

Industrial

Automotive

TC0

–40

105

°C 1, 2, 3, 4

Junction temperature:

Commercial

Industrial

Automotive

TJ0

–40

110

°C 3

Ambient temperature:

Commercial

Industrial

Automotive

TA0

–40

105

°C 3, 5

Peak reflow temperature TPEAK –260°C

Table 13: Thermal Impedance Simulated Values

Die

Revision Package Substrate θ JA (°C/W)

Airflow = 0m/s θ JA (°C/W)

Airflow = 1m/s θ JA (°C/W)

Airflow = 2m/s θ JB

(°C/W) θ JC

(°C/W)

G 86-pin

TSOP 4-layer 66.6 57.7 54.6 53.6 12.7

90-ball

FBGA 2-layer 70.6 57.6 69.5 35.7 7.95

4-layer 54 47.3 52.7 35.2

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Electrical Specifications

Figure 31: Example Temperature Test Point Location, 86-Pin TSOP (Top View)

Figure 32: Example Temperature Test Point Location, 90-Ball FBGA (Top View)

22.22mm

11.11mm

Test point

10.16mm

5.08mm

8.00mm

4.00mm

Test point

6.50mm

13.00mm

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Electrical Specifications

Table 14: DC Electrical Characteristics and Operating Conditions

Notes 1, 6, 27 apply to entire table; notes ap pear on pages 49 and 50; VDD, VDDQ = +3.3V ±0.3V

Parameter/Condition Symbol Min Max Units Notes

Supply voltage VDD, VDDQ3 3.6 V

Input high voltage: Logic 1; All inputs VIH 2VDD + 0.3 V 22

Input low voltage: Logic 0; All inputs VIL –0.3 0.8 V 22

Input leakage current:

Any input 0V ≤ VIN ≤ VDD (All other pins not under test = 0V) II–5 5 µA

Output leakage current: DQs are disabled; 0V ≤ VOUT ≤ VDDQIOZ –5 5 µA

Output levels:

Output high voltage (IOUT = –4mA)

Output low voltage (IOUT = 4mA) VOH 2.4 – V

VOL –0.4V

Table 15: IDD Specifications and Conditions

Notes 1, 6, 11, 13, 27 apply to entire table; notes appear on pages 49 and 50; VDD, VDDQ = +3.3V ±0.3V

Parameter/Condition Symbol

Max

Units Notes-5 -55 -6 -7

Operating current: Active mode; Burst = 2; READ or WRITE; tRC

≥ tRC (MIN); CL = 3 IDD1 200 190 150 130 mA 3, 18,

19, 26

Standby current: Power-down mode; All banks idle; CKE = LOW IDD22222mA

Standby current: Active mode; CKE = HIGH; CS# = HIGH; All

banks active after tRCD met; No accesses in progress IDD380706050mA3, 12,

19, 26

Operating current: Burst mode; Continuous burst; READ or

WRITE; All banks active; CL = 3 IDD4 280 260 180 160 mA 3, 18,

19, 26

Auto refresh current:

CL = 3; CKE, CS# = HIGH

tRFC = tRFC (MIN) IDD5 225 225 225 225 mA 3, 12,

18, 19,

Self refresh current: CKE ≤ 0.2V IDD62222mA4

Table 16: TSOP Capacitance

Note 2 applies to entire table; notes appear on pages 49 and 50

Parameter Symbol Min Max Units

Input capacitance: CLK CI12.54.0pF

Input capacitance: All other input-only pin s CI22.54.0pF

Input/output capacitance: DQs CIO 4.0 6.5 pF

Table 17: VFBGA Capacitance

Note 2 applies to entire table; notes appear on pages 49 and 50

Parameter Symbol Min Max Units

Input capacitance: CLK CI12.54.0pF

Input capacitance: All other input-only balls CI22.54.0pF

Input/output capacitance: DQs CIO 4.0 6.5 pF

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Electrical Specifications

Table 18: Electrical Characteristics and Recommended AC Operating Conditions

Notes 5, 6, 8, 9, 11 apply to entire table; notes appear on pages 49 and 50; VDD, VDDQ = +3.3V ±0.3V

AC Characteristics -5 -55 -6 -7

Units NotesParameter Symbol Min Max Min Max Min Max Min Max

Access time from CLK

(positive edge) CL = 3 tAC (3) – 4.5 – 5 5.5 – 5.5 ns

CL = 2 tAC (2)–––– 7.5–8ns

CL = 1 tAC (1)–––– 17–17ns

Address hold time tAH1–1–1–1–ns

Address setup time tAS 1.5 – 1.5 – 1.5 – 2 – ns

CLK high-level width tCH2–2–2.5–2.75–ns

CLK low-level width tCL2–2–2.5–2.75–ns

Clock cycle time CL = 3 tCK (3)5–5.5–6–7–ns23

CL = 2 tCK (2)––––10–10–ns23

CL = 1 tCK (1)––––20–20–ns23

CKE hold time tCKH1–1–1–1–ns

CKE setup time tCKS 1.5 – 1.5 – 1.5 – 2 – ns

CS#, RAS#, CAS#, WE#, DQM

hold time

tCMH1–1–1–1–ns

CS#, RAS#, CAS#, WE#, DQM

setup time

tCMS 1.5 – 1.5 – 1.5 – 2 – ns

Data-in hold time tDH1–1–1–1–ns

Data-in setup time tDS 1.5 – 1.5 – 1.5 – 2 – ns

Data-out High-Z time CL = 3 tHZ (3) 4.5 – 5 – 5.5 – 5.5 ns 10

CL = 2 tHZ (2) –––– 7.5 –8ns10

CL = 1 tHZ (1) –––– 17– 17ns10

Data-out Low-Z time tLZ1–1–1–1–ns

Data-out hold time tOH 1.5 – 2 – 2 – 2.5 – ns

ACTIVE-to-PRECHARGE

command

tRAS 38.7 120k 38.7 120k 42 120k 42 120k ns

ACTIVE-to-ACTIVE command

period

tRC 55 – 55 – 60 – 70 – ns

AUTO REFRESH period tRFC60–60–60–70–ns

ACTIVE to READ or WRITE delay tRCD15–16.5–18–20–ns

Refresh period (4,096 rows) tREF – 64 – 64 – 64 – 64 ms

Refresh period–Automotive

(4,096 rows)

tREFAT –16–16–16–16ms

PRECHARGE command period tRP 15 – 16.5 – 18 – 20 – ns

ACTIVE bank a to ACTIVE bank b

command

tRRD10–11–12–14–ns25

Transition time tT 0.3 1.2 0.3 1.2 0.3 1.2 0.3 1.2 ns 7

Write recovery time tWR2–2–1CLK

+ 6ns –1CLK

+ 7ns –tCK 24

12ns – 14ns – ns 28

Exit self refresh to ACTIVE

command

tXSR55–55–70 –70–ns20

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Electrical Specifications

Table 19: AC Functional Characteristics

Notes 5, 6, 8, 9, 11 apply to entire table; notes appear on pages 49 and 50

Parameter Symbol -5 -55 -6 -7 Units Notes

READ/WRITE command to READ/WRITE command tCCD1111tCK 17

CKE to clock disable or power-down entry mode tCKED1111tCK 14

CKE to clock enable or power-down exit setup mode tPED1111tCK 14

DQM to input data delay tDQD0000tCK 17

DQM to data mask during WRITEs tDQM0000tCK 17

DQM to data High-Z during READs tDQZ2222tCK 17

WRITE command to input data delay tDWD0000tCK 17

Data-in to ACTIVE command CL = 3 tDAL (3)5555tCK 15, 21

CL = 2 tDAL (2) – – 4 4 tCK 15, 21

CL = 1 tDAL (1) – – 3 3 tCK 15, 21

Data-in to PRECHARGE command tDPL2222tCK 16, 21

Last data-in to burst stop command tBDL1111tCK 17

Last data-in to new READ/WRITE command tCDL1111tCK 17

Last data-in to PRECHARGE command tRDL2222tCK 16, 21

LOAD MODE REGISTER command to ACTIVE or REFRESH

command

tMRD2222tCK 26

Data-out to High-Z from PRECHARGE

command CL = 3 tROH (3)3333tCK 17

CL = 2 tROH (2) – – 2 2 tCK 17

CL = 1 tROH (1)–––1

tCK 17

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Notes

Notes 1. All v o ltages referenced to VSS.

2. This param eter is sampled. VDD, VDDQ = +3.3V; f = 1 MHz, TA = 25°C; pin under test

biased at 1.4V. AC can range from 0pF to 6pF.

3. IDD is dependent on output loading and cycle rates. Specified values are obtained

with minimum cycle time and the outputs open.

4. Enables on-chip refresh and address counters.

5. The minimum specifications are used only to indicate cycle time at which proper

operation o ver the full temper ature r ange (0°C ≤ T A ≤ +70°C (commercial), –40°C ≤ TA ≤

+85°C (industrial), and –40°C ≤ TA ≤ +105°C (automotive) is ensured.

6. An initial pause of 100µs is required after power-up, followed by two AUTO REFRESH

commands, before proper device operation is ensured (VDD and VDDQ must be pow-

ered up simultaneously. VSS and VSSQ must be at same po te ntial). The two AU TO

REFRESH command wake-ups should be repeated any time the tREF re fresh require-

ment is exceeded.

7. AC characteristics assume tT = 1ns.

8. In addition to meeting the transition rate specification, the clock and CKE must tr an-

sit between VIH and VIL (or between VIL and VIH) in a monotonic manner.

9. Outputs measured at 1.5V with equi valent load :

10. tHZ defines the time at which the output achieves the open circuit condition; it is not

a reference to VOH or VOL. The last valid data element will meet tOH before going

High-Z.

11. AC timing and IDD tests have VIL = 0.25 and VIH = 2.75, wit h timing referenced to 1.5V

crossover point.

12. Other input signals are allowed to transition no more than once in any two-clock

period and are otherwise at valid VIH or VIL levels.

13. IDD specifications are tested after the device is properly initialized.

14. Timing is actually specified by tCKS; clock(s) specified as a reference only at mini-

mum cycle rate.

15. Timing is actually specified by tWR plus tRP; clock(s) is (are) specified as a reference

only at minimum cycle rate.

16. Timing actually specified by tWR.

17. Required clocks are specified by JEDEC functionality and are not dependent on any

timing parameter.

18. The I DD curr ent will decrease as the CL is reduced. This is due to the fact that the max-

imum cycle ra te is slower as the CL is reduced.

19. Address transitions average one transition every two clocks.

20. CLK must be toggled a minimum of two times during this period.

21. Based on tCK = 143 MHz for -7, 166 MHz for -6, 183 MHz for -55, and 200 MHz for -5.

22. VIH overshoot: VIH(MAX) = VDDQ + 1.2V for a pulse width ≤ 3ns, and the pulse width

cannot be greater than one-thir d the cycle rate . VIL undershoot: VIL(MIN) = -1.2V for a

pulse width ≤ 3ns, and the pulse width cannot be gr eater than one-thir d the cycle r ate .

Q30pF

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Notes

23. The clock frequency must remain constant during access or precharge states (READ,

WRITE, including tWR, and PRECHARGE commands). CKE may be used to reduce the

data rate.

24. Auto precharge mode only.

25. JEDEC and PC100 specify three clocks.

26. tCK = 7ns for -7, 6ns for -6, 5.5ns for -55, and 5ns for -5.

27. VDD(MIN) = 3.135V for -6, -55, and -5 speed grades.

28. Check fac tory for availability of specia lly screened devices having tWR = 10ns. tWR = 1

tCK for 100 MHz and slower (tCK = 10ns and higher) in manual precharge.

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Timing Diagrams

Figure 33: Initialize and Load Mode Register

Notes: 1. The mode register may be loaded prior to the AUTO REFRESH cycles if desired.

2. Outputs are guaranteed High-Z after command is issued.

tCH

tCL

tCK

CKE

CLK

COMMAND

BA0, BA1

BANK

tRFC tMRD

tRFC

AUTO REFRESH AUTO REFRESH Program Mode Register

1, 2

tCMH

tCMS

Precharge

all banks

()()

tRP

()()

tCKS

Power-up:

and

CK stable

T = 100µs

(MIN)

PRECHARGE NOP AUTO

REFRESH NOP

LOAD MODE

()()

AUTO

REFRESH

ALL

BANKS

()()

High-Z

tCKH

()()

DQM 0–3

()()

()()()()

()()

NOP

()()

tCMH

tCMS tCMH

tCMS

A0–A9

ROW

tAH

tAS

CODE

tAH

tAS

CODE

()()

A10

ROW

tAH

tAS

CODE

()()

ALL BANKS

SINGLE BANK

()()

DON’T CARE

UNDEFINED

T0 T1 Tn + 1 To + 1 Tp + 1 Tp + 2 Tp + 3

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Timing Diagrams

Figure 34: Power-Down Mode

Note: Violating refresh requirements during power-down may result in a loss of data.

tCH

tCL

tCK

Two clock cycles

CKE

CLK

All banks idle, enter

power-down mode

Precharge all

active banks

Input buffers gated off while in

power-down mode

Exit power-down mode

()()

tCKS tCKS

COMMAND

tCMH

tCMS

PRECHARGE NOP NOP ACTIVENOP

()()

All banks idle

BA0, BA1

BANK

BANK(S)

()()

High-Z

tAH

tAS

tCKH

tCKS

DQM 0-3

()()

A0-A9

ROW

()()

ALL BANKS

SINGLE BANK

A10

ROW

()()

T0 T1 T2 Tn + 1 Tn + 2

DON’T CARE

UNDEFINED

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Timing Diagrams

Figure 35: Clock Suspend Mode

Notes: 1. For this example, BL = 2, CL = 3, and auto precharge is disabled.

2. A8 and A9 = “Don’t Care.”

tCH

tCL

tCK

tAC

tLZ

DQM0–3

CLK

A10

tOH

DOUT m

tAH

tAS

tAH

tAS

tAH

tAS

BANK

tDH

DOUT e

tAC tHZ

DOUT m + 1

COMMAND

tCMH

tCMS

NOPNOP NOP NOPNOPREAD WRITE

DON’T CARE

UNDEFINED

CKE

tCKS tCKH

BANK

COLUMN m

tDS

DOUT e + 1

NOP

tCKH

tCKS

tCMH

tCMS

COLUMN e

T0 T1 T2 T3 T4 T5 T6 T7 T8 T9

BA0, BA1

A0–A9

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Timing Diagrams

Figure 36: Auto Refresh Mode

UNDEFINEDDON’T CARE

tCH

tCL

tCK

CKE

CLK

tRFC

()()

tRP

()()

COMMAND

tCMH

tCMS

NOPNOP

()()

BANK

ACTIVE

AUTO

REFRESH

()()

NOPNOPPRECHARGE

Precharge all

active banks

AUTO

REFRESH

tRFC

High-Z

BANK(S)

()()

tAH

tAS

tCKH

tCKS

()()

NOP

()()

ROW

()()

ALL BANKS

SINGLE BANK

A10

ROW

()()

T0 T1 T2 Tn + 1 To + 1

BA0, BA1

A0–A9

DQM 0–3

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Timing Diagrams

Figure 37: Self Refresh Mode

Notes: 1. Self refresh mode not supported on automotive temperature (AT) devices.

tCH

tCL

tCK

tRP

CKE

CLK

Enter self refresh mode

Precharge all

active banks

tXSR

CLK stable prior to exiting

self refresh mode

Exit self refresh mode

(Restart refresh time base)

()()()()

()()

DON’T CARE

UNDEFINED

COMMAND

tCMH

tCMS

AUTO

REFRESH

PRECHARGE NOP NOP

BANK(S)

High-Z

tCKS

AUTO

REFRESH

> tRAS

tCKH

tCKS

ALL BANKS

SINGLE BANK

A10

T0 T1 T2 Tn + 1 To + 1 To + 2

BA0, BA1

DQM0–3

A0–A9

()()

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Timing Diagrams

Figure 38: Single READ

Notes: 1. For this example, BL = 1, CL = 2, and the READ burst is followed by a “manual” PRECHARGE.

2. A8, A9 = “Don’t Care.”

ALL BANKS

tCH

tCL

tCK

tAC

tLZ

tRP

tRAS

tRCD CAS Latency

tRC

DQM /

DQML, DQMH

CKE

CLK

A0-A9

BA0, BA1

A10

tOH

OUT

tCMH

tCMS

tAH

tAS

tAH

tAS

tAH

tAS

ROW

BANK BANK BANK

ROW

BANK

tHZ

COMMAND

tCMH

tCMS

PRECHARGEACTIVE NOP READ NOP ACTIVE

DISABLE AUTO PRECHARGE SINGLE BANK

tCKH

tCKS

COLUMN

T0 T1 T2 T4T3 T5

DON’T CARE

UNDEFINED

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Timing Diagrams

Figure 39: Single READ – Without Auto Precharge

Notes: 1. For this example, BL = 4, CL = 2, and the READ is followed by a “manual” PRECHARGE.

2. A8 and A9 = “Don’t Care.”

ALL BANKS

tCH

tCL

tCK

tAC

tLZ

tRP

tRAS

tRCD CAS Latency

tRC

CKE

CLK

A10

tOH

OUT

tCMH

tCMS

tAH

tAS

tAH

tAS

tAH

tAS

ROW

BANK BANK BANK

ROW

BANK

tHZ

tOH

OUT

m + 3

tAC tOH

tAC

OUT

m + 2D

OUT

m + 1

COMMAND

tCMH

tCMS

PRECHARGENOPNOP NOPACTIVE NOP READ NOP ACTIVE

DISABLE AUTO PRECHARGE SINGLE BANK

DON’T CARE

UNDEFINED

tCKH

tCKS

COLUMN m

T0 T1 T2 T4T3 T5 T6 T7 T8

BA0, BA1

DQM 0-3

A0-A9

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Timing Diagrams

Figure 40: READ – with Auto Precharge

Notes: 1. For this example, BL = 4 and CL = 2.

2. A8 and A9 = “Don’t Care.”

DON’T CARE

UNDEFINED

ENABLE AUTO PRECHARGE

tCH

tCL

tCK

tAC

tLZ

tRP

tRAS

tRCD CAS Latency

tRC

CKE

CLK

A10

tOH

OUT

tCMH

tCMS

tAH

tAS

tAH

tAS

tAH

tAS

ROW

BANK BANK

ROW

BANK

tHZ

tOH

OUT

+ 3

tAC tOH

tAC

OUT

+ 2D

OUT

+ 1

COMMAND

tCMH

tCMS

NOPNOP NOPACTIVE NOP READ NOP ACTIVENOP

tCKH

tCKS

COLUMN m

T0 T1 T2 T4T3 T5 T6 T7 T8

BA0, BA1

DQM 0-3

A0-A9

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Timing Diagrams

Figure 41: Alternating Bank Read Accesses

Notes: 1. For this example, BL = 4 and CL = 2.

2. A8 and A9 = “Don’t Care.”

DON’T CARE

UNDEFINED

ENABLE AUTO PRECHARGE

tCH

tCL

tCK

tAC

tLZ

CLK

A10

tOH

OUT

tCMH

tCMS

tAH

tAS

tAH

tAS

tAH

tAS

ROW

tOH

DOUT m + 3

tAC tOH

tAC

DOUT m + 2DOUT m + 1

COMMAND

tCMH

tCMS

NOP NOPACTIVE NOP READ NOP ACTIVE

tOH

OUT

tAC tAC

READ

ENABLE AUTO PRECHARGE

ROW

ACTIVE

ROW

BANK 0 BANK 0 BANK 4 BANK 4 BANK 0

CKE

tCKH

tCKS

COLUMN m

COLUMN b

T0 T1 T2 T4T3 T5 T6 T7 T8

tRP - BANK 0

tRAS - BANK 0

tRCD - BANK 0 tRCD - BANK 0

CAS Latency - BANK 0

tRCD - BANK 4 CAS Latency - BANK 4

tRC - BANK 0

RRD

BA0, BA1

DQM 0-3

A0-A9

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Timing Diagrams

Figure 42: READ – Full-Page Burst

Notes: 1. For this example, CL = 2.

2. A8 and A9 = “Don’t Care.”

3. Page left open; no tRP.

tCH

tCL tCK

tAC

tLZ

tRCD CAS Latency

CKE

CLK

A10

tOH

Dout m

tCMH

tCMS

tAH

tAS

tAH

tAS

tAC tOH

OUT

m+1

ROW

tHZ

tAC tOH

OUT

m+1

tAC tOH

OUT

m+2

tAC tOH

OUT

m-1

tAC tOH

OUT

Full-page burst does not self-terminate.

Can use BURST TERMINATE command.

()()

Full page completed

256 locations within same row

DON’T CARE

UNDEFINED

COMMAND

tCMH

tCMS

NOPNOP NOPACTIVE NOP READ NOP BURST TERMNOP NOP

()()

NOP

()()

tAH

tAS

BANK

()()

BANK

tCKH

tCKS

()()

COLUMN m

T0 T1 T2 T4T3 T5 T6 Tn + 1 Tn + 2 Tn + 3 Tn + 4

BA0, BA1

DQM 0-3

A0-A9

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Timing Diagrams

Figure 43: READ – DQM Operation

Notes: 1. For this example, CL = 2.

2. A8 and A9 = “Don’t Care.”

tCH

tCL

tCK

tRCD CAS Latency

CKE

CLK

A10

tCMS

ROW

BANK

ROW

BANK

DON’T CARE

UNDEFINED

tAC

DOUT m

tOH

DOUT m + 3DOUT m + 2

ttHZ LZ

tCMH

COMMAND

NOPNOP NOPACTIVE NOP READ NOPNOP NOP

tHZ

tAC tOH

tAH

tAS

tCMS tCMH

tAH

tAS

tAH

tAS

tCKH

tCKS

ENABLE AUTO PRECHARGE

DISABLE AUTO PRECHARGE

COLUMN m

T0 T1 T2 T4T3 T5 T6 T7 T8

BA0, BA1

DQM 0-3

A0-A9

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Timing Diagrams

Figure 44: Single WRITE

Notes: 1. For this example, BL = 4, and the WRITE burst is followed by a “manual” PRECHARGE.

2. 10ns is required between <DIN m> and the PRECHARGE command, regardless of frequency,

to meet tWR.

3. A8 and A9 = “Don’t Care.”

DON’T CARE

DISABLE AUTO PRECHARGE

ALL BANKS

tCH

tCL

tCK

tRP

tRAS

tRCD

tRC

DQM /

DQML, DQMH

CKE

CLK

A0-A9

BA0, BA1

A10

tCMH

tCMS

tAH

tAS

ROW

BANK BANK BANK

ROW

BANK

tWR

tDH

tDS

COMMAND

tCMH

tCMS

ACTIVE NOP WRITE NOP PRECHARGE ACTIVE

tAH

tAS

tAH

tAS

SINGLE BANK

tCKH

tCKS

COLUMN m

T0 T1 T2 T4T3 T5 T6

NOP

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Timing Diagrams

Figure 45: WRITE – Without Auto Precharge

Notes: 1. For this example, BL = 4, and the WRITE burst is followed by a “manual” PRECHARGE.

2. Faster frequencies require two clocks (when tWR > tCK).

3. A8 and A9 = “Don’t Care.”

4. tWR of 1 CLK available if running 100 MHz or slower. Check factory for availability.

DISABLE AUTO PRECHARGE

ALL BANKs

tCH

tCL

tCK

tRP

tRAS

tRCD

tRC

CKE

CLK

A10

tCMH

tCMS

tAH

tAS

ROW

BANK BANK BANK

ROW

BANK

tWR

DON’T CARE

UNDEFINED

tDH

tDS

m + 1 D

m + 2 D

m + 3

COMMAND

tCMH

tCMS

NOPNOP NOPACTIVE NOP WRITE NOPPRECHARGE ACTIVE

tAH

tAS

tAH

tAS

tDH

tDS tDH

tDS

SINGLE BANK

tCKH

tCKS

COLUMN m

T0 T1 T2 T4T3 T5 T6 T7 T8

DQM 0-3

BA0, BA1

A0-A9

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Timing Diagrams

Figure 46: WRITE – with Auto Precharge

Notes: 1. For this example, BL = 4.

2. Faster frequencies require two clocks (when tWR > tCK).

3. A8 and A9 = “Don’t Care.”

DON’T CARE

UNDEFINED

ENABLE AUTO PRECHARGE

tCH

tCL

tCK

tRP

tRAS

tRCD

tRC

CKE

CLK

A10

tCMH

tCMS

tAH

tAS

ROW

BANK BANK

ROW

BANK

tWR

tDH

tDS

m + 1 D

m + 2 D

m + 3

COMMAND

tCMH

tCMS

NOPNOP NOPACTIVE NOP WRITE NOP ACTIVE

tAH

tAS

tAH

tAS

tDH

tDS tDH

tDS

tCKH

tCKS

NOP NOP

COLUMN m

T0 T1 T2 T4T3 T5 T6 T7 T8 T9

BA0, BA1

DQM 0-3

A0-A9

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Timing Diagrams

Figure 47: Alternating Write Accesses

Notes: 1. For this example, BL = 4.

2. Faster frequencies require two clocks (when tWR > tCK).

3. A8 and A9 = “Don’t Care.”

DON’T CARE

CLK

m + 1 D

m + 2 D

m + 3

COMMAND

CMH

CMS

NOP NOP ACTIVE NOP WRITE NOP NOP ACTIVE

DS t

ACTIVE WRITE

b + 1 D

b + 3

DS t

ENABLE AUTO PRECHARGE

DQM /

DQML, DQMH

A0-A9

BA0, BA1

A10

CMH

CMS

ROW

ENABLE AUTO PRECHARGE

ROW

BANK 0 BANK 0 BANK 1 BANK 0

BANK 1

CKE

CKH

CKS

b + 2

COLUMN b

COLUMN m

tRP - BANK 0

RAS - BANK 0

RCD - BANK 0 t

RCD - BANK 0

WR - BANK 0

WR - BANK 1

RCD - BANK 1

RC - BANK 0

RRD

T0 T1 T2 T3 T4 T5 T6 T7 T8 T9

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Timing Diagrams

Figure 48: WRITE – Full-Page Burst

Notes: 1. A8 and A9 = “Don’t Care.”

2. tWR must be sati sf ied prior to PRECHARGE command.

3. Page left open; no tRP.

tCH

tCL tCK

tRCD

CKE

CLK

A10

tCMS

tAH

tAS

tAH

tAS

ROW

Full-page burst does

not self-terminate. Can

use BURST TERMINATE

command to stop.2, 3

()()

Full page completed

DON’T CARE

UNDEFINED

COMMAND

tCMH

tCMS

NOPNOP NOPACTIVE NOP WRITE BURST TERMNOP NOP

()()

tDH

tDS

m + 1 D

m + 2 D

m + 3

tDH

tDS tDH

tDS

m - 1

tDH

tDS

tAH

tAS

BANK

()()

BANK

tCMH

tCKH

tCKS

()()

256 locations within same row

COLUMN m

T0 T1 T2 T3 T4 T5 Tn + 1 Tn + 2 Tn + 3

BA0, BA1

DQM 0-3

A0-A9

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Timing Diagrams

Figure 49: WRITE – DQM Operation

Notes: 1. For this example, BL = 4.

2. A8 and A9 = “Don’t Care.”

DON’T CARE

UNDEFINED

tCH

tCL

tCK

tRCD

CKE

CLK

A10

tCMS

tAH

tAS

ROW

BANK

ROW

BANK

ENABLE AUTO PRECHARGE

m + 3

tDH

tDS

m + 2

tCMH

COMMAND NOPNOP NOPACTIVE NOP WRITE NOPNOP

tCMS tCMH

tDH

tDS

tDH

tDS

tAH

tAS

tAH

tAS

DISABLE AUTO PRECHARGE

tCKH

tCKS

COLUMN m

T0 T1 T2 T3 T4 T5 T6 T7

BA0, BA1

DQM 0-3

A0-A9

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Package Dimensions

Figure 50: 86-Pin Plastic TSOP II (400 mil)

Notes: 1. All dimensions are in millimeters.

2. Package width and length do not include mold protrusion; allowable mold protru sio n is

0.025mm per side.

3. “2X” means the notch is present in two locations (both ends of the device).

SEE DETAIL A

2X R 1.00

2X R 0.75

0.50

TYP

0.61

10.16 ±0.08

0.50 ±0.10

11.76 ±0.20

PIN #1 ID

DETAIL A

22.22 ±0.08

0.20 +0.07

-0.03

0.15 +0.03

-0.02

0.10 +0.10

-0.05

1.20 MAX 0.10

0.25

GAGE

PLANE

0.80

TYP

2X 0.10

2X 2.80

PLASTIC PACKAGE MATERIAL: EPOXY NOVOLAC

PLATED LEAD FINISH:

TG (90% Sn, 10% Pb) OR P (100% Sn) 0.01 ±0.005 THICK PER SIDE

PACKAGE WIDTH AND LENGTH DO NOT INCLUDE

MOLD PROTRUSION. ALLOWABLE PROTRUSION

IS 0.25 PER SIDE.

8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900

www.micron.com/productsupport Customer Comment Line: 800-932-4992

Micron, the M logo, and the Micron logo are trademarks of Micron Technology, Inc.

All other trademarks are the property of their respective owners.

This data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein. Although

considered final, these specifications are subject to change, as further product development and data characterization sometimes occur.

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Package Dimensions

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Figure 51: 90-Ball VFBGA (8mm x 13mm)

Notes: 1. All dimensions are in millimeters.

2. Package width and length do not include mold protrusion; allowable mold protru sio n is

0.025mm per side.

3. Recommended pad size for PCB is 0.33mm ±0.025mm.

4. Topside part marking decoder can be found at: www.micron.com/support/designsupport/

tools/fbga/decoder.

BALL A1 ID

1.00 MAX

MOLD COMPOUND: EPOXY NOVOLAC

SUBSTRATE MATERIAL: PLASTIC LAMINATE

SOLDER BALL MATERIAL: 62% Sn, 36% Pb, 2% Ag OR

96.5% Sn, 3%Ag, 0.5% Cu

SOLDER MASK DEFINED BALL PADS: Ø0.40

13.00 ±0.10

BALL A1

BALL A9 BALL A1 ID

0.80 TYP

6.50 ±0.05

8.00 ±0.10

4.00 ±0.053.20 ±0.05

5.60 ±0.05

0.65 ±0.05

SEATING PLANE

11.20 ±0.10

6.40

0.10 C

90X Ø0.45 ±0.05

SOLDER BALL DIAMETER

REFERS TO POST REFLOW

CONDITION. THE PRE-

REFLOW DIAMETER IS Ø0.42