
MAX9880A Evaluation Kit
Evaluates: MAX9880A
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The two top group boxes (Setup and Calibration)
represent the procedures for properly configuring the
ADC for performing DC voltage measurements. The first
time this window is opened, the Calibration and Voltage
Measurement group boxes are disabled. This is inten-
tional and ensures that the ADC gets properly configured
before the first DC measurement is taken. Refer to the
ADC section in the MAX9880A IC data sheet for detailed
steps for configuring the device.
The Setup group box contains a Clocking Mode group
box that provides radio buttons to determine how the
device should be set up. As there are specific device-
configuration requirements, the Autoconfigure Device
option is recommended, unless it is known that the cur-
rent device configuration meets the setup requirements.
The disabled labels are associated with the autoconfigu-
ration option and display the settings that are applied
once the Configure button is pressed.
Once the configuration is complete, the Offset group box
is activated, enabling the second step, offset calibration.
If the Use existing configuration (manual operation) is
selected, the Select current LRCLK Frequency drop-
down list is also activated; otherwise, it stays disabled.
Pressing the offset Calibrate button executes the proce-
dure listed in the Offset Calibration Procedure section of
the MAX9880A IC data sheet.
Once the offset calibration sequence is complete, the
Gain group box is activated, enabling the final step, gain
calibration. Pressing the gain Calibrate button executes
the procedure listed in the Gain Calibration Procedure
section of the MAX9880A IC data sheet. The result
(K) of the gain calibration is displayed below the gain
Calibrate button.
After the calibration sequences are completed, the
Voltage Measurement group box is activated and the
device is ready to perform DC measurements. Pressing
the Measure button executes the procedure listed in the
DC Measurement Procedure of the MAX9880A IC data
sheet. The result is displayed both as a voltage and a
16-bit hex value. Additional DC measurements are per-
formed by pressing the Measure button again.
Digital Microphone Input Register
Using the on-board digital microphones requires
both hardware and software configuration. See the
Microphone Inputs section for hardware configuration
options. For software configuration, select the DIG MIC
block on the Analog Audio tab. The digital microphone
clock is set by selecting one of the radio button options,
and the left/right digital microphone inputs are enabled
by checking the corresponding checkbox on the Digital
Microphone Input window. When using either of the dig-
ital microphone inputs, the left analog microphone input
is not available. Similarly, the left/right ADC input mixers
are disabled when the left/right digital microphones are
enabled.
Mode Register
The Mode register is used to configure slew speed
(DSLEW), volume-change smoothing (VSEN), line input
zero-crossing detection (ZDEN), and headphone ampli-
fier mode (HPMODE). The DSLEW, VSEN, and ZDEN
settings are configurable through the Left Line Output
Gain and Right Line Output Gain windows; addition-
ally, the ZDEN setting can be configured through the
Left MIC PGA and Right MIC PGA windows.
Headphone Modes (HPMODE)
The headphone amplifier mode is configured by select-
ing either of the headphone output amplifier blocks
and selecting one of the eight headphone amplifier
modes. Once a selection is made, the headphone image
changes to display the current headphone configuration.
Figure 16 shows images for two of the eight possible
headphone configurations, stereo capless and stereo
single-ended. The EV kit hardware should also be con-
figured to match the software-selected headphone con-
figuration (see the Headphone Outputs section).
Jack Detection
Jack detection is configured and monitored on the Jack
Detect/Jack Status window, which is accessed by
selecting the JACKSNS block on the Analog Audio tab.
This window provides access to both the Jack Detect
register (0x25) and the Jack Status register (0x01).
Also note that the JDET bit of the Status register (0x00)
is displayed in the Status group box at the top of the
main software window. See Table 11 for jack detect/jack
status controls.