XLH735048.000000X - INTEGRATED DEVICE TECHNOLOGY

Description

The Renesas XL devices (XO and VCXO options) are

ultra-precision crystal oscillators with 750 to 890fs typical phase

jitter over 12kHz to 20MHz bandwidth. Available in a wide

frequency range from 0.750MHz to 1350MHz, the XL series

crystal oscillators utilize a family of proprietary ASICs, with a key

focus on noise reduction technologies.

The 3rd order Delta Sigma Modulator reduces noise to the levels

that are comparable to traditional Bulk Quartz and SAW

oscillators. With short lead-time, low cost, low noise, wide

frequency range, excellent ambient performance, the XL devices

are an excellent choice over the conventional technologies. The

XL (XO option) devices have stabilities as tight as ±20ppm and

the XL (VCXO option) devices have ±50ppm APR. Either option

provides extremely quick delivery for both standard and custom

frequencies.

Features

▪Output types: LVDS, LVPECL, LVCMOS

▪Phase jitter (12kHz to 20MHz): 750fs to 890fs typical

▪Supply voltage: 2.5V or 3.3V

▪Package options:

•3.2 × 2.5 × 1.0 mm (not available for VCXO)

•5.0 × 3.2 × 1.2 mm

•7.0 × 5.0 × 1.3 mm

▪Operating temperature: -20°C to +70°C

•Frequency stability options: ±20, ±25, ±50, or ±100 ppm

(XO only)

•±50ppm APR (VCXO only)

▪Operating temperature: -40°C to +85°C

•Frequency stability options: ±25, ±50, or ±100 ppm

(XO only)

•±50ppm APR (VCXO only)

▪Operating temperature: -40°C to +105°C (XO only)

•Frequency stability options: ±50 or ±100 ppm

▪kV of 85ppm/volt typical from 0.5VDC to VDD (VCXO only)

•Better than ±10% linearity for Vc range

Pin Assignments (XO option)

NOTE: To minimize power supply line noise, a 0.01μF bypass capacitor should be placed between VDD (Pin 6) and GND (Pin 3) on 6-pin

devices, or VDD (Pin 4) and GND (Pin 2) on 4-pin devices.

Table 1. XO 6-pin Package Table 2. XO 4-pin Package

[a] Pulled high internally.

[b] Low = output disabled.

See Ordering Information (XO) for more details.

Number Name Description

1 E/D

Enable/Disable [a][b]

No connect

2 NC

E/D

No connect

Enable/Disable [a][b]

3 GND Connect to ground

4 OUT Output

5 OUT2 Complementary output

6 VDD Supply voltage

123

456

E/D / NC

NC / E/D

OUT

OUT2

VDD

GND

Number Name Description

1 E/D Enable/Disable [a][b]

2 GND Connect to ground

3 OUT Output

4 VDD Supply voltage

E/D

OUT

VDD

GND

Datasheet

XL Family of Low Phase Noise

Quartz-based PLL Oscillators

XL Datasheet

Pin Assignments (VCXO option)

NOTE: To minimize power supply line noise, a 0.01μF bypass capacitor should be placed between VDD (Pin 6) and GND (Pin 3).

Table 3. VCXO 6-pin Package

[a] Pulled high internally.

[b] Low = output disabled.

See Ordering Information (VCXO) for more details.

Number Name Description

1 Vc Voltage control

2 E/D Enable/Disable [a][b]

3 GND Connect to ground

4 OUT Output

5 OUT2 Complementary output (NC LVCMOS)

6 VDD Supply voltage

123

456

E/D

OUT

OUT2

VDD

GND

XL Datasheet

Contents

Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Pin Assignments (XO option) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Pin Assignments (VCXO option) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

ESD Compliance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Mechanical Testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Solder Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

AC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Output Waveforms – LVDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Output Waveforms – LVPECL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Output Waveforms – LVCMOS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Package Outline Drawings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Ordering Information (XO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Ordering Information (VCXO). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

XL Datasheet

Absolute Maximum Ratings

Stresses above the ratings listed below can cause permanent damage to the device. These ratings, which are standard values for

Renesas commercially rated parts, are stress ratings only. Functional operation of the device at these or any other conditions above

those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for

extended periods can affect product reliability. Electrical parameters are guaranteed only over the recommended operating temperature

range.

ESD Compliance

Mechanical Testing

Solder Reflow Profile

Table 4. Absolute Maximum Ratings

Item Rating

VDD -0.5 to +5.0V

E/D -0.5V to VDD + 0.5V

OUT -0.5V to VDD + 0.5V

Storage Temperature -55°C to 125°C

Maximum Junction Temperature 125°C

Core Current 65mA maximum

Theta JAJU6

7.0 × 5.0 × 1.3 mm

75.9 °C/W JS6

5.0 × 3.2 × 1.2 mm

89.6 °C/W JX6

3.2 × 2.5 × 1.0 mm

94.7 °C/W

Theta JB48.6°C/W 54.3 °C/W 66.8 °C/W

Table 5. ESD Compliance

Human Body Model (HBM 1000V

Machine Model (MM) 150V

Table 6. Mechanical Testing

Parameter Test Method

Mechanical Shock Drop from 75cm to hardwood surface–3 times.

Mechanical Vibration 10–55Hz, 1.5mm amplitude, 1 minute sweep; 2 hours each in 3 directions (X, Y, Z).

High Temperature Burn-in Under power at 125°C for 2000 hours.

Hermetic Seal He pressure: 4 ±1kgf/cm2 2 hour soak.

tP10 seconds Max within

5°C of 260°C peak

Ramp down not

to exceed 6°C/s

Ramp up 3°C/s Max

120 ±20 seconds

in pre-heating

area

50 ±10

seconds

above 225°C

reflow area

400 seconds MAX from +25°C to 260°C peak

25°C

160°C

180°C

225°C

260°C

XL Datasheet

DC Electrical Characteristics

Table 7. 3.3V IDD DC Electrical Characteristics

VDD = 3.3V ±5%, TA = -20°C to +70°C; -40°C to +85°C, -40°C to +105°C.

Symbol Parameter Output Type Conditions Minimum Typical Maximum Units

IDD Power Supply Current

LVDS

0.75MHz to 40MHz. — 32 37

40+MHz to 220MHz. — 40 47

220+MHz to 630MHz. — 49 57

630+MHz to 1350MHz. — 72 100

LVPECL[a]

[a] Without termination resistors.

0.75MHz to 40MHz. — 26 31

40+MHz to 220MHz. — 38 45

220+MHz to 630MHz. — 56 64

630+MHz to 1350MHz. — 96 120

LVCMOS

0.75MHz to 20MHz. — 27 32

20+MHz to 50MHz. — 32 35

50+MHz to 130MHz. — 43 47

130+MHz to 200MHz. — 48 55

200+MHz to 250MHz. — 48 60

Table 8. 2.5V IDD DC Electrical Characteristics

VDD = 2.5V ±5%, TA = -20°C to +70°C; -40°C to +85°C, -40°C to +105°C.

Symbol Parameter Output Type Conditions Minimum Typical Maximum Units

IDD Power Supply Current

LVDS

0.75MHz to 20MHz. — 24 26

20+MHz to 220MHz. — 29 34

220+MHz to 630MHz. — 36 44

630+MHz to 1000MHz. — 46 65

LVPECL[a]

[a] Without termination resistors.

0.75MHz to 20MHz. — 20 33

20+MHz to 220MHz. — 28 41

220+MHz to 630MHz. — 41 63

630+MHz to 1000MHz. — 56 72

LVCMOS

0.75MHz to 20MHz. — 17 22

20+MHz to 50MHz. — 23 25

50+MHz to 100MHz. — 28 29

100+MHz to 130MHz. — 30 32

130+MHz to 160MHz. — 32 35

160+MHz to 180MHz. — 33 37

XL Datasheet

Table 9. LVDS DC Electrical Characteristics

VDD = 3.3V, 2.5V ±5%, TA = -20°C to +70°C; -40°C to +85°C, -40°C to +105°C. Below are guaranteed for listed standard frequencies.

Symbol Parameter Conditions Minimum Typical Maximum Units

VOD Differential Output Voltage VDD = 3.3V ±5%. — — 0.6

VDD = 2.5V ±5%. — — 0.4

VOS Output Offset Voltage VDD = 3.3V ±5%. — — 1.3

VDD = 2.5V ±5%. — — 1.25

VIH

Enable/Disable Input High Voltage

(Output enabled) — 70% VDD — —

VIL

Enable/Disable Input Low Voltage

(Output disabled) — — — 30% VDD

Table 10. LVPECL DC Electrical Characteristics

VDD = 3.3V, 2.5V ±5%, TA = -20°C to +70°C; -40°C to +85°C, -40°C to +105°C. Below are guaranteed for listed standard frequencies.

Symbol Parameter Conditions Minimum Typical Maximum Units

VOD Differential Output Voltage VDD = 3.3V ±5%. 2.055 2.405

VDD = 2.5V ±5%. — 1.4 —

VOS Output Offset Voltage VDD = 3.3V ±5%. 1.305 1.65

VDD = 2.5V ±5%. — 0.68 —

VIH

Enable/Disable Input High Voltage

(Output enabled) — 70% VDD — —

VIL

Enable/Disable Input Low Voltage

(Output disabled) — — — 30% VDD

XL Datasheet

Table 11. LVCMOS DC Electrical Characteristics

VDD = 3.3V, 2.5V ±5%, TA = -20°C to +70°C; -40°C to +85°C, -40°C to +105°C. Below are guaranteed for listed standard frequencies.

Symbol Parameter Conditions Minimum Typical Maximum Units

VOH Output High Voltage

VDD = 3.3V ±5%. 0.75MHz to 150MHz. 90% VDD — —

150+MHz to 250MHz. 80% VDD — —

VDD = 2.5V ±5%. 0.75MHz to 160MHz. 90% VDD — —

160+MHz to 180MHz. 80% VDD — —

VOL Output Low Voltage

VDD = 3.3V ±5%. 0.75MHz to 150MHz. — — 10% VDD

150+MHz to 250MHz. — — 20% VDD

VDD = 2.5V ±5%. 0.75MHz to 160MHz. — — 10% VDD

160+MHz to 180MHz. — — 20% VDD

VIH

Enable/Disable Input High Voltage

(Output enabled) — — 70% VDD — —

VIL

Enable/Disable Input Low Voltage

(Output disabled) — — — — 30% VDD

XL Datasheet

AC Electrical Characteristics

Table 12. 3.3V AC Electrical Characteristics

VDD = 3.3V ±5%, TA = -20°C to +70°C; -40°C to +85°C, -40°C to +105°C.

Symbol Parameter Test Condition Minimum Typical Maximum Units

F Output Frequency Range

LVDS. 0.75 — 1350

MHzLVPECL. 0.75 — 1350

LVCMOS. 0.75 — 250

Frequency Stability

Temperature = -20°C to +70°C. ±20 — ±100 ppm

Temperature = -40°C to +85°C. ±25 — ±100 ppm

Temperature = -40°C to +105°C. ±50 — ±100 ppm

Aging (1st year) TA = 25°C. — — ±3 ppm

Aging (10 years) TA = 25°C. — — ±10 ppm

Output Load

LVDS. Differential. — 100 — Ω

LVPECL. VDD - 2.0V. — 50 —

LVCMOS. To GND. — 15 — pF

TST Start-up Time Output valid time after VDD meets minimum

specified level. — — 10 ms

tROutput Rise Time

LVDS. 20% to 80% Vpp. — — 400 ps

LVPECL. — — 400

LVCMOS. 10% to 90% VDD. — — 3 ns

tFOutput Fall Time

LVDS. 80% to 20% Vpp. — — 400 ps

LVPECL. — — 400

LVCMOS. 90% to 10% VDD. — — 3 ns

ODC Output Clock Duty Cycle

LVDS. 45 — 55

LVPECL. 45 — 55

LVCMOS. FOUT < 62.5MHz. 45 — 55

FOUT > 62.5MHz. 40 — 60

TOE Output Enable/ Disable Time — — — 100 ns

JPER Period Jitter, RMS

LVDS. — 3 —

psLVPECL. — 5.8 —

LVCMOS. FOUT = 125MHz. — 5 —

RJRandom Jitter

LVDS. — 1.3 —

psLVPECL. — 1.29 —

LVCMOS. FOUT = 125MHz. — 0.6 —

DJDeterministic Jitter

LVDS. — 5.8 —

psLVPECL. — 9.3 —

LVCMOS. FOUT = 125MHz. — 10 —

XL Datasheet

TJTotal Jitter

LVDS. — 23.6 —

psLVPECL. — 27.7 —

LVCMOS. FOUT = 125MHz. — 19 —

fJITTER Phase Jitter (12kHz–20MHz)

LVDS. — 890 —

fsLVPECL. — 860 —

LVCMOS. FOUT = 125MHz. — 750 —

Table 13. 2.5V AC Electrical Characteristics

VDD = 2.5V ±5%, TA = -20°C to +70°C; -40°C to +85°C, -40°C to +105°C.

Symbol Parameter Test Condition Minimum Typical Maximum Units

F Output Frequency Range

LVDS. 0.75 — 1000

MHzLVPECL. 0.75 — 1000

LVCMOS. 0.75 — 180

Frequency Stability

Temperature = -20°C to +70°C. ±20 — ±100 ppm

Temperature = -40°C to +85°C. ±25 — ±100 ppm

Temperature = -40°C to +105°C. ±50 — ±100 ppm

Aging (1st year) TA = 25°C. — — ±3 ppm

Aging (10 years) TA = 25°C. — — ±10 ppm

Output Load

LVDS. Differential. — 100 — Ω

LVPECL. VDD - 2.0V. — 50 —

LVCMOS. To GND. — 15 — pF

TST Start-up Time Output valid time after VDD meets minimum

specified level. — — 10 ms

tROutput Rise Time

LVDS. 20% to 80% Vpp. — — 400 ps

LVPECL. — — 400

LVCMOS. 10% to 90% VDD. — — 3.5 ns

tFOutput Fall Time

LVDS. 80% to 20% Vpp. — — 400 ps

LVPECL. — — 400

LVCMOS. 90% to 10% VDD. — — 3 ns

ODC Output Clock Duty Cycle

LVDS. 45 — 55

%LVPECL. 45 — 55

LVCMOS. 45 — 55

TOE Output Enable/ Disable Time — — — 100 ns

Table 12. 3.3V AC Electrical Characteristics (Cont.)

VDD = 3.3V ±5%, TA = -20°C to +70°C; -40°C to +85°C, -40°C to +105°C.

Symbol Parameter Test Condition Minimum Typical Maximum Units

XL Datasheet

Notes for all AC Electrical Characteristics tables:

1 All jitter values provided at 156.25MHz, unless noted otherwise.

JPER Period Jitter, RMS

LVDS. — 4 —

psLVPECL. — 5.12 —

LVCMOS. FOUT = 125MHz. — 3.3 —

RJRandom Jitter

LVDS. — 1.4 —

psLVPECL. — 1.36 —

LVCMOS. FOUT = 125MHz. — 1.3 —

DJDeterministic Jitter

LVDS. — 9.2 —

psLVPECL. — 10 —

LVCMOS. FOUT = 125MHz. — 6.7 —

TJTotal Jitter

LVDS. — 29.2 —

psLVPECL. — 29.3 —

LVCMOS. FOUT = 125MHz. — 25.6 —

fJITTER Phase Jitter (12kHz–20MHz)

LVDS. — 1040 —

fsLVPECL. — 1200 —

LVCMOS. FOUT = 125MHz. — 850 —

Table 13. 2.5V AC Electrical Characteristics (Cont.)

VDD = 2.5V ±5%, TA = -20°C to +70°C; -40°C to +85°C, -40°C to +105°C.

Symbol Parameter Test Condition Minimum Typical Maximum Units

XL Datasheet

Output Waveforms – LVDS

Output Waveforms – LVPECL

Oscillator Symmetry

Output Levels/Rise Time/Fall Time Measurements

OUTPUT 2

OUTPUT 1

OUTPUT 2

OUTPUT 1

50% VPP

VOH

VOL

VOD

½ Period

Period

TRTF

20% to 80% VPP

Ideally, Symmetry should be 50/50 for ½ period –Other expressions are 45/55 or 55/45

50% VPP VOS

Oscillator Symmetry

Rise Time/Fall Time Measurements

OUTPUT 2

OUTPUT 1

OUTPUT 2

OUTPUT 1

50% VPP

VOH

VOL

VOH

VOL

½ Period

Period

TRTF

20% to 80% VPP

XL Datasheet

Output Waveforms – LVCMOS

XL Datasheet

Package Outline Drawings

The package outline drawings are appended at the end of this document and are accessible from the links below. The package

information is the most current data available.

www.idt.com/document/psc/js6-package-outline-50-x-32-mm-body-11-mm-thick

www.idt.com/document/psc/jx6-package-outline-32-x-25-mm-body-09-mm-thick

www.idt.com/document/psc/ju6-package-outline-70-x-50-mm-body-13-mm-thick

www.idt.com/document/psc/js4-package-outline-50-x-32-mm-body-11-mm-thick

www.idt.com/document/psc/ju4-package-outline-70-x-50-mm-body-13-mm-thick

www.idt.com/document/psc/jx4-package-outline-32-x-25-mm-body-09-mm-thick

Ordering Information (XO)

FamilyandASIC

OutputType

Package

Voltage

P recis io n

125.000000

Frequency

TemperatureRange

I:

Industrialrange:‐40to+85°C

K:

Extendedi ndus tria lrange:‐40t o+105°C

X:

Extendedcommercialrange:‐20to+70°C

125.000000listedinMHzasexample

3digitsbeforedecimaland6digitsafterdecima l

000.750000to000.999999

75kHz to999.999kHz

001.000000to009.999999

1MHzto9.999999MHz

010.000000to099.999999

10 MHzto99.999999MH z

100.000000to999.999999

10 0MHzt o99 9.999999MHz

A00.000000toA99.999999

1000MHzto1099.999MHz

B00.000000toB99.999999

1100MHzto1199.999MHz

C00.000000toC99.999999

1200MHzto12 99.999MHz

D00.000000toD50.000000

1300MHzto13 50MHz

0:

±100ppm**

5:

±50ppm**

6:

±25ppm

8:

±20ppm*

2:

2.5VDC±5%

3:

3.3VDC±5%



3

:3.2x2.5mm

5:

5.0x3.2mm

7:

7.0x5.0mm

H:

LVCMOSEnable/DisablePin1(4‐pin)

J:

LVCMOSEnable/DisablePin2(6‐pin)

L:

LVDSEnable/DisablePin1(6‐pin)

M:

LVDSEnable/DisablePin2(6‐pin)

P:

LVPECLEnable/DisablePin1(6‐pin)

Q:

LVPECLEnable/DisablePin2(6‐pin)

X:

XLVCMOSCompHCMOSEnable/DisablePin1(6‐pin)

Y:

XLVCMOSCompHCMOSEnable/DisablePin2(6‐pin)

XL:

1,00 0fsjitter



*±20ppmforX(‐20°to+70°C)only.

** ±100ppman d±50ppmforK(‐40°Cto+10 5° C)onl y.

XL Datasheet

Ordering Information (VCXO)

Revision History

Revision Date Description of Change

October 27, 2020 Added pin counts to Output Type in XO ordering table.

September 21, 2020 Added typical IDD to tables. Added more frequency ranges to IDD tables. Updated H to be LVCMOS in order

code.

April 27, 2020 Updated ODC parameter. 2nd LVCMOS row to be changed from <= to > 62.5 MHz.

September 7, 2018 Updated frequency stability options value from ±20ppm to ±25ppm for -40°C to +85°C XO only.

June 25, 2018 ▪Updated Package Outline Drawings section.

May 4, 2018 ▪Added XO and VCXO options.

▪Updated description and Features sections.

▪Updated Package Outline Drawings section.

▪Added VCXO Ordering Information decoder diagram.

January 12, 2018 Initial release.

FamilyandASIC

OutputType

Package

Voltage V125.000000

Frequency

TemperatureRange

I:Industrialrange:‐40to+85°C

X:Extendedcommercialrange:‐20to+70°C

125.000000listedinMHzasexample

3digitsbeforedecimaland6digitsafterdecimal

000.750000to000.99999975kHzto999.999kHz

001.000000to009.9999991MHzto9.999999MHz

010.000000to099.99999910MHzto99.999999MHz

100.000000to999.999999100MHzto999.999999MHz

A00.000000toA99.9999991000MHzto1099.999MHz

B00.000000toB99.9999991100MHzto1199.999MHz

C00.000000toC99.9999991200MHzto1299.999MHz

D00.000000toD50.0000001300MHzto1350MHz

V:VCXOoption

2:2.5VDC±5%

3:3.3VDC±5%

5:5.0x3.2mm

7:7.0x5.0mm

H:LVCMOSEnable/Disable

L:LVDSEnable/Disable

P:LVPECLEnable/Disable

XL:1,000fsjitter



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(Rev.1.0 Mar 2020)