ABMP
ATM Buffer Manager
ABMP 2.1
Preliminary Data Sheet, DS 1.2, January 14, 2001
DATACOM
Never stop thinking.
Editio n 2001-14-01
Published by Infineon Technologies AG,
St.-Martin-Strasse 53 ,
D-8154 1 Münche n, Germany
© Infineon Technologies AG 1/14/01.
All Ri ghts Rese rved.
Attention ple as e!
The information herei n is given to describe certain components and shall not be con s idered as warranted
characteristics.
Terms of delivery an d rights to technical change reserved.
We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding
circuits, description s and charts stated herei n.
Infin eon Technol ogies is an appr oved CECC manu facturer.
Information
For further information on te chnology, delivery terms and con ditions and prices please contact your nearest
Infin eon Technol ogies Office in Germany or our Infi neon Techno logies Representa tives worldwide (see address
list).
Warnings
Due to technical requirements components may contain dangerous substances. Fo r inf ormation on the types in
question pl ease contact your nea rest Infi neon Technologies O ffice .
Infineon Technologies Components may only be used in life-support devices or systems with the express written
approval of Infineon T echnologies, if a failure of such components can reasonably be expected to cause the failure
of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support
devices or systems are in te nded to be implanted in the human body, or to support and/or maintain and sustain
and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may
be endangered.
DATACOM
PRELIMINARY
ABMP
ATM Buffer Manager
ABMP 2.1
Preliminary Data Sheet, DS 1.2, January 14, 2001
Never stop thinking.
•
For questions on technology, delivery and prices please contact the Infineon
Technologies Offices in Germany or the Infineon Technologies Companies and
Representatives worldwide: see our webpage at http://www.infineon.com
Disclaimer:
This Preliminary Document describes a product under development by Infineon Technologies AG (‘In-
fineon’). Infineon reserves the right to change features and characteristics of the product or discontinue
this product without notice. None of the information contained in this document constitutes an express
or implied assurance of availability or functionality. Please contact Infineon for latest information on the
product.
ABMP
PRELIMINARY
Revision History: 2001-14-01 DS 1.2
Previous Version: DS 1.1, 2000-03-10
Page Subjects (major changes since last revision)
From Data Sheet version 1.1 to 1.2, recognized typing errors have been
removed.
Prel. ABMP Data Sheet
Preliminary Data Sheet 5 2001-14-01
PRELIMINARY
1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
1.1.1 Queueing Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
1.1.2 Thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
1.1.3 Scheduling Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
1.1.4 Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
1.1.5 Supervision Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
1.1.6 Technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
1.2 Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
1.3 Typical Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
2 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
2.1 Pin Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
2.2 Pin Diagram with Functional Groupings . . . . . . . . . . . . . . . . . . . . . . . . . . 25
2.3 Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
2.3.1 Common System Clock Supply (6 pins) . . . . . . . . . . . . . . . . . . . . . . . . 26
2.3.2 Utopia Receive Interface Upstream (Master/Slave) (32 pins) . . . . . . . . 27
2.3.3 Utopia Transmit Interface Downstream (Master/Slave) (32 pins) . . . . . 29
2.3.4 Utopia Receive Interface Downstream (Master/Slave) (32 pins) . . . . . . 30
2.3.5 Utopia Transmit Interface Upstream (Master/Slave) (32 pins) . . . . . . . 31
2.3.6 Microprocessor Interface (32 pins) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
2.3.7 Cell Storage RAM Upstream (50 pins) . . . . . . . . . . . . . . . . . . . . . . . . . 35
2.3.8 Cell Storage RAM Downstream (50 pins) . . . . . . . . . . . . . . . . . . . . . . . 36
2.3.9 Common Up- and Downstream Cell Pointer RAM (42 pins) . . . . . . . . . 39
2.3.10 JTAG Boundary Scan (5 pins) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
2.3.11 SPI Interface (5 pins) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
2.3.12 QCI Interface (3 pins) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
2.3.13 Test (1 pin) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
2.3.14 Production Test (1 pin) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
2.3.15 Supply (74 VSS , 32 VDD33 and 14 VDD18 pins) . . . . . . . . . . . . . . . . 41
2.3.16 Un-Connected (13 pins) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
3 Functional Descr ipt i o n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
3.1 Block Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
3.2 Functional Block Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
3.2.1 Cell Handler (Upstream/Downstream) . . . . . . . . . . . . . . . . . . . . . . . . . . 46
3.2.2 Queue Manager and Scheduler Block (Overview) . . . . . . . . . . . . . . . . 46
3.2.3 Enhanced Rate Control (ERC) Unit (Overview) . . . . . . . . . . . . . . . . . . . 46
3.2.4 AAL5 Assistant . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
3.2.5 Internal Address Reduction Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
3.2.6 Queue Congestion Indication Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
3.2.7 Clocking System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
3.2.7.1 Clocking System Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
3.2.7.2 DPLL Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Prel. ABMP Data Sheet
Preliminary Data Sheet 6 2001-14-01
PRELIMINARY
3.2.7.3 Programming Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
3.2.7.4 Initialization Phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
3.2.8 Reset System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
3.3 System Integration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
3.3.1 LCI Translation in Mini-Switch Configurations . . . . . . . . . . . . . . . . . . . . 61
3.4 Detailed Queue Manager and Scheduler Block Description . . . . . . . . . . . 63
3.4.1 The Scheduler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
3.4.2 Scheduler Usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
3.4.3 Quality of Service Class Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
3.4.4 EPD/PPD Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
3.4.5 Threshold Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
3.4.6 Statistical Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
3.4.7 Supervision Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
3.4.7.1 Cell Header Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
3.4.7.2 Cell Queue Supervision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
3.4.8 DBA Threshold Indication Mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . 76
3.4.9 VC-Merge and Dummy Queue Description . . . . . . . . . . . . . . . . . . . . . . 77
3.4.9.1 VC-Merge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
3.4.9.2 Dummy Queue . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
3.5 Detailed ERC Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
3.5.1 ERC Unit Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
3.5.2 ERC Unit Functional Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
3.5.3 Explicit Rate Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
3.5.3.1 Rate Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
3.5.3.2 Other Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
3.5.4 Reactive Switch Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
3.5.5 VS/VD Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
3.5.6 ERC Mailbox . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
3.6 Internal Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
3.6.1 Table Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
3.6.2 LCI: Local Connection Identifier Table . . . . . . . . . . . . . . . . . . . . . . . . . . 91
3.6.3 QCT: Queue Configuration Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
3.6.4 TCT: Traffic Class Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
3.6.5 QPT: Queue Parameter Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
3.6.6 SOT: Scheduler Occupancy Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
3.6.7 SCTI: Scheduler Configuration Table (Integer) . . . . . . . . . . . . . . . . . . . 91
3.6.8 SCTF: Scheduler Configuration Table (Fractional) . . . . . . . . . . . . . . . . 92
3.6.9 MGT: Merge Group Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
3.6.10 AVT: ABR/VBR Configuration Table . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
3.6.10.1 AVT Context RAM Organization and Addressing . . . . . . . . . . . . . . . 93
3.6.10.2 AVT Context RAM Section for ABR-VS/VD Support . . . . . . . . . . . . . 94
3.6.10.3 AVT Context RAM Section for ABR-ER Support . . . . . . . . . . . . . . . . 95
3.6.10.4 AVT Context RAM Section for VBR Shaping Support . . . . . . . . . . . . 96
Prel. ABMP Data Sheet
Preliminary Data Sheet 7 2001-14-01
PRELIMINARY
3.6.10.5 Common AVT CONFIG Field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
3.6.11 QCIT: Congestion Indication Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
4 Operational Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
4.1 Basic Device Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
4.2 Basic Traffic Management Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . 100
4.2.1 Setup of Queues . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
4.2.2 ABM Configuration Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
4.2.3 Normal Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
4.2.4 Bandwidth Reservation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
4.2.5 Bandwidth Reservation Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
4.2.6 Programming of the Peak Rate Limiter / PCR Shaper . . . . . . . . . . . . 109
4.2.7 Scheduler Output Rate Calculation Example . . . . . . . . . . . . . . . . . . . 110
4.2.8 Empty Cell Rate Calculation Example . . . . . . . . . . . . . . . . . . . . . . . . . 111
4.2.9 Traffic Classes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
4.2.9.1 CBR Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
4.2.9.2 VBR-rt Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
4.2.9.3 VBR-nrt Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
4.2.9.4 ABR Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
4.2.9.5 UBR+ Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
4.2.9.6 GFR Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
4.2.9.7 UBR Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
4.2.9.8 Generic Service Classes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
4.3 Basic Enhanced Rate Control Initialization . . . . . . . . . . . . . . . . . . . . . . . 113
4.4 Connection Tear-Down Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
4.5 AAL5 Packet Insertion/Extraction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
4.6 Exception Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
5 Interface Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
5.1 UTOPIA L2 Interfaces (PHY-side) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
5.1.1 URXU: UTOPIA Receive Upstream (PHY side) . . . . . . . . . . . . . . . . . 115
5.1.2 UTXD: UTOPIA Transmit Downstream (PHY side) . . . . . . . . . . . . . . . 117
5.1.3 UTOPIA Port/Address Mapping (PHY side) . . . . . . . . . . . . . . . . . . . . 119
5.1.4 Functional UTOPIA Timing (PHY side) . . . . . . . . . . . . . . . . . . . . . . . . 120
5.1.5 UTOPIA Master Mode Polling Scheme (PHY side) . . . . . . . . . . . . . . . 121
5.1.6 UTOPIA Cell Format (PHY side) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
5.1.6.1 UTOPIA Level 2 Standard Cell Formats . . . . . . . . . . . . . . . . . . . . . 122
5.1.6.2 LCI Mapping Mode: VPI Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
5.1.6.3 LCI Mapping Mode: VCI Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
5.1.6.4 LCI Mapping Mode: Infineon Mode . . . . . . . . . . . . . . . . . . . . . . . . . 124
5.1.6.5 LCI Mapping Mode: Address Reduction Mode . . . . . . . . . . . . . . . . 124
5.2 UTOPIA L2 Interface (Backplane-side) . . . . . . . . . . . . . . . . . . . . . . . . . . 126
5.2.1 URXD: UTOPIA Receive Downstream (Backplane side) . . . . . . . . . . 126
5.2.2 UTXU: UTOPIA Transmit Upstream (Backplane side) . . . . . . . . . . . . 126
Prel. ABMP Data Sheet
Preliminary Data Sheet 8 2001-14-01
PRELIMINARY
5.2.3 UTOPIA Port/Address Mapping (Backplane side) . . . . . . . . . . . . . . . . 126
5.2.4 Functional UTOPIA Timing (Backplane side) . . . . . . . . . . . . . . . . . . . 126
5.2.5 UTOPIA Master Mode Polling Scheme (Backplane side) . . . . . . . . . . 126
5.2.6 UTOPIA Cell Format (Backplane side) . . . . . . . . . . . . . . . . . . . . . . . . 127
5.3 MPI: Microprocessor Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
5.3.1 Intel Style Write Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
5.3.2 Intel Style Read Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
5.3.3 Motorola style Write Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
5.3.4 Intel Style Read Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
5.3.5 Interrupt Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
5.4 External RAM Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
5.4.1 RAM Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
5.4.2 CSR: Cell Storage SDRAM Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . 133
5.4.3 CPR: Cell Pointer SSRAM Interface . . . . . . . . . . . . . . . . . . . . . . . . . . 134
5.5 SPI: Serial Pheripheral Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
5.5.1 SPI Read Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
5.5.2 SPI Write Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
5.6 QCI: Queue Congestion Indication Interface . . . . . . . . . . . . . . . . . . . . . . 135
5.7 Test Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
5.8 Clock and Reset Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
5.8.1 Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
5.8.2 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
6 Memory Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
7 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
7.1 Overview of the ABM Register Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
7.2 Detailed Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
8 Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 341
9 Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 342
10 Application Hints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 343
10.1 Backpressure Controlled Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . 343
10.2 AAL5-Processed Cell Insertion/Extraction . . . . . . . . . . . . . . . . . . . . . . . . 343
11 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 344
11.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 344
11.2 Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 344
11.3 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 345
11.4 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 347
11.4.1 Microprocessor Interface Timing Intel Mode . . . . . . . . . . . . . . . . . . . . 349
11.4.1.1 Microprocessor Write Cycle Timing (Intel) . . . . . . . . . . . . . . . . . . . . 349
11.4.1.2 Microprocessor Read Cycle Timing (Intel) . . . . . . . . . . . . . . . . . . . . 350
Prel. ABMP Data Sheet
Preliminary Data Sheet 9 2001-14-01
PRELIMINARY
11.4.2 Microprocessor Interface Timing Moto rola Mode . . . . . . . . . . . . . . . . 351
11.4.2.1 Microprocessor Write Cycle Timing (Motorola) . . . . . . . . . . . . . . . . 351
11.4.2.2 Microprocessor Read Cycle Timing (Motorola) . . . . . . . . . . . . . . . . 353
11.4.3 UTOPIA Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 355
11.4.4 CPR SSRAM Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 360
11.4.5 CSR SDRAM Interface(s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 361
11.4.6 Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 363
11.4.7 Boundary-Scan Test Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 364
11.4.8 SPI Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 366
11.4.9 Queue Congestion Interface (QCI) . . . . . . . . . . . . . . . . . . . . . . . . . . . 367
11.5 Capacitances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 368
11.6 Package Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 368
12 Testmode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 369
13 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 371
14 Appendix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 372
15 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 373
Prel. ABMP Data Sheet
Preliminary Data Sheet 10 2001-14-01
PRELIMINARY
Figure 1-1 Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 1-2 G eneral System Integration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 2-1 Pin Configuration (Bottom View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 2-2 Pin Configuration (Bottom View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 3-1 Sub-Sy stem Integration Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Figure 3-2 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Figure 3-3 Logical Block Diagram (One Direction) . . . . . . . . . . . . . . . . . . . . . . . . 45
Figure 3-4 LCI Building Patterns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Figure 3-5 LCI Building Patterns (cont.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Figure 3-6 LCI Building Patterns (VPI only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Figure 3-7 LCI Building Patterns (VPI only) (cont.) . . . . . . . . . . . . . . . . . . . . . . . . 53
Figure 3-8 Clocking System Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Figure 3-9 DPLL Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Figure 3-10 Reset System Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Figure 3-11 ABMP in Bi-directional Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Figure 3-12 ABMP in Uni-directional Mode Using both Cores . . . . . . . . . . . . . . . . 60
Figure 3-13 ABMP in Uni-directional Mode Using one Core. . . . . . . . . . . . . . . . . . 60
Figure 3-14 Connection Identifiers in Mini-Switch Configuration. . . . . . . . . . . . . . . 61
Figure 3-15 Cell Acceptance and Scheduling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Figure 3-16 Scheduler Structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Figure 3-17 Scheduler Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Figure 3-18 Data Traffic Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Figure 3-19 Scheduler Behavior Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Figure 3-20 Scheduler Usage at Switch Output . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Figure 3-21 Scheduler Usage at Switch Input. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Figure 3-22 Queue Grouping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Figure 3-23 Example of Threshold Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Figure 3-24 ERC Unit Sub-System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Figure 3-25 Example Network Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Figure 3-26 ABR Mechanisms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Figure 3-27 Example Beha vior of an Explicit Rate controlled ABR Connection . . . 82
Figure 3-28 RM and User Cell Sequence: General Case . . . . . . . . . . . . . . . . . . . . 84
Figure 3-29 RM and User Cell Sequence: worst Case . . . . . . . . . . . . . . . . . . . . . . 84
Figure 3-30 Capacity Usage of ABR VCs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Figure 3-31 VS/VD Cell Streams. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Figure 3-32 Distribution of VS/VD Function in a Switch . . . . . . . . . . . . . . . . . . . . . 88
Figure 3-33 Table Access Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Figure 3-34 Context RAM Addressing Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Figure 3-35 AVT Context Table: ABR-VS/VD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Figure 3-36 AVT Context Table: ABR-ER. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Figure 3-37 AVT Context Table: VBR Shaping. . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Figure 4-1 Parameters for Connection Setup (Bitfield width indicated). . . . . . . . 101
Figure 4-2 ABMP Application Example: DSLAM. . . . . . . . . . . . . . . . . . . . . . . . . 105
Prel. ABMP Data Sheet
Preliminary Data Sheet 11 2001-14-01
PRELIMINARY
Figure 5-1 UTOPIA Receive Upstream Master Mode. . . . . . . . . . . . . . . . . . . . . 115
Figure 5-2 UTOPIA Receive Upstream Slave Mode. . . . . . . . . . . . . . . . . . . . . . 116
Figure 5-3 UTOPIA Transmit Downstream Master Mode . . . . . . . . . . . . . . . . . . 117
Figure 5-4 UTOPIA Transmit Downstream Slave Mode . . . . . . . . . . . . . . . . . . . 118
Figure 5-5 Intel Style Write Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
Figure 5-6 Intel Style Read Access. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
Figure 5-7 Motorola Style Write Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
Figure 5-8 Motorola Style Read Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
Figure 5-9 CSR Interface and Connection Example. . . . . . . . . . . . . . . . . . . . . . 133
Figure 5-10 CPR Interface(s) and Connection Example. . . . . . . . . . . . . . . . . . . . 134
Figure 5-11 SPI Read Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
Figure 5-12 SPI Write Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
Figure 5-13 QCI Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
Figure 7-1 Table Access Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
Figure 11-1 Input/Output Waveform for AC Measurements . . . . . . . . . . . . . . . . . 347
Figure 11-2 Microprocessor Interface Write Cycle Timing (Intel) . . . . . . . . . . . . . 349
Figure 11-3 Microprocessor Interface Read Cycle Timing (Intel) . . . . . . . . . . . . . 350
Figure 11-4 Microprocessor Interface Write Cycle Timing (Motorola). . . . . . . . . . 351
Figure 11-5 Microprocessor Interface Read Cycle Timing (Motorola). . . . . . . . . . 353
Figure 11-6 Setup and Hold Time Definition (Single- and Multi-PHY). . . . . . . . . . 355
Figure 11-7 Tristate Timing (Multi-PHY, Multiple Devices Only). . . . . . . . . . . . . . 356
Figure 11-8 SSRAM Interface Generic Timing Diagram . . . . . . . . . . . . . . . . . . . . 360
Figure 11-9 Generic SDRAM Interface Timing Diagram. . . . . . . . . . . . . . . . . . . . 361
Figure 11-10 Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 363
Figure 11-11 Boundary-Scan Test Interface Timing Diagram. . . . . . . . . . . . . . . . . 364
Figure 11-12 SPI Interface Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 366
Figure 11-13 QCI Interface Timing Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 367
Figure 12-1 Block Diagram of Test Access Port and Boundary Scan Unit . . . . . . 369
Prel. ABMP Data Sheet
Preliminary Data Sheet 12 2001-14-01
PRELIMINARY
Table 2-1 Ball Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 3-1 Guaranteed Rates for each Traffic Class. . . . . . . . . . . . . . . . . . . . . . . 67
Table 3-2 Threshold Overview Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Table 3-3 ABR Support of ABM v1.1 vs. ABMP. . . . . . . . . . . . . . . . . . . . . . . . . . 80
Table 3-4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Table 3-5 In-rate and out-of-rate Cells . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Table 3-6 Bandwidth Efficiency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Table 3-7 Config(5:0) Bit Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Table 4-1 Number of Possible Connections per PHY . . . . . . . . . . . . . . . . . . . . 108
Table 4-2 Minimum Peak Rate Shaper Values . . . . . . . . . . . . . . . . . . . . . . . . . 109
Table 5-1 Port/Address Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Table 5-2 Port Polling Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
Table 5-3 Standardized UTOPIA Level 2 Cell Format (16-bit). . . . . . . . . . . . . . 122
Table 5-4 Standardized UTOPIA Level 2 Cell Format (16-bit): OAM Cells . . . . 122
Table 5-5 Standardized UTOPIA Level 2 Cell Format (16-bit): OAM Cells . . . . 123
Table 5-6 Standardized UTOPIA Level 2 Cell Format (16-bit): OAM Cells . . . . 123
Table 5-7 Standardized UTOPIA Level 2 Cell Format (16-bit): OAM Cells . . . . 124
Table 5-8 Standardized UTOPIA Level 2 Cell Format (16-bit): OAM Cells . . . . 124
Table 5-9 External RAM Sizes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
Table 5-10 Cell Pointer RAM Width . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
Table 5-11 SDRAM Configuration Examples. . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
Table 5-12 SSRAM and SDRAM Type Examples . . . . . . . . . . . . . . . . . . . . . . . . 132
Table 7-1 Color Convention for Internal Table Field Illustration. . . . . . . . . . . . . 141
Table 7-2 ABM Registers Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
Table 7-3 External RAM Sizes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
Table 7-5 WAR Register Mapping for DTC Table access . . . . . . . . . . . . . . . . 196
Table 7-4 Registers DTC Upstream/Downstream Table Access. . . . . . . . . . . . 196
Table 7-7 WAR Register Mapping for LCI Table Access . . . . . . . . . . . . . . . . . 199
Table 7-6 Registers for LCI Table Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
Table 7-9 WAR Register Mapping for TCT Table Access . . . . . . . . . . . . . . . . 203
Table 7-8 Registers for TCT Table Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
Table 7-10 Registers for Queue Configuration Table Access . . . . . . . . . . . . . . . 219
Table 7-11 WAR Register Mapping for LCI Table Access . . . . . . . . . . . . . . . . . 220
Table 7-12 Registers for SOT Table Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230
Table 7-13 WAR Register Mapping for SOT Table Access . . . . . . . . . . . . . . . . 231
Table 7-14 Registers for MGT Table Access. . . . . . . . . . . . . . . . . . . . . . . . . . . . 235
Table 7-15 WAR Register Mapping for MGT Table Access . . . . . . . . . . . . . . . . 236
Table 7-17 WAR Register Mapping for DTC Table access . . . . . . . . . . . . . . . . 243
Table 7-16 Registers QCIT Table Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243
Table 7-18 Registers for QPT1 Upstream Table Access. . . . . . . . . . . . . . . . . . . 253
Table 7-19 Registers for QPT1 Downstream Table Access . . . . . . . . . . . . . . . . 253
Table 7-20 WAR Register Mapping for QPT Table Access . . . . . . . . . . . . . . . . 254
Table 7-21 Registers for QPT2 Upstream Table Access. . . . . . . . . . . . . . . . . . . 257
Prel. ABMP Data Sheet
Preliminary Data Sheet 13 2001-14-01
PRELIMINARY
Table 7-22 Registers for QPT2 Downstream Table Access . . . . . . . . . . . . . . . . 257
Table 7-23 WAR Register Mapping for QPT Table Access . . . . . . . . . . . . . . . . 258
Table 7-24 Registers SCTI Upstream Table Access . . . . . . . . . . . . . . . . . . . . . . 262
Table 7-25 Registers SCTI Downstream Table Access. . . . . . . . . . . . . . . . . . . . 262
Table 7-26 Registers SCTF Upstream Table Access . . . . . . . . . . . . . . . . . . . . . 274
Table 7-27 Registers SCTF Downstream Table Access . . . . . . . . . . . . . . . . . . . 274
Table 7-28 WAR Register Mapping for SCTFU/SCTFD Table access . . . . . . . 275
Table 7-29 Registers for AVT Table Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285
Table 7-30 WAR Register Mapping for AVT Table Access . . . . . . . . . . . . . . . . 286
Table 11-1 Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 344
Table 11-2 Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 344
Table 11-3 DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 345
Table 11-4 Clock Frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 348
Table 11-5 Microprocessor Interface Write Cy cle Timing (Intel) . . . . . . . . . . . . . 349
Table 11-6 Microprocessor Interface Read Cycle Timing (Intel) . . . . . . . . . . . . . 350
Table 11-7 Microprocessor Interface Write Cycle Timing (Motorola). . . . . . . . . . 351
Table 11-8 Microprocessor Interface Read Cycle Timing (Motorola). . . . . . . . . . 353
Table 11-9 Transmit Timing (16-Bit Data Bus, 50 MHz at Cell Interface, Single
PHY) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 356
Table 11-10 Receive Timing (16-Bit Data Bus, 50 MHz at Cell Interface, Single
PHY) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 357
Table 11-11 Transmit Timing (16-Bit Data Bus, 50 MHz at Cell Interface,
Multi-PHY) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 358
Table 11-12 Receive Timing (16-Bit Data Bus, 50 MHz at Cell Interface,
Multi-PHY) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 359
Table 11-13 SSRAM Interface AC Timing Characteristics . . . . . . . . . . . . . . . . . . 360
Table 11-14 SDRAM Interface AC Timing Characteristics . . . . . . . . . . . . . . . . . . 361
Table 11-15 Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 363
Table 11-16 Boundary-Scan Test Interface AC Timing Characteristics . . . . . . . . 364
Table 11-17 SPI Interface AC Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . 366
Table 11-18 QCI Interface AC Timing Characteristics . . . . . . . . . . . . . . . . . . . . . 367
Table 11-20 Thermal Package Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 368
Table 11-19 Capacitances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 368
Prel. ABMP Data Sheet
List of Registers Page
Preliminary Data Sheet 14 2001-14-01
Register 1 UCFTST/DCFTST............................................................................... 152
Register 2 URCFG/DRCFG ................................................................................. 154
Register 3 UA5TXHD0/DA5TXHD0 ..................................................................... 155
Register 4 UA5TXHD1/DA5TXHD1 ..................................................................... 156
Register 5 UA5TXDAT0/DA5TXDAT0 ................................................................. 158
Register 6 UA5TXDAT1/DA5TXDAT1 ................................................................. 159
Register 7 UA5TXTR/DA5TXTR .......................................................................... 160
Register 8 UA5TXCMD/DA5TXCMD ................................................................... 161
Register 9 UA5RXHD0/DA5RXHD0..................................................................... 162
Register 10 UA5RXHD1/DA5RXHD1..................................................................... 164
Register 11 UA5RXDAT0/DA5RXDAT0................................................................. 165
Register 12 UA5RXDAT1/DA5RXDAT1................................................................. 166
Register 13 UA5SARS/DA5SARS ......................................................................... 167
Register 14 UBOC/DBOC ...................................................................................... 170
Register 15 UNGBOC/DN GBOC ........................................................................... 171
Register 16 UBMTH/DBMTH ................................................................................. 172
Register 17 UMAC/DMAC...................................................................................... 174
Register 18 UMIC/DMIC......................................................................................... 175
Register 19 CLP1DIS............................................................................................. 176
Register 20 CONFIG.............................................................................................. 177
Register 21 UUBPTH0 ........................................................................................... 178
Register 22 UUBPTH1 ........................................................................................... 179
Register 23 UUBPTH2 ........................................................................................... 180
Register 24 UUBPTH3 ........................................................................................... 181
Register 25 UBPEI ................................................................................................. 182
Register 26 DUBPTH0 ........................................................................................... 183
Register 27 DUBPTH1 ........................................................................................... 184
Register 28 DUBPTH2 ........................................................................................... 185
Register 29 DUBPTH3 ........................................................................................... 186
Register 30 DQCIC ................................................................................................ 187
Register 31 DSBT1 ................................................................................................ 189
Register 32 DSBT2 ................................................................................................ 191
Register 33 DSBT3 ................................................................................................ 192
Register 34 DSBT4 ................................................................................................ 194
Register 35 DTCT .................................................................................................. 197
Register 36 LCI0 .................................................................................................... 200
Register 37 LCI1 .................................................................................................... 201
Register 38 LCI2 .................................................................................................... 202
Register 39 TCT0................................................................................................... 206
Register 40 TCT1................................................................................................... 208
Register 41 TCT2................................................................................................... 211
Register 42 TCT3................................................................................................... 213
Register 43 QCT0 .................................................................................................. 220
Register 44 QCT1 .................................................................................................. 221
Register 45 QCT2 .................................................................................................. 224
Register 46 QCT3 .................................................................................................. 226
Register 47 QCT4 .................................................................................................. 228
Register 48 QCT5 .................................................................................................. 228
Register 49 QCT6 .................................................................................................. 229
Register 50 SOT0................................................................................................... 231
Register 51 SOT1................................................................................................... 232
Prel. ABMP Data Sheet
Preliminary Data Sheet 15 2001-14-01
PRELIMINARY
Register 52 SOT2................................................................................................... 232
Register 53 SOT3................................................................................................... 233
Register 54 SOT4................................................................................................... 234
Register 55 MGT0.................................................................................................. 236
Register 56 MGT1.................................................................................................. 237
Register 57 MGT2.................................................................................................. 237
Register 58 MASK0/MASK1................................................................................... 238
Register 59 MASK2/MASK3................................................................................... 239
Register 60 MASK4/MASK5................................................................................... 240
Register 61 MASK6................................................................................................ 241
Register 62 QCIT ................................................................................................... 244
Register 63 UCDV/DC DV....................................................................................... 245
Register 64 UQPTM0/DQPTM0............................................................................. 246
Register 65 UQPTM1/DQPTM1............................................................................. 247
Register 66 UQPTM2/DQPTM2............................................................................. 248
Register 67 UQPTM3/DQPTM3............................................................................. 249
Register 68 UQPTM4/DQPTM4............................................................................. 250
Register 69 UQPTM5/DQPTM5............................................................................. 251
Register 70 USCONF/D SCONF............................................................................. 252
Register 71 UQPT1T0/DQPT1T0........................................................................... 255
Register 72 UQPT1T1/DQPT1T1........................................................................... 256
Register 73 UQPT2T0/DQPT2T0........................................................................... 259
Register 74 UQPT2T1/DQPT2T1........................................................................... 259
Register 75 UQPT2T2/DQPT2T2........................................................................... 260
Register 76 UQPT2T3/DQPT2T3........................................................................... 261
Register 77 USADR/DSADR.................................................................................. 263
Register 78 USCTI/DSCTI ..................................................................................... 264
Register 79 UECRI/DECRI..................................................................................... 267
Register 80 UECRF/DECRF.................................................................................. 270
Register 81 UCRTQ/DCRTQ ................................................................................. 272
Register 82 USCTFM/DSCTFM............................................................................. 272
Register 83 USCTFT/DSCTFT............................................................................... 275
Register 84 USCEN0 /DSCEN0.............................................................................. 277
Register 85 USCEN1 /DSCEN1.............................................................................. 277
Register 86 USCEN2 /DSCEN2.............................................................................. 278
Register 87 USCEN3 /DSCEN3.............................................................................. 279
Register 88 USCEN4 /DSCEN4.............................................................................. 279
Register 89 USCEN5 /DSCEN5.............................................................................. 280
Register 90 USCEN6 /DSCEN6.............................................................................. 281
Register 91 USCEN7 /DSCEN7.............................................................................. 281
Register 92 UCRTRI/DCRTRI................................................................................ 282
Register 93 UCRTRF/DCRTRF ............................................................................. 283
Register 94 ERCT0 ................................................................................................ 286
Register 95 ERCT1 ................................................................................................ 287
Register 96 ERCM0 ............................................................................................... 288
Register 97 ERCM1 ............................................................................................... 289
Register 98 ERCMB0............................................................................................. 290
Register 99 ERCMB1............................................................................................. 291
Register 100 ERCMB2............................................................................................. 292
Register 101 ERCC ONF0 ........................................................................................ 293
Register 102 ERCC ONF1 ........................................................................................ 294
Register 103 PLL1CONF ......................................................................................... 296
Prel. ABMP Data Sheet
Preliminary Data Sheet 16 2001-14-01
PRELIMINARY
Register 104 PLL2CONF ......................................................................................... 298
Register 105 PLLTST............................................................................................... 300
Register 106 ERCR AC............................................................................................. 301
Register 107 ERCR AM ............................................................................................ 303
Register 108 VERL................................................................................................... 304
Register 109 VERH.................................................................................................. 304
Register 110 ISRU ................................................................................................... 305
Register 111 ISRD ................................................................................................... 308
Register 112 ISRC ................................................................................................... 311
Register 113 IMRU................................................................................................... 312
Register 114 IMRD................................................................................................... 313
Register 115 IMRC................................................................................................... 314
Register 116 ISRDBA............................................................................................... 315
Register 117 IMRDBA.............................................................................................. 316
Register 118 MAR.................................................................................................... 317
Register 119 WAR.................................................................................................... 319
Register 120 STATU S.............................................................................................. 320
Register 121 MODE1 ............................................................................................... 321
Register 122 MODE2 ............................................................................................... 325
Register 123 UTRXCFG........................................................................................... 327
Register 124 UUTRXP0 ........................................................................................... 329
Register 125 UUTRXP1 ........................................................................................... 329
Register 126 UUTRXP2 ........................................................................................... 330
Register 127 DUTRXP0 ........................................................................................... 331
Register 128 DUTRXP1 ........................................................................................... 331
Register 129 DUTRXP2 ........................................................................................... 332
Register 130 UUTTXCF G ........................................................................................ 333
Register 131 DUTTXCF G ........................................................................................ 334
Register 132 UUTTXP0............................................................................................ 336
Register 133 UUTTXP1............................................................................................ 336
Register 134 UUTTXP2............................................................................................ 337
Register 135 DUTRXP0 ........................................................................................... 338
Register 136 DUTTXP1............................................................................................ 338
Register 137 DUTTXP2............................................................................................ 339
Register 138 TEST................................................................................................... 340
Prel. ABMP Data Sheet
Preliminary Data Sheet 17 2001-14-01
PRELIMINARY
Preface
The purpose of this Preliminary Data Sheet is to provide comprehensive information
about the ABMP device covering system level integration, hardware/board design and
software driver aspects.
Organization of this Document
This Preliminary Data Sheet is divided into 13 chapters and two appendices. It is
organized as follows:
•Chapter 1, Overview
Gives a general description of the product and its family, lists the key features, and
presents some typical applications.
•Chapter 2, Pin Descriptions
Lists pin locations with associated signals, categorizes signals according to function,
and describes signals.
•Chapter 3, Functional Description
Gives a description of major function blocks, configuration tables and global device
functions.
•Chapter 4, Operational De scription
Describes basic initialization and operation procedures.
•Chapter 5, Interface Description
Gives a functional description of all interfaces.
•Chapter 6, Memory Structure
•Chapter 7, Register Description
Lists all registers and tables with functional description.
•Chapter 8, Programming
•Chapter 9, Timing Diagrams
•Chapter 10, Application Hints
•Chapter 11, Electrical Characteristics
Provides detailed information about electrical characteristics and interface timings.
Prel. ABMP Data Sheet
Preliminary Data Sheet 18 2001-14-01
PRELIMINARY
•Chapter 12, Testmode
•Chapter 13, Package Outlines
Related Documentat ion
• ITU-T Recommendation I.371 “Traffic Control and Congestion Control in B-ISDN” 2nd
Release, March 1996
• ATMF “Traffic Management Specification 4.1”, March 1999
• ATMF “UTOPIA Level 1 Specification Version 2.01”, March 1994
• ATMF “UTOPIA Level 2 Specification Version 1”, June 1995
Your Comment s
We welcome your comments on this document. We are continuously trying improving
our documentation. Please send your remarks and suggestions by e-mail to
sc.docu_comments@infineon.com
Please provide in the
subject
of your e-mail:
device name (ABMP), device part number (x), device version (x),
and in the
body
of your e-mail:
document type (Preliminary Data Sheet), issue date (2001-14-01) and document
revision number (DS 1.2).
Preliminary Data Sheet 19 2001-14-01
Type Package
ABMP BGA-456
ATM Buffer Manager
ABMP ABMP
2.1
PRELIMINARY
•
1Overview
The ABM PXB 4330 Traffic Management Device is well
accepted in a variety of applications where extensive
ATM Traffic Management capabilities are required in
either distributed or centralized system architectures of
Enterprise and CO Switches, DSLAMs and ATM Line
Cards for Routers and Swi tches. The second gener ation
ABMP targets the next generation of Multi-Service
platforms with combined ATM cell and packet handling
requirements. The new Enhanced Rate Control (ERC)
unit provides a powerful mecha nism to achieve maxi mum link utili zation by rate adap tive
schemes like ABR-ER, ABR-VS/VD and RSC. Optional per queue Dual Leaky Bucket
scheduling completes the shaping functions with full VBR support. Special features are
implemented to allow performance optimized interworking of ATM and higher layer traffic
management and flow control schemes.
1.1 Features
• ATM Traffic Management processing up to STM-4/OC-12 equivalent bandwidth
• Throughput up to 688 Mbit/s, bi-directional
• Speed-up factor at switching fabric receive interface 1.27
• Uni-directional mode with combined resources of both directions (optional)
• 256k cells buffer per direction (configurable in guaranteed and shared buffer)
• Up to 16384 connections arbitrary assignable to queues
• Up to 8192 queues pe r di re ct ion , individually assignable to schedul er s and to ser vice
classes
• FIFO queuing within each queue
• Up to 128 schedulers per direction with programmable service rates, individually
assignable t o PHYs (up to 512 schedu lers per dir ection by cascadin g four ABM chips)
• Up to 16 traffic classes with individually selectable thresholds for service classes
• Up to 48 PHYs (Ports per UTOPIA interface)
Prel. ABMP Data Sheet
Overview
Preliminary Data Sheet 20 2001-14-01
PRELIMINARY
• Traffic Classes:
UBR, UBR+, CBR, VBR-rt, VBR-nrt, GFR, ABR (relative marking, ER, VS/VD, RSC),
PHB (traffic class settings are not pre-defined; generic PHB characteristics can be
configured)
• Configurable cell address translation modi
1.1.1 Queueing Functions
• Common high-priority real-time bypass for both directions
• High-priority real-time bypass per scheduler
• Per-VC queueing for up to 8192 connections per direction
• Weighted fair queuing with 15,360 weight factors programmable for each queue
• Optional PCR shaping selectable for each queue with minimum rate 100 cells/s
(63,488 programmable rates)
• Optional VBR shaping selectable for up to 2046 queues
• Guaranteed per queue buffer reservation
• Subset of cell acceptance thresholds with hysteresis evaluation
• EPD/PPD thresholds for GFR support
1.1.2 Thresholds
• Cell acceptance based on threshold sets
• Threshold sets for individual queues, traffic classes, schedulers and global buffer
• PPD discard thresholds
• EPD discard thresholds
• CLP discard thresholds
• EFCI and CI/NI thresholds
• Head-of-line blocking free UTOPIA port backpressure thresholds
• Per queue congestion indication/avoidance thresholds
1.1.3 Scheduling Functions
• Two stage scheduler units with 2 Round Robbin and 1 WFQ scheduler connected to
a second stage priority scheduler
• VC/VP merge function for up to 128 merge groups (arbitrary queues per merge group)
• Dual-Leaky-Bucket shaping (queue associated function; allows shaping on
aggregated connections, e.g. UBR bundles)
1.1.4 Interfaces
• Two external SDRAM Interfaces for cell storage, one for upstream and one for
downstream direction (up to 256k cell buffer per direction)
• One common cell pointer SSRAM Interface
Prel. ABMP Data Sheet
Overview
Preliminary Data Sheet 21 2001-14-01
PRELIMINARY
• Multipor t UTOPIA Level 2 Interface in u p- and downstr eam direction according to The
ATM Forum, UTOPIA Level 1 and 2 specifications []
• 4-cell FIFO buffer at UTOPIA receive interfaces for clock synchronization
(Head-of-line blocking free)
• 96-cell buffer logical queueing for up to 48 PHYs at UTOPIA transmit interfaces
(Head-of-line blocking free)
• 16-bit Microprocessor Interface, configurable as Intel or Motorola type (with AAL5
packet insertion/extraction support)
• Queue Congestion Indication interface
• Boundary Scan Interface according to JTAG []
1.1.5 Supervision Functions
• Internal pointer supervision
• Cell header protection function
1.1.6 Technology
• Supply voltages 1.8V (core) and 3.3V (I/Os)
• Ball Grid Array BGA-456 package (Power BGA 35sqmm)
• Tempe rat ure ran ge -40°C to 85°C
• Power dissipation 2.0 W (typical)
Prel. ABMP Data Sheet
Overview
Preliminary Data Sheet 22 2001-14-01
PRELIMINARY
1.2 Logic Symbol
•
Figure 1-1 L ogic Symbol
Cell Pointer
RAM
SSRAM
Interface
Upstream Cell
Storage RAM
SDRAM
Interface
UTOPIA L2
Interface
(PHY Side)
UTOPIA L2
Interface
(Backplane Side)
16 Bit uP
Interface Bus
Optional
Code ROM
PXB 4330
ABMP
Downstream Cell
Storage RAM
SDRAM I n t er fac e
Test/ JTAG/
Clocking IF
Queue Congestion
Ind ica ti on I n t er fa ce
Prel. ABMP Data Sheet
Overview
Preliminary Data Sheet 23 2001-14-01
PRELIMINARY
1.3 Typical Applications
Traffic Management on Line and Trunk cards for
• ATM Switches
• DSLAMs, DLCs
• Multi Service Access Switches
• 3G Wireless Infrastructure Switches
•
Figure 1-2 General System Integration
Prel. ABMP Data Sheet
Pin Descriptions
Preliminary Data Sheet 24 2001-14-01
PRELIMINARY
2 Pin De scriptions
2.1 Pin Diagram
•
Figure 2-1 Pin Configuration (Bottom View)
URX
PRTYU URX
CLKU
URX
DATU
0
URX
DATU
2
URX
DATU
4
URX
DATU
8
URX
DATU
12 VDD18 CPR
ADR
18
CPR
ADR
14
CPR
ADR
10
CPR
ADR
7
CPR
ADR
2
CPR
DAT
18
CPR
DAT
13
CPR
DAT
10
CPR
DAT
5
CPR
DAT
2
UTX
DATD
15
UTX
DATD
11 NC UTX
DATD
4
UTX
DATD
1NC UTX
CLKD UTX
CLAV2
URX
ENBU
1
URX
ENBU
2
URX
DATU
1
URX
DATU
3
URX
DATU
5
URX
DATU
9
URX
DATU
13
CPR
OE
CPR
ADR
17
CPR
ADR
13
CPR
ADR
9
CPR
ADR
6
CPR
ADR
1
CPR
DAT
19
CPR
DAT
14
CPR
DAT
11
CPR
DAT
6NC VDD18 UTX
DATD
12
UTX
DATD
8
UTX
DATD
5
UTX
DATD
2
UTX
DATD
0
UTX
PRTYD UTX
CLAV1
URX
ENBU
3
URX
ADRU
0
URX
ENBU
0NC URX
DATU
6
URX
DATU
10
URX
DATU
14
CPR
GW
CPR
ADR
16
CPR
ADR
12
CPR
ADR
8
CPR
ADR
5
CPR
ADR
0VDD18 CPR
DAT
15
CPR
DAT
12
CPR
DAT
7
CPR
DAT
3
CPR
DAT
0
UTX
DATD
13
UTX
DATD
9
UTX
DATD
6
UTX
DATD
3
UTX
SOCD
UTX
ADRD
4
UTX
CLAV0
URX
ADRU
1
URX
ADRU
2
URX
ADRU
3
URX
SOCU
URX
DATU
7
URX
DATU
11
URX
DATU
15
CPR
ADSC
CPR
ADR
15
CPR
ADR
11 NC CPR
ADR
4
CPR
ADR
3
CPR
DAT
17
CPR
DAT
16
CPR
DAT
9
CPR
DAT
8
CPR
DAT
4
CPR
DAT
1
UTX
DATD
14
UTX
DATD
10
UTX
DATD
7
UTX
CLAV3
UTX
ADRD
1
UTX
ADRD
2
UTX
ADRD
3
URX
ADRU
4VDD18 URX
CLAVU
0
URX
CLAVU
1
URX
CLAVU
2
URX
CLAVU
3
CSR
WEU CSR
CASU
CSR
RASU CSR
CSU
CSR
ADRU
0
CSR
ADRU
2
CSR
ADRU
3
CSR
ADRU
4
CSR
ADRU
5
CSR
ADRU
6
CSR
ADRU
7
CSR
ADRU
8
CSR
ADRU
9
CSR
ADRU
10
CSR
ADRU
11
CSR
BAU
1
CSR
BAU
0
CSR
DATU
1
CSR
DATU
2
CSR
DATU
3
CSR
DATU
0
VDD18 CSR
DATU
4
CSR
DATU
5
CSR
DATU
6
CSR
DATU
8
CSR
DATU
9
CSR
DATU
10
CSR
DATU
7
CSR
DATU
13
CSR
DATU
12
CSR
DATU
11
CSR
DATU
14
CSR
DATU
18
CSR
DATU
17
CSR
DATU
15
CSR
DATU
16
CSR
DATU
21
CSR
DATU
20
CSR
DATU
19
CSR
DATU
22
CSR
DATU
26
CSR
DATU
25
CSR
DATU
24
CSR
DATU
23
CSR
DATU
29
CSR
DATU
28 VDD18 CSR
DATU
27
SPI
SI
ERC
RAM
SEL
CSR
DATU
31
CSR
DATU
30
TST
ERC
CLK
SPI
CS SPI
CLK SPI
SO
TDI TRST EXT
FREEZE RAM
CLK
UTX
ENBU
0TDO TMS TCK
UTX
ENBU
3
UTX
ENBU
2
UTX
ENBU
1
UTX
ADRU
4
UTX
DATU
2
UTX
DATU
6
UTX
DATU
14
MP
MODE
VDD18
PLL VSS
PLL MP
ADR2 VDD18 MP
DAT1 MP
DAT2 MP
DAT6 MP
DAT9 MP
DAT13
URX
DATD
1
URX
DATD
4NC URX
CLAVD
2
URX
CLAVD
1
URX
CLAVD
0
UTX
ADRU
1
UTX
ADRU
0
UTX
PRTYU
UTX
DATU
5
UTX
DATU
9
UTX
DATU
13
UTX
DATU
10
VSS
PLL
SYS
CLK
SEL
SYS
CLK MP
ADR3 MP
ADR6 MP
DAT3 MP
DAT7 MP
DAT10 MP
DAT14 VDD18 URX
DATD
5
URX
DATD
8
URX
DATD
15 NC URX
PRTYD
UTX
ADRU
2
UTX
CLAVU
0
UTX
CLAVU
3
UTX
SOCU
UTX
DATU
0
UTX
DATU
4
UTX
DATU
8
UTX
DATU
12
UTX
DATU
1
MP
INT MP
RD
ERC
CLK RESET MP
ADR0 MP
ADR4 MP
ADR7 MP
DAT4 MP
DAT8 MP
DAT11 MP
DAT15
URX
DATD
2
URX
DATD
6
URX
DATD
9
URX
DATD
11
URX
CLKD URX
SOCD
UTX
CLAVU
1
UTX
CLAVU
2VDD18 UTX
CLKU
UTX
DATU
3
UTX
DATU
7
UTX
DATU
11
UTX
DATU
15
MP
CS MP
WR
ERC
CLK
SEL
VDD18
PLL MP
ADR1 MP
ADR5 MP
DAT0 MP
DAT5 NC MP
DAT12
URX
DATD
0
URX
DATD
3
URX
DATD
7
URX
DATD
10
URX
DATD
12
URX
DATD
13
URX
DATD
14
UTX
ENBD
2
UTX
ENBD
3VDD18 UTX
ADRD
0
CSR
DATD
30
CSR
DATD
31
UTX
ENBD
0
UTX
ENBD
1
CSR
DATD
26
CSR
DATD
27
CSR
DATD
28
CSR
DATD
29
CSR
DATD
23
CSR
DATD
24 NC CSR
DATD
25
CSR
DATD
19
CSR
DATD
20
CSR
DATD
21
CSR
DATD
22
CSR
DATD
16
CSR
DATD
17 NC CSR
DATD
18
CSR
DATD
15
CSR
DATD
12
CSR
DATD
13
CSR
DATD
14
CSR
DATD
10
CSR
DATD
9VDD18 CSR
DATD
11
CSR
DATD
8
CSR
DATD
5
CSR
DATD
6
CSR
DATD
7
CSR
DATD
2
CSR
DATD
4NC CSR
DATD
3
CSR
DATD
1
CSR
DATD
0
CSR
BAD
0
CSR
BAD
1
CSR
ADRD
8
CSR
ADRD
11
CSR
ADRD
10
CSR
ADRD
9
CSR
ADRD
7
CSR
ADRD
6
CSR
ADRD
5
CSR
ADRD
4
CSR
ADRD
3
CSR
ADRD
2
CSR
ADRD
1NC
CSR
ADRD
0
CSR
CSD CSR
RASD CSR
CASD
CSR
WED VDD18 URX
ENBD
3
URX
ENBD
2
URX
ENBD
1
URX
ENBD
0
URX
ADRD
4
URX
ADRD
3
URX
ADRD
2
URX
ADRD
1
URX
ADRD
0
URX
CLAVD
3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
ABCDEFGHJKLMNPRTUVWYAAABACADAEAF
Bottom View
UTX
ADRU
3
VSS
CSR
ADRU
1
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS VSS VSS VSS VSS VSS VSS VSSVSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSSVSSVSSVSSVSSVSSVSSVSSVSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33
VDD33 VDD33VDD33 VDD33VDD33 VDD33VDD33 VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
ABCDEFGHJKLMNPRTUVWYAAABACADAEAF
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
NC
oD
signal
name
xxx
Special Pin Type:
oD: open Drain
tri: TriState
Internal
Pull-Up
Transistor
Internal
Pull-Down
Transistor
Signal Names:
xxx: active high
xxx: active low
VSS: 0V
VDD33: 3.3V
VDD18: 1.8V
QCI
TXCLK
QCI
TXDAT
MP
RDY
tri
MP
INTD
oD
QCI
TX
FRAME
ERC
FREQ
SEL
Bottom View
Prel. ABMP Data Sheet
Pin Descriptions
Preliminary Data Sheet 25 2001-14-01
PRELIMINARY
2.2 Pin Diagram with Functional Groupings
•
Figure 2-2 Pin Configuration (Bottom View)
URX
PRTYU URX
CLKU
URX
DATU
0
URX
DATU
2
URX
DATU
4
URX
DATU
8
URX
DATU
12 VDD18 CPR
ADR
18
CPR
ADR
14
CPR
ADR
10
CPR
ADR
7
CPR
ADR
2
CPR
DAT
18
CPR
DAT
13
CPR
DAT
10
CPR
DAT
5
CPR
DAT
2
UTX
DATD
15
UTX
DATD
11 NC UTX
DATD
4
UTX
DATD
1NC UTX
CLKD UTX
CLAV2
URX
ENBU
1
URX
ENBU
2
URX
DATU
1
URX
DATU
3
URX
DATU
5
URX
DATU
9
URX
DATU
13
CPR
OE
CPR
ADR
17
CPR
ADR
13
CPR
ADR
9
CPR
ADR
6
CPR
ADR
1
CPR
DAT
19
CPR
DAT
14
CPR
DAT
11
CPR
DAT
6NC VDD18 UTX
DATD
12
UTX
DATD
8
UTX
DATD
5
UTX
DATD
2
UTX
DATD
0
UTX
PRTYD UTX
CLAV1
URX
ENBU
3
URX
ADRU
0
URX
ENBU
0NC URX
DATU
6
URX
DATU
10
URX
DATU
14
CPR
GW
CPR
ADR
16
CPR
ADR
12
CPR
ADR
8
CPR
ADR
5
CPR
ADR
0VDD18 CPR
DAT
15
CPR
DAT
12
CPR
DAT
7
CPR
DAT
3
CPR
DAT
0
UTX
DATD
13
UTX
DATD
9
UTX
DATD
6
UTX
DATD
3
UTX
SOCD
UTX
ADRD
4
UTX
CLAV0
URX
ADRU
1
URX
ADRU
2
URX
ADRU
3
URX
SOCU
URX
DATU
7
URX
DATU
11
URX
DATU
15
CPR
ADSC
CPR
ADR
15
CPR
ADR
11 NC CPR
ADR
4
CPR
ADR
3
CPR
DAT
17
CPR
DAT
16
CPR
DAT
9
CPR
DAT
8
CPR
DAT
4
CPR
DAT
1
UTX
DATD
14
UTX
DATD
10
UTX
DATD
7
UTX
CLAV3
UTX
ADRD
1
UTX
ADRD
2
UTX
ADRD
3
URX
ADRU
4VDD18 URX
CLAVU
0
URX
CLAVU
1
URX
CLAVU
2
URX
CLAVU
3
CSR
WEU CSR
CASU
CSR
RASU CSR
CSU
CSR
ADRU
0
CSR
ADRU
2
CSR
ADRU
3
CSR
ADRU
4
CSR
ADRU
5
CSR
ADRU
6
CSR
ADRU
7
CSR
ADRU
8
CSR
ADRU
9
CSR
ADRU
10
CSR
ADRU
11
CSR
BAU
1
CSR
BAU
0
CSR
DATU
1
CSR
DATU
2
CSR
DATU
3
CSR
DATU
0
VDD18 CSR
DATU
4
CSR
DATU
5
CSR
DATU
6
CSR
DATU
8
CSR
DATU
9
CSR
DATU
10
CSR
DATU
7
CSR
DATU
13
CSR
DATU
12
CSR
DATU
11
CSR
DATU
14
CSR
DATU
18
CSR
DATU
17
CSR
DATU
15
CSR
DATU
16
CSR
DATU
21
CSR
DATU
20
CSR
DATU
19
CSR
DATU
22
CSR
DATU
26
CSR
DATU
25
CSR
DATU
24
CSR
DATU
23
CSR
DATU
29
CSR
DATU
28 VDD18 CSR
DATU
27
SPI
SI
ERC
RAM
SEL
CSR
DATU
31
CSR
DATU
30
TST
ERC
CLK
SPI
CS SPI
CLK SPI
SO
TDI TRST EXT
FREEZE RAM
CLK
UTX
ENBU
0TDO TMS TCK
UTX
ENBU
3
UTX
ENBU
2
UTX
ENBU
1
UTX
ADRU
4
UTX
DATU
2
UTX
DATU
6
UTX
DATU
14
MP
MODE
VDD18
PLL VSS
PLL MP
ADR2 VDD18 MP
DAT1 MP
DAT2 MP
DAT6 MP
DAT9 MP
DAT13
URX
DATD
1
URX
DATD
4NC URX
CLAVD
2
URX
CLAVD
1
URX
CLAVD
0
UTX
ADRU
1
UTX
ADRU
0
UTX
PRTYU
UTX
DATU
5
UTX
DATU
9
UTX
DATU
13
UTX
DATU
10
VSS
PLL
SYS
CLK
SEL
SYS
CLK MP
ADR3 MP
ADR6 MP
DAT3 MP
DAT7 MP
DAT10 MP
DAT14 VDD18 URX
DATD
5
URX
DATD
8
URX
DATD
15 NC URX
PRTYD
UTX
ADRU
2
UTX
CLAVU
0
UTX
CLAVU
3
UTX
SOCU
UTX
DATU
0
UTX
DATU
4
UTX
DATU
8
UTX
DATU
12
UTX
DATU
1
MP
INT MP
RD
ERC
CLK RESET MP
ADR0 MP
ADR4 MP
ADR7 MP
DAT4 MP
DAT8 MP
DAT11 MP
DAT15
URX
DATD
2
URX
DATD
6
URX
DATD
9
URX
DATD
11
URX
CLKD URX
SOCD
UTX
CLAVU
1
UTX
CLAVU
2VDD18 UTX
CLKU
UTX
DATU
3
UTX
DATU
7
UTX
DATU
11
UTX
DATU
15
MP
CS MP
WR
ERC
CLK
SEL
VDD18
PLL MP
ADR1 MP
ADR5 MP
DAT0 MP
DAT5 NC MP
DAT12
URX
DATD
0
URX
DATD
3
URX
DATD
7
URX
DATD
10
URX
DATD
12
URX
DATD
13
URX
DATD
14
UTX
ENBD
2
UTX
ENBD
3VDD18 UTX
ADRD
0
CSR
DATD
30
CSR
DATD
31
UTX
ENBD
0
UTX
ENBD
1
CSR
DATD
26
CSR
DATD
27
CSR
DATD
28
CSR
DATD
29
CSR
DATD
23
CSR
DATD
24 NC CSR
DATD
25
CSR
DATD
19
CSR
DATD
20
CSR
DATD
21
CSR
DATD
22
CSR
DATD
16
CSR
DATD
17 NC CSR
DATD
18
CSR
DATD
15
CSR
DATD
12
CSR
DATD
13
CSR
DATD
14
CSR
DATD
10
CSR
DATD
9VDD18 CSR
DATD
11
CSR
DATD
8
CSR
DATD
5
CSR
DATD
6
CSR
DATD
7
CSR
DATD
2
CSR
DATD
4NC CSR
DATD
3
CSR
DATD
1
CSR
DATD
0
CSR
BAD
0
CSR
BAD
1
CSR
ADRD
8
CSR
ADRD
11
CSR
ADRD
10
CSR
ADRD
9
CSR
ADRD
7
CSR
ADRD
6
CSR
ADRD
5
CSR
ADRD
4
CSR
ADRD
3
CSR
ADRD
2
CSR
ADRD
1NC
CSR
ADRD
0
CSR
CSD CSR
RASD CSR
CASD
CSR
WED VDD18 URX
ENBD
3
URX
ENBD
2
URX
ENBD
1
URX
ENBD
0
URX
ADRD
4
URX
ADRD
3
URX
ADRD
2
URX
ADRD
1
URX
ADRD
0
URX
CLAVD
3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
ABCDEFGHJKLMNPRTUVWYAAABACADAEAF
Bottom View
UTX
ADRU
3
VSS
CSR
ADRU
1
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS VSS VSS VSS VSS VSS VSS VSSVSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSSVSSVSSVSSVSSVSSVSSVSSVSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33
VDD33 VDD33VDD33 VDD33VDD33 VDD33VDD33 VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
ABCDEFGHJKLMNPRTUVWYAAABACADAEAF
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
UTOPIA Receive Upstream IF Cell Pointer SSRAM IF UTOPIA Tran s mit Downstr eam IF
Cell St orage SDRAM Upstrem IF
Cell Storag e SDRAM Dow nstrem IF
UTOPIA Receive Downstream IFuP IF, Clock Supply IF and QCI IFUTOPIA Transmit Upstream IF
SPI & Test IF
NC
oD
signal
name
xxx
Special Pin Type:
oD: open Drain
tri: TriState
Internal
Pull-Up
Transistor
Internal
Pull-Down
Transistor
Signal Names:
xxx: active high
xxx: active low
VSS: 0V
VDD33: 3.3V
VDD18: 1.8V
QCI
TXCLK
QCI
TXDAT
MP
RDY
tri
MP
INTD
oD
QCI
TX
FRAME
ERC
FREQ
SEL
Bottom View
Prel. ABMP Data Sheet
Pin Descriptions
Preliminary Data Sheet 26 2001-14-01
PRELIMINARY
2.3 Pin Definitions and Functions
Table 2-1 lists and explains all pins/balls organ ized in fu nctional groups. Table 2-1 uses
the following naming conventions:
Note: The ABMP signal pins are not 5V I/O tolerant. For further details refer to “DC
Characteristics” on Page 345.
Ball No. Ball Number with respect to package outline
(see Figure 2-1)
Symbol Signal Name
Type Type of pin/ball:
I Input pin
IPD Input pin (Internal Pull-Down Transistor)
IPU Input pin (Internal Pull-Up Transistor)
O Output pin (Push/Pull)
O (oD) Output pin (Open Drain)
O (tri) Output pin (TriState)
Function Functional pin/ball description
Table 2- 1 Ball Definitions and Functions
Ball
No. Symbol Type Function
2.3.1 Common System Clock Supply (6 pins)
P24 SYSCLK I System Clock
This clock signal feeds D PLL1 and DPLL2 a nd the
internal ABMP Core Clock depending on signal
SYSCLKSEL.
N24 SYSCLKSEL IPD Internal ABMP Core Clock Source Select:
’H’: Internal Core Clock is supplied by signal
SYSCLK
’L’: Internal Core Clock is supplied by DPLL1
M25 ERCCLK I Alternative ERC Cl ock Supply
It is recommended to connect this signal to VSS if
not used.
Prel. ABMP Data Sheet
Pin Descriptions
Preliminary Data Sheet 27 2001-14-01
PRELIMINARY
M26 ERCCLKSEL IPD Internal Alternative ERC Clock Source Select:
’H’: ERC unit alternative cl ock is supplied by signal
‘ERCCLK’.
’L’: ERC unit alternative clock is supplied by
DPLL2.
L24 ERC-
FREQSEL IPD Internal ERC Clock Source Select:
’H’: Asynchronous ERC Operation
ERC unit clock is supplied by signal ‘ERCCLK’ or
DPLL2.
’L’: Synchronous ERC Operation
ERC unit clock is supplied by internal core clock
(signal ‘SYSCLK’ or DPLL1).
D21 RAMCLK O Reference cl ock for external RAMs (CSRU, C SRD
and CPR)
2.3.2 Utopia Receive Interface Upstream (Master/Slave) (32 pins)
G4,
G3,
G2,
G1,
F4,
F3,
F2,
F1,
E4,
E3,
E2,
E1,
D2,
D1,
C2,
C1
15,
14,
13,
12,
11,
10,
9,
8,
7,
6,
5,
4,
3,
2,
1,
0
URXDATU(15:0)
I UTOPIA Receive Data Bus Upstream
(from PHY)
A1 URXPRTYU IPD UTOPIA Receive Odd Parity of URXDATU(15:0)
(PHY side)
Table 2-1 Ball Definitions and Functi ons (cont’d)
Ball
No. Symbol Type Function
Prel. ABMP Data Sheet
Pin Descriptions
Preliminary Data Sheet 28 2001-14-01
PRELIMINARY
A5,
C4,
B4,
A4,
B3
4,
3,
2,
1,
0
URXADRU(4:0)
I/OPD UTOPIA Receive Address Bus (PHY side)
Master Mode: output
Slave Mode: input
A3,
B2,
A2,
C3
3,
2,
1,
0
URXENBU(3:0)
I/OPU UTOPIA Receive Enable Bus (PHY side)
Master Mode: output
Slave Mode: input
B6,
A6,
D5,
C5
3,
2,
1,
0
URXCLAVU(3:0)
I/OPD UTOPIA Receive CLAV Bus (PHY side)
Master Mode: input
Slave Mode: output
D4 URXSOCU IPD UTOPIA Receive Start of Ce ll signal (PHY side )
B1 URXCLKU I UTOPIA Receive Clock signal (PHY side)
Table 2-1 Ball Definitions and Functi ons (cont’d)
Ball
No. Symbol Type Function
Prel. ABMP Data Sheet
Pin Descriptions
Preliminary Data Sheet 29 2001-14-01
PRELIMINARY
2.3.3 Utopia Transmit Interface Downstream (Master/Slave) (32 pins)
W1,
Y4,
Y3,
Y2,
Y1,
AA4,
AA3,
AA2,
AB4,
AB3,
AB2,
AB1,
AC3,
AC2,
AC1,
AD2
15,
14,
13,
12,
11,
10,
9,
8,
7,
6,
5,
4,
3,
2,
1,
0
UTXDATD(15:0)
O UTOPIA Transmit Data Bus Downstream
(to PHY)
AE2 UTXPRTYD OPD UTOPIA Transmit Odd Parity of UTXDATD(15:0)
(PHY side)
AE3,
AF4,
AE4,
AD4,
AF5
4,
3,
2,
1,
0
UTXADRD(4:0)
I/OPD UTOPIA Transmit Address Bus (PHY side)
Master Mode: output
Slave Mode: input
AD5,
AC5,
AF6,
AE6
3,
2,
1,
0
UTXENBD(3:0)
I/OPU UTOPIA Transmit Enable Bus (PHY side)
Master Mode: output
Slave Mode: input
Table 2-1 Ball Definitions and Functi ons (cont’d)
Ball
No. Symbol Type Function
Prel. ABMP Data Sheet
Pin Descriptions
Preliminary Data Sheet 30 2001-14-01
PRELIMINARY
AC4,
AF1,
AF2,
AF3
3,
2,
1,
0
UTXCLAVD(3:0)
I/OPD UTOPIA Transmit CLAV Bus (PHY side)
Master Mode: input
Slave Mode: output
AD3 UTXSOCD OPD UTOPIA Transmit Start of Cell signal (PHY side)
AE1 UTXCLKD I UTOPIA Transmit Clock signal (PHY side)
2.3.4 Utopia Receive Interface Downstream (Master/Slave) (32 pins)
AD24,
AF26,
AE26,
AD26,
AD25,
AC26,
AC25,
AC24,
AB26,
AB25,
AB24,
AB23,
AA26,
AA25,
AA23,
Y26
15,
14,
13,
12,
11,
10,
9,
8,
7,
6,
5,
4,
3,
2,
1,
0
URXDATD(15:0)
I UTOPIA Receive Data Bus Downstream
(from SF)
AF24 URXPRTYD IPD UTOPIA Receive Odd Parity of URXDATD(15:0)
(SF side)
AE21,
AF21,
AC22,
AD22,
AE22
4,
3,
2,
1,
0
URXADRD(4:0)
I/OPD UTOPIA Receive Address Bus (SF side)
Master Mode: output
Slave Mode: input
Table 2-1 Ball Definitions and Functi ons (cont’d)
Ball
No. Symbol Type Function
Prel. ABMP Data Sheet
Pin Descriptions
Preliminary Data Sheet 31 2001-14-01
PRELIMINARY
AE20,
AF20,
AC21,
AD21
3,
2,
1,
0
URXENBD(3:0)
I/OPU UTOPIA Receive Enable Bus (SF side)
Master Mode: output
Slave Mode: input
AF22,
AD23,
AE23,
AF23
3,
2,
1,
0
URXCLAVD(3:0)
I/OPD UTOPIA Receive CLAV Bus (SF side)
Master Mode: input
Slave Mode: output
AF25 URXSOCD IPD UTOPIA Receive Start of Cell signal (SF side)
AE25 URXCLKD I UTOPIA Receive Clock signal (SF side)
2.3.5 Utopia Transmit Interface Upstream (Master/Slave) (32 pins)
J26,
H23,
H24,
H25,
H26,
G23,
G24,
G25,
G26,
F23,
F24,
F25,
F26,
E23,
E24,
E25
15,
14,
13,
12,
11,
10,
9,
8,
7,
6,
5,
4,
3,
2,
1,
0
UTXDATU(15:0)
O UTOPIA Transmit Data Bus Upstream
(to SF)
D24 UTXPRTYU OPD UTOPIA Transmit Odd Parity of UTXDATU(15:0)
(SF side)
Table 2-1 Ball Definitions and Functi ons (cont’d)
Ball
No. Symbol Type Function
Prel. ABMP Data Sheet
Pin Descriptions
Preliminary Data Sheet 32 2001-14-01
PRELIMINARY
D23,
A26,
A25,
A24,
B24
4,
3,
2,
1,
0
UTXADRU(4:0)
I/OPD UTOPIA Transmit Address Bus (SF side)
Master Mode: output
Slave Mode: input
A23,
B23,
C23,
A22
3,
2,
1,
0
UTXENBU(3:0)
I/OPU UTOPIA Transmit Enable Bus (SF side)
Master Mode: output
Slave Mode: input
C25,
C26,
B26,
B25
3,
2,
1,
0
UTXCLAVU(3:0)
I/OPD UTOPIA Transmit CLAV Bus (SF side)
Master Mode: input
Slave Mode: output
D25 UTXSOCU OPD UTOPIA Transmit Start of Cell signal (SF side)
E26 UTXCLKU I UTOPIA Transmit Clock signal (SF side)
2.3.6 Microprocessor Interface (32 pins)
N25 RESET I ABMP Reset
Table 2-1 Ball Definitions and Functi ons (cont’d)
Ball
No. Symbol Type Function
Prel. ABMP Data Sheet
Pin Descriptions
Preliminary Data Sheet 33 2001-14-01
PRELIMINARY
Y25,
Y24,
Y23,
W26,
W25,
W24,
W23,
V25,
V24,
V23,
U26,
U25,
U24,
U23,
T23,
T26
15,
14,
13,
12,
11,
10,
9,
8,
7,
6,
5,
4,
3,
2,
1,
0
MPDAT(15:0)
I/O Microprocessor Data Bus
T25,
T24,
R26,
R25,
R24,
P23,
P26,
P25
7,
6,
5,
4,
3,
2,
1,
0
MPADR(7:0)
I Microprocessor Address Bus
K24 MPWR IWR when MPMOD=0 (Intel Mode)
R/W when MPMOD=1 (Motorola Mode).
K23 MPRD IRD when MPMOD=0 (Intel Mode)
DS when MPMOD=1 (Motorola Mode).
J24 MPCS I Chip Select from Microprocessor.
J23 MPINT O(oD) Interrupt Request to Microprocessor.
Open drain, needs external pull-up resistor. Inter-
rupt pins of several devices can be wired-or
together.
Table 2-1 Ball Definitions and Functi ons (cont’d)
Ball
No. Symbol Type Function
Prel. ABMP Data Sheet
Pin Descriptions
Preliminary Data Sheet 34 2001-14-01
PRELIMINARY
K26 MPINTD O(oD) Interrupt Request DBA to Microprocessor.
Open drain, needs external pull-up resistor. Inter-
rupt pins of several devices can be wired-or
together.
This interrupt signal is exclusively for DBA related
events and thus associated to register ISRDBA [].
K25 MPRDY O( tri) Ready Output to Microproce ssor fo r read and w rite
accesses.
J25 MPMODE IPD Select Intel type processor when connected to log-
ical 0 or select Motorola type processor when
connected to logical 1.
Table 2-1 Ball Definitions and Functi ons (cont’d)
Ball
No. Symbol Type Function
Prel. ABMP Data Sheet
Pin Descriptions
Preliminary Data Sheet 35 2001-14-01
PRELIMINARY
2.3.7 Cell Storage RAM Upstream (50 pins)
C19,
D19,
A18,
B18,
D18,
A17,
B17,
C17,
D17,
D16,
A16,
B16,
C16,
A15,
B15,
D15,
C15,
D14,
A14,
B14,
C14,
C13,
B13,
A13,
D13,
D12,
C12,
B12,
C11,
B11,
A11,
D11
31,
30,
29,
28,
27,
26,
25,
24,
23,
22,
21,
20,
19,
18,
17,
16,
15,
14,
13,
12,
11,
10,
9,
8,
7,
6,
5,
4,
3,
2,
1,
0
CSRDATU(31:0)
I/O Data Bus to Cell Storage RAM Upstream
D10 CSRBAU0 O Cell Storage RAM Bank Address 0 Upstream
C10 CSRBAU1 O Cell Storage RAM Bank Address 1Upstream
Table 2-1 Ball Definitions and Functi ons (cont’d)
Ball
No. Symbol Type Function
Prel. ABMP Data Sheet
Pin Descriptions
Preliminary Data Sheet 36 2001-14-01
PRELIMINARY
B10,
A10,
D9,
C9,
B9,
A9,
D8,
C8,
B8,
A8,
D7,
C7
11,
10,
9,
8,
7,
6,
5,
4,
3,
2,
1,
0
CSRADRU(11:0)
O Address Bus of Cell Storage RAM Upstream
B7 CSRCSU O Cell Storage RAM Upstream Chip Select
A7 CSRRASU O Cell Storage RAM Upstream Row Address Strobe
D6 CSRCASU O Cell Storage RAM Upstream Column Addr ess
Strobe
C6 CSRWEU O Cell Storage RAM Upstream Write Enable
2.3.8 Cell Storage RAM Downstream (50 pins)
Table 2-1 Ball Definitions and Functi ons (cont’d)
Ball
No. Symbol Type Function
Prel. ABMP Data Sheet
Pin Descriptions
Preliminary Data Sheet 37 2001-14-01
PRELIMINARY
AD6,
AC6,
AF7,
AE7,
AD7,
AC7,
AF8,
AD8,
AC8,
AF9,
AE9,
AD9,
AC9,
AF10,
AD10,
AC10,
AC11,
AF11,
AE11,
AD11,
AF12,
AC12,
AD12,
AC13,
AF13,
AE13,
AD13,
AD14,
AF14,
AC14,
AC15,
AD15
31,
30,
29,
28,
27,
26,
25,
24,
23,
22,
21,
20,
19,
18,
17,
16,
15,
14,
13,
12,
11,
10,
9,
8,
7,
6,
5,
4,
3,
2,
1,
0
CSRDATD(31:0)
I/O Data Bus to Cell Storage RAM Downstream
AE15 CSRBAD0 O Cell Storage RAM Bank Address 0 Downstream
AF15 CSRBAD1 O Cell Storage RAM Bank Address 1Downstream
Table 2-1 Ball Definitions and Functi ons (cont’d)
Ball
No. Symbol Type Function
Prel. ABMP Data Sheet
Pin Descriptions
Preliminary Data Sheet 38 2001-14-01
PRELIMINARY
AD16,
AE16,
AF16,
AC16,
AC17,
AD17,
AE17,
AF17,
AC18,
AD18,
AE18,
AC19
11,
10,
9,
8,
7,
6,
5,
4,
3,
2,
1,
0
CSRADRD(11:0)
O Address Bus of Cell Storage RAM Downstream
AD19 CSRCSD O Cell Storage RAM Downstream Chip Select
AE19 CSRRASD O Cell Storage RAM Downstream Row Address
Strobe
AF19 CSRCASD O Cell Storage RAM Downstream Column Address
Strobe
AC20 CSRWED O Cell Storage RAM Downstream Write Enable
Table 2-1 Ball Definitions and Functi ons (cont’d)
Ball
No. Symbol Type Function
Prel. ABMP Data Sheet
Pin Descriptions
Preliminary Data Sheet 39 2001-14-01
PRELIMINARY
2.3.9 Common Up- and Downst ream Cell Pointer RAM (42 pins)
P2,
P1,
P4,
R4,
R3,
R2,
R1,
T3,
T2,
T1,
T4,
U4,
U3,
U2,
U1,
V4,
V3,
V1,
W4,
W3
19,
18,
17,
16,
15,
14,
13,
12,
11,
10,
9,
8,
7,
6,
5,
4,
3,
2,
1,
0
CPRDAT(19:0)
I/O Data Bus to Cell Pointer RAM
Table 2-1 Ball Definitions and Functi ons (cont’d)
Ball
No. Symbol Type Function
Prel. ABMP Data Sheet
Pin Descriptions
Preliminary Data Sheet 40 2001-14-01
PRELIMINARY
J1,
J2,
J3,
J4,
K1,
K2,
K3,
K4,
L1,
L2,
L3,
M1,
M2,
M3,
M4,
N4,
N1,
N2,
N3
18,
17,
16,
15,
14,
13,
12,
11,
10,
9,
8,
7,
6,
5,
4,
3,
2,
1,
0
CPRADR(18:0)
O Address Bus of Cell Pointer RAM
H4 CPRADSC O Cell Pointer RAM Chip Select
H3 CPRGW O Cell Pointer RAM
H2 CPROE O Cell Pointer RAM Output Enabl e
2.3.10 JTAG Bounda ry Scan (5 pins)
A21 TDI IPU Test Data Input.
This pin has an internal pull-up resistor.
D22 TCK IPU Test Clock.
This pin has an internal pull-up resistor.
C22 TMS IPU Test Mode Select.
This pin has an internal pull-up resistor.
B21 TRST IPU Test Data Reset
This pin has an internal pull-up resistor.
B22 TDO O Test Data Output
In normal operation, must not be connected.
Table 2-1 Ball Definitions and Functi ons (cont’d)
Ball
No. Symbol Type Function
Prel. ABMP Data Sheet
Pin Descriptions
Preliminary Data Sheet 41 2001-14-01
PRELIMINARY
2.3.11 SPI Interface (5 pins)
B20 SPICS O SPI Chip Select
C20 SPICLK O SPI Clock
D20 SPISO O SPI Serial Out
A19 SPISI IPD SPI Serial In
B19 IOPRAMSEL IPD IOP Code RAM Select
2.3.12 QCI Interface (3 pins)
L26 QCITXDAT O QCI Transmit Data
L25 QCITXCLK I QCI Clock
L23 QCITXFRAME I QCI Transmit Frame Sync
2.3.13 Test (1 pin)
A20 TSTERCCLK IPD
2.3.14 Production Test (1 pin)
C21 EXTFREEZ IPD For device test only, do not connect.
Must not be connected in normal operation.
2.3.15 Supply (74 VSS , 32 VDD33 and 14 VDD18 pins)
Table 2-1 Ball Definitions and Functi ons (cont’d)
Ball
No. Symbol Type Function
Prel. ABMP Data Sheet
Pin Descriptions
Preliminary Data Sheet 42 2001-14-01
PRELIMINARY
Total signal pins: 323; total power supply pins: 120.
E5, E6, E9, E10, E13, E14, E17,
E18, E21, E22, F5, F22, J5, J22,
K5, K22, L11, L12, L13, L14, L15,
L16, M11, M12, M13, M14, M15,
M16, N5, N11, N12, N13, N14,
N15, N16, N22, P5, P11, P12,
P13, P14, P15, P16, P22, R11,
R12, R13, R14, R15, R16, T11,
T12, T13, T14, T15, T16, U5, U22,
V5, V22, AA5, AA22, AB5, AB6,
AB9, AB10, AB13, AB14, AB17,
AB18, AB21, AB22
VSS, Chip Ground
(All pins should be connected to the same level)
E7, E8, E11, E12, E15, E16, E19,
E20, G5, G22, H5, H22, L5, L22,
M5, M22, R5, R22, T5, T22, W5,
W22, Y5, Y22, AB7, AB8, AB11,
AB12, AB15, AB16, AB19, AB20
VDD33, Chip 3.3 V Supply
(All pins should be connected to the same level)
B5, A12, C18, D26, R23, AA24,
AD20, AE12, AE5, W2, P3, H1 VDD18, Chip 1.8 V Supply
(All pins should be connected to the same level)
N23, M24 VSS PLL, Chip GND Supply
(All pins should be connected to the same level)
N26, M23 VDD18 PLL, Chip 1.8 V Supply
(All pins should be connected to the same level)
2.3.16 Un-Connected (13 pins)
D3, L4, V2, AA1, AD1, AE8, AE10,
AE14, AF18, AE24, AC23, V26,
C24
Un-Conncted pins.
It is recommended to leave these pins unconnected
on the board to guarantee board compatibility to
furture device versions.
Table 2-1 Ball Definitions and Functi ons (cont’d)
Ball
No. Symbol Type Function
Prel. ABMP Data Sheet
Functional Descript ion
Preliminary Data Sheet 43 2001-14-01
PRELIMINARY
3 Functional Description
3.1 Block Diagrams
Figure 3-1 shows a typical sub-system integration scenario of the ABMP. The memory
configurations are examples and depend on ABMP operation modes and required
queuing resources.
•
Figure 3-1 Sub-System Integration Diagram
Figure 3-2 shows a functional block diagram illustration of the ABMP. The function
blocks are referenced and described in more details in subsequent chapters.
. . .
. . .
. . .
. . .
4M*16
. . .
. . .
. . .
. . .
4M*16
. . .
. . .
. . .
. . .
512K*32
. . .
. . .
. . .
. . .
4M*16
. . .
. . .
. . .
. . .
4M*16
EEPROM
Cell Pointer
RAM Ups tre am Ce ll
Storage RAM
Downstre am Ce ll
Storage RAM
UTOPIA L2
Interface
(PHY S ide)
UTOPIA L2
Interface
(Backplane Side)
16 Bit uP
Interface Bus
Optional
Code ROM
Test/ JTAG/
Clocking IF
PXB 4330
ABMP
Queue Congestion
Indication Interface
Prel. ABMP Data Sheet
Functional Descript ion
Preliminary Data Sheet 44 2001-14-01
PRELIMINARY
•
Figure 3-2 F unctional Block Diagram
Figure 3-3 shows a logical illustration of the ATM Buffer Manager (ABMP) core for one
direction. Cells with up to 688 Mbit/s equivalent data rate are received by the UTOPIA
receive interface and get assign ed to schedulers and queues within the cel l acceptance
part of the Queue Manager unit. The cell acceptance algorithm verifies that no
thresholds are exceeded which are provided for queues, schedulers, service classes
(traffic classes), as well as the global buffer. Once accepted, a cell cannot be lost, but
will be emitted at the respective UTOPIA interface after some time (exception: queue has
been disabled while cells are stored). Alternatively cells can be received from the
microprocessor interface via the AAL5 assistant unit. In case of ABR connections,
Resource Management (RM) cells are handled in a dedicated function block within the
Enhanced Rate Control (ERC) unit. The demultiplexer forwards the cells to the
respective queue associated with scheduler which sorts them for transmission according
to the programmed configuration. As part of the scheduling function the optional Peak
Rate Limiter and Dual-Leaky-Bucket shaper is provided for the shaping of individual
queues (connections). The scheduler is the key queuing element of the ABMP. The
behavior of the scheduler is described in subsequent chapters. The output multiplexer
recombines the cell streams of all schedulers. Their output rates shall be programmed
such that the accumulated rate does not exceed the total output bandwidth. Emitted cells
are either forwarded to the UTOPIA transmit interface or to the AAL5 assistant unit for
extraction
SDRAM Interface (up)
Cell Handler (CH) upstream
SDRAM Interface (dn)
Cell Handler (CH) downstream
Queue
Manager
(QM)
Scheduler
Block
(SB)
ERC
SSRAM IF
UTOPIA IF (Backplane Side)
UTOPIA IF (PHY Side)
BSCAN/
SPI
uP IF
AAL5
42 50
64 64
10 32 50
Test/
Clocks
14
688 Mbps
688 Mbps
874 Mbps
688 Mbps
ARC
ARC
QCI IF
3
Prel. ABMP Data Sheet
Functional Descript ion
Preliminary Data Sheet 45 2001-14-01
PRELIMINARY
Figure 3-3 Logical Block Diagram (One Direction)
Scheduler #127
Scheduler #1
W
F
Q
Scheduler #0
Global Real Time By pass
D
E
M
U
XM
U
X
ABR Control
Cell Acceptance Algorithm
Address Re duction
cells in cells out
Queue withShaping Function
Sched ul er Rate Shaping
Cyclic Mux
Weighted Fair Queueing Scheduler
WFQ
Strict Priority Mux
ARC QM ERC
UTOPIA Receive
UTOPIA TransmituP Interface
AAL5 Assistant
AAL5 Assistant
uP Interface
Prel. ABMP Data Sheet
Functional Descript ion
Preliminary Data Sheet 46 2001-14-01
PRELIMINARY
3.2 Functional Block Description
3.2.1 Cell Handler (Upstream/Downstream)
The Cell Handler (CH) units are responsible for the physical data flow of storing and
retrieving cells to/from the respective Cell Storage RAM or insertion and extraction of
Resource Management (RM) cells. Updates to the cell header section or to the cell
contents in case of OAM-RM cells are also performed by the Cell Handler units.
3.2.2 Queue Manager and Scheduler Block (Overview)
The Queue Manager (QM) unit is the central function of the ABMP device and handles
the logical data flows for upstream and downstream direction. It utilizes the Scheduler
Block (SB) as a co-processor function and a common Cell Pointer RAM (SSRAM) to
administrate cell storage.
Any cell entering the CH unit is reported to the QM unit running the cell acceptance
algorithm. In a fi rst step a cell is cla ssified and associated to the logi cal resource e ntities
connection, queue, tra ffic class and scheduler. As an exception R esource Management
(RM) cells are extracted and forwarded to the Enhanced Rate Control (ERC) unit for
further processing. Once all associated resources are determined, the QM runs the cell
acceptance algorithm based on the current parameter sets. As a result of all threshold
evaluations the cell is either discarded or accepted and related counters are updated
accordingly. Non-empty queues are reported to the Scheduler Block (SB) unit to be
scheduled by the associated calendar. In return the SB u nit reports queues to the Queue
Manager that are due for cell transmission in the current cell slot. Upon a cell emit
request for a specific queue the QM either requests the Cell Handler to retrieve and
transmit the next cell or to insert an RM cell as prepared by the ERC unit.
Since the QM and SB units are the central functions of the ABMP device they are
described in more details in chapter “Detailed Queue Manager and Scheduler Block
Description” on Page 63.
3.2.3 Enhanced Rate Control (ERC) Unit (Overview)
The Enhanced Rate Control (ERC) unit interfaces to the QM and the CH units for RM
cell insertion and extraction. It controls the following functions on a per connection basis:
• ABR-VS/VD: Processing of RM cells, related state machines and rate adjustment
• ABR-ER: Rate calculation and RM cell processing (and adjustment in case of RSC)
• VBR: Dual-Leaky-Bucket algorithm for VBR shaping
The ERC unit is described in more details in chapter “D etailed ERC Descript ion” on
Page 78.
Prel. ABMP Data Sheet
Functional Descript ion
Preliminary Data Sheet 47 2001-14-01
PRELIMINARY
3.2.4 AAL5 Assistant
The AAL5 Assistant unit allows insertion and extraction of AAL5 segmented packets
from and towards the microprocessor interface. Supported by the corresponding
software driver, the unit realizes an “in-line” SAR function, i.e. one packet is processed
at any time by a SAR function. However upstream and downstream flow as well as
extraction and insertion are independent functions that may be operated interleaved.
For extraction at l east one schedul er must be associated to the AAL5 Assistan t unit and
each queue assigned to the scheduler must be assigned to a VC-merge group to
guarantee that complete packets are forwarded to the AAL5 Assistant unit. The
scheduler rate s can be adjusted according to the microprocessor i nterface bandwidth or
the intended CPU load. However the CPU may extract the payload chunks at a lower
rate which will resu lt in in ternal scheduler backpres sure. No data l oss will occur i n that
case. The CPU reads consecutive 48 byte payload chunks that can be re-assembled
immediately in the host memory while the AAL5 Assistant unit checks the AAL5 trailor.
For insertion the CPU prepares the ATM cell header for the following packet and writes
48 byte payload chunks to the AAL5 Assistant unit which will generate the cells and the
AAL5 trailor for automatic completion of the last cell of the packet. Internally, the cells
are forwarded to either the downstream or upstream Cell Handler and processed in the
same way as cells received by an UTOPIA receive interface.
Prel. ABMP Data Sheet
Functional Descript ion
Preliminary Data Sheet 48 2001-14-01
PRELIMINARY
3.2.5 Internal Address Reduction Unit
The ABMP requires an internal 16 bit Local Connection Identifier (LCI) to address its
resources. Two basic cell addressing schemes are supported to extract/generate an LCI
from the cell header:
• LCI mapping modes
An external device generates an LCI and mapps it into the ATM cell header. Three
different mapping modes are supported by the ABMP.
The LCI mapping mode s are described as part of the UTOPIA interf ace description in
chapters “UTOPIA L2 Interfaces (PHY-side)” on Page 115 and “UTOPIA L2
Interface (Backplane-side)” on Page 126.
• Internal Address Reduction mode
The ABMP generates its own internal LCI as a pr ogr ammabl e combi na tion of the cell
header fields VPI, VCI and the Port Number (PN). The port number is taken either
from the UTOPIA port number, the UDF1 or the UDF2 cell header byte.
Internal AddressReduction
Two parameters in register “MODE2” on Page 325 determine the building function of
the internal LCI value:
1. PNUM(2:0)
Determines the number of bits taken from the port number field.
2. MNUM(3:0)
Determines the VCI and VPI ranges depending on the cell header VPI value.
Two translation functions are effective depending on the cell header VPI(11:0) value
compared to the configured parameter MNUM.
In case
the LCI is build by {VPI, VCI, PN} values whereas the VCI range is given by
(MNUM - PNUM) bits and the VPI range is given by (16 - MNUM) bits.
Note: Programming MNUM(3:0) = 0 is interpreted as decimal 16.
The foll owing t ables prov ide the po ssible LC I buildi ng patter ns for all PN UM and MNUM
configurations. The resulting LCI is internally treated the same way as in the LCI cell
header mapping modes, i.e. the two MSB’s are checked against the quarter segement
configuration that allows for cascading of up to 4 ABMP de vices.
Note: VPI, VCI cell header field and port number bit positions that are not mapped into
the LCI are checked against ‘0’. Mismatches are treated as ‘invalid LCI’ and the
cell is discarded.
VPI 110(,)2x1 with;x16MNUM–= for MNUM 0>
x0=for MNUM 0=
–<
Prel. ABMP Data Sheet
Functional Descript ion
Preliminary Data Sheet 49 2001-14-01
PRELIMINARY
Figure 3-4 L CI Building Patterns
PNUM MNUM 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 1 VPI14 VPI13 VPI12 VPI11 VPI10 VPI9 VPI8 VPI7 VPI6 VPI5 VPI4 VPI3 VPI2 VPI1 VPI0 VCI0
0 2 VPI13 VPI12 VPI11 VPI10 VPI9 VPI8 VPI7 VPI6 VPI5 VPI4 VPI3 VPI2 VPI1 VPI0 VCI1 VCI0
0 3 VPI12 VPI11 VPI10 VPI9 VPI8 VPI7 VPI6 VPI5 VPI4 VPI3 VPI2 VPI1 VPI0 VCI2 VCI1 VCI0
0 4 VPI11 VPI10 VPI9 VPI8 VPI7 VPI6 VPI5 VPI4 VPI3 VPI2 VPI1 VPI0 VCI3 VCI2 VCI1 VCI0
0 5 VPI10 VPI9 VPI8 VPI7 VPI6 VPI5 VPI4 VPI3 VPI2 VPI1 VPI0 VCI4 VCI3 VCI2 VCI1 VCI0
0 6 VPI9 VPI8 VPI7 VPI6 VPI5 VPI4 VPI3 VPI2 VPI1 VPI0 VCI5 VCI4 VCI3 VCI2 VCI1 VCI0
0 7 VPI8 VPI7 VPI6 VPI5 VPI4 VPI3 VPI2 VPI1 VPI0 VCI6 VCI5 VCI4 VCI3 VCI2 VCI1 VCI0
0 8 VPI7 VPI6 VPI5 VPI4 VPI3 VPI2 VPI1 VPI0 VCI7 VCI6 VCI5 VCI4 VCI3 VCI2 VCI1 VCI0
0 9 VPI6 VPI5 VPI4 VPI3 VPI2 VPI1 VPI0 VCI8 VCI7 VCI6 VCI5 VCI4 VCI3 VCI2 VCI1 VCI0
0 10 VPI5 VPI4 VPI3 VPI2 VPI1 VPI0 VCI9 VCI8 VCI7 VCI6 VCI5 VCI4 VCI3 VCI2 VCI1 VCI0
0 11 VPI4 VPI3 VPI2 VPI1 VPI0 VCI10 VCI9 VCI8 VCI7 VCI6 VCI5 VCI4 VCI3 VCI2 VCI1 VCI0
0 12 VPI3VPI2VPI1VPI0VCI11VCI10VCI9VCI8VCI7VCI6VCI5VCI4VCI3VCI2VCI1VCI0
0 13 VPI2 VPI1 VPI0 VCI12 VCI11 VCI10 VCI9 VCI8 VCI7 VCI6 VCI5 VCI4 VCI3 VCI2 VCI1 VCI0
0 14 VPI1 VPI0 VCI13 VCI12 VCI11 VCI10 VCI9 VCI8 VCI7 VCI6 VCI5 VCI4 VCI3 VCI2 VCI1 VCI0
0 15 VPI0 VCI14 VCI13 VCI12 VCI11 VCI10 VCI9 VCI8 VCI7 VCI6 VCI5 VCI4 VCI3 VCI2 VCI1 VCI0
0 16 VCI15 VCI14 VCI13 VCI12 VCI11 VCI10 VCI9 VCI8 VCI7 VCI6 VCI5 VCI4 VCI3 VCI2 VCI1 VCI0
1 1 VPI14 VPI13 VPI12 VPI11 VPI10 VPI9 VPI8 VPI7 VPI6 VPI5 VPI4 VPI3 VPI2 VPI1 VPI0 PN0
1 2 VPI13 VPI12 VPI11 VPI10 VPI9 VPI8 VPI7 VPI6 VPI5 VPI4 VPI3 VPI2 VPI1 VPI0 VCI0 PN0
1 3 VPI12 VPI11 VPI10 VPI9 VPI8 VPI7 VPI6 VPI5 VPI4 VPI3 VPI2 VPI1 VPI0 VCI1 VCI0 PN0
1 4 VPI11 VPI10 VPI9 VPI8 VPI7 VPI6 VPI5 VPI4 VPI3 VPI2 VPI1 VPI0 VCI2 VCI1 VCI0 PN0
1 5 VPI10 VPI9 VPI8 VPI7 VPI6 VPI5 VPI4 VPI3 VPI2 VPI1 VPI0 VCI3 VCI2 VCI1 VCI0 PN0
1 6 VPI9 VPI8 VPI7 VPI6 VPI5 VPI4 VPI3 VPI2 VPI1 VPI0 VCI4 VCI3 VCI2 VCI1 VCI0 PN0
1 7 VPI8 VPI7 VPI6 VPI5 VPI4 VPI3 VPI2 VPI1 VPI0 VCI5 VCI4 VCI3 VCI2 VCI1 VCI0 PN0
1 8 VPI7 VPI6 VPI5 VPI4 VPI3 VPI2 VPI1 VPI0 VCI6 VCI5 VCI4 VCI3 VCI2 VCI1 VCI0 PN0
1 9 VPI6 VPI5 VPI4 VPI3 VPI2 VPI1 VPI0 VCI7 VCI6 VCI5 VCI4 VCI3 VCI2 VCI1 VCI0 PN0
1 10 VPI5 VPI4 VPI3 VPI2 VPI1 VPI0 VCI8 VCI7 VCI6 VCI5 VCI4 VCI3 VCI2 VCI1 VCI0 PN0
1 11 VPI4VPI3VPI2VPI1VPI0VCI9VCI8VCI7VCI6VCI5VCI4VCI3VCI2VCI1VCI0PN0
1 12 VPI3 VPI2 VPI1 VPI0 VCI10 VCI9 VCI8 VCI7 VCI6 VCI5 VCI4 VCI3 VCI2 VCI1 VCI0 PN0
1 13 VPI2 VPI1 VPI0 VCI11 VCI10 VCI9 VCI8 VCI7 VCI6 VCI5 VCI4 VCI3 VCI2 VCI1 VCI0 PN0
1 14 VPI1 VPI0 VCI12 VCI11 VCI10 VCI9 VCI8 VCI7 VCI6 VCI5 VCI4 VCI3 VCI2 VCI1 VCI0 PN0
1 15 VPI0 VCI13 VCI12 VCI11 VCI10 VCI9 VCI8 VCI7 VCI6 VCI5 VCI4 VCI3 VCI2 VCI1 VCI0 PN0
1 16 VCI14 VCI13 VCI12 VCI11 VCI10 VCI9 VCI8 VCI7 VCI6 VCI5 VCI4 VCI3 VCI2 VCI1 VCI0 PN0
2 1 VPI13 VPI12 VPI11 VPI10 VPI9 VPI8 VPI7 VPI6 VPI5 VPI4 VPI3 VPI2 VPI1 VPI0 PN1 PN0
2 2 VPI12 VPI11 VPI10 VPI9 VPI8 VPI7 VPI6 VPI5 VPI4 VPI3 VPI2 VPI1 VPI0 VCI0 PN1 PN0
2 3 VPI11 VPI10 VPI9 VPI8 VPI7 VPI6 VPI5 VPI4 VPI3 VPI2 VPI1 VPI0 VCI1 VCI0 PN1 PN0
2 4 VPI10 VPI9 VPI8 VPI7 VPI6 VPI5 VPI4 VPI3 VPI2 VPI1 VPI0 VCI2 VCI1 VCI0 PN1 PN0
2 5 VPI9 VPI8 VPI7 VPI6 VPI5 VPI4 VPI3 VPI2 VPI1 VPI0 VCI3 VCI2 VCI1 VCI0 PN1 PN0
2 6 VPI8 VPI7 VPI6 VPI5 VPI4 VPI3 VPI2 VPI1 VPI0 VCI4 VCI3 VCI2 VCI1 VCI0 PN1 PN0
2 7 VPI7 VPI6 VPI5 VPI4 VPI3 VPI2 VPI1 VPI0 VCI5 VCI4 VCI3 VCI2 VCI1 VCI0 PN1 PN0
2 8 VPI6 VPI5 VPI4 VPI3 VPI2 VPI1 VPI0 VCI6 VCI5 VCI4 VCI3 VCI2 VCI1 VCI0 PN1 PN0
2 9 VPI5 VPI4 VPI3 VPI2 VPI1 VPI0 VCI7 VCI6 VCI5 VCI4 VCI3 VCI2 VCI1 VCI0 PN1 PN0
2 10 VPI4VPI3VPI2VPI1VPI0VCI8VCI7VCI6VCI5VCI4VCI3VCI2VCI1VCI0PN1 PN0
2 11 VPI3VPI2VPI1VPI0VCI9VCI8VCI7VCI6VCI5VCI4VCI3VCI2VCI1VCI0PN1 PN0
2 12 VPI2 VPI1 VPI0 VCI10 VCI9 VCI8 VCI7 VCI6 VCI5 VCI4 VCI3 VCI2 VCI1 VCI0 PN1 PN0
2 13 VPI1 VPI0 VCI11 VCI10 VCI9 VCI8 VCI7 VCI6 VCI5 VCI4 VCI3 VCI2 VCI1 VCI0 PN1 PN0
2 14 VPI0 VCI12 VCI11 VCI10 VCI9 VCI8 VCI7 VCI6 VCI5 VCI4 VCI3 VCI2 VCI1 VCI0 PN1 PN0
2 15 VCI13 VCI12 VCI11 VCI10 VCI9 VCI8 VCI7 VCI6 VCI5 VCI4 VCI3 VCI2 VCI1 VCI0 PN1 PN0
2 16 VCI13 VCI12 VCI11 VCI10 VCI9 VCI8 VCI7 VCI6 VCI5 VCI4 VCI3 VCI2 VCI1 VCI0 PN1 PN0
3 1 VPI12 VPI11 VPI10 VPI9 VPI8 VPI7 VPI6 VPI5 VPI4 VPI3 VPI2 VPI1 VPI0 PN2 PN1 PN0
3 2 VPI11 VPI10 VPI9 VPI8 VPI7 VPI6 VPI5 VPI4 VPI3 VPI2 VPI1 VPI0 VCI0 PN2 PN1 PN0
3 3 VPI10 VPI9 VPI8 VPI7 VPI6 VPI5 VPI4 VPI3 VPI2 VPI1 VPI0 VCI1 VCI0 PN2 PN1 PN0
3 4 VPI9 VPI8 VPI7 VPI6 VPI5 VPI4 VPI3 VPI2 VPI1 VPI0 VCI2 VCI1 VCI0 PN2 PN1 PN0
3 5 VPI8 VPI7 VPI6 VPI5 VPI4 VPI3 VPI2 VPI1 VPI0 VCI3 VCI2 VCI1 VCI0 PN2 PN1 PN0
3 6 VPI7 VPI6 VPI5 VPI4 VPI3 VPI2 VPI1 VPI0 VCI4 VCI3 VCI2 VCI1 VCI0 PN2 PN1 PN0
3 7 VPI6 VPI5 VPI4 VPI3 VPI2 VPI1 VPI0 VCI5 VCI4 VCI3 VCI2 VCI1 VCI0 PN2 PN1 PN0
3 8 VPI5 VPI4 VPI3 VPI2 VPI1 VPI0 VCI6 VCI5 VCI4 VCI3 VCI2 VCI1 VCI0 PN2 PN1 PN0
3 9 VPI4 VPI3 VPI2 VPI1 VPI0 VCI7 VCI6 VCI5 VCI4 VCI3 VCI2 VCI1 VCI0 PN2 PN1 PN0
3 10 VPI3 VPI2 VPI1 VPI0 VCI8 VCI7 VCI6 VCI5 VCI4 VCI3 VCI2 VCI1 VCI0 PN2 PN1 PN0
3 11 VPI2 VPI1 VPI0 VCI9 VCI8 VCI7 VCI6 VCI5 VCI4 VCI3 VCI2 VCI1 VCI0 PN2 PN1 PN0
3 12 VPI1 VPI0 VCI10 VCI9 VCI8 VCI7 VCI6 VCI5 VCI4 VCI3 VCI2 VCI1 VCI0 PN2 PN1 PN0
3 13 VPI0 VCI11 VCI10 VCI9 VCI8 VCI7 VCI6 VCI5 VCI4 VCI3 VCI2 VCI1 VCI0 PN2 PN1 PN0
3 14 VCI12 VCI11 VCI10 VCI9 VCI8 VCI7 VCI6 VCI5 VCI4 VCI3 VCI2 VCI1 VCI0 PN2 PN1 PN0
3 15 VCI12 VCI11 VCI10 VCI9 VCI8 VCI7 VCI6 VCI5 VCI4 VCI3 VCI2 VCI1 VCI0 PN2 PN1 PN0
3 16 VCI12 VCI11 VCI10 VCI9 VCI8 VCI7 VCI6 VCI5 VCI4 VCI3 VCI2 VCI1 VCI0 PN2 PN1 PN0
Prel. ABMP Data Sheet
Functional Descript ion
Preliminary Data Sheet 50 2001-14-01
PRELIMINARY
Figure 3-5 L CI Building Patterns (cont.)
4 1 VPI11 VPI10 VPI9 VPI8 VPI7 VPI6 VPI5 VPI4 VPI3 VPI2 VPI1 VPI0 PN3 PN2 PN1 PN0
4 2 VPI10 VPI9 VPI8 VPI7 VPI6 VPI5 VPI4 VPI3 VPI2 VPI1 VPI0 VCI0 PN3 PN2 PN1 PN0
4 3 VPI9 VPI8 VPI7 VPI6 VPI5 VPI4 VPI3 VPI2 VPI1 VPI0 VCI1 VCI0 PN3 PN2 PN1 PN0
4 4 VPI8 VPI7 VPI6 VPI5 VPI4 VPI3 VPI2 VPI1 VPI0 VCI2 VCI1 VCI0 PN3 PN2 PN1 PN0
4 5 VPI7 VPI6 VPI5 VPI4 VPI3 VPI2 VPI1 VPI0 VCI3 VCI2 VCI1 VCI0 PN3 PN2 PN1 PN0
4 6 VPI6 VPI5 VPI4 VPI3 VPI2 VPI1 VPI0 VCI4 VCI3 VCI2 VCI1 VCI0 PN3 PN2 PN1 PN0
4 7 VPI5 VPI4 VPI3 VPI2 VPI1 VPI0 VCI5 VCI4 VCI3 VCI2 VCI1 VCI0 PN3 PN2 PN1 PN0
4 8 VPI4 VPI3 VPI2 VPI1 VPI0 VCI6 VCI5 VCI4 VCI3 VCI2 VCI1 VCI0 PN3 PN2 PN1 PN0
4 9 VPI3 VPI2 VPI1 VPI0 VCI7 VCI6 VCI5 VCI4 VCI3 VCI2 VCI1 VCI0 PN3 PN2 PN1 PN0
4 10 VPI2 VPI1 VPI0 VCI8 VCI7 VCI6 VCI5 VCI4 VCI3 VCI2 VCI1 VCI0 PN3 PN2 PN1 PN0
4 11 VPI1 VPI0 VCI9 VCI8 VCI7 VCI6 VCI5 VCI4 VCI3 VCI2 VCI1 VCI0 PN3 PN2 PN1 PN0
4 12 VPI0 VCI10 VCI9 VCI8 VCI7 VCI6 VCI5 VCI4 VCI3 VCI2 VCI1 VCI0 PN3 PN2 PN1 PN0
4 13 VCI11 VCI10 VCI9 VCI8 VCI7 VCI6 VCI5 VCI4 VCI3 VCI2 VCI1 VCI0 PN3 PN2 PN1 PN0
4 14 VCI11 VCI10 VCI9 VCI8 VCI7 VCI6 VCI5 VCI4 VCI3 VCI2 VCI1 VCI0 PN3 PN2 PN1 PN0
4 15 VCI11 VCI10 VCI9 VCI8 VCI7 VCI6 VCI5 VCI4 VCI3 VCI2 VCI1 VCI0 PN3 PN2 PN1 PN0
4 16 VCI11 VCI10 VCI9 VCI8 VCI7 VCI6 VCI5 VCI4 VCI3 VCI2 VCI1 VCI0 PN3 PN2 PN1 PN0
5 1 VPI10 VPI9 VPI8 VPI7 VPI6 VPI5 VPI4 VPI3 VPI2 VPI1 VPI0 PN4 PN3 PN2 PN1 PN0
5 2 VPI9 VPI8 VPI7 VPI6 VPI5 VPI4 VPI3 VPI2 VPI1 VPI0 VCI0 PN4 PN3 PN2 PN1 PN0
5 3 VPI8 VPI7 VPI6 VPI5 VPI4 VPI3 VPI2 VPI1 VPI0 VCI1 VCI0 PN4 PN3 PN2 PN1 PN0
5 4 VPI7 VPI6 VPI5 VPI4 VPI3 VPI2 VPI1 VPI0 VCI2 VCI1 VCI0 PN4 PN3 PN2 PN1 PN0
5 5 VPI6 VPI5 VPI4 VPI3 VPI2 VPI1 VPI0 VCI3 VCI2 VCI1 VCI0 PN4 PN3 PN2 PN1 PN0
5 6 VPI5 VPI4 VPI3 VPI2 VPI1 VPI0 VCI4 VCI3 VCI2 VCI1 VCI0 PN4 PN3 PN2 PN1 PN0
5 7 VPI4 VPI3 VPI2 VPI1 VPI0 VCI5 VCI4 VCI3 VCI2 VCI1 VCI0 PN4 PN3 PN2 PN1 PN0
5 8 VPI3 VPI2 VPI1 VPI0 VCI6 VCI5 VCI4 VCI3 VCI2 VCI1 VCI0 PN4 PN3 PN2 PN1 PN0
5 9 VPI2 VPI1 VPI0 VCI7 VCI6 VCI5 VCI4 VCI3 VCI2 VCI1 VCI0 PN4 PN3 PN2 PN1 PN0
5 10 VPI1 VPI0 VCI8 VCI7 VCI6 VCI5 VCI4 VCI3 VCI2 VCI1 VCI0 PN4 PN3 PN2 PN1 PN0
5 11 VPI0 VCI9 VCI8 VCI7 VCI6 VCI5 VCI4 VCI3 VCI2 VCI1 VCI0 PN4 PN3 PN2 PN1 PN0
5 12 VCI10 VCI9 VCI8 VCI7 VCI6 VCI5 VCI4 VCI3 VCI2 VCI1 VCI0 PN4 PN3 PN2 PN1 PN0
5 13 VCI10 VCI9 VCI8 VCI7 VCI6 VCI5 VCI4 VCI3 VCI2 VCI1 VCI0 PN4 PN3 PN2 PN1 PN0
5 14 VCI10 VCI9 VCI8 VCI7 VCI6 VCI5 VCI4 VCI3 VCI2 VCI1 VCI0 PN4 PN3 PN2 PN1 PN0
5 15 VCI10 VCI9 VCI8 VCI7 VCI6 VCI5 VCI4 VCI3 VCI2 VCI1 VCI0 PN4 PN3 PN2 PN1 PN0
5 16 VCI10 VCI9 VCI8 VCI7 VCI6 VCI5 VCI4 VCI3 VCI2 VCI1 VCI0 PN4 PN3 PN2 PN1 PN0
6 1 VPI9 VPI8 VPI7 VPI6 VPI5 VPI4 VPI3 VPI2 VPI1 VPI0 PN5 PN4 PN3 PN2 PN1 PN0
6 2 VPI8 VPI7 VPI6 VPI5 VPI4 VPI3 VPI2 VPI1 VPI0 VCI0 PN5 PN4 PN3 PN2 PN1 PN0
6 3 VPI7 VPI6 VPI5 VPI4 VPI3 VPI2 VPI1 VPI0 VCI1 VCI0 PN5 PN4 PN3 PN2 PN1 PN0
6 4 VPI6 VPI5 VPI4 VPI3 VPI2 VPI1 VPI0 VCI2 VCI1 VCI0 PN5 PN4 PN3 PN2 PN1 PN0
6 5 VPI5 VPI4 VPI3 VPI2 VPI1 VPI0 VCI3 VCI2 VCI1 VCI0 PN5 PN4 PN3 PN2 PN1 PN0
6 6 VPI4 VPI3 VPI2 VPI1 VPI0 VCI4 VCI3 VCI2 VCI1 VCI0 PN5 PN4 PN3 PN2 PN1 PN0
6 7 VPI3 VPI2 VPI1 VPI0 VCI5 VCI4 VCI3 VCI2 VCI1 VCI0 PN5 PN4 PN3 PN2 PN1 PN0
6 8 VPI2 VPI1 VPI0 VCI6 VCI5 VCI4 VCI3 VCI2 VCI1 VCI0 PN5 PN4 PN3 PN2 PN1 PN0
6 9 VPI1 VPI0 VCI7 VCI6 VCI5 VCI4 VCI3 VCI2 VCI1 VCI0 PN5 PN4 PN3 PN2 PN1 PN0
6 10 VPI0 VCI8 VCI7 VCI6 VCI5 VCI4 VCI3 VCI2 VCI1 VCI0 PN5 PN4 PN3 PN2 PN1 PN0
6 11 VCI9 VCI8 VCI7 VCI6 VCI5 VCI4 VCI3 VCI2 VCI1 VCI0 PN5 PN4 PN3 PN2 PN1 PN0
6 12 VCI9 VCI8 VCI7 VCI6 VCI5 VCI4 VCI3 VCI2 VCI1 VCI0 PN5 PN4 PN3 PN2 PN1 PN0
6 13 VCI9 VCI8 VCI7 VCI6 VCI5 VCI4 VCI3 VCI2 VCI1 VCI0 PN5 PN4 PN3 PN2 PN1 PN0
6 14 VCI9 VCI8 VCI7 VCI6 VCI5 VCI4 VCI3 VCI2 VCI1 VCI0 PN5 PN4 PN3 PN2 PN1 PN0
6 15 VCI9 VCI8 VCI7 VCI6 VCI5 VCI4 VCI3 VCI2 VCI1 VCI0 PN5 PN4 PN3 PN2 PN1 PN0
6 16 VCI9 VCI8 VCI7 VCI6 VCI5 VCI4 VCI3 VCI2 VCI1 VCI0 PN5 PN4 PN3 PN2 PN1 PN0
7 0 VPI8 VPI7 VPI6 VPI5 VPI4 VPI3 VPI2 VPI1 VPI0 PN6 PN5 PN4 PN3 PN2 PN1 PN0
7 1 VPI7 VPI6 VPI5 VPI4 VPI3 VPI2 VPI1 VPI0 VCI0 PN6 PN5 PN4 PN3 PN2 PN1 PN0
7 2 VPI6 VPI5 VPI4 VPI3 VPI2 VPI1 VPI0 VCI1 VCI0 PN6 PN5 PN4 PN3 PN2 PN1 PN0
7 3 VPI5 VPI4 VPI3 VPI2 VPI1 VPI0 VCI2 VCI1 VCI0 PN6 PN5 PN4 PN3 PN2 PN1 PN0
7 4 VPI4 VPI3 VPI2 VPI1 VPI0 VCI3 VCI2 VCI1 VCI0 PN6 PN5 PN4 PN3 PN2 PN1 PN0
7 5 VPI3 VPI2 VPI1 VPI0 VCI4 VCI3 VCI2 VCI1 VCI0 PN6 PN5 PN4 PN3 PN2 PN1 PN0
7 6 VPI2 VPI1 VPI0 VCI5 VCI4 VCI3 VCI2 VCI1 VCI0 PN6 PN5 PN4 PN3 PN2 PN1 PN0
7 7 VPI1 VPI0 VCI6 VCI5 VCI4 VCI3 VCI2 VCI1 VCI0 PN6 PN5 PN4 PN3 PN2 PN1 PN0
7 8 VPI0 VCI7 VCI6 VCI5 VCI4 VCI3 VCI2 VCI1 VCI0 PN6 PN5 PN4 PN3 PN2 PN1 PN0
7 9 VCI8 VCI7 VCI6 VCI5 VCI4 VCI3 VCI2 VCI1 VCI0 PN6 PN5 PN4 PN3 PN2 PN1 PN0
7 10 VCI8 VCI7 VCI6 VCI5 VCI4 VCI3 VCI2 VCI1 VCI0 PN6 PN5 PN4 PN3 PN2 PN1 PN0
7 11 VCI8 VCI7 VCI6 VCI5 VCI4 VCI3 VCI2 VCI1 VCI0 PN6 PN5 PN4 PN3 PN2 PN1 PN0
7 12 VCI8 VCI7 VCI6 VCI5 VCI4 VCI3 VCI2 VCI1 VCI0 PN6 PN5 PN4 PN3 PN2 PN1 PN0
7 13 VCI8 VCI7 VCI6 VCI5 VCI4 VCI3 VCI2 VCI1 VCI0 PN6 PN5 PN4 PN3 PN2 PN1 PN0
7 14 VCI8 VCI7 VCI6 VCI5 VCI4 VCI3 VCI2 VCI1 VCI0 PN6 PN5 PN4 PN3 PN2 PN1 PN0
7 15 VCI8 VCI7 VCI6 VCI5 VCI4 VCI3 VCI2 VCI1 VCI0 PN6 PN5 PN4 PN3 PN2 PN1 PN0
7 16 VCI8 VCI7 VCI6 VCI5 VCI4 VCI3 VCI2 VCI1 VCI0 PN6 PN5 PN4 PN3 PN2 PN1 PN0
Prel. ABMP Data Sheet
Functional Descript ion
Preliminary Data Sheet 51 2001-14-01
PRELIMINARY
In case
the LCI is build by {VPI, PN} values only whereas the VPI range is given by
MNUM bits.
Note: Programming MNUM(3:0) = 0 is interpreted as decimal 16.
The foll owing t ables prov ide the po ssible LC I buildi ng patter ns for all PN UM and MNUM
configurations. The resulting LCI is internally treated the same way as in the LCI cell
header mapping modes, i.e. the two MSB’s are checked against the quarter segment
configuration that allows for cascading of up to 4 ABMP de vices.
Note: VPI cell header field and port number bit positions that are not mapped into the
LCI are checked against ‘0’. Mismatches are treated as ‘i nvalid LCI’ and the cell is
discarded.
VPI 110(,)2x1 with;x16MNUM–= for MNUM 0>
x0=for MNUM 0=
–≥
Prel. ABMP Data Sheet
Functional Descript ion
Preliminary Data Sheet 52 2001-14-01
PRELIMINARY
Figure 3-6 L CI Building Patterns (VPI only)
PNUMMNUM1514131211109876543210
0 1 111111111111111VPI0
0 2 11111111111111VPI1VPI0
0 3 1111111111111VPI2VPI1VPI0
0 4 111111111111VPI3VPI2VPI1VPI0
0 5 11111111111VPI4VPI3VPI2VPI1VPI0
0 6 1111111111VPI5VPI4VPI3VPI2VPI1VPI0
0 7 111111111VPI6VPI5VPI4VPI3VPI2VPI1VPI0
0 8 11111111VPI7VPI6VPI5VPI4VPI3VPI2VPI1VPI0
0 9 1 1 1 1 1 1 1 VPI8 VPI7 VPI6 VPI5 VPI4 VPI3 VPI2 VPI1 VPI0
0 10 1 1 1 1 1 1 VPI9 VPI8 VPI7 VPI6 VPI5 VPI4 VPI3 VPI2 VPI1 VPI0
0 11 1 1 1 1 1 VPI10 VPI9 VPI8 VPI7 VPI6 VPI5 VPI4 VPI3 VPI2 VPI1 VPI0
0 12 1 1 1 1 VPI11 VPI10 VPI9 VPI8 VPI7 VPI6 VPI5 VPI4 VPI3 VPI2 VPI1 VPI0
0 13 1 1 1 0 VPI11 VPI10 VPI9 VPI8 VPI7 VPI6 VPI5 VPI4 VPI3 VPI2 VPI1 VPI0
0 14 1 1 0 0 VPI11 VPI10 VPI9 VPI8 VPI7 VPI6 VPI5 VPI4 VPI3 VPI2 VPI1 VPI0
0 15 1 0 0 0 VPI11 VPI10 VPI9 VPI8 VPI7 VPI6 VPI5 VPI4 VPI3 VPI2 VPI1 VPI0
0 16 0 0 0 0 VPI11 VPI10 VPI9 VPI8 VPI7 VPI6 VPI5 VPI4 VPI3 VPI2 VPI1 VPI0
1 1 11111111111111VPI0PN0
1 2 1111111111111VPI1VPI0PN0
1 3 111111111111VPI2VPI1VPI0PN0
1 4 11111111111VPI3VPI2VPI1VPI0PN0
1 5 1111111111VPI4VPI3VPI2VPI1VPI0PN0
1 6 111111111VPI5VPI4VPI3VPI2VPI1VPI0PN0
1 7 11111111VPI6VPI5VPI4VPI3VPI2VPI1VPI0PN0
1 8 1 1 1 1 1 1 1 VPI7 VPI6 VPI5 VPI4 VPI3 VPI2 VPI1 VPI0 PN0
1 9 1 1 1 1 1 1 VPI8 VPI7 VPI6 VPI5 VPI4 VPI3 VPI2 VPI1 VPI0 PN0
1 10 1 1 1 1 1 VPI9 VPI8 VPI7 VPI6 VPI5 VPI4 VPI3 VPI2 VPI1 VPI0 PN0
1 11 1 1 1 1 VPI10 VPI9 VPI8 VPI7 VPI6 VPI5 VPI4 VPI3 VPI2 VPI1 VPI0 PN0
1 12 1 1 1 VPI11 VPI10 VPI9 VPI8 VPI7 VPI6 VPI5 VPI4 VPI3 VPI2 VPI1 VPI0 PN0
1 13 1 1 0 VPI11 VPI10 VPI9 VPI8 VPI7 VPI6 VPI5 VPI4 VPI3 VPI2 VPI1 VPI0 PN0
1 14 1 0 0 VPI11 VPI10 VPI9 VPI8 VPI7 VPI6 VPI5 VPI4 VPI3 VPI2 VPI1 VPI0 PN0
1 15 0 0 0 VPI11 VPI10 VPI9 VPI8 VPI7 VPI6 VPI5 VPI4 VPI3 VPI2 VPI1 VPI0 PN0
1 16 0 0 0 VPI11 VPI10 VPI9 VPI8 VPI7 VPI6 VPI5 VPI4 VPI3 VPI2 VPI1 VPI0 PN0
2 1 1111111111111VPI0PN1PN0
2 2 111111111111VPI1VPI0PN1PN0
2 3 11111111111VPI2VPI1VPI0PN1PN0
2 4 1111111111VPI3VPI2VPI1VPI0PN1PN0
2 5 111111111VPI4VPI3VPI2VPI1VPI0PN1PN0
2 6 11111111VPI5VPI4VPI3VPI2VPI1VPI0PN1PN0
2 7 1 1 1 1 1 1 1 VPI6 VPI5 VPI4 VPI3 VPI2 VPI1 VPI0 PN1 PN0
2 8 1 1 1 1 1 1 VPI7 VPI6 VPI5 VPI4 VPI3 VPI2 VPI1 VPI0 PN1 PN0
2 9 1 1 1 1 1 VPI8 VPI7 VPI6 VPI5 VPI4 VPI3 VPI2 VPI1 VPI0 PN1 PN0
2 10 1 1 1 1 VPI9 VPI8 VPI7 VPI6 VPI5 VPI4 VPI3 VPI2 VPI1 VPI0 PN1 PN0
2 11 1 1 1 VPI10 VPI9 VPI8 VPI7 VPI6 VPI5 VPI4 VPI3 VPI2 VPI1 VPI0 PN1 PN0
2 12 1 1 VPI11 VPI10 VPI9 VPI8 VPI7 VPI6 VPI5 VPI4 VPI3 VPI2 VPI1 VPI0 PN1 PN0
2 13 1 0 VPI11 VPI10 VPI9 VPI8 VPI7 VPI6 VPI5 VPI4 VPI3 VPI2 VPI1 VPI0 PN1 PN0
2 14 0 0 VPI11 VPI10 VPI9 VPI8 VPI7 VPI6 VPI5 VPI4 VPI3 VPI2 VPI1 VPI0 PN1 PN0
2 15 0 0 VPI11 VPI10 VPI9 VPI8 VPI7 VPI6 VPI5 VPI4 VPI3 VPI2 VPI1 VPI0 PN1 PN0
2 16 0 0 VPI11 VPI10 VPI9 VPI8 VPI7 VPI6 VPI5 VPI4 VPI3 VPI2 VPI1 VPI0 PN1 PN0
3 1 111111111111VPI0PN2PN1PN0
3 2 11111111111VPI1VPI0PN2PN1PN0
3 3 1111111111VPI2VPI1VPI0PN2PN1PN0
3 4 111111111VPI3VPI2VPI1VPI0PN2PN1PN0
3 5 11111111VPI4VPI3VPI2VPI1VPI0PN2PN1PN0
3 6 1 1 1 1 1 1 1 VPI5 VPI4 VPI3 VPI2 VPI1 VPI0 PN2 PN1 PN0
3 7 1 1 1 1 1 1 VPI6 VPI5 VPI4 VPI3 VPI2 VPI1 VPI0 PN2 PN1 PN0
3 8 1 1 1 1 1 VPI7 VPI6 VPI5 VPI4 VPI3 VPI2 VPI1 VPI0 PN2 PN1 PN0
3 9 1 1 1 1 VPI8 VPI7 VPI6 VPI5 VPI4 VPI3 VPI2 VPI1 VPI0 PN2 PN1 PN0
3 10 1 1 1 VPI9 VPI8 VPI7 VPI6 VPI5 VPI4 VPI3 VPI2 VPI1 VPI0 PN2 PN1 PN0
3 11 1 1 VPI10 VPI9 VPI8 VPI7 VPI6 VPI5 VPI4 VPI3 VPI2 VPI1 VPI0 PN2 PN1 PN0
3 12 1 VPI11 VPI10 VPI9 VPI8 VPI7 VPI6 VPI5 VPI4 VPI3 VPI2 VPI1 VPI0 PN2 PN1 PN0
3 13 0 VPI11 VPI10 VPI9 VPI8 VPI7 VPI6 VPI5 VPI4 VPI3 VPI2 VPI1 VPI0 PN2 PN1 PN0
3 14 0 VPI11 VPI10 VPI9 VPI8 VPI7 VPI6 VPI5 VPI4 VPI3 VPI2 VPI1 VPI0 PN2 PN1 PN0
3 15 0 VPI11 VPI10 VPI9 VPI8 VPI7 VPI6 VPI5 VPI4 VPI3 VPI2 VPI1 VPI0 PN2 PN1 PN0
3 16 0 VPI11 VPI10 VPI9 VPI8 VPI7 VPI6 VPI5 VPI4 VPI3 VPI2 VPI1 VPI0 PN2 PN1 PN0
Prel. ABMP Data Sheet
Functional Descript ion
Preliminary Data Sheet 53 2001-14-01
PRELIMINARY
Figure 3-7 L CI Building Patterns (VPI only) (cont.)
4 1 11111111111VPI0PN3PN2PN1PN0
4 2 1111111111VPI1VPI0PN3PN2PN1PN0
4 3 111111111VPI2VPI1VPI0PN3PN2PN1PN0
4 4 11111111VPI3VPI2VPI1VPI0PN3PN2PN1PN0
4 5 1 1 1 1 1 1 1 VPI4 VPI3 VPI2 VPI1 VPI0 PN3 PN2 PN1 PN0
4 6 1 1 1 1 1 1 VPI5 VPI4 VPI3 VPI2 VPI1 VPI0 PN3 PN2 PN1 PN0
4 7 1 1 1 1 1 VPI6 VPI5 VPI4 VPI3 VPI2 VPI1 VPI0 PN3 PN2 PN1 PN0
4 8 1 1 1 1 VPI7 VPI6 VPI5 VPI4 VPI3 VPI2 VPI1 VPI0 PN3 PN2 PN1 PN0
4 9 1 1 1 VPI8 VPI7 VPI6 VPI5 VPI4 VPI3 VPI2 VPI1 VPI0 PN3 PN2 PN1 PN0
4 10 1 1 VPI9 VPI8 VPI7 VPI6 VPI5 VPI4 VPI3 VPI2 VPI1 VPI0 PN3 PN2 PN1 PN0
4 11 1 VPI10 VPI9 VPI8 VPI7 VPI6 VPI5 VPI4 VPI3 VPI2 VPI1 VPI0 PN3 PN2 PN1 PN0
4 12 VPI11 VPI10 VPI9 VPI8 VPI7 VPI6 VPI5 VPI4 VPI3 VPI2 VPI1 VPI0 PN3 PN2 PN1 PN0
4 13 VPI11 VPI10 VPI9 VPI8 VPI7 VPI6 VPI5 VPI4 VPI3 VPI2 VPI1 VPI0 PN3 PN2 PN1 PN0
4 14 VPI11 VPI10 VPI9 VPI8 VPI7 VPI6 VPI5 VPI4 VPI3 VPI2 VPI1 VPI0 PN3 PN2 PN1 PN0
4 15 VPI11 VPI10 VPI9 VPI8 VPI7 VPI6 VPI5 VPI4 VPI3 VPI2 VPI1 VPI0 PN3 PN2 PN1 PN0
4 16 VPI11 VPI10 VPI9 VPI8 VPI7 VPI6 VPI5 VPI4 VPI3 VPI2 VPI1 VPI0 PN3 PN2 PN1 PN0
5 1 1111111111VPI0PN4PN3PN2PN1PN0
5 2 111111111VPI1VPI0PN4PN3PN2PN1PN0
5 3 11111111VPI2VPI1VPI0PN4PN3PN2PN1PN0
5 4 1 1 1 1 1 1 1 VPI3 VPI2 VPI1 VPI0 PN4 PN3 PN2 PN1 PN0
5 5 1 1 1 1 1 1 VPI4 VPI3 VPI2 VPI1 VPI0 PN4 PN3 PN2 PN1 PN0
5 6 1 1 1 1 1 VPI5 VPI4 VPI3 VPI2 VPI1 VPI0 PN4 PN3 PN2 PN1 PN0
5 7 1 1 1 1 VPI6 VPI5 VPI4 VPI3 VPI2 VPI1 VPI0 PN4 PN3 PN2 PN1 PN0
5 8 1 1 1 VPI7 VPI6 VPI5 VPI4 VPI3 VPI2 VPI1 VPI0 PN4 PN3 PN2 PN1 PN0
5 9 1 1 VPI8 VPI7 VPI6 VPI5 VPI4 VPI3 VPI2 VPI1 VPI0 PN4 PN3 PN2 PN1 PN0
5 10 1 VPI9 VPI8 VPI7 VPI6 VPI5 VPI4 VPI3 VPI2 VPI1 VPI0 PN4 PN3 PN2 PN1 PN0
5 11 VPI10 VPI9 VPI8 VPI7 VPI6 VPI5 VPI4 VPI3 VPI2 VPI1 VPI0 PN4 PN3 PN2 PN1 PN0
5 12 VPI10 VPI9 VPI8 VPI7 VPI6 VPI5 VPI4 VPI3 VPI2 VPI1 VPI0 PN4 PN3 PN2 PN1 PN0
5 13 VPI10 VPI9 VPI8 VPI7 VPI6 VPI5 VPI4 VPI3 VPI2 VPI1 VPI0 PN4 PN3 PN2 PN1 PN0
5 14 VPI10 VPI9 VPI8 VPI7 VPI6 VPI5 VPI4 VPI3 VPI2 VPI1 VPI0 PN4 PN3 PN2 PN1 PN0
5 15 VPI10 VPI9 VPI8 VPI7 VPI6 VPI5 VPI4 VPI3 VPI2 VPI1 VPI0 PN4 PN3 PN2 PN1 PN0
5 16 VPI10 VPI9 VPI8 VPI7 VPI6 VPI5 VPI4 VPI3 VPI2 VPI1 VPI0 PN4 PN3 PN2 PN1 PN0
6 1 111111111VPI0PN5PN4PN3PN2PN1PN0
6 2 11111111VPI1VPI0PN5PN4PN3PN2PN1PN0
6 3 1 1 1 1 1 1 1 VPI2 VPI1 VPI0 PN5 PN4 PN3 PN2 PN1 PN0
6 4 1 1 1 1 1 1 VPI3 VPI2 VPI1 VPI0 PN5 PN4 PN3 PN2 PN1 PN0
6 5 1 1 1 1 1 VPI4 VPI3 VPI2 VPI1 VPI0 PN5 PN4 PN3 PN2 PN1 PN0
6 6 1 1 1 1 VPI5 VPI4 VPI3 VPI2 VPI1 VPI0 PN5 PN4 PN3 PN2 PN1 PN0
6 7 1 1 1 VPI6 VPI5 VPI4 VPI3 VPI2 VPI1 VPI0 PN5 PN4 PN3 PN2 PN1 PN0
6 8 1 1 VPI7 VPI6 VPI5 VPI4 VPI3 VPI2 VPI1 VPI0 PN5 PN4 PN3 PN2 PN1 PN0
6 9 1 VPI8 VPI7 VPI6 VPI5 VPI4 VPI3 VPI2 VPI1 VPI0 PN5 PN4 PN3 PN2 PN1 PN0
6 10 VPI9 VPI8 VPI7 VPI6 VPI5 VPI4 VPI3 VPI2 VPI1 VPI0 PN5 PN4 PN3 PN2 PN1 PN0
6 11 VPI9 VPI8 VPI7 VPI6 VPI5 VPI4 VPI3 VPI2 VPI1 VPI0 PN5 PN4 PN3 PN2 PN1 PN0
6 12 VPI9 VPI8 VPI7 VPI6 VPI5 VPI4 VPI3 VPI2 VPI1 VPI0 PN5 PN4 PN3 PN2 PN1 PN0
6 13 VPI9 VPI8 VPI7 VPI6 VPI5 VPI4 VPI3 VPI2 VPI1 VPI0 PN5 PN4 PN3 PN2 PN1 PN0
6 14 VPI9 VPI8 VPI7 VPI6 VPI5 VPI4 VPI3 VPI2 VPI1 VPI0 PN5 PN4 PN3 PN2 PN1 PN0
6 15 VPI9 VPI8 VPI7 VPI6 VPI5 VPI4 VPI3 VPI2 VPI1 VPI0 PN5 PN4 PN3 PN2 PN1 PN0
6 16 VPI9 VPI8 VPI7 VPI6 VPI5 VPI4 VPI3 VPI2 VPI1 VPI0 PN5 PN4 PN3 PN2 PN1 PN0
7 0 VPI9 VPI8 VPI7 VPI6 VPI5 VPI4 VPI3 VPI2 VPI1 VPI0 PN5 PN4 PN3 PN2 PN1 PN0
7 1 11111111VPI0PN6PN5PN4PN3PN2PN1PN0
7 2 1 1 1 1 1 1 1 VPI1 VPI0 PN6 PN5 PN4 PN3 PN2 PN1 PN0
7 3 1 1 1 1 1 1 VPI2 VPI1 VPI0 PN6 PN5 PN4 PN3 PN2 PN1 PN0
7 4 1 1 1 1 1 VPI3 VPI2 VPI1 VPI0 PN6 PN5 PN4 PN3 PN2 PN1 PN0
7 5 1 1 1 1 VPI4 VPI3 VPI2 VPI1 VPI0 PN6 PN5 PN4 PN3 PN2 PN1 PN0
7 6 1 1 1 VPI5 VPI4 VPI3 VPI2 VPI1 VPI0 PN6 PN5 PN4 PN3 PN2 PN1 PN0
7 7 1 1 VPI6 VPI5 VPI4 VPI3 VPI2 VPI1 VPI0 PN6 PN5 PN4 PN3 PN2 PN1 PN0
7 8 1 VPI7 VPI6 VPI5 VPI4 VPI3 VPI2 VPI1 VPI0 PN6 PN5 PN4 PN3 PN2 PN1 PN0
7 9 VPI8 VPI7 VPI6 VPI5 VPI4 VPI3 VPI2 VPI1 VPI0 PN6 PN5 PN4 PN3 PN2 PN1 PN0
7 10 VPI8 VPI7 VPI6 VPI5 VPI4 VPI3 VPI2 VPI1 VPI0 PN6 PN5 PN4 PN3 PN2 PN1 PN0
7 11 VPI8 VPI7 VPI6 VPI5 VPI4 VPI3 VPI2 VPI1 VPI0 PN6 PN5 PN4 PN3 PN2 PN1 PN0
7 12 VPI8 VPI7 VPI6 VPI5 VPI4 VPI3 VPI2 VPI1 VPI0 PN6 PN5 PN4 PN3 PN2 PN1 PN0
7 13 VPI8 VPI7 VPI6 VPI5 VPI4 VPI3 VPI2 VPI1 VPI0 PN6 PN5 PN4 PN3 PN2 PN1 PN0
7 14 VPI8 VPI7 VPI6 VPI5 VPI4 VPI3 VPI2 VPI1 VPI0 PN6 PN5 PN4 PN3 PN2 PN1 PN0
7 15 VPI8 VPI7 VPI6 VPI5 VPI4 VPI3 VPI2 VPI1 VPI0 PN6 PN5 PN4 PN3 PN2 PN1 PN0
7 16 VPI8 VPI7 VPI6 VPI5 VPI4 VPI3 VPI2 VPI1 VPI0 PN6 PN5 PN4 PN3 PN2 PN1 PN0
Prel. ABMP Data Sheet
Functional Descript ion
Preliminary Data Sheet 54 2001-14-01
PRELIMINARY
3.2.6 Queue Congestion Indication Unit
Some system implementations are based on in-system flow control mechanisms that
require per queue (i.e. typically per connection) congestion indication information from
the downstream queues. As an example a traffic management optimized IP over ATM
implementation requires a control link between the ATM traffic management and the
packet scheduling unit.
Queue status information can generally be obtained by reading the Queue Configuration
Table (QCT). For a large number of queues (e.g. 8k) and typical time constraints of
control loop mechanisms, a software based queue monitoring is not feasible.
The Queue Congestion Indication interface (QCI) is a serial interface providing a bit
pattern with queu e specific threshol d exceed information. Each bit repr esents the queue
number corresp onding to the bit position. A ‘1’ mea ns congestion, i .e. the queue specific
threshold is currently exceeded. The bit-pattern is generated with a minimum HDLC
framing and can be limited to 1024, 2048, 4096 or 8192 bits payload depending on the
number of queues that need to be monitored.
Global confi guration of the QCI u nit is perform ed in register “DQCIC” on Page 187. The
queue specific thresholds are programmed in table QCIT via transfer register “QCIT” on
Page 244.
3.2.7 Clocking System
The clocking system of the ABMP distinguishes 3 major functional clock domains. The
core clock, the ERC core clock and the UTOPIA interfaces whereas each UTOPIA
interface and direction (transmit/receive) is clocked independently as shown in Figure 3-
8.
The ERC core clock can be derived internally from either the SYSCLK signal or the
internal core clock. Programmable DPLL’s allow for a wide range of external clocks to
derive the required core clocks.
In addition to the major clock domains, the serial interfaces SPI and QCI are also clocked
independently.
Prel. ABMP Data Sheet
Functional Descript ion
Preliminary Data Sheet 55 2001-14-01
PRELIMINARY
3.2.7.1 Clocking System Overview
Figure 3-8 Clocking System Overview
3.2.7.2 DPLL Programming
DPLL1 and DPLL2 are identical function blocks with identical programming interfaces.
Each DPPL features 2 factors programmed by parameters m and n in registers
“PLL1CONF” on Page 296 and “PLL2CONF” on Page 298 respectively:
ABM
Core
Logic
UTOPIA
ATM
transmit
UTOPIA
ATM
receive
UTOPIA
PHY
transmit
UTOPIA
PHY
receive
ERC
Unit
internal ABM
core clock
internal ERC
unit clock
UTXCLKU
UTXCLKD
SYSCLK
URXCLKU
URXCLKD
DPLL2
Devider1
Bypass2
DPLL1
Devider1
Devider2
Bypass1
ERCFREQSEL
SYSCLKSEL
Note:
Testmodi are not illust rated in this fi
g
ure.
ERCCLK
ERCCLKSEL
’alternative
ERC cl ock ’
asynchr./synchr.
Prel. ABMP Data Sheet
Functional Descript ion
Preliminary Data Sheet 56 2001-14-01
PRELIMINARY
Figure 3-9 DPLL Structure
The division factor determi ned by m must be choosen such, that i ntermediate freque ncy
f1 is in the range 2..15 MHz based on the input frequency at signal ‘SYSCLK’.
The multiplication factor determined by n must be choosen such, that intermediate
frequency f2 is equal or twice the final value in case of DPLL2 and twice or 4 times the
final value in case of DPLL1.
Finally the divisio n by 2 factor may be enabled i n case of DPLL2 and one or two division
by 2 factors in case of DPLL1 to achieve the final clock frequency.
3.2.7.3 Programming Example
Follow in g number s are assumed f or this exa mpl e:
• ABMP internal core clock: 80 MH z
• ABMP Enhanced Rate Control (ERC) clock: 100 MHz
• Clock supply: 52 MHz at signal SYSCLK
In this example signal SYSCLKSEL must be connected to VSS to connect the internal
core clock to the DPLL1 output. Signal ERCCLKSEL must be connected to VSS to
connect the alternative ERC clock to the DPLL2 output. Signal ERCFREQSEL must be
connected to VDD to connect the internal ERC core clock to the alternative ERC clock
(which is DPLL2 output in this example). (Please refer to Figure 3-8)
f2fin n1+
m1+
--------------×=
1
(m + 1)
f
in
(n + 1)
f
1
2..15 MHz 1/2 1/2XX
f
2
f
out
X
(1)
(0)
(1)
(0)
(1)
(0)
LockediDev2EniDev1EniBypassi PUi RESi
Mi(3:0) Ni(5:0)
Register PLLCONFi (i=1,2)
15 0
Prel. ABMP Data Sheet
Functional Descript ion
Preliminary Data Sheet 57 2001-14-01
PRELIMINARY
DPLL1 Programming
A reasonable value for par ameter M 1 in register “PLL1CONF” on Page 296 is M1 = 12
which results in
f1 = 52 MHz / (12 + 1) = 4 MHz.
Now a possible value for param eter N1 is N1 = 39 which result s in
f2 = 4 MHz * (39 + 1) = 160 MHz.
To achieve the 80 MHz core clock devision factor 1 shall be enabled.
Thus for this example the value 3B27H must be programmed to register PLL1CONF.
Note: Multiple combinations of parameters are possible to achieve a 80 MHz clock in
this example.
DPLL2 Programming
A reasonable value for par ameter M 2 in register “PLL2CONF” on Page 298 is M2 = 12
which results in
f2 = 52 MHz / (12 + 1) = 4 MHz.
Now a possible value for param eter N2 is N2 = 24 which result s in
f2 = 4 MHz * (24 + 1) = 100 MHz.
The devision factor shall be disabled to maintain the 100 MHz clock frequency.
Thus for this example the value 1B1DH must be programmed to register PLL2CONF.
Note: Multiple combinations of parameters are possible to achieve a 100 MHz clock in
this example.
3.2.7.4 Initialization Phase
After power-on reset, both DPLLs are in bypass mode which means that signal
‘SYSCLK’ is directly feeding the internal core clock and internal ERC core clock. After
basic configuration at least of the DPLL configuration registers, the bypass can be
disabled which will glitch-free adjust the internal clocks to the selected frequency.
3.2.8 Reset System
The ABMP provides 3 different reset sources as shown in Figure 3-10. The hardware
signal RE SET effects t he e nti re devic e incl uding the m icropr ocessor i nterface. The sel f-
clearing soft ware reset bit ‘SWRES’ in register “MODE1” on Page 321 effects the entire
device except the microprocessor interface. The software reset bit ‘ERCSWRES’ in
register “MODE1” on Page 321 effects only the ERC unit. This bit is not self-clearing
and allows the entire ERC unit to be kept in reset state while the rest of the device is
working.
Hardware reset as well as software reset bit ‘SWRES’ completely initialize the device
into power-on reset state.
Prel. ABMP Data Sheet
Functional Descript ion
Preliminary Data Sheet 58 2001-14-01
PRELIMINARY
Figure 3-10 Reset System Overview
Note: Initialization of external and internal RAMs must be started by software via
command bits ‘INITRAM’ and ‘INITSDRAM’ in register
“MODE1” on Page 321
following the device reset.
3.3 System Integration
The ABMP has two operational modes: Bi-directional Mode and Uni-directional Mode.
The directi onal te rminology for th e modes refers to the usage of the ABMP cores, not to
the connections. The connections are bi-directional in all cases. In Bi-directional Mode,
one ABMP core is used exclusively for the cells of a connection in the upstream direction
and the other core exclusively handles cells of the same connection in the downstream
direction. In Uni-directional Mode, only one core always will be used to handle the cells
of a connection both in up- and downstream direction. The two basic applications for
these modes are the switch port line card application and the mini-switch, respectively.
SDRAM Interface (up)
Cell Handler (CH) upstream
SDRAM Interface (dn)
Cell Handler (CH) downstream
Queue
Manager
(QM)
Scheduler
Block
(SB)
ERC
SSRAM IF
UTOPIA IF (Backplane Side)
UTOPIA IF (PHY Side)
BSCAN/
SPI
uP IF
AAL5
Test/
Clocks
ARC
ARC
QCI IF
RESET
SWRES ERC
SWRES
bit 15 bit 14
Register ’MODE1’
Prel. ABMP Data Sheet
Functional Descript ion
Preliminary Data Sheet 59 2001-14-01
PRELIMINARY
On a typical switch port line card, both the upstream and downstream cell flow pass
through the same ABMP device. One ABMP Core is used for each direction as shown
in Figure 3-11.
Figure 3-11 ABMP in Bi-directional Mode
The ABMP assumes that all connections are setup bi-directionally with the same Local
Connection Identifier (LCI) in both directions. In the Infineon ATM chip set environment,
the LCI is provided by the PXB 4350 E ALP and contains VPI, VCI, and PHY information.
If the ABMP is n ot used wi th the AL P, i t can o per ate o n VPI o r VCI i den tif ier s only usi ng
the internal Address Reduction Circuit.
In a mini-switch application, the throughput is only one times 622 Mbit/s. Only the
UTOPIA Receive and Transmit interface PHY-side are active. Both ABMP Cores are
selected from the multiplexer options shown in Figure 3-12. Each cell is forwarded to
both ABMP Cores; but, the LCI table entry for the connection determines which of the
two Cores accepts the cell. The other Core ignores it. Thus, each cell is stored and
queued in one of the two Cores. The cell streams of both Cores are multiplexed together
at the output. The schedulers must be programmed such that the sum of all outp ut rates
does not exceed the maximum rate supported by the UTOPIA transmit interface.
SSRAM interface
UTOPIA
upstream
receive
MASTER
mP interface JTAG interfaceSDRA M interface
SDRA M interface
UTOPIA
downstr.
receive
SLAVE
UTOPIA
upstream
transmit
SLAVE
UTOPIA
downstr.
transmit
MASTER
ABM Core
upstream
ABM Core
downstream
common
LCI Table
Prel. ABMP Data Sheet
Functional Descript ion
Preliminary Data Sheet 60 2001-14-01
PRELIMINARY
Figure 3-12 ABMP in Uni-directional Mode Using both Cores
If the resources of one Core are sufficient, the downstream Core can be deactivated (see
Figure 3-13). This reduces the power consumption and allows omission of the external
downstream SDRAM. It also permits the SSRAM to be smaller (see below).
Figure 3-13 ABMP in Uni-directional Mode Using one Core
SSRAM interface
UTOPIA
upstream
receive
MASTER
mP interface
SDRA M interface
UTOPIA
downstr.
transmit
MASTER
ABM Core
upstream
common
LCI Table
JTAG interface
UTOPIA
downstr.
receive
SLAVE
UTOPIA
upstream
transmit
SLAVE
SDRA M interface
ABM Core
downstream
SSRA M interface
UTOPIA
upstream
receive
MASTER
mP interface
SDRAM interface
UTOPIA
downstr.
transmit
MASTER
ABM Core
upstream
common
LCI Table
JTAG in terfaceSDRAM interface
UTOPIA
downstr.
receive
SLAVE
ABM Core
downstream
UTOPIA
upstream
transmit
SLAVE
Prel. ABMP Data Sheet
Functional Descript ion
Preliminary Data Sheet 61 2001-14-01
PRELIMINARY
3.3.1 LCI Tran slation in Mini-Switch Configurations
In Uni-directional applications, the ABMP can be programmed to make a minimum head-
er translation. This is necessary in a Mini-Switch configuration as both the forward and
backward direct ion of a connection traverse the device s in the same direction. The OAM
functions in the ALP or AOP device need the same LCI for forward and backward direc-
tion of a connection.
This is clarified by the example shown in Figure 3-14 in which a connection is setup from
PHY1 to PHY2. VPI/VCI1 is the identifier on the transmission line where PHY1 is connect-
ed. The terminal sends ATM cells with this identifier and expects cells in the backward
direction from PHY2 with the same identifier. The ALP in the upstream direction trans-
lates VPI/VCI1 into LCI1, the unique local identifier for this connection in the upstream
direction. Similarly, for the backward connection from PHY2 to PHY1, the ALP receives
ATM cells from PHY2 with the identifier VPI/VCI2 and translates them into LCI2.
Figure 3-14 Connection Identifiers in Mini-Switch Configuration
For minimum complexity, the header translation of the ABMP is done by inverting the
Least Significant Bit (L SB) of the LCI. This measure divides the available LC I range into
two parts:
odd
LCI values for forward connections and
even
LCI values for backward
connection (or vice-versa), i.e. it reduces the available number of connection identifiers
to 8192, because two LCI values are used per connection.
C U d ec o a odes
ALP
ABM (uni-direc tional mode)
AOP
VPI/VCI1
LCI1LCI1
VPI/VCI2
LCI2LCI2
LCI1LCI1
LCI2LCI2
Cores
HT = Header Translation
LCI = Local Connection Identifier
HT
HT
LCI=
LCI+/-1
Phy 1
Phy 2
Prel. ABMP Data Sheet
Functional Descript ion
Preliminary Data Sheet 62 2001-14-01
PRELIMINARY
This is not a restriction in the case of arbitrary addr ess reduct ion modes as, for exampl e,
the ALP with the CAME chip , as ATM connections ar e always setup bi-directio nally with
the same VPI/VCI in both directions of a link.
Note: In case of fixed address reduction, as, for example, the ALP with the built-in Ad-
dress Reduction Circuit (ARC), the usable LCI range may be seriously restricted,
depending on the PHY configuration.
Prel. ABMP Data Sheet
Functional Descript ion
Preliminary Data Sheet 63 2001-14-01
PRELIMINARY
3.4 Detailed Queue Manager and Scheduler Block Description
This chapter provides more detailed information about scheduling and queuing (cell
acceptance) functions.
Figure 3-15 Cell Acceptance and Scheduling
3.4.1 The Scheduler
One of the basic building blocks of the ABMP is the scheduling unit that ser ves as a co-
processing unit to the Queue Manager. A single scheduler entity is a cascade of two mul-
tiplexer levels. A Weighted Fair Queuing (WFQ) Multiplexer and two Round Robbin (RR)
Multiplexers built the first level aggregating to a second level priority multiplexer as
shown in Figure 3-16. An arbitrary number of queues can be assigned to each first level
multiplexer.
W
F
Q
R
R
R
R
(1)
(2)
(3)
Scheduler 1
Sche duler 2
Sche duler j
Scheduler 16
Sche duler 15
MUX
DEMUX
Queue Manager
Scheduler Block
Cell Acceptance
Algorithm
accept
discard
Denotes an optional per queue Peak Rate Shaper (PCR)
Denotes an absolute per scheduler rate
Prel. ABMP Data Sheet
Functional Descript ion
Preliminary Data Sheet 64 2001-14-01
PRELIMINARY
Figure 3-16 Scheduler Structure
One RR scheduler is provided for real-time connections. It is connected to the highest
priority input of the Priority Multiplexer (marked with the arrow symbol). The 3-input Pri-
ority Multiplexer first accepts cells from the high-priority input and only if there is no cell
offered it continues looking for the WFQ multiplexer connected with the second priority.
Thus, real-time traffic is always prioritized. As the output rate of the Scheduler is limited
- as denoted in Figure 3-16 with the bubble symbol at the Priority Multiplexer output - the
non-real-time connections share the remaining bandwidth. This behavior is shown in
Figure 3-17. The low priority round robbin multiplexer is only served in case neither real-
time nor the WFQ offers a cell within a cell cycle.
W
F
Q
Scheduler #j
scheduler output rate
w
0
w
1
w
2
w
3
w
i
: WFQ Weight Factor
optional PCR or VBR Shaper
Real-Time Traffic
Non-Real-Time Traffic
Low Priority
Non-Real-Time Traffic
Prel. ABMP Data Sheet
Functional Descript ion
Preliminary Data Sheet 65 2001-14-01
PRELIMINARY
Figure 3-17 Scheduler Behavior
The WFQ multiplexer permits sharing of the remaining bandwidth by the non-real-time
connections. The WFQ multiplexer has a maximum of 8192 inputs with a weight factor
assigned to each input. It distr ibutes the remaining band width among acti ve or occupied
queues according to the weight factors.
The WFQ multiplexer has the following properties:
• Fair distribution of bandwidth
• Guaranteed Quality of Service (QoS) for each connection (minimum service rate,
bounded delay)
• Load conserving, that is, the output is always 100%
• Protection against misbehaving connections (exceeding their bandwidth budget).
These are important, for e xample, in data connections having start-stop behavior. An ex-
ample is show n in Figure 3-18. The duration of the da ta bursts and the idle pe riods vary
over a wide range.
Figure 3-18 Data Traffic Example
For non-r eal-tim e connections, n ormally one queue is assigned to each conn ection, that
is, per-VC queuing. During idle periods, the queues will run empty, and, when a data
burst is sent, they fill up again. The WFQ multiplexer automatically deals with the varying
bandwidth
output rate
real time connections
(high priority)
non-real time
connections
(low priority)
bit rate
time
Prel. ABMP Data Sheet
Functional Descript ion
Preliminary Data Sheet 66 2001-14-01
PRELIMINARY
load situation s and al ways distr ibutes th e bandwidth according to the weight factors. An
example of a Scheduler with one real-time queue (Queue 1) and nine non-real-time
queues (Queue 2 through Queue 10) is shown in Figure 3-19. Queue 1 is shared by a
number of connections with different bit rates.
Figure 3-19 Scheduler Behavior Example
The le ft column in Figure 3-19 shows the Scheduler load as seen from Connection Ac-
ceptance Control (CAC). New connections are accepted as long as their guaranteed
rates fit the spare bandwidth of the Scheduler. "Guaranteed rate" is defined below.
The center column shows the case in which all Queues 2..10 are filled; that is, all non-
real time connecti ons are sending data. The to tal non-re al-time b andwidth, inclu ding the
spare bandwidth, is then distributed to the 9 queues according to their weight. In this
case, two weight factors are defined, 1 and 10.
The right column shows the case of only three queues (6, 7 and 9) filled; all other con-
nections are not sending data at this time. Again, the available bandwidth is fairly
distributed among the queues, still conserving the 1:10 ratio defined by their weights.
Notice that bandwidth of the real-time connections is not affected by bandwidth re-ad-
justments; but, remains constant over time under the assumption that real-time
connections are constant ly sending data. If, however, a real-time connect ion shoul d not
use its bandwidth, the bandwidth would be used immediately by the non-real-time con-
nections. The behavior shown in Figure 3-19 of the WFQ Multiplexer for non-real-time
connections has advantages for both the network operator and for the end user:
connection setup
with guaranteed
cell rates
not reserved
bandwidth
distributed
spare
bandwidth
Scheduler
bandwidth
10
9
8
7
6
1
5
4
3
2
9
7
6
1
6
1
5
4
3
2
unused
bandwidth distributed
10
9
8
7
real time
traffic
Prel. ABMP Data Sheet
Functional Descript ion
Preliminary Data Sheet 67 2001-14-01
PRELIMINARY
• The available bandwidth is always used completely, resulting in optimum usage of
transmission resources
• A user paying for a higher guaranteed rate also obtains higher throughput under all
load conditions.
Guaranteed Rate
The guaranteed rate is the rate which the network must guarantee the user at any time.
3.4.2 Scheduler Usage
The ABMP chip allows arbitrary assignment of connections to queues and of queues to
Schedulers. A Scheduler can be assigned to any UTOPIA PHY. Usage of a Scheduler
differs in swit ch input (ingr ess) or output (eg ress). For the Mini- Switch applicati on the in-
gress case does not exist.
At a switch output, the Schedulers provide constant cell streams to fill the payloads of
the PHYs. Either the entire cell stream of a PHY is provided or it is disassembled into
several VPCs as shown in Figure 3-20. A VPC may contain both real-time and data con-
nections. This is the case for a VPC which connects two corporate networks (virtual
private networ ks), for example. The scheduler concept has the advan tage that data traf-
fic is automatically adjusted after setup or teardown of a real-time connection. The output
rate of a Scheduler in both applications is usually constant.
The schedulers always react to UTOPIA backpressure or can be controlled completely
by backpressure instead of shaping. All Schedulers whose physical outputs are assert-
ing backpressure are hold on serving. S cheduler serving tim e slots which ar e lost d ue to
temporary b ackpressure a re mainta ined and served later, if possible . Therefore, the r ate
with some CDV will be maintained. The maximum number of stored time slots which can
be configured is equal to the maximum burst possible for that port or path.
Table 3-1 Guaranteed Rates for each Traffic Class
Traffic Class Guaranteed Rate Comment
CBR PCR
VBR-rt SCR...PCR Guaranteed rate can be chosen below
PCR for stat istical m ultiplexing gain
VBR-nrt SCR
ABR MCR (CCR in ABR VS/VD)
UBR+ MCR
UBR none Guaranteed rate is always > 0 with queue
connected to the WFQ multiplexer
Prel. ABMP Data Sheet
Functional Descript ion
Preliminary Data Sheet 68 2001-14-01
PRELIMINARY
Figure 3-20 Scheduler Usage at Switch Output
At a switch i nput , each Schedul er is assign ed t o a swi tch output (Figure 3-21). A switch
with n ports needs n2 Schedulers. Th e output rate of each Schedul er is re-adjusted con-
tinuously to obtain maximum switch throughput without overloading the switch port
output rate. This principle is called Preemptive Congestion Control, that is, congestion
due to overload is avoided.
PHY 1
Switch
Fabric* Switch Port
(ABM) PHY
bottleneck
155 Mbps
PHY
155 Mbps
PHY n
VPC1
bottleneck
VPC2
bottleneck
= Scheduler
* no Switch Fabric for
Work group Switch
Prel. ABMP Data Sheet
Functional Descript ion
Preliminary Data Sheet 69 2001-14-01
PRELIMINARY
Figure 3-21 Scheduler Usage at Switch Input
There are three options for Scheduler rate adjustment:
• After each connection setup or teardown (static bandwidth allocation).
• Dynamic bandwidth allocation using Input Scheduler Buffer fill information to assign
Scheduler rates dynamically.
• Backpressure controlled.
Port 1
Port n
Port 1 (ABM)
Port n
swit c h egr es s port
bottleneck
622 Mbps
swit c h egr es s port
bottleneck
622 Mbps
= Scheduler
Switch
Fabric
switch ingress port
bottlenecks
622 Mbps
R1,n
Rn,1
R1,1
Rn,n
Ri,j = Rate from Port i to Port j
Prel. ABMP Data Sheet
Functional Descript ion
Preliminary Data Sheet 70 2001-14-01
PRELIMINARY
3.4.3 Quality of Service Class Support
As well as rate guarantees, the support of Quality of Service (QoS) classes (Traffic
Classes) is related closely to the threshold-based cell acceptance algorithm. One set of
thresholds for each QoS class is programmed in the traffic class table (see also
Figure 3-23). The ABMP provides 16 sets of traffic classes per direction. Each traffic
class can be configured according to the required behavior and is not pre-defined or
fixed to the standard ATM service classes. This allows for configuration of generic or new
service classes (e.g. Packet Hop Behavior classes).
The traffic class table contains the following thresholds (please refer to “Threshold
Overview” on Page 72 for a numeric desription of the thresholds):
1. Maximum non-real time cells in the entire buffer
2. EPD threshold for non-real-time cells in the entire buffer
3. Multi purpose threshold
A) Maximum stored cells in each queue of this traffic class (if EPD disabled)
or
B) The EPD threshold for each queue of this traffic class (if EPD enabled)
4. Multi purpose threshold
A) Threshold for each queue of the traffic class where the Congestion Indication (CI)
for ABR traffic is set
and
B) Threshold where low priority cells (CLP=1) are not accepted (if the CLP transparent
flag CLPT is set for the connection)
C) Queue EPD thr eshol d for GFR ( CLPT is false). EPD is triggered if both threshold s
4C and 2 are exceeded.
5. Threshold for the maximum number of cells of this traffic class that can be buffe red
6. Multi purpose threshold for the scheduler occupancy
A) maximum number of cells in the scheduler if EPD not enabled
or
B) EPD threshold for cells in the scheduler if EPD enabled
or
C) ABR congestion indication (EFCI, CI) if ABR is enabled
Note: All m aximum thresholds are automatically also PPD thresholds, that is, i f the max-
imum fill value is reached, PPD is started if enabled. If PPD is not enabled, cells
are discarded if the threshold is reached.
Also a configurable hysteresis is applied to all maximum thresholds if PPD is not
enabled.
Figure 3-22 shows the independent assignment of queue s to traffic classes and sched-
ulers. Because schedulers fulfill the logical switching function by assignment of
schedulers to U TOPIA por ts, they are i ndepen dent of the QoS cl ass r epre sented by the
traffic class table.
Prel. ABMP Data Sheet
Functional Descript ion
Preliminary Data Sheet 71 2001-14-01
PRELIMINARY
Figure 3-22 Queue Grouping
Examples of traffic classes are
• Real-time traffic
• LAN emulation traffic
• Internet (IP) traffic
Figure 3-23 shows an example of threshold configurations for four traffic classes.
Figure 3-23 Example of Threshold Configuration
Scheduler 1
d
e
m
u
x
W
F
Q
W
F
Q
Scheduler 48
Traffic
class 1 Traffic
class 2 Traffic
clas s 16
VBR PPD = Buffer Size-256
ABR PPD
ABR EPD
UBR PPD
UBR EPD
guaranteed
buffer space
for VBR guaranteed
buffer space
for ABR+VBR
new UBR packets are not accepted
new ABR packets are
not accepted
buffer
fill 4 traffic classes: UBR, ABR, VBR, real time
Total Buffer Size
guaranteed 256 cells for real time
Prel. ABMP Data Sheet
Functional Descript ion
Preliminary Data Sheet 72 2001-14-01
PRELIMINARY
3.4.4 EPD/PPD Handling
These functions can be enabled individuall y per traffic class. The dyn amic flags of these
functions are stored in the connection specific (LCI ) table. For both functions, the ABMP
looks at the PTI bit of the ATM cells to determine the packet borders.
EPD Threshold Behavior
If the buffer fill level exceeds an EPD threshold and EPD is enabled, new packets will not
be accepted but will be discarded completely. Cells belonging to packets which have
been transmitted partially are accepted.
PPD Threshold Behavior
If the ce ll fill exceeds a PPD (=max) thresho ld, the next cel l is dis carded a nd, if PPD is
enabled, all subsequent cells of the packet are discarded except the last cell. The sub-
sequent cells are discarded even if the cell fill might have dropped below the PPD
threshold in the meantime. The last cell is accepted again to convey the discard informa-
tion to the ter minal (cell acceptance is possible only if the qu eue fill level dropped bel ow
the threshold in the meantime). By checking the CRC-32 checksum of AAL5, the termi-
nal can determine rapidly that cells were lost and can immediately ask for
retransmission. Otherwise, the terminal would need to wait for a time-out.
3.4.5 Threshold Overview
The different threshold types are listed in Table 3-2. The following is a short description
of each type:
A) Discard Thresholds
1. Total Buffer Threshold
Limits the total buffer size per ABMP core (maximum 256k cells per ABMP direction)
depending on the RAM configuration.
2. Maximum Fill Threshold
This threshold has two possible modes, a basic mode (cell discard) or a selective
mode (Partial Packet Discard = PPD).
Basic mode:
The maximum amount of storable cells without PPD and EPD function i. e. the
respective physical storage area. Each cell which exceeds that threshold is discarded.
If in th e meantim e the storage area fill level falls be low that thr eshold the next a rriving
cell is accepted again.
Selective mode:
Every time a cell discarding occurs and PPDen=’1’ applies for the traffic class of this
cell, then also the remaining cells of this packet are discarded (beside non-user cells
Prel. ABMP Data Sheet
Functional Descript ion
Preliminary Data Sheet 73 2001-14-01
PRELIMINARY
and the last cell of the packet). For simplification this selectable PPD behavior of the
maximum fill threshold is denoted as PPD threshold in the remaining document.
3. PPD Threshold
It is the maximum fill threshold in case of the selective mode (see 2. under Maximum
Fill Threshold) and acts like an "emergency brake". The exceeding cell and all
subsequent cells (besides non- user cells and the last cell of t his packet) of this packet
are also discarded i f t he fill le ve l fal ls belo w that thr eshol d i n the mea nti me. The PPD
threshold is intended to be used for VBR-nrt, ABR, GFR and UBR.
4. Maximum Fill Threshold (CLP=1)
Acts like a normal maximum fill threshold but exclusively discards cells with CLP=’1’.
5. EPD Threshold
This is used for overload protection against bursty data traffic and so it is a "normal"
threshold for data traffic. Global buffer EPD threshold BufNrtEPD is intended to be
used for traffic classes which are not already policed (e.g. ABR, GFR and UBR).
6. EP D CL P1 Threshold for GFR
Acts like a normal EPD threshold but with the difference that it is a global threshold that
triggers EPD for CLP1 frames (not for CLP1 cells !) used by GFR service.
Note: Cel l discar din g of EPD and PPD thresho ld s doe s not appl y to non-user cell s, e.g.
an OAM cell in a packet is not discarded.
B) Indication Thresholds
1. ABR CI Threshold (applies to binary marking scheme of queue manager only)
This is used to indicate con gestion stat e to ABR connections ( ABRen=’1’) on a gl obal
buffer, scheduler and queue basis. By exceeding one or a combination of these
thresholds EFCI, NI and CI bits of user cells and RM cells are set appropriately. NI is
set in a slightly congested situation. NI and CI are set in a congested situation.
2. Low Prority / High Priority Scheduler Indication Thresholds
If the scheduler low and high priority buffer occupation exceeds the respective
thresholds the correspo nding threshold crossing indication bi ts for this schedulers are
set to ’1’ and related interrupts generated in “ISRDBA” on Page 315.
C) Backpressure Thresholds
1. UTOPIA Backpressure Thresholds
These thresholds (4 in upstream and 4 in downstream) are global thresholds with
respect to the cell buffer fill level and result in backpressure of specific port gro ups of
the respective UTOPIA receive interface.
2. Queue Congestion Indication Thresholds
These per queue thresholds generate a queue specific congestion indication that is
provided to the QCI interface and translated into a serial bit pattern to be processed
by external devices.
Prel. ABMP Data Sheet
Functional Descript ion
Preliminary Data Sheet 74 2001-14-01
PRELIMINARY
The following
Table 3-2
gives an overview of all thresholds. For each arriving cell all con-
ditions in this table are checked. Several thresholds may be exceeded.
Note: According to the cell acceptance algorithm of the ABMP, all threshold types are
evaluated at each cell ar ri val event, i ndepe ndent wheth er th e individual threshold
is actually used or not by the traffic class to which the cell belongs. Therefore
Table 3-2 is no truth table! For instance, if the maximum fill threshold of UBMTH/
DBMTH is scanned then all bits (ABRen..CLPT) are don’t care as the ABMP
checks this threshold by ignoring the values of these bits (hence e.g. PPDen can
be ’1’ as the value of PPDen is ignored during the scan of the basic mode of the
maximum fil l thr eshol d) . U ntil i f the selectable mode of the maxi mum fill th reshol d
(i.e. the PPD threshol d) is scanned, the ABMP checks the value of the bit PPDen
and all other bits are don’t care (according to Table 3-2).
.
Table 3-2 Threshold Overview Table
Contro lle d Logical
Buffer Entity
Location
Threshold Compare
Values Threshold Type
Granularity
Traffic
Class Table
Settings
to enable
Threshold
LCI Table
effected Cells
ABRen
EPDen
PPDen
CLPT
CLP
Global Buffer
Reg UBMTH
DBMTH UBOC
DBOC Total cell buffer size 4 xxxxx
TCT BufMax UNRTOC
DNRTOC Maximum threshold 1024xxxx0/1
PPD threshold 1024 x x 1 x 0/1
TCT BufEPD UNRTOC
DNRTOC EPD th reshold 1024 x 1 x 0 0/1
TCT BufCiCLP1 UNRTOC
DNRTOC ABR CI threshold 1024 1 x x x 1/0
EPD CLP1 threshold 1024 0 1 x 0 1
Reg UUBTH0
DUBTH0 UBOC
DBOC UTOPIA receive
backpressure
threshold
4 xxxxx
Reg UUBTH1
DUBTH1 4 xxxxx
Reg UUBTH2
DUBTH2 4 xxxxx
Reg UUBTH3
DUBTH3 4 xxxxx
Prel. ABMP Data Sheet
Functional Descript ion
Preliminary Data Sheet 75 2001-14-01
PRELIMINARY
Agenda:
The flags in columns “Traffic Class Table Settings to enable Threshold” indicate the traffic class settings
required to make the threshold effective during cell acceptance algorithm for a cell (connection) determined to
belong to that traffic class. An ‘x’ means don’t care, i.e. th e flag has no effect on the threshold.
The same applies to flag “CLPT” w hich is a connect ion specific setting in the LCI table.
The column “effected cel ls” ind icate whether the threshold effects CLP0, CLP1 or all cells.
Scheduler
TCT SBMa x SBOCNG Maximum threshold 1024 xxx00/1
PPD threshold 1024001x0/1
EPD threshold 1024 0 1 x x 0/1
TCT SBCi CL P 1 SBOCNG ABR CI threshold 64 1 x x x 0/1
PPD CLP1 threshold 64 001x1
EPD CLP1 threshold 64 0 1 x x 1
Reg CLP1DIS SBOCLP CLP1 discard threshold 64 x 0 x x 1
Reg DSBT1 SBOCLP,
SBOCHP
SBOCLPd
SB low priority/ high
priority threshold
crossing indica ti on
16 xxxx0
for
HP,
1
for
LP
RegDSBT2 16 xxxx
RegDSBT3 16 xxxx
RegDSBT4 16 xxxx
Traffic
Class TCT TrafClassMax TrafClassOcc
Ng Maximum threshold 1024 x 0 x x 0/1
PPD threshold 1024 x 0 1 x 0/1
EPD threshold 1024 x 1 x x 0/1
Queue
const max. queue
length 16383 Maximum threshold - xxxx0/1
PPD threshold - x x 1 x 0/1
TCT QueueMax Queu eLength Maximum threshold 64 x 0 x x 0/1
PPD threshold 64 x 0 1 x 0/1
EPD threshold 64 x 1 x x 0/1
QCTMinBG QueueLengthMinimum threshold 1, 8 xxxx0/1
TCT QueueCiCLP1 QueueLength Maximum threshold for
CLP1 cells 4 0xx01
PPD threshold 4 0 1 x 0 1
EPD threshold 4 1 x x 0 0/1
ABR CI threshold 4 1 x x x 0/1
Table 3-2 Threshold Overview Table
Controlle d Logical
Buffer Entity
Location
Threshold Compare
Values Threshold Type
Granularity
Traffic
Class Table
Settings
to enable
Threshold
LCI Table
effected Cells
ABRen
EPDen
PPDen
CLPT
CLP
Prel. ABMP Data Sheet
Functional Descript ion
Preliminary Data Sheet 76 2001-14-01
PRELIMINARY
3.4.6 Statistical C ounters
The ABMP device provides several statistical counters for maintenance purposes.
Global Counters:
• Total stored cells upstream and downstream
• Total stored non-real-time cells upstream and downstream
Per Traffic Class Counters:
• Accepted packets
• Discarded packets or discarded CLP = 1 cells
• Total discarded cells
• Discarded cells due to scheduler overflow
• Discarded cells due to traffic overflow
In addition, two types of sample-hold registers are provided:
• Minimum buffer occupancy value since last readout upstream and downstream
• Maximum buffer occupancy value since last readout upstream and downstream
3.4.7 Supervision Functions
3.4.7.1 Cell Header Protection
To guaran tee that the cel l header is no t corrupted by the external SDRAM , it is pr otected
by a 8-bit interleaved parity octet. It extends over the 5-octet standard header including
the UDF1 octet. The BIP-8 octet is calculated for all incoming cells and stored at the
place of the UDF2 octet. When a cell is read out, the BIP-8 is calculated again and is
compared with the stored BIP-8. In case of a mismatch, an interrupt is signaled and the
cell is discarded or not, depending on the configuration.
Note: Due to the usage of the UDF2 field for the BIP-8, the UDF2 octet is not transparent
through the ABM.
3.4.7.2 Cell Queue Supervision
The queuing of cells in the ABMP is implemented mostly by pointers. To detect pointer
errors, the number of the queue in which the cell is stored is appended to the cell in the
external cell storage SDRAM. When the cell is read out later, the selected queue number
is compared to the QID stored with the cell. In case of a mismatch, an interrupt is
signaled.
3.4.8 DBA Thre s hold Indication Mechanism
(For future document version.)
Prel. ABMP Data Sheet
Functional Descript ion
Preliminary Data Sheet 77 2001-14-01
PRELIMINARY
3.4.9 VC-Merge and Dummy Queue Description
Any queue can be configured (mutual exclusive) for participating in a VC-merge group
or being a ‘dummy queue’. A ‘dummy queue’ is always served according to its
associated rates and parameters independent of whether the queue stores cells or not.
The dummy queue feature can be used for bandwidth reservation e.g. for subsequent
multicast operation or any other cell insert/multiplier process. A detailed description of
enabling/disabling those special queue functions is provided in the description of
“Queue Configuration Table Transfer Registers QCT0..6” on Page 219.
3.4.9.1 VC-Merge
Any queue can be conf igured to be membe r of one of th e 128 merg e groups in the QC T
via “Queue Configuration Table Transfer Registers QCT0..6” on Page 219.
Assigning a queue to a VC-merge group already enables the packet boundary aware
scheduling of all queues within the same group.
Optionally th e ATM cell header may be overw ritten wit h a new value pr ogrammed i n the
MGT via “Merge Group Table Transfer Registers MGT0..MGT2” on Page 235.
A queue is released from its VC-merge group by resetting bit ‘QIDvalid’.
3.4.9.2 Dummy Queue
A queue can be configured as a ‘dummy queue’ and de-activated respectively via bits
‘DQac’ and ‘RSall’ in “Queue Configuration Table Transfer Registers QCT0..6” on
Page 219.
A ‘dummy queue’ (in contrast to a normal queue) is always scheduled independent of
whether cells are currently stored in the queue or not. Examples for ‘dummy queue’
configurations are bandwidth reservation for
• insertion of out-of-rate OAM cells or signalling packets,
• subsequent multicast/dualcast functions.
Prel. ABMP Data Sheet
Functional Descript ion
Preliminary Data Sheet 78 2001-14-01
PRELIMINARY
3.5 Detailed E RC Description
3.5.1 ERC Unit Overview
The following illustration provid es an overview of the ERC sub-system:
Figure 3-24 ERC Unit Sub-System
The central function blocks of the ER C sub-system are the processor running the ABR
state machines and the AVT context table storing all connection specific parameters.
The SCAN unit next to the AVT table enforces all time-out related parameters by
generating time-out notifications. During initialization the Code RAM is either loaded
from the internal ROM or via the SPI interface from an external serial EEPROM device.
Communication with the ABMP core (RM cell insert/extract, queue information, rate
update messages, cell emit events) i s handled by the message i nterface. The ERC sub-
system shares the uP interface with the ABMP core. Communication with an external
Processor
Code RAM
RAM
SPI
ext. EEPROM
ROM
ext. Context
RAM AVT
(Contex t RAM)
Mail Box
Message
Interface
ABMP
Core
(shared) uP-IF
SCAN
Prel. ABMP Data Sheet
Functional Descript ion
Preliminary Data Sheet 79 2001-14-01
PRELIMINARY
microprocessor (e.g. extended context RAM access) is performed via a mailbox while
access to the main context table AVT is possible via dedicated transfer regis ters.
3.5.2 ERC Unit Functional Overview
Available Bit Rate service ABR is the only traffic type with dynamic adaptation of the
transmission rate according to the currently available bandwidth. It uses an ATM layer
control loop using special Resource Management RM cells to convey bandwidth
information along a connection’s path thru the network. The RM cells are inserted in
regular intervals by the source of a connection - usually the terminal. At the end of the
connection the receiving terminal loops the RM cells back to the source. All the switches/
bottlenecks on the way updat e the Explicit Rate (ER) field of the cells, so that the send er
knows the optimum current transmission rate.
Reducing the rate to the value determined by the smallest bottleneck in the network
leaves unused bandwidth to all other links. It can be used by other ABR connections as
shown in the example of Figure 3-25, where four connections with different source and
destination points are traversing four switches. Assume e.g. that connection 4 is severely
restricted in Switch 4 then additional bandwidth is released in Switch 2 which can be
used by the other connections.
Figure 3-25 Example Network Configuration
ABR behavior is described with several options by the Traffic Management Specification
[] of the ATM Forum by complex descriptions of source, destination behavior and the
switch behavior. The implementation of the switch behavior is mainly left to the
manufacturer; it is implicitly stated that the switch should update the RM cells in such a
way that no cell losses occur. Source and destination behavior normally occur in
terminals only, but there is an op tion to realize vir tual source (VS) and virtual desti nation
(VD) behavior in a switch as described below.
D1
S1 Switch 1 Switch 2 Switch 3 Switch 4
S3
S2 D2S4
D3
D4
S1..S4 = Connection Sources
D1..D4 = Connection Destinations
Prel. ABMP Data Sheet
Functional Descript ion
Preliminary Data Sheet 80 2001-14-01
PRELIMINARY
The options for swi tch behavi or are show n i n Table 3-3 with increasing complexity fr om
top to bottom.
Table 3-3 ABR Support of ABM v1.1 vs. ABMP
Figure 3-26 ABR Mechanisms
Switch behavior Description ABM
v1.1 ABMP
EFCI marking Setting the PT bits in the user cell header
to "congestion experienced" yes yes
Relative rate marking Setting CI and/or NI bits of forward or
backward RM cells to 1 (binary
feedback)
yes yes
Explicit rate marking Reducing the ER field of forward or
backward RM cells no yes
Reactive switch
behavior Explicit rate marking and additional
reduction of the transmission rate of user
cells to the ER
no yes
VS/VD control Segmentation of the ABR control loop
using a virtual source and destination no yes
Source
Source and
sink RM cells
É
Switch
adjust
ACR
update RM
Switch
ÉÉ
update RM
Destination
Turn-around
RM cells
É
upda te RM
adjust
ACR
Relative rate
or explicit rate
marking
Reactive switch control
user and RM cell flow
RM cell flow Note: in case of EFCI switches only the RM cells are
generated at t he dest i nation
Switch
set
PTI
É
EFCI marking
Prel. ABMP Data Sheet
Functional Descript ion
Preliminary Data Sheet 81 2001-14-01
PRELIMINARY
3.5.3 Explicit Rate Marking
3.5.3.1 Rate Parameters
Using Explicit Rate Marking the sending rate of a source is permanently adjusted to
varying network load conditions. An example of rate variation over time of an Explicit
Rate controlled ABR connection is shown in Figure 3-27. Along with this figure the
different rates are explained, with text in blue relating to the realisation in the ABMP:
• PCR (Peak Cell Rate) is the upper bound for ACR and may never be exceeded. It is
constant for each connection and may be supervised by policing.
• MCR (M in im um C ell Ra te) is the lower bound for ACR; constan t for each connecti on.
The souce may send at any time with MCR, hence this rate must be guaranteed by
the network all the time. The explicit rate ER carried in the RM cells never assumes
values below MCR.
The ABMP guarantees the minimum service rate when per-VC queuing is used and
the appropr iate weight factor is set for the queue. Also connection acceptance contro l
(CAC) must assure that no overbooking occurs.
• ACR (Allowed Cell Rate) is computed by the source according to the rules 1, 2, 5, 6,
8 and 9 of section 5.10.4, Source Behavior, of ATM Forum TM4.1.
The ABMP supports ABR service with per-VC queuing and with the peak rate limiter
for the queue enabled. The ACR is programmed to the peak rate limiter.
• ICR ( Inititial Ce ll Rate) i s the value of ACR at init time of a connection and aft er a long
inactive time; defined by the global constant ADTF (ACR Decrese Time Factor).
• The Sending Rate of the source must never exceed ACR, but may stay below it.
Prel. ABMP Data Sheet
Functional Descript ion
Preliminary Data Sheet 82 2001-14-01
PRELIMINARY
Figure 3-27 Example Behavior of an Explicit Rate controlled ABR Connection
Some special situ ations are pointed out in Figure 3-27, denoted w ith numbers in circles.
These are explained below, again using blue color for ABMP related issues:
1. The sending rate remains below ACR. The reason for this could be that the connection
is restricted at some other point in the network or even within the source. In such a
case the unused bandwidth will be consumed after some time by other connections.
The WFQ multiplexer of the ABMP distributes bandwidth immediately among used
queues accordi ng to thei r weigh t. No bandwid th is lost as long as a at least one single
queue is not empty.
2. Same as 1 with the sending rate dropping below MCR.
3. The sender stops transmitting data. After some time the ACR is reduced to MCR.
4. After the timeout defined by ADTF the connection is allowed to start with ICR, i.e. ACR
is set to ICR.
3.5.3.2 Other Parameters
The ABR implementation in the ABMP uses global (configurable) values for those
parameters which have recommended default values in the standard:
PCR
MCR
ICR
ACR
sendin g rate
1
23
4
ADTF
Legend:
PCR = Peak Cell Rate
MCR = Minimum Cell Rate
ACR = Allowed Cell Rate
ICR = Initial Cell Rate
ADTF = ACR Decreas Time Factor (default 0. 5 sec)
The dashed line indicates the tr ue sending rate of the source
The numbers in circl es denote sp ecial cases which are ex plaine d in the text
Prel. ABMP Data Sheet
Functional Descript ion
Preliminary Data Sheet 83 2001-14-01
PRELIMINARY
The param eters Nrm and Mrm tog ether with sour ce rule #3 l ead to the sequen ce of user
and RM cells shown in Figure 3-28. This picture also explains the definition of in-rate
and out-of-rate cells together with Table 3-5:
In the ABR im plemen tation o f the ABMP BRM cells are insert ed wit hin the A CR if opti on
1 is selected (option 2 is not supported) for the turn-around of RM cells. The additional
rate of 10 cells/s should be taken into account when reserving the MCR.
When the cell interar rival distance T at the actual sending r ate is very small compared to
Trm the cell sequence will be:
• one in-rate FRM cell
• optionally one in-rate BRM cell (if there is one to be turned around)
• 30 user cells (31 in case there is no BRM cell to be turned around)
and the TRM timeout will never happen. If, however, onl y a few cell slots fit into the TRM
interval the timeout event will occur before 30 user cells have been transmitted.
Table 3-4
Parameter Default
Value Description
Nrm 32 Number of user cells between two in-rate FRM cells;
Trm 100 ms After Trm the ne xt FRM cell is generated if at l east two in-
rate cells (user or BRM) have been sent;
ADTF 500 ms Timeout of a connection; if no user cells are received for
this time the conne ction is considered in active and has to
restart with ICR;
Mrm 2 Controls the bandwidth allocation between RM cells and
user cells: minimum 2 user cells must be transmitted
between two consecutive FR M cells;
TCR 10 cells/s Tagged cell rate: controls insertion of out-of-rate FRM
cells
Table 3-5 In-rate and out-of-rate Cells
Cell type User cells FRM cells BRM cells CLP Within ACR
In-rate yes yes yes 0 yes
Out-of-rate not allow ed yes yes 1 no
Prel. ABMP Data Sheet
Functional Descript ion
Preliminary Data Sheet 84 2001-14-01
PRELIMINARY
Figure 3-28 RM and User Cell Sequence: General Case
The worst case that only one user cell is transmitted in each FRM cell cycle is shown in
Figure 3-29, where the cell sequence is
• one in-rate FRM cell
• one in-rate BRM cell (let’s assume there is one to be turned around)
• 1 user cell.
Figure 3-29 RM and User Cell Sequence: worst Case
Table 3-6 Bandwidth Efficiency
Range of T Edge Rate
[cells/s] Edge Rate
[kbit/s] RM cells /
user cells Bandwidth
Efficiency
Trm/3 < T 2/1 33.3%
Trm/4 < T =< Trm/3 30 12.72 2/2 50%
Trm/5 < T =< Trm/4 40 16.96 2/3 60%
: : :::
Trm/31 < T =< Trm/30 300 127.2 2/29 93.55
T =< Trm/31 310 131.44 2/30 93.75
Σin-rate cells ≤ Nrm = 32
Σin-rate cells ≥ Mrm = 2
Trm = 100 ms
user cell
BRM cell
FRM cell out-of-rate
BRM cell
in-r ate cells
out-of-rate cells
1/rate
Σin-r ate cells = 2
Trm = 100 ms
user cell
BRM cell
FRM cell FRM cell BRM cell
in-rate cells
out-of-rate cells
1/rate
Prel. ABMP Data Sheet
Functional Descript ion
Preliminary Data Sheet 85 2001-14-01
PRELIMINARY
Figure 3-30 Capacity Usage of ABR VCs
3.5.4 Reactive Switch Behavior
Reactive Switch control is an extension to the Explicit Rate ope ration. A switch with RSC
behavior enabled is supposed to adjust the connection specific rates to the current
explicit rate value copied from the BRM cells (see Figure 3-27).
3.5.5 VS/VD Behavior
The VS/VD behavior is basically the source and destination behavior.
The VS/VD source behavior performs two different tasks:
• Multiplexing user cells, forward RM cells (FRM) and backward RM cells (BRM)
• Adjustment of the allowed cell rate ACR (Current Cell rate (CCR)).
Multiplexing user cells and FRM cells means that after each 32 (default) user cells a FRM
cell is inserted . But also turned-aroun d FRM cells must be inserted as BRM cells for the
associated opposite direction of the connection. One BRM cell is allowed to be inserted
between two FRM cells. In case of asymmetrical data rates of the two opposite directions
- one direction might have user cell rate zero for some time - various scenarios can
occur; e.g. it could be possible that due to the absence of user cells no FRM cells are
Bandwidth Usage
0,00%
20,00%
40,00%
60,00%
80,00%
100,00%
0 20406080100120140
kbit/s
Prel. ABMP Data Sheet
Functional Descript ion
Preliminary Data Sheet 86 2001-14-01
PRELIMINARY
generated and according ly also no BRM cells. Several options are given by the standard
to cope with special cases.
Adjustment of ACR is basically using the ER conveyed in the BRM cell as new sending
rate. However, as the standard work at ATM Forum has been accompanied by extensive
simulations a bunch of parameters has been introduced in oder to avoid overflows,
deadlocks or oscillations in the network. These give further constraints for ACR
• ACR must stay between MCR and PCR
• in the absence of received BRM cells the source assumes heavy congestion in the
network and reduces ACR by a factor.
Finally the ACR is not identical to the actual sending rate:
In the implementati on the ACR is prog rammed to the peak rate limiter of a queue. Then
the rule is fulfilled that the actual sending rate shall never be higher than ACR. If the
queue is served at a lower rate than ACR - due to many other active queues - the unused
bandwidth will be consumed by the network ("use-it-or-lose-it" principle). Using the WFQ
multiplexer assignment of an appropriate weight assures that ACR is not falling below
MCR.
The VS/VD destination behavior is basically converting the received FRM cells into BRM
cells and conveying them to the virtual source. Optionally the destination may also
reduce ACR. The received BRM cells are evaluated and the ACR is conveyed to the
source.
Prel. ABMP Data Sheet
Functional Descript ion
Preliminary Data Sheet 87 2001-14-01
PRELIMINARY
Figure 3-31 VS/VD Cell Streams
In a switch the VS/VD function is distributed as shown in Figure 3-32.
ABR VC_f
ABR VC_b
FRM_f
BRM_b É
≈
BRM_f
FRM_b
adjust
BRM_b
FRM_f
É
≈
FRM_b
BRM_f
adjust
ABR segment 1 ABR s egment 2
Legend:
ABR VC_f = ABR connection in f orward dir ection
ABR VC _b = ABR connect ion in backward dir ection
FRM = forward Resource Management cell
BRM = backward Resource Managment cell
Notes:
• per-VC queues separate rates in both ABR segments
• ser ving rates of queues dynamically adjusted
= Virtual Sour ce
= Virtual Destination
= Queue with peak rat e limiter
É
≈
Prel. ABMP Data Sheet
Functional Descript ion
Preliminary Data Sheet 88 2001-14-01
PRELIMINARY
Figure 3-32 Di stribution of VS/VD Function in a Switch
3.5.6 ERC Mailbox
(For future document version.)
Line card with ABM Line Card with ABM
VS
VD
FRM_f
É
≈
BRM_f
FRM_badjust
BRM_b BRM_b
FRM_f
É
≈
FRM_b
BRM_f
adjust
ABR segment 1 ABR segment 2No ABR Protocol
VD
VS
ABR VC_f
ABR VC_b
Prel. ABMP Data Sheet
Functional Descript ion
Preliminary Data Sheet 89 2001-14-01
PRELIMINARY
3.6 Internal Tables
3.6.1 Table Overview
The ABMP provides a set of internal tables for configuration and runtime parameters.
The tables are accessed by the microcontroller via control registers, data transfer
registers and mask registers. While the control registers “MAR” on Page 317 and
“WAR” on Page 319 are common to all tables (except SCTI tables), sets of mask
registers are dedicated or shared among some tables. Data transfer registers are always
dedicated to the specific table. The following illustration gives an overview of all (user
accessible) tables and related control/transfer/mask registers:
Prel. ABMP Data Sheet
Functional Descript ion
Preliminary Data Sheet 90 2001-14-01
PRELIMINARY
Figure 3-33 Table Access Overview
LCI Table
MAR =
00d
TCT Tabl e
MAR =
01d
QCT
Table
MAR =
02d
SOT
Table
MAR =
03d
MGT
Table
MAR =
07d
QCI Table
MAR =
08d
DTC Table
MAR =
05d
MASK6 MASK5 MASK4 MASK3
MASK2 MASK1 MASK0
Common Mask
Register Set:
no Mask no Mask
LCI0
LCI1
LCI2
TCT0
TCT1
TCT2
TCT3
QCT0
QCT1
QCT2
QCT3
QCT4
QCT5
QCT6
SOT0
SOT1
SOT2
SOT3
SOT4
MGT0
MGT1
MGT2
QCIT DTCT
AVT Table
MAR =
10d
QPT1
Table
Upstream
MAR =
16d
QPT2
Table
Upstream
MAR =
17d
QPT1
Table
Downstr.
MAR =
24d
QPT2
Table
Downstr.
MAR =
25d
SCTF
Table
Upstream
MAR =
23d
SCTF
Table
Downstr.
MAR =
31d
ERCM1
ERCM0
ERCT1
ERCT0
UQPTM3
UQPTM2 UQPTM2
UQPTM0
UQPT1T1
UQPT1T0 UQPT2T1
UQPT2T0
UQPT2T3
UQPT2T2
DQPTM3
DQPTM2 DQPTM2
DQPTM0
DQPT1T1
DQPT1T0 DQPT2T1
DQPT2T0
DQPT2T3
DQPT2T2
USCTFM DSCTFM
USCTFT DSCTFT
MAR
WAR
Common
Table Access
Control
Registers:
Mask
Registers
Data Transfer
Registers
Mask
Registers Data Transfer
Registers
SCTI
Table
Upstream
SCTI
Table
Downstr.
no Mask no Mask
USCTI DSCTI
DSADR
USADR
SCTI Table
Access
Control
Registers:
Prel. ABMP Data Sheet
Functional Descript ion
Preliminary Data Sheet 91 2001-14-01
PRELIMINARY
3.6.2 LCI: Local Connection Identifier Table
The basic function of the LCI tabl e is assigning the connection (identified by the LCI) to
one out of 8192 queues per direction. Single connections can be assigned to a dedicated
queue (per VC queuing) or multiple connections might be assigned to the same queue.
Please refer to “LCI Table Transfer Registers LCIC, LCI1, LCI2” on Page 199 for
further details.
3.6.3 QCT: Queue Configu ration Table
The basic function of the QCT table is to determine queue specific parameters and to
assign the queue to dedicated resources {Traffic Class, Scheduler Entity, Merge Group}.
Please refer to “Queue Configuration Table Transfer Registers QCT0..6” on
Page 219 for further detai l s.
3.6.4 TCT: Traffic Class Table
The function of the TCT table is to configure the buffer management behavior of up to
16 traffic classes (service classes).
Please refer to “Traffic Class Table Transfer Registers TCT0, TCT1, TCT2, TCT3”
on Page 203 for further details.
3.6.5 QPT: Queue Parameter Table
The function of the QPT table is to configure the weight factor (in case of the queue is
assigned to the WFQ scheduler) and the peak cell rate value (in case the peak cell rate
shaper is enabled).
Please refer to “Queue Parameter Table 2 Transfer Registers” on Page 257 for
further details.
3.6.6 SOT: Scheduler Occupancy Table
The function of the SOT table (for 2*128 scheduler entities) is to maintain the buffer filling
levels associated with the dedicated scheduler and to control the scheduler specific DBA
threshold indications.
Please refer to “Scheduler Occupancy Table Transfer Registers SOT0..SOT4” on
Page 230 for furth er detai l s.
3.6.7 SCTI: Scheduler Configuration Table (Integer)
The function of the SCTI table (for 2*128 scheduler entities) is to determine the integer
part of the scheduler output rates as well as the UTOPIA port number the scheduler is
assigned to.
Prel. ABMP Data Sheet
Functional Descript ion
Preliminary Data Sheet 92 2001-14-01
PRELIMINARY
Please refer to “Scheduler Configuration Table Integer Transfer Registers” on
Page 262 for furth er detai l s.
3.6.8 SCTF: Scheduler Configuration Table (Fractional)
The function of the SCTF table (for 2*128 scheduler entities) is to determine the
fractional part of the scheduler output rates.
Please refer to “Scheduler Configuration Table Fractional Transfer Registers” on
Page 274 for further detai l s.
3.6.9 MGT: Merge Group Table
The function of the MGT table (for 128 merge groups per direction) is to enable and
specify the cell header overwrite function for the merge group output streams.
Please refer to “Merge Group Table Transfer Reg isters MGT0..MGT2” on Page 235
for further details.
Prel. ABMP Data Sheet
Functional Descript ion
Preliminary Data Sheet 93 2001-14-01
PRELIMINARY
3.6.10 AVT: ABR/VBR Configuration Table
The AVT table is the main context RAM of the ERC sub-system.
3.6.10.1 AVT Context RAM Organization and Addressing
The AVT context RAM addressing scheme imposes some restrictions to the choice of
QID numbers for support of VBR shaping or ABR (ER, VS/VD) operation. The table is
organized into 2k sections of 4 double w ords each whereas each sectio n corresponds to
the respective QID numbe r.
Support of VBR shapin g requir es one section, i .e. up to 2k connecti ons assigne d to QID
numbers {(0,) 1, ..., 2047} can be supported for VBR shaping.
Support of ABR functionality requires 2 sections per connection, i.e. up to 1k connections
can be supported with full ABR functionality. Only even QID numbers can be used for
ABR operation. Selecting ABR for QID n (n = (0,) 2, 4, ..., 2046) also occupies section
(n+1) prohibiting VBR operation for QIDs n and (n+1).
In case support for 1k conne ction s wi th eithe r ABR or VBR functi ona lity i s suffi cien t, the
resource management algorithm is significantly easier for administrating the AVT
context RAM and QID resources.
Prel. ABMP Data Sheet
Functional Descript ion
Preliminary Data Sheet 94 2001-14-01
PRELIMINARY
Figure 3-34 Context RAM Addressing Scheme
The parameter utilization of each section depends on the mode selected for the
particular queue (QID). The mode specific parameter sets are described in the
subsequent chapters.
3.6.10.2 AVT Context RAM Section for ABR -VS/VD Support
In ABR-VS/VD mode one connecti on en try re qui res 2 conte xt RAM sections wi th a tota l
of 8 double words. Since the AVT table is accessed from the external micro controller via
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
8184
8185
8186
8187
8188
8189
8190
8191
RAM DWord
Address: VBR Context
Offset Address:
0
1
2
3
2046
2047
DWord #0
DWord #1
DWord #2
DWord #3
IOP /ABR Context
Offset Address:
0
Word #0,1
Word #2,3
Word #4,5
Word #6,7
Word #8,9
Word #10,11
Word #12,13
Word #14,15
2
2046
VBRaddr := QID*4 +
DWordOffset(0..8)
ABRaddr := (QID<<1)*8 + WordOf fset
WordOffset(0..15)
Note:
only even QIDs (
0
, 2, 4, ... 2046) are allowed for ABR
operation (check QID Filter in RM/Emit FIFOs!);
An active ABR connection prohibits VBR operation for
the same and the following QID, e.g. ABR on QID=2
prohibits VBR for QIDs 2
and 3
;
Prel. ABMP Data Sheet
Functional Descript ion
Preliminary Data Sheet 95 2001-14-01
PRELIMINARY
a 16 bit transfer register, the ABR-VS/VD connection context appears as a 16 bit
organized table with 16 entries as shown in Figure 3-35:
Figure 3-35 AV T Context Table: A BR-VS/VD
The following parameters are supported as global values common to all ABR
connections:
•TRM:
Register “ERCCONF1” on Page 294
Granularity 100 ms, value: 100 ms*2^(-TRM), range: (2^(-7) .. 2^0) * 100 ms
•NRM:
Provided to ERC unit via mailbox.
•CDF:
Provided to ERC unit via mailbox.
3.6.10.3 AVT Context RAM Section for ABR-ER Support
In ABR-ER mode one connection entry requires 2 context RAM s ections with a total of
8 double words. Since the AVT table is accessed from the external micro controller via
a 16 bit transfer register, the ABR-VS/VD connection context appears as a 16 bit
organized table with 16 entries as shown in Figure 3-36:
QID*16 F0 CIb NIb EFCId EFCIu
QID*16 + 1
QID*16 + 2 C
QID*16 + 3
QID*16 + 4
QID*16 + 5
QID*16 + 6
QID*16 + 7
QID*16 + 8 CIt NIt
QID*16 + 9
QID*16 + 10
QID*16 + 11
QID*16 + 12
QID*16 + 13 DIR BN RA
QID*16 + 14
QID*16 + 15 ToT ToA
FInRateCount(5:0)
VCI
(
11:0
)
VPI(11:0)
Confi
g
(6:0)
LastFRMSent
(
3:0
)
ADTF
(
9:0
)
ERb*(15:0)
LastInRateSent(9:0)
dTi(15:0)
Flags(3:0)
PTI
VCI(15:12)
Confi
g
(6:0) unused
ERt*(15:0)
MCRf*(15:0)
UDF1
(
7:0
)
UDF2
(
7:0
)
CCRf*(15:0)
PCRf*(15:0)
CRM(5:0) CRMcnt(9:0)
dTf(15:0)
RDFb(3:0) RIFb(3:0) reserved
Prel. ABMP Data Sheet
Functional Descript ion
Preliminary Data Sheet 96 2001-14-01
PRELIMINARY
Figure 3-36 AV T Context Table: A BR-ER
3.6.10.4 AVT Context RAM Section for VBR Shaping Su pport
In VBR shaping mode one connection entry requires 1 context RAM section with a total
of 4 double words. Since the AVT table is accessed from the external micro controller via
a 16 bit transfer register, the ABR-VS/VD connection context appears as a 16 bit
organized table with 8 entries as shown in Figure 3-37:
CIf NIf CIb NIb EFCId EFCIu
Vb
Vf
SumdTf
(
20:16
)
Cntf(4:0)
Tlastf
(
20:16
)
Tlastf(15:0)
IQLf(1:0)
MCRf*(15:0)
SumdTf(15:0)
Cntb(4:0) Tlastb(20:16)
Tlastb(15:0)
dTb(15:0)
ERf*(15:0)
Confi
g(
6:0
)
Qlenf(13:0)
QID*16 + 4
MCRb*(15:0)
SumdTb
(
15:0
)
SumdTb(20:16)
QID*16 + 2
QID*16 + 3
QID*16 Confi
g(
6:0
)
Qlenb(13:0) IQLb(1:0)QID*16 + 1
QID*16 + 8
QID* 16 + 12
QID*16 + 9
QID* 16 + 10
QID* 16 + 11
QID* 16 + 14
QID*16 + 5
QID* 16 + 13
QID*16 + 6
QID*16 + 7
ERb*(15:0)
dTf(15:0)
QID* 16 + 15
Prel. ABMP Data Sheet
Functional Descript ion
Preliminary Data Sheet 97 2001-14-01
PRELIMINARY
Figure 3-37 AV T Context Table: VB R Shaping
QID* 16 + 5
QID* 16 + 6
QID* 16 + 3
QID* 16 + 4
QID* 16 + 7
QID*16 + 2a
QID*16 + 3a
QID* 16 + 2
QID*16
QID* 16 + 1
VDTr,n,f(18:16)
TET
(
23:16
)
Confi
g(
6:0
)
TSn,f(15:0)
ST0r,n(12:10)SDT1r,n(12:0)
unused
TPn,f(15:0)
IDT(15:0
STf(5:0)SDT0r,n(9:0)
τso,e
Temitr,n(12:0)unused VDTr,n,f(15:0)
Prel. ABMP Data Sheet
Functional Descript ion
Preliminary Data Sheet 98 2001-14-01
PRELIMINARY
3.6.10.5 Common AVT CONFIG Field
The first word (WORD0) of each entry defines the entry type {inactive, ABR, VBR} with
its respective submodes. The mapping of the 6 configuration bits Config(5:0) is
summarized in “Config(5:0) Bit Map” on Page 98. For proper VBR operation, the
Config(5:0) field must be replicated in WORD8.
Note: The configuration bit-field Conf(5:0) is duplicated in WORD8. This is required for
correct SCAN operation since VBR operation utilizes two 8 word sections of the
context table for two VBR connections. In case of ABR, the duplicated Conf(5:0)
bit-field is ignored by the SCAN.
Table 3-7 Config(5:0) Bit Map
Config
field
bit
position
absolute
WORD
bit
position
Function
Bit 6 Bit 15 ERC
enable if ‘1’ then ERC functions enabled
Bit 5 Bit 14 ABR
enable ‘1’: ABR Mode ‘0’: VBR Mode
Bit 4 Bit 13 ABR-VSVD
enable;
Core select
‘1’: VS/VD Mode
‘0’: ER Mode ‘1’: upstream core
‘0’: down st ream core
Bit 3 Bit 12 ABR-FWD
enable;
VBR mode
ER:
‘1’: BRM cell update
‘0’: FRM cell update
VS/VD:
‘1’: downstream rate ctrl.
‘0’: upstream rate ctrl.
‘0’: VBR1
‘1’: VBR2 and VBR3
Bit 2 Bit 11 ABR-BIDIR
enable;
Flag
‘1’: Bi-directional mode
enabled CLP
Bit 1 Bit 10 ABR-RSC
enable;
Flag
‘1’: Reactiv e Sw itch
Control enabled SDT valid
Bit 0 Bit 9 unused;
Flag unused IDTvalid
Prel. ABMP Data Sheet
Functional Descript ion
Preliminary Data Sheet 99 2001-14-01
PRELIMINARY
3.6.11 QCIT: Congestion Indication Table
The function of the QCIT table (for 8192 downstream queues) is to determine the per
queue threshold that triggers the queue congestion indication toward the QCI interface.
Please refer to “Queue Congestion Indication Table Transfer Register” on
Page 243 for furth er detai l s.
Prel. ABMP Data Sheet
Operational Description
Preliminary Data Sheet 100 2001-14-01
PRELIMINARY
4 Operational Description
4.1 Basic Device Initialization
The following actions are recommended to be performed after reset to prepare the
ABMP chip for operation:
Basic settings:
• Configure clocking system (DPLLs)
• Check register Reset values
• Initi alize SDR AM
• Reset internal tables (RAMs)
• Set hardware configuration (UTOPIA configuration)
ABMP diagno stic possibiliti es:
• Check all internal RAMs and register values
Data path setting and initial queueing and scheduling initialization:
• Set MODE1 and MODE2 registers
(Uni-directional Mode or Bi-directional Mode)
• Configure UTOPIA interfaces: modi, number of PHYs
• Initialize traffic class tables
• Check data path (via adjacent ABMP devices)
• Set empty rate generator (if required)
• Set paramet er MaxBurstS(3:0) (r egister “UECRI /DECRI” on Pa ge 267) of the output
Multipl exer and the parameter C DVMAX(8:0 ) (register “UCDV/DCDV” on Page 245)
of the Peak Rate Limiter
• Set global thresholds
• Programming of Scheduler output rates
• Assignment of Schedulers to PHYs at switch egress side
• Assignment of Schedulers to switch outputs at ingress side
4.2 Basic Traffic Management Initializa tion
To set up a connection, the complete linked list must be established:
LCI → Queue ID → Scheduler and
LCI → Queue ID → Traffic Class
(see Figure 4-1). Additionally, the bandwidth and buffer space reservations must be per-
formed (see below). Depending on the traffic class, special functions must be enabled;
for example: ABR feedback enable or EPD/PPD for UBR.
Prel. ABMP Data Sheet
Operational Description
Preliminary Data Sheet 101 2001-14-01
PRELIMINARY
Figure 4-1 Parameters for Connection Setup (Bitfield width indicated)
8k common entry(D n/Up)
LCI
Table
UpQID(13)
DnQID(13)
ABMcore(1)
CLPT(1)
LCI
2*8k entries
QCT
Table
MinBG(8)
MGID(7)
MGconf/DQsch(1)
SID(7)
QIDvalid(1)
TraffClass(4)
ABRcore(1)
VSVDen(1)
RSall(1)
DQac(1)
QueueLength(14)
DnQID
UpQID
2*16 entries
TCT
Table
SbMax(8)
TraffClassMax(8)
CLPtransDBA(1)
GFRen(1)
CntLPDBA(1)
SCNT(1)
PPDen(1)
EPDen(1)
ABRvp(1)
ABRen(1)
DH(3)
SbCiCLP1(12)
QueueMax(8)
BufCiCLP1(18)
QueueCiCLP1(12)
BufEPD(8)
BufMax(8)
2*128 en tries
MGT
Table
LCIoen(1)
LCI(14)
8k entries
(downstream only)
QCI
Table
QCITH(12)
8k entries
QPT1
(Up) Table
flags(2)
8k entries
QPT2
(Up) Table
RateFactor(16)
WFQfactor(14)
8k entries
SCTI
(Up) Table
IntRate(14)
Init(10)
UtopiaPort(6)
8k entries
SCTF
(Up) Table
FracRate(8)
Upstream Scheduler
Block
Downstream Scheduler
Block
2*128 en tr ies
SOT
Table
DBAThresCross(8)
Prel. ABMP Data Sheet
Operational Description
Preliminary Data Sheet 102 2001-14-01
PRELIMINARY
Figure 4-1 refers to the following parameters:
Abbreviation Description See
page
UpQID Points to the queu e assigned to this connection i n the
upstream direction 7-202
DnQID Points to the queu e assigned to this connection i n the
downstream direction 7-201
CLPT If set, the CLP bit of the cells are ignored;
(not to be set for GFR; optional for ABR and UBR;) 7-200
ABMcore Selects upstream or downstream ABM Core in the
Uni- di rectional Mode 7-200
MinBG Minimum guaranteed queue length 7-224
MGID Selects the VC-M erge Group the que ue is a ssigned to 7-224
MGconf/DQsch Command bit to enable merge group assignment or
dummy queue function 7-224
SID Selects the Scheduler 7-221
QIDvalid Enables queue; if cle ared, cel ls directed to this q ueue
are discarded and interrupt QIDINV (see 6-149f.)
occurs
7-221
TrafClass Selects the traffic class 7-221
ABRcore Selects the ABM Core in which RM cell update is made
for ABR connections 7-221
VSVDen Enables ABR-VS/VD (ERC unit) functions for this
queue 7-221
RSall Enables the dummy queue function 7-221
DQac Status bit 7-221
QueueLength Status value (read only) 7-221
Prel. ABMP Data Sheet
Operational Description
Preliminary Data Sheet 103 2001-14-01
PRELIMINARY
DBAThCross High threshold for Scheduler occupancy in steps of
256 7-231
IntRat e Integer pa rt of increment al value for Scheduler outpu t
rate 7-264
Init Initialization value 7-264
UtopiaPort Specify UTOPIA port for this scheduler 7-264
flags Initializati on va lue 7-255
FracRate Fractional part of increment al valu e for Scheduler out-
put rate 7-270
RateFactor Select value of peak rate limiter 7-259
WFQFactor Weight of multiplexer input in 15,360 steps 7-259
DH Selects the hysteresis value for threshold evaluation 7-213
ABRen If set, binary ABR marking by ABMP core is enabled 7-213
ABRvp (ABR service category) relating to the VP or to the indi-
vidual VC, respectively;
If set, congestion is indicated via VP RM cells (F4 flow)
7-213
EPDen If set, EPD is enabled 7-213
PPDen If set, PPD is enabled 7-213
SCNT Selects whether accepted packets or cells are counted 7-213
CntLPDBA Selects whether low and high priority cells are counted
separately for DBA thresholds 7-213
GFRen 7-213
CLPTransDBA 7-213
Abbreviation Description See
page
Prel. ABMP Data Sheet
Operational Description
Preliminary Data Sheet 104 2001-14-01
PRELIMINARY
4.2.1 Setup of Queues
Before assigning a connection to a new queue, it should be verified to be empty, as some
cells could remain from the previous connectio n. A queue is emptied by setting it ‘invalid’
while maintaining the scheduling parameters. An invalid queue will not except further
cells; cells will be scheduled and de-queued, but not transmitted to the UTOPIA inter-
face. The queue length can be monitored by the external microprocessor.
BufMax Defines maximum number of non-guaranteed cells
allowed in the entire buffer for this traffic class 7-206
BufEPD Defines threshold for EPD/maximum1) for this traffic
class for the entire buffer 7-206
TrafClassMax Defines maxim um number of cells for this traffic class 7-213
SbMax Defines thr eshold for the number of cells of th is traffic
class allowed in the associated Scheduler 7-213
QueueMax Defines threshold for each queue for this traffic class 7-208
QueueCICLP1 Combined threshold for each queue for CI indication
(ABR) and CLP=1 cell discard in case of CLPT=0 7-206
BufCiCLP This 8-bit value determines a global cell filling level
threshold with a granularity of 1024 cells that triggers
explicit packet discard (EPD) for CLP=1 tagged
frames used by GFR traffic class service (low
watermark).
7-208
SbCiCLP T his threshold determines a maximum number of low
priority cells allowed to be stored per scheduler block
with a granularity of 64 cells
7-211
1) mixed threshold: EPD if enabled; otherwise, maximum threshold
Abbreviation Description See
page
Prel. ABMP Data Sheet
Operational Description
Preliminary Data Sheet 105 2001-14-01
PRELIMINARY
4.2.2 ABM Configuration Example
In this section, a popular mini-switch scenario (Figure 4-2) is used to de scrib e the most
important points for the software configuration of the ABMP. Among other t hings, the fol-
lowing fixed assignments can be made in software by the user:
• Assignment of Schedulers to PHYs and programming of Scheduler output rates
• Definition of the necessary traffic classes
• Assignment of the queues to the traffic classes
• Assignment of the queues (QIDs) to the Schedulers (SIDs)
Assignment of Schedulers and Programming Output Rates:
The ABMP has 256 Schedulers (128 in the upstream direction and 128 in the down-
stream direction). In this example each xDSL device is assigned to a separate Scheduler
(this guarantees each xDSL device a 2-Mbit/s data throughput without bandwidth restric-
tions caused by the other xDSL devices); then, 255 xDSL devices can be connected.
The 256th Schedu ler will be occupied by the E3 uplink to the public network. The assign-
ment of the Schedulers to the PHYs is totally independent and even such a strong
asymmetrical structure as in (Figure 4-2) can be supported. The output rates of the
Schedulers must be pr ogr amme d i n such a way tha t the to tal sum do es n ot excee d 622
Mbit/s (paylo ad rate). From the exam ple, the f ollowi ng result is deriv ed: 255 x 2 Mbi t/s +
1 x 34 Mbit/s = 544 Mbit/s ≤ 622 Mbit/s.
Figure 4-2 ABMP Application Example: DSLAM
Prel. ABMP Data Sheet
Operational Description
Preliminary Data Sheet 106 2001-14-01
PRELIMINARY
Definition of Necessary Traffic Classes:
The ABM allows up to 16 traffic classes to be defined by Traffic Class Table RAM entry
via the registers TCT0 and TCT1, Page 93. In this example, there are 3 traffic classes:
• CBR (real-time) = traffic class 1
• GFR (non-real-time) = tr affi c class 2
• UBR (non-real-time) = traffic class 3
Assignment of the queues to the traffic classes:
Each queue must relate to a defined traffic class according to the Queue Configuration
Table RAM entry via the TrafClass(3:0) bits of the QCT table.
Assignment of the Queues (QIDs) to the Schedulers (SIDs):
Every Scheduler possesses a certain number of queues depending on the assignment
by the user of the SID(5:0) bits of register QCT1. In the example, every ADSL device has
four data connections so that four queues per Scheduler are necessary. Each Scheduler
of the ABM has one real-time queue and an arbitrary number of non-real-time queues.
For Schedulers #1..#255 , indicate that the first queue belongs to Traffic Class 1, the 2nd
and 3rd Queue to Traffic Class 2, and the 4th Queue to Traffic Class 3. There are 1020
(1..1020) queues altogether for Schedulers #1..# 255. The 256th scheduler must be able
to serve the 255 xDSL devices (255 Schedul ers and appropriate queues). Thus, Sched-
uler #256 has 255 x 2 = 510 non-real-time queues as every Scheduler from #1..#255
possesses two GFR non-real-time queues (GFR has a guaranteed minimum rate; thus,
each GFR queue needs a per VC queueing). The 255 UBR queues of Schedulers
#1..#255 need onl y on e UBR queue at the 256th Schedul er as U BR has no gu ara nteed
minimum rate. As every Scheduler has only one real-time queue, the 255 real-time
queues from Schedulers #1..#255 flow into the one real-time queue of Scheduler #256.
Therefore, Scheduler #256 needs the assignment of 510 (GFR) + 1 (UBR) + 1 (CBR) =
512 queues.
4.2.3 Normal Operation
In normal operati on, no microprocessor interactio n is necessary as the ABMP chip does
all queuing and scheduling automatically. For maintenance purposes, periodically the
microprocessor could read out the counters for buffer overflow events. Some overflow
events may also be programmed as interrupts.
The only instance of permanent microprocessor interaction is operation of the dynamic
bandwidth a llocation p rotocol. In thi s case, t he mi cropro cessor mu st permane ntly check
the two fill thresholds of the upstream Schedulers and adjust their output rates
accordingly.
In case of static bandwidth allocation, all rate adjustments are made only at connection
setup or teardown.
Prel. ABMP Data Sheet
Operational Description
Preliminary Data Sheet 107 2001-14-01
PRELIMINARY
4.2.4 Bandwidth Reservation
Due to the WFQ Scheduler concept of the ABMP, the Connection Acceptance Check
(CAC) is very simple:
• Check if the Guaranteed Rate of the connection fits within the spare bandwi dth of the
Scheduler.
For the definition of the Guaranteed Rate, see Table 3-1. Mathematically, the CAC can
be reduced to the following formulas:
For all connections, verify that the Scheduler is not overbooked:
Sum of Guaranteed Rates ≤ Scheduler output rate (1)
For real-time connections, (CBR, VBR-rt) in equation (1) is the only condition required.
For non-real-time connections or connections using the WFQ Multiplexer, additional
conditions must be fulfilled.
VBR, ABR and UBR + connections must be set up in per-VC queuing confi gurations, that
is, an empty queu e must be foun d for the connection. The Guara nteed Rat e determi nes
the weight of the queue:
ni = INT (2)
with
•n
i ∈ {1, 2, 3, ...15360} is the WFQ factor for the connection i
(1/ni is the weight factor Wi)
GRmin the defined constant defining the minimum rate to be guaranteed
Note: n
i
with a maximum value of 15360 due to hardware limitations.
Note: In addition to the hardware related tasks, a key system constant must be pre-
defined: the minimum Guaranteed Rate GR
min
. This parameter provides an
absolute value to the relative weight factors of the WFQ Multiplexers. It is usually
identical for all Schedulers in a system, as the Guaranteed Rate is related to the
service classes - and these are identical for all users, independent of where they
are connected to a network.
• INT(x) the integer part of x.
The integer function in equation (2) selects the next s maller value of the integer n, that
is to say, the weight fa ctor is hi gher than re quired and, thus, the queue is ser ved slig htly
faster in order to guarantee the rate.
For UBR connections w ithout any rate guarantee, t he follow ing proced ure is app ropriate
for the W FQ Multiple xer:
• Reserve one queue per Scheduler for all UBR connections
GRmin
GR
---------------------214
×
Prel. ABMP Data Sheet
Operational Description
Preliminary Data Sheet 108 2001-14-01
PRELIMINARY
• Assign minimum weight factor to this queue
• Take the bandwidth of the queue into account using formulas (1) and (2) as if for a
non-real-time connection
• Assign UBR connections to this queue without any further CAC
Note: EPD/PPD functionality is offered by the ABMP on a per-VC basis. Hence, these
functions can be supported also for UBR connections sharing one queue.
Note: In addition to the ban dwidth reservation, buffer space must be assigned by the ap-
propriate setting of thresholds.
4.2.5 Bandwidth Reservation Example
As an example, an access network multiplexer is assumed with ADSL lines and an E3
uplink. CBR and UBR+ connections are supported. A minimum Guaranteed Rate of
GRmin = 19.2 kbit/s is selected. This allows GR up to 314.57 Mbit/s with increasin g gran-
ularity for higher values.
This behavior is w el l suited to the Guaranteed Rates which are mi nimum or sustai nabl e
rates. The values for MCR and SCR will be well below 10 Mbit/s for public networks. In
high speed LANs with high MCR and SCR values, a higher minimum rate could be
selected.
Additionally, it is assumed that three types of line interfaces (PH Y) exist in the system:
34 Mbit/s for the uplink, ADSL rates of 8 Mbit/s downstream, and 0.6 Mbit/s upstream.
For each PHY, a maximum possible weight factor 1/n exists: nmax = 9, nmax= 39, and
nmax = 524, respectively.
Two types of non-real-time connection are defined with Guaranteed Rates of 100 kbit/s
and 20 kbit/s with the weight factors 1/n, n100 = 3146 and n20 = 15730, re spectively. The
100 kbit/s connections would be used for the downstream direction, and the 20 kbit/s
connections for the upstream direction. Table 4-1 provides the maximum number of con-
nections possible on each PHY.
Table 4-1 Number of Possible Connections per PHY
PHY GR = 100 kbit/s GR = 20 kbit/s
34 Mbit/s 349 1747
8 Mbit/s 80 403
0.6 Mbit/s 6 30
Prel. ABMP Data Sheet
Operational Description
Preliminary Data Sheet 109 2001-14-01
PRELIMINARY
For example, if the maximum number of connections for each Subscriber is fixed (such
as 5 data connections), the queues can be pre-configured for each Subscriber so that
only the LCI assignment must be changed when a connection is setup or released.
4.2.6 Programming of the Peak Rate Limiter / PCR Shaper
For each queue, an optional peak rate shaper can be programmed. The possible peak
rate values can be determined with:
r = [cells/s] (3)
with
•m ∈ {1, 2, 3, ...65472} the rate factor
•T
StepC ∈ {0, 1, 2, 3, ...7} the shaper speed factor
(default TStepC = 4 guarantees compatibility to ABM version 1.1)
(see “USCONF/DSCONF” on Page 252 for coding of parameter TStepC)
• rmin depending on the total throughput, i.e. the clock frequency:
rmin = [cells/s] (4)
The following table provides some examples for the minimum cell rates to be shaped
depending on configuration value TStepC:
Table 4-2 Minimum Peak Rate Shaper Values
Minimum
Rates SYSCLK
TStepC 52 MHz 80 MHz
0 6.20 cells/s 2.38 kbps 9.54 cells/s 3.67 kbps
1 12.40 cells/s 4.76 kbps 19.07 cells/s 7.32 kbps
2 24.80 cells/s 9.52 kbps 38.15 cells/s 14.65 kbps
3 49.59 cells/s 19.04 kbps 76.29 cells/s 29.30 kbps
4 (default) 99.18 cells/s 38.09 kbps 152.58 cells/s 58.59 kbps
5 198.36 cells/s 76.17 kbps 305.16 cells/s 117.19 kbps
6 396.73 cells/s 152.34 kbps 610.35 cell/s 234.38 kbps
7 793.46 cells/s 304.69 kbps 1220.70 cells/s 468.75 kbps
rmin
m
--------------216
×
SYSCLK
216
-------------------------2TStepC 7–()
()×
Prel. ABMP Data Sheet
Operational Description
Preliminary Data Sheet 110 2001-14-01
PRELIMINARY
4.2.7 Scheduler Output Rate Calculation Example
The parameters of the Schedulers must be chosen in relation to the transmission rates
of the PHYs, respectively. That means for a Scheduler which transmits in the upstream
direction such as 150 Mbit/s output rate and for a Scheduler which transmits in the down-
stream direction such as 6 Mbit/s output rate for a ADSL device (as depicted in Figure 4-
2). Within the ABM, the Scheduler output rate is represented by the two parameters:
IntRate(13:0) and FracRate(7:0). These parameters are without dimension and thus only
indirectly represent the output rate. The following part declares how to derive the two pa-
rameters by a time parameter T and the correlation between these parameters and the
output rate R:
T = [without dimension] (5)
with
• ABM core clock SYSCLK = [1/s]
• Scheduler output rate R = [cells/s]
IntRate = (6)
with
• int(T) is integer part of T
FracRate = (7)
Note: ‘ceil’ is an operator that rounds-up to the next integer number.
Example:
Ch osen values: R0 = 347000 cells/s (150 Mbit/s), SYSCLK = 50 MHz
with (5)⇒
thus with (6) and (7)⇒
IntRate = 4 and FracRate = 130 (rounded up)
Because of rounding the FracRat e value, the effective scheduler rate R needs to be cal-
culated by solving equation (7) to T and equation (5) to R:
⇒
SYSCLK
32 cells 1–R×
------------------------------------
int T()
ceil T int T()–{}256×
T050 106
×
32 347000×
---------------------------------4.50288…==
T130 1–
256
-------------------IntRate T0
[]4.5039…=+=
Prel. ABMP Data Sheet
Operational Description
Preliminary Data Sheet 111 2001-14-01
PRELIMINARY
and
4.2.8 Empty Cell Rate Calculation Example
The internal SDRAM refresh generator uses empty cell cycles to perform its refresh cy-
cles. Thus the refresh function is closely related to the scheduler output rate
configuration. The empty cell rate generator guarantees a minimum number of empty
cell cycles required for refresh cycles. A maximum value for parameter T can be derived
by the following term:
with:
• ABMP core clock SYSCLK = [1/s]
• SDRAM RefreshPeriod = [s]
• SDRAM RefreshCycles requirement
The empty cel l rate p arameter defin ition for fracti onal and i nteger parts of T is accordi ng
to equations (5) and (6).
Example:
Given values: RefreshPeriod = 64ms, RefreshCycles = 4096, SYSCLK = 50 MHz
⇒ Tmax = 24.414
Thus the value of T that is repres ented by programmed device parameters IntRate and
FracRate acco rding to equations (6) and (7), must be less or equal to T max to g uarantee
sufficient refresh cycles according to the SDRAM specification.
In case of addi tional bandwidth needs to be reser ved (e.g. for mu lticast operati on in sub-
sequent devices), a second maximum condition for parameter T can be derived
depending on the empty cell rate required for multicast bandwidth reservation. In this
case the value of T must conform the following equation:
R50 106
×
32 4.5039…×
------------------------------------- cells 1–346921cells 1–
==
Tmax SYSCLK RefreshPeriod×
32 RefreshCycles×
--------------------------------------------------------------------------8()=
TMinT
equation 5()
TMCreservation Tmax
,{, } 9()=
Prel. ABMP Data Sheet
Operational Description
Preliminary Data Sheet 112 2001-14-01
PRELIMINARY
4.2.9 Traffic Classes
4.2.9.1 CBR Connections
These connections should use the real-time bypass of the respective Scheduler. How-
ever, if tw o pri ority level s for real-t ime connectio ns mu st be offer ed, a sligh tly lower real-
time perfor mance can be achi eved by using the W FQ Multi plexer wi th maximum wei ght.
In this case, the bandwidth must fit into the WFQ Multiplexer (conditions (1) and (2) in
“Bandwidth Reservation” on Page 107).
4.2.9.2 VBR-rt Connections
These connectio ns can be treate d like C BR connections w ith a gua ranteed cell rate l ess
than or equ al to the Peak Cell Rate (PCR). D ependin g on the beha vior o f the sour ces, a
statistical benefit could be obtained by reserving less than PCR.
As an example, assume 1000 connections with compressed voice are multiplexed on a
link. PCR is 32 kbit/s, but on average only 16 kbit/s. SCR is 8 kbit/s. Hence, instead of
reserving 32 Mbit/s for the ensemble of connections, only 16 Mbit/s must be reserved.
The large number of connections guarantees that the mean sum rate of 16 Mbit/s is nev-
er exceeded.
4.2.9.3 VBR-nrt Connections
For these connections, the three parameters PCR, SCR, and MBS are given. One queue
is reserved for each VBR-nr t connecti on wit h SCR program med as the w eight of the r e-
spective Scheduler queue. The maximum queue size is set to MBS plus ~100 cells for
cell level bursts. If the buffer space reserved for VBR-nrt connections is set to the sum
of all MBS, i t i s gua ran teed that no cell is lo st. Ho wever , w it h a lar ge numb er of VBR-nrt
connections, the total reserved buffer can be smaller with a negligible number of cell
losses.
For the PCR, no adjustment is necessary as the rates of the queues of a Scheduler al-
ways adjust automatically to the maximum possible values. As an option for network
endpoints, the PC R m ay be sha ped. The output rate of each queue may b e l imite d i ndi -
vidually to a programmable value which results in PCR shaping. This could be useful at
points where a connection l eaves one network and enters the next network which might
police the connection (NPC function).
4.2.9.4 ABR Connections
ABR connections must be setup in per-VC queuing configuration. The queue is assigned
a weight guaranteeing the MCR of the connection.
A backward direction connection must be setup. In Bi-dire ctional Mode, the same queue
ID must be chosen in order to make the ABR functions work properly.
Prel. ABMP Data Sheet
Operational Description
Preliminary Data Sheet 113 2001-14-01
PRELIMINARY
Binary ABR marking functions can be performed by programming an appropriate traffic
class in the queue manager. For ABR explicit rate or VS/VD functions, the ERC unit must
be programmed accordingly for the same QID.
In Uni-directional Mode, the queue ID value with the toggled LSB must be setup for the
backward direction. EFCI marking in forward data cells or CI/NI marking in backward RM
cells can be enabled per traffic class.
Note: Also th e LCI is toggled in the Uni-directi onal Mode (see “LCI Translation in Mini-
Switch Configuratio ns” on Page 27).
4.2.9.5 UBR+ Connections
UBR+ connections are UBR connections with MCR. They must be setup in individual
queues with the weight factor guaranteeing the MCR.
To enhance the overall throughput, the EPD/PPD function is enabled.
4.2.9.6 GFR Connections
GFR Connections are setup like UBR+ connections with a Guaranteed Rate in individual
queues, with the weight factor guaranteeing the rate for the high-priority packets. The
threshold for the discard for low-priority packets must be set accordingly.
4.2.9.7 UBR Connections
As described in “Bandwidth Reservation” on Page 107, one queue per Scheduler is
reserved for UBR connections with the smallest weight assigned. All UBR connections
share this queue. EPD/PPD can be enabled as the relevant parameters are stored per
connection (LCI table).
4.2.9.8 Generic Service Classes
4.3 Basic Enhanced Rate Contr ol Initialization
After reset, the ERC unit automatically starts loading the firmware either from the internal
ROM or from an external serial EEPROM via the SPI interface. The Source is selected
by signal ‘IOPRAMSEL’ (“SPI Interface (5 pins)” on Page 41).
In either case, firmware download completion is indicated by status bit ‘FWDF’ (bit 15)
in register “ERCCONF0” o n Page 293 that can be polled by the external uP.
At this time the ERC will start to run the firmware initialization and self-test routines.
Completion of firmware ini tialization will be reported to the exter nal uP by a message via
the ERC uP mailbox.
Prel. ABMP Data Sheet
Operational Description
Preliminary Data Sheet 114 2001-14-01
PRELIMINARY
After generating this message the firmware is fully operative and in its “idle loop”. The
external uP may:
• enable the SCAN unit,
• set-up connections,
• modify/monitor connection parameter ,
• tear-down connections.
4.4 Connection Tear-Down Example
Teardown of Queues
Disabling a queue via the queue-disable bit does not clear the cells contained in the
queue, but:
• The acceptance of the queue for new cells is disabled
• The queue is still served, but the cells are discarded
Normally, at the time a queue is cleared, there will be no more cells in the queue. This
can be checked by reading the queue length.
In case of a hig hly filled queue which is served slow ly, the time to e mpty the que ue could
be long. To deplete the queue more quickly, its weight can be increased temporarily.
However, because the discarded cells produce idle times on the UTOPIA output, the
chosen weight factor should not be too high.
4.5 AAL5 Packet Insertion/Extraction
(For future document version.)
4.6 Exception Handling
The ABMP provides a set of ‘fatal error’ interrupts and few interrupts that are required for
normal operation. Those are
• control interrupts for activation/de-activation of VC-merge groups
• control interrupts for activation/de-activation of ‘dummy’ queues
• control interrupts for DBA threshold crossing information
It is recommended to reset the device upon occurrence of a ‘fatal interrupt’ which is
generated by the ABMP detecting internal consistency violations.
Prel. ABMP Data Sheet
Interface Descript ion
Preliminary Data Sheet 115 2001-14-01
PRELIMINARY
5 Interface Description
5.1 UTOPIA L2 Interfaces (PHY-side)
The UTOPIA interface to the PHY is ATMF UTOPIA Level2 and Level1 compliant. The
interf ace can be config ured in Master or Slave Mode. Inter nal UTOPIA FIFOs guarantee
Head-of-Line Blocking free operation in both modes. Each interface direction (receive
and transmit) is independently clocked. The PHY-side and Backplane-side UTOPIA
interfaces are identical with minor exceptions as described in the subsequent chapters.
5.1.1 URXU: UTOPIA Receive Upstream (PHY side)
The UTOPIA receive i nterface supports up to 48 PHY addresses that can individ ually be
enabled.
In Master mode, 48 PHYs are supported in 4 groups (4*12 scheme).
In slave configuration two polling modi are supported []:
• Up to 48 Ports in 4 groups (4*12 scheme)
• Up to 31 Ports in 1 group (1*31 scheme)
Note: In slave mode, the interface responds to all enabled port addresses in either
scheme.
Figure 5-1 UTOPIA Receive Upstream Master Mode
PHY 3
Address
0..11
PHY 2
Address
0..11
PHY 1
Address
0..11
URXDATU(15:0)
URXSOCU
URXPRTYU
URXCLKU
URXADRU(4:0)
URXENBU(3:0)
URXCLAVU(3:0)
UTOPIA Receive Upstream
(PHY side)
Master Mode
4 cell FIFO
Backpressure
Cell Handler (Upstream)
Addressing up to
4*12 PHYs:
PHY 0
Address
0..11
Prel. ABMP Data Sheet
Interface Descript ion
Preliminary Data Sheet 116 2001-14-01
PRELIMINARY
Figure 5-2 UTOPIA Receive Upstream Slave Mode
Head of Line Blocking Avoidance
The inter nal Cell H andl er U ni t accepts an y cell fr om the com mon UTOPIA r eceiv e FIFO
to either accept the cell or discard the cell depending on threshold decisions. Thus no
HOL blocking can occur.
Optionally, internal t hresholds can be enabled to ge nerate backpressure to UTOPIA port
groups in a fixed scheme []:
• Threshold 0 effects ports {0, 4, 8, 12, 16, 20, 24, 28, 32, 36, 40, 44}
• Threshold 1 effects ports {1, 5, 9, 13, 17, 21, 25, 29, 33, 37, 41, 45}
• Threshold 2 effects ports {2, 6, 10, 14, 18, 22, 26, 30, 33, 38, 42, 46}
• Threshold 3 effects ports {3, 7, 11, 15, 19, 23, 27, 31, 34, 39, 43, 47}
In case of pending backpressure, a specific port reacts in the same way as being
disabled:
• Master Mode:
A backpressured (or disabled) port is deleted from the polling scheme.
• Slave Mode:
A backpressured (or disabled) port does not generate a cell available signal indication.
Note: The internal backpressure does only effect the polling/response scheme. The
UTOPIA receive FIFO is serviced in any case to avoid HOL blocking.
URXDATU(15:0)
URXSOCU
URXPRTYU
URXCLKU
URXADRU(4:0)
URXENBU(3:0)
URXCLAVU(3:0)
UTOPIA Receive Upstream
(PHY side)
Slave Mode
4 cell FIFO
Backpressure
Cell Handler (Upstream)
Responding to
a) up to 4*12 addresses
b) up to 1*31 addresses
(URXENBU(0), URXCLAVU(0) only)
Prel. ABMP Data Sheet
Interface Descript ion
Preliminary Data Sheet 117 2001-14-01
PRELIMINARY
5.1.2 UTXD: UTOPIA Transmit Downstream (PHY side)
The UTOPIA transmit interface supports up to 48 PHY addresses that can individually
be enabled.
In Master mode, 48 PHYs are supported in 4 groups (4*12 scheme).
In slave configuration two polling modi are supported []:
• Up to 48 Ports in 4 groups (4*12 scheme)
• Up to 31 Ports in 1 group (1*31 scheme)
Note: In slave mode, the interface responds to all enabled port addresses in either
scheme.
A cell buffer pool of 9 6 cells is provided for UTOPIA port specifi c queues. The num ber of
enabled ports determines the queue length that can be configured, e.g. 2 cells per queue
in case all 48 ports are enabled.
Figure 5-3 UTOPIA Transmit Downstream Master Mode
PHY 3
Address
0..11
PHY 2
Address
0..11
PHY 1
Address
0..11
UTXDATD(15:0)
UTXSOCD
UTXPRTYD
UTXCLKD
UTXADRD(4:0)
UTXENBD(3:0)
UTXCLAVD(3:0)
UTOPIA Transm it Downs t ream
(PHY si d e )
Master Mode
Scheduler Block
Cell Handler (Downstream)
Addressing up to
4*12 PHYs:
PHY 0
Address
0..11
96 Cells Buffer Pool:
Logical Queues per
UTOPIA port
Queue Specific
Backpressure
Prel. ABMP Data Sheet
Interface Descript ion
Preliminary Data Sheet 118 2001-14-01
PRELIMINARY
Figure 5-4 UTOPIA Transmit Downstream Slave Mode
Head of Line Blocking Avoidance
The internal Cel l Handler Unit forw ards cells to UTOPIA port specifi c queues. In case of
a filled queue, queue-specific backpressure is signalled to all schedulers that are
associated to that queue/port prohibiting further cell emits. Thus no HOL blocking can
occur.
UTXDATD(15:0)
UTXSOCD
UTXPRTYD
UTXCLKD
UTXADRD(4:0)
UTXENBD(3:0)
UTXCLAVD(3:0)
UTOPIA T ransmit Downstream
(PHY side)
Master Mo de
Schedule r Block
Cell Handler (Downstream)
96 Cells Buffer Pool:
Logical Queues per
UTOPIA port
Queue Specific
Backpressure
Responding to
a) up to 4*12 addres ses
b) up to 1*31 addres ses
(UTXENBD(0), UTXCLAVD(0) only)
Prel. ABMP Data Sheet
Interface Descript ion
Preliminary Data Sheet 119 2001-14-01
PRELIMINARY
5.1.3 UTOPIA Port/Address Mapping (PHY side)
The following table describes the mapping of UTOPIA addresses and groups to port
numbers.
Table 5-1 Port/Address Mapping
Port Number Group 0 Group 1 Group 2 Group 3
Address Slave
Mode 2 Slave Modes 1 and Master Modes
30 30 - - - -
... ... ... ... ... ...
12 12 - - - -
11 11 11 23 35 47
10 10 10 22 34 46
999213345
888203244
777193143
666183042
555172941
444162840
333152739
222142638
111132537
000122436
Prel. ABMP Data Sheet
Interface Descript ion
Preliminary Data Sheet 120 2001-14-01
PRELIMINARY
5.1.4 Functional UTOPIA Timing (PHY side)
The functional timing is compatible to ATMF UTOPIA Level 2 standard [] and ATMF
UTOPIA Level 1 standard [] respectively.
Remark 1
The ABMP UTOPIA interfaces always introduce at least 2 idle clocks between
transmission or reception of subsequent ATM cells.
Remark 2
The ABMP UTOPIA interfaces in Level 1 slave mode do not support constant active
enable signals UT XENBi/URXENBi (i = {D(Downstrea m); U(Up stream)}).
The enable signals must be deasserted with each cell cycle.
Prel. ABMP Data Sheet
Interface Descript ion
Preliminary Data Sheet 121 2001-14-01
PRELIMINARY
5.1.5 UTOPIA Master Mode Polling Scheme (P HY side)
The polling scheme is based on a port priority list. A serviced port is automatically moved
to the end of the priority list. The priority list port sequence is based on incrementing
addresses; for a given address, the port numbers are in increasing order:
Example:
Assuming port 25 (printed bold in example pattern) is top of the priority list and gets
serviced. Now t he l is t to p p oin ter is m oved t o th e n ext en try whi ch is port 37 (i.e. port 25
becomes the end of the list).
Note: Disabled or internally backpressured port numbers are deleted from the priority
list.
Note: The po lling operation of Recei ve and Transmit interfaces are independe nt to each
other.
Table 5-2 Port Polling Sequence
Address: 0 1234
Sequence: 0 12 24 36 1 13 25 37 2 14 26 38 3 15 27 39 4
Priority: decreasing
priority ->
min Prio.
max Prio.
decreasing pri or i ty ->
Prel. ABMP Data Sheet
Interface Descript ion
Preliminary Data Sheet 122 2001-14-01
PRELIMINARY
5.1.6 UTOPIA Cell Format (PHY side)
The following sub-chapters describe the cell format expected by the ABMP depending
on the selected mapping mode. Transmitted cells have the same format.
The ABMP may modify user-cell field ‘EFCI’ and the LCI field (VC-Merge function)
depending on the configuration. In OAM cells, bits ‘CI’ and ‘NI’ as well as Function
Specific fields may be modified. The CRC10 field gets recalculated accordingly.
5.1.6.1 UTOPIA Level 2 Standard Cell Formats
Note: All Fields According to Standards, Unused Octets Shaded
Note: All Fields According to Standards, Unused Octets Shaded
Table 5-3 Standardized UTOPIA Level 2 Cell Format (16-bit)
bit:1514131211109876543210
0 VPI(11:0) VCI(15:12)
1 VCI(11:0) PT(2:0) CLP
2UDF1 UDF2
3 Payload Octet 1 Payload Octet 2
4 Payload Octet 3 Payload Octet 4
... : :
26 Payload Octet 47 Payload Octet 48
Table 5-4 Standardized UTOPIA Level 2 Cell Format (16-bit): OAM Cells
bit:1514131211109876543210
0 VPI(11:0) VCI(15:12)
1 VCI(11:0) PT(2:0) CLP
2UDF1 UDF2
3 OAM Type(3:0) Function Type(3:0) Function Specific Octet 1
4 Function Specific Octet 2 Function Specific Octet 3
... : :
25 Function Specific Octet 44 Function Specific Octet 45
26 Reserved CRC10
Prel. ABMP Data Sheet
Interface Descript ion
Preliminary Data Sheet 123 2001-14-01
PRELIMINARY
5.1.6.2 LCI Mapping Mode: VPI Mode
In mapping mode ‘VPI’ the ABMP expects a 12 bit local connection identifier in the
locatio n of the VPI fi eld. M apping mode ‘ VPI’ is config ured vi a bitf ield LCIMOD(1:0 )=’00 ’
in Register [].
5.1.6.3 LCI Mapping Mode: VCI Mode
In mapping mode ‘VCI’ the ABMP expects a 16 bit local connection identifier in the
locatio n of the VCI field. Mapping mod e ‘VCI’ is configured via bit field LCIMOD(1:0)= ’01’
in Register [].
Since the ABMP supports 16k connections, the MSB’s bit 15 and 14 of the LCI must
match the selected quar ter segme nt. Oth erw ise the cells ar e au tomati call y for warded to
the global real time bypass queue (Queue 0) and may be handled by a subsequent
ABMP device.
Table 5-5 Standardized UTOPIA Level 2 Cell Format (16-bit): OAM Cells
bit:1514131211109876543210
0LCI(11:0) VCI(15:12)
1 VCI(11:0) PT(2:0) CLP
2UDF1 UDF2
3 Payload Octet 1 Payload Octet 2
4 Payload Octet 3 Payload Octet 4
... : :
26 Payload Octet 47 Payload Octet 48
Table 5-6 Standardized UTOPIA Level 2 Cell Format (16-bit): OAM Cells
bit:1514131211109876543210
0LCI(11:0) VCI(15:12)
1 VCI(11:0) PT(2:0) CLP
2UDF1 UDF2
3 Payload Octet 1 Payload Octet 2
4 Payload Octet 3 Payload Octet 4
... : :
26 Payload Octet 47 Payload Octet 48
Prel. ABMP Data Sheet
Interface Descript ion
Preliminary Data Sheet 124 2001-14-01
PRELIMINARY
5.1.6.4 LCI Mapping Mode: Infineon Mode
In mapping mode ‘Infineon’ the ABMP expects a 16 bit local connection identifier in the
location of the VCI field. Mapping mode ‘Infineon’ is configured via bitfield
LCIMOD(1:0)=’10’ in Register [].
Since the ABMP supports 16k connections, the MSB’s bit 15 and 14 of the LCI must
match the selected quar ter segme nt. Oth erw ise the cells ar e au tomati call y for warded to
the global real time bypass queue (Queue 0) and may be handled by a subsequent
ABMP device.
5.1.6.5 LCI Mapping Mode: Address Reduction Mode
In mapping mode ‘Address Reduction’ the ABMP generates a 16 bit local connection
identifier based on the marked bit fields. Mapping mode ‘Address Reduction’ is
configured via bitfield LCIMOD(1:0)=’11’ in Register [].
Table 5-7 Standardized UTOPIA Level 2 Cell Format (16-bit): OAM Cells
bit:1514131211109876543210
0LCI(11:0) VCI(15:12)
1 VCI(11:0) PT(2:0) CLP
2LCI(13:12) transparent LCI(15:14) UDF2
3 Payload Octet 1 Payload Octet 2
4 Payload Octet 3 Payload Octet 4
... : :
26 Payload Octet 47 Payload Octet 48
Table 5-8 Standardized UTOPIA Level 2 Cell Format (16-bit): OAM Cells
bit:1514131211109876543210
0LCI(11:0) VCI(15:12)
1VCI(11:0) PT(2:0) CLP
2transp. optiona l PNUT(5:0) transp. optional PNUT(5:0)
3 Payload Octet 1 Payload Octet 2
4 Payload Octet 3 Payload Octet 4
... : :
26 Payload Octet 47 Payload Octet 48
Prel. ABMP Data Sheet
Interface Descript ion
Preliminary Data Sheet 125 2001-14-01
PRELIMINARY
Note: Mapping of UTOPIA port number to UDF1 or UDF2 fields is optionally. The port
inform ation used by the internal addr ess reduction unit i s also provided by int ernal
side-band signals .
To generate an interna l connection iden tifier (LCI) , program mable parts of the fields VCI
and VPI optionally supplemented by the UTOPIA port number can be used as basis. The
UTOPIA port number is internally provided either b y side-band signa ls (no modificati ons
to ATM cell) or mapped into either the UDF1 or UDF2 field of the cells. In those cases,
the respective fields are not transparent.
The Address Reduction Mode is described in Chapter 3.2.5.
Prel. ABMP Data Sheet
Interface Descript ion
Preliminary Data Sheet 126 2001-14-01
PRELIMINARY
5.2 UTOPIA L2 Interface (Backplane-side)
5.2.1 URXD: UTOPIA Receive Downstream (Backplane side)
The UTOPIA Receive Downstream Interface is identical to the UTOPIA Receive
Upstream Inte rface as described in Chapter 5.1.1 beside the supported clock frequency
range.
Standard Exceeding UTOPIA Feature:
To support system architectures that require a bandwidth overprovisioning from the
backplane, the URXD can be operated up to 66 MHz which corresponds to a data rate
of 874 Mbit/s received from the backplane. This provides an overprovisioning factor of
1.4 to OC12 data rate on the line side.
Please refer to [] for timing requirements of this operation mode.
5.2.2 UTXU: UTOPIA Transmit Upstream (Backplane side )
The UTOPIA Transmit Upstream Interface is identical to the UTOPIA Transmit
Downstream Interface as described in Chapter 5.1.2.
5.2.3 UTOPIA Port/Address Mapping (Backplane side)
The UTOPIA Port/Address mapping (Backplane side) is identical to the UTOPIA Port/
Address Mapping as described in Chapter 5.1.3.
5.2.4 Functional UTOPIA Timing (Backplane side)
The functional timing is compatible to ATMF UTOPIA Level 2 standard [] and ATMF
UTOPIA Level 1 standard [] respectively.
Remark 1
The ABMP UTOPIA interfaces always introduce at least 2 idle clocks between
transmission or reception of subsequent ATM cells.
Remark 2
The ABMP UTOPIA interfaces in Level 1 slave mode do not support constant active
enable signals UT XENBi/URXENBi (i = {D(Downstrea m); U(Up stream)}).
The enable signals must be deasserted with each cell cycle.
5.2.5 UTOPIA Master Mode Polling Scheme (Backplane side)
The UTOPIA Polling scheme (Backplane side) is identical to the UTOPIA Polling scheme
as described in Chapter 5.1.5.
Prel. ABMP Data Sheet
Interface Descript ion
Preliminary Data Sheet 127 2001-14-01
PRELIMINARY
5.2.6 UTOPIA Cell Format (Backplane side)
The UTOPIA Polling scheme (Backplane side) is identical to the UTOPIA Polling scheme
as described in Chapter 5.1.6.
5.3 MPI: Microprocessor Interface
The ABMP microprocessor interface is a generic asynchronous 16 bit slave-only
interface that supports Intel and Motorola style control signals. The interface is ‘ready’
signal controlled, since execution times for read cycles depend on the specific
transaction, e.g. indirect access of internal tables require more clock cycles than
standard register access.
5.3.1 Intel Style Write Access
Figure 5-5 Intel Style Write Access
MPADR(7:0)
MPCS
MPWR
MPRDY
MPDAT(15:0)
MPMODE
Prel. ABMP Data Sheet
Interface Descript ion
Preliminary Data Sheet 128 2001-14-01
PRELIMINARY
5.3.2 Intel Style Read Access
Figure 5-6 Intel Style Read Access
5.3.3 Motorola style Writ e Access
Figure 5-7 Motorola Style Write Access
MPADR(7:0)
MPCS
MPRD
MPRDY
MPDAT(15:0)
MPMODE
MPADR(7:0)
MPCS
MPDAT(15:0)
(MPRD)
DS
(MPRDY)
RDY
(
DTACK
)
(MPWR)
R/W
MPMODE
Prel. ABMP Data Sheet
Interface Descript ion
Preliminary Data Sheet 129 2001-14-01
PRELIMINARY
5.3.4 Intel Style Read Access
Figure 5-8 Motorola Style Read Access
5.3.5 Interrupt Signals
The ABMP asserts it s interrupt signals if non-masked i nterrupt events are pending i n the
respective interrupt status registers. Interrupt signals are deasserted in case all events
are cleared by writing ‘1’ to pending interrupt bits (e.g. write 0xFFFFH to the respective
Interrupt Status Register). This allows edge sensitive interrupt implementations.
Interrupt sign al s are of type ‘ Open Drain’ to allow wi re d-or implementati ons shar i ng one
interrupt signal with other devices.
MPADR(7:0)
MPCS
(MPRD)
DS
(MPRDY)
RDY
(
DTACK
)
MPDAT(15:0)
(MPWR)
R/W
MPMODE
Prel. ABMP Data Sheet
Interface Descript ion
Preliminary Data Sheet 130 2001-14-01
PRELIMINARY
5.4 External RAM Interfaces
5.4.1 RAM Configurations
The ABMP device uses synchronous dynamic RAM (SDRAM) for the storage of ATM
cells and synchronous static RAM (SSRAM) for the storage of cell pointers. Two SDRAM
Interfaces and one SSRAM Interface are provided. Each of the two SDRAM Interfaces
is associated with one of the ABM Cores. The SSRAM Interface is shared by both ABMP
Cores. All RAM Interfaces are operated with the system clock provided by the ABMP:
Note: The upstream cell storage RAM must always be connected.
Table 5-9 External RAM Sizes
Cell Pointer
SSRAM Min.
Required
Up-
stream Cell
SDRAM
Min.
Required
Down-
stream Cell
SDRAM
UBMTH Up-
stream
Buffer:
DBMTH Down-
stream
Buffer:
e.g.
512 k x 32 bit 128 Mb
e.g.
2*(4Mb*16)
128 Mb
e.g.
2*(4Mb*16)
3FFFFH256k cells 3FFFFH256k cells
e.g.
256 k x 32 bit 64 Mb
e.g.
1*(2Mb*32)
64 Mb
e.g.
1*(2Mb*32)
1FFFFH128k cells 1FFFFH128k cells
e.g.
128 k x 32 bit 32 Mb 32 Mb 0FFFFH64k cells 0FFFFH64k cells
e.g.
256 k x 32 bit 128 Mb
e.g.
2*(4Mb*16)
none 3FFFFH256k cells 0000H0
e.g.
128 k x 32 bit 64 Mb
e.g.
1*(2Mb*32)
none 1FFFFH128k cells 0000H0
e.g.
64 k x 32 bit 32 Mb none 0FFFFH64k cells 0000H0
Prel. ABMP Data Sheet
Interface Descript ion
Preliminary Data Sheet 131 2001-14-01
PRELIMINARY
The minimum required width of the cell pointer SSRAM is in the range 16..20 bit
depending on the selected Cell Storage Size and additional feature configurations:
Note: VBR.2/3 represents VBR shaping function 2 and 3 requiring one additional bit
storage in the CPR for the CLP bit.
EOP Mark. represents one additional bit storage in the CPR for End-of-Packet
indication required by EPD/PPD and VC-Merge operation.
The following table gives an example of supported SDRAM configuration:
Table 5-10 Cell Pointer RAM Width
Cell Storage RAM
cell capacity
(each)
Enabled
Features Stored
Address Ptr
Width
Feature
Bits Min. SSRAM
Width
256k VBR.2/3 +
EOP Mark. 18 2 20
EOP Mark. 18 1 19
none 18 0 18
128k VBR.2/3 +
EOP Mark. 17 2 19
EOP Mark. 17 1 18
none 17 0 17
64k VBR.2/3 +
EOP Mark. 16 2 18
EOP Mark. 16 1 17
none 16 0 16
Prel. ABMP Data Sheet
Interface Descript ion
Preliminary Data Sheet 132 2001-14-01
PRELIMINARY
The following table gives an example of supported SSRAM configurations:
Table 5- 11 SDRAM Configuration Examples
Type Configuration per Direction
512k * 32 (4 bank)
(64Mb Type) 1 SDRAM:
8 bit column address
10 bit row address
2 bit bank select
Note: This Configuration supports only
128k cells storage per direction.
1Mb * 16 (4 bank)
(64Mb Types) 2 SDRAMs:
8 bit column address
12 bit row address
2 bit bank select
Note: This Configuration supports 256k
cells storage per direction.
2Mb * 16 (4 bank)
(128Mb Types) 2 SDRAMs:
9 bit column address
12 bit row address
2 bit bank select
Note: This Configuration supports 256k
cells storage per direction.
(50% memory remains unused)
4Mb * 16 (4 bank)
(256Mb Types) 2 SDRAMs:
9 bit column address
12 bit row address (13)
2 bit bank select
Note: This Configuration supports 256k
cells storage per direction.
(75% memory remains unused; one
of the 13 memory address bits
remains unused)
Table 5-12 SSRAM and SDRAM Type Examples
Type Configuration
SSRAM
1 GALVANTECH GVT71512ZC36 512k * 36
Prel. ABMP Data Sheet
Interface Descript ion
Preliminary Data Sheet 133 2001-14-01
PRELIMINARY
5.4.2 CSR: Cell Storage SDRAM Interfaces
Figure 5-9 CSR Interface and Connection Example
Both CSR Interfaces support 8 bit and 9 bit column address width SDRAM types (see
register “MODE2” on Page 325).
SDRAM
1 Infineon HYB39S64160 BT 4 bank * 1M * 16
2 Infineon HYB39S25616 0BT 4 bank * 4M * 16
Table 5-12 SSRAM and SDRAM Type Examples
Type Configuration
Prel. ABMP Data Sheet
Interface Descript ion
Preliminary Data Sheet 134 2001-14-01
PRELIMINARY
5.4.3 CPR: Cell Pointer SSRAM Interface
Figure 5-10 CPR Interface(s) and Connection Example
5.5 SPI: Serial Pheripheral Interface
Via the SPI interface the ERC subsystem firmware can be loaded into the internal code
RAM during start-up of the device.
The SPI Interface supports EEPROMs with an eight bit address space.
After a system reset, the ABMP starts reading the first byte out of the connected
EEPROM at address 00H. If this byte i s equal AAH, the device continue s reading out the
memory contents. Everytime four bytes are read out of the EEPROM (starting with byte
address 01H), the EEPROM interface writes the read information into the code RAM.
If the first byte in the EEPROM is not equal AAH, the EEPROM interface stops loading
the immediately.
The configuration mechanism through the serial interface can be disabled by pin
IOPRAMSEL. If this pin is connected to ‘0’, the SPI interface is disabled and the code
RAM will be loaded from the internal ROM.
5.5.1 SPI Read Sequence
The ABMP selects an external EEPROM by pulling SPICS low. The eight bit read
sequence is transmitted followed by the eight bit address. After the read instruction and
address is sent, the data stored in the memory at the selected address is shifted in on
the SPISI pin. The read operation is terminated by setting SPICS high (see Figure 5-11).
Prel. ABMP Data Sheet
Interface Descript ion
Preliminary Data Sheet 135 2001-14-01
PRELIMINARY
•
Figure 5-11 SPI Read Sequence
5.5.2 SPI Write Sequence
Prior to any attempt to write data to an external EEPROM, the write enable latch must
be set by issuing the WREN instruction. This is done by setting SPICS low and then
clocking out the WREN instruction. After all eight bits of the instruction are transmitted,
the SPICS will be brought high to set the write enable latch.
Once the write enable latch is set, the user may proceed by issuing a write instruction,
followed by the eight bit address and then the data to be written. In order that data will
actually be written to the EEPROM, the SPICS is set high after the least significant bit
(D0) of the data byte has been clocked in. Refer to Figure 5-12 for detailed illustrations
on the byte write sequence.
Figure 5-12 SPI Write Sequence
5.6 QCI: Queue Congestion Indication Interface
The Queue Congestion Indication Interface provides threshold crossing information of
up to 8k queues of the downstream core. Dedicated queue specific thresholds are
0123456789 14151617181920212223
7 6 0
7 6 5 4 3 2 1 0
00000011
instruction 8 bit address
data in
SPCS
SPCLK
SPSO
SPSI
0123456789 14151617181920212223
7 6 0 7 6 5 4 3 2 1 000000010
instruction 8 bit address data out
SPCS
SPCLK
SPSO
SPSI
Prel. ABMP Data Sheet
Interface Descript ion
Preliminary Data Sheet 136 2001-14-01
PRELIMINARY
internal ly supervi sed using a hysteresi s. The thr eshold e xceed infor mation is store d in a
bit pattern that is accessible via the QCI Interface in a basic HDLC framing.
The QCI Interface supports 2 modi:
• Peri odi c Frame Mode:
The pattern is periodically transmitted with an HDLC framing. The transmit clock is
provided externally.
• Single Step Frame Mode:
A single pattern is transmitted with an HDLC framing if the ‘QCITXFRAME’ signal is
asserted. The transmit clock is provided externally.
The bit-stuffing function is optional. In case of Single Step Frame Mode, the bit-stuffing
can be disabled. The HDLC frame is transmitted-octet synchronous starting with the
‘QCITXFRAME’ signal.
Figure 5-13 QCI Interface
012
81918190
QueueThresholdIndication(8191..0)
Table QTI
read
Mini HDLC Engine
7Eh 1024 Byte (Payload); opt. bit-stuffing CRC16 7Eh7Eh 7Eh
Frame N N+1
N-1
QCI Interface
QCITXCLK QCITXDAT
Note:
At 66 MHz, a complete pattern is
transmitted in appr. 0.125ms.
Note:
1k queues: 128 byte payload
2k queues: 256 byte payload
4k queues: 512 byte payload
8k queues:1024 byte payload
QCITXFRAME
Prel. ABMP Data Sheet
Interface Descript ion
Preliminary Data Sheet 137 2001-14-01
PRELIMINARY
The bit-pattern length can be limited to 1k, 2k, 4k or 8k (maximum number of
downstream queues). The first data bit of the pattern always represents the threshold
status of queue 0, the second bit represents queue 1 respectively (increasing order).
Global confi guration of the QCI u nit is perform ed in register “DQCIC” on Page 187. The
queue specific thresholds are programmed in table QCIT via transfer register “QCIT” on
Page 244.
5.7 Test Interface
in work
5.8 Clock and Reset Interface
5.8.1 Clocking
The ABMP supports different clock domains and clock generation configurations. Please
refer to “Clocking System” on Page 54 for further details.
5.8.2 Reset
The Reset signal can be asserted anytime asynchronously to the system clock. After
detecting an active reset, the ABM P starts internal initi alization processes and resets al l
registers to their reset value. Please refer to chapter “Reset System” on Page 57 for
further details.
Note: Internal and external RAM initialization must be initiated by software via register
“MODE1” on Page 321.
Prel. ABMP Data Sheet
Memory Structure
Preliminary Data Sheet 138 2001-14-01
PRELIMINARY
6 Memory St ruct ure
The ABMP i s a sl ave devi ce regar ding the microcon tro ller bu s and pr ovides a set of 256
16 bit wide registers. Internal tables are accessed via dedicated transfer registers.
Typically the register structure is mapped into the memory address space of the local
controller.
Prel. ABMP Data Sheet
Regi ster Desc ript ion
Preliminary Data Sheet 139 2001-14-01
PRELIMINARY
7 Register Description
This chapter pr ovide s both an over vi ew of the ATM Buffer Manager ABMP Regi ster Set
and detailed register descriptions and Table Access descriptions.
7.1 Overview of the ABM Register Set
Control and operation of the ABMP chip can be done by directly configuring Status
Registers or, to a large extent, by programming the internal tables. Access to these
tables is not direct, but occurs via Transfer Registers and Transfer Commands. Any
transfer must be prepared by writing appropriate values to the Transfer Registers. Bit
positions named ’don’t Write’ must be masked by writing 1 to the corresponding bit
positions in the Mask Register. This avoids overwriting these table bit positions with the
Transfer Register contents, which may cause fatal malfunction. The specific table
position which should be modified with the Transfer Register contents is selected via
Register W AR. Transfer is star ted by writing the table address to Register MAR and a lso
setting the ’Start’ bit . The ABMP device will reset the ’Star t’ bit after transfer completi on.
The ABMP contains the following internal tables for configur ation:
• LCI Table (LCI)
• Traffic Class Table (TCT)
• Queue Configuration Table (QCT)
• Queue Parameter Table 1 (QPT1)
• Queue Parameter Table 2 (QPT2)
• Scheduler Block Occupancy Table (SOT)
• Scheduler Rate Tables (consisting of 4 tables):
- SCTI Upstream
- SCTI Downstrea m
- SCTF Upstream
- SCTF Downstream
• Merge Group Table (MGT)
• Queue Congestion Indication Table (QCIT)
The following illustration gives an overview of all (user accessible) tables and related
control/transfer/mask registers:
Prel. ABMP Data Sheet
Regi ster Desc ript ion
Preliminary Data Sheet 140 2001-14-01
PRELIMINARY
Figure 7-1 Table Access Overview
The Status Registers and Transfer Registers are described below in Table 7-2. Offset
addresses are 16-bit word addresses. Performing Write accesses to ’Reserved Register’
addresses is not recommended in order to prevent malfunctions and to guarantee
upwards compatibility to future versions of the device.
LCI Table
MAR =
00d
TCT Tabl e
MAR =
01d
QCT
Table
MAR =
02d
SOT
Table
MAR =
03d
MGT
Table
MAR =
07d
QCI Table
MAR =
08d
DTC Table
MAR =
05d
MASK6 MASK5 MASK4 MASK3
MASK2 MASK1 MASK0
Common Mask
Register Set:
no Mask no Mask
LCI0
LCI1
LCI2
TCT0
TCT1
TCT2
TCT3
QCT0
QCT1
QCT2
QCT3
QCT4
QCT5
QCT6
SOT0
SOT1
SOT2
SOT3
SOT4
MGT0
MGT1
MGT2
QCIT DTCT
AVT Table
MAR =
10d
QPT1
Table
Upstream
MAR =
16d
QPT2
Table
Upstream
MAR =
17d
QPT1
Table
Downstr.
MAR =
24d
QPT2
Table
Downstr.
MAR =
25d
SCTF
Table
Upstream
MAR =
23d
SCTF
Table
Downstr.
MAR =
31d
ERCM1
ERCM0
ERCT1
ERCT0
UQPTM3
UQPTM2 UQPTM2
UQPTM0
UQPT1T1
UQPT1T0 UQPT2T1
UQPT2T0
UQPT2T3
UQPT2T2
DQPTM3
DQPTM2 DQPTM2
DQPTM0
DQPT1T1
DQPT1T0 DQPT2T1
DQPT2T0
DQPT2T3
DQPT2T2
USCTFM DSCTFM
USCTFT DSCTFT
MAR
WAR
Common
Table Access
Control
Registers:
Mask
Registers
Data Transfer
Registers
Mask
Registers Data Transfer
Registers
SCTI
Table
Upstream
SCTI
Table
Downstr.
no Mask no Mask
USCTI DSCTI
DSADR
USADR
SCTI Table
Access
Control
Registers:
Prel. ABMP Data Sheet
Regi ster Desc ript ion
Preliminary Data Sheet 141 2001-14-01
PRELIMINARY
Internal table entries contain bit-fields for internal device operation only. The different
meaning of fields is illustrated by the following color convention used in the register
chapter:
Table 7-1 Color Convention for Internal Table Field Illustration
Color Meaning
Grey shaded fields are ’unused’. Reading these fields will
return ’0’.
Green shaded fields require attention by CPU. They can be
written or read by CPU; usage depends on the respective
field description. Typically green fields must be written for
initialization and configuration or read for status query.
Blue shaded fields require/allow READ attention by CPU.
Typically blue fields provide counter or status information.
The CPU MUST N O T write to blue fields.
Red shaded fields are for device internal use only and
require NO attention by CPU.
The CPU MUST N O T write to red fields.
Prel. ABMP Data Sheet
Regi ster Desc ript ion
Preliminary Data Sheet 142 2001-14-01
PRELIMINARY
Table 7-2 ABM Registers Overview
Addr
(hex) Register Description Reset
value
(hex)
µPSee
pag
e
Cell Flow Test Registers
01/11 UCFTST/
DCFTST Upstream/Downstream Cell Flow Test
Registers 0000 R/W 152
SDRAM Configuration Registers
02/12 URCFG/
DRCFG Upstream/Downstream SDRAM
Configuration Regi sters 0033 R/W 154
03/13 - Reserved Register 0000 R -
04/14 - Reserved Register 0000 R -
Cell Insertion/Extraction and AA L5 Control Registers
05/15 UA5TXHD0/
DA5TXHD0 Upstream/Downstream AAL5 Transmit
Header 0 Registe rs 0000 R/W 155
06/16 UA5TXHD1/
DA5TXHD1 Upstream/Downstream AAL5Transmit
Header 1 Registe rs 0000 R/W 156
07/17 UA5TXDAT0/
DA5TXDAT0 Upstream/Downstream AAL5Transmit
Data 0 Registers 0000 R/W 158
08/18 UA5TXDAT1/
DA5TXDAT1 Upstream/Downstream AAL5 Transmit
Data 1 Registers 0000 R/W 159
09/19 UA5TXTR/
DA5TXTR Upstream/Downstream AAL5 Transmit
Trailer Registers 0000 R/W 160
0A/1A UA5TXCMD/
DA5TXCMD Upstream/Downstream AAL5 Transmit
Command Registers 0000 R/W 161
0B/1B UA5RXHD0/
DA5RXHD0 Upstream/Downstream AAL5 Receive
Header 0 Registe rs 0000 R/W 162
0C/1C UA5RXHD1/
DA5RXHD1 Upstream/Downstream AAL5 Receive
Header 1 Registe rs 0000 R/W 164
0D/1D UA5RXDAT0/
DA5RXDAT0 Upstream/Downstream AAL5 Receive
Data 0 Registers 0000 R/W 165
0E/1E UA5RXDAT1/
DA5RXDAT1 Upstream/Downstream AAL5 Receive
Data 1 Registers 0000 R/W 166
0F/1F UA5SARS/
DA5SARS Upstream/Downstream AAL5 SAR
Status Registers 0000 R/W 167
Prel. ABMP Data Sheet
Regi ster Desc ript ion
Preliminary Data Sheet 143 2001-14-01
PRELIMINARY
Buffer Occupati on Counter Registers
20 UBOC Upstream/Downstream Buffer
Occupation Registers 0000 R 170
21 DBOC 0000 R 170
22 UNGBOC Up-/Downstream Non-Guaranteed
Buffer Occupation Registers 0000 R 171
23 DNGBOC 0000 R 171
Buffer Threshold and Occupation Capture Registers
24 UBMTH Upstream/Downstream Buf fer Maximum
Threshold Registers 0000 R/W 172
25 DBMTH 0000 R/W 172
26 UMAC Upstream/Downstream Maximum
Occupation Capture Registers 0000 R 174
27 DMAC 0000 R 174
28 UMIC Upstream/Downstream Minimum
Occupation Capture Registers FFFF R 175
29 DMIC FFFF R 175
2A CLP1DIS CLP1 Discard Global Thr eshol d
Registers 0000 R/W 176
Configuration Register
2B CONFIG Configuration Regi ster 0000 R/W 177
Backpressure Control Registers
2C UUBPTH0 Upstream UTOPIA Backpressure
Threshold Register 0 FFFF R/W 178
2D UUBPTH1 Upstream UTOPIA Backpressure
Threshold Register 1 FFFF R/W 179
2E UUBPTH2 Upstream UTOPIA Backpressure
Threshold Register 2 FFFF R/W 180
2F UUBPTH3 Upstream UTOPIA Backpressure
Threshold Register 3 FFFF R/W 181
30 UBPEI UTOPIA Backpressure Exceed
Indication Register 0000 R/W 182
31 DUBPTH0 Downstream UTOPIA Backpressure
Threshold Register 0 FFFF R/W 183
32 DUBPTH1 Downstream UTOPIA Backpressure
Threshold Register 1 FFFF R/W 184
Table 7-2 ABM Registers Overview (cont’d)
Addr
(hex) Register Description Reset
value
(hex)
µPSee
pag
e
Prel. ABMP Data Sheet
Regi ster Desc ript ion
Preliminary Data Sheet 144 2001-14-01
PRELIMINARY
33 DUBPTH2 Downstream UTOPIA Backpressure
Threshold Register 2 FFFF R/W 185
34 DUBPTH3 Downstream UTOPIA Backpressure
Threshold Register 3 FFFF R/W 186
QCI Control Registers
35 DQCIC Downstream Queue Congestion
Indication Control Register 0080 R/W 187
DBA Control Registers
36 DSBT1 Upstream/Downstream DBA Scheduler
Block Threshold Register 1 0000 R/W 189
37 DSBT2 Upstream/Downstream DBA Scheduler
Block Threshold Register 2 0000 R/W 191
38 DSBT3 Upstream/Downstream DBA Scheduler
Block Threshold Register 3 0000 R/W 192
39 DSBT4 Upstream/Downstream DBA Scheduler
Block Threshold Register 4 0000 R/W 194
3A DBACTC DTC Transfer Register 0000 R 197
LCI Table Transfer Registers LCIC, L CI1, LCI2
3B LCI0 LCI Transfer Register 0 0000 R/W 200
3C LCI1 LCI Transfer Register 1 0000 R/W 201
3D LCI2 LCI Transfer Register 2 0000 R/W 202
Traffic Class Table T ransfer Registers TCT0, TCT1, TCT2, TCT3
3E TCT0 TCT Transfer Register 0 0000 R/W 206
3F TCT1 TCT Transfer Register 1 0000 R/W 208
40 TCT2 TCT Transfer Register 2 0000 R/W 211
41 TCT3 TCT Transfer Register 3 0000 R/W 213
Queue Configuration Table Transfer Registers QCT0..6
42 QCT0 Queue Co nfiguration Transfer Register 0 0000 R/W 220
43 QCT1 Queue Co nfiguration Transfer Register 1 0000 R/W 221
44 QCT2 Queue Co nfiguration Transfer Register 2 0000 R/W 224
45 QCT3 Queue Co nfiguration Transfer Register 3 0000 R/W 226
Table 7-2 ABM Registers Overview (cont’d)
Addr
(hex) Register Description Reset
value
(hex)
µPSee
pag
e
Prel. ABMP Data Sheet
Regi ster Desc ript ion
Preliminary Data Sheet 145 2001-14-01
PRELIMINARY
46 QCT4 Queue Co nfiguration Transfer Register 4 0000 R/W 228
47 QCT5 Queue Co nfiguration Transfer Register 5 0000 R/W 228
48 QCT6 Queue Co nfiguration Transfer Register 6 0000 R/W 229
Scheduler Occupancy Table Transfer Registers SOT0..SOT4
49 SOT0 SOT Transfer Register 0 0000 R/W 231
4A SOT1 SOT Transfer Register 1 0000 R/W 232
4B SOT2 SOT Transfer Register 2 0000 R/W 232
4C SOT3 SOT Transfer Register 3 0000 R/W 233
4D SOT4 SOT Transfer Register 4 0000 R/W 234
Merge Group Table
4E MGT0 MGT Transfer Register 0 0000 R/W 236
4F MGT1 MGT Transfer Register 1 0000 R/W 237
50 MGT2 MGT Transfer Register 2 0000 R/W 237
51 - Reserved Register 0000 R/W -
52 - Reserved Register 0000 R/W -
53 - Reserved Register 0000 R/W -
54 - Reserved Register 0000 R/W -
Mask Registers
for Read/Write transfer access control of LCI-, Traffic Class-, Queue Configuration-,
Scheduler Occupancy and Merge Group Tables
55/56 MASK0/
MASK1 Table Access Mask Registers 0/1 0000 R/W 238
57/58 MASK2/
MASK3 Table Access Mask Registers 2/3 0000 R/W 239
59/5A MASK4/
MASK5 Table Access Mask Registers 4/5 0000 R/W 240
5B MASK6 Table Access Mask Registers 6 0000 R/W 241
Queue Congest ion Indication Table
5C QCIT QCIT Transfer Register 0000 R/W 244
5D - Reserved Register 0000 R/W -
5E - Reserved Register 0000 R/W -
Table 7-2 ABM Registers Overview (cont’d)
Addr
(hex) Register Description Reset
value
(hex)
µPSee
pag
e
Prel. ABMP Data Sheet
Regi ster Desc ript ion
Preliminary Data Sheet 146 2001-14-01
PRELIMINARY
5F - Reserved Register 0000 R/W -
Rat e Shaper CDV R egisters
60/80 - Reserved Register 0000 R -
61/81 - Reserved Register 0000 R -
62/82 UCDV/
DCDV Upstream/Downstream Rate Shaper
CDV Registers 0000 R/W 245
63/83 - Reserved Register 0000 R -
64/84 - Reserved Register 0000 R -
Queue Parameter Tables 1 and 2 Mask Registers
65/85 UQPTM0/
DQPTM0 Upstream/Downstream Queue
Parameter Table Mask Registers 0 0000 R/W 246
66/86 UQPTM1/
DQPTM1 Upstream/Downstream Queue
Parameter Table Mask Registers 1 0000 R/W 247
67/87 UQPTM2/
DQPTM2 Upstream/Downstream Queue
Parameter Table Mask Registers 2 0000 R/W 248
68/88 UQPTM3/
DQPTM3 Upstream/Downstream Queue
Parameter Table Mask Registers 3 0000 R/W 249
69/89 UQPTM4/
DQPTM4 Upstream/Downstream Queue
Parameter Table Mask Registers 4 0000 R/W 250
6A/8A UQPTM5/
DQPTM5 Upstream/Downstream Queue
Parameter Table Mask Registers 5 0000 R/W 251
6B/8B USCONF/
DSCONF Upstream/Downstream Scheduler
Configuration Regi sters 0000 R/W 252
6C/8C - Reserved Register 0000 R -
6D/8D - Reserved Register 0000 R -
6E/8E - Reserved Register 0000 R -
6F/8F - Reserved Register 0000 R -
Queue Parameter Tables 1 and 2 Transfer Registers
70/90 UQPT1T0/
DQPT1T0 Upstream/Downstream QPT1 Table
Transfer Register 0 0000 R/W 255
71/91 UQPT1T1/
DQPT1T1 Upstream/Downstream QPT1 Table
Transfer Register 1 0000 R/W 256
Table 7-2 ABM Registers Overview (cont’d)
Addr
(hex) Register Description Reset
value
(hex)
µPSee
pag
e
Prel. ABMP Data Sheet
Regi ster Desc ript ion
Preliminary Data Sheet 147 2001-14-01
PRELIMINARY
72/92 UQPT2T0/
DQPT2T0 Upstream/Downstream QPT2 Table
Transfer Register 0 0000 R/W 259
73/93 UQPT2T1/
DQPT2T1 Upstream/Downstream QPT2 Table
Transfer Register 1 0000 R/W 259
74/94 UQPT2T2/
DQPT2T2 Upstream/Downstream QPT2 Table
Transfer Register 2 0000 R/W 260
75/95 UQPT2T3/
DQPT2T3 Upstream/Downstream QPT2 Table
Transfer Register 3 0000 R/W 261
76/96 - Reserved Register 0000 R/W -
77/97 - Reserved Register 0000 R/W -
78/98 - Reserved Register 0000 R/W -
79/99 - Reserved Register 0000 R/W -
7A/9A - Reserved Register 0000 R/W -
7B/9B - Reserved Register 0000 R/W -
7C/9C - Reserved Register 0000 R/W -
7D/9D - Reserved Register 0000 R/W -
7E/9E - Reserved Register 0000 R/W -
7F/9F - Reserved Register 0000 R/W -
Upstream/Downstream Scheduler Configuration Table Transfer/Mask Registers,
SDRAM Refresh Registers,
UTOPIA Port Select of Common Real Time Queue Registers
A0/B8 USADR/
DSADR Upstream/Downstream SCTI Address
Registers 0000 R/W 263
A1/B9 USCTI/
DSCTI Upstream/Downstream SCTI Transfer
Registers 0000 R/W 264
A2/BA UECRI/
DECRI Upstream/Downstream Empty Cycle
Rate Integer Part Registers 0000 R/W 267
A3/BB UECRF/
DECRF Upstream/Downstream Empty Cycle
Rate Fractional Part Registers 0000 R/W 270
A4/BC UCRTQ/
DCRTQ Upstream/Downstream Common Real
Time Queue UTOPIA Port Select
Registers
0000 R/W 272
Table 7-2 ABM Registers Overview (cont’d)
Addr
(hex) Register Description Reset
value
(hex)
µPSee
pag
e
Prel. ABMP Data Sheet
Regi ster Desc ript ion
Preliminary Data Sheet 148 2001-14-01
PRELIMINARY
A5/BD USCTFM/
DSCTFM Upstream/Downstream SCTF Mask
Registers 0000 R/W 272
A6/BE USCTFT/
DSCTFT Upstream/Downstream SCTF Transfer
Registers 0000 R/W 275
A7/BF - Reserved Register 0000 R -
Scheduler Enable Registers
A8/C0 USCEN0/
DSCEN0 Upstream/Downstream Scheduler
Enable 0 Registers 0000 R/W 277
A9/C1 USCEN1/
DSCEN1 Upstream/Downstream Scheduler
Enable 1 Registers 0000 R/W 277
AA/C2 USCEN2/
DSCEN2 Upstream/Downstream Scheduler
Enable 2 Registers 0000 R/W 278
AB/C3 USCEN3/
DSCEN3 Upstream/Downstream Scheduler
Enable 3 Registers 0000 R/W 279
AC/C4 USCEN4/
DSCEN4 Upstream/Downstream Scheduler
Enable 4 Registers 0000 R/W 279
AD/C5 USCEN5/
DSCEN5 Upstream/Downstream Scheduler
Enable 5 Registers 0000 R/W 280
AE/C6 USCEN6/
DSCEN6 Upstream/Downstream Scheduler
Enable 6 Registers 0000 R/W 281
AF/C7 USCEN7/
DSCEN7 Upstream/Downstream Scheduler
Enable 7 Registers 0000 R/W 281
Common Real Time Queue Rate Registers
B0/C8 UCRTRI/
DCRTRI Upstream/Downstream CRT Rate
Integer Registers 0000 R/W 282
B1/C9 UCRTRF/
DCRTRF Upstream/Downstream CRT Rate
Fractional Registers 0000 R/W 283
B2 - Reserved Register 0000 R -
B3 - Reserved Register 0000 R -
B4 - Reserved Register 0000 R -
B5 - Reserved Register 0000 R -
B6 - Reserved Register 0000 R -
Table 7-2 ABM Registers Overview (cont’d)
Addr
(hex) Register Description Reset
value
(hex)
µPSee
pag
e
Prel. ABMP Data Sheet
Regi ster Desc ript ion
Preliminary Data Sheet 149 2001-14-01
PRELIMINARY
B7 - Reserved Register 0000 R -
ERC Registers
CA ERCT0 AVT Table Transfer Register 0 0000 R/W 286
CB ERCT1 AVT Table Transfer Register 1 0000 R/W 287
CC ERCM0 AVT Table Access Mask Register 0 0000 R/W 288
CD ERCM1 AVT Table Access Mask Register 1 0000 R/W 289
CE - Reserved Register 0000 R -
CF - Reserved Register 0000 R -
D0 - Reserved Register 0000 R -
D1 - Reserved Register 0000 R -
D2 ERCMB0 ERC MailBox Register 0 0000 R/W 290
D3 ERCMB1 ERC MailBox Register 1 0000 R/W 291
D4 ERCMB2 ERC MailBox Register 2 0000 R/W 292
D5 ERCCONF0 ERC Configuration Register 0 0000 R/W 293
D6 ERCCONF1 ERC Configuration Register 1 0000 R/W 294
PLL Control Registers
D7 PLL1CONF PLL1 Configuration Register 0000 R/W 296
D8 PLL2CONF PLL2 Configuration Register 0000 R/W 298
D9 PLLTST PLL Test Register 0000 R/W 300
ERC Register Access Control
DA ERCRAC ERC Register Access C o ntrol Register 0000 R/W 301
DB ERCRAM ERC Register Access Mask Register 0000 R/W 303
Reserved Test Registers
DC - Reserved Register 0000 R/W -
DD - Reserved Register 0000 R/W -
DE - Reserved Register 0000 R/W -
DF - Reserved Register 0000 R/W -
E0 - Reserved Register 0000 R/W -
ABM Version Code R egi sters
E1 VERL Version Number Low Register F083 R 304
Table 7-2 ABM Registers Overview (cont’d)
Addr
(hex) Register Description Reset
value
(hex)
µPSee
pag
e
Prel. ABMP Data Sheet
Regi ster Desc ript ion
Preliminary Data Sheet 150 2001-14-01
PRELIMINARY
E2 VERH Version Number High Register 1007 R 304
Interrupt Status/Mask Registers
E3 ISRU Interrupt Status Register Upstream 0000 R/W 305
E4 ISRD Interrupt Status Register Downstream 0000 R/W 308
E5 ISRC Interrupt Status Register Common 0000 R/W 311
E6 IMRU Interrupt Mask Register Upstream 0000 R/W 312
E7 IMRD Interrupt Mask Register Downstream 0000 R/W 313
E8 IMRC Interrupt Mask Register Common 0000 R/W 314
E9 ISRDBA Interrupt Status Register DBA 0000 R/W 315
EA IMRDBA Interrupt Mask Register DBA 0000 R/W 316
RAM Select Registers
EB MAR Memory Address Register 0000 R/W 317
EC WAR Word Address Register 0000 R/W 319
Global ABM Status and Mode Registers
ED STATUS ABM STATUS Register 0000 R/W 320
EE MODE1 ABM Mode 1 Register 0000 R/W 321
EF MODE2 ABM Mode 2 Register 0000 R/W 325
UTOPIA Configuration Registers
F0 UTRXCFG Upstream/Downstream UTOPIA Receive
Configuration Regi ster 0001 R/W 327
F1 UUTRXP0 Up stream UTOPIA Receive Port
Register 0 0000 R/W 329
F2 UUTRXP1 Up stream UTOPIA Receive Port
Register 1 0000 R/W 329
F3 UUTRXP2 Up stream UTOPIA Receive Port
Register 2 0000 R/W 330
F4 DUTRXP0 D ownstream UTOPIA Receive Port
Register 0 0000 R/W 331
F5 DUTRXP1 D ownstream UTOPIA Receive Port
Register 1 0000 R/W 331
Table 7-2 ABM Registers Overview (cont’d)
Addr
(hex) Register Description Reset
value
(hex)
µPSee
pag
e
Prel. ABMP Data Sheet
Regi ster Desc ript ion
Preliminary Data Sheet 151 2001-14-01
PRELIMINARY
F6 DUTRXP2 D ownstream UTOPIA Receive Port
Register 2 0000 R/W 332
F7 UUTTXCFG Upstream UTOPIA Transmit
Configuration Regi ster 0000 R/W 333
F8 DUTTXCFG Downstream UTOPIA Transmit
Configuration Regi ster 0001 R/W 334
F9 UUTTXP0 Upstream UTOPIA Transmit Port
Register 0 0000 R/W 336
FA UUTTXP1 Upstream UTOPIA Transmit Port
Register 1 0000 R/W 336
FB UUTTXP2 Upstream UTOPIA Transmit Port
Register 2 0000 R/W 337
FC DUTTXP0 Downstream UTOPIA Transmit Port
Register 0 0000 R/W 338
FD DUTTXD1 Downstream UTOPIA Transmit Port
Register 1 0000 R/W 338
FE DUTTXD2 Downstream UTOPIA Transmit Port
Register 2 0000 R/W 339
Test Regi sters/Special Mode Registers
FF TEST TEST Register 0000 R/W 340
Table 7-2 ABM Registers Overview (cont’d)
Addr
(hex) Register Description Reset
value
(hex)
µPSee
pag
e
Prel. ABMP Data Sheet
Regi ster Desc ript ion
Preliminary Data Sheet 152 2001-14-01
PRELIMINARY
7.2 Detailed Register Description
Register 1 UCFTST/DCFTST
Upstream/Downstream Cell Flow Test Registers
•
CPU Accessibility : Read/Write
Reset Value: 0000H
Offset Address: UCFTST 01HDCFTST 11H
Typical Usage: Written by CPU to test internal integrity functions during
special system test scenarios
Bit151413121110 9 8
Unused(15:8)
Bit76543210
Unused(7:2) TSTBIP TSTQID
TSTBIP Test BIP-8 Supervision
0Normal Operation:
BIP-8 for cell protection is generated normally. No
’BIP8ER’ interrupt should occur indicating a cell storage
failure.
1Test Mode:
Least Significant Bit (LSB) of BIP-8 is inverted to test
BIP-8 checking function. An ’BIP8ER’ (Register 110:
ISRU, Register 111: ISRD) interrupt is generated
whenever a cell is Read out of the Cell Buffer RAM.
TSTQID Test Queue ID Supervision
(see “Cell Queue Supervision” on Page 76)
Prel. ABMP Data Sheet
Regi ster Desc ript ion
Preliminary Data Sheet 153 2001-14-01
PRELIMINARY
0Normal Operation:
A correct QID is generated. No ’BUFER5’ interrupt
should occur indicating an internal queue pointer failure.
1Test Mode:
The LSB of the QID is inverted to test the QID checking
function. A ’BUFER5’ (Register 110: ISRU, Register
111: ISRD) interrupt is generated whenever a cell is
Read out out the Cell Buffer RAM.
Note: The respective QID value is stored with each cell
when written to the appropriate queue in the cell
storage RAM. The ABMP checks the stored QID
value against the supposed QID when a cell is
read back from the cell storage RAM.
Prel. ABMP Data Sheet
Regi ster Desc ript ion
Preliminary Data Sheet 154 2001-14-01
PRELIMINARY
Register 2 URCFG/DRC FG
Upstream/Downstream SDRAM Configuration Registers
CPU Accessibility : Read/Write
Reset Value: 0033H
Offset Address: URCFG 02HDRCFG 12H
Typical Usage: (Reserved)
Bit151413121110 9 8
Reserved(15:8)
Bit76543210
Reserved(7:0)
Note: These registers are for internal use only. Do not to Write a value different from
the Reset Value 0033
H
to Registers URCFG/DRCFG.
Prel. ABMP Data Sheet
Regi ster Desc ript ion
Preliminary Data Sheet 155 2001-14-01
PRELIMINARY
Register 3 UA5TX HD0/DA5TXHD0
Upstream/Downstream AAL5 Transmit Header 0 Registers
CPU Accessibility : Read/Write
Reset Value: 0000H
Offset Address: UA5TXHD0 05HDA5TXHD0 15H
Typical Usage: Written by CPU
Bit151413121110 9 8
LCI(11:4),
VPI(11:4) or GFC(3:0) | VPI(7:4),
LCI(11:4),
VPI(11:4) or GFC(3:0) | VPI(7:4),
Bit76543210
LCI(3:0),
VPI(3:0),
LCI(3:0),
VPI(3:0)
VCI(15:12),
LCI(15:12),
VCI(15:12),
VCI(15:12)
First 16 bit word of an ATM cell.
The ABM does not interpret these bit fields, but copy them into ATM cells that are
inserted during AAL5 packet segmentation process. Inserted cells are forward ed to the
ABM like a ny cell received by the r espective UTOPIA interface. Thus the bit field usage
must comply to the selected LCI mapping mode in the particular application.
VPI(11:0)
or
GFC(3:0) |
VPI(7:0)
or
LCI(11:0)
The meaning of this bit fi el d depen ds on the selected LCI mapping
mode in Register Mode (refer ???):
MODE->LCIMOD(1:0):
’00’
’01’
’10’
’11’
VPI Address translated mode: LCI(11:0)
VPI transparent mode:
• NNI cell format: 12 bit VPI field
• UNI cell format: 4 bit GFC field and 8 bit VPI field
VPI Address translated mode: LCI(11:0)
VPI transparent mode:
• NNI cell format: 12 bit VPI field
• UNI cell format: 4 bit GFC field and 8 bit VPI field
Prel. ABMP Data Sheet
Regi ster Desc ript ion
Preliminary Data Sheet 156 2001-14-01
PRELIMINARY
Register 4 UA5TX HD1/DA5TXHD1
Upstream/Downstream AAL5Transmit Header 1 Registers
VCI(15:12)
or
LCI(15:12)
or
VCI(15:12)
The meaning of this bit fi el d depen ds on the selected LCI mapping
mode in Register Mode (refer ???):
MODE->LCIMOD(1:0):
’00’
’01’
’10’
’11’
VCI transparent mode: VCI(15:12)
VCI Address translated mode: LCI(15:12)
VCI transparent mode: VCI(15:12)
VCI transparent mode: VCI(15:12)
CPU Accessibility : Read/Write
Reset Value: 0000H
Offset Address: UA5TXHD1 06HDA5TXHD1 16H
Typical Usage: Written by CPU
Bit151413121110 9 8
VCI(11:4),
LCI(11:4),
VCI(11:4),
VCI(11:4)
Bit76543210
VCI(3:0),
LCI(3:0),
VCI(3:0),
VCI(3:0)
PT(2:0) CLP
Prel. ABMP Data Sheet
Regi ster Desc ript ion
Preliminary Data Sheet 157 2001-14-01
PRELIMINARY
Second 16 bit word of an ATM cell.
The ABM does not interpret these bit fields, but copy them into ATM cells that are
inserted during AAL5 packet segmentation process. Inserted cells are forward ed to the
ABM like a ny cell received by the r espective UTOPIA interface. Thus the bit field usage
must comply to the selected LCI mapping mode in the particular application.
VCI(11:0)
or
LCI(11:0)
The meaning of this bit fi el d depen ds on the selected LCI mapping
mode in Register Mode (refer ???):
MODE->LCIMOD(1:0):
’00’
’01’
’10’
’11’
VCI transparent mode: VCI(11:0)
VCI Address translated mode: LCI(11:0)
VCI transparent mode: VCI(11:0)
VCI transparent mode: VCI(11:0)
PT(2:0) Payload Type Field in ATM cell Header
PT(0) is automatically handled by the ABM (End of Packet
indication set to ’1’ in last cell of any AAL5 segmented packet).
PT(1) (’Congestion Experienced’) may be overwritten by CPU
anytime during segmentation process and will be inserted in the
following AAL5 cell generated.
CLP Cell Loss Priority Bit in ATM cell Header
The CLP bit is copied transparently and may be overwritten
(changed) by CPU anytime during segmentation process (new
value will be inserted in the following AAL5 cell generated).
Prel. ABMP Data Sheet
Regi ster Desc ript ion
Preliminary Data Sheet 158 2001-14-01
PRELIMINARY
Register 5 UA5TXDAT0/DA5TXDAT0
Upstream/Downstream AAL5Transmit Data 0 Registers
CPU Accessibility : Read/Write
Reset Value: 0000H
Offset Address: UA5TXDAT0 07HDA5TXDAT0 17H
Typical Usage: Written by CPU
Bit151413121110 9 8
Octet(4n)(7:0)
Bit76543210
Octet(4n+1)(7:0)
Cell Transmit Data Transfer Register
Octet(4n)(7:0) Payload data Octet (4n)
Octet(4n+1)(7:0) Payload data Octet (4n+1)
The 48 payload data octets of a cell to be inserted in either
upstream or downstream direction are written by 12 consecutive
write accesses to registers UTXDAT0/DTXDAT0 and UTXDAT1/
DTXDAT1 in alternat ing mann er:
cycle n=0: Octet 0 and 1: write to UTXDAT0/DTXDAT0
cycle n=0: Octet 2 and 3: write to UTXDAT1/DTXDAT1
cycle n=1: Octet 4 and 5: write to UTXDAT0/DTXDAT0
cycle n=1: Octet 6 and 7: write to UTXDAT1/DTXDAT1
...
cycle n=11: Octet 44 and 45: write to UTXDAT0/DTXDAT0
cycle n=11: Octet 46 and 47: write to UTXDAT1/DTXDAT1
Prel. ABMP Data Sheet
Regi ster Desc ript ion
Preliminary Data Sheet 159 2001-14-01
PRELIMINARY
Register 6 UA5TXDAT1/DA5TXDAT1
Upstream/Downstream AAL5 Transmit Data 1 Registers
CPU Accessibility : Read/Write
Reset Value: 0000H
Offset Address: UA5TXDAT1 08HDA5TXDAT1 18H
Typical Usage: Written by CPU
Bit151413121110 9 8
Octet(4n+2)(7:0)
Bit76543210
Octet(4n+3)(7:0)
Cell Transmit Data Transfer Register
Octet(4n+2)(7:0) Payload data Octet (4n+2)
Octet(4n+3)(7:0) Payload data Octet (4n+3)
The 48 payload data octets of a cell to be inserted in either
upstream or downstream direction are written by 12 consecutive
write accesses to registers UTXDAT0/DTXDAT0 and UTXDAT1/
DTXDAT1 in alternat ing mann er:
cycle n=0: Octet 0 and 1: write to UTXDAT0/DTXDAT0
cycle n=0: Octet 2 and 3: write to UTXDAT1/DTXDAT1
cycle n=1: Octet 4 and 5: write to UTXDAT0/DTXDAT0
cycle n=1: Octet 6 and 7: write to UTXDAT1/DTXDAT1
...
cycle n=11: Octet 44 and 45: write to UTXDAT0/DTXDAT0
cycle n=11: Octet 46 and 47: write to UTXDAT1/DTXDAT1
Prel. ABMP Data Sheet
Regi ster Desc ript ion
Preliminary Data Sheet 160 2001-14-01
PRELIMINARY
Register 7 UA5TXTR/DA5TXTR
Upstream/Downstream AAL5 Transmit Trailer Registers
CPU Accessibility : Read/Write
Reset Value: 0000H
Offset Address: UA5TXTR 09HDA5TXTR 19H
Typical Usage: Written by CPU
Bit151413121110 9 8
CPCSUU(7:0)
Bit76543210
CPI(7:0)
CPCS-UU(7:0) Common Part Convergence Sublayer User to User Indication
The CPCS-UU bit field i s copied transpa rently i nto the CPCS-PD U
trailer in the last cell of a AAL5 segmented packet.
CPI(7:0) Common Part Indicatior
The CPI bit field is copied transparently into the CPCS-PDU trailer
in the last cell of a AAL5 segmented packet.
Prel. ABMP Data Sheet
Regi ster Desc ript ion
Preliminary Data Sheet 161 2001-14-01
PRELIMINARY
Registe r 8 UA5TXCMD/DA5TXCMD
Upstream/Downstream AAL5 Transmit Command Registers
CPU Accessibility : Read/Write
Reset Value: 0000H
Offset Address: UA5TXCMD 0AHDA5TXCMD 1AH
Typical Usage: Written by CPU
Bit151413121110 9 8
AAL5EN PLENGTH(14:8)
Bit76543210
PLENGTH(7:0)
AAL5EN AAL5 Segmentation Enable
This bit enables AAL5 segmentation process accompanied by the
payload length octet counter PLENGTH:
’0’ AAL5 segmentation is disabled. Payload data octets
written to the cell transmit data registers are ignored.
Note: Setting AAL5EN=’0’ during an active packet
segmentation process leads to an abort of the
packet, i.e. the current cell is inserted with
PT(0)=’1’ (Endof Packet indication) and CPCS-
SDU Length field of the trailer set to zero.
To abort it is recommen ded to write all ze ro to the
register: AAL5EN | PLENGTH(14:0) = 0000
H
’1’ AAL5 segmentation is enabled. Payload data octets
written to the cel l transmi t data reg isters are processed
and the CPCS-PDU trailer is automatically appended in
the last cell controlled by the payload length octet
counter.
PLENGTH(14:0) Payload Length Octet Counter
Prel. ABMP Data Sheet
Regi ster Desc ript ion
Preliminary Data Sheet 162 2001-14-01
PRELIMINARY
Register 9 UA5RXHD0/DA5RXHD0
Upstream/Downstream AAL5 Receive Header 0 Registers
This bit-field represents the numbe r of PDU payload octets for the
current packet and is equal to the CPC S-SD U length field which is
automatically inserted in the PDU trailer (last cell of the packet).
The ABM uses this counter value to control the AAL5 segmentat ion
process.
Note: The maxim um suppor ted CPCS -SDU le ngth is 3 2767 octets.
CPU Accessibility : Read/Write
Reset Value: 0000H
Offset Address: UA5RXHD0 0BHDA5RXHD0 1BH
Typical Usage: Read by CPU
Bit151413121110 9 8
LCI(11:4),
VPI(11:4) or GFC(3:0) | VPI(7:4),
LCI(11:4),
VPI(11:4) or GFC(3:0) | VPI(7:4),
Bit76543210
LCI(3:0),
VPI(3:0),
LCI(3:0),
VPI(3:0)
VCI(15:12),
LCI(15:12),
VCI(15:12),
VCI(15:12)
Prel. ABMP Data Sheet
Regi ster Desc ript ion
Preliminary Data Sheet 163 2001-14-01
PRELIMINARY
First 16 bit word of an ATM cell.
The ABMP SAR unit does not interpret these bit fields, but copy them from ATM cells
that are extracted during AAL5 packet reassembly process. Extracted cells are
forwarded from the ABMP like any cell to be transmitted by the respective UTOPIA
interface. Thus the bit field usage depends on the selected LCI mapping mode in the
particular application. From scheduler point of view the reassembly unit is addressed as
UTOPIA port number 31D.
VPI(11:0)
or
GFC(3:0) |
VPI(7:0)
or
LCI(11:0)
The meaning of this bit fi el d depen ds on the selected LCI mapping
mode in Register Mode1:
MODE1->LCIMOD(1:0):
’00’
’01’
’10’
’11’
VPI Address translated mode: LCI(11:0)
VPI transparent mode:
• NNI cell format: 12 bit VPI field
• UNI cell format: 4 bit GFC field and 8 bit VPI field
VPI Address translated mode: LCI(11:0)
VPI transparent mode:
• NNI cell format: 12 bit VPI field
• UNI cell format: 4 bit GFC field and 8 bit VPI field
VCI(15:12)
or
LCI(15:12)
or
VCI(15:12)
The meaning of this bit fi el d depen ds on the selected LCI mapping
mode in Register Mode1:
MODE1->LCIMOD(1:0):
’00’
’01’
’10’
’11’
VCI transparent mode: VCI(15:12)
VCI Address translated mode: LCI(15:12)
VCI transparent mode: VCI(15:12)
VCI transparent mode: VCI(15:12)
Prel. ABMP Data Sheet
Regi ster Desc ript ion
Preliminary Data Sheet 164 2001-14-01
PRELIMINARY
Register 10 UA5RXHD1/DA5RXHD1
Upstream/Downstream AAL5 Receive Header 1 Registers
CPU Accessibility : Read/Write
Reset Value: 0000H
Offset Address: UA5RXHD1 0CHDA5RXHD1 1CH
Typical Usage: Read by CPU
Bit151413121110 9 8
VCI(11:4),
LCI(11:4),
VCI(11:4),
VCI(11:4)
Bit76543210
VCI(3:0),
LCI(3:0),
VCI(3:0),
VCI(3:0)
PT(2:0) CLP
First 16 bit word of an ATM cell.
The ABMP SAR unit does not interpret these bit fields, but copy them from ATM cells
that are extracted during AAL5 packet reassembly process. Extracted cells are
forwarded from the ABMP like any cell to be transmitted by the respective UTOPIA
interface. Thus the bit field usage depends on the selected LCI mapping mode in the
particular application. From scheduler point of view the reassembly unit is addressed as
UTOPIA port number 31D.
VCI(11:0)
or
LCI(11:0)
The meaning of this bit fi el d depen ds on the selected LCI mapping
mode in Register Mode1:
MODE1->LCIMOD(1:0):
’00’
’01’
’10’
’11’
VCI transparent mode: VCI(11:0)
VCI Address translated mode: LCI(11:0)
VCI transparent mode: VCI(11:0)
VCI transparent mode: VCI(11:0)
PT(2:0) Payload Type Field in ATM cell Header
Prel. ABMP Data Sheet
Regi ster Desc ript ion
Preliminary Data Sheet 165 2001-14-01
PRELIMINARY
Register 11 UA5RXDAT0/DA5RXDAT0
Upstream/Downstream AAL5 Receive Data 0 Registers
PT(0) is automatically handled by the ABM (End of Packet
detection).
Note: OAM or RM cells detected with PT(2)=’1’ are discarded by
the reassembly unit and ignored for the packet reassembly
process. Thus packet reassembly is not disturbed by inserted
OAM cells .
CLP Cell Loss Priority Bit in ATM cell Header
The CLP bit is copied transparently from the ATM cell.
CPU Accessibility : Read/Write
Reset Value: 0000H
Offset Address: UA5RXDAT0 0DHDA5RXDAT0 1DH
Typical Usage: Read by CPU
Bit151413121110 9 8
Octet(4n)(7:0)
Bit76543210
Octet(4n+1)(7:0)
Cell Receive Data Transfer Register
Octet(4n)(7:0) Payload data Octet (4n)
Octet(4n+1)(7:0) Payload data Octet (4n+1)
Prel. ABMP Data Sheet
Regi ster Desc ript ion
Preliminary Data Sheet 166 2001-14-01
PRELIMINARY
Register 12 UA5RXDAT1/DA5RXDAT1
Upstream/Downstream AAL5 Receive Data 1 Registers
The 48 payloa d data octets of a cell extracted from ei ther upstream
or downstream direction are read by 12 consecutive read accesses
to registers URXDAT0/DRXDAT0 and URXDAT1/DRXDAT1 in
alternating manner:
cycle n=0: Octet 0 and 1: read from URXDAT0/DRXDAT0
cycle n=0: Octet 2 and 3: read from URXDAT1/DRXDAT1
cycle n=1: Octet 4 and 5: read from URXDAT0/DRXDAT0
cycle n=1: Octet 6 and 7: read from URXDAT1/DRXDAT1
...
cycle n=11: Octet 44 and 45: read from URXDAT0/DRXDAT0
cycle n=11: Octet 46 and 47: read from URXDAT1/DRXDAT1
CPU Accessibility : Read/Write
Reset Value: 0000H
Offset Address: UA5RXDAT1 0EHDA5RXDAT1 1EH
Typical Usage: Read by CPU
Bit151413121110 9 8
Octet(4n+2)(7:0)
Bit76543210
Octet(4n+3)(7:0)
Prel. ABMP Data Sheet
Regi ster Desc ript ion
Preliminary Data Sheet 167 2001-14-01
PRELIMINARY
Register 13 UA5SARS/DA5SARS
Upstream/Downstream AAL5 SAR Status Registers
Cell Receive Data Transfer Register
Octet(4n)(7:0) Payload data Octet (4n)
Octet(4n+1)(7:0) Payload data Octet (4n+1)
The 48 payloa d data octets of a cell extracted from ei ther upstream
or downstream direction are read by 12 consecutive read accesses
to registers URXDAT0/DRXDAT0 and URXDAT1/DRXDAT1 in
alternating manner:
cycle n=0: Octet 0 and 1: read from URXDAT0/DRXDAT0
cycle n=0: Octet 2 and 3: read from URXDAT1/DRXDAT1
cycle n=1: Octet 4 and 5: read from URXDAT0/DRXDAT0
cycle n=1: Octet 6 and 7: read from URXDAT1/DRXDAT1
...
cycle n=11: Octet 44 and 45: read from URXDAT0/DRXDAT0
cycle n=11: Octet 46 and 47: read from URXDAT1/DRXDAT1
CPU Accessibility : Read/Write
Reset Value: 0000H
Offset Address: UA5SARS 0FHDA5SARS 1FH
Typical Usage: Read and written by CPU
Bit151413121110 9 8
PE CRC
ERR ILEN MFLE RAB OV(1:0) RXS
Bit76543210
WAIT SP SAB SE unused(3:0)
PE Packet End
A ‘1’ indicates that with the preceeding read to register
UA5RXDAT0/DA5RXDAT0 or UA5RXDAT1/DA5RXDAT1 the last
two bytes of the current packet have been read.
Prel. ABMP Data Sheet
Regi ster Desc ript ion
Preliminary Data Sheet 168 2001-14-01
PRELIMINARY
CRCE RR CRC Error
A ‘1’ indicates that the CRC32 of the current packet is erroneous.
ILEN Illegal Length
A ‘1’ indi cates that the len gth of the curr ent packet is e rroneous, i. e
the number of octets does not match the length field in the AAL5
trailer or exceeds the maximum supported packet length of 32768
octets.
MFLE Maximum Frame Length Exceeded
A ‘1’ indicates that the length of the current packet exceeds the
maximum supported packet length of 32768 octets.
RAB Receive Abort
A ‘1’ indicates that the length field of the current packet is zero
indicating an aborted or corrupted packet.
OV(1:0) Octets Valid
This bit field indicates the number of valid octets in registers
UA5RXDAT0 and UA5RXDAT1 or DA5RXDAT0 and
DA5RXDAT1 respectiv ely.
RXS Receive Packet Start
A ‘1’ indicates that the first octets of a new packet are available in
registers UA5RXDAT0 and UA5RXDAT1 or DA5RXDAT0 and
DA5RXDAT1 respectiv ely.
WAIT Wait
A ‘1’ indicates that no valid octets are available in registers
UA5RXDAT0 and UA5RXDAT1 or DA5RXDAT0 and
DA5RXDAT1 respectively. Read access to any read regi ster while
WAIT is asserted results into an error interrupt.
Prel. ABMP Data Sheet
Regi ster Desc ript ion
Preliminary Data Sheet 169 2001-14-01
PRELIMINARY
SP Segmentation Pending
A ‘1’ indicates that a cell is ready to be transmitted towards the
ABMP core. A cell is re ady either when 48 octets have been writ ten
to UA5TXDAT0 and UA5TXDAT1 or DA5TXDAT0 and
DA5TXDAT1 respectively or when the last cell is being built.
Bit ‘SP’ is set when the 48-byte transmit buffer is full and it is reset
as soon as at least 4 octet space is available for new octets. The
microprocessor has to poll this bit before writing the next 48-octet
bunch or beginning a new packet. If the microprocessor attempts to
write to UA5TXDAT0 and UA5TXDAT1 or DA5TXDAT0 and
DA5TXDAT1 respectively while ‘SP’ is set, an interrupt is generated
and the write access is delayed by the READY signal.
SAB Segmentation Abort
A ‘1’ indicates that the transmission of a packet has been aborted
because the enable bit EN was r eset by the micropro cessor before
the transmission was completed. The AAL5 unit automatically
closed the packet with an abort sequence in the last cell (length field
set to zero).
Note: Status bit ‘SE’ is not set in this case.
SE Segmentation Ended
A ‘1’ indicates that the transmission of a packet has been completed
successfully.
Prel. ABMP Data Sheet
Regi ster Desc ript ion
Preliminary Data Sheet 170 2001-14-01
PRELIMINARY
Register 14 UBOC/DBOC
Upstream/Downstream Buffer Occupation Registers
CPU Accessibility : Read only
Reset Value: 0000H
Offset Address: UBOC 20HDBOC 21H
Typical Usage: Read by CPU
Bit151413121110 9 8
UBOC/DBOC(17:10)
Bit76543210
UBOC/DBOC(9:2)
UBOC(17:2) Upstream Buffer Occupation Counter
DBOC(17:2) Downstream Buffer Occupation Counter
These bit fields represent the most significant 16-bits of the internal
18 bit wide counters reflecting the number of cells currently stored
in the upstream/downstream cell storage RAM.
The CPU determines the buffer fill level with a granularity of 4 by
reading register UBOC/DBOC and left shifting the value by 2:
fill_level(17:0) := (xBOC(17:2) << 2)
Prel. ABMP Data Sheet
Regi ster Desc ript ion
Preliminary Data Sheet 171 2001-14-01
PRELIMINARY
Register 15 UNGBOC/DNGBOC
Up-/Downstream Non-Guaranteed Buffer Occupation Registers
•
CPU Accessibility : Read only
Reset Value: 0000H
Offset Address: UNGBOC 22HDNGBOC 23H
Typical Usage: Read by CPU
Bit151413121110 9 8
UNGBOC/DNGBOC(17:10)
Bit76543210
UNGBOC/DNGBOC(9:2)
UNGBOC(17:2) Upstream Non-Guaranteed Buffer Occupation Counter
DNGBOC(17:2) Downstream Non-Guaranteed Buffer Occupation Counter
These bit fields represent the most significant 16-bits of the internal
18 bit wide counters reflecting the number of non-guaranteed cells
currently stored in the upstream/downstream cell storage RAM.
The CPU determines the number of cells with a granularity of 4 by
reading register UNGBOC/DNGBOC and left shifting the value by 2:
fill_level(17:0) := (xNGBOC(17:2) << 2)
"Non-Guaranteed" cell count refers to cells, that are accepted
(stored) because of shared buffer availability although the
guarant eed mini mu m per queue buffer size is already occupied by
the specific queue.
The sum of all per queue guaranteed buffer sizes virtually devides
the global buffer space into a "guaranteed" part and a "non-
guaranteed" (shared) part.
Note: This counter function has been modified from ABM version
1.x since minimum per queue buffer reservation was
introduced in version 2.x.
In ABM version 1.1 these counters represented the number
stored "non-real-time" cells belonging to traffic classes with
the real-time indication bit ’RTind’ cleared in the version 1.x
traffic class table.
Prel. ABMP Data Sheet
Regi ster Desc ript ion
Preliminary Data Sheet 172 2001-14-01
PRELIMINARY
Register 16 UBMTH/DBMTH
Upstream/Downstream Buffer Maximum Threshold Registers
The following table provides typical values and related RAM sizes:
CPU Accessibility : Read/Write
Reset Value: 0000H
Offset Address: UBMTH 24HDBMTH 25H
Typical Usage: Written by CPU
Bit151413121110 9 8
UBMTH/DBMTH(17:10)
Bit76543210
UBMTH/DBMTH(9:2)
UBMTH(17:2) Upstream Buffer Maximum Threshold
DBMTH(17:2) Downstream Buffer Maximum Threshold
These bit fields determine a maximum limit for the total upstream
and downstre am buffer size with a gra nularity of 4 cel ls. The val ues
depend on:
• The size of the external cell pointer RAM,
• Whether the downstream cell storage RAM is connected.
See Table 7-3 for recommended values.
The CPU programs the maximum number of cells with a granularity
of 4 by right shifting the value by 2:
xBMTH(17:2) := (maximum_cells(17:0) >> 2)
Prel. ABMP Data Sheet
Regi ster Desc ript ion
Preliminary Data Sheet 173 2001-14-01
PRELIMINARY
:
Note: The upstream cell storage RAM must always be connected.
Table 7-3 External RAM Sizes
Cell Pointer
SSRAM Min.
Required
Up-
stream Cell
SDRAM
Min.
Required
Down-
stream Cell
SDRAM
UBMTH Up-
stream
Buffer:
DBMTH Down-
stream
Buffer:
e.g.
512 k x 32 bit 128 Mb
e.g.
2*(4Mb*16)
128 Mb
e.g.
2*(4Mb*16)
3FFFFH256k cells 3FFFFH256k cells
e.g.
256 k x 32 bit 64 Mb
e.g.
1*(2Mb*32)
64 Mb
e.g.
1*(2Mb*32)
1FFFFH128k cells 1FFFFH128k cells
e.g.
128 k x 32 bit 32 Mb 32 Mb 0FFFFH64k cells 0FFFFH64k cells
e.g.
256 k x 32 bit 128 Mb
e.g.
2*(4Mb*16)
none 3FFFFH256k cells 00000H0
e.g.
128 k x 32 bit 64 Mb
e.g.
1*(2Mb*32)
none 1FFFFH128k cells 00000H0
e.g.
64 k x 32 bit 32 Mb none 0FFFFH64k cells 00000H0
Prel. ABMP Data Sheet
Regi ster Desc ript ion
Preliminary Data Sheet 174 2001-14-01
PRELIMINARY
Register 17 UMAC/DMAC
Upstream/Downstream Maximum Occupation Capture Registers
CPU Accessibility : Read only, self-clearing on Read
Reset Value: 0000H
Offset Address: UMAC 26HDMAC 27H
Typical Usage: Read by CPU
Bit151413121110 9 8
UMAC/DMAC(17:10)
Bit76543210
UMAC/DMAC(9:2)
UMAC(17:2) Upstream Maximum Occupation Capture Counter
DMAC(17:2) Downstream Maximum Occupation Capture Counter
These bit fields repr esent the m ost significa nt 16-bits o f the i nternal
18 bit wide counters reflecting the absolute maximum number of
cells stored in the respe ctive external cell buffer since the last Read
access (peak cell filling level within measurement interval).
The CPU determines the maximum number of cells with a
granularity of 4 by reading register UMAC/DMAC and left shifting
the value by 2:
max_level(17:0) := (xMAC(17:2) << 2)
The counter value is automatically cleared to 0000H after Read.
Prel. ABMP Data Sheet
Regi ster Desc ript ion
Preliminary Data Sheet 175 2001-14-01
PRELIMINARY
Register 18 UMIC/DMIC
Upstream/Downstream Minimum Occupation Capture Registers
CPU Accessibility : Read only, self-clearing on Read
Reset Value: FFFFH
(may be modified by chip logic immediately after reset)
Offset Address: UMIC 28HDMIC 29H
Typical Usage: Read by CPU
Bit151413121110 9 8
UMIC/DMIC(17:10)
Bit76543210
UMIC/DMIC(9:2)
UMIC(17:2) Upstream Minimum Occupation Capture Counter
DMIC(17:2) Downstream Minimum Occupation Capture Counter
These bit fields repr esent the m ost significa nt 16-bits o f the i nternal
18 bit wide counters reflecting the absolute minimum number of
cells stored in the respe ctive external cell buffer since the last Read
access (minimum cell filling level within measurement interval).
The CPU determines the minimum number of cells with a
granulari ty of 4 by readi ng register UMIC/DMIC and left shifting th e
value by 2:
min_level(17:0) := (xMIC(17:2) << 2)
The counter value is automatically cleared to FFFFH after Read.
Note: The reset value may be modified by chip logic immediately
after reset or clearing read and thus shall not be included in
register reset value test programs.
Prel. ABMP Data Sheet
Regi ster Desc ript ion
Preliminary Data Sheet 176 2001-14-01
PRELIMINARY
Register 19 CLP1DIS
CLP1 Discard Global Threshold Registers
CPU Accessibility : Read/Write
Reset Value: 0000H
Offset Address: CLP1DIS 2AH
Typical Usage: Written by CPU
Bit151413121110 9 8
DCLP1DIS(13:6)
Bit76543210
UCLP1DIS(13:6)
UCLP1DIS(13:6) Upstream CLP1 Discard Threshold value
DCLP1DIS(13:6) Downstream CLP1 Discard Threshold value
These 8-bit values determine a global 14 bit threshold value
(granularity of 64 cells) that enables discard of low-priority (CLP=’1’)
cells.
The threshold values are compared with the per scheduler low
priority cell counter SBOCCLP (Scheduler Block Low Priority
Occupancy) (see Internal Table 5:: Scheduler Occupancy Table
Transfer Registers SOT0..SOT4) and enables all CLP1 related
discard thresholds, i.e.
TCT1.BufCiCLP1(7:0) ( Register 40: TCT1)
TCT2.SbCiCLP1(7:0) (Regis ter 41: TCT2)
TCT0.QueueCiCLP1(11:0) (Register 39: TCT0)
As a second condition, CLP1 related discard thresholds are only
effective, if the specific queue that is asked to accept the cell is
associated to a traffic class that has EPD function disabled
(EPDen=’0’, see “Traffic Class Table Transfer Registers TCT0,
TCT1, TCT2, TCT3” on Page 203).
The CPU programs the threshold with a granularity of 64 cells by
right shifting the value by 6:
xCLP1DIS(13:6) := (threshold_value(13:0) >> 6)
Prel. ABMP Data Sheet
Regi ster Desc ript ion
Preliminary Data Sheet 177 2001-14-01
PRELIMINARY
Register 20 CONFIG
Configu r ation Register
CPU Accessibility : Read/Write
Reset Value: 0000H
Offset Address: 2BH
Typical Usage: Written by CPU
Bit151413121110 9 8
Unused(13:6)
Bit765432 1 0
Unused(5:0) Reserved1 ABRTQ
Reserved1 this bit is for internal use only and must be set at 0 during normal
operation.
ABRTQ ABR Toggle Queue ID:
This global bit controls treatment of RM cells for uni-directional
(mini swi tch) mode.
0 Normal Operation (set for bi-directional mode).
1 Only RM cells with toggled LCI and QID are modified.
Note: The following conditions must apply for proper CI/NI operation:
In Bi-directio nal Mode, the same LCI and the same que ue identifier QID must be
used for the ABR connection in forward and backwar d directions; for example, in
forward direction LCI=2 and QID=7, in backward direction LCI=2 and QID=7.
In Uni-directional Mode, LCI and QID must have the LSB inverted; for example,
in forward direction LCI=3 and QID=7, in backward direction LCI=2 and QID=6.
The LCI inversion (toggle) is activated by setting the LCI toggle bit in the MODE1
register to 1.
Prel. ABMP Data Sheet
Regi ster Desc ript ion
Preliminary Data Sheet 178 2001-14-01
PRELIMINARY
Register 21 UUBPTH0
Upstream UTOPIA Backpressure Threshold Register 0
CPU Accessibility : Read/Write
Reset Value: FFFFH
Offset Address: UUBPTH0 2CH
Typical Usage: Written by CPU
Bit151413121110 9 8
UUBPTH0(17:10)
Bit765432 1 0
UUBPTH0(9:2)
UUBPTH0(17:2) Upstream UTOPIA Backpressure Threshold 0
This bit field determines the backpressure threshold for the
Upstream UTOPIA Receive interface group 0 with a granularity of 4
cells.
The CPU programs the threshold with a granularity of 4 by right
shifting the value by 2:
UUBPTH0(17:2) := (maximum_cells(17:0) >> 2)
Prel. ABMP Data Sheet
Regi ster Desc ript ion
Preliminary Data Sheet 179 2001-14-01
PRELIMINARY
Register 22 UUBPTH1
Upstream UTOPIA Backpressure Threshold Register 1
CPU Accessibility : Read/Write
Reset Value: FFFFH
Offset Address: UUBPTH1 2DH
Typical Usage: Written by CPU
Bit151413121110 9 8
UUBPTH1(17:10)
Bit765432 1 0
UUBPTH1(9:2)
UUBPTH1(17:2) Upstream UTOPIA Backpressure Threshold 1
This bit field determines the backpressure threshold for the
Upstream UTOPIA Receive interface group 1 with a granularity of 4
cells.
The CPU programs the threshold with a granularity of 4 by right
shifting the value by 2:
UUBPTH1(17:2) := (maximum_cells(17:0) >> 2)
Prel. ABMP Data Sheet
Regi ster Desc ript ion
Preliminary Data Sheet 180 2001-14-01
PRELIMINARY
Register 23 UUBPTH2
Upstream UTOPIA Backpressure Threshold Register 2
CPU Accessibility : Read/Write
Reset Value: FFFFH
Offset Address: UUBPTH2 2EH
Typical Usage: Written by CPU
Bit151413121110 9 8
UUBPTH2(17:10)
Bit765432 1 0
UUBPTH2(9:2)
UUBPTH2(17:2) Upstream UTOPIA Backpressure Threshold 2
This bit field determines the backpressure threshold for the
Upstream UTOPIA Receive interface group 2 with a granularity of 4
cells.
The CPU programs the threshold with a granularity of 4 by right
shifting the value by 2:
UUBPTH2(17:2) := (maximum_cells(17:0) >> 2)
Prel. ABMP Data Sheet
Regi ster Desc ript ion
Preliminary Data Sheet 181 2001-14-01
PRELIMINARY
Register 24 UUBPTH3
Upstream UTOPIA Backpressure Threshold Register 3
CPU Accessibility : Read/Write
Reset Value: FFFFH
Offset Address: UUBPTH3 2EH
Typical Usage: Written by CPU
Bit151413121110 9 8
UUBPTH3(17:10)
Bit765432 1 0
UUBPTH3(9:2)
UUBPTH#(17:2) Upstream UTOPIA Backpressure Threshold #
This bit field determines the backpressure threshold for the
Upstream UTOPIA Receive interface group 3 with a granularity of 4
cells.
The CPU programs the threshold with a granularity of 4 by right
shifting the value by 2:
UUBPTH3(17:2) := (maximum_cells(17:0) >> 2)
Prel. ABMP Data Sheet
Regi ster Desc ript ion
Preliminary Data Sheet 182 2001-14-01
PRELIMINARY
Register 25 UBPEI
UTOPIA Backpressure Exceed Indication Register
CPU Accessibility : Read/Write
Reset Value: 0000H
Offset Address: UBPEI 30H
Typical Usage: Read by CPU
Bit151413121110 9 8
Unused(7:0)
Bit765432 1 0
DUBPEI(3:0) UUBPEI(3:0)
DUBPEI(3:0) Downstream UTOPIA Backpressure Exceed Indication (3:0)
UUBPEI(3:0) Upstream UTOPIA Backpressure Exceed Indication (3:0)
These bits indicate the r espective UTOPIA ba ckpressur e thr eshold
status.
Bit i (i = 0..3) active indicates, that the backpressure threshold for
group i is exceeded (bit = ‘H’) and the UTOPIA receive interface
backpressures the respective UTOPIA ports.
Prel. ABMP Data Sheet
Regi ster Desc ript ion
Preliminary Data Sheet 183 2001-14-01
PRELIMINARY
Register 26 DUBPTH0
Downstream UTOPIA Backpressure Threshold Register 0
CPU Accessibility : Read/Write
Reset Value: FFFFH
Offset Address: DUBPTH0 31H
Typical Usage: Written by CPU
Bit151413121110 9 8
DUBPTH0(17:10)
Bit765432 1 0
DUBPTH0(9:2)
DUBPTH0(17:2) Downstream UTOPIA Backpressure Threshold 0
This bit field determines the backpressure threshold for the
Downstream UTOPIA Receive interface group 0 with a granularity
of 4 cells.
The CPU programs the threshold with a granularity of 4 by right
shifting the value by 2:
DUBPTH0(17:2) := (maximum_cells(17:0) >> 2)
Prel. ABMP Data Sheet
Regi ster Desc ript ion
Preliminary Data Sheet 184 2001-14-01
PRELIMINARY
Register 27 DUBPTH1
Downstream UTOPIA Backpressure Threshold Register 1
CPU Accessibility : Read/Write
Reset Value: FFFFH
Offset Address: DUBPTH1 32H
Typical Usage: Written by CPU
Bit151413121110 9 8
DUBPTH1(17:10)
Bit765432 1 0
DUBPTH1(9:2)
DUBPTH1(17:2) Downstream UTOPIA Backpressure Threshold 1
This bit field determines the backpressure threshold for the
Downstream UTOPIA Receive interface group 1 with a granularity
of 4 cells.
The CPU programs the threshold with a granularity of 4 by right
shifting the value by 2:
DUBPTH1(17:2) := (maximum_cells(17:0) >> 2)
Prel. ABMP Data Sheet
Regi ster Desc ript ion
Preliminary Data Sheet 185 2001-14-01
PRELIMINARY
Register 28 DUBPTH2
Downstream UTOPIA Backpressure Threshold Register 2
CPU Accessibility : Read/Write
Reset Value: FFFFH
Offset Address: DUBPTH2 33H
Typical Usage: Written by CPU
Bit151413121110 9 8
DUBPTH2(17:10)
Bit765432 1 0
DUBPTH2(9:2)
DUBPTH2(17:2) Downstream UTOPIA Backpressure Threshold 2
This bit field determines the backpressure threshold for the
Downstream UTOPIA Receive interface group 2 with a granularity
of 4 cells.
The CPU programs the threshold with a granularity of 4 by right
shifting the value by 2:
DUBPTH2(17:2) := (maximum_cells(17:0) >> 2)
Prel. ABMP Data Sheet
Regi ster Desc ript ion
Preliminary Data Sheet 186 2001-14-01
PRELIMINARY
Register 29 DUBPTH3
Downstream UTOPIA Backpressure Threshold Register 3
CPU Accessibility : Read/Write
Reset Value: FFFFH
Offset Address: DUBPTH3 34H
Typical Usage: Written by CPU
Bit151413121110 9 8
DUBPTH3(17:10)
Bit765432 1 0
DUBPTH3(9:2)
DUBPTH#(17:2) Downstream UTOPIA Backpressure Threshold #
This bit field determines the backpressure threshold for the
Downstream UTOPIA Receive interface group 3 with a granularity
of 4 cells.
The CPU programs the threshold with a granularity of 4 by right
shifting the value by 2:
DUBPTH3(17:2) := (maximum_cells(17:0) >> 2)
Prel. ABMP Data Sheet
Regi ster Desc ript ion
Preliminary Data Sheet 187 2001-14-01
PRELIMINARY
Register 30 DQCIC
Downstream Queue Congestion Indication Control Register
CPU Accessibility : Read/Write
Reset Value: 0080H
Offset Address: DQCIC 35H
Typical Usage: Written by CPU
Bit151413121110 9 8
Bit765432 1 0
FSEN BSEN BPLEN(1:0) QCIHYS(3:0)
FSEN Frame Sync Enable
This bit enables frame sync operation controlled by signal
‘QCITXFRAME’.
0 Frame Sync Operation disabled. Input signal
‘QCITXFRAME’ is ignored.
1 Frame Sync Operation enabled.
An active high edge at input signal ‘QCITXFRAME’
starts transmission of a new pattern..
BSEN Bit-Stuffing Enable
This bit enables HDLC bit-stuffing within the transmission pattern.
0 Bit-stuffing disabled.
1 Bit-stuffing enabled.
BPLEN(1:0) Bit-Pattern Length
This bit-field determines the bit pattern payload length depending
on the number of queues that need to be monitored.
00 1k bits (queues 0..1023 are monitored)
01 2k bits (queues 0..2047 are monitored)
10 4k bits (queues 0..4095 are monitored)
Prel. ABMP Data Sheet
Regi ster Desc ript ion
Preliminary Data Sheet 188 2001-14-01
PRELIMINARY
11 8k bits (queues 0..8191 are monitored)
QCIHYS(3:0) Queue Congestion Indication Hysteresis
This bit-field determines the hystere sis that is appl ied to the Queue
Congestion Indication threshold evaluation. The queue specific
threshold is programmed in table QCIT.
The hysteresis determines a lower threshold THhys with
THhysi := Thresholdi - Deltai
The Delta i value is determined by bit-field DH(2:0) and Thresholdi
with:
Deltai := Thresholdi >> [QCIHYS(3:0)]
The following table shows the operation and resulting example
THhysi values for the example of a threshold programmed to 1024
cells:
QCIHYS
(2:0): Deltai:= Example:
0d 0 (hysteresis disabled) THhysi := 1024
1d Thresholdi >>1 THhysi := 512
2d Thresholdi >>2 THhysi := 768
4d Thresholdi >>4 THhysi := 960
8d Thresholdi >>8 THhysi := 1020
10d Thresholdi >>10 hysteresis ineffective)
Prel. ABMP Data Sheet
Regi ster Desc ript ion
Preliminary Data Sheet 189 2001-14-01
PRELIMINARY
Register 31 DSBT1
Upstream/Downstream DBA Scheduler Block Threshold Register 1
CPU Accessibility : Read/Write
Reset Value: 0000H
Offset Address: DSBT1 36H
Typical Usage: Written and Read by CPU during initialization
Bit151413121110 9 8
DSBT1HP(11:4)
Bit76543210
DSBT1LP(11:4)
DSBT1HP(11:4) DBA Scheduler Block Threshold 1 High Priority
This bit field repr esents the most significant 8-bits of the inter nal 12
bit wide High Priority DBA Threshold 1. The threshold value is
global, but individually evaluated against all scheduler block
specific fill level counter (upstream and downstream) of the same
priority class (SBOCCHP).
The threshold range is (0..4095) with a granularity of 16 cells.
The CPU programs the threshold with a granularity of 4 cells by
right shifting the value by 4:
DSBT1HP(11:4) := ( threshold_value >> 4)
DSBT1LP(11:4) DBA Scheduler Block Threshold 1 Low Priority
Prel. ABMP Data Sheet
Regi ster Desc ript ion
Preliminary Data Sheet 190 2001-14-01
PRELIMINARY
This bit field repr esents the most significant 8-bits of the inter nal 12
bit wide Low Priority DBA Threshold 1. The threshold value is
global, but individually evaluated against all scheduler block
specific fill level counter (upstream and downstream) of the same
priority class (SBOCCLP).
The threshold range is (0..4095) with a granularity of 16 cells.
The CPU programs the threshold with a granularity of 4 cells by
right shifting the value by 4:
DSBT1LP(11:4) := ( threshold_value >> 4)
Prel. ABMP Data Sheet
Regi ster Desc ript ion
Preliminary Data Sheet 191 2001-14-01
PRELIMINARY
Register 32 DSBT2
Upstream/Downstream DBA Scheduler Block Threshold Register 2
CPU Accessibility : Read/Write
Reset Value: 0000H
Offset Address: DSBT2 37H
Typical Usage: Written and Read by CPU during initialization
Bit151413121110 9 8
DSBT2HP(11:4)
Bit76543210
DSBT2LP(11:4)
DSBT2HP(11:4) DBA Scheduler Block Threshold 2 High Priority
This bit field repr esents the most significant 8-bits of the inter nal 12
bit wide High Priority DBA Threshold 2. The threshold value is
global, but individually evaluated against all scheduler block
specific fill level counter (upstream and downstream) of the same
priority class (SBOCCHP).
The threshold range is (0..4095) with a granularity of 16 cells.
The CPU programs the threshold with a granularity of 4 cells by
right shifting the value by 4:
DSBT2HP(11:4) := ( threshold_value >> 4)
DSBT2LP(11:4) DBA Scheduler Block Threshold 2 Low Priority
Prel. ABMP Data Sheet
Regi ster Desc ript ion
Preliminary Data Sheet 192 2001-14-01
PRELIMINARY
Register 33 DSBT3
Upstream/Downstream DBA Scheduler Block Threshold Register 3
This bit field repr esents the most significant 8-bits of the inter nal 12
bit wide Low Priority DBA Threshold 2. The threshold value is
global, but individually evaluated against all scheduler block
specific fill level counter (upstream and downstream) of the same
priority class (SBOCCLP).
The threshold range is (0..4095) with a granularity of 16 cells.
The CPU programs the threshold with a granularity of 4 cells by
right shifting the value by 4:
DSBT2LP(11:4) := ( threshold_value >> 4)
CPU Accessibility : Read/Write
Reset Value: 0000H
Offset Address: DSBT3 38H
Typical Usage: Written and Read by CPU during initialization
Bit151413121110 9 8
DSBT3HP(11:4)
Bit76543210
DSBT3LP(11:4)
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Regi ster Desc ript ion
Preliminary Data Sheet 193 2001-14-01
PRELIMINARY
DSBT3HP(11:4) DBA Scheduler Block Threshold 3 High Priority
This bit field repr esents the most significant 8-bits of the inter nal 12
bit wide High Priority DBA Threshold 3. The threshold value is
global, but individually evaluated against all scheduler block
specific fill level counter (upstream and downstream) of the same
priority class (SBOCCHP).
The threshold range is (0..4095) with a granularity of 16 cells.
The CPU programs the threshold with a granularity of 4 cells by
right shifting the value by 4:
DSBT3HP(11:4) := ( threshold_value >> 4)
DSBT3LP(11:4) DBA Scheduler Block Threshold 3 Low Priority
This bit field repr esents the most significant 8-bits of the inter nal 12
bit wide Low Priority DBA Threshold 3. The threshold value is
global, but individually evaluated against all scheduler block
specific fill level counter (upstream and downstream) of the same
priority class (SBOCCLP).
The threshold range is (0..4095) with a granularity of 16 cells.
The CPU programs the threshold with a granularity of 4 cells by
right shifting the value by 4:
DSBT3LP(11:4) := ( threshold_value >> 4)
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Regi ster Desc ript ion
Preliminary Data Sheet 194 2001-14-01
PRELIMINARY
Register 34 DSBT4
Upstream/Downstream DBA Scheduler Block Threshold Register 4
CPU Accessibility : Read/Write
Reset Value: 0000H
Offset Address: DSBT4 39H
Typical Usage: Written and Read by CPU during initialization
Bit151413121110 9 8
DSBT4HP(11:4)
Bit76543210
DSBT4LP(11:4)
DSBT4HP(11:4) DBA Scheduler Block Threshold 4 High Priority
This bit field repr esents the most significant 8-bits of the inter nal 12
bit wide High Priority DBA Threshold 4. The threshold value is
global, but individually evaluated against all scheduler block
specific fill level counter (upstream and downstream) of the same
priority class (SBOCCHP).
The threshold range is (0..4095) with a granularity of 16 cells.
The CPU programs the threshold with a granularity of 4 cells by
right shifting the value by 4:
DSBT4HP(11:4) := ( threshold_value >> 4)
DSBT4LP(11:4) DBA Scheduler Block Threshold 4 Low Priority
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Regi ster Desc ript ion
Preliminary Data Sheet 195 2001-14-01
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This bit field repr esents the most significant 8-bits of the inter nal 12
bit wide Low Priority DBA Threshold 4. The threshold value is
global, but individually evaluated against all scheduler block
specific fill level counter (upstream and downstream) of the same
priority class (SBOCCLP).
The threshold range is (0..4095) with a granularity of 16 cells.
The CPU programs the threshold with a granularity of 4 cells by
right shifting the value by 4:
DSBT4LP(11:4) := ( threshold_value >> 4)
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Regi ster Desc ript ion
Preliminary Data Sheet 196 2001-14-01
PRELIMINARY
Internal Table 1: DBA Threshold Crossing Table Transfer Register
The DBA Threshold Crossing Table (DTCT) Transfer Register is used to access the
internal Upstream/Downstream DBA Threshold Crossing Table containi ng 2*8 entries of
16 bit each. Table 7-4 summarize the registers.
DTCT is the transfer register (read on ly) for a 16-bit DTC Table entry. The Read process
is controlled by the MAR (Memory Address Register). The 5 LSBs (= Bit 4..0) of the MAR
register select the memory/table that will be accessed; to select the DTC Table, bit field
MAR(4:0) must be set to 05H. Bit 5 of MAR starts the transfer and is automatically
cleared after execution of the Read-Modify-Write process.
Table 7-5 WAR Register Mapping for DTC Table access
Table 7-4 Registers DTC Upstream/Downstream Table Access
15 0
DTCT RAM Entry RAM Select:
15 0 15 0
DTCT MAR=05H
Entry Select:
15 0
no Mask;
read access only
WAR (0..7D)
Bit151413121110 9 8
Unused(11:4)
Bit76543210
unused(3:0) Core EntrySel(3:0)
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Preliminary Data Sheet 197 2001-14-01
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Register 35 DTCT
DTC Transfer Register
Core Selects the core (upstream/downstream) for access of the DBA
Threshold Crossing Indication entries:
0 Upstream Core
1 Downstream Core
EntrySel(3:0) Selects one of the 8 DBA Threshold Crossing Indication Entries.
CPU Accessibility : Read
Reset Value: 0000H
Offset Address: DTCT 3AH
Typical Usage: Read by CPU
Bit151413121110 9 8
DTCSBE(15:8)
Bit76543210
DTCSBE(7:0)
DTCSBE(15:0) DBA Threshold Crossing Scheduler Block Event
Each bit indicates that a DBA Threshold Crossing Event has
occured in a specific Scheduler Block (SB). The Threshold Crossing
type must then be read from the respective SOT table entry (see
Regi ste r 50: SOT0 ).
The Scheduler Block
j
is determined from the bit-position
N
in bit-
field DTCSBE(15:8) and the Entry number (Register WAR bit-field
’EntrySel(3:0)’ and bit ’Core’):
Core=’0’ Upstream Events:
jSBUp := EntrySel(3:0) * 16 + N
Core=’1’ Downstream Events:
jSBDn := EntrySel(3:0) * 16 + N
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Regi ster Desc ript ion
Preliminary Data Sheet 199 2001-14-01
PRELIMINARY
Internal Table 2: LCI Table Transfer Registers LCIC, LCI1, LCI2
These registers are used to access the internal Local Connection Identifier (LCI) table
containing 8191 entries (one entry serves for upstream and downstream direction).
Table 7-6 shows an overview of the registers involved.
LCIC, LCI1 and LCI2 are the transfer registers for one 48-bit LCI table entry. The LCI
value representing the table entry which needs to be Read or modified must be written
to the Word Address Register (WAR). The dedicated LCI table entry is Read into the
LCIC/LCI1/LCI2 Registers or modified by the LCIC/LCI1/LCI2 Register values with a
Read-Modify-Write mechanism. The associated Mask Registers MASK0 to MASK2
allow a bit-by-bit selection between Read (1) and Write (0) operation. In case of Read
operation, the dedicated LCIC/LCI1/LCI2 register bit will be overwritten by the respective
LCI table entry bit value. In case of Write operation, the dedicated LCIC/LCI1/LCI2
register bit will modify the respective LCI table entry bit value.
The Read-Modify-Write process is controlled by the Memory Address Register (MAR).
The 5 LSBs (= Bit 4..0) of the MAR select the memory/table that will be accessed; to
select the LCI table bit field MAR(4:0) must be set to 0. Bit 5 of the MAR starts the
transfer and is automatically cleared after execution of the Read-Modify-Write process.
Table 7-7 WAR Register Mapping for LCI Table Access
•
Table 7-6 Registers for LCI Table Access
47 0
LCI RAM entry RAM select:
15 0 15 0 15 0 15 0
LCI2 LCI1 LCIC MAR=00H
LCI select:
15 0 15 0 15 0 15 0
MASK2 MASK1 MASK0 WAR (0..16383D)
Bit151413121110 9 8
Unused(2:0) LCISel(13:8)
Bit76543210
LCISel(7:0)
LCISel(13:0) Selects an LCI entry within the range (0..8191).
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Register 36 LCI0
LCI Transfer Register 0
CPU Accessibility : Read/Write
Reset Value: 0000H
Offset Address: LCI0 3BH
Typical Usage: Written and Read by CPU to maintain the LCI table
Bit151413121110 9 8
Unused(13:6)
Bit76543210
Unused(5:0) CLPT ABM
core
CLPT CLP Transparent:
Specifies whether the CLP bit of cells belonging to this connection
is evaluated or not in threshold checks. Valid for both upstream and
downstream cores.
0 CLP bit is evaluated.
1 CLP bit is not evaluated; all cells are treated as high
priority cells assuming C LP=0.
ABMcore ABM Core Selection:
This bit is valid in Uni-directional Mode only and specifies the core
responsible for cells of this LCI.
0 Schedulers 0..127 are selected (core 0).
1 Schedulers 128..255 are selected (core 1).
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Preliminary Data Sheet 201 2001-14-01
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Register 37 LCI1
LCI Transfer Register 1
CPU Accessibility : Read/Write
Reset Value: 0000H
Offset Address: LCI1 3CH
Typical Usage: Written and Read by CPU to maintain the LCI table
Bit151413121110 9 8
DnQID(12:5)
Bit76543210
DnQID(4:0) flags(2:0)
DnQID(12:0) Downstream Queue Identifier.
Specifies the queue (0..8191) in which the cells of the connection
are stored.
flag 2 Last cell of packet flag for downstream direction;
This bit is autonomously used by the EPD function of the ABM.
Initialize to 1 at connection setup.
Do not Write during normal operation.
flag 1 Discard packet flag in downstream direction;
This bit is autonomously used by the EPD function of the ABM.
Initialize to 0 at connection setup.
Do not Write during normal operation.
flag 0 Discard rest of packet flag in downstream direction;
This bit is autonomously used by the EPD function of the ABM.
Initialize to 0 at connection setup.
Do not Write during normal operation.
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Preliminary Data Sheet 202 2001-14-01
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Register 38 LCI2
LCI Transfer Register 2
CPU Accessibility : Read/Write
Reset Value: 0000H
Offset Address: LCI1 3DH
Typical Usage: Written and Read by CPU to maintain the LCI table
Bit151413121110 9 8
UpQID(12:5)
Bit76543210
UpQID(4:0) flags(2:0)
UpQID(12:0) Upstream Queue Identifier.
Specifies the queue (0..8191) in which the cells of the connection
are stored.
flag 2 Last cell of packet flag for upstream direction;
This bit is autonomously used by the EPD function of the ABM.
Initialize to 1 at connection setup.
Do not Write during normal operation.
flag 1 Discard packet flag in upstream direction;
This bit is autonomously used by the EPD function of the ABM.
Initialize to 0 at connection setup.
Do not Write during normal operation.
flag 0 Discard rest of packet flag in upstream direction;
This bit is autonomously used by the EPD function of the ABM.
Initialize to 0 at connection setup.
Do not Write during normal operation.
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Regi ster Desc ript ion
Preliminary Data Sheet 203 2001-14-01
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Internal Table 3: Traffic Class Table Transfer Registers TCT0, TCT1, TCT2, TCT3
The Traffic Class Table Transfer Registers are used to access the internal Traffic Class
Table (TCT) containing 2*16 entries of 4*64 bits each (16 traffic classes per ABM core,
4 words of 64 bit per entry). Table 7-8 shows an overview of the registers involved.
TCT0, TCT1, TCT2 and TCT3 are the transfer registers used to access the 4*64 bit TCT
table entries.
Core selection, traffic class number, and 64-bit word selection of the table entry which
needs to be Read or Modified must be programmed to the Word Address Register
(WAR). The dedicated TCT table entry 64-bit word is Read into the TCT3/TCT2/TCT1/
TCT0 registers or Modified by th e TCT3/TCT2/ TC T1 /TC T 0 r egister values with a Read-
Modify-Write mechanism. The associated Mask Registers MASKi (i=3..0) allow a bit-by-
bit selection between Read (1) and Write (0) operations. In case of Read operation, the
dedicated TCTi (i=3..0) register bit will be overwritten by the respective TCT table entry
bit value. In case of Write operation, the dedicated TCTi (i=3..0) register bit will modify
the respective TCT table entry bit value.
The Read-Modify-Write process is controlled by the Memory Address Register ( MAR).
The 5 LSBs (= Bit 4..0) of the MAR select the memory/table that will be accessed; to
select the TCT table bit field MAR(4:0) must be set to 1. Bit 5 of MAR starts the transfer
and is automatically cleared after execution of the Read-Modify-Write process.
Table 7-9 WAR Register Mapping for TCT Table Access
Table 7-8 Registers for TCT Table Access
63 0
TCT RAM entry RAM select:
15 0 15 0 15 0 15 0 15 0
TCT3 TCT2 TCT1 TCT0 MAR=01H
TCT entry select:
15 0 15 0 15 0 15 0 15 0
MASK3 MASK2 MASK1 MASK0 WAR (0..127D)
Bit151413121110 9 8
Unused(7:0)
Bit76543210
Unused CoreSel TrafClass(3:0) word64Sel(1:0)
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Regi ster Desc ript ion
Preliminary Data Sheet 204 2001-14-01
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The meaning of registers TCTi (i=3..0) depends on the word selection bit field
’word64Sel(1:0)’ in the WAR, because 256-bit TCT entries are mapped to 64 bits of
registers TCTi (i=3..0) by this selection:
CoreSel Selects the ABM core for TCT table access:
0 Upstream core selected (core 0)
1 Downstream core selected (core 1)
TrafClass(3:0) Selects The Traffic Class for the TCT table access in the range
(0..15).
word64Sel(1:0) Selects The 64-Bit Word of the 256-bit TCT table ent ry for access:
00 Bit field (63..0) of traffic class entry is selected.
01 Bit field (127..64) of traffic class entry is selected.
10 Bit field (191..128) of traffic class entry is selected.
11 Bit field (256..192) of traffic class entry is selected.
WAR modulo 4
63
56
55
48
47 40
39
32
3DiscardedCells(31:0)1)
1) All 5 statistical counters stop at their maximum value. Automatic reset is performed after Read access, i.e. it is
not necessary to initialize them to 0.
2Accepted/Transmitted Packets(31:0)1)
1TrafClassMax(7:0) SbMax(7:0) unused(3:0) SbCiCLP1(11:0)
0DH
(3:0) 2827262524232221 unused(4:0) unused(15:0)
TCT3(15:0) TCT2(15:0)
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Preliminary Data Sheet 205 2001-14-01
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Note: - grey fields are ’unused’, it is recommended to mask them for write access
- green fields must be configured (written) by the CPU
- blue fields are statistic counter values optionally read by CPU
WAR modulo 4
31
24
23
16
15 8
7
0
3unused(7:0) LostCells
TrafClass
(3:0)1)
1) All 5 statistical counters stop at their maximum value. Automatic reset is performed after Read access, i.e. it is
not necessary to initialize them to 0.
LostCells
Scheduler
(3:0)1)
DiscardedPackets/CLP1Cells(15:0)1)
2unused(13:0) TrafClassOccNg(17:0)
1unused(7:0) QueueMax(7:0) unused(3:0) QueueCiCLP1(11:0)
0unused(7:0) BufCiCLP1(7:0) BufMax(7:0) BufEPD(7:0)
TCT1(15:0) TCT0(15:0)
Prel. ABMP Data Sheet
Regi ster Desc ript ion
Preliminary Data Sheet 206 2001-14-01
PRELIMINARY
Register 39 TCT0
TCT Transfer Register 0
Register WAR.Word64Sel(1:0) = ’00’:
Register WAR.Word64Sel(1:0) = ’01’:
CPU Accessibility : Read/Write
Reset Value: 0000H
Offset Address: TCT0 3EH
Typical Usage: Written and Read by CPU to maintain the TCT table;
the meaning of register TCT0 depends on the bit-field
’Word64Sel’ in WAR;
Bit151413121110 9 8
BufMax(7:0)
Bit76543210
BufEPD(7:0)
BufMax(7:0) Maximum Buffer Fill Threshold for a non-real-t ime traff ic class
configuration (register TCT1, DwordSel=00).
The first cell exceedi ng this threshold i s discard ed and if also PPD
is enabled for this traffic class (register TCT1, DwordSel=00,
PPDen=1) PPD is applied on a per connection (LCI) basis.
The threshold is defined with a granularity of 1024 cells:
Threshold = BufNrtMax(7:0) * 1024 Cells
BufEPD(7:0) EPD threshold for a non-real-time traffic class configuration
(register TCT1, DwordS el=’00’).
If the buffer fill exceeds this threshold and EPD is enabled for this
traffic class (register TCT1, DwordSel=00, EPDen=1) EPD is
applied on a per connection (LCI) basis.
The threshold is defined with a granularity of 1024 cells:
Threshold = BufEPD(7:0) * 1024Cells
Prel. ABMP Data Sheet
Regi ster Desc ript ion
Preliminary Data Sheet 207 2001-14-01
PRELIMINARY
•
Register WAR.Word64Sel(1:0) = ’10’:
Register WAR.Word64Sel(1:0) = ’11’:
Bit151413121110 9 8
unused(3:0) QueueCiCLP1(11:8)
Bit76543210
QueueCiCLP1(7:0)
QueueCiCLP1
(11:0) Combined Queue Threshold of this Traffic Class for the
following cases:
a) if ABRen=1 for the traffic class
⇒ ABR Congestion Indication CI/EFCI is triggered
b) if CLPT=0 (CLP transparent bit is not true) and EPDen=0
⇒ CLP1 queue threshold for CLP=1 cells
(cells with CLP=1 are discarded)
c) if CLPT=0 and EPDen=1
⇒ EPD GFR queue threshold. If that threshold and additionally
BufNrtEPD (of the respective traffic class) is exceeded then
EPD is triggered.
The threshold is defined with a granularity of 4:
Threshold = QueueCiCLP1(7:0) * 4 Cells
Bit151413121110 9 8
TrafClassOccNg(15:8)
Bit76543210
TrafClassOccNg(7:0)
TrafClassOccNg
(15:0) Current Buffer Occupation in number of cells for this traffic class.
Do not Write in normal operation.
Prel. ABMP Data Sheet
Regi ster Desc ript ion
Preliminary Data Sheet 208 2001-14-01
PRELIMINARY
Register 40 TCT1
TCT Transfer Register 1
Register WAR.Word64Sel(1:0) = ’00’:
Bit151413121110 9 8
DiscardedPackets/CLP1Cells(15:8)
Bit76543210
DiscardedPackets/CLP1Cells(7:0)
Discarded
Packets/
CLP1Cells(15:0)
Count of Lost Packets due to EPD Overf low for this traffic class
or count of lost CLP=1 cells due to CLP threshold overflow.
Automatically reset after Read access.
CPU Accessibility : Read/Write
Reset Value: 0000H
Offset Address: TCT1 3FH
Typical Usage: Written and Read by CPU to maintain the TCT table;
the meaning of register TCT1 depends on the bit-field
’Word64Sel’ in WAR;
Bit151413121110 9 8
unused(7:0)
Bit76543210
BufCiCLP1(17:10)
Prel. ABMP Data Sheet
Regi ster Desc ript ion
Preliminary Data Sheet 209 2001-14-01
PRELIMINARY
Register WAR.Word64Sel(1:0) = ’01’:
BufCiCLP1
(17:10) Buffer EPD CLP1 Thresh old
This 8-bit value determines a global cell filling level threshold with a
granularity of 1024 cells that triggers explicit packet discard (EPD)
for CLP=1 tagged frames used by GFR traffic class service (low
watermark).
The threshold values are compared with the per scheduler non
guaranteed cell counter SBOCCNG (Scheduler Block Non
Guaranteed Occupancy) (see Internal Table 5:: Scheduler
Occupancy Table Transfer Registers SOT0..SOT4).
The CPU programs the threshold with a granularity of 1024 cells by
right shifting the value by 10:
BufCiCLP1(17:10) := (threshold_value(17:0) >> 10)
Note: In ABM v1.1 this thr eshold was de termined by re giste rs UEC
and DEC.
Bit151413121110 9 8
unused(7:0)
Bit76543210
QueueMax(7:0)
QueueMax
(7:0) This 8-bit value determines the maximum queue length with a
granularity of 64 cells.
The CPU programs the maximum queue length with a granularity of
64 cells by right shifting the value by 6:
QueueMax(7:0) := queuelength >> 6
The maximum length of any queue i s limited to (256*64-1) = 16320
cells.
Prel. ABMP Data Sheet
Regi ster Desc ript ion
Preliminary Data Sheet 210 2001-14-01
PRELIMINARY
Register WAR.Word64Sel(1:0) = ’10’:
•
Register WAR.Word64Sel(1:0) = ’11’:
Bit151413121110 9 8
unused(7:0)
Bit76543210
unused(5:0) TrafClassOccNg
(17:16)
TrafClassOccNg
(17:16) MSBs of Current Buffer Occupation Counter
TrafClassOccNg(17:0) counts the number of cells stored for this
traffic class.
Do not Write in normal operation.
Bit151413121110 9 8
unused(7:0)
Bit76543210
LostCellsTrafClass(3:0) LostCellsScheduler(3:0)
LostCellsTraf
Class(3:0) Count of L ost Cells due to Buffer Overflow for this traffic class.
Automatically reset after Read access.
LostCells
Scheduler(3:0) Count of Lost Cells due to Scheduler Overflow for this traffic
class.
Automatically reset after Read access.
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Preliminary Data Sheet 211 2001-14-01
PRELIMINARY
Register 41 TCT2
TCT Transfer Register 2
Register WAR.Word64Sel(1:0) = ’00’:
•
Register WAR.Word64Sel(1:0) = ’01’:
CPU Accessibility : Read/Write
Reset Value: 0000H
Offset Address: TCT2 40H
Typical Usage: Not used by CPU;
the meaning of register TCT2 depends on the bit-field
’Word64Sel’ in WAR;
Bit151413121110 9 8
unused(7:0)
Bit76543210
unused(7:0)
Bit151413121110 9 8
unused(3:0) SbCiCLP1(11:8)
Bit76543210
SbCiCLP1(7:0)
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Preliminary Data Sheet 212 2001-14-01
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Register WAR.Word64Sel(1:0) = ’10’:
•
Register WAR.Word64Sel(1:0) = ’11’:
SbCiCLP1(11:0) Scheduler Block Ci/CLP1 Threshold
This threshold determines a maximum number of low priority cells
allowed to be stored per scheduler block with a granularity of 64
cells.
The CPU programs the threshold with a granularity of 64 cells by
right shifting the value by 6:
SbCiCLP1(11:0) := threshold >> 6
Bit151413121110 9 8
Accepted/TransmittedPackets(15:8)
Bit76543210
Accepted/TransmittedPackets(7:0)
Accepted/
Transmitted
Packets(15:0)
Count of Accepted AAL5 Units within this traffic class.
This counter is incremented when a user data cell with AAL_
indication=1 is accepted (Pa cket end indicat ion in AAL5: PTI= xx1).
Do not Write in normal operation.
Automatically reset after Read access.
Bit151413121110 9 8
Accepted/TransmittedPackets(15:8)
Bit76543210
Accepted/TransmittedPackets(7:0)
Prel. ABMP Data Sheet
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Preliminary Data Sheet 213 2001-14-01
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Register 42 TCT3
TCT Transfer Register 3
Register WAR.Word64Sel(1:0) = ’00’:
DiscardedCells
(31:16) Count of all discarded cells for this traffic class.
Do not Write in normal operation.
Automatically reset after Read access.
CPU Accessibility : Read/Write
Reset Value: 0000H
Offset Address: TCT3 41H
Typical Usage: Written and Read by CPU to maintain the TCT table;
the meaning of register TCT3 depends on the bit-field
’Word64Sel’ in WAR;
Bit151413121110 9 8
DH(2:0) ABRen ABRVp EPDen PPDen SCNT
Bit76543210
CntLP
DBA GFRen CLPtrans
DBA unused(4:0)
Prel. ABMP Data Sheet
Regi ster Desc ript ion
Preliminary Data Sheet 214 2001-14-01
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DH(2:0) DeltaHysteresis for threshold evaluations with hysteresis applied:
This value is per traffic class, but is evaluated individually for each
effected threshold relative to the threshold size. The hysteresis
determines a lower threshold THhys with
THhysi := Thresholdi - Deltai
The Delta i value is determined by bit-field DH(2:0) and Thresholdi
with:
Deltai := Thresholdi >> [DH(2:0) +1]
The following table shows the operation and resulting THhysi values
for the example of a threshold programmed to 256 cells:
DH(2:0): Deltai:= Example:
0d 0 (hysteresis disabled) THhysi := 256
1d Thresholdi >>2 THhysi := 192
2d Thresholdi >>3 THhysi := 224
3d Thresholdi >>4 THhysi := 240
4d Thresholdi >>5 THhysi := 248
5d Thresholdi >>6 THhysi := 252
6d Thresholdi >>7 THhysi := 254
7d Thresholdi >>8 ( hysteresis ineffective) THhysi := 256
ABRen Congestion indication
This bit enables congestion indication marking in user cells (EFCI
marking) within every ABR connection (LCI) that belongs to this
traffic class:
0 Congestion indication disabled.
1 Congestion indication enabled.
Note: This ABR function is a queue manager function and not
related to the Enhaced Rate Control (ERC) unit.
ABRvp Indication for update of RM cells (ABR service cate gory) relating
to the VP or to the individual VC, respectively:
0 Congestion is indicated via VC RM cells (F5 flow).
VC RM cells are identified with PTI=110 and VCI <> 6.
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Preliminary Data Sheet 215 2001-14-01
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1 Congestion is indicated via VP RM cells (F4 flow).
VP RM cells are identified with VCI=6 (regardless of the
value of the PTI field)
Note: According to the standards, VP RM cells MUST
have VCI=6 and PTI=110. If cells with PTI=110
and VCI <> 6 are contained in the cell stream they
are ignored. This is the correct behavior for an
ABR VC within an ABR VP.
EPDen EPD for the individual traffic class. EPD is used for every
connection (LCI) within that traffic class:
0 EPD is disabled.
1 EPD is enabled.
PPDen PPD for the individual traffic class. PPD is used for every
connection (LCI) within that traffic class:
0 PPD is disabled
1 PPD is enabled
SCNT Counter Function Select
This bit selects the function of counter ’Accepted Packets/
Cells(31:0)’:
0 Accepted Packets are counted
1 Accepted Cells are counted
CntLPDBA Count all Low Priority (DBA):
This bit enforces that all cells of that traffic class are counted as low
priority cells for DBA threshold counters, regardless of the CLP bit
value.
0 CLP bit is evaluated and deter mines whet her the cell is
counted by the High Priority (HP) or Low Priority (LP)
counters.
1 CLP bit is not evaluated; all cells are treated as low
priority and are counted by the Low Priority counter
(LP).
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Preliminary Data Sheet 216 2001-14-01
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Register WAR.Word64Sel(1:0) = ’01’:
GFRen GFR Enable:
This bit enables a modified EPD threshold evaluation for GFR
traffic.
0
1
CLPtransDBA CLP Transparent (DBA):
Specifies whether the CLP bit of cells belonging to this connection
is evaluated or not for DBA thres hold checks and counters.
0 CLP bit is evaluated.
1 CLP bit is not evaluated; all cells are treated as high
priority cells assuming C LP=0.
Bit151413121110 9 8
TrafClassMax(7:0)
Bit76543210
SbMax(7:0)
TrafClassMax
(7:0) Maximum Traffic Class Fill Threshold (determines th e maximum
number of cells in al l queues associated with this traffic class). The
threshold is defined with a granularity of 1024:
Threshold = TrafClassMax(7:0) * 1024 Cells
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Preliminary Data Sheet 217 2001-14-01
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Register WAR.Word64Sel(1:0) = ’10’:
•
Register WAR.Word64Sel(1:0) = ’11’:
SbMax(7:0) Combined Threshold of the Maximum Number of Buffered
Cells in the Scheduler; that is, all cells which are in the traffic
classes (= cells in the corresponding queues) of the Scheduler for
the following cases:
a) If EPDen=0 and ABRen=0
⇒ Maximum Scheduler fill threshold for CLP=’0/1’ cells
b) If EPDen=1 and ABRen=0
⇒ EPD Scheduler threshold
c) If ABRen=1
⇒ CI Scheduler threshold for ABR connections
(Set CI-Bit (Congestion Indication) in the RM cells)
The threshold is defined with a granularity of 256:
Threshold = SbMaxEpdCi(7:0) * 256 Cells
Bit151413121110 9 8
Accepted/TransmittedPackets(31:24)
Bit76543210
Accepted/TransmittedPackets(23:16)
Accepted/
Transmitted
Packets(31:16)
Count of Accepted AAL5 Units within this traffic class.
This counter is incremented when a user data cell with AAL_
indication=1 is accepted (Pa cket end indicat ion in AAL5: PTI= xx1).
Do not Write in normal operation.
Automatically reset after Read access.
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Bit151413121110 9 8
DiscardedCells(31:24)
Bit76543210
DiscardedCells(23:16)
DiscardedCells
(31:16) Count of all discarded cells for this traffic class.
Do not Write in normal operation.
Automatically reset after Read access.
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Preliminary Data Sheet 219 2001-14-01
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Internal Table 4: Queue Configuration Table Transfer Registers QCT0..6
Queue Configuration Table Transfer Registers are used to access the internal Queue
Configuration Table (QCT) containing 2*8192 entries. The lower 8K entries control the
upstream core queues and the upper 8K entries control the downstream core queues.
Table 7-10 shows an overview of the registers involved.
QCT0...QCT6 are the transfer registers for one 112 bit QCT table entry. The core
selection and queue number representing the table entry which needs to be Read or
modified must be written to the Word Address Register (WAR). The dedicated QCT table
entry is Read into the QCT0..QCT6 registers or modified by the QCT0..QCT6 register
values with a Read-Modify-Write mechanism. The associated Mask Registers
MASK0..MASK6 allow a bit-by-bit selection between Read (1) and Write (0) operation.
In case o f Read ope ration, the dedicated QCT0..QCT6 register bit will be overwritte n b y
the respective QCT table entry bit value. In case of Write operation, the dedicated
QCT0..QCT6 register bit will modify the respective QCT table entry bit value.
Note: It is recommended not to Write to bit fields (111:64) and (15:0) of the QCT table
entries; i.e. registers MASK0, MASK6, MASK5, MASK4 and MASK3 should
always be programmed with FFFF
H
.
The 13 LSBs (= Bit 12..0) of the WAR regi ster select the queue-specific en try that will be
accessed and bit ’CoreSel’ the ABM core.
The Read-Modify-Write process is controlled by the Memory Address Register (MAR).
The 5 LSBs (= Bit 4..0) of the MAR select the memory/table that will be accessed; to
select the QCT table, bit fi eld MAR(4:0) must be set to 2. Bit 5 of MAR starts the tra nsfer
and is automatically cleared after execution of the Read-Modify-Write process.
Table 7-10 Regi sters for Queue Conf iguration Table Ac cess
111 0
QCT RAM entry RAM
select:
15 0 15 0 15 0 15 0 15 0 15 0 15 0 15 0
QCT6 QCT5 QCT4 QCT3 QCT2 QCT1 QCT0 MAR=02H
Queue
select:
15 0 15 0 15 0 15 0 15 0 15 0 15 0 15 0
MASK6
=FFFFH
MASK5
=FFFFH
MASK4
=FFFFH
MASK3
=FFFFHMASK2 MASK1 MASK0
=FFFFH
WAR
(0..16383D
)
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Table 7-11 WAR Register Mapping for LCI Table Access
Register 43 QCT0
Queue Configuration Transfer Register 0
Bit151413121110 9 8
unused(1:0) CoreSel QSel(12:8)
Bit76543210
QSel(7:0)
CoreSel Selects an ABM Core:
0 Upstream core selected
1 Downstream core selected
QSel(12:0) Selects a Queue Entry within the range (0..8191).
CPU Accessibility : Read/Write
Reset Value: 0000H
Offset Address: QCT0 42H
Typical Usage: Read by CPU
Bit151413121110 9 8
Unused(1:0) QueueLength(13:8)
Bit76543210
QueueLength(7:0)
QueueLength
(13:0) Represents the Current Number of Cells Stored in this Queue.
Do not Write in normal operation.
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Register 44 QCT1
Queue Configuration Transfer Register 1
CPU Accessibility : Read/Write
Reset Value: 0000H
Offset Address: QCT1 43H
Typical Usage: Written and Read by CPU to maintain the LCI table
Bit151413121110 9 8
DQac RSall VS/VD
en ABR
dir TrafClass(3:0)
Bit76543210
QIDvalid SID(6:0)
DQac Dummy Queue Action
This bit is a command bit that must always be set when a dummy
queue is activated or deactivated.
Note: Read access to this command bit will always return ’0’.
RSall ReSchedule Always
This bit determines the queue scheduling process:
’0’ The queue is only scheduled/re-scheduled with its
specific rate while the queue is not empty (normal
operation).
Note: ’RSall’ can be reset anytime while the queue is
enabled. In response to resetting ’RSall’ the
ABMP will generate an interrupt (Bit ’DDQACC’
in...) and reset bit ’MGConf/DQsch’ in this table.
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’1’ The queue is always scheduled/re-scheduled with its
specifc rate independent of the queue filling level.
Scheduling an empty queue results in an ’empty cell
cycle’ (no cell is emitted during this cycle).
A so called ’dummy queue’ is used either for generat ing
empty cell cycles or by the ERC unit for generati ng out-
of-rate RM cells.
Note: ’RSall’ can be set with co nnection setup (together
with QIDvalid=’1’) or anytime while the queue is
enabled.
Note: The ’RSall’ information is internally conveyed to
the scheduler. This process is acknowledged by
setting bit ’DQac’ and an interrupt (Bit ’DDQACC’
in...). It is recommended not to select any other
table or table entry while waiting for this
acknowledge.
Note: After setting bit ’RSall’, the ABMP will
automatically set bit ’MGConf/DQsch’ to
acknowledge the first dummy schedule event.
Note: To activate or deactivate a dummy queue, command bit
’DQac’ must be set in conjuntion with setting or resetting bit
’RSall’.
VS/VDen VS/VD Enable
This bit enables ABR VS/VD operation for the queue (in conjunction
with appropriate settings of the ERC unit):
’0’ The queue is not configured for ABR VS/VD operation.
’1’ The queue is configured for ABR VS/VD operation in
conjunction with proper settings of the ERC unit.
This bit enables contr ol i nformati on e xchange be twee n
the Queue Manager and the ERC unit as well as
enables ABR OAM cell handling.
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•
QIDvalid Queue Enable:
0 Queue disabled.
An attempt to store a cell to a disabled queue leads to
discard of the cell an d a QIDINV inter rupt is generat ed.
If a filled queue gets disabled, cells may still be in the
queue. In this case the disabled queue is still scheduled,
and cells are logically emitted from the queue but will not
be transmitted.
Actual filling of the queue can be ob tained via
QueueLength(13:0) parameter in the QCT entry.
Note: If the queue was part of a VC-merge group,
deactivating the queue by setting QIDvalid=’0’
automatically starts an internal process to delete
the queue from the VC-merge group. This
process is acknowledged by status bit ’DQacc’.
It is recommended not to disable any further
queue while waiting for this acknowledge.
1 Queue enabled.
Cells are allowed to enter the queue.
TrafClass(3:0) Traffic Class Number (0..15)
Assigns the queue to one of the 16 traffic classes defined in the
traffic class table TCT for this core.
SID(6:0) Scheduler Number (0..127)
Assigns the queue to one of the 128 schedulers of this core.
ABRdir ABR CI/NI update of backward RM cells:
0 RM cells of the same core are updated.
1 RM cells of the opposite core are updated.
Note: ABR Congestion Indication is done in RM cells of the backward ABR connection.
In Bi-directional Mode, these cells are handled by the opposite core (therefore
ABRdir must be 1 for each ABR QID). In Mini-switch Mode, these cells can be
handled fro m the same or opposite core depending on configuration. (If o nly one
core will be used ,ABRdir must be 0 for each ABR QID.)
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Register 45 QCT2
Queue Configuration Transfer Register 2
CPU Accessibility : Read/Write
Reset Value: 0000H
Offset Address: QCT2 44H
Typical Usage: Written by CPU to configure VC-Merge operation
Bit151413121110 9 8
MGconf/
DQsch MGID(6:0)
Bit76543210
MinBG(7:0)
Prel. ABMP Data Sheet
Regi ster Desc ript ion
Preliminary Data Sheet 225 2001-14-01
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MGconf/
DQsch Merge Group Configured/
Dummy Queue Scheduled
The meaning of this flag depends on bit ’RSall’:
RSall=’0’
The queue is not configured as a ’dummy queue’ and may be
configured as a VC-merge group member:
MGconf
0 The queue is neith er a dummy qu eue, nor mem ber of a
VC-merge group.
1 The queue is member of a VC-merge group. The VC-
merge group is determined by bit-field ’MGID(6:0).
Note: To disable an active VC-merge group, bit
’QIDvalid’ must be reset. Deactivating the queue
by setting QIDvalid=’0’ automatically starts an
internal process to delete the queue from the VC-
merge group. In response to resetting ’QIDvalid’
the ABMP will generate an interrupt (Bit
’DMQACC’ in...) and reset bit ’MGConf/DQsch’ in
this table.
RSall=’1’
The queue is configured as a ’dummy queue’:
DQsch
0 The queue is activated as a ’dummy queue’ , but no first
dummy schedule event has occured.
1 The queue is activated as a ’dummy queue’ and at least
one first dummy schedule event has occured.
Note: ’RSall’ can be reset anytime while the queue is
enabled. In response to resetting ’RSall’ the
ABMP will generate an interrupt (Bit ’DDQACC’
in...) and reset bit ’MGConf/DQsch’ in this table.
MGID(6:0) Merge Group Number (0..127)
Assigns the queue to one of 128 merge groups of this core.
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Preliminary Data Sheet 226 2001-14-01
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Register 46 QCT3
Queue Configuration Transfer Register 3
MinBG(7:0) Minimum Buffer Guarantee
This bit-field determines a minimum buffer reservation for this
particular queue. The sum of all minimum buffer reservations
virtually devides the total buffer into a ’guaranteed’ part and a
shared ’Non-Guaranteed’ part.
The minimum buffer reservation offers to granularities depending
on MSB bit MinBG(7):
MinBG(7)
:= 0 Granularity of 1 cell for short queues (e.g. real-time
queues):
The minimum reserved buffer in number of cells is
reserved_buffer = MinBG(6:0) = {0,1,2,..127}
MinBG(7)
:= 1 Granularity of 8 cells for long queues (e.g. non-real-time
queues):
The minimum reserved buffer in number of cells is
reserved_buffer = MinBG(6:0) << 3 = {0,8,16,..1016}
CPU Accessibility : Read/Write
Reset Value: 0000H
Offset Address: QCT3 45H
Typical Usage: Not used by CPU
Bit151413121110 9 8
unused(11:4)
Bit76543210
unused(3:0) EOP CI NI EFCI
EOP EOP-Flag:
Do not Write during normal operation.
CI CI-Flag:
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Preliminary Data Sheet 227 2001-14-01
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Whenever a cell is a ccepted the respective que ue threshol d values
are checked. In case a CI condition is detected, this condition is
stored in flag2 for further recognition by resource monitoring
operation (ABR).
It is recommended to set this bit to 0 during queue setup.
Do not Write during normal operation.
NI NI-Flag:
Whenever a cell is a ccepted the respective que ue threshol d values
are checked. In case a NI condition is detected, this condition is
stored in flag1 for further recognition by resource monitoring
operation (ABR).
It is recommended to set this bit to 0 during queue setup.
Do not Write during normal operation.
EFCI EFCI-Flag:
Whenever a cell is a ccepted the respective que ue threshol d values
are checked. In case a EFCI cond ition is detected, this condition is
stored in flag0 for further recognition by resource monitoring
operation (ABR).
It is recommended to set this bit to 0 during queue setup.
Do not Write during normal operation.
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Preliminary Data Sheet 228 2001-14-01
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Register 47 QCT4
Queue Configuration Transfer Register 4
Register 48 QCT5
Queue Configuration Transfer Register 5
CPU Accessibility : Read/Write
Reset Value: 0000H
Offset Address: QCT4 46H
Typical Usage: Not used by CPU
Bit151413121110 9 8
Reserved(15:8)
Bit76543210
Reserved(15:8)
reserved(15:0) Do not Write in normal operation.
CPU Accessibility : Read/Write
Reset Value: 0000H
Offset Address: QCT5 47H
Typical Usage: Not used by CPU
Bit151413121110 9 8
Reserved(15:8)
Bit76543210
Reserved(15:8)
Prel. ABMP Data Sheet
Regi ster Desc ript ion
Preliminary Data Sheet 229 2001-14-01
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Register 49 QCT6
Queue Configuration Transfer Register 6
reserved(15:0) Do not Write in normal operation.
CPU Accessibility : Read/Write
Reset Value: 0000H
Offset Address: QCT6 48H
Typical Usage: Not used by CPU
Bit151413121110 9 8
Reserved(15:8)
Bit76543210
Reserved(15:8)
reserved(15:0) Do not Write in normal operation.
Prel. ABMP Data Sheet
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Preliminary Data Sheet 230 2001-14-01
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Internal Table 5: Scheduler Occupancy Table Transfer Registers SOT0..SOT4
The Scheduler Occupancy Table Transfer Registers are used to access the internal
Scheduler Occupancy Table (SOT) containing 2*128 entries of 80 bit each. Table 7-12
shows an overview of the registers involved.
Note: The SOT table information is typically not required by the CPU. The SOT
maintains global counters that are internally used for threshold evaluation.
In case of DBA operation, the SOT0 transfer register provides information about
threshold crossing events that are evaluated by CPU for the DBA algorithm.
For statistical purposes, reading the SOT entries provides a snap shot of the
respective scheduler occupation situation distinguished by priorities and also the
current number of discarded low priority cells.
SOT0..SOT4 are the transfer registers for one 80-bit SOT table entry. The Scheduler
number representing the table entry which needs to be Read or modified must be written
to the Word Address Register (WAR). The dedicated SOT table entry is Read into the
SOT0..SOT4 Registers or modified by the SOT0..SOT4 register values with a Read-
Modify-Write mechanism. The associated Mask Registers MASK0..MASK4 allow a bit-
by-bit selection between Read (1) and Write (0) operation. In case of Read operation,
the dedicated SOT0..SOT4 register bit will be overwritten by the respective SOT table
entry bit value. In case of Write operation, the dedicated SOT0..SOT4 register bit will
modify the respective SOT table entry bit value.
The Read-Modify-Write process is controlled by the Memory Address Register (MAR).
The 5 LSBs (= Bit 4..0) of the MAR register select the memory/table that will be
accessed; to select the SOT table, bit field MAR(4:0) must be set to 3. Bit 5 of MAR starts
the transfer and is automatically cleared after execution of the Read-Modify-Write
process.
Table 7-12 Registers for SOT Table Access
79 0
SOT RAM entry RAM Select:
15 0 15 0 15 0 15 0 15 0 15 0
SOT4 SOT3 SOT2 SOT1 SOT0 MAR=03H
Entry select:
15 0 15 0 15 0 15 0 15 0 15 0
MASK4 MASK3 MASK2 MASK1 MASK0 WAR (0..255D)
Prel. ABMP Data Sheet
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Preliminary Data Sheet 231 2001-14-01
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Table 7-13 WAR Register Mapping for SOT Table Access
Register 50 SOT0
SOT Transfer Register 0
Bit 15 14 13 12 11 10 9 8
Unused(7:0)
Bit 7 6 5 4 3 2 1 0
CoreSel SchedSel(6:0)
CoreSel Selects an ABM core:
0 Upstream core selected
1 Downstream core selected
SchedSel(6:0) Selects one of the 128 core-specific Schedulers.
CPU Accessibility : Read only
Reset Value: 0000H
Offset Address: SOT0 49H
Typical Usage: Read by CPU
Bit151413121110 9 8
SBOCCNG(1:0) SBOCCHP(1:0) SBOCCLP(1:0) SBOCCLPd(1:0)
Bit76543210
DBATHCROSS(7:0)
DBATHCROSS
(7:0) DBA Threshold Crossing Indication
Prel. ABMP Data Sheet
Regi ster Desc ript ion
Preliminary Data Sheet 232 2001-14-01
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Register 51 SOT1
SOT Transfer Register 1
Register 52 SOT2
SOT Transfer Register 2
CPU Accessibility : Read/Write
Reset Value: 0000H
Offset Address: SOT1 4AH
Typical Usage: Read by CPU (for debug purposes or statistics)
Bit151413121110 9 8
SBOCCLPd(17:10)
Bit76543210
SBOCCLPd(9:2)
SBOCCLPd
(17:2) Scheduler Block Occupancy Counter Low Priority Discarded
Cells
Note: The LSBs SBOCCLPd(1:0) are mapped to transfer register
SOT0.
CPU Accessibility : Read/Write
Reset Value: 0000H
Offset Address: SOT1 4BH
Typical Usage: Read by CPU (for debug purposes or statistics)
Bit151413121110 9 8
SBOCCLP(17:10)
Bit76543210
SBOCCLP(9:2)
Prel. ABMP Data Sheet
Regi ster Desc ript ion
Preliminary Data Sheet 233 2001-14-01
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Register 53 SOT3
SOT Transfer Register 3
SBOCCLP(17: 2) Scheduler Block Occupancy Counter Low Priority
Note: The LSBs SBOCCLP(1:0) are mapped to transfer register
SOT0.
CPU Accessibility : Read/Write
Reset Value: 0000H
Offset Address: SOT3 4CH
Typical Usage: Read by CPU (for debug purposes or statistics)
Bit151413121110 9 8
SBOCCHP(17:10)
Bit76543210
SBOCCHP(9:2)
SBOCCHP(17:2) Scheduler Block Occupancy Counter High Priority
Note: The LSBs SBOCCHP(1:0) are mapped to transfer register
SOT0.
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Preliminary Data Sheet 234 2001-14-01
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Register 54 SOT4
SOT Transfer Register 4
CPU Accessibility : Read/Write
Reset Value: 0000H
Offset Address: SOT4 4DH
Typical Usage: Read by CPU (for debug purposes or statistics)
Bit151413121110 9 8
SBOCCNG(17:10)
Bit76543210
SBOCCNG(9:2)
SBOCCNG(17:2) Scheduler Block Occupancy Counter Non Guaranteed
Note: The LSBs SBOCCNG(1:0) are mapped to transfer register
SOT0.
Prel. ABMP Data Sheet
Regi ster Desc ript ion
Preliminary Data Sheet 235 2001-14-01
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Internal Table 6: Merge Group Table Transfer Registers MGT0..MGT2
The Merge Group Table Transfer Registers are used to access the internal Merge Group
Table (MGT) containi ng 2*128 entries of 48 bit each. Table 7-12 shows an overview of
the registers involved.
MGT0..MGT2 are the transfer registers for one 48-bit MGT table entry. The Scheduler
number repr esenting the table en try which needs to b e rea d or modifi ed must be wri tten
to the Word Address Register (WAR). The dedicated MGT table entry is read into the
MGT0..MGT2 Registers or modified by the MGT0..MGT2 register values with a Read-
Modify-Write mechanism. The associated Mask Registers MASK0..MASK2 allow a bit-
by-bit selectio n betwe en Read (1) and Write (0) oper ation. In case of read operation, the
dedicated MGT0..MGT2 register bit will be overwritten by the respective MGT table entry
bit value. In case of Write operation, the dedicated MGT0..MGT2 register bit will modify
the respective MGT table entry bit value.
The Read-Modify-Write process is controlled by the Memory Address Register (MAR).
The 5 LSBs (= Bit 4..0) of the MAR register select the memory/table that will be
accessed; to select the MGT table, bit field MAR(4:0) must be set to 6. Bit 5 of MAR
starts the transfer and i s automatical ly cleared after exe cution of the Read-Modify- Write
process.
Table 7-14 Registers for MGT Table Access
47 0
MGT RAM entry RAM Select:
15 0 15 0 15 0 15 0
MGT2 MGT1 MGT0 MAR=06H
Entry select:
15 0 15 0 15 0 15 0
MASK2 MASK1 MASK0 WAR (0..255D)
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Preliminary Data Sheet 236 2001-14-01
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Table 7-15 WAR Register Mapping for MGT Table Access
Register 55 MGT0
MGT Transfer Register 0
Bit 15 14 13 12 11 10 9 8
Unused(7:0)
Bit 7 6 5 4 3 2 1 0
CoreSel GroupSel(6:0)
CoreSel Selects an ABM core:
0 Upstream core selected
1 Downstream core selected
GroupSel(6:0) Selects one of the 128 Merge Groups.
CPU Accessibility : Read/Write
Reset Value: 0000H
Offset Address: MGT0 4EH
Typical Usage: Not used by CPU
Bit151413121110 9 8
Reserved(15:8)
Bit76543210
Reserved(7:0)
Reserved(15:0)
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Preliminary Data Sheet 237 2001-14-01
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Register 56 MGT1
MGT Transfer Register 1
Register 57 MGT2
MGT Transfer Register 2
CPU Accessibility : Read/Write
Reset Value: 0000H
Offset Address: MGT1 4FH
Typical Usage: Not used by CPU
Bit151413121110 9 8
Reserved(15:8)
Bit76543210
Reserved(7:0)
Reserved(15:0)
CPU Accessibility : Read/Write
Reset Value: 0000H
Offset Address: MGT2 50H
Typical Usage: Written by CPU to maintain the MGT table
Bit151413121110 9 8
unused LCIOen LCI(13:8)
Bit76543210
LCI(7:0)
Prel. ABMP Data Sheet
Regi ster Desc ript ion
Preliminary Data Sheet 238 2001-14-01
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Register 58 MASK0/MASK1
Table Access Mask Registers 0/1
LCIOen LCI Overwrite Enable:
This bit enables the LCI overwrite function for cells/packets emitted
by the VC-Merge Group.
0 Disable LCI overwrite
1 Enable LCI overwrite
LCI(13:0) LCI
In case LCI overw rite function is enabled, this value overwrites the
original LCI of any cell emitted by this VC-Merge Group.
The cell field that is overwritten depends on the selected LCI
mapping mode.
CPU Accessibility : Read/Write
Reset Value: 0000H
Offset Address: MASK0 55HMASK1 56H
Typical Usage: Written by CPU to control internal table Read/Write
access
Bit151413121110 9 8
MASK(15:8)
Bit76543210
MASK(7:0)
MASK0(15:0) Mask Register 0
MASK1(15:0) Mask Register 1
Prel. ABMP Data Sheet
Regi ster Desc ript ion
Preliminary Data Sheet 239 2001-14-01
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Register 59 MASK2/MASK3
Table Access Mask Registers 2/3
Mask Regi sters 0..6 control the Read-Modif y-Write access from the
respective transfer registers to the internal tables on a per-bit
selection basis. The mask registers correspond to the respective
transfer registers (LCI0..LCI2, TCT0..TCT3, QCT0..6,
SOT0..SOT4, MGT0..MGT2):
0 The dedicated bit of the transfer register is
not
overwritten by the corresponding table entry bit during
Read; but overwrites the table entry bit during the
Modify-Write process.
This is a Write access to the internal table entry.
1 The dedicated bit of the transfer register is overwritten
by the corresponding tab le entry bit dur ing Read and is
written back to the table entry bit during Modify-Write.
This is a Read access to the internal table entry.
CPU Accessibility : Read/Write
Reset Value: 0000H
Offset Address: MASK2 57HMASK3 58H
Typical Usage: Written by CPU to control internal table Read/Write
access
Bit151413121110 9 8
MASK(15:8)
Bit76543210
MASK(7:0)
Prel. ABMP Data Sheet
Regi ster Desc ript ion
Preliminary Data Sheet 240 2001-14-01
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Register 60 MASK4/MASK5
Table Access Mask Registers 4/5
MASK2(15:0) Mask Register 2
MASK3(15:0) Mask Register 3
Mask Regi sters 0..6 control the Read-Modif y-Write access from the
respective transfer registers to the internal tables on a per-bit
selection basis. The mask registers correspond to the respective
transfer registers (LCI0..LCI2, TCT0..TCT3, QCT0..6,
SOT0..SOT4, MGT0..MGT2):
0 The dedicated bit of the transfer register is
not
overwritten by the corresponding table entry bit during
Read; but overwrites the table entry bit during the
Modify-Write process.
This is a Write access to the internal table entry.
1 The dedicated bit of the transfer register is overwritten
by the corresponding tab le entry bit dur ing Read and is
written back to the table entry bit during Modify-Write.
This is a Read access to the internal table entry.
CPU Accessibility : Read/Write
Reset Value: 0000H
Offset Address: MASK4 59HMASK5 5AH
Typical Usage: Written by CPU to control internal table Read/Write
access
Bit151413121110 9 8
MASK(15:8)
Bit76543210
MASK(7:0)
MASK4(15:0) Mask Register 4
MASK5(15:0) Mask Register 5
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Regi ster Desc ript ion
Preliminary Data Sheet 241 2001-14-01
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Register 61 MASK6
Table Access Mask Registers 6
Mask Regi sters 0..6 control the Read-Modif y-Write access from the
respective transfer registers to the internal tables on a per-bit
selection basis. The mask registers correspond to the respective
transfer registers (LCI0..LCI2, TCT0..TCT3, QCT0..6,
SOT0..SOT4, MGT0..MGT2):
0 The dedicated bit of the transfer register is
not
overwritten by the corresponding table entry bit during
Read; but overwrites the table entry bit during the
Modify-Write process.
This is a Write access to the internal table entry.
1 The dedicated bit of the transfer register is overwritten
by the corresponding tab le entry bit dur ing Read and is
written back to the table entry bit during Modify-Write.
This is a Read access to the internal table entry.
CPU Accessibility : Read/Write
Reset Value: 0000H
Offset Address: MASK6 5BH
Typical Usage: Written by CPU to control internal table Read/Write
access
Bit151413121110 9 8
MASK(15:8)
Bit76543210
MASK(7:0)
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Regi ster Desc ript ion
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MASK6(15:0) Mask Register 6
Mask Regi sters 0..6 control the Read-Modif y-Write access from the
respective transfer registers to the internal tables on a per-bit
selection basis. The mask registers correspond to the respective
transfer registers (LCI0..LCI2, TCT0..TCT3, QCT0..6,
SOT0..SOT4, MGT0..MGT2):
0 The dedicated bit of the transfer register is
not
overwritten by the corresponding table entry bit during
Read; but overwrites the table entry bit during the
Modify-Write process.
This is a Write access to the internal table entry.
1 The dedicated bit of the transfer register is overwritten
by the corresponding tab le entry bit dur ing Read and is
written back to the table entry bit during Modify-Write.
This is a Read access to the internal table entry.
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Regi ster Desc ript ion
Preliminary Data Sheet 243 2001-14-01
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Internal Table 7: Queue Congestion Indication Table Transfer Register
The Queue C ongestion Indication Table (QCIT) Transfer Regi ster is used to access the
internal Downstream Queue Congestion Indication Table containing 8192 entries of 16
bit each. Table 7-4 summarize the registers.
QCIT is the transfer re gister for a 16- bit QCIT Table entry. Table access is contr olled by
the MAR (Memory Address Re gister). Th e 5 LSBs (= Bit 4..0) of the MAR register select
the memory/table that will be accessed; to select the QCIT Table, bit field MAR(4:0) must
be set to 08H. Bit 5 of MAR starts the transfer and is automatically cleared after execution
of the Read-Modify-Write process.
Table 7-17 WAR Register Mapping for DTC Table access
Table 7-16 Registers QCIT Table Access
15 0
QCIT RAM Entry RAM Select:
15 0 15 0
QCIT MAR=08H
Entry Select:
15 0
no Mask
WAR (0..8191D)
Bit151413121110 9 8
Unused(2:0) EntrySel(12:8)
Bit76543210
EntrySel(7:0)
EntrySel(12:0) Selects one of the 8192 Queue Congestion Indication Table
Entries.
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Register 62 QCIT
QCIT Transfer Register
CPU Accessibility : Read/Write
Reset Value: 0000H
Offset Address: QCIT 5CH
Typical Usage: Written by CPU
Bit151413121110 9 8
Unused(3:0) QCITH(11:8)
Bit76543210
QCITH(7:0)
QCITH(11:0) Queue Congestion Ind i cation Thresh old
This threshold determines the number of cells stored in the
dedicated queue to set the associated congestion indication bit in
the bit pattern of the QCI interface. The threshold value is
programmed with a granularity of 4 cells.
The CPU programs the threshold with a granularity of 4 cells by
right shifting the value by 2:
QCITH(11:0) := threshold >> 2
Note: Reset of the congestion indication is performed with a
hysteresis. The hysteresi s value is common to al l congestio n
indication thresholds, but evaluated queue threshold specific.
See Register 30: DQCIC for more details.
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Regi ster Desc ript ion
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Register 63 UCDV/DCDV
Upstream/Downstream Rate Shaper CDV Registers
CPU Accessibility : Read/Write
Reset Value: 0000H
Offset Address: UCDV 62HDCDV 82H
Typical Usage: Written by CPU
Bit151413121110 9 8
Unused(6:0) CDV
Max(8)
Bit76543210
CDVMax(7:0)
CDVMax(8:0) Maximal Cell Delay Variation (without notice)
This bit-field determines a maximum CDV value for peak rate
limited queues that can be introduced without notice.
The CDVMax is measured in multiples of 16-cell cycles.
If this maximum CDV is exceeded, a CDVOV (see registers ISRU/
ISRD) interrupt is generated to indicate an unexpected CDV value.
This can occur if multipl e peak rate limited queues ar e scheduled to
emit a cell in the same Scheduler time slot.
No cells are discarded due to this event.
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Regi ster Desc ript ion
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Register 64 UQPTM0/DQPTM0
Upstream/Downstream Queue Parameter Table Mask Registers 0
CPU Accessibility : Read/Write
Reset Value: 0000H
Offset Address: UQPTM0 65HDQPTM0 85H
Typical Usage: Written by CPU to control internal table Read/Write
access
Bit151413121110 9 8
xQPTM0(15:8)
Bit76543210
xQPTM0(7:0)
UQPTM0(15:0) Upstream QPT Mask Register 0
DQPTM0(15:0) Downstream QPT Mask Register 0
UQPTM0/DQPTM0 contr ol t he R ead- Modi fy- Write a ccess fr om th e
respective transfer registers to the internal tables on a per-bit
selection basis. The mask registers correspond to the respective
transfer registers (QPTHU0/QPTHU1, QPTLU0/QPTLU1):
0 The dedicated bit of the transfer register is not
overwritten by the corresponding table entry bit during
Read; but overwrites the table entry bit during the
Modify-Write process.
This is a Write access to the internal table entry.
1 The dedicated bit of the transfer register is overwritten
by the corresponding tab le entry bit dur ing Read and is
written back to the table entry bit during Modify-Write.
This is a Read access to the internal table entry.
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Register 65 UQPTM1/DQPTM1
Upstream/Downstream Queue Parameter Table Mask Registers 1
CPU Accessibility : Read/Write
Reset Value: 0000H
Offset Address: UQPTM1 66HDQPTM1 86H
Typical Usage: Written by CPU to control internal table Read/Write
access
Bit151413121110 9 8
xQPTM1(15:8)
Bit76543210
xQPTM1(7:0)
UQPTM1(15:0) Upstream QPT Mask Register 1
DQPTM1(15:0) Downstream QPT Mask Register 1
UQPTM1/DQPTM1 contr ol t he R ead- Modi fy- Write a ccess fr om th e
respective transfer registers to the internal tables on a per-bit
selection basis. The mask registers correspond to the respective
transfer registers (QPTHU0/QPTHU1, QPTLU0/QPTLU1):
0 The dedicated bit of the transfer register is not
overwritten by the corresponding table entry bit during
Read; but overwrites the table entry bit during the
Modify-Write process.
This is a Write access to the internal table entry.
1 The dedicated bit of the transfer register is overwritten
by the corresponding tab le entry bit dur ing Read and is
written back to the table entry bit during Modify-Write.
This is a Read access to the internal table entry.
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Regi ster Desc ript ion
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Register 66 UQPTM2/DQPTM2
Upstream/Downstream Queue Parameter Table Mask Registers 2
CPU Accessibility : Read/Write
Reset Value: 0000H
Offset Address: UQPTM2 67HDQPTM2 87H
Typical Usage: Written by CPU to control internal table Read/Write
access
Bit151413121110 9 8
xQPTM2(15:8)
Bit76543210
xQPTM2(7:0)
UQPTM2(15:0) Upstream QPT Mask Register 2
DQPTM2(15:0) Downstream QPT Mask Register 2
UQPTM2/DQPTM2 contr ol t he R ead- Modi fy- Write a ccess fr om th e
respective transfer registers to the internal tables on a per-bit
selection basis. The mask registers correspond to the respective
transfer registers (QPTHU0/QPTHU1, QPTLU0/QPTLU1):
0 The dedicated bit of the transfer register is not
overwritten by the corresponding table entry bit during
Read; but overwrites the table entry bit during the
Modify-Write process.
This is a Write access to the internal table entry.
1 The dedicated bit of the transfer register is overwritten
by the corresponding tab le entry bit dur ing Read and is
written back to the table entry bit during Modify-Write.
This is a Read access to the internal table entry.
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Regi ster Desc ript ion
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Register 67 UQPTM3/DQPTM3
Upstream/Downstream Queue Parameter Table Mask Registers 3
CPU Accessibility : Read/Write
Reset Value: 0000H
Offset Address: UQPTM3 68HDQPTM3 86H
Typical Usage: Written by CPU to control internal table Read/Write
access
Bit151413121110 9 8
xQPTM3(15:8)
Bit76543210
xQPTM3(7:0)
UQPTM3(15:0) Upstream QPT Mask Register 3
DQPTM3(15:0) Downstream QPT Mask Register 3
UQPTM3/DQPTM3 contr ol t he R ead- Modi fy- Write a ccess fr om th e
respective transfer registers to the internal tables on a per-bit
selection basis. The mask registers correspond to the respective
transfer registers (QPTHU0/QPTHU1, QPTLU0/QPTLU1):
0 The dedicated bit of the transfer register is not
overwritten by the corresponding table entry bit during
Read; but overwrites the table entry bit during the
Modify-Write process.
This is a Write access to the internal table entry.
1 The dedicated bit of the transfer register is overwritten
by the corresponding tab le entry bit dur ing Read and is
written back to the table entry bit during Modify-Write.
This is a Read access to the internal table entry.
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Regi ster Desc ript ion
Preliminary Data Sheet 250 2001-14-01
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Register 68 UQPTM4/DQPTM4
Upstream/Downstream Queue Parameter Table Mask Registers 4
CPU Accessibility : Read/Write
Reset Value: 0000H
Offset Address: UQPTM4 69HDQPTM4 89H
Typical Usage: Not used for user-accessible tables.
Bit151413121110 9 8
xQPTM4(15:8)
Bit76543210
xQPTM4(7:0)
UQPTM4(15:0) Upstream QPT Mask Register 4
DQPTM4(15:0) Downstream QPT Mask Register 4
UQPTM4/DQPTM4 contr ol t he R ead-Modi fy- Write a ccess from th e
respective transfer registers to the internal tables on a per-bit
selection basis. The mask registers correspond to the respective
transfer registers:
0 The dedicated bit of the transfer register is not
overwritten by the corresponding table entry bit during
Read; but overwrites the table entry bit during the
Modify-Write process.
This is a Write access to the internal table entry.
1 The dedicated bit of the transfer register is overwritten
by the corresponding tab le entry bit dur ing Read and is
written back to the table entry bit during Modify-Write.
This is a Read access to the internal table entry.
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Regi ster Desc ript ion
Preliminary Data Sheet 251 2001-14-01
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Register 69 UQPTM5/DQPTM5
Upstream/Downstream Queue Parameter Table Mask Registers 5
CPU Accessibility : Read/Write
Reset Value: 0000H
Offset Address: UQPTM5 6AHDQPTM5 8AH
Typical Usage: Not used for user-accessible tables.
Bit151413121110 9 8
xQPTM5(15:8)
Bit76543210
xQPTM5(7:0)
UQPTM5(15:0) Upstream QPT Mask Register 5
DQPTM5(15:0) Downstream QPT Mask Register 5
UQPTM5/DQPTM5 contr ol t he R ead- Modi fy- Write a ccess fr om th e
respective transfer registers to the internal tables on a per-bit
selection basis. The mask registers correspond to the respective
transfer registers:
0 The dedicated bit of the transfer register is not
overwritten by the corresponding table entry bit during
Read; but overwrites the table entry bit during the
Modify-Write process.
This is a Write access to the internal table entry.
1 The dedicated bit of the transfer register is overwritten
by the corresponding tab le entry bit dur ing Read and is
written back to the table entry bit during Modify-Write.
This is a Read access to the internal table entry.
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Register 70 USCONF/DSCONF
Upstream/Downstream Scheduler Configuration Registers
CPU Accessibility : Read/Write
Reset Value: 0004H
Offset Address: USCONF 6BHDSCONF 8BH
Typical Usage: Written by CPU during global initialization
Bit151413121110 9 8
unused(12:5)
Bit76543210
unused(4:0) TstepC(2:0)
TstepC(2:0) Time Base for the Rate Shaper Calendar
This bit-field determines a multiplication factor for the PCR rate
shaper calendar clock. With default settings (after reset) the rate
shaper calendar is triggered by every 16th cell cycle (1 cell cycle is
32 SYSCLKs) (as in ABM v1.1). The minimum cell rate that can be
shaped is limited by the range of the cycle counter to 262144
entries:
minimum cell rate := SYSCLK / 32 / 262144
To enhance shaping to desired lower or higher rates, the calendar
clock (cell rate respectively) can be multiplied by an additi onal
factor:
minimum cell rate := [SYSCLK / 32 / 262144] * Factor
TstepC(2:0)
0d Factor 1
1d Factor 2
2d Factor 4
3d Factor 8
4d Factor 16 (default reset value)
5d Factor 32
6d Factor 64
7d Factor 128
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Internal Table 8: Queue Parameter Table 1 Transfer Registers
Queue Parameter Table Transfer Registers are used to access the internal Upstream
and Downstream Queue Parameter Table 1 (QPT1) containing 8192 entries each. In
both Table 7-18 and Table 7-19 provide an overview of the registers involved. Each
QPT1 entry consists of 32 bit.
Note: The QPT1 table information is not used by the CPU beside during queue
initialization.
UQPT1T0 and UQPT1T1 are the transfer registers for the 32-bit entry of the upstream
QPT1 table. DQPT1T0 and DQPT1T1 are the transfer registers for the 32-bit entry of the
downstream QPT1 table. Access to high and low word are both controlled by mask
registers UQPTM0/UQPTM1 and DQPTM0/DQPTM1 respectively. The Mask registers
Table 7-18 Registers for QPT1 Upstream Table Access
31 0
QPT1 RAM entry (Upstream) RAM Select:
15 0 15 0 15 0
UQPT1T1 UQPT1T0 MAR=10H
Entry Select:
15 0 15 0 15 0
UQPTM1 UQPTM0 WAR (0..8191D)
Table 7-19 Registers for QPT1 Downstream Table Access
31 0
QPT1 RAM entry (Downstream) RAM Select:
15 0 15 0 15 0
DQPT1T1 DQPT1T0 MAR=18H
Entry Select:
15 0 15 0 15 0
DQPTM1 DQPTM0 WAR (0..8191D)
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Preliminary Data Sheet 254 2001-14-01
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are shared for access to b oth tables QPT1 and QPT2 wher eas the transfer r egisters a re
unique for each table.
The queue number representing the table entry which needs to be Read or modified
must be written to the Word Address Register (WAR). The dedicated QPT1 table entry
is Read into the xQPT1T0/xQPT1T1 transfer registers (x=U,D) or modified by the
xQPT1T0/xQPT1T1 transfer register values with a Read-Modify-Write mechanism. The
associated mask registers xQPTM0 and xQPTM1 allow a bit-by-bit selection between
Read (1) and Write (0) operation. In case of Read operation, the dedicated xQPT1T0/
xQPT1T1 register bit will be overwritten by the respective QPT1 table entry bit value. In
case of Write operation, the dedicated xQPT1T0/xQPT1T1 register bit will modify the
respective QPT1 table entry bit value.
The Read-Modify-Write process is controlled by the Memory Address Register (MAR).
The 5 LSBs (= Bit 4..0) of the MAR register select the memory/table that will be
accessed; to select the QPT table bit field MAR(4:0) must be set to
10H for QPT1 upstream table,
18H for QPT1 downstream table.
Bit 5 of MAR starts the transfer and is cleared au tomatically after execution of the Read-
Modify-Write pro ce ss.
Table 7-20 WAR Register Mapping for QPT Table Access
Bit151413121110 9 8
Unused(2:0) QueueSel(12:8)
Bit76543210
QueueSel(7:0)
QueueSel(12:0) Selects one of the 8192 queue parameter table entries.
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Preliminary Data Sheet 255 2001-14-01
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Register 71 UQPT1T0/DQPT1T0
Upstream/Downstream QPT1 Table Transfer Register 0
CPU Accessibility : Read/Write
Reset Value: 0000H
Offset Address: UQPT1T0 70HDQPT1T0 90H
Typical Usage: Written by CPU during queue initialization
Bit151413121110 9 8
Reserved(13:6)
Bit76543210
Reserved(5:0) flags(1:0)
Reserved(13:0) These bits a re used by the device logic. D o not Write to this field as
that could lead to complete malfunctioning of the ABM which can be
corrected by chip reset only.
flags(1:0) These bits must be written to 0 when initializing the queue. Do not
Write during normal operation.
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Preliminary Data Sheet 256 2001-14-01
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Register 72 UQPT1T1/DQPT1T1
Upstream/Downstream QPT1 Table Transfer Register 1
CPU Accessibility : Read/Write
Reset Value: 0000H
Offset Address: UQPT1T1 71HDQPT1T0 91H
Typical Usage: Not used by CPU
Bit151413121110 9 8
Reserved(15:8)
Bit76543210
Reserved(7:0)
Reserved(15:0) These bits a re used by the device logic. D o not Write to this field as
that could lead to complete malfunctioning of the ABM which can be
corrected by chip reset only.
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Internal Table 9: Queue Parameter Table 2 Transfer Registers
Queue Parameter Table Transfer Registers are used to access the internal Upstream
and Downstream Queue Parameter Table 2 (QPT2) containing 8192 entries each. In
both Table 7-21 and Table 7-22 provide an overview of the registers involved. Each
QPT2 entry consists of 64 bit.
UQPT2T0..UQPT2T3 are the transfer registers for the 64-bit entry of the upstream QPT2
table. DQPT1T0..DQPT1T3 are the transfer registers for the 64-bit entry of the
downstream QPT2 table. Access to the RAM entry is controlled by mask registers
UQPTM0..UQPTM3 and DQPTM0..DQPTM3 respectively. The Mask registers are
shared for access to both tables QPT1 and QPT2 whereas the transfer registers are
unique for each table.
Table 7-21 Registers for QPT2 Upstream Table Access
63 0
QPT2 RA M entry (Upstream) RAM Select:
15 0 15 0 15 0 15 0 15 0
UQPT2T3 UQPT2T2 UQPT2T1 UQPT2T0 MAR=11H
Entry Select:
15 0 15 0 15 0 15 0 15 0
UQPTM3 UQ PTM2 UQPTM1 UQPTM0 WAR (0..8191D)
Table 7-22 Registers for QPT2 Downstream Table Access
63 0
QPT2 RAM entry (Downstream) RAM Select:
15 0 15 0 15 0 15 0 15 0
DQPT2T3 DQPT2T2 DQPT2T1 DQPT2T0 MAR=19H
Entry Select:
15 0 15 0 15 0 15 0 15 0
DQPTM3 DQ PTM2 DQPTM1 DQPTM0 WAR (0..8191D)
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Preliminary Data Sheet 258 2001-14-01
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The queue number representing the table entry which needs to be Read or modified
must be written to the Word Address Register (WAR). The dedicated QPT2 table entry
is Read into the xQPT2T0..xQPT2T3 transfer registers (x=U,D) or modified by the
xQPT2T0..xQPT2T3 transfer register val ues with a Read-Mo dify-Write me chanism. The
associated mask regi sters xQPTM0..xQPTM3 allow a bit-b y-bit selection between R ead
(1) and Write (0) operation. In case of Read operation, the dedicated
xQPT2T0..xQPT2T3 register bit will be overwritten by the respective QPT1 table entry
bit value. In case of Write operation, the dedicated xQPT2T0..xQPT2T3 register bit will
modify the respective QPT1 table entry bit value.
The Read-Modify-Write process is controlled by the Memory Address Register (MAR).
The 5 LSBs (= Bit 4..0) of the MAR register select the memory/table that will be
accessed; to select the QPT table bit field MAR(4:0) must be set to
11H for QPT2 upstream table,
19H for QPT2 downstream table.
Bit 5 of MAR starts the transfer and is cleared au tomatically after execution of the Read-
Modify-Write pro ce ss.
Table 7-23 WAR Register Mapping for QPT Table Access
Bit151413121110 9 8
Unused(2:0) QueueSel(12:8)
Bit76543210
QueueSel(7:0)
QueueSel(12:0) Selects one of the 8192 queue parameter table entries.
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Preliminary Data Sheet 259 2001-14-01
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Register 73 UQPT2T0/DQPT2T0
Upstream/Downstream QPT2 Table Transfer Register 0
Register 74 UQPT2T1/DQPT2T1
Upstream/Downstream QPT2 Table Transfer Register 1
CPU Accessibility : Read/Write
Reset Value: 0000H
Offset Address: UQPT2T0 72HDQPT2T0 92H
Typical Usage: Written by CPU during queue initialization
Bit151413121110 9 8
RateFactor(15:8)
Bit76543210
RateFactor(7:0)
RateFactor(15:0) Controls the Peak Cell Rate of the queue. It is identical to the Rate
factor ’m ’ des c r ib ed in “Programming of the Peak Rate Limiter /
PCR Shaper” on Page 109. The valu e 0 disables th e PCR li miter,
that is, the cells from this queue bypass the shaper circuit.
CPU Accessibility : Read/Write
Reset Value: 0000H
Offset Address: UQPT2T1 73HDQPT2T1 93H
Typical Usage: Written by CPU during queue initialization
Bit151413121110 9 8
Unused(1:0) WFQFactor(13:8)
Bit76543210
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Register 75 UQPT2T2/DQPT2T2
Upstream/Downstream QPT2 Table Transfer Register 2
WFQFactor(7:0)
WFQFactor
(13:0) Determines the weight factor W of the queue at the WFQ
multiplexer input to which it is connected. 1/n = W is the weight
factor.
The value WFQ factor = 0 connects the queue directly to the priority
multiplexor bypassing the WFQ Multiplexer. (If more then one
queue is connected to the priority multiplexer, then scheduled
queues are served with LIFO bahavior).
CPU Accessibility : Read/Write
Reset Value: 0000H
Offset Address: UQPT2T2 74HDQPT2T2 94H
Typical Usage: Not used by CPU
Bit151413121110 9 8
Reserved(15:8)
Bit76543210
Reserved(7:0)
Reserved(15:0) These bits a re used by the device logic. D o not Write to this field as
that could lead to complete malfunctioning of the ABM which can be
corrected by chip reset only.
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Register 76 UQPT2T3/DQPT2T3
Upstream/Downstream QPT2 Table Transfer Register 3
CPU Accessibility : Read/Write
Reset Value: 0000H
Offset Address: UQPT2T3 75HDQPT2T3 95H
Typical Usage: Not used by CPU
Bit151413121110 9 8
Reserved(15:8)
Bit76543210
Reserved(7:0)
Reserved(15:0) These bits a re used by the device logic. D o not Write to this field as
that could lead to complete malfunctioning of the ABM which can be
corrected by chip reset only.
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Internal Table 10: Scheduler Configuration Table Integer Transfer Registers
The Scheduler Configuration Table Integer Transfer Registers are used to access the
internal Upstream/Downstream Scheduler Configuration Tables Integer Part (SCTI)
containing 128 entries each.
These tables are not addressed by the MAR and WAR regisers, but are addressed via
dedicated address registers (USADR/DSADR) and data registers (USCTI/DSCTI).
Table 7-24 and Table 7-25 show an overview of the registers involved.
Table 7-24 Registers SCTI Upstream Table Access
31 0
SCTI RAM entry
(Upstream) RAM/Entry/Word
select:
15 0 15 0
USCTI USADR
(WSEL=1)
15 0 15 0
USCTI USADR
(WSEL=0)
Table 7-25 Registers SCTI Downstream Table Access
31 0
SCTI RAM Entry
(Downstream) RAM/Entry/Word
select:
15 0 15 0
DSCTI DSADR
(WSEL=1)
15 0 15 0
DSCTI DSADR
(WSEL=0)
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USCTI and DSCTI are the transfer registers for the 32-bit SCTI upstream/downstream
table entries. The upstream and downstream Schedulers use different tables (internal
RAMs) addressed via dedicated registers, USADR/DSADR. The address registers
select the sche dul er- speci fi c entry as w ell as the hi gh or l ow word of a 32-bit entry to be
accessed. Further, th ere is no command bit , but transfers are t riggered via Wri te access
of the address registers and the data registers:
• To initiate a Read access, the Scheduler number must be written to the address
register USADR (upstream) or to the address register DSADR (downstream). One
system clock cycle later, the data can be Read from the respective transfer register
USCTI or DSCTI.
• To in itiate a Wri te access, it is suffi cient to Wri te the desir ed Schedul er number to the
address registers, USADR and DSADR, and then Write the desired data to the
respective transfer register, USCTI or DSCTI, respectively. The transfer to the integ er
table is executed one system clock cycle after the Write access to USCTI or DSCT I.
Thus, consecutive Write cycles may be executed by the microprocessor.
The SCTI tab le en tri es a re ei ther r ead or wr itt en. Thus, no additi ona l ma sk registers are
provided for bit-wise control of table entry accesses.
Register 77 USADR/DSADR
Upstream/Downstream SCTI Address Registers
CPU Accessibility : Read/Write
Reset Value: 0000H
Offset Address: USADR A0HDSADR B8H
Typical Usage: Written and Read by CPU to maintain the SCTI tables
Bit151413121110 9 8
unused(7:0)
Bit76543210
WSel SchedNo(6:0)
WSel SCTI table entry Word Select
1 Selects the high word (bit 31..16) for next access via
register SCTIU/SCTID
0 Selects the low word (bit 15..0) for next access via
register SCTIU/SCTID
Prel. ABMP Data Sheet
Regi ster Desc ript ion
Preliminary Data Sheet 264 2001-14-01
PRELIMINARY
Register 78 USCTI/DSCTI
Upstream/Downstream SCTI Transfer Registers
Register SADRx.WSel = 0:
SchedNo(6:0) Scheduler Number
Selects one of the 128 core-specific Schedulers for next access via
register USCTI/ DSC TI.
CPU Accessibility : Read/Write
Reset Value: 0000H
Offset Address: USCTI A1HDSCTI B9H
Typical Usage: Written by CPU to maintain the SCTI tables
Bit151413121110 9 8
unused(1:0) IntRate(13:8)
Bit76543210
IntRate(7:0)
IntRate (13:0) Integer Rate
This value d etermines the i nteger part of the Scheduler output rate.
Note: Recommendation for changing the UTOPIA port number or scheduler rate
during operation:
Disable specific scheduler by read-mod ify-write operation to corresponding bit in
registe rs USCEN0/DSCEN0... USCEN7/DSCEN7.
Modify scheduler specific UTOPIA port number and rates via Table 10
"Scheduler Configuration Table Integer Transfer Registers" on Page 262,
registers USCTI/DSCTI and Table 11 "Scheduler Configuration Table
Fractional Transfer Registers" on Page 274, registers USCTFT/DSCTFT.
Enable specifi c schedu ler by read -modi fy-wri te operati on to co rresponding bit i n
registe rs USCEN0/DSCEN0... USCEN7/DSCEN7.
Prel. ABMP Data Sheet
Regi ster Desc ript ion
Preliminary Data Sheet 265 2001-14-01
PRELIMINARY
Register SADRx.WSel = 1:
Note: Read access to bit-field IntRate(13:0) is not supported and will retu rn undef ine d
values.
The following formulars explain how the two parameters IntRate and FracRate deter-
mine the scheduler output rate R via an auxiliary parameter T:
T = [without dimension]
with
• ABM core clock, [SYSCLK} = 1/s
• Sc heduler output rate, [R] = cells/s
IntRate =
with
• int(T) is integer part of T
FracRate =
Thus IntRate and FracRate can be calculated for a given scheduler output rate R.
Bit151413121110 9 8
Init(9:2)
Bit76543210
Init(1:0) UtopiaPort(5:0)
Init(9:0) Initialization Value
It is recommended to Write this bit-field to all zeroes during
Scheduler configuration/initialization (see note below for further
details).
SYSCLK
32 cells 1–R×
------------------------------------
int T()
TintT()–{}256 1+×
Prel. ABMP Data Sheet
Regi ster Desc ript ion
Preliminary Data Sheet 266 2001-14-01
PRELIMINARY
UtopiaPort(5:0) UTOPIA Port Number
Specifies one of the 48 UTOPIA ports to which the Scheduler is
assigned to. Only values in the range 0..47D are valid. The UTOPIA
port number value can be changed during operation (see note
below).
The UTOPIA port number can be modified during operation; (port) switch-over is
e.g. used for ATM protection switching. The following Notes explain switch-over and
rate adaption during operation:
Note: This SCTI table entry should be programmed during Scheduler configuration/
initialization. However the UTOPIA port number value can be modified during
operation (e.g. for port switchi ng) . In this case the Init( 9:0) value can be r eset to
zero. This bit-field contains a 4 bit counter incrementing the number of unused
scheduler cell cycles. Unused cell cycles occur whenever a scheduled event
cannot be served, because a previo usly generated event is still in service (active
cell tran sfer at U TOPIA i nterface). Thi s counter value is used ( and decre mented
accordingly) to determine the allowed cell burst size for following scheduler
events. Such bursts are treated as ’one event’ to allow a near 100% scheduler
rate utilization. The maximum burst size is programmed in registers
UECRI/
DECRI on page 7-267.
Thus overwriting bit-field Init(9:0) with zero during operation may invalidate some
stored cell cycles, only if maximum burst size is programmed >1 for this port.
Only saved scheduler cell cycles can get lost, in no means stored cells can get
lost or discarded by these operations.
To minimize even this small im pact, value Init( 9:0) can be read and wri tten back
with the new UTOPIA port number.
Note: Recommendation for changing the UTOPIA port number or scheduler rate
during operation:
Disable specific scheduler by read-mod ify-write operation to corresponding bit in
registe rs USCEN0/DSCEN0... USCEN7/DSCEN7.
Modify scheduler specific UTOPIA port number and rates via Table 10
"Scheduler Configuration Table Integer Transfer Registers" on Page 262,
registers USCTI/DSCTI and Table 11 "Scheduler Configuration Table
Fractional Transfer Registers" on Page 274, registers USCTFT/DSCTFT.
Enable specifi c schedu ler by read -modi fy-wri te operati on to co rresponding bit i n
registe rs USCEN0/DSCEN0... USCEN7/DSCEN7.
Prel. ABMP Data Sheet
Regi ster Desc ript ion
Preliminary Data Sheet 267 2001-14-01
PRELIMINARY
Register 79 UECRI/DECRI
Upstream/Downstream Empty Cycle Rate Integer Part Registers
CPU Accessibility : Read/Write
Reset Value: 0000H
Offset Address: UECRI A2HDECRI BAH
Typical Usage: Written by CPU for global Scheduler configuration
Bit151413121110 9 8
MaxBurstS(3:0) Unused(1:0) ECIntRate(9:8)
Bit76543210
ECIntRate(7:0)
Prel. ABMP Data Sheet
Regi ster Desc ript ion
Preliminary Data Sheet 268 2001-14-01
PRELIMINARY
MaxBurstS(3:0) Maximum Burst size for a Scheduler
Per scheduler cell bursts can occur due to previously unused cell
cycles. Each scheduler has an event generator that determines
when this scheduler should be served based on the programmed
scheduler rates. Because several schedulers share one UTOPIA
interface, it may happe n that events cannot be served immedia tely
due to active cell transfers of previous events. Such ’unused cell
cycles’ are counted (see also registers USCTI/DSCTI on page 7-
264) and can be used for later cell bursts allowing a near 100%
scheduler rate u tilization. Cell bursts due to this mechanism are not
rate limited.
The maximum burst size, generated due to previously counted
’unused cell cycles’, is controlled by bit field MaxBurstS(3:0) in the
range 0..15 cells (a minimum value of 1 is recommended).
Maximum burst size dimensioning depends on the burst tolerance
of subsequent devices (buffer capacity and backpressure
capability).
E.g. if PHY(s) connected to the ABM do not support backpressure
and provide a 3 cell transmit buffer, a value in the range 1..3 is
recommended to avoid PHY buffer overflows resulting in cell losses
(e.g. typical for ADSL PHYs connected to the ABM).
If a PHY is connected that supports port specific backpressure to
prevent its transmit buffers from overflowing or provides sufficient
buffering, the maximum value of 15 can be programmed
guaranteeing a near 100% scheduler rate utilization.
Prel. ABMP Data Sheet
Regi ster Desc ript ion
Preliminary Data Sheet 269 2001-14-01
PRELIMINARY
ECIntRate(9:0) Integer part of Empty Cycle Rate
The empty cycles are required by internal logic to perform the
refresh cycles of the SDRAMS.
Minimum value is 10H and should be programmed during
configuration.
The following formulars explain how the two parameters ECIntRate and ECFracRate
determine the scheduler output rate R via an auxiliary parameter T:
with:
• ABM core clock SYSCLK = [1/s]
• SDRAM RefreshPeriod = [s]
• SDRAM RefreshCycles requirement
ECIntRate =
with
• int(T) is integer part of T
ECFracRate =
Thus ECIntRate and ECFracRate can be calculated for a gi ven scheduler output rate
R.
(see “Empty Cell Rate Calculation Example” on Page 111)
Tmax SYSCLK RefreshPeriod×
32 RefreshCycles×
--------------------------------------------------------------------------8()=
int T()
TintT()–{}256 1+×
Prel. ABMP Data Sheet
Regi ster Desc ript ion
Preliminary Data Sheet 270 2001-14-01
PRELIMINARY
Register 80 UECRF/DECRF
Upstream/Downstream Empty Cycle Rate Fractional Part Registers
CPU Accessibility : Read/Write
Reset Value: 0000H
Offset Address: UECRF A3HDECRF BBH
Typical Usage: Written by CPU for global Scheduler configuration
Bit151413121110 9 8
Unused(7:0)
Bit76543210
ECFracRate(7:0)
Prel. ABMP Data Sheet
Regi ster Desc ript ion
Preliminary Data Sheet 271 2001-14-01
PRELIMINARY
ECFracRate(7:0) Fractional part of Empty Cycle Rate
The empty cycles are required by internal logic to perform the
refresh cycles of the SDRAMS.
Recommended value is 00H and should be programmed during
configuration.
The following formulars explain how the two parameters ECIntRate and ECFracRate
determine the scheduler output rate R via an auxiliary parameter T:
with:
• ABM core clock SYSCLK = [1/s]
• SDRAM RefreshPeriod = [s]
• SDRAM RefreshCycles requirement
ECIntRate =
with
• int(T) is integer part of T
ECFracRate =
Thus ECIntRate and ECFracRate can be calculated for a gi ven scheduler output rate
R.
(see “Empty Cell Rate Calculation Example” on Page 111)
Tmax SYSCLK RefreshPeriod×
32 RefreshCycles×
--------------------------------------------------------------------------8()=
int T()
TintT()–{}256 1+×
Prel. ABMP Data Sheet
Regi ster Desc ript ion
Preliminary Data Sheet 272 2001-14-01
PRELIMINARY
Register 81 UCRTQ/DCRTQ
Upstream/Downstream Common Real Time Queue UTOPIA Port
Select Registers
Register 82 USCTFM/DSCTFM
Upstream/Downstream SCTF Mask Registers
CPU Accessibility : Read/Write
Reset Value: 0000H
Offset Address: UCRTQ A4HDCRTQ BCH
Typical Usage: Written by CPU for global Scheduler configuration
Bit151413121110 9 8
Unused(9:2)
Bit76543210
Unused(1:0) CrtqUtopia(5:0)
CtrqUtopia(4:0) Common Real Time Queue UTOPIA Port Number.
Specifies one of the 48 UTOPIA ports to which the common real
time queue is assigned. Only values in the range 0..47D are valid.
CPU Accessibility : Read/Write
Reset Value: 0000H
Offset Address: USCTFM A5HDSCTFM BDH
Typical Usage: Written by CPU to control internal table Read/Write
access
Bit151413121110 9 8
SCTFM(15:8)
Bit76543210
SCTFM(7:0)
Prel. ABMP Data Sheet
Regi ster Desc ript ion
Preliminary Data Sheet 273 2001-14-01
PRELIMINARY
USCTFM(15:0) Upstream SCTF Mask Register
DSCTFM(15:0) Downstream SCTF Mask Register
USCTFM and DSCTFM control the Read-Modify-Write access from
the respective transfer registers to the internal tables on a per-bit
selection basis. The mask registers correspond to the respective
transfer registers (USCTFT, DSCTFT):
0 The dedicated bit of the transfer register is not
overwritten by the corresponding table entry bit during
Read; but does overwrite the table entry bit during the
Modify-Write process.
This is a Write access to the internal table entry.
1 The dedicated bit of the transfer register is overwritten
by the corresponding tab le entry bit dur ing Read and is
written back to the table entry bit during the Modify-Write
process.
This is a Read access to the internal table entry.
Prel. ABMP Data Sheet
Regi ster Desc ript ion
Preliminary Data Sheet 274 2001-14-01
PRELIMINARY
Internal Table 11: Scheduler Configuration Table Fractional Transfer Registers
The Scheduler Co nfiguration Table Fractional Transfer Registers are used to access the
internal Upstream/Downstream Scheduler Configuration Tables Fractional Part (SCTF)
containing 128 entries each. Table 7-26 and Table 7-27 summarize the registers.
SCTFU and SCTFD are transfer registers for one 16-bit SCTF upstream/downstream
table entry. The upstream and downstream Schedulers use different tables (internal
RAMs) addressed via the MAR. The Scheduler number representing the table entry
which needs to be Read or modified must be written to the WAR (Word Address
Register). The dedicated SCTFU/D table entry is Read into the SCTFU/D registers or
modified by the SCTFU/D register value with a Read-Modify-Write mechanism. The
associated mask registers, SMSKU and SMSKD, allow a bit-by-bit selection between
Read (1) and Write (0) operation. In case of Read operation, the dedicated SCTFU/D
register bit will be overwritten by the respective SCTFU/D table entry bit value. In case
Table 7-26 Registers SCTF Upstream Table Access
15 0
SCTF RAM Entry
(Upstream) RAM Select:
15 0 15 0
USCTF MAR=17H
Entry Select:
15 0 15 0
USCTFM WAR (0..127D)
Table 7-27 Registers SCTF Downstream Table Access
15 0
SCTF RAM Entry
(Downstream) RAM Select:
15 0 15 0
DSCTF MAR=1FH
Entry Select:
15 0 15 0
DSCTFM WAR (0..127D)
Prel. ABMP Data Sheet
Regi ster Desc ript ion
Preliminary Data Sheet 275 2001-14-01
PRELIMINARY
of Write operation, the dedicated SCTFU/D register bit will modify the value of the
respective SCTFU/D table entry bit.
The Read-Modify-Write process is controlled by the MAR (Memory Address Register).
The 5 LSBs (= Bit 4..0) of the MAR register select the memory/table that will be
accessed; to select the SCTF Upstrea m table, bit field MAR( 4:0) must be set to 17H and
1FH for the SCTF Downstream table respectively. Bit 5 of MAR starts the transfer and is
automatically cleared after execution of the Read-Modify-Write process.
Table 7-28 WAR Register Mapping for SCTFU/SCTFD Table access
Register 83 USCTFT/DSCTFT
Upstream/Downstream SCTF Transfer Registers
Bit151413121110 9 8
Unused(9:2)
Bit76543210
unused SchedSel(6:0)
SchedSel(6:0) Selects one of the 128 core specific Schedulers.
CPU Accessibility : Read/Write
Reset Value: 0000H
Offset Address: USCTFT A6HDSCTFT BEH
Typical Usage: Written and Read by CPU to maintain the SCTF tables
Bit151413121110 9 8
Init(7:0)
Bit76543210
FracRate(7:0)
Prel. ABMP Data Sheet
Regi ster Desc ript ion
Preliminary Data Sheet 276 2001-14-01
PRELIMINARY
Init(7:0) Scheduler Initialization Value
This bit-field must be written to 00H at the time of Scheduler
configuration/initialization and should not be written during normal
operation.
FracRate(7:0) Fractional Rate
This value determines the fractional part of the Scheduler output
rate.
Note: Recommendation for changing the UTOPIA port number or scheduler rate
during operation:
Disable specific scheduler by read-mod ify-write operation to corresponding bit in
registe rs USCEN0/DSCEN0... USCEN7/DSCEN7.
Modify scheduler specific UTOPIA port number and rates via Table 10
"Scheduler Configuration Table Integer Transfer Registers" on Page 262,
registers USCTI/DSCTI and Table 11 "Scheduler Configuration Table
Fractional Transfer Registers" on Page 274, registers USCTFT/DSCTFT.
Enable specifi c schedu ler by read -modi fy-wri te operati on to co rresponding bit i n
registe rs USCEN0/DSCEN0... USCEN7/DSCEN7.
The following formulars explain how the two parameters IntRate and FracRate deter-
mine the scheduler output rate R via an auxiliary parameter T:
T = [without dimens io n]
with
• ABM core clock, [SYSCLK} = 1/s
• Sc heduler output rate, [R] = cells/s
IntRate =
with
• int(T) is integer part of T
FracRate =
Thus IntRate and FracRate can be calculated for a given scheduler output rate R.
SYSCLK
32 cells 1–R×
------------------------------------
int T()
TintT()–{}256 1+×
Prel. ABMP Data Sheet
Regi ster Desc ript ion
Preliminary Data Sheet 277 2001-14-01
PRELIMINARY
Register 84 USCEN0/DSCEN0
Upstream/Downstream Scheduler Enable 0 Registers
Register 85 USCEN1/DSCEN1
Upstream/Downstream Scheduler Enable 1 Registers
CPU Accessibility : Read/Write
Reset Value: 0000H
Offset Address: USCEN0 A8HDSCEN0 C0H
Typical Usage: Written by CPU for global Scheduler configuration
Bit151413121110 9 8
SchedEn(15:8)
Bit76543210
SchedEn(7:0)
SchedEn(15:0) Scheduler Enable
Each bit position enables/disables the respective Scheduler (15..0):
1 Scheduler enabled
0 Scheduler disabled
CPU Accessibility : Read/Write
Reset Value: 0000H
Offset Address: USCEN0 A9HDSCEN0 C1H
Typical Usage: Written by CPU for global Scheduler configuration
Bit151413121110 9 8
SchedEn(31:24)
Bit76543210
SchedEn(23:16)
Prel. ABMP Data Sheet
Regi ster Desc ript ion
Preliminary Data Sheet 278 2001-14-01
PRELIMINARY
Register 86 USCEN2/DSCEN2
Upstream/Downstream Scheduler Enable 2 Registers
SchedEn(31:16) Scheduler Enable
Each bit position enables/disables the respective Scheduler
(31..16):
1 Scheduler enabled
0 Scheduler disabled
CPU Accessibility : Read/Write
Reset Value: 0000H
Offset Address: USCEN2 AAHDSCEN2 C2H
Typical Usage: Written by CPU for global Scheduler configuration
Bit151413121110 9 8
SchedEn(47:40)
Bit76543210
SchedEn(39:32)
SchedEn(47:32) Scheduler Enable
Each bit position enables/disables the respective Scheduler
(47..32):
1 Scheduler enabled
0 Scheduler disabled
Prel. ABMP Data Sheet
Regi ster Desc ript ion
Preliminary Data Sheet 279 2001-14-01
PRELIMINARY
Register 87 USCEN3/DSCEN3
Upstream/Downstream Scheduler Enable 3 Registers
Register 88 USCEN4/DSCEN4
Upstream/Downstream Scheduler Enable 4 Registers
CPU Accessibility : Read/Write
Reset Value: 0000H
Offset Address: USCEN3 ABHDSCEN3 C3H
Typical Usage: Written by CPU for global Scheduler configuration
Bit151413121110 9 8
SchedEn(63:56)
Bit76543210
SchedEn(55:48)
SchedEn(63:48) Scheduler Enable
Each bit position enables/disables the respective Scheduler
(63..48):
1 Scheduler enabled
0 Scheduler disabled
CPU Accessibility : Read/Write
Reset Value: 0000H
Offset Address: USCEN4 ACHDSCEN4 C4H
Typical Usage: Written by CPU for global Scheduler configuration
Bit151413121110 9 8
SchedEn(79:72)
Bit76543210
SchedEn(71:64)
Prel. ABMP Data Sheet
Regi ster Desc ript ion
Preliminary Data Sheet 280 2001-14-01
PRELIMINARY
Register 89 USCEN5/DSCEN5
Upstream/Downstream Scheduler Enable 5 Registers
SchedEn(79:64) Scheduler Enable
Each bit position enables/disables the respective Scheduler
(79..64):
1 Scheduler enabled
0 Scheduler disabled
CPU Accessibility : Read/Write
Reset Value: 0000H
Offset Address: USCEN5 ADHDSCEN5 C5H
Typical Usage: Written by CPU for global Scheduler configuration
Bit151413121110 9 8
SchedEn(95:88)
Bit76543210
SchedEn(87:80)
SchedEn(95:80) Scheduler Enable
Each bit position enables/disables the respective Scheduler
(95..80):
1 Scheduler enabled
0 Scheduler disabled
Prel. ABMP Data Sheet
Regi ster Desc ript ion
Preliminary Data Sheet 281 2001-14-01
PRELIMINARY
Register 90 USCEN6/DSCEN6
Upstream/Downstream Scheduler Enable 6 Registers
Register 91 USCEN7/DSCEN7
Upstream/Downstream Scheduler Enable 7 Registers
CPU Accessibility : Read/Write
Reset Value: 0000H
Offset Address: USCEN6 AEHDSCEN6 C6H
Typical Usage: Written by CPU for global Scheduler configuration
Bit151413121110 9 8
SchedEn(111:104)
Bit76543210
SchedEn(103:96)
SchedEn
(111:96) Scheduler Enable
Each bit position enables/disables the respective Scheduler
(111..96):
1 Scheduler enabled
0 Scheduler disabled
CPU Accessibility : Read/Write
Reset Value: 0000H
Offset Address: USCEN7 AFHDSCEN7 C7H
Typical Usage: Written by CPU for global Scheduler configuration
Bit151413121110 9 8
SchedEn(127:120)
Bit76543210
SchedEn(119:112)
Prel. ABMP Data Sheet
Regi ster Desc ript ion
Preliminary Data Sheet 282 2001-14-01
PRELIMINARY
Register 92 UCRTRI/DCRTRI
Upstream/Downstream CRT Rate Integer Registers
SchedEn
(127:112) Scheduler Enable
Each bit position enables/disables the respective Scheduler
(127..112):
1 Scheduler enabled
0 Scheduler disabled
CPU Accessibility : Read/Write
Reset Value: 0000H
Offset Address: UCRTRI B0HDCRTRI C8H
Typical Usage: Written by CPU for global Scheduler configuration
Bit151413121110 9 8
Unused(5:0) CRTIntRate(9:8)
Bit76543210
CRTIntRate(7:0)
Prel. ABMP Data Sheet
Regi ster Desc ript ion
Preliminary Data Sheet 283 2001-14-01
PRELIMINARY
Register 93 UCRTRF/DCRTRF
Upstream/Downstream CRT Rate Fractional Registers
CRT IntRate(9:0) Integer part of CRT Queue R ate
The following formulars explain how the two parameters CRTIntRate and
CRTFracRate determine the CRT Queue output rate R via an auxiliary parameter T:
with:
• ABM core clock SYSCLK = [1/s]
• SDRAM RefreshPeriod = [s]
• SDRAM RefreshCycles requirement
CRTIntRate =
with
• int(T) is integer part of T
CRTFracRate =
Thus CRTIntRate and CRTFracRate can be calculated for a given rate R.
CPU Accessibility : Read/Write
Reset Value: 0000H
Offset Address: UCRTRF B1HDCRTRF C9H
Typical Usage: Written and Read by CPU
Bit151413121110 9 8
Init(7:0)
Bit76543210
CRTFracRate(7:0)
Tmax SYSCLK RefreshPeriod×
32 RefreshCycles×
--------------------------------------------------------------------------8()=
int T()
ceil T int T()–{}256×
Prel. ABMP Data Sheet
Regi ster Desc ript ion
Preliminary Data Sheet 284 2001-14-01
PRELIMINARY
Init(7:0) Scheduler Initialization Value
This bit-field must be written to 00H at the time of Scheduler
configuration/initialization and should not be written during normal
operation.
CRTFracRate
(7:0) CRT Fractional Rate
This value determine s the fractional par t of the CR T Queue output
rate.
The following formulars explain how the two parameters CRTIntRate and CRTFrac-
Rate determine the scheduler output rate R via an auxiliary parameter T:
T = [without dimension]
with
• ABM core clock, [SYSCLK} = 1/s
• Sc heduler output rate, [R] = cells/s
CRTIntRate =
with
• int(T) is integer part of T
CRTFracRate =
Thus CRTIntRate and CRTFracRate can be calculated for a given CRT Queue output
rate R.
SYSCLK
32 cells 1–R×
------------------------------------
int T()
TintT()–{}256 1+×
Prel. ABMP Data Sheet
Regi ster Desc ript ion
Preliminary Data Sheet 285 2001-14-01
PRELIMINARY
Internal Table 12: ABR/VBR Table Transfer Registers
ABR/VBR Context Table Transfer Registers are used to access the ABR/VBR Context
Table (AVT) containing 1024 context entries. Each context entry consists of 8*32 bit
words.
Table 7-29 provides an overview of the registers involved. Each AVT word consists of
32 bit.
ERCT0 and ERCT1 are the transfer registers for one 32-bit word of the AVT table.
Access to words are controlled by mask registers ERCM0/ERCM1.
The context entry number and the corresponding word number representing the table
word which need s to be Read or modified mu st be written to the Word Address Register
(WAR). The dedicated AVT table word is Read into the ERCT0/ERCT1 transfer registers
or modified by the ERCT0/ERCT1 transfer register values with a Read-Modify-Write
mechanism. The associated mask registers ERCM0 and ERCM1 allow a bit-by-bit
selection between Read (1) and Write (0) operation. In case of Read operation, the
dedicated ERCT0/ERCT1 register bit will be overwritten by the respective AVT table
entry bit value. In case of Write operation, the dedicated ERCT0/ERCT1 register bit will
modify the respective AVT table entry bit value.
The Read-Modify-Write process is controlled by the Memory Address Register (MAR).
The 5 LSBs (= Bit 4..0) of the MAR register select the memory/table that will be
accessed; to select the AVT table bit field MAR(4:0) must be set to 08H.
Table 7-29 Registers for AVT Table Access
31 0
AVT RAM word RAM Select:
15 0 15 0 15 0
ERCT1 ERCT0 MAR=08H
Entry Select:
15 0 15 0 15 0
ERCM1 ERCM0 WAR:
EntrySel(9:0) = (0..1023D)
WordSel(2:0) = (0..7D)
Prel. ABMP Data Sheet
Regi ster Desc ript ion
Preliminary Data Sheet 286 2001-14-01
PRELIMINARY
Bit 5 of MAR starts the transfer and is cleared au tomatically after execution of the Read-
Modify-Write pro ce ss.
Table 7-30 WAR Register Mapping for AVT Table Access
Register 94 ERCT0
AVT Table Transfer Register 0
Bit151413121110 9 8
Unused(2:0) EntrySel(9:5)
Bit76543210
EntrySel(4:0) WordSel(2:0)
EntrySel(9:0) Selects one of the 1024 AVT table context entries.
WordSel(2:0) Selects one of the 8 DWORDs per AVT table context entries.
CPU Accessibility : Read/Write
Reset Value: 0000H
Offset Address: ERCT0 CAH
Typical Usage: Written and Read by CPU
Bit151413121110 9 8
Word0(15:8)
Bit76543210
Word0(7:0)
Prel. ABMP Data Sheet
Regi ster Desc ript ion
Preliminary Data Sheet 287 2001-14-01
PRELIMINARY
Register 95 ERCT1
AVT Table Transfer Register 1
Word0(15:0) The meaning of the ’Word0’ depends on
1. The selected context entry word (WordSel(2:0))
2. The mode of this particular context entry
For detailed description of the context en try fields refer to “AVT
Context RAM Organization and Addressing” on Page 93 f.
CPU Accessibility : Read/Write
Reset Value: 0000H
Offset Address: ERCT1 CBH
Typical Usage: Written and Read by CPU
Bit151413121110 9 8
Word1(31:24)
Bit76543210
Word1(23:16)
Word1(31:16) The meaning of the ’Word1’ depends on
1. The selected context entry word (WordSel(2:0))
2. The mode of this particular context entry
For detailed description of the context en try fields refer to ???)
Prel. ABMP Data Sheet
Regi ster Desc ript ion
Preliminary Data Sheet 288 2001-14-01
PRELIMINARY
Register 96 ERCM0
AVT Table Access Mask Register 0
CPU Accessibility : Read/Write
Reset Value: 0000H
Offset Address: ERCM0 CCH
Typical Usage: Written by CPU to control internal table Read/Write
access
Bit151413121110 9 8
ERCM0(15:8)
Bit76543210
ERCM0(7:0)
ERCM0(15:0) ERC Mask Register 0
ERC Mask Registers 0..1 control the Read-Modify-Write access
from transfe r registers ERCT0 and ERCT1 to th e internal AVT table
on a per-bit selection basis. The mask register bit positions
correspond to the respect ive transfer registers ERCT0 and ERCT1:
0 The dedicated bit of the transfer register is
not
overwritten by the corresponding table entry bit during
Read; but overwrites the table entry bit during the
Modify-Write process.
This is a Write access to the internal table entry.
1 The dedicated bit of the transfer register is overwritten
by the corresponding tab le entry bit dur ing Read and is
written back to the table entry bit during Modify-Write.
This is a Read access to the internal table entry.
Prel. ABMP Data Sheet
Regi ster Desc ript ion
Preliminary Data Sheet 289 2001-14-01
PRELIMINARY
Register 97 ERCM1
AVT Table Access Mask Register 1
CPU Accessibility : Read/Write
Reset Value: 0000H
Offset Address: ERCM0 CDH
Typical Usage: Written by CPU to control internal table Read/Write
access
Bit151413121110 9 8
ERCM1(31:24)
Bit76543210
ERCM1(23:16)
ERCM1(31:16) ERC Mask Register 1
ERC Mask Registers 0..1 control the Read-Modify-Write access
from transfe r registers ERCT0 and ERCT1 to th e internal AVT table
on a per-bit selection basis. The mask register bit positions
correspond to the respect ive transfer registers ERCT0 and ERCT1:
0 The dedicated bit of the transfer register is
not
overwritten by the corresponding table entry bit during
Read; but overwrites the table entry bit during the
Modify-Write process.
This is a Write access to the internal table entry.
1 The dedicated bit of the transfer register is overwritten
by the corresponding tab le entry bit dur ing Read and is
written back to the table entry bit during Modify-Write.
This is a Read access to the internal table entry.
Prel. ABMP Data Sheet
Regi ster Desc ript ion
Preliminary Data Sheet 290 2001-14-01
PRELIMINARY
Register 98 ERCMB0
ERC MailBox Register 0
CPU Accessibility : Read/Write
Reset Value: 0000H
Offset Address: ERCMB0 D2H
Typical Usage: Written and Read by CPU
Bit151413121110 9 8
Bit765432 1 0
Prel. ABMP Data Sheet
Regi ster Desc ript ion
Preliminary Data Sheet 291 2001-14-01
PRELIMINARY
Register 99 ERCMB1
ERC MailBox Register 1
CPU Accessibility : Read/Write
Reset Value: 0000H
Offset Address: ERCMB1 D3H
Typical Usage: Written and Read by CPU
Bit151413121110 9 8
Bit765432 1 0
Prel. ABMP Data Sheet
Regi ster Desc ript ion
Preliminary Data Sheet 292 2001-14-01
PRELIMINARY
Register 100 ERCMB2
ERC MailBox Register 2
CPU Accessibility : Read/Write
Reset Value: 0000H
Offset Address: ERCMB2 D4H
Typical Usage: Written and Read by CPU
Bit151413121110 9 8
Bit765432 1 0
Prel. ABMP Data Sheet
Regi ster Desc ript ion
Preliminary Data Sheet 293 2001-14-01
PRELIMINARY
Register 101 ERCCONF0
ERC Configuration Register 0
CPU Accessibility : Read/Write
Reset Value: 0000H
Offset Address: ERCCONF0 D5H
Typical Usage: Written and Read by CPU
Bit151413121110 9 8
FWDF unused(3:0) QIDFR QIDFE SCAND
Bit765432 1 0
VBRFW SCANP(6:0)
FWDF Firmware Downlo ad Finished
0
1
QIDFR QID Filter RM FIFO
0 QID Filter for RM FIFO enabled
1 QID Filter for RM FIFO disabled (Bypass)
Note:
QIDFE QID Filter EMIT FIFO
0 QID Filter for EMIT FIFO enabled
1 QID Filter for EMIT FIFO disabled (Bypass)
Note:
SCAND SCAN Disa ble
Prel. ABMP Data Sheet
Regi ster Desc ript ion
Preliminary Data Sheet 294 2001-14-01
PRELIMINARY
Register 102 ERCCONF1
ERC Configuration Register 1
0
1
VBRFW VBR Firmware Mode
0
1
SCANP(6:0) SCAN Period
0
1
CPU Accessibility : Read/Write
Reset Value: 000AH
Offset Address: ERCCONF1 D6H
Typical Usage: Written and Read by CPU
Bit151413121110 9 8
unused(11:4)
Bit765432 1 0
unused(3:0) TRM(3:0)
Prel. ABMP Data Sheet
Regi ster Desc ript ion
Preliminary Data Sheet 295 2001-14-01
PRELIMINARY
TRM(3:0) ABR TRM Parameter
Global for all connections.
The bit-field TRM(3:0) determines a 10ms counter:
Tout := TRM(3:0) * 10ms
The default (reset) value is 000AH which equals to 100ms.
Prel. ABMP Data Sheet
Regi ster Desc ript ion
Preliminary Data Sheet 296 2001-14-01
PRELIMINARY
Register 103 PLL1CONF
PLL1 Configuration Register
CPU Accessibility : Read/Write
Reset Value: 0000H
Offset Address: PLL1CONF D7H
Typical Usage: Written and Read by CPU
Bit151413121110 9 8
Locked1 Dev2En1 Dev1En1 BYPASS1 PU1 RES1 M1(3:2)
Bit765432 1 0
M1(1:0) N1(5:0)
DPLL1 generates a clock that is an alternative clock source for the ABMP. The DPLL1
is feeded by clock input signal ‘SYSCLK’. Signal ‘SYSCLKSEL’ determines the clock
source of the ABMP.
LOCKED1 DPLL1 Locked
(read only)
1 DPLL1 is locked based on the current parameter
setting.
0 DPLL1 is in transient status.
DEV2EN1 Devision Factor 2 Enable for DPLL1
This bit enables one of the additional devide by 2 factors
subsequent to the DPLL1 output.
0 Devision Factor 2 disabled.
1 Devision Factor 2 enabled.
DEV1EN1 Devision Factor 1 Enable for DPLL1
This bit enables one of the additional devide by 2 factors
subsequent to the DPLL1 output.
0 Devision Factor 1 disabled.
1 Devision Factor 1 enabled.
Prel. ABMP Data Sheet
Regi ster Desc ript ion
Preliminary Data Sheet 297 2001-14-01
PRELIMINARY
BYPASS1 DPL L1 Bypass
Switching between bypass and non-bypass mode is glitch-free with
respect to the internal clock output. The DPLL1 is bypassed after
power-on reset and can be switched to non-bypass mode by
software during device configuration.
0 DPLL1 is internally bypassed,
i.e. DPLL1 clock in put connected to DPLL1 clock outp ut
1 DPLL1 is not bypassed,
i.e. DPLL1 clock output is generated by DPLL1
depending on its parameter configuration
PU1 Power Up DPLL1
0 DPLL1 is in power-down mode.
(The analog part of DPLL1 is switched-off for power
saving.)
1 DPLL1 is in power on (operational) mode.
RES1 Reset DPLL1
0 DPLL1 is in operational mode.
1 DPLL1 is in reset mode.
Note: The result of reset mode is identical to bypass
mode, but switching betw een reset and non-reset
status is not g litch-fre e with respect to the i nternal
clock output.
M1(3:0) M1 Parameter of DPLL 1
This parameter deter mines the fir st stage division factor of DPL L1.
The effective division factor is (M1 + 1) in the range 1..16.
N1(5:0) N1 P arameter of DPLL1
This parameter determines the second stage multiplication factor of
DPLL1. The effective multiplication factor is (N1 + 1) in the range
1..64.
Prel. ABMP Data Sheet
Regi ster Desc ript ion
Preliminary Data Sheet 298 2001-14-01
PRELIMINARY
Register 104 PLL2CONF
PLL2 Configuration Register
CPU Accessibility : Read/Write
Reset Value: 0000H
Offset Address: PLL2CONF D8H
Typical Usage: Written and Read by CPU
Bit151413121110 9 8
Locked2 Dev1En2 BYPASS2 PU2 RES2 M2(3:2)
Bit765432 1 0
M2(1:0) N2(5:0)
DPLL2 generates a clock that is an alternative clock source for the ERC unit. The
DPLL2 is feeded by clock input signal ‘SYSCLK’. Signal ‘IOPCLKSEL’ determines the
clock source of the ERC unit.
LOCKED2 DPLL2 Locked
(read only)
1 DPLL2 is locked based on the current parameter
setting.
0 DPLL2 is in transient status.
DEV1EN2 Devision Factor 1 Enable for DPLL2
This bit enables the add itional devide by 2 factor sub sequent to the
DPLL2 output.
0 Devision Factor 1 disabled.
1 Devision Factor 1 enabled.
BYPASS2 DPL L2 Bypass
Switching between bypass and non-bypass mode is glitch-free with
respect to the internal clock output. The DPLL2 is bypassed after
power-on reset and can be switched to non-bypass mode by
software during device configuration.
Prel. ABMP Data Sheet
Regi ster Desc ript ion
Preliminary Data Sheet 299 2001-14-01
PRELIMINARY
0 DPLL2 is internally bypassed,
i.e. DPLL2 clock in put connected to DPLL2 clock outp ut
1 DPLL2 is not bypassed,
i.e. DPLL2 clock output is generated by DPLL2
depending on its parameter configuration
PU2 Power Up DPLL2
0 DPLL2 is in power-down mode.
(The analog part of DPLL2 is switched-off for power
saving.)
1 DPLL2 is in power on (operational) mode.
RES2 Reset DPLL2
0 DPLL2 is in operational mode.
1 DPLL2 is in reset mode.
Note: The result of reset mode is identical to bypass
mode, but switching betw een reset and non-reset
status is not g litch-fre e with respect to the i nternal
clock output.
M2(3:0) M2 Parameter of DPLL 2
This parameter deter mines the fir st stage division factor of DPL L2.
The effective division factor is (M2 + 1) in the range 1..16.
N2(5:0) N2 P arameter of DPLL2
This parameter determines the second stage multiplication factor of
DPLL2. The effective multiplication factor is (N2 + 1) in the range
1..64.
Prel. ABMP Data Sheet
Regi ster Desc ript ion
Preliminary Data Sheet 300 2001-14-01
PRELIMINARY
Register 105 PLLTST
PLL Test Register
CPU Accessibility : Read/Write
Reset Value: 0000H
Offset Address: PLLTST D9H
Typical Usage: Written and Read by CPU
Bit151413121110 9 8
Bit765432 1 0
Prel. ABMP Data Sheet
Regi ster Desc ript ion
Preliminary Data Sheet 301 2001-14-01
PRELIMINARY
Register 106 ERCRAC
ERC Register Access Control Register
CPU Accessibility : Read/Write
Reset Value: 0000H
Offset Address: ERCRAC DAH
Typical Usage: Written and Read by CPU
Bit151413121110 9 8
unused(8:1)
Bit765432 1 0
unused0 ERCACF IUPAC ERCRTAC IERCAC UPRTAC ERCRD ERCWR
ERCWR ERC Write Access
0
1
ERCRD ERC Read Access
0
1
UPRTAC UP RAM Transfer Access
0
1
IERCRAC Inhibit ERC Register Access
0
1
ERCRTAC ERC RAM Transfer Access
0
Prel. ABMP Data Sheet
Regi ster Desc ript ion
Preliminary Data Sheet 302 2001-14-01
PRELIMINARY
1
IUPRAC Inhibit UP Register Access
0
1
ERCACF ERC Access Free
0
1
Prel. ABMP Data Sheet
Regi ster Desc ript ion
Preliminary Data Sheet 303 2001-14-01
PRELIMINARY
Register 107 ERCRAM
ERC Register Access Mask Register
CPU Accessibility : Read/Write
Reset Value: 0000H
Offset Address: ERCRAM DBH
Typical Usage: Written and Read by CPU
Bit151413121110 9 8
MASK(15:8)
Bit765432 1 0
MASK(7:0)
Prel. ABMP Data Sheet
Regi ster Desc ript ion
Preliminary Data Sheet 304 2001-14-01
PRELIMINARY
Register 108 VERL
Version Number Low Register
•
Register 109 VERH
Version Number High Register
CPU Accessibility: Read
Reset Value: F083H
Offset Address: VERL E1H
Typical Usage: Read by CPU to determine device version number
Bit151413121110 9 8
VERL(15..8)
Bit76543210
VERL(7..0)
VERL(15..0) F083H
CPU Accessibility : Read
Reset Value: 1007H
Offset Address: VERH E2H
Typical Usage: Read by CPU to determine device version number
Bit151413121110 9 8
VERH(15..8)
Bit76543210
VERH(7..0)
VERH(15..0) 1007H
Prel. ABMP Data Sheet
Regi ster Desc ript ion
Preliminary Data Sheet 305 2001-14-01
PRELIMINARY
Register 110 ISRU
Interrupt Status Register Upstream
CPU Accessibility : Read/Write
Reset Value: 0000H
Offset Address: ISRU E3H
Typical Usage: Read by CPU to evaluate interrupt events related to the
upstream core. Int errupt indications must be cleare d by writing
a 1 to the respective bit locations; writing a 0 has no effect;
Bit151413121110 9 8
Unused BCFGE QIDINV BUFER
1LCI
INVAL PARITY
ER SOCER BUFER
2
Bit76543210
BUFER
3CDVOV MUXOV AAL5
COL RMCER BIP8ER BUFER
5VCRM
ER
BCFGE Buffer Configuration Error
QIDINV This interrupt is generated if the ABM tries to write a cell into a
disabled queue. The cell is discarded in this case.
(Typically occurs on queue configuration errors.)
BUFER1 Unexpected buffer error number 1. Should never occur in normal
operation. Immediate reset of the chip recommended.
LCIINVAL Cell with invalid LCI received, that is, a LCI value > 16383.
The cell is discarded.
PARITYER Parity error at UTOPIA recei ve upstream (PH Y) Interface detecte d.
SOCER Start of Cell Error at UTOPIA receive upstream (PHY) Interface
detected.
Prel. ABMP Data Sheet
Regi ster Desc ript ion
Preliminary Data Sheet 306 2001-14-01
PRELIMINARY
BUFER2 Unexpected Buffer Error number 2. Should never occur in normal
operation. Immediate reset of the chip is recommended.
BUFER3 Unexpected Buffer Error number 3. Should never occur in normal
operation. Immediate reset of the chip is recommended.
CDVOV The maximum upstream CDV value for shaped connections given
in CDVU register has been exceeded. This interrupt is a notification
only; that is, no cells are discarded due to this event.
MUXOV Indicates that a Scheduler lost a serving time slot. (Can indicate a
static backpressure on one port).
The ’MUXOV’ interrupt is generated when the number of lost
serving time slots exceeds the number specified in bit field
MaxBurstS(3:0) (see register UECRI/DECRI).
No further action is required upon this interrupt.
AAL5COL Indicates that an interrupt event occured in the upstream AAL5 unit.
The interrupt reason must be read from the AAL5 status register
“UA5SARS/DA5SARS” on Page 167 (upstream).
BUFER4/
CNTUF Indicates that a scheduler specific counter for ’unused cell cycles’
has falsely been set to its maximum value by device logic
(maximum value is determined by parameter MaxBurstS(3:0)
programmed in register UECRI/DECRI).
This can occur when either the scheduler rate or the UTOPIA port
number are changed during operation without disabling the
scheduler.
As a consequence a burst of up to MaxBurstS(3:0) cells can be sent
out that is not justified by previously saved cell cycles.
No cells are discarded due to this event and no further action is
required upon this interrupt.
RMCER ABR RM Cell received with corrupted CRC-10.
Prel. ABMP Data Sheet
Regi ster Desc ript ion
Preliminary Data Sheet 307 2001-14-01
PRELIMINARY
BIP8ER BIP-8 error detected when reading a cell from the upstream external
SDRAM. BIP-8 protects the cell header of each cell. The cell is
discarded. One single sporadic event can be ignored. Hardware
should be taken out of service when the error rate exceeds 10-10.
BUFER5 Unexpected Buffer Error number 5. Should never occur in normal
operation. Immediate reset of the chip recommended.
For consistency check the ABMP stores the queue ID with each cell
written to the respective queue within the cell storage RAM. When
reading a cell from the cell storage RAM, the queue ID is compared
to the stored queue ID.
A queue ID mismatch would indicate a global buffering/pointer
problem.
VCRMER VC RM Cell received erroneously when traffic class is configured for
ABR VPs using bit ABRvp in Register TCT1
(see Register 40: TCT1).
Note: Several mechanisms are implemented in the ABM to check for consistency of
pointer operation and internal/external memory control. The interrupt events
BUFFER1..BUFFER5 indicate errors detected by these mechanisms.
It is recommended that these interrupts be classified as "fatal device errors."
Prel. ABMP Data Sheet
Regi ster Desc ript ion
Preliminary Data Sheet 308 2001-14-01
PRELIMINARY
Register 111 ISRD
Interrupt Status Register Downstream
CPU Accessibility : Read/Write
Reset Value: 0000H
Offset Address: ISRD E4H
Typical Usage: Read by CPU to eva luate interrupt events re lated to the
upstream core. Interru pt indications must be cleared by
writing a 1 to th e respective bit locations; writ ing a 0 has
no effect;
Bit151413121110 9 8
Unused(1:0) QIDINV BUFER
1LCI
INVAL PARITY
ER SOCER BUFER
2
Bit76543210
BUFER
3CDVOV MUXOV AAL5
COL RMCER BIP8ER BUFER
5VCRM
ER
QIDINV This interrupt is generated if the ABM tries to Write a cell into a
disabled queue. The cell is discarded.
(Typically occurs on queue configuration errors.)
BUFER1 Unexpected Buffer Error number 1. Should never occur in normal
operation. Immediate reset of the chip is recommended.
LCIINVAL Cell with invalid LCI received, i.e. a LCI value >16383. The cell is
discarded.
PARITYER Parity Error at UTOPIA receive downstream (PHY) interface
detected.
SOCER Start of Cell Error at UTOPIA receive downstream (PHY) interface
detected.
Prel. ABMP Data Sheet
Regi ster Desc ript ion
Preliminary Data Sheet 309 2001-14-01
PRELIMINARY
BUFER2 Unexpected Buffer Error number 2. Should never occur in normal
operation. Immediate reset of the chip is recommended.
BUFER3 Unexpected Buffer Error number 3. Should never occur in normal
operation. Immediate reset of the chip recommended.
CDVOV The maximum downstream CDV value for shaped connections
given in CDVU register has been exceeded.
This interrupt is a notification only; that is, no cells are discarded
due to this event.
MUXOV Indicates that a Scheduler lost a serving time slot. (Can indicate a
static backpressure on one port).
The ’MUXOV’ interrupt is generated when the number of lost
serving time slots exceeds the number specified in bit field
MaxBurstS(3:0) (see register UECRI/DECRI).
No further action is required upon this interrupt.
AAL5COL Indicates that an interrupt event occured in the downstream AAL5
unit. The interrupt reason must be read from the AAL5 status
register “UA5SARS/DA5SARS” on Page 167 (downstream).
BUFER4/
CNTUF Indicates that a scheduler specific counter for ’unused cell cycles’
has falsely been set to its maximum value by device logic
(maximum value is determined by parameter MaxBurstS(3:0)
programmed in register UECRI/DECRI).
This can occur when either the scheduler rate or the UTOPIA port
number are changed during operation without disabling the
scheduler.
As a consequence a burst of up to MaxBurstS(3:0) cells can be sent
out that is not justified by previously saved cell cycles.
No cells are discarded due to this event and no further action is
required upon this interrupt.
RMCER ABR RM cell received with corrupted CRC-10.
Prel. ABMP Data Sheet
Regi ster Desc ript ion
Preliminary Data Sheet 310 2001-14-01
PRELIMINARY
BIP8ER BIP-8 error detected when reading a cell from the downstream
external SDRAM. BIP-8 protects the cell header of each cell. The
cell is discarded. One single sporadic event can be ignored.
Hardware should be taken out of service when the error rate
exceeds 10-10.
BUFER5 Unexpected Buffer Error number 5. Should never occur in normal
operation. Immediate reset of the chip is recommended.
For consistency check the ABMP stores the queue ID with each cell
written to the respective queue within the cell storage RAM. When
reading a cell from the cell storage RAM, the queue ID is compared
to the stored queue ID.
A queue ID mismatch would indicate a global buffering/pointer
problem.
VCRMER VC RM Cell received erroneously, when traffic class is configured
for ABR VPs using bit ABRvp TCT1(see Register 40: TCT1).
Note: Several mechanisms are implemented in the ABM to check for consistency of
pointer operation and internal/external memory control. The interrupt events
BUFFER1..BUFFER5 indicate errors detected by these mechanisms.
It is recommended that these interrupts be classified as "fatal device errors."
Prel. ABMP Data Sheet
Regi ster Desc ript ion
Preliminary Data Sheet 311 2001-14-01
PRELIMINARY
Register 112 ISRC
Interrupt Status Register Common
CPU Accessibility : Read/Write
Reset Value: 0000H
Offset Address: ISRC E5H
Typical Usage: Read by CPU to evaluate interrupt events related to both
cores. Interrupt i ndications must be cleared b y writing a
1 to the re spective bit locations; writing a 0 has no effect;
Bit151413121110 9 8
Unused(10:3)
Bit76543210
Unused(2:0) RAMER DDQRD UDQRD DQ
VCMGD UQ
VCMGD
RAMER Configuration of common Cell Pointer RAM has been changed after
cells have been received (see Register MODE1, bit field CPR).
DDQRD Downstream Dummy Queue Relogged/Deactivated
This interrupt confirms the dummy queue operation being
deactivated.
UDQRD Upstream Dummy Queue Relogged/Deactivated
This interrupt confirms the dummy queue operation being
deactivated.
DQVCMGD Downstream Queue VC-Merge Group Deactivated
This interrupt confirms the VC-Merge group being deactivated.
UQVCMGD Upstream Queue VC-Merge Group Deactivated
This interrupt confirms the VC-Merge group being deactivated.
Prel. ABMP Data Sheet
Regi ster Desc ript ion
Preliminary Data Sheet 312 2001-14-01
PRELIMINARY
Register 113 IMRU
Interrupt Mask Register Upstream
CPU Accessibility : Read/Write
Reset Value: 0000H
Offset Address: IMRU E6H
Typical Usage: Written by CPU to control interrupt signal effective
events
Bit151413121110 9 8
IMRU(15:8)
Bit76543210
IMRU(7:0)
IMRU(15:0) Interrupt Mask Upstream
Each bit controls whether the corresponding interrupt indication in
register ISRU (same bit location) activates the interrupt signal:
1 Interrupt indication masked.
The interrupt signal is not activated upon this event.
0 Interrupt indication unmasked.
The interrupt signal is activated upon this event.
Prel. ABMP Data Sheet
Regi ster Desc ript ion
Preliminary Data Sheet 313 2001-14-01
PRELIMINARY
Register 114 IMRD
Interrupt Mask Register Downstream
CPU Accessibility : Read/Write
Reset Value: 0000H
Offset Address: IMRD E7H
Typical Usage: Written by CPU to control interrupt signal effective
events
Bit151413121110 9 8
IMRD(15:8)
Bit76543210
IMRD(7:0)
IMRD(15:0) Interrupt Mask Downstream
Each bit controls whether the corresponding interrupt indication in
register ISRD (same bit location) activates the interrupt signal:
1 Interrupt indication masked.
The interrupt signal is not activated upon this event.
0 Interrupt indication unmasked.
The interrupt signal is activated upon this event.
Prel. ABMP Data Sheet
Regi ster Desc ript ion
Preliminary Data Sheet 314 2001-14-01
PRELIMINARY
Register 115 IMRC
Interrupt Mask Register Common
CPU Accessibility : Read/Write
Reset Value: 0000H
Offset Address: IMRC E8H
Typical Usage: Written by CPU to control interrupt signal effective
events
Bit151413121110 9 8
IMRC(15:8)
Bit76543210
IMRC(7:0)
IMRU(15:0) Interrupt Mask Upstream
Each bit controls whether the corresponding interrupt indication in
register ISRU (same bit location) activates the interrupt signal:
1 Interrupt indication masked.
The interrupt signal is not activated upon this event.
0 Interrupt indication unmasked.
The interrupt signal is activated upon this event.
Prel. ABMP Data Sheet
Regi ster Desc ript ion
Preliminary Data Sheet 315 2001-14-01
PRELIMINARY
Register 116 ISRDBA
Interrupt Status Register DBA
CPU Accessibility : Read/Write
Reset Value: 0000H
Offset Address: ISRDBA E9H
Typical Usage: Read by CPU to evaluate interrupt events related to both
cores. Interrupt i ndications must be cleared b y writing a
1 to the re spective bit locations; writing a 0 has no effect;
Bit151413121110 9 8
DBATC(15:8)
Bit76543210
DBATC(7:0)
DBATC(15:0) Each bit position indicates that a DBA Threshold Crossing Event
occured in the respective Register i (i=15..0).
Prel. ABMP Data Sheet
Regi ster Desc ript ion
Preliminary Data Sheet 316 2001-14-01
PRELIMINARY
Register 117 IMRDBA
Interrupt Mask Register DBA
CPU Accessibility : Read/Write
Reset Value: 0000H
Offset Address: IMRDBA EAH
Typical Usage: Written by CPU to control interrupt signal effective
events
Bit151413121110 9 8
IMRDBA(15:8)
Bit76543210
IMRDBA(7:0)
IMRDBA(15:0) Interrupt Mask Upstream
Each bit controls whether the corresponding interrupt indication in
register ISRDBA (same bit location) activates the interrupt signal:
1 Interrupt indication masked.
The interrupt signal is not activated upon this event.
0 Interrupt indication unmasked.
The interrupt signal is activated upon this event.
Prel. ABMP Data Sheet
Regi ster Desc ript ion
Preliminary Data Sheet 317 2001-14-01
PRELIMINARY
Register 118 MAR
Memory Address Register
CPU Accessibility : Read/Write
Reset Value: 0000H
Offset Address: MAR EBH
Typical Usage: Written by CPU to address internal RAMs/tables for
Read-Modify-Write operation via transfer registers
Bit151413121110 9 8
Unused(9:2)
Bit76543210
Unused(1:0) Start MAR(4:0)
Start This command bit starts the Read-Modify-Write procedure to the
internal RAM/table addressed by bit-field MAR(4:0). The specific
data transfer and mask registers must be prepar ed appropriately in
advance.
This bit is automatically cleared after completion of the Read-
Modify-Write procedure.
MAR(4:0) Memory Address
This bit-field selects one of the internal RAMs/tables for Read-
Modify-Write operation:
00000 LCI: LCI Table RAM (see page 199)
00001 TCT: Traffic Class Table (see page 203)
00010 QCT: Queue Configuration Table (see page 219)
00011 SOT: Scheduler Occupation Table (see page 230)
00101 DTC: DBA Threshold Crossing Table (see page 196)
00111 MGT: Merge Group Table (see page 235)
01000 QCI: Qeue C onge sti on Indi cation Tabl e ( se e page 243)
01010 AVT: ABR/VBR Table (see page 285)
10000 QPT1 Upstream:
Queue Parameter Table 1 Up (see page 253)
Prel. ABMP Data Sheet
Regi ster Desc ript ion
Preliminary Data Sheet 318 2001-14-01
PRELIMINARY
10001 QPT2 Upstream:
Queue Parameter Table 2 Up (see page 257)
11000 QPT1 Downstream:
Queue Parameter Table 1 Dn (see page 253)
11001 QPT2 Downstream:
Queue Parameter Table 2 Dn (see page 257)
10111 SCTF Upstream:
Scheduler Configuration Table Fractional Part
(see page 262)
11111 SCTF Downstream:
Scheduler Configuration Table Fractional Part
(see page 274)
Note: The SCTI Table (Scheduler Configuratio n Table Integer Part)
is addressed via dedicated address registers and thus not
listed in bit-field MAR(4:0)
(see page 263)
.
Note: MAR(4:0) values not listed above are invalid and reserved. It is recommended to
not use invalid/reserved values.
Prel. ABMP Data Sheet
Regi ster Desc ript ion
Preliminary Data Sheet 319 2001-14-01
PRELIMINARY
Register 119 WAR
Word Address Register
CPU Accessibility : Read/Write
Reset Value: 0000H
Offset Address: WAR ECH
Typical Usage: Written by CPU to address entries of internal RAMs/
tables for Read-Modify-Write operation via transfer
registers.
Bit151413121110 9 8
WAR(15:8)
Bit76543210
WAR(7:0)
WAR(15:0) Word Address
This bit-field selects an entry within the internal RAM/table selected
by the MAR reegister.
In general, it can address up to 64K entries.
The current range of supported values depends on the size and
organization of the selected RAM/table.
Thus, the specific WAR register meaning is listed in the overview
part of each internal RAM/table description:
LCI LCI Table RAM (see page 199)
TCT Traffic Class Table (see page 203)
QCT Queue Configuration Table (see page 230)
SOT Scheduler Occupation Table (see page 230)
QPTHU QPT High Word Upstream:
Queue Parameter Table (see page 253f.)
QPTHD QPT High Word Downstream:
Queue Parameter Table (see page 253f.)
QPTLU QPT Low Word Upstream:
Queue Parameter Table( see page 253)
QPTLD QPT Low Word Downstream:
Queue Parameter Table (see page 253)
Prel. ABMP Data Sheet
Regi ster Desc ript ion
Preliminary Data Sheet 320 2001-14-01
PRELIMINARY
Register 120 STATUS
ABM STATUS Register
SCTFU SCTF Upstream:
Scheduler Configuration Table Fractional Part
(see page 274)
SCTFD SCTF Downstre am:
Scheduler Configuration Table Fractional Part
(see page 274)
Note: The SCTI Table (Scheduler Configuratio n Table Integer Part)
is addressed via dedicated address registers and, thus, is not
listed in the MAR and WAR registers
(see page 262)
.
CPU Accessibility : Read/Write
Reset Value: 0000H
Offset Address: STATUS EDH
Typical Usage: Read by CPU
Bit1514131211109 8
unused DUTFL(6:0)
Bit 7 6 5 4 3 2 1 0
unused UUTFL(6:0)
DUTFL(6:0) Downstream UTOPIA Transmit Buffer Fill Level
This bit-field indicates the current number of cells stored in the
UTOPIA transmit buffers (0..96 cells). A high fill level indicates a
global ba ckpressure situ ation. Si nce the UTOPIA tr ansmit buff er is
shared by all enabled UTOPIA ports, DUTFL and UUTFL do not
indicate backpressure on particular ports only.
Prel. ABMP Data Sheet
Regi ster Desc ript ion
Preliminary Data Sheet 321 2001-14-01
PRELIMINARY
Register 121 MODE1
ABM Mode 1 Register
UUTFL(6:0) Upstream UTOPIA Transmit Buffer Fill Level
This bit-field indicates the current number of cells stored in the
UTOPIA transmit buffer (0..96 cells). A high fill level indicates a
global ba ckpressure situ ation. Si nce the UTOPIA tr ansmit buff er is
shared by all enabled UTOPIA ports, DUTFL and UUTFL do not
indicate backpressure on particular ports only.
CPU Accessibility : Read/Write
Reset Value: 0000H
Offset Address: MODE1 EEH
Typical Usage: Written and Read by CPU
Bit1514131211109 8
SWRES ERC
SWRES CPR(1:0) VC
MERGE INIT
RAM INIT
SDRAM CORE
Bit 7 6 5 4 3 2 1 0
WGS BIN EFCI BIP8 CRC10 LCItog LCIMOD(1:0)
SWRES Software Reset (clears automatically after four cycles).
This bit is automatically cleared after execution.
’SWRES’ controls reset of all ABMP units excluding the ERC unit.
1 Starts internal reset procedure
(0) self-clearing
Prel. ABMP Data Sheet
Regi ster Desc ript ion
Preliminary Data Sheet 322 2001-14-01
PRELIMINARY
ERCSWRES ABR/VBR Software Reset (not self-clearing).
’ERCSWRES’ controls reset of the ERC unit.
1 Starts internal reset pr ocedure and keeps the ER C unit
in reset state.
0 Releases the ERC unit from reset state to operational
state.
CPR(1:0) Cell Pointer Ram Size configuration
(see also Table 5-4 "External RA Ms" on Page 68)
00 256k pointer entries per direction
(corresponds to 256k cells in each cell storage RAM)
01 128k pointer entries per direction
(corresponds to 128k cells in each cell storage RAM)
10 64k pointer entries per direction
(corresponds to 64k cells in each cell storage RAM)
11 reserved
Note: The Cell Pointer RAM Size should be programmed during
initialization and should not be changed during operation.
VCMerge VC Merge Enable
This bit enables VC-Merge operation on a global basis. It
determines the usage (required width) of the Cell Pointer RAM,
since VC-Merge ope rati on requi r es one additi ona l fl ag ‘ EOP Mark’
in the C PR.
(see also Table 5-10 "Cell Pointer RAM Width" on Page 131)
0 VC-Merge operation disabled.
1 VC-Merge operation enabled.
INITRAM Init RAMs
Start of Initialization of the internal RAMs.
This bit is automatically cleared after execution.
1 Starts internal RAMs initialization procedure.
Note: The internal RAM initialization process can be
activated only once after hardware reset.
(0) self-clearing
Prel. ABMP Data Sheet
Regi ster Desc ript ion
Preliminary Data Sheet 323 2001-14-01
PRELIMINARY
INITSDRAM Init SDRAMs
Initialization and configuration of the external SDRAMs. This bit
must be set to 1 after reset (initial pause of at least 200 µs is
necessary) and is automatically cleared by the ABM after
configuration of the SDRAMs has been executed.
1 Starts SDRAM initialization procedure
(0) self-clearing
CORE Downstream Core Disable
This bit disables the down stream ABM Core, wh ich is necessary in
some MiniSwitch configurations (Uni-Directional Mode using one
core).
It is recommended to set CORE = 0 in Bi-directional operation
modes.
1 Downstream ABM core disabled
0 Downstream ABM core enabled
WGS Work Group Switch Mode
Selects MiniSwitch (Uni-directional) Mode if set to 1.
1 MiniSwitch (Uni-directional) operation mode selected:
upstream transmit UTOPIA interface is disabled;
downstream receive UTOPIA interface is disabled.
0 Normal (Bi-directional) operation mode
BIN Indicate the usage of the CI/NI mechanism for ABR connections:
1 Enables CI/NI feedback
0 CI/NI feedback disabled
EFCI Indicate the usage of the EFCI mechanism for ABR connections:
1 Enables EFCI feedback
0 EFCI feedback disabled
BIP8 Disables discard of cells with BIP-8 header error.
1 BIP-8 errored cells are not discarded
0 BIP-8 errored cells are discarded
Prel. ABMP Data Sheet
Regi ster Desc ript ion
Preliminary Data Sheet 324 2001-14-01
PRELIMINARY
CRC Disables discard of RM cells with defect CRC10.
1 CRC10 errored RM cells are not discarded
0 CRC10 errored RM cells are discarded
LCItog Enables toggling of the LCI(0) bit in outgoing cells in MiniSwitch
(uni-directional) mode.
1 LCI bit zero is toggled in outgoing cells in case of
MiniSwitch operation mode selected
0 LCI bit zero remains unchanged
LCIMOD(1:0) Specifies the expected mapping of Local Connection Identifier (LCI)
field to cell header:
00 LCI(13, 12) = ’00’, LCI(11:0) mapped to VPI(11:0) field
01 LCI(15:0) mapped to VCI(15:0) field;
10 LCI(15:14) mapped to UDF1(1:0) field;
LCI(13:12) mapped to UDF1(7:6) field;
LCI(11:0) mapped to VPI(11:0) field
11 Internal Address reduction mode;
The LCI is derived from programmable parts of the VPI,
VCI and PN bit-fields. The derived LCI is used by the
ABMP, but nor written to the cell.
Prel. ABMP Data Sheet
Regi ster Desc ript ion
Preliminary Data Sheet 325 2001-14-01
PRELIMINARY
Register 122 MODE2
ABM Mode 2 Register
CPU Accessibility : Read/Write
Reset Value: 0000H
Offset Address: MODE EFH
Typical Usage: Written and Read by CPU
Bit1514131211109 8
SD
CAW SDRR unused ERCPD TUTS DQSC QS(1:0)
Bit 7 6 5 4 3 2 1 0
PNSRC MNUM(3:0) PNUM(2:0)
SDCAW SDRAM Column Address Width
08 bit
19 bit
SDRR SDRAM Refresh Rate
0 Default Refresh Rate
1 Double Refresh Rate
ERCPD ERC Power Down
0 ERC active
1 ERC in power-down mode
Note:
TUTS Tristate all UTOPIA Signals
0 Normal mode
1 UT OPIA Signals in TriState
Prel. ABMP Data Sheet
Regi ster Desc ript ion
Preliminary Data Sheet 326 2001-14-01
PRELIMINARY
DQSC Disable Quarter Segment Check
0 Normal mode
1 Quarter Segment Check disabled
QS(1:0) Quarter Segment
If Quarter Segment Check is enabled, the ABMP processes only
cells matching the LCI segment:
LCI(15:14) = QS(1:0)
All other cells are forwarded to the Common Real-Time Queue to
be processed by a subsequent ABMP (cascading).
PNSRC Port Number Source
This bit determines, which Port Number field is used for internal
Address Reduction Mode:
0 PN field is taken from the Utopia Port number, that
accepted the cell.
1 PN field is taken from the UDF1(5:0) field in the cell
MNUM(3: 0) M Par ame t er
This bit field determines the ranges of VPI and VCI cell header fields
mapped into the LCI in internal Address Reduction mode.
Please refer to Chapter 3.2.5 for further details.
PNUM(2:0) P Parameter
This bit field determines the number of port number bits mapped
into the LCI in internal Address Reduction mode.
Please refer to Chapter 3.2.5 for further details.
Prel. ABMP Data Sheet
Regi ster Desc ript ion
Preliminary Data Sheet 327 2001-14-01
PRELIMINARY
Register 123 UTRXCFG
Upstream/Downstream UTOPIA Receive Configuration Register
•
CPU Accessibility : Read/Write
Reset Value: 0001H
Offset Address: UTRXCFG F0H
Typical Usage: Written and Read by CPU
Bit151413121110 9 8
DURD DURUT DURPD DURPE DURCFG(1:0) DURBUS DURM
Bit76543210
UURD UURUT UURPD UURPE UURCFG(1:0) UURBUS UURM
DURD Downstream UTOPIA Receive Discard
UURD Upstream UTOPIA Receive Discard
0
1
DURUT Downstream UTOPIA Receive UDF1 Transparent
UURUT Upstream UTOPIA Receive UDF1 Transparent
0
1
DURPD Downstream UTOPIA Receive Parity Error discard
UURPD Upstream UTOPIA Receive Parity Error discard
0
1
DURPE Downstream UTOPIA Receive Parity Check Enable
Prel. ABMP Data Sheet
Regi ster Desc ript ion
Preliminary Data Sheet 328 2001-14-01
PRELIMINARY
UURPE Upstream UTOPIA Receive Parity Check Enable
0 Pari t y check disa bled
1 Parity check enabled
DURCFG(1:0) Downstream UTOPIA Receive Port Configuration
UURCFG(1:0) Upstream UTOPIA Receive Port Configuration
00 4 x 12 ports
01
10
11 Level 1 mode (4 x 1 port)
DURBUS Downstream UTOPIA Receive Bus Width
UURBUS Upstream UTOPIA Receive Bus Width
0 8 bit bus width
1 16 bit bus width
DURM Downstream UTOPIA Receive Mode
UURM Upstream UTOPIA Receive Mode
0Slave Mode
1 Master Mode
Prel. ABMP Data Sheet
Regi ster Desc ript ion
Preliminary Data Sheet 329 2001-14-01
PRELIMINARY
Register 124 UUTRXP0
Upstream UTOPIA Receive Port Register 0
•
Register 125 UUTRXP1
Upstream UTOPIA Receive Port Register 1
CPU Accessibility : Read/Write
Reset Value: 0000H
Offset Address: UUTRXP0 F1H
Typical Usage: Written and Read by CPU
Bit151413121110 9 8
UURXPEnable(15..8)
Bit76543210
UUTRXPEnable(7..0)
UUTRXPEnable
(15:0) Upstream UTOPIA Receive Port Enable
Each bit enables or disables the respective UTOPIA port (15..0):
bit = 0 Port disabled.
bit = 1 Port enabled.
CPU Accessibility : Read/Write
Reset Value: 0000H
Offset Address: UUTRXP1 F2H
Typical Usage: Written and Read by CPU
Bit151413121110 9 8
UURXPEnable(31..24)
Bit76543210
UUTRXPEnable(23..16)
Prel. ABMP Data Sheet
Regi ster Desc ript ion
Preliminary Data Sheet 330 2001-14-01
PRELIMINARY
•
Register 126 UUTRXP2
Upstream UTOPIA Receive Port Register 2
•
UUTRXPEnable
(31:16) Upstream UTOPIA Receive Port Enable
Each bit enables or disables the respective UTOPIA port (31..16):
bit = 0 Port disabled.
bit = 1 Port enabled.
CPU Accessibility : Read/Write
Reset Value: 0000H
Offset Address: UUTRXP2 F3H
Typical Usage: Written and Read by CPU
Bit151413121110 9 8
UURXPEnable(47..40)
Bit76543210
UUTRXPEnable(39..32)
UUTRXPEnable
(47:32) Upstream UTOPIA Receive Port Enable
Each bit enables or disables the respective UTOPIA port (47..32):
bit = 0 Port disabled.
bit = 1 Port enabled.
Prel. ABMP Data Sheet
Regi ster Desc ript ion
Preliminary Data Sheet 331 2001-14-01
PRELIMINARY
Register 127 DUTRXP0
Downstream UTOPIA Receive Port Register 0
•
Register 128 DUTRXP1
Downstream UTOPIA Receive Port Register 1
CPU Accessibility : Read/Write
Reset Value: 0000H
Offset Address: DUTRXP0 F4H
Typical Usage: Written and Read by CPU
Bit151413121110 9 8
DURXPEnable(15..8)
Bit76543210
DUTRXPEnable(7..0)
DUTRXPEnable
(15:0) Downstream UTOPIA Receive Port Enable
Each bit enables or disables the respective UTOPIA port (15..0):
bit = 0 Port disabled.
bit = 1 Port enabled.
CPU Accessibility : Read/Write
Reset Value: 0000H
Offset Address: DUTRXP1 F5H
Typical Usage: Written and Read by CPU
Bit151413121110 9 8
DURXPEnable(31..24)
Bit76543210
DUTRXPEnable(23..16)
Prel. ABMP Data Sheet
Regi ster Desc ript ion
Preliminary Data Sheet 332 2001-14-01
PRELIMINARY
•
Register 129 DUTRXP2
Downstream UTOPIA Receive Port Register 2
•
DUTRXPEnable
(31:16) Downstream UTOPIA Receive Port Enable
Each bit enables or disables the respective UTOPIA port (31..16):
bit = 0 Port disabled.
bit = 1 Port enabled.
CPU Accessibility : Read/Write
Reset Value: 0000H
Offset Address: DUTRXP2 F6H
Typical Usage: Written and Read by CPU
Bit151413121110 9 8
DURXPEnable(47..40)
Bit76543210
DUTRXPEnable(39..32)
DUTRXPEnable
(47:32) Downstream UTOPIA Receive Port Enable
Each bit enables or disables the respective UTOPIA port (47..32):
bit = 0 Port disabled.
bit = 1 Port enabled.
Prel. ABMP Data Sheet
Regi ster Desc ript ion
Preliminary Data Sheet 333 2001-14-01
PRELIMINARY
Register 130 UUTTXCFG
Upstream UTOPIA Transmit Configuration Register
•
CPU Accessibility : Read/Write
Reset Value: 0000H
Offset Address: UUTTXCFG F7H
Typical Usage: Written and Read by CPU
Bit151413121110 9 8
unused(2:0) UUTES UUTUT UUTCFG(1:0) UUTBUS
Bit76543210
UUTQL(6:0) UUTM
UUTM Upstream UTOPIA Transmit Mode
0Slave Mode
1 Master Mode
UUTQL(6:0) Upstream UTOPIA Transmit Queue Length
UURBUS Upstream UTOPIA Transmit Bus Width
0 8 bit bus width
1 16 bit bus width
UUTCFG(1:0) Upstream UTOPIA Transmit Port Configuration
00 4 x 12 ports
01
10
Prel. ABMP Data Sheet
Regi ster Desc ript ion
Preliminary Data Sheet 334 2001-14-01
PRELIMINARY
Register 131 DUTTXCFG
Downstream UTOPIA Transmit Configuration Register
•
11 Level 1 mode (4 x 1 port)
UUTUT Upstream UTOPIA Receive UDF2 Transparent
0
1
UUTES Upstream UTOPIA Transmit External Slave
0
1
CPU Accessibility : Read/Write
Reset Value: 0001H
Offset Address: DUTTXCFG F8H
Typical Usage: Written and Read by CPU
Bit151413121110 9 8
unused(2:0) DUTES DUTUT DUTCFG(1:0) DUTBUS
Bit76543210
DUTQL(6:0) DUTM
DUTM Downstream UTOPIA Transmit Mode
0Slave Mode
1 Master Mode
Prel. ABMP Data Sheet
Regi ster Desc ript ion
Preliminary Data Sheet 335 2001-14-01
PRELIMINARY
DUTQL(6:0) Downstream UTOPIA Transmit Queue Length
DURBUS Do wnstream UTOPIA Transmit Bus Width
0 8 bit bus width
1 16 bit bus width
DUTCFG(1:0) Downstream UTOPIA Transmit Port Config uration
00 4 x 12 ports
01
10
11 Level 1 mode (4 x 1 port)
DUTUT Downstream UTOPIA Receive UDF2 Transparent
0
1
DUTES Downstream UTOPIA Transmit External Slave
0
1
Prel. ABMP Data Sheet
Regi ster Desc ript ion
Preliminary Data Sheet 336 2001-14-01
PRELIMINARY
Register 132 UUTTXP0
Upstream UTOPIA Transmit Port Register 0
•
Register 133 UUTTXP1
Upstream UTOPIA Transmit Port Register 1
CPU Accessibility : Read/Write
Reset Value: 0000H
Offset Address: UUTTXP0 F9H
Typical Usage: Written and Read by CPU
Bit151413121110 9 8
UUTXPEnable(15..8)
Bit76543210
UUTTXPEnable(7..0)
UUTTXPEnable
(15:0) Upstream UTOPIA Transmit Port Enable
Each bit enables or disables the respective UTOPIA port (15..0):
bit = 0 Port disabled.
bit = 1 Port enabled.
CPU Accessibility : Read/Write
Reset Value: 0000H
Offset Address: UUTTXP1 FAH
Typical Usage: Written and Read by CPU
Bit151413121110 9 8
UUTTXPEnable(31..24)
Bit76543210
UUTTXPEnable(23..16)
Prel. ABMP Data Sheet
Regi ster Desc ript ion
Preliminary Data Sheet 337 2001-14-01
PRELIMINARY
•
Register 134 UUTTXP2
Upstream UTOPIA Transmit Port Register 2
•
UUTTXPEnable
(31:16) Upstream UTOPIA Transmit Port Enable
Each bit enables or disables the respective UTOPIA port (31..16):
bit = 0 Port disabled.
bit = 1 Port enabled.
CPU Accessibility : Read/Write
Reset Value: 0000H
Offset Address: UUTTXP2 FBH
Typical Usage: Written and Read by CPU
Bit151413121110 9 8
UUTTXPEnable(47..40)
Bit76543210
UUTTXPEnable(39..32)
UUTTXPEnable
(47:32) Upstream UTOPIA Transmit Port Enable
Each bit enables or disables the respective UTOPIA port (47..32):
bit = 0 Port disabled.
bit = 1 Port enabled.
Prel. ABMP Data Sheet
Regi ster Desc ript ion
Preliminary Data Sheet 338 2001-14-01
PRELIMINARY
Register 135 DUTRXP0
Downstream UTOPIA Transmit Port Register 0
•
Register 136 DUTTXP1
Downstream UTOPIA Transmit Port Register 1
CPU Accessibility : Read/Write
Reset Value: 0000H
Offset Address: DUTTXP0 FCH
Typical Usage: Written and Read by CPU
Bit151413121110 9 8
DUTTXPEnable(15..8)
Bit76543210
DUTTXPEnable(7..0)
DUTTXPEnable
(15:0) Downstream UTOPIA Transmit Port Enable
Each bit enables or disables the respective UTOPIA port (15..0):
bit = 0 Port disabled.
bit = 1 Port enabled.
CPU Accessibility : Read/Write
Reset Value: 0000H
Offset Address: DUTTXP1 FDH
Typical Usage: Written and Read by CPU
Bit151413121110 9 8
DUTTXPEnable(31..24)
Bit76543210
DUTTXPEnable(23..16)
Prel. ABMP Data Sheet
Regi ster Desc ript ion
Preliminary Data Sheet 339 2001-14-01
PRELIMINARY
•
Register 137 DUTTXP2
Downstream UTOPIA Transmit Port Register 2
•
DUTTXPEnable
(31:16) Downstream UTOPIA Transmit Port Enable
Each bit enables or disables the respective UTOPIA port (31..16):
bit = 0 Port disabled.
bit = 1 Port enabled.
CPU Accessibility : Read/Write
Reset Value: 0000H
Offset Address: DUTTXP2 FEH
Typical Usage: Written and Read by CPU
Bit151413121110 9 8
DUTTXPEnable(47..40)
Bit76543210
DUTTXPEnable(39..32)
DUTTXPEnable
(47:32) Downstream UTOPIA Transmit Port Enable
Each bit enables or disables the respective UTOPIA port (47..32):
bit = 0 Port disabled.
bit = 1 Port enabled.
Prel. ABMP Data Sheet
Regi ster Desc ript ion
Preliminary Data Sheet 340 2001-14-01
PRELIMINARY
Register 138 TEST
TEST Register
•
CPU Accessibility : Read/Write
Reset Value: 0000H
Offset Address: TEST FFH
Typical Usage: Written and Read by CPU for device test purposes
Bit 15 14 13 12 11 10 9 8
Unused(1:0) CLKdelay(1:0) BistRes(4:1)
Bit7 6543210
BistRes0 StartBist flags(5:0)
CLKDelay(1:0) This bit-field adjusts the delay of TSTCLK output with respect to
SYSCLK input.
00 Delay 0
01 Delay 2
10 Delay 4
11 Delay 6
BistRes(4:0) Result of BIST of internal RAMs.
After execution, all five bits must be zero; otherwise, an internal
RAM failure was dete cted.
StartBist Starts internal RAM BIST
Automatically cleared after execution of the Bist procedure.
flags(5:0) This bit-field controls special test mode s.
It is recommended to Write all 0s to this bit-field.
Prel. ABMP Data Sheet
Programming
Preliminary Data Sheet 341 2001-14-01
PRELIMINARY
8 Programming
(Left blank intentionally.)
Prel. ABMP Data Sheet
Application Hints
Preliminary Data Sheet 343 2001-14-01
PRELIMINARY
10 Application Hints
10.1 Backpressure Controlled Applications
(For future document update.)
10.2 AAL5-Processed Cell Insertion/Extraction
(For future document update.)
Prel. ABMP Data Sheet
Electrical Characteristics
Preliminary Data Sheet 344 2001-14-01
PRELIMINARY
11 Electrical Chara cteristics
11.1 Absolute Maximum Ratings
Table 11-1 Absolute Maximum Ratings
Note:Stresses above those listed here may cause permanent damage to the
device. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.
11.2 Operating Range
Table 11-2 Operating Range
Note: In the operating range, the functions given in the circuit description are fulfilled.
Parameter Symbol Limit Values Unit
Ambient temperature under bias PXB TA-40 to 85 °C
Storage temperature Tstg -40 to 125 °C
IC supply voltage with respect to ground VDD -0.3 to 3.6 V
Voltage on any pin with respect to ground VS-0.4 to VDD + 0.4 V
ESD robustness1)
HBM: 1.5 kΩ, 100 pF
1) According to MIL-Std 883 D, method 301 5.7 and ESD Association Standard EOS/ESD-5.1-1993.
The RF Pi ns 20, 21, 26, 29, 32, 33, 34 and 35 are not prote c ted against voltage st ress > 300 V (versus VS or
GND). Th e high freq uency perform ance prohibits the use of adequate protecti ve structures.
VESD,HBM 2000 V
Parameter Symbol Limit Values Unit Test Condition
min. max.
Ambient temperature
under bias TA-40 85 °C
Junction temperature TJ125 °C
Supply voltage 3.3V VDD33 3.0 3.6 V
Supply voltage 1.8V VDD18 1.62 1.98 V
Ground VSS 00V
Power dissipation P2.5 W
Prel. ABMP Data Sheet
Electrical Characteristics
Preliminary Data Sheet 345 2001-14-01
PRELIMINARY
11.3 DC Characteristics
Table 11-3 DC Characteristics
Parameter Symbol Limit Values Unit Notes
min. typ. max
Input low voltage VIL –0.4 0.8 V
Input high voltage VIH 2.0 VDD +
0.3 V LVTTL (3.3V)
Output low voltage VOL 0.2 0.4 V IOL =5mA
Output high voltage VOH 2.4 VDD VIOH =–5mA
Average
power supply current ICC (AV
)330 mA VDD33 =3.3V,
VDD18 =1.8V,
TA=25°C,
SYSCLK =
80 MHz;
UTRXCLKU =
UTTCCLKU =
UTRXCLKD =
UTTXCLKD =
52MHz;
Average
power down supply current ICCPD
(AV) 10 mA VDD =3.3V,
TA=25°C,
no output loads,
no clocks
Average
power dissipation P(AV) 1 1.3 W VDD33 =3.3V,
VDD18 =1.8V,
TA=25°C,
SYSCLK =
80 MHz;
UTRXCLKU =
UTTCCLKU =
UTRXCLKD =
UTTXCLKD =
52MHz;
Prel. ABMP Data Sheet
Electrical Characteristics
Preliminary Data Sheet 346 2001-14-01
PRELIMINARY
Input current IIIN -1 1 µAVIN =VDD33 or
VSS
48µAVIN =VDD33 for
Inputs with
internal Pull-
Down resistor
-4 -8 µAVIN =VSS for
Inputs with
internal Pull-Up
resistor
Input leakage current IIL 1µAVDD33 =3.3V,
VDD18 =1.8V,
GND = 0 V; all
other pins are
floating
Output leakage current IOZ 1µAVDD33 =3.3V,
VDD18 =1.8V,
GND = 0 V;
VOUT =0V
Parameter Symbol Limit Values Unit Notes
min. typ. max
Prel. ABMP Data Sheet
Electrical Characteristics
Preliminary Data Sheet 347 2001-14-01
PRELIMINARY
11.4 AC Characteristics
TA = -40 to 85 °C, VDD33 = 3.3 V ± 9 %, VDD18 = 1.8 V ± 10%, VSS = 0 V
All inputs are driven to VIH = 2.4 V for a logical 1
and to VIL = 0.4 V for a logical 0
All outputs are measured at VH = 2.0 V for a logical 1
and at VL = 0.8 V for a logical 0
The AC testing input/output waveforms are shown below.
•
Figure 11-1 Input/Output Waveform for AC Measurements
Test Points
ac_int.ds4
V
HDevice
under
Test
C
LOAD = 5 0 pF max
V
H
V
L
V
L
Prel. ABMP Data Sheet
Electrical Characteristics
Preliminary Data Sheet 348 2001-14-01
PRELIMINARY
Table 11-4 Clock Frequencies
Parameter Symbol Limit Values Unit
min. max.
Core clock (internal) 2 5 80 MHz
ERC core clock (internal) 25 100 MHz
External core clock source SYSCLK 25 52 MHz
UTOPIA clocks at PHY-side UTRXCLKU fint.coreclock/2 ΜΙΝ
{fint. core clock,
52 MHz}
MHz
UTTXCLKD fint.coreclock/2 ΜΙΝ
{fint. core clock,
52 MHz}
MHz
UTOPIA clock at Backplane-side UTRXCLKD fint.coreclock/2 ΜΙΝ
{fint. core clock,
66 MHz}
MHz
UTTXCLKU fint.coreclock/2 ΜΙΝ
{fint. core clock,
52 MHz}
MHz
µP clock1)
1) Supplied only to external microprocessor
≤fSYSCLK MHz
SPI interface clock SPICLK ΜΙΝ
{fint. core clock,
52 MHz}
MHz
QCI interface clock QCITXCLK ΜΙΝ
{fint. core clock,
66 MHz}
MHz
Prel. ABMP Data Sheet
Electrical Characteristics
Preliminary Data Sheet 349 2001-14-01
PRELIMINARY
11.4.1 Microprocessor Interface Timing Intel Mode
11.4.1.1 Microprocessor Write Cycle Timing (Intel)
•
Figure 11-2 Microprocessor Interface Write Cycle Timing (Intel)
Table 11-5 Microprocessor Interface Write Cycle Timing (Intel)
No. Parameter Limit Values Unit
Min Typ Max
1MPADR setup time before MPCS
low 0ns
2MPCS setup time before MPWR low 0 ns
3 MPRDY low delay after MPWR low 0 20 ns
4 MPDAT setup time before MPWR high 5 ns
5 Pulse width MPRDY low 4 SYSCLK
cycles 5 SYSCLK
cycles
6 MPRDY high to MPWR high 5 ns
7 MPDAT hold time after MPWR high 5 ns
8MPCS hold time after MPWR high 5 ns
9 MPADR hold time after MPWR high 5 ns
10 MPCS low to MPRDY low impedance 0 ns
11 MPCS high to MPRDY high
impedance 15 ns
1
3
4
56
7
8
9
MPADR
MPCS
MPWR
MPRDY
MPDAT
2
11
10
Prel. ABMP Data Sheet
Electrical Characteristics
Preliminary Data Sheet 350 2001-14-01
PRELIMINARY
11.4.1.2 Microprocessor Read Cycle Timing (Intel)
•
Figure 11-3 Microprocessor Interface Read Cycle Timing (Intel)
Table 11-6 Microprocessor Interface Read Cycle Timing (Intel)
No. Parameter Limit Values Unit
Min Typ Max
20 MPADR setup time before MPCS
low 0ns
21 MPCS setup time before MPRD low 0 ns
22 MPRDY low delay after MPRD low 0 20 ns
23 Pulse width MPRDY low 4 SYSCLK
cycles 5 SYSCLK
cycles
24 MPDAT valid before MPRDY high 5 ns
25 MPRDY high to MPRD high 5 ns
26 MPDAT hold time after MPRD high 2 ns
27 MPCS hold time after MPRD high 5 ns
28 MPADR hold time after MPRD high 5 ns
29 MPRD low to MPDAT low impedance 0 15 ns
30 MPRD high to MPDAT high impedance 0 17 ns
31 MPCS low to MPRDY low impedance 0 ns
32 MPCS high to MPRDY high
impedance 15 ns
20
22
24
23 25
26
27
28
MPADR
MPCS
MPRD
MPRDY
MPDAT
21
29
30
32
31
Prel. ABMP Data Sheet
Electrical Characteristics
Preliminary Data Sheet 351 2001-14-01
PRELIMINARY
11.4.2 Microprocessor Interface Timing Motorola Mode
11.4.2.1 Microprocessor Write Cycle Timing (Motorola)
•
Figure 11-4 Microprocessor Interface Write Cycle Timing (Motorola)
Table 11-7 Microprocessor Interface Write Cycle Timing (Motorola)
No. Parameter Limit Values Unit
Min Typ Max
40 MPADR setup time before MPCS
low 0ns
41 MPCS setup time before DS low 0 ns
42 RDY low delay after DS low 0 20 ns
43 MPDAT setup time before DS high 5 ns
44 Pulse width RDY low 4 SYSCLK
cycles 5 SYSCLK
cycles
45 RDY high to DS high 5 ns
46 MPDAT hold time after DS high 5 ns
47 MPCS hold time after DS high 5 ns
48 MPADR hold time after DS high 5 ns
51 R/W setup time before DS low 10 ns
40
43 46
48
MPADR
MPCS
MPDAT
42 44 45
47
(MPRD)
DS
(MPRDY)
RDY
(
DTACK
)
41
(MPWR)
R/W
5251
54
53
Prel. ABMP Data Sheet
Electrical Characteristics
Preliminary Data Sheet 352 2001-14-01
PRELIMINARY
52 R/W hold time after DS high 0 ns
53 MPCS low to RDY low impedance 0 ns
54 MPCS high to RDY high impedance 15 ns
Table 11-7 Microprocessor Interface Write Cycle Timing (Motorola)
No. Parameter Limit Values Unit
Min Typ Max
Prel. ABMP Data Sheet
Electrical Characteristics
Preliminary Data Sheet 353 2001-14-01
PRELIMINARY
11.4.2.2 Microprocessor Read Cycle Timing (Motorola)
•
Figure 11-5 Microprocessor Interface Read Cycle Timing (Motorola)
Table 11-8 Microprocessor Interface Read Cycle Timing (Motorola)
No. Parameter Limit Values Unit
Min Typ Max
60 MPADR setup time before MPCS
low 0ns
61 MPCS setup time before DS low 0 ns
62 RDY low delay after DS low 0 20 ns
63 Pulse width RDY low 4 SYSCLK
cycles 5 SYSCLK
cycles
64 MPDAT valid before RDY high 5 ns
65 RDY high to DS high 5 ns
66 MPDAT hold time after DS high 2 ns
67 MPCS hold time after DS high 5 ns
68 MPADR hold time after DS high 5 ns
69 DS low to MPDAT low impedance 0 15 ns
70 DS high to MPDAT high impedance 0 17 ns
71 R/W setup time before DS low 10 ns
60
62
64
63 65
66
67
68
MPADR
MPCS
(MPRD)
DS
(MPRDY)
RDY
(
DTACK
)
MPDAT
61
69
70
(MPWR)
R/W
7271
73 74
Prel. ABMP Data Sheet
Electrical Characteristics
Preliminary Data Sheet 354 2001-14-01
PRELIMINARY
72 R/W hold time after DS high 0 ns
73 MPCS low to RDY low imp edance 0 ns
74 MPCS high to RDY high impedance 15 ns
Table 11-8 Microprocessor Interface Read Cycle Timing (Motorola)
No. Parameter Limit Values Unit
Min Typ Max
Prel. ABMP Data Sheet
Electrical Characteristics
Preliminary Data Sheet 355 2001-14-01
PRELIMINARY
11.4.3 UTOPIA Interface
The AC characteristics of the UTOPIA Interface fulfill the standard of [1] and [2]. Setup
and hold times of the 50 MHz UTOPIA Specification are valid.
According to the UTOPIA Specification, the AC characteristics are based on the timing
specification for the receiver side of a signal. The setup and the hold times are defined
with regards to a positive clock edge, see Figure 11-6.
Taking into account the actual clock frequency (up to the maximum frequency), the
corresponding (min. and max.) transmit side "clock to output" propagation delay
specifications can be derived. The timing references (tT5 to tT12) are according to the
data found in Table 11-9 to Table 11-12.
Note: The UTOPIA receive interface backplane-side is optimized for operation up to
66 MHz UTOPIA clock frequency to achieve a speed-up factor of 1.25 in
bandwidth accepted from the backplane. Respective values are provided in
brackets.
•
Figure 11-6 Set up and Hold Time Definition (Single- and Multi-PHY)
Figure 11-7 shows the tristate timing for the multi-PHY application (multiple PHY
devices, multiple output signals are multiplexed together).
Clock
Signal
84, 86 85, 87
input setup to clock input hold from clock
Prel. ABMP Data Sheet
Electrical Characteristics
Preliminary Data Sheet 356 2001-14-01
PRELIMINARY
•
Figure 11-7 Tristate Timing (Multi-PHY, Multiple Devices Only)
In the following tables, A⇒P (column DIR, Direction) defines a signal from the ATM
Layer (transmitter, driver) to the PHY Layer (receiver), A⇐P defines a signal from the
PHY Layer (transmitter, driver) to the ATM Layer (receiver).
Both UTOPIA interfaces (PHY-side and Backplane-side) can be configured in either
slave or master mode. If configured in Master mode, the interface is considered to be the
ATM Laye r devi ce ( A) and if configured in Sl ave mode , the interface is consid ere d to be
the PHY Layer device (P) respectively.
All timings also apply to UTOPIA Level 1 8-bit data bus operation.
•
Table 11-9 Transmit Timing (16-Bit Data Bus, 50 MHz at Cell Interface, Single
PHY)
No. Signal Name DIR Description Limit Values Unit
Min Max
80 UTXCLKD,
UTXCLKU A>P TxClk frequency (nominal) 0 52 MHz
81 TxClk duty cycle 40 60 %
82 TxClk peak-to-peak jitter - 5 %
83 TxClk rise/fall time - 2 ns
84 UTXDATD,
UTXDATU,
UTXPRTYD,
UTXPRTYU,
UTXSOCD,
UTXSOCU,
UTXENBD,
UTXENBU
A>P Input setup to TxClk 4 - ns
85 Input hold from TxClk 1 - ns
Clock
Signal
90 91
signal goin g low
impedance from clock
88 89
signal going low
impedance to clock signal going high
impedance from clock signal go ing high
impedance to clock
Prel. ABMP Data Sheet
Electrical Characteristics
Preliminary Data Sheet 357 2001-14-01
PRELIMINARY
86 UTXCLAVD,
UTXCLAVU A<P Input setup to TxClk 4 - ns
87 Input hold from TxClk 1 - ns
Table 11-10 Receive Timing (16-Bit Data Bus, 50 MHz at Cell Interface, Single
PHY)
No. Signal Name DIR Description Limit Values Unit
Min Max
80 URXCLKD,
URXCLKU A>P RxClk frequency (nominal)
URXCLKD:
URXCLKU: 0
052 (66)
52
MHz
81 R xClk duty cycle 40 6 0 %
82 RxClk peak-to-peak jitter - 5 %
83 RxClk rise/fall time - 2 ns
84 URXENBD,
URXENBU A>P Input setup to RxClk 4 - ns
85 Input hold from RxClk 1 - ns
86 URXDATD,
URXDATU,
URXPRTYD,
URXPRTYU,
URXSOCD,
URXSOCU,
URXCLAVD,
URXCLAVU
A<P Input setup to RxClk 4 - ns
87 Input hold from RxClk 1 - ns
Table 11-9 Transmit Timing (16-Bit Data Bus, 50 MHz at Cell Interface, Single
PHY)
No. Signal Name DIR Description Limit Values Unit
Min Max
Prel. ABMP Data Sheet
Electrical Characteristics
Preliminary Data Sheet 358 2001-14-01
PRELIMINARY
Table 11-11 Transmit Timing (16-Bit Data Bus, 50 MHz at Cell Interface,
Multi-PHY)
No. Signal Name DIR Description Limit Values Unit
Min Max
80 UTXCLKD,
UTXCLKU A>P TxClk frequency (nominal) 0 52 MHz
81 TxClk duty cycle 40 60 %
82 TxClk peak-to-peak jitter - 5 %
83 TxClk rise/fall time - 2 ns
84 UTXDATD,
UTXDATU,
UTXPRTYD,
UTXPRTYU,
UTXSOCD,
UTXSOCU,
UTXENBD,
UTXENBU,
UTXADRD,
UTXADRU
A>P Input setup to TxClk 4 - ns
85 Input hold from TxClk 1 - ns
86 UTXCLAVD,
UTXCLAVU A<P Input setup to TxClk 4 - ns
87 Input hold from TxClk 1 - ns
88 Signal going low impedance to
TxCLK 4- ns
89 Signal going high impedance
to TxCLK 0- ns
90 Signal going low impedance
from TxCLK 1- ns
91 Signal going high impedance
from TxCLK 1- ns
Prel. ABMP Data Sheet
Electrical Characteristics
Preliminary Data Sheet 359 2001-14-01
PRELIMINARY
Note: The setup and hold times for receive interfaces deviate for non-standard 66 MHz
operation. Timings are provided on request.
Table 11-12 Receive Timing (16-Bit Data Bus, 50 MHz at Cell Interface,
Multi-PHY)
No. Signal Name DIR Description Limit Values Unit
Min Max
80 URXCLKD,
URXCLKU A>P RxClk frequency (nominal)
URXCLKD:
URXCLKU: 0
052 (66)
52
MHz
81 RxClk duty cycle 40 60 %
82 RxClk peak-to-peak jitter - 5 %
83 RxClk rise/fall time - 2 ns
84 URXENBD,
URXENBU,
URXADRD,
URXADRU
A>P Input setup to RxClk 4 - ns
85 Input hold from RxClk 1 - ns
86 URXDATD,
URXDATU,
URXPRTYD,
URXPRTYU,
URXSOCD,
URXSOCU,
URXCLAVD,
URXCLAVU
A<P Input setup to RxClk 4 - ns
87 Input hold from RxClk 1 - ns
88 Signal going low impedance to
RxCLK 4- ns
89 Signal going high impedance
to RxCLK 0- ns
90 Signal going low impedance
from RxCLK 1- ns
91 Signal going high impedance
from RxCLK 1- ns
Prel. ABMP Data Sheet
Electrical Characteristics
Preliminary Data Sheet 360 2001-14-01
PRELIMINARY
11.4.4 CPR SSRAM Interface
Timing of the Synchronous Static RAM Interfaces is simplified as all signals are refer-
enced to the rising edge of RAMCLK. In Figure 11-8, it can be seen that all signals
output by the PXB 4330 E ABMP have identical delay times with reference to the clock.
When readi ng fr om the R AM, the PXB 4330 E ABMP samples th e data wi thi n a w indow
at the rising clock edge.
Figure 11-8 SSRAM Interface Generic Timing Diagram
Table 11-13 SSRAM Interface AC Timing Characteristics
No. Parameter Limit Values Unit
Min Typ Max
100 TRAMCLK : Period RAMCLK 19.3 ns
100A FRAMCLK : Frequency RAMCLK TBD MHz
101 RAMCLK Low Pulse Width TBD ns
102 RAMCLK High Pulse Width TBD ns
103 Delay RAMCLK rising to CPRADSC,
CPRADR(18:0), CPRGW, CPROE TBD TBD ns
104 Delay RAMCLK rising to CPRRDAT
Output TBD TBD ns
RAMCLK
CPRADSC,
CPRADR(18:0),
CPRGW, CPROE
CPRDAT(19:0), output
CPRDAT(19:0), input
100
101 102
103
104
106105
Prel. ABMP Data Sheet
Electrical Characteristics
Preliminary Data Sheet 361 2001-14-01
PRELIMINARY
11.4.5 CSR SDRAM Interface(s)
Timing of the Synchron ous Dynam ic RAM Interface is simplifi ed as al l si gnals are r efer -
enced to the rising edge of RAMCLK. In Figure 11-9, it can be seen that all signals
output by the PXB 4330 E ABMP have identical delay times with reference to the clock.
When readi ng fr om the R AM, the PXB 4330 E ABMP samples th e data wi thi n a w indow
at the rising clock edge.
Figure 11-9 Generic SDRAM Interface Timing Diagram
105 Setup time CPRDAT Input before CLK
rising (read cycles) TBD ns
106 Hold time CPRDAT Input after CLK ris-
ing (read cycles) TBD ns
Table 11-14 SDRAM Interface AC Timing Characteristics
No. Parameter Limit Values Unit
Min Typ Max
110 TRAMCLK : Period RAMCLK 19.3 ns
110A FRAMCLK : Frequency RAMCLK TBD MHz
Table 11-13 SSRAM Interface AC Timing Characteristics (cont’d)
No. Parameter Limit Values Unit
Min Typ Max
RAMCLK
CSRADRi(13:0),
CSRRASi, CSRCASi,
CSRCSi, CSRWEi,
CSRBAi0, CSRBAi1
CS RDATi(31:0) , output
CS RDAT i(31:0), input
110
111 112
113
114
116115
i = D (Downstream), U (Upstream)
Prel. ABMP Data Sheet
Electrical Characteristics
Preliminary Data Sheet 362 2001-14-01
PRELIMINARY
111 RAMCLK Low Pulse Width 7.3 ns
112 RAMCLK High Pulse Width 7.3 ns
113 Delay RAMCLK rising to
CSRADRi(13:0), CSRC Si, CSRRASi,
CSRCASi, CSRWEi, CSRBAi0,
CSRBAi1
TBD TBD ns
114 Delay RAMCLK rising to CSRDATi
Output TBD TBD ns
115 Setup time CSRDATi Input before
RAMCLK rising (read cycles) TBD ns
116 Ho ld time CSR DATi Input after RAM-
CLK rising (read cycles) TBD ns
Table 11-14 SDRAM Interface AC Timing Characteristics (cont’d)
No. Parameter Limit Values Unit
Min Typ Max
Prel. ABMP Data Sheet
Electrical Characteristics
Preliminary Data Sheet 363 2001-14-01
PRELIMINARY
11.4.6 Reset Timing
Figure 11-10 Reset Timing
Note: RESET ma y be asynchrono us to CLK when asser ted or deassert ed. RESET may
be asserted during power-up or asserted after power-up. Nevertheless,
deassertion must be at a clean, bounce-free edge.
Table 11-15 Reset Timing
No. Parameter Limit Values Unit
min. max.
150 RESET pulse width 120 ns
151 Number of SYSCLK cycles during
RESET active 2 SYSCLK
cycles
power-on
VDD
CLK
RESET
150
151
Prel. ABMP Data Sheet
Electrical Characteristics
Preliminary Data Sheet 364 2001-14-01
PRELIMINARY
11.4.7 Boundary-Scan Test Interface
Figure 11-11 Boundary-Scan Test Interface Timing Diagram
Table 11-16 Boundary-Scan Te st Interface AC Timing Characteristics
No. Param eter Limit Val ues Unit
Min Typ Max
160 TTCK : Period TCK 100 ns
160A FTCK : Frequency TCK 10 MHz
161 TCK high time 40 ns
162 TCK low time 40 ns
163 Setup time TMS before TCK rising 10 ns
164 Hold time TMS after TCK rising 10 ns
165 Setup time TDI before TCK rising 10 ns
166 Hold time TDI after TCK rising 10 ns
167 Delay T CK falling to TDO valid 30 ns
160/
160A
161 162
163 164
165 166
167/
167A
TCK
TMS
TDI
TRST
TDO
168
Prel. ABMP Data Sheet
Electrical Characteristics
Preliminary Data Sheet 365 2001-14-01
PRELIMINARY
167A Delay TCK falling to TDO high
impedance 30 ns
168 Pulse width TRST lo w 200 ns
Table 11-16 Boundary-Scan Te st Interface AC Timing Characteristics (cont’d)
No. Param eter Limit Val ues Unit
Min Typ Max
Prel. ABMP Data Sheet
Electrical Characteristics
Preliminary Data Sheet 366 2001-14-01
PRELIMINARY
11.4.8 SPI Interface
Figure 11-12 SPI Interface Timing Diagram
Table 11-17 SPI Interface AC Timing Characteristics
No. Param eter Limit Val ues Unit
Min Typ Max
200 SPICS low to SPICLK delay 500 ns
201 SPICLK to SPICS delay 500 ns
202 SPICLK high time 500 ns
203 SPICLK low time 500 ns
204 SPICS low to SPISO delay 100 ns
205 SPICLK to SPISO delay 100 ns
206 SPISI to SPICLK setup time 100 ns
207 SPISI to SPICLK hold time 100 ns
SPICLK
SPISI
205
SPICS
SPISO
204
200 201202 203
206 207
Prel. ABMP Data Sheet
Electrical Characteristics
Preliminary Data Sheet 367 2001-14-01
PRELIMINARY
11.4.9 Queue Congestion Interface (QCI)
Figure 11-13 QCI Interface Timing Diagram
Table 11-18 QCI Interface AC Timing Characteristics
No. Param eter Limit Val ues Unit
Min Typ Max
250 TQCICLK : Period QCICLK 15.15 ns
250A FQCICLK : Frequency QCICLK 66 MHz
251 QCICLK low time 7 ns
252 QCICLK high time 7 ns
253 Setup time QCITXFRAME before
QCICLK rising 4ns
254 Hold time QCITXFRAME after
QCICLK rising 4ns
255 Setup time QCITXDAT before
QCICLK rising 4ns
256 Hold time QCITXDAT after
QCICLK rising 4ns
QCICLK
QCITXFRAME
QCITXDAT
250
251 252
254
256255
253
Prel. ABMP Data Sheet
Electrical Characteristics
Preliminary Data Sheet 368 2001-14-01
PRELIMINARY
11.5 Capacitances
11.6 Package Characteristics
Table 11-20 Thermal Package Characteristics
Table 11-19 Capacitances
Parameter Symbol Limit Values U nit
min. max.
Input Capacitance CIN 2.5 5 pF
Output Capacitance COUT 25pF
Load Capacitance at:
UTOPIA Outputs
MPDAT(15:0), MPRDY
other outputs
CFO1
CFO2
CFO3
40
50
20
pF
pF
pF
Parameter Symbol Value Unit
Thermal Package Resistance Junction to Ambient
Airflow Ambient Temperature
No airfl ow
T
A=25°C RJA(0,25) TBD °C/W
Airflow 100 lfpm = 0.5m/s
T
A=25°C RJA(0,25) TBD °C/W
Airflow 200 lfpm = 1m/s
T
A=25°C RJA(0,25) TBD °C/W
Airflow 300 lfpm = 1.5m/s
T
A=25°C RJA(0,25) TBD °C/W
Airflow 400 lfpm = 2m/s
T
A=25°C RJA(0,25) TBD °C/W
Airflow 500 lfpm = 2.5m/s
T
A=25°C RJA(0,25) TBD °C/W
Prel. ABMP Data Sheet
Testmode
Preliminary Data Sheet 369 2001-14-01
PRELIMINARY
12 Testmode
A test access port (TAP) is implemented in the ABMP. The essential part of the TAP is
a finite state machine (16 states) controlling the different operational modes of the
boundary scan. Both, TAP controller and boundary scan, meet the requirements given
by the JTAG standard: IEEE 1149.1. Figure 12-1 gives an overview about the TAP
controller.
•
Figure 12-1 Block Diagram of Test Access Port and Boundary Scan Unit
If no boundary scan ope ration is pl anned TRST has to be connect ed with VSS. TMS and
TDI do not need to be connected since pull- up transistors ensure high input levels in this
case. Nevertheless it would be a good practice to put the unused inputs to defined levels.
In this case, if the JTAG is not used:
TMS = TCK = ‘1’ is recommended.
Test handling (boundary scan operation) is performed via the pins TCK (Test Clock),
TMS (Test Mode Select), TDI (Test Data Input) and TDO (Test Data Output) when the
TAP controller is not in its reset state, i. e. TRST is connected to VDD3 or it remains
unconnected due to its internal pull up. Test data at TDI are loaded with a clock signal
connected to TCK. ‘1’ or ‘0’ on TMS causes a transition from one controller state to
another; constant ‘1’ on TMS leads to normal operation of the chip.
An input pin (I) uses one boundary scan cell (data in), an output pin (O) uses two cells
(data out, enable) and an I/O-pin (I/O) uses three cells (data in, data out, enable). Note
that most functional output and input pins of the ABMP are tested as I/O pins in boundary
scan, hence using three cells. The bound ary scan unit of the ABMP conta ins a total of n
Clock Generati on
Test Access Port (TAP)
TAP Controller
- Finite State Machine
- Instruction Regist er (4 bit)
- Test Signal Generator
CLOCK
TCK
TRST
TMS
Reset
Data in
TDI
Test
Control
TDO
Enable
Data out
CLOCK
Identifica tion Scan (32 bit)
Boundary Scan (n bi t)
Control
Bus
ID Data out
SS Data
out n
.
.
.
.
.
.
1
2
Pins
Prel. ABMP Data Sheet
Testmode
Preliminary Data Sheet 370 2001-14-01
PRELIMINARY
= TBD scan cells. The desired test mode is selected by serially loading a 4-bit instruction
code into the instruction register via TDI (LSB first).
EXTEST is used to examine the int erconn ecti on o f the devi ces o n the bo ard . In this test
mode at first all input pins capture the current level on the corresponding external
interconnecti on line, whereas all output pins are held at constant values (‘0’ or ‘ 1’). Then
the contents of the boundary scan is shifted to TDO. At the same time the next scan
vector is loaded from TDI. Subsequently all output pins are updated according to the new
boundary scan contents and all input pins again capture the current external level
afterwards, and so on.
INTEST supports internal testing of the chip, i. e. the output pins capture the current level
on the corre sponding intern al l ine wher eas all i nput pi ns are held on constant val ues (‘0’
or ‘1’). The resulting boundary scan vector is shifted to TDO. The next test vector is
serially loaded via TDI. Then all input pins are updated for the following test cycle.
SAMPLE/PRELOAD is a test mode which provides a snapshot of pin levels during
normal operation.
IDCODE: A 32- bit identification register is serially read out via TDO. It contains the
version number (4 bits), the device code (16 bits) and the manufacturer code (11 bits).
The LSB is fixed to ‘1’.
Standard mode:
The ID code field is set to
Version : 1H
Part Number : TBDH
Manufacturer : 083H (including LSB, whic h is fixed to ’1’)
Alternate mode:
The ID code field is set to
Version : 1H
Part Number : TBDH
Manufacturer : 083H (including LSB, whic h is fixed to ’1’)
Note: Since in test logic reset state the code ‘0011’ is automatically loaded into the
instruction register, the ID code can easily be read out in shift DR state.
BYPASS: A bit entering TDI is shifted to TDO after one TCK clock cycle.
CLAMP allows the state of signals driven from component pins to be determined from
the boundary-scan register while the bypass register is selected as the serial path
between TDI and TDO. Si gnals driven from the ABM P will no t change whil e the CLAMP
instruction is selected.
HIGHZ places all of the system outputs in an inactive drive state.
Prel. ABMP Data Sheet
Package Outlines
Preliminary Data Sheet 371 2001-14-01
PRELIMINARY
13 Package Outlines
•
(Super BGA 456 Package with metal heat sink)
GPM05247
SMD = Surface Mounted Device
Sorts of Packing
Package outlines for tubes, trays etc. are contained in our
Data Book “Package Information”. Dimensions in mm
Prel. ABMP Data Sheet
Appendix
Preliminary Data Sheet 372 2001-14-01
PRELIMINARY
14 Appendix
(Left blank intentionally.)
Prel. ABMP Data Sheet
Glossary
Preliminary Data Sheet 373 2001-14-01
PRELIMINARY
15 Glossary
(Left blank intentionally.)
•
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