MC14081BCL - Motorola / Freescale Semiconductor

MOTOROLA CMOS LOGIC DATA 7

MC14001B

%& "#  $#

The B Series logic gates are constructed with P and N channel

enhancement mode devices in a single monolithic structure (Complemen-

tary MOS). Their primary use is where low power dissipation and/or high

noise immunity is desired.

•Supply Voltage Range = 3.0 Vdc to 18 Vdc

•All Outputs Buffered

•Capable of Driving Two Low–power TTL Loads or One Low–power

Schottky TTL Load Over the Rated Temperature Range.

•Double Diode Protection on All Inputs Except: Triple Diode Protection

on MC14011B and MC14081B

•Pin–for–Pin Replacements for Corresponding CD4000 Series B Suffix

Devices (Exceptions: MC14068B and MC14078B)

L SUFFIX

CERAMIC

CASE 632

ORDERING INFORMATION

MC14XXXBCP Plastic

MC14XXXBCL Ceramic

MC14XXXBD SOIC

TA = – 55° to 125°C for all packages.

P SUFFIX

PLASTIC

CASE 646

D SUFFIX

SOIC

CASE 751A

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

MAXIMUM RATINGS* (Voltages Referenced to VSS)

ÎÎÎÎ

Symbol

ÎÎÎÎÎÎÎÎÎÎÎ

Parameter

ÎÎÎÎÎÎ

Value

ÎÎÎ

Unit

ÎÎÎÎ

VDD

ÎÎÎÎÎÎÎÎÎÎÎ

DC Supply Voltage

ÎÎÎÎÎÎ

– 0.5 to + 18.0

ÎÎÎ

ÎÎÎÎ

Vin, Vout

ÎÎÎÎÎÎÎÎÎÎÎ

Input or Output Voltage (DC or Transient)

ÎÎÎÎÎÎ

– 0.5 to VDD + 0.5

ÎÎÎ

ÎÎÎÎ

lin, lout

ÎÎÎÎÎÎÎÎÎÎÎ

Input or Output Current (DC or Transient),

per Pin

ÎÎÎÎÎÎ

± 10

ÎÎÎ

ÎÎÎÎ

ÎÎÎÎÎÎÎÎÎÎÎ

Power Dissipation, per Package†

ÎÎÎÎÎÎ

500

ÎÎÎ

ÎÎÎÎ

Tstg

ÎÎÎÎÎÎÎÎÎÎÎ

Storage Temperature

ÎÎÎÎÎÎ

– 65 to + 150

ÎÎÎ

ÎÎÎÎ

ÎÎÎÎÎÎÎÎÎÎÎ

Lead Temperature (8–Second Soldering)

ÎÎÎÎÎÎ

260

ÎÎÎ

*Maximum Ratings are those values beyond which damage to the device may occur.

†Temperature Derating:

Plastic “P and D/DW” Packages: – 7.0 mW/

C From 65

C To 125

Ceramic “L” Packages: – 12 mW/

C From 100

C To 125

This device contains protection circuitry to guard against damage

due to high static voltages or electric fields. However , precautions must

be taken to avoid applications of any voltage higher than maximum rated

voltages to this high-impedance circuit. For proper operation, Vin and

Vout should be constrained to the range VSS ≤ (Vin or Vout) ≤ VDD.

Unused inputs must always be tied to an appropriate logic voltage

level (e.g., either VSS or VDD). Unused outputs must be left open.



SEMICONDUCTOR TECHNICAL DATA

 Motorola, Inc. 1995

REV 3

1/94

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MOTOROLA CMOS LOGIC DATAMC14001B

LOGIC DIAGRAMS

2 INPUT

3 INPUT

12 10

4 INPUT

11 13

13 13

8 INPUT

NC = 6, 8 NC = 6, 8 NC = 6, 8 NC = 6, 8

NC = 6, 8 NC = 6, 8

VDD = PIN 14

VSS = PIN 7

FOR ALL DEVICES

NOR

MC14001B

Quad 2–Input NOR Gate

MC14025B

Triple 3–Input NOR Gate

MC14002B

Dual 4–Input NOR Gate

MC14078B

8–Input NOR Gate MC14068B

8–Input NAND Gate

MC14012B

Dual 4–Input NAND Gate

MC14023B

Triple 3–Input NAND Gate

NAND

MC14011B

Quad 2–Input NAND Gate

MC14071B

Quad 2–Input OR Gate

AND

MC14081B

Quad 2–Input AND Gate

MC14075B

Triple 3–Input OR Gate MC14073B

Triple 3–Input AND Gate

MC14072B

Dual 4–Input OR Gate MC14082B

Dual 4–Input AND Gate

MOTOROLA CMOS LOGIC DATA 9

MC14001B

PIN ASSIGNMENTS

105

OUTC

OUTD

IN 1D

IN 2D

VDD

IN 1C

IN 2C

OUTB

OUTA

IN 2A

IN 1A

VSS

IN 2B

IN 1B

105

IN 2B

IN 3B

IN 4B

OUTB

VDD

IN 1B

IN 3A

IN 2A

IN 1A

OUTA

VSS

IN 4A

105

OUTC

OUTD

IN 1D

IN 2D

VDD

IN 1C

IN 2C

OUTB

OUTA

IN 2A

IN 1A

VSS

IN 2B

IN 1B

105

IN 2B

IN 3B

IN 4B

OUTB

VDD

IN 1B

IN 3A

IN 2A

IN 1A

OUTA

VSS

IN 4A

105

OUTC

IN 1C

IN 2C

IN 3C

VDD

IN 3A

OUTA

IN 2B

IN 1B

IN 2A

IN 1A

VSS

OUTB

IN 3B

105

OUTC

IN 1C

IN 2C

IN 3C

VDD

IN 3A

OUTA

IN 2B

IN 1B

IN 2A

IN 1A

VSS

OUTB

IN 3B

105

IN 6

IN 7

IN 8

OUT

VDD

IN 5

IN 3

IN 2

IN 1

VSS

IN 4

105

OUTC

OUTD

IN 1D

IN 2D

VDD

IN 1C

IN 2C

OUTB

OUTA

IN 2A

IN 1A

VSS

IN 2B

IN 1B

105

IN 2B

IN 3B

IN 4B

OUTB

VDD

IN 1B

IN 3A

IN 2A

IN 1A

OUTA

VSS

IN 4A

105

OUTC

IN 1C

IN 2C

IN 3C

VDD

IN 3A

OUTA

IN 2B

IN 1B

IN 2A

IN 1A

VSS

OUTB

IN 3B

105

IN 6

IN 7

IN 8

OUT

VDD

IN 5

IN 3

IN 2

IN 1

VSS

IN 4

105

OUTC

IN 1C

IN 2C

IN 3C

VDD

IN 3A

OUTA

IN 2B

IN 1B

IN 2A

IN 1A

VSS

OUTB

IN 3B

105

OUTC

OUTD

IN 1D

IN 2D

VDD

IN 1C

IN 2C

OUTB

OUTA

IN 2A

IN 1A

VSS

IN 2B

IN 1B

105

IN 2B

IN 3B

IN 4B

OUTB

VDD

IN 1B

IN 3A

IN 2A

IN 1A

OUTA

VSS

IN 4A

NC = NO CONNECTION

MC14012B

Dual 4–Input NAND Gate

MC14023B

Triple 3–Input NAND Gate

MC14001B

Quad 2–Input NOR Gate MC14002B

Dual 4–Input NOR Gate MC14011B

Quad 2–Input NAND Gate

MC14078B

8–Input NOR Gate

MC14082B

Dual 4–Input AND Gate

MC14081B

Quad 2–Input AND Gate

MC14025B

Triple 3–Input NOR Gate MC14068B

8–Input NAND Gate MC14071B

Quad 2–Input OR Gate

MC14072B

Dual 4–Input OR Gate MC14073B

Triple 3–Input AND Gate MC14075B

Triple 3–Input OR Gate

MOTOROLA CMOS LOGIC DATAMC14001B

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)

ÎÎÎÎÎÎÎÎÎÎ

Characteristic

ÎÎÎÎ

Symbol

ÎÎÎ

VDD

Vdc

ÎÎÎÎÎÎ

– 55

ÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎ

125

ÎÎÎ

Unit

ÎÎÎÎÎÎÎÎÎÎ

Characteristic

ÎÎÎÎ

Symbol

ÎÎÎ

VDD

Vdc

ÎÎÎ

Min

ÎÎÎÎ

Max

ÎÎÎ

Min

ÎÎÎÎ

Typ #

ÎÎÎ

Max

ÎÎÎÎ

Min

ÎÎÎ

Max

ÎÎÎ

Unit

ÎÎÎÎÎÎÎÎÎÎ

Output Voltage “0” Level

Vin = VDD or 0

ÎÎÎÎ

VOL

ÎÎÎ

5.0

ÎÎÎ

—

ÎÎÎÎ

0.05

ÎÎÎ

—

ÎÎÎÎ

ÎÎÎ

0.05

ÎÎÎÎ

—

ÎÎÎ

0.05

ÎÎÎ

Vdc

ÎÎÎÎÎÎÎÎÎÎ

“1” Level

Vin = 0 or VDD

ÎÎÎÎ

VOH

ÎÎÎ

5.0

ÎÎÎ

4.95

9.95

14.95

ÎÎÎÎ

—

ÎÎÎ

4.95

9.95

14.95

ÎÎÎÎ

5.0

ÎÎÎ

—

ÎÎÎÎ

4.95

9.95

14.95

ÎÎÎ

—

ÎÎÎ

Vdc

ÎÎÎÎÎÎÎÎÎÎ

Input Voltage “0” Level

(VO = 4.5 or 0.5 Vdc)

(VO = 9.0 or 1.0 Vdc)

(VO = 13.5 or 1.5 Vdc)

ÎÎÎÎ

VIL

ÎÎÎ

5.0

ÎÎÎ

—

ÎÎÎÎ

1.5

3.0

4.0

ÎÎÎ

—

ÎÎÎÎ

2.25

4.50

6.75

ÎÎÎ

1.5

3.0

4.0

ÎÎÎÎ

—

ÎÎÎ

1.5

3.0

4.0

ÎÎÎ

Vdc

ÎÎÎÎÎÎÎÎÎÎ

“1” Level

(VO = 0.5 or 4.5 Vdc)

(VO = 1.0 or 9.0 Vdc)

(VO = 1.5 or 13.5 Vdc)

ÎÎÎÎ

VIH

ÎÎÎ

5.0

ÎÎÎ

3.5

7.0

ÎÎÎÎ

—

ÎÎÎ

3.5

7.0

ÎÎÎÎ

2.75

5.50

8.25

ÎÎÎ

—

ÎÎÎÎ

3.5

7.0

ÎÎÎ

—

ÎÎÎ

Vdc

ÎÎÎÎÎÎÎÎÎÎ

Output Drive Current

(VOH = 2.5 Vdc) Source

(VOH = 4.6 Vdc)

(VOH = 9.5 Vdc)

(VOH = 13.5 Vdc)

ÎÎÎÎ

IOH

ÎÎÎ

5.0

ÎÎÎ

– 3.0

– 0.64

– 1.6

– 4.2

ÎÎÎÎ

—

ÎÎÎ

– 2.4

– 0.51

– 1.3

– 3.4

ÎÎÎÎ

– 4.2

– 0.88

– 2.25

– 8.8

ÎÎÎ

—

ÎÎÎÎ

– 1.7

– 0.36

– 0.9

– 2.4

ÎÎÎ

—

ÎÎÎ

mAdc

ÎÎÎÎÎÎÎÎÎÎ

(VOL = 0.4 Vdc) Sink

(VOL = 0.5 Vdc)

(VOL = 1.5 Vdc)

ÎÎÎÎ

IOL

ÎÎÎ

5.0

ÎÎÎ

0.64

1.6

4.2

ÎÎÎÎ

—

ÎÎÎ

0.51

1.3

3.4

ÎÎÎÎ

0.88

2.25

8.8

ÎÎÎ

—

ÎÎÎÎ

0.36

0.9

2.4

ÎÎÎ

—

ÎÎÎ

mAdc

ÎÎÎÎÎÎÎÎÎÎ

Input Current

ÎÎÎÎ

Iin

ÎÎÎ

—

ÎÎÎÎ

± 0.1

ÎÎÎ

—

ÎÎÎÎ

±0.00001

ÎÎÎ

± 0.1

ÎÎÎÎ

—

ÎÎÎ

± 1.0

ÎÎÎ

µAdc

ÎÎÎÎÎÎÎÎÎÎ

Input Capacitance

(Vin = 0)

ÎÎÎÎ

Cin

ÎÎÎ

—

ÎÎÎ

—

ÎÎÎÎ

—

ÎÎÎ

—

ÎÎÎÎ

5.0

ÎÎÎ

7.5

ÎÎÎÎ

—

ÎÎÎ

—

ÎÎÎ

ÎÎÎÎÎÎÎÎÎÎ

Quiescent Current

(Per Package)

ÎÎÎÎ

IDD

ÎÎÎ

5.0

ÎÎÎ

—

ÎÎÎÎ

0.25

0.5

1.0

ÎÎÎ

—

ÎÎÎÎ

0.0005

0.0010

0.0015

ÎÎÎ

0.25

0.5

1.0

ÎÎÎÎ

—

ÎÎÎ

7.5

ÎÎÎ

µAdc

ÎÎÎÎÎÎÎÎÎÎ

Total Supply Current**†

(Dynamic plus Quiescent,

Per Gate, CL = 50 pF)

ÎÎÎÎ

ÎÎÎ

5.0

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

IT = (0.3 µA/kHz) f + IDD/N

IT = (0.6 µA/kHz) f + IDD/N

IT = (0.9 µA/kHz) f + IDD/N

ÎÎÎ

µAdc

#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’ s potential performance.

**The formulas given are for the typical characteristics only at 25

†To calculate total supply current at loads other than 50 pF:

IT(CL) = IT(50 pF) + (CL – 50) Vfk

where: IT is in µA (per package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency , and k = 0.001 x the number of exercised gates per

package.

MOTOROLA CMOS LOGIC DATA 11

MC14001B

B–SERIES GATE SWITCHING TIMES

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

SWITCHING CHARACTERISTICS* (CL = 50 pF, TA = 25

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Characteristic

ÎÎÎÎ

Symbol

ÎÎÎÎÎ

VDD

Vdc

ÎÎÎÎ

Min

ÎÎÎÎ

Typ #

ÎÎÎÎ

Max

ÎÎÎ

Unit

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Output Rise Time, All B–Series Gates

tTLH = (1.35 ns/pF) CL + 33 ns

tTLH = (0.60 ns/pF) CL + 20 ns

tTLH = (0.40 ns/PF) CL + 20 ns

ÎÎÎÎ

tTLH

ÎÎÎÎÎ

5.0

ÎÎÎÎ

—

ÎÎÎÎ

100

ÎÎÎÎ

200

100

ÎÎÎ

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Output Fall Time, All B–Series Gates

tTHL = (1.35 ns/pF) CL + 33 ns

tTHL = (0.60 ns/pF) CL + 20 ns

tTHL = (0.40 ns/pF) CL + 20 ns

ÎÎÎÎ

tTHL

ÎÎÎÎÎ

5.0

ÎÎÎÎ

—

ÎÎÎÎ

100

ÎÎÎÎ

200

100

ÎÎÎ

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Propagation Delay Time

MC14001B, MC14011B only

tPLH, tPHL = (0.90 ns/pF) CL + 80 ns

tPLH, tPHL = (0.36 ns/pF) CL + 32 ns

tPLH, tPHL = (0.26 ns/pF) CL + 27 ns

All Other 2, 3, and 4 Input Gates

tPLH, tPHL = (0.90 ns/pF) CL + 115 ns

tPLH, tPHL = (0.36 ns/pF) CL + 47 ns

tPLH, tPHL = (0.26 ns/pF) CL + 37 ns

8–Input Gates (MC14068B, MC14078B)

tPLH, tPHL = (0.90 ns/pF) CL + 155 ns

tPLH, tPHL = (0.36 ns/pF) CL + 62 ns

tPLH, tPHL = (0.26 ns/pF) CL + 47 ns

ÎÎÎÎ

tPLH, tPHL

ÎÎÎÎÎ

5.0

ÎÎÎÎ

—

ÎÎÎÎ

125

160

200

ÎÎÎÎ

250

100

300

130

100

350

150

110

ÎÎÎ

*The formulas given are for the typical characteristics only at 25

#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’ s potential performance.

VDD

VSS

PULSE

GENERATOR

INPUT OUTPUT

90%

50%

10%

50%

90%

20 ns 20 ns

tPHL tPLH

tTLH

tTHL VOL

VOH

0 V

VDD

INPUT

OUTPUT

INVERTING

*All unused inputs of AND, NAND gates must be connected to VDD.

All unused inputs of OR, NOR gates must be connected to VSS.

90%

50%

10% VOL

VOH

OUTPUT

NON–INVERTING tTHL

tTLH

tPLH tPHL

Figure 1. Switching Time Test Circuit and Waveforms

MOTOROLA CMOS LOGIC DATAMC14001B

CIRCUIT SCHEMATIC

NOR, OR GATES

VSS

3, 4, 10, 11

VDD

VSS

VDD

*Inverter omitted in MC14001B

1, 6, 8, 13

2, 5, 9, 12

9, 6, 10

VSS

VDD

1, 3, 11

2, 4, 12

VSS

VDD

VSS

VDD

*Inverter omitted in MC14025B

8, 5, 13

1, 13

VSS

VDD

3, 9

2, 10

VSS

VDD

*Inverter omitted in MC14002B

SAME AS

ABOVE

5, 11

4, 12

VSS

VDD

VSS

VDD

SAME AS

ABOVE

SAME AS

ABOVE

SAME AS

ABOVE

MC14001B, MC14071B

One of Four Gates Shown

MC14025B, MC14075B

One of Three Gates Shown

MC14002B, MC14072B

One of Two Gates Shown

MC14078B

Eight Input Gate

MOTOROLA CMOS LOGIC DATA 13

MC14001B

CIRCUIT SCHEMATIC

NAND, AND GATES

3, 4, 10, 11

VSS

VDD

*Inverter omitted in MC14011B

9, 6, 10

VSS

VDD

*Inverter omitted in MC14023B

2, 5, 9, 12

1, 6, 8, 13

2, 4, 12

1, 3, 11

VDD

VSS

8, 5, 13

1, 13

VSS

VDD

*Inverter omitted in MC14012B

2, 10

3, 9

VDD

VSS

SAME AS

ABOVE

4, 12

5, 11

VSS

VDD

VSS

VDD

VSS

VDD

VSS

SAME AS

ABOVE

SAME AS

ABOVE

SAME AS

ABOVE

MC14011B, MC14081B

One of Four Gates Shown

MC14023B, MC14073B

One of Three Gates Shown

MC14012B, MC14082B

One of Two Gates Shown

MC14068B

Eight Input Gate

MOTOROLA CMOS LOGIC DATAMC14001B

TYPICAL B–SERIES GATE CHARACTERISTICS

N–CHANNEL DRAIN CURRENT

(SINK) P–CHANNEL DRAIN CURRENT

(SOURCE)

– 40

+ 85

+ 125

Figure 2. VGS = 5.0 Vdc Figure 3. VGS = – 5.0 Vdc

1.0

3.0

5.0

4.0

2.0

01.0 3.0 5.04.02.00

VDS, DRAIN–TO–SOURCE VOLTAGE (Vdc)

– 1.0

TA = – 55

Figure 4. VGS = 10 Vdc Figure 5. VGS = – 10 Vdc

8.0

6.0

4.0

2.0

05.03.01.0 108.06.04.02.00 00

Figure 6. VGS = 15 Vdc Figure 7. VGS = – 15 Vdc

0000

– 40

+ 25

+ 85

+ 125

– 1.0 – 3.0 – 5.0– 4.0– 2.0

VDS, DRAIN–TO–SOURCE VOLTAGE (Vdc)

TA = – 55

+ 25

TA = – 55

– 40

+ 25

+ 85

+ 125

VDS, DRAIN–TO–SOURCE VOLTAGE (Vdc) VDS, DRAIN–TO–SOURCE VOLTAGE (Vdc)

TA = – 55

– 40

+ 25

C+ 85

+ 125

9.07.0 – 5.0– 3.0– 1.0 – 10– 8.0– 6.0– 4.0– 2.0 – 9.0– 7.0

– 40

– 35

– 30

– 25

– 20

– 15

– 10

– 5.0

– 45

– 50

106.02.0 2016128.04.0 1814

TA = – 55

– 40

+ 25

C+ 85

– 10– 6.0– 2.0 – 20– 16– 12– 8.0– 4.0 – 18– 14

– 80

– 70

– 60

– 50

– 40

– 30

– 20

– 10

– 90

– 100

5.0

TA = – 55

C– 40

+ 25

C+ 85

– 2.0

– 3.0

– 4.0

– 5.0

– 6.0

– 7.0

– 8.0

– 9.0

– 10

I ,

DDRAIN CURRENT (mA)

I ,

DDRAIN CURRENT (mA)

I ,

DDRAIN CURRENT (mA)

I ,

DDRAIN CURRENT (mA)

I ,

DDRAIN CURRENT (mA)

I ,

DDRAIN CURRENT (mA)

+ 125

These typical curves are not guarantees, but are design aids.

Caution: The maximum rating for output current is 10 mA per pin.

MOTOROLA CMOS LOGIC DATA 15

MC14001B

TYPICAL B–SERIES GATE CHARACTERISTICS (cont’d)

VOLTAGE TRANSFER CHARACTERISTICS

Figure 8. VDD = 5.0 Vdc Figure 9. VDD = 10 Vdc

1.0

3.0

5.0

4.0

2.0

01.0 3.0 5.04.02.00 00

Vin, INPUT VOLTAGE (Vdc)

SINGLE INPUT NAND, AND

MULTIPLE INPUT NOR, OR

SINGLE INPUT NOR, OR

MULTIPLE INPUT NAND, AND

SINGLE INPUT NAND, AND

MULTIPLE INPUT NOR, OR

SINGLE INPUT NOR, OR

MULTIPLE INPUT NAND, AND

2.0

6.0

8.0

4.0

2.0 6.0 108.04.0 Vin, INPUT VOLTAGE (Vdc)

V ,

out OUTPUT VOLTAGE (Vdc)

V ,

out OUTPUT VOLTAGE (Vdc)

Figure 10. VDD = 15 Vdc

SINGLE INPUT NAND, AND

MULTIPLE INPUT NOR, OR

SINGLE INPUT NOR, OR

MULTIPLE INPUT NAND, AND

2.0

6.0

8.0

4.0

2.0 6.0 108.04.0 Vin, INPUT VOLTAGE (Vdc)

V ,

out OUTPUT VOLTAGE (Vdc)

DC NOISE MARGIN

The DC noise margin is defined as the input voltage range

from an ideal “1” or “0” input level which does not produce

output state change(s). The typical and guaranteed limit val-

ues of the input values VIL and VIH for the output(s) to be at a

fixed voltage VO are given in the Electrical Characteristics

table. VIL and VIH are presented graphically in Figure 11.

Guaranteed minimum noise margins for both the “1” and

“0” levels =

1.0 V with a 5.0 V supply

2.0 V with a 10.0 V supply

2.5 V with a 15.0 V supply

Figure 11. DC Noise Immunity

Vout

VIL

VIH

Vin

VDD

VDD Vout

VIL

VIH

Vin

VDD

(a) Inverting Function (b) Non–Inverting Function

VSS = 0 VOLTS DC

MOTOROLA CMOS LOGIC DATAMC14001B

OUTLINE DIMENSIONS

L SUFFIX

CERAMIC DIP PACKAGE

CASE 632–08

ISSUE Y

DIM MIN MAX MIN MAX

MILLIMETERSINCHES

A0.750 0.785 19.05 19.94

B0.245 0.280 6.23 7.11

C0.155 0.200 3.94 5.08

D0.015 0.020 0.39 0.50

F0.055 0.065 1.40 1.65

G0.100 BSC 2.54 BSC

J0.008 0.015 0.21 0.38

K0.125 0.170 3.18 4.31

L0.300 BSC 7.62 BSC

M0 15 0 15

N0.020 0.040 0.51 1.01

____

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

3. DIMENSION L TO CENTER OF LEAD WHEN

FORMED PARALLEL.

4. DIMENSION F MAY NARROW TO 0.76 (0.030)

WHERE THE LEAD ENTERS THE CERAMIC

BODY.

–A–

–B–

14 PLDGF N

14 PLJM

0.25 (0.010) T

–T–

SEATING

PLANE

1 7

14 9

P SUFFIX

PLASTIC DIP PACKAGE

CASE 646–06

ISSUE L

NOTES:

1. LEADS WITHIN 0.13 (0.005) RADIUS OF TRUE

POSITION AT SEATING PLANE AT MAXIMUM

MATERIAL CONDITION.

2. DIMENSION L TO CENTER OF LEADS WHEN

FORMED PARALLEL.

3. DIMENSION B DOES NOT INCLUDE MOLD

FLASH.

4. ROUNDED CORNERS OPTIONAL.

1 7

14 8

H G D K

SEATING

PLANE

DIM MIN MAX MIN MAX

MILLIMETERSINCHES

A0.715 0.770 18.16 19.56

B0.240 0.260 6.10 6.60

C0.145 0.185 3.69 4.69

D0.015 0.021 0.38 0.53

F0.040 0.070 1.02 1.78

G0.100 BSC 2.54 BSC

H0.052 0.095 1.32 2.41

J0.008 0.015 0.20 0.38

K0.115 0.135 2.92 3.43

L0.300 BSC 7.62 BSC

M0 10 0 10

N0.015 0.039 0.39 1.01

_ _ _ _

MOTOROLA CMOS LOGIC DATA 17

MC14001B

OUTLINE DIMENSIONS

D SUFFIX

PLASTIC SOIC PACKAGE

CASE 751A–03

ISSUE F

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSIONS A AND B DO NOT INCLUDE

MOLD PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)

PER SIDE.

5. DIMENSION D DOES NOT INCLUDE DAMBAR

PROTRUSION. ALLOWABLE DAMBAR

PROTRUSION SHALL BE 0.127 (0.005) TOTAL

IN EXCESS OF THE D DIMENSION AT

MAXIMUM MATERIAL CONDITION.

–A–

–B–

P7 PL

14 8

71 M

0.25 (0.010) B M

0.25 (0.010) A S

–T–

RX 45

SEATING

PLANE

D14 PL K

DIM MIN MAX MIN MAX

INCHESMILLIMETERS

A8.55 8.75 0.337 0.344

B3.80 4.00 0.150 0.157

C1.35 1.75 0.054 0.068

D0.35 0.49 0.014 0.019

F0.40 1.25 0.016 0.049

G1.27 BSC 0.050 BSC

J0.19 0.25 0.008 0.009

K0.10 0.25 0.004 0.009

M0 7 0 7

P5.80 6.20 0.228 0.244

R0.25 0.50 0.010 0.019

_ _ _ _

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MC14001B/D

*MC14001B/D*

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