SiP41103 New Product Vishay Siliconix Half-Bridge N-Channel MOSFET Driver for DC/DC Conversion FEATURES APPLICATIONS D D D D D D D D D D D D D D 5-V Gate Drive Undervoltage Lockout Internal Bootstrap Diode Adaptive Shoot-Through Protection Syncronous MOSFET Disable Adjustable Highside Propagation Delay Switching Frequency Up to 1 MHz Drive MOSFETs In 4.5- to 55-V Systems Multi-Phase DC/DC Conversion High Current Synchronous Buck Converters High Frequency Synchronous Buck Converters Asynchronous-to-Synchronous Adaptations Mobile Computer DC/DC Converters Desktop Computer DC/DC Converters DESCRIPTION SiP41103 is a high-speed half-bridge MOSFET driver with adaptive shoot-through protection for use in high frequency, high current, multiphase dc-dc synchronous rectifier buck power supplies. It is designed to operate at switching frequencies up to 1 MHz. The high-side driver is bootstrapped to allow driving n-channel MOSFETs. SiP41103 comes with adaptive shoot-through protection to prevent simultaneous conduction of the external MOSFETs. The SiP41103 is available in an 10-Pin MLP-33 package for operation over the industrial operating range (-40C to 85C) FUNCTIONAL BLOCK DIAGRAM +5 to 55 V +5 V VDD BOOT DELAY OUTH SiP41103 PWM LX VOUT Controller ENSYNC OUTL GND GND Document Number: 72718 S-32672--Rev. A, 29-Dec-03 GND www.vishay.com 1 SiP41103 New Product Vishay Siliconix ABSOLUTE MAXIMUM RATINGS (ALL VOLTAGES REFERENCED TO GND = 0 V) VDD, PWM, ENSYNC, DELAY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V LX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 V BOOT to LX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 40 to 150_C Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125_C Power Dissipationa,b MLP-33 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 960 mW Thermal Impedance (QJA)a,b MLP-33 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105_C/W Notes a. Device mounted with all leads soldered or welded to PC board. a. Derate 9.6 mW/_C Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. RECOMMENDED OPERATING RANGE (ALL VOLTAGES REFERENCED TO GND = 0 V) VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.5 V to 5.5 V CBOOT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 nF to 1 mF VBOOT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.5 V to 55 V Operating Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . - 40 to 85_C SPECIFICATIONSa Test Conditions Unless Specified Parameter Symbol VDD = 5 V, VBOOT - VLX = 5 V, CLOAD = 3 nF TA = - 40 to 85_C Limits Mina Typb Maxa Unit Power Supplies Supply Voltage VDD Quiescent Current IDDQ 4.5 fPWM = 1 MHz, CLOAD = 0 2.3 5.5 V 3.0 mA Reference Voltage Break-Before-Make VBBM 1 V PWM Input Input High VIH Input Low VIL Bias Current IB 4.0 VDD 0.5 "0.3 "1 V mA ENSYNC Inputs Input High VIH Input Low VIL 2.0 VDD 1.0 Bias Current IB "1 mA V High-Side Undervoltage Lockout Threshold VUVHS Rising or Falling 2.5 3.35 3.75 V VF IF = 10 mA, TA = 25_C 0.6 0.65 0.7 V IPKH(source) 0.9 1.1 IPKH(sink) 1.1 1.4 IPKL(source) 0.8 1.1 Bootstrap Diode Forward Voltage MOSFET Drivers High-Side Drive Currentc Low-Side Drive Currentc High Side Driver Impedance High-Side Low Side Driver Impedance Low-Side www.vishay.com 2 A IPKL(sink) 1.5 1.9 RDH(source) 1.7 2.5 3.8 RDH(sink) 1.5 2.2 3.3 RDL(source) 2.3 3.4 5.1 RDL(sink) 1.0 1.4 2.1 W Document Number: 72718 S-32672--Rev. A, 29-Dec-03 SiP41103 New Product Vishay Siliconix SPECIFICATIONSa Test Conditions Unless Specified Symbol VDD = 5 V, VBOOT - VLX = 5 V, CLOAD = 3 nF TA = - 40 to 85_C High-Side Rise Time trH High-Side Fall Time tfH Parameter Limits Mina Typb Maxa 10% - 90% 32 40 90% - 10% 36 45 td(off)H See Timing Waveforms 20 td(on)H See Timing Waveforms 30 trL 10% - 90% 45 55 30 Unit MOSFET Drivers High Side Propagation Delayc High-Side Low-Side Rise Time Low-Side Fall Time Low Side Propagation Delayc Low-Side tfL 90% - 10% 20 td(off)L See Timing Waveforms 30 td(on)L See Timing Waveforms 30 ns LX Timer LX Falling Timeoutc tLX 420 ns VDD Undervoltage Lockout Threshold Rising VUVLOR Threshold Falling VUVLOF 4.3 3.7 4.5 4.1 Hysteresis 0.4 Power on Reset Timec 2.5 V ms Thermal Shutdown Temperature TSD Temperature Rising 165 Hysteresis TH Temperature Falling 25 _C Notes a. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum (- 40_ to 85_C). b. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing and are measured at VCC = 5 V unless otherwise noted. c. Guaranteed by design. TIMING WAVEFORMS PWM 90% 10% 90% OUTH 10% 90% 10% OUTL td(off)H 10% td(off)L td(on)H td(on)L Document Number: 72718 S-32672--Rev. A, 29-Dec-03 www.vishay.com 3 SiP41103 New Product Vishay Siliconix PIN CONFIGURATION AND TRUTH TABLE TRUTH TABLE MLP33 OUTH BOOT PWM DELAY GND 10 9 8 7 6 2 3 4 5 PWM LX ENSYNC NC VDD OUTL ENSYNC OUTH OUTL L L L L L H L H H X H L Top View ORDERING INFORMATION Part Number Temperature Range Marking SiP41103DM-T1 - 40 to 85_C 41103 Eval Kit Temperature Range SiP41103DB - 40 to 85_C PIN DESCRIPTION Pin Number Name 1 OUTH High-side MOSFET gate drive 2 BOOT Bootstrap supply for high-side driver. A capacitor connects between BOOT and LX. 3 PWM Input signal for the MOSFET drivers 4 DELAY 5 GND Ground 6 OUTL Synchronous or low-side MOSFET gate drive 7 VDD +5-V supply 8 NC No Connect 9 ENSYNC 10 LX www.vishay.com 4 Function Connection for the highside delay adjustment capacitor. Enables OUTL, the driver for the synchronus MOSFET Connection to source of high-side MOSFET, drain of the low-side MOSFET, and the inductor Document Number: 72718 S-32672--Rev. A, 29-Dec-03 SiP41103 New Product Vishay Siliconix FUNCTIONAL BLOCK DIAGRAM VDD BOOT OUTH UVLO OTP LX DELAY + DELAY VBBM PWM ENSYNC VDD OUTL GND Figure 1. DETAILED OPERATION PWM The PWM pin controls the switching of the external MOSFETs. The driver logic operates in a noninverting configuration. The PWM input stage should be driven by a signal with fast transition times, like those provided by a PWM controller or logic gate, (<200 ns). The PWM input functions as a logic input and is not intended for applications where a slow changing input voltage is used to generate a switching output when the input switching threshold voltage is reached. Low-Side Driver The supplies for the low-side driver are VDD and GND. During shutdown, OUTL is held low. integrated bootstrap diode replaces the external Schottky diode needed for the bootstrap circuit; only a capacitor is necessary to complete the bootstrap circuit. The bootstrap capacitor is sized according to, CBOOT = (QGATE/DVBOOT - LX) x 10 where QGATE is the gate charge needed to turn on the high-side MOSFET and DVBOOT - LX is the amount of droop allowed in the bootstrapped supply voltage when the high-side MOSFET is driven high. The bootstrap capacitor value is typically 0.1 mF to 1 mF. The bootstrap capacitor voltage rating must be greater than VDD + 5 V to withstand transient spikes and ringing. Shoot-Through Protection High-Side Driver The high-side driver is isolated from the substrate to create a floating high-side driver so that an n-channel MOSFET can be used for the high-side switch. The supplies for the high-side driver are BOOT and LX. The voltage is supplied by a floating bootstrap capacitor, which is continually recharged by the switching action of the output. During shutdown OUTH is held low. Bootstrap Circuit The internal bootstrap diode and a bootstrap capacitor form a charge pump that supplies voltage to the BOOT pin. An Document Number: 72718 S-32672--Rev. A, 29-Dec-03 The external MOSFETs are prevented from conducting at the same time during transitions. Break-before-make circuits monitor the voltages on the LX pin and the OUTL pin and control the switching as follows: When the signal on PWM goes low, OUTH will go low after an internal propagation delay. After the voltage on LX falls below 1 V by the inductor action, the low-side driver is enabled and OUTL goes high after some delay. When the signal on PWM goes high, OUTL will go low after an internal propagation delay. After the voltage on OUTL drops below 1 V the high-side driver is enabled and OUTH will go high after an internal propagation delay. If LX does not drop below 1 V within 400 ns after OUTH goes low, OUTL is forced high until the next PWM transition. www.vishay.com 5 SiP41103 New Product Vishay Siliconix VDD Bypass Capacitor Delay The addition of a capacitor between DELAY and GND will increase the propagation delay time for OUTH going high. Delay capacitance may be added to prevent shoot through current in the low-side MOSFET due to the finite time between OUTL going low and the continuing conduction of the low-side MOSFET. Choose a MOSFET with lower gate resistance to reduce this effect. If necessary, choose a capacitor value that prevents MOSFET conduction under worst-case temperature and manufacturing conditions. Propagation delay is increased according to the ratio of 1.2 ns/pF. Synchronous MOSFET Enable Under light load conditions, efficiency can be increased by disabling the synchronous MOSFET, thus avoiding the gate charge losses of the synchronous MOSFET. When ENSYNC is low, OUTL is forced low. When high, the low-side driver operates normally. ENSYNC should be driven by a 5-V signal. MOSFET drivers draw large peak currents from the supplies when they switch. A local bypass capacitor is required to supply this current and reduce power supply noise. Connect a 1-mF ceramic capacitor as close as practical between the VDD and GND pins. Undervoltage Lockout Undervoltage lockout prevents control of the circuit until the supply voltages reach valid operating levels. The UVLO circuit forces OUTL and OUTH to low when VDD is below its specified voltage. A separate UVLO forces OUTH low when the voltage between BOOT and LX is below the specified voltage. Thermal Protection Shutdown The driver enters shutdown mode when a period of inactivity on PWM elapses. Shutdown current is less than 1 mA. If the die temperature rises above 165_C, the thermal protection disables the drivers. The drivers are re-enabled after the die temperature has decreased below 140_C. TYPICAL CHARACTERISTICS Highside Turn On Delay vs.CDELAY IDD vs. CLOAD vs. Frequency 140.0 50 120.0 40 td(on)H(ns) IDD (mA) 100.0 30 1 MHz 500 kHz 80.0 60.0 20 40.0 200 kHz 10 20.0 0.0 0 0 1 2 3 CLOAD (nF) www.vishay.com 6 4 5 0 10 20 30 40 50 60 70 80 90 100 110 CDelay (pF) Document Number: 72718 S-32672--Rev. A, 29-Dec-03 SiP41103 New Product Vishay Siliconix TYPICAL WAVEFORMS Figure 2. PWM Signal vs. LX (Rising) Figure 3. PWM Signal vs. LX (Falling) PWM IN 2 V/div PWM IN 2 V/div VLX 2 V/div VLX 2 V/div 50 ns/div 50 ns/div Figure 4. PWM Signal vs. HS Gate and LS Gate (Rising) Figure 5. PWM IN 5 V/div PWM IN 5 V/div HS Gate 5 V/div HS Gate 5 V/div LS Gate 5 V/div LS Gate 5 V/div 50 ns/div Figure 6. PWM Signal vs. HS Gate and LS Gate (Falling) 50 ns/div ENSYNC Delay ENSYNC 5 V/div HS Gate 5 V/div LS Gate 5 V/div 50 ms/div Document Number: 72718 S-32672--Rev. A, 29-Dec-03 www.vishay.com 7