SiP41103
Vishay Siliconix
New Product
Document Number: 72718
S-32672—Rev. A, 29-Dec-03 www.vishay.com
1
Half-Bridge N-Channel MOSFET Driver for DC/DC Conversion
FEATURES APPLICATIONS
D5-V Gate Drive
DUndervoltage Lockout
DInternal Bootstrap Diode
DAdaptive Shoot-Through Protection
DSyncronous MOSFET Disable
DAdjustable Highside Propagation Delay
DSwitching Frequency Up to 1 MHz
DDrive MOSFETs In 4.5- to 55-V Systems
DMulti-Phase DC/DC Conversion
DHigh Current Synchronous Buck Converters
DHigh Frequency Synchronous Buck Converters
DAsynchronous-to-Synchronous Adaptations
DMobile Computer DC/DC Converters
DDesktop Computer DC/DC Converters
DESCRIPTION
SiP41103 is a high-speed half-bridge MOSFET driver with
adaptive shoot-through protection for use in high frequency,
high current, multiphase dc-dc synchronous rectifier buck
power supplies. It is designed to operate at switching
frequencies up t o 1 MHz. The high-side driver is bootstrapped
to allow driving n-channel MOSFETs. SiP41103 comes with
adaptive shoot-through protection to prevent simultaneous
conduction of the external MOSFETs.
The SiP41103 is available in an 10-Pin MLP-33 package for
operation over the industrial operating range (-40°C to 85°C)
FUNCTIONAL BLOCK DIAGRAM
Controller
PWM
GND
VDD
VOUT
GND
GND
+5 V
+5 to 55 V
BOOT
OUTH
LX
OUTL
SiP41103
ENSYNC
DELAY
SiP41103
Vishay Siliconix New Product
www.vishay.com
2Document Number: 72718
S-32672—Rev. A, 29-Dec-03
ABSOLUTE MAXIMUM RATINGS (ALL VOLTAGES REFERENCED TO GND = 0 V)
VDD, PWM, ENSYNC, DELAY 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LX 60 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
BOOT to LX 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage Temperature -40 to 150_C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating Junction Temperature 125_C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power Dissipationa,b
MLP-33 960 mW. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Thermal Impedance (QJA)a,b
MLP-33 105_C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Notes
a. Device mounted with all leads soldered or welded to PC board.
a. Derate 9.6 mW/_C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation
of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING RANGE (ALL VOLTAGES REFERENCED TO GND = 0 V)
VDD 4.5 V to 5.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
VBOOT 4.5 V to 55 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CBOOT 100 nF to 1 mF. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating Temperature Range -40 to 85_C. . . . . . . . . . . . . . . . . . . . . . . . . . .
SPECIFICATIONSa
Test Conditions Unless Specified Limits
Parameter Symbol VDD = 5 V, VBOOT - VLX = 5 V, CLOAD = 3 nF
TA = -40 to 85_CMinaTypbMaxaUnit
Power Supplies
Supply Voltage VDD 4.5 5.5 V
Quiescent Current IDDQ fPWM = 1 MHz, CLOAD = 0 2.3 3.0 mA
Reference Voltage
Break-Before-Make VBBM 1 V
PWM Input
Input High VIH 4.0 VDD
V
Input Low VIL 0.5
V
Bias Current IB"0.3 "1mA
ENSYNC Inputs
Input High VIH 2.0 VDD
V
Input Low VIL 1.0 V
Bias Current IB"1mA
High-Side Undervoltage Lockout
Threshold VUVHS Rising or Falling 2.5 3.35 3.75 V
Bootstrap Diode
Forward Voltage VFIF = 10 mA, TA = 25_C 0.6 0.65 0.7 V
MOSFET Drivers
High
-
Side Drive Current
cIPKH(source) 0.9 1.1
Hi
g
h
-
Sid
e
D
r
i
ve
C
urrent
c
IPKH(sink) 1.1 1.4
A
Low
-
Side Drive Current
cIPKL(source) 0.8 1.1 A
L
ow-
Sid
e
D
r
i
ve
C
urrent
c
IPKL(sink) 1.5 1.9
High Side Driver Impedance
RDH(source) 1.7 2.5 3.8
High-Side Driver Impedance RDH(sink) 1.5 2.2 3.3
W
Low Side Driver Impedance
RDL(source) 2.3 3.4 5.1 W
Low-Side Driver Impedance RDL(sink) 1.0 1.4 2.1
td(off)H td(off)L
PWM
OUTH
OUTL
td(on)H
90%
90%
90%
10%
10%
10%
10%
td(on)L
SiP41103
Vishay Siliconix
New Product
Document Number: 72718
S-32672—Rev. A, 29-Dec-03 www.vishay.com
3
SPECIFICATIONSa
Limits
Test Conditions Unless Specified
VDD = 5 V, VBOOT - VLX = 5 V, CLOAD = 3 nF
TA = -40 to 85_C
Parameter UnitMaxa
Typb
Mina
Test Conditions Unless Specified
VDD = 5 V, VBOOT - VLX = 5 V, CLOAD = 3 nF
TA = -40 to 85_C
Symbol
MOSFET Drivers
High-Side Rise Time trH 10% - 90% 32 40
High-Side Fall Time tfH 90% - 10% 36 45
High Side Propagation Delayc
td(off)H See Timing Waveforms 20
High-Side Propagation Delayctd(on)H See Timing Waveforms 30
ns
Low-Side Rise Time trL 10% - 90% 45 55 ns
Low-Side Fall Time tfL 90% - 10% 20 30
Low Side Propagation Delayc
td(off)L See Timing Waveforms 30
Low-Side Propagation Delayctd(on)L See Timing Waveforms 30
LX T imer
LX Falling TimeoutctLX 420 ns
VDD Undervoltage Lockout
Threshold Rising VUVLOR 4.3 4.5
Threshold Falling VUVLOF 3.7 4.1 V
Hysteresis 0.4
Power on Reset Timec2.5 ms
Thermal Shutdown
Temperature TSD Temperature Rising 165 _
C
Hysteresis THTemperature Falling 25
_C
Notes
a. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum (-40_ to 85_C).
b. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing and are measured at VCC = 5 V unless otherwise noted.
c. Guaranteed by design.
TIMING WAVEFORMS
2
3
4
10
9
8
7
OUTH
BOOT
PWM
DELAY
LX
ENSYNC
NC
VDD
Top View
5
GND 6OUTL
MLP33
SiP41103
Vishay Siliconix New Product
www.vishay.com
4Document Number: 72718
S-32672—Rev. A, 29-Dec-03
PIN CONFIGURATION AND TRUTH TABLE
TRUTH TABLE
PWM ENSYNC OUTHOUTL
L L L L
L H L H
H X H L
ORDERING INFORMATION
Part Number Temperature Range Marking
SiP41103DM-T1 -40 to 85_C 41103
Eval Kit Temperature Range
SiP41103DB -40 to 85_C
PIN DESCRIPTION
Pin Number Name Function
1 OUTHHigh-side MOSFET gate drive
2 BOOT Bootstrap supply for high-side driver. A capacitor connects between BOOT and LX.
3 PWM Input signal for the MOSFET drivers
4 DELAY Connection for the highside delay adjustment capacitor.
5 GND Ground
6 OUTLSynchronous or low-side MOSFET gate drive
7 VDD +5-V supply
8 NC No Connect
9 ENSYNC Enables OUTL, the driver for the synchronus MOSFET
10 LX Connection to source of high-side MOSFET, drain of the low-side MOSFET, and the inductor
SiP41103
Vishay Siliconix
New Product
Document Number: 72718
S-32672—Rev. A, 29-Dec-03 www.vishay.com
5
FUNCTIONAL BLOCK DIAGRAM
Figure 1.
PWM
GND
VDD
OUTH
LX
OUTL
OTP
VDD
BOOT
VBBM
-
+
UVLO
DELAY
ENSYNC
DELAY
DETAILED OPERATION
PWM
The PWM pin controls the switching of the external MOSFETs.
The driver logic operates in a noninverting configuration. The
PWM input stage should be driven by a signal with fast
transition times, like those provided by a PWM controller or
logic gate, (<200 ns). The PWM input functions as a logic input
and is not intended for applications where a slow changing
input voltage is used to generate a switching output when the
input switching threshold voltage is reached.
Low-Side Driver
The supplies for the low-side driver are VDD and GND. During
shutdown, OUTL is held low.
High-Side Driver
The high-side driver is isolated from the substrate to create a
floating high-side driver so that an n-channel MOSFET can be
used for the high-side switch. The supplies for the high-side
driver are BOOT and LX. The voltage is supplied by a floating
bootstrap capacitor, which is continually recharged by the
switching action of the output. During shutdown OUTH is held
low.
Bootstrap Circuit
The internal bootstrap diode and a bootstrap capacitor form a
charge pump that supplies voltage to the BOOT pin. An
integrated bootstrap diode replaces the external Schottky
diode needed for the bootstrap circuit; only a capacitor is
necessary to complete the bootstrap circuit. The bootstrap
capacitor is sized according to,
CBOOT = (QGATE/DVBOOT - LX) x 10
where QGATE is the gate charge needed to turn on the
high-side MOSFET and DVBOOT - LX is the amount of droop
allowed in the bootstrapped supply voltage when the high-side
MOSFET is driven high. The bootstrap capacitor value is
typically 0.1 mF to 1 mF. The bootstrap capacitor voltage rating
must be greater than VDD + 5 V to withstand transient spikes
and ringing.
Shoot-Through Protection
The external MOSFETs are prevented from conducting at the
same time during transitions. Break-before-make circuits
monitor the voltages on the LX pin and the OUTL pin and
control the switching as follows: When the signal on PWM goes
low, OU T H will go low after an internal propagation delay. After
the voltage on LX falls below 1 V by the inductor action, the
low-side driver is enabled and OUTL goes high after some
delay. When the signal on PWM goes high, OUTL will go low
after an internal propagation delay. After the voltage on OU TL
drops below 1 V the high-side driver is enabled and OUTH will
go high after an internal propagation delay. If LX does not drop
below 1 V within 400 ns after OUTH goes low, OUTL is forced
high until the next PWM transition.
SiP41103
Vishay Siliconix New Product
www.vishay.com
6Document Number: 72718
S-32672—Rev. A, 29-Dec-03
Delay
The addition of a capacitor between DELAY and GND will
increase the propagation delay time for OUTH going high.
Delay capacitance may be added to prevent shoot through
current i n the low-side MOSFET due to the finite time between
OUTL going low and the continuing conduction of the low-side
MOSFET. Choose a MOSFET with lower gate resistance to
reduce this ef fect. If necessary, choose a capacitor value that
prevents MOSFET conduction under worst-case temperature
and manufacturing conditions. Propagation delay is increased
according to the ratio of 1.2 ns/pF.
Synchronous MOSFET Enable
Under light load conditions, efficiency can be increased by
disabling the synchronous MOSFET, thus avoiding the gate
charge losses of the synchronous MOSFET. When ENSYNC
is low, OUTL is forced low. When high, the low-side driver
operates normally. ENSYNC should be driven by a 5-V signal.
Shutdown
The driver enters shutdown mode when a period of inactivity
on PWM elapses. Shutdown current is less than 1 mA.
VDD Bypass Capacitor
MOSFET drivers draw large peak currents from the supplies
when they switch. A local bypass capacitor is required to
supply this current and reduce power supply noise. Connect
a 1-mF ceramic capacitor as close as practical between the
VDD and GND pins.
Undervoltage Lockout
Undervoltage lockout prevents control of the circuit until the
supply voltages reach valid operating levels. The UVLO circuit
forces OU T L and O U T H to low when VDD is below its specified
voltage. A separate UVLO forces OUTH low when the voltage
between BOOT and LX is below the specified voltage.
Thermal Protection
If the die temperature rises above 165_C, the thermal
protection disables the drivers. The drivers are re-enabled
after the die temperature has decreased below 140_C.
TYPICAL CHARACTERISTICS
0.0
20.0
40.0
60.0
80.0
100.0
120.0
140.0
0 102030405060708090100110
0
10
20
30
40
50
012345
Highside Turn On Delay vs.CDELAY
CDelay (pF)
IDD vs. CLOAD vs. Frequency
CLOAD (nF)
1 MHz
IDD (mA)
500 kHz
200 kHz
td(on)H(ns)
SiP41103
Vishay Siliconix
New Product
Document Number: 72718
S-32672—Rev. A, 29-Dec-03 www.vishay.com
7
TYPICAL WAVEFORMS
50 ns/div
Figure 2. PWM Signal vs. LX (Rising) Figure 3. PWM Signal vs. LX (Falling)
Figure 4. PWM Signal vs. HS Gate
and LS Gate (Rising)
Figure 6. ENSYNC Delay
50 ms/div
PWM IN
2 V/div
VLX
2 V/div
50 ns/div
PWM IN
2 V/div
VLX
2 V/div
50 ns/div
PWM IN
5 V/div
HS Gate
5 V/div
LS Gate
5 V/div
Figure 5. PWM Signal vs. HS Gate
and LS Gate (Falling)
50 ns/div
PWM IN
5 V/div
HS Gate
5 V/div
LS Gate
5 V/div
HS Gate
5 V/div
LS Gate
5 V/div
ENSYNC
5 V/div
