TL/F/5948
CD4015BM/CD4015BC Dual 4-Bit Static Shift Register
June 1996
CD4015BM/CD4015BC Dual 4-Bit Static Shift Register
General Description
The CD4015BM/CD4015BC contains two identical, 4-stage,
serial-input/parallel-output registers with independent
‘‘Data’’, ‘‘Clock,’’ and ‘‘Reset’’ inputs. The logic level pres-
ent at the input of each stage is transferred to the output of
that stage at each positive-going clock transition. A logic
high on the ‘‘Reset’’ input resets all four stages covered by
that input. All inputs are protected from static discharge by a
series resistor and diode clamps to VDD and VSS.
Features
YWide supply voltage range 3.0V to 18V
YHigh noise immunity 0.45 VDD (typ.)
YLow power TTL Fan out of 2 driving 74L
compatibility or 1 driving 74LS
YMedium speed operation 8 MHz (typ.) clock rate
YFully static design @VDD bVSS e10V
Applications
YSerial-input/parallel-output data queueing
YSerial to parallel data conversion
YGeneral purpose register
Connection Diagram and Truth Table
Dual-In-Line Package
TL/F/5948–1
CLUDRQ
1Q
n
L00 0 Q
n
b
1
L10 1 Q
n
b
1
KX0Q
1Q
n(No change)
XX10 0
U
Level change
XeDon’t care case
Order Number CD4015B
C1996 National Semiconductor Corporation RRD-B30M76/Printed in U. S. A. http://www.national.com
Absolute Maximum Ratings (Notes1&2)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
DC Supply Voltage (VDD)b0.5 to a18 VDC
Input Voltage (VIN)b0.5 to VDD a0.5 VDC
Storage Temperature Range (TS)b65§Ctoa
150§C
Power Dissipation (PD)
Dual-In-Line 700 mW
Small Outline 500 mW
Lead Temperature (TL)
(Soldering, 10 seconds) 260§C
Recommended Operating
Conditions
DC Supply Voltage (VDD)a3toa
15 VDC
Input Voltage (VIN) 0 to VDD VDC
Operating Temperature Range (TA)
CD4015BM b55§Ctoa
125§C
CD4015BC b40§Ctoa
85§C
DC Electrical Characteristics CD4015BM (Note 2)
Symbol Parameter Conditions b55§Ca25§Ca125§CUnits
Min Max Min Typ Max Min Max
IDD Quiescent Device VDD e5V, VIN eVDD or VSS 5 0.005 5 150 mA
Current VDD e10V, VIN eVDD or VSS 10 0.010 10 300 mA
VDD e15V, VIN eVDD or VSS 20 0.015 20 600 mA
VOL Low Level VDD e5V 0.05 0 0.05 0.05 V
Output Voltage VDD e10V
l
IO
l
k1mA 0.05 0 0.05 0.05 V
VDD e15V (0.05 0 0.05 0.05 V
VOH High Level VDD e5V 4.95 4.95 5 4.95 V
Output Voltage VDD e10V
l
IO
l
k1mA 9.95 9.95 10 9.95 V
VDD e15V (14.95 14.95 15 14.95 V
VIL Low Level VDD e5V, VOe0.5V or 4.5V 1.5 2.25 1.5 1.5 V
Input Voltage VDD e10V, VOe1.0V or 9.0V 3.0 4.50 3.0 3.0 V
VDD e15V, VOe1.5V or 13.5V 4.0 6.75 4.0 4.0 V
VIH High Level VDD e5V, VOe0.5V or 4.5V 3.5 3.5 2.75 3.5 V
Input Voltage VDD e10V, VOe1.0V or 9.0V 7.0 7.0 5.50 7.0 V
VDD e15V, VOe1.5V or 13.5V 11.0 11.0 8.25 11.0 V
IOL Low Level Output VDD e5V, VOe0.4V 0.64 0.51 0.88 0.36 mA
Current (Note 3) VDD e10V, VOe0.5V 1.6 1.3 2.25 0.9 mA
VDD e15V, VOe1.5V 4.2 3.4 8.8 2.4 mA
IOH High Level Output VDD e5V, VOe4.6V b0.64 b0.51 b0.88 b0.36 mA
Current (Note 3) VDD e10V, VOe9.5V b1.6 b1.3 b2.25 b0.9 mA
VDD e15V, VOe13.5V b4.2 b3.4 b8.8 b2.4 mA
IIN Input Current VDD e15V, VIN e0V b0.1 b10b5b0.1 b1.0 mA
VDD e15V, VIN e15V 0.1 10b50.1 1.0 mA
Note 1: ‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed; they are not meant to imply that the devices
should be operated at these limits. The tables of ‘‘Recommended Operating Conditions’’ and ‘‘Electrical Characteristics’’ provide conditions for actual device
operation.
Note 2: VSS e0V unless otherwise specified.
Note 3: IOH and IOL are tested one output at a time.
http://www.national.com 2
DC Electrical Characteristics CD4015BC (Note 2)
Symbol Parameter Conditions b55§Ca25§Ca125§CUnits
Min Max Min Typ Max Min Max
IDD Quiescent Device VDD e5V, VIN eVDD or VSS 20 0.005 20 150 mA
Current VDD e10V, VIN eVDD or VSS 40 0.010 40 300 mA
VDD e15V, VIN eVDD or VSS 80 0.015 80 600 mA
VOL Low Level VDD e5V 0.05 0 0.05 0.05 V
Output Voltage VDD e10V 0.05 0 0.05 0.05 V
VDD e15V 0.05 0 0.05 0.05 V
VOH High Level VDD e5V 4.95 4.95 5 4.95 V
Output Voltage VDD e10V 9.95 9.95 10 9.95 V
VDD e15V 14.95 14.95 15 14.95 V
VIL Low Level VDD e5V, VOe0.5V or 4.5V 1.5 2.25 1.5 1.5 V
Input Voltage VDD e10V, VOe1.0V or 9.0V 3.0 4.50 3.0 3.0 V
VDD e15V, VOe1.5V or 13.5V 4.0 6.75 4.0 4.0 V
VIH High Level VDD e5V, VOe0.5V or 4.5V 3.5 3.5 2.75 3.5 V
Input Voltage VDD e10V, VOe1.0V or 9.0V 7.0 7.0 5.50 7.0 V
VDD e15V, VOe1.5V or 13.5V 11.0 11.0 8.25 11.0 V
IOL Low Level Output VDD e5V, VOe0.4V 0.52 0.44 0.88 0.36 mA
Current (Note 3) VDD e10V, VOe0.5V 1.3 1.1 2.25 0.9 mA
VDD e15V, VOe1.5V 3.6 3.0 8.8 2.4 mA
IOH High Level Output VDD e5V, VOe4.6V b0.52 b0.44 b0.88 b0.36 mA
Current (Note 3) VDD e10V, VOe9.5V b1.3 b1.1 b2.25 b0.9 mA
VDD e15V, VOe13.5V b3.6 b3.0 b8.8 b2.4 mA
IIN Input Current VDD e15V, VIN e0V b0.3 b10b5b0.3 b1.0 mA
VDD e15V, VIN e15V 0.3 10b50.3 1.0 mA
Note 1: ‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed; they are not meant to imply that the devices
should be operated at these limits. The tables of ‘‘Recommended Operating Conditions’’ and ‘‘Electrical Characteristics’’ provide conditions for actual device
operation.
Note 2: VSS e0V unless otherwise specified.
Note 3: IOH and IOL are tested one output at a time.
http://www.national.com3
AC Electrical Characteristics*
TAe25§C, CLe50 pF, RLe200k, tretfe20 ns, unless otherwise specified
Symbol Parameter Conditions Min Typ Max Units
CLOCK OPERATION
tPHL,t
PLH Propagation Delay Time VDD e5V 230 350 ns
VDD e10V 80 160 ns
VDD e15V 60 120 ns
tTHL,t
TLH Transition Time VDD e5V 100 200 ns
VDD e10V 50 100 ns
VDD e15V 40 80 ns
tWL,t
WM Minimum Clock VDD e5V 160 250 ns
Pulse-Width VDD e10V 60 110 ns
VDD e15V 50 85 ns
trCL,t
fCL Clock Rise and VDD e5V 15 ms
Fall Time VDD e10V 15 ms
VDD e15V 15 ms
tSU Minimum Data VDD e5V 50 100 ms
Set-Up Time VDD e10V 20 40 ms
VDD e15V 15 30 ms
fCL Maximum Clock VDD e5V 2 3.5 MHz
Frequency VDD e10V 4.5 8 MHz
VDD e15V 6 11 MHz
CIN Input Capacitance Clock Input 7.5 10 pF
Other Inputs 5 7.5 pF
RESET OPERATION
tPHL(R) Propagation Delay Time VDD e5V 200 400 ns
VDD e10V 100 200 ns
VDD e15V 80 160 ns
tWH(R) Minimum Reset VDD e5V 135 250 ns
Pulse Width VDD e10V 40 80 ns
VDD e15V 30 60 ns
*AC Parameters are guaranteed by DC correlated testing.
Logic Diagrams
TL/F/5948–2
http://www.national.com 4
Logic Diagrams (Continued)
Terminal No. 16 eVDD
TL/F/5948–3
Terminal No. 8 eGND
Physical Dimensions inches (millimeters) unless otherwise noted
Ceramic Dual-In-Line Package (J)
Order Number CD4015BMJ or CD4015BCJ
NS Package Number J16A
http://www.national.com5
CD4015BM/CD4015BC Dual 4-Bit Static Shift Register
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
Molded Dual-In-Line Package (N)
Order Number CD4015BMN or CD4015BCN
NS Package Number N16E
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with instructions for use provided in the labeling, can effectiveness.
be reasonably expected to result in a significant injury
to the user.
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