Rev. 1.5 4/14 Copyright © 2014 by Silicon Laborato ries Si570/Si571
Si570/Si571
10 MHZ TO 1.4 GHZ I2C PROGRAMMABLE XO/VCXO
Features
Applications
Description
The Si570 XO/Si571 VCXO utilizes Silicon Laboratories’ advanced DSPLL
®
circuitry to provide a low-jitter clock at any frequency. The Si570/Si571 are user-
programmable to any output frequency from 10 to 945 MHz and select frequencies
to 1400 MHz with <1 ppb resolution. The device is programmed via an I
2
C serial
interface. Unlike traditional XO/VCXOs where a different crystal is required for
each output frequency, the Si57x uses one fixed-frequency crystal and a DSPLL
clock synthesis IC to provide any-frequency operation. This IC-based approach
allows the crystal resonator to provide exceptional frequency stability and
reliability. In addition, DSPLL clock synthesis provides superior supply noise
rejection, simplifying the task of generating low-jitter clocks in noisy environments
typically found in communication systems.
Functional Block Diagram
Any programmable output
frequencies from 10 to 945 MHz and
select frequencies to 1.4 GHz
I2C serial interface
3rd generation DSPLL® with superior
jitter performance
3x better frequency stability than
SAW-based oscillators
Internal fixed crystal frequency
ensures high reliability and low
aging
Available LVPECL, CMOS,
LVDS, and CML outputs
Industry-standard 5x7 mm
package
Pb-free/RoHS-compliant
1.8, 2.5, or 3.3 V supply
SONET/SDH
xDSL
10 GbE LAN/WAN
ATE
High performance
instrumentation
Low-jitter clock generation
Optical modules
Clock and data recovery
Fixed
Frequency
XO
10-1400 MHz
DSPLLClock
Synthesis
CLK- CLK+
SCL
GND
OE
VDD
SDA
VC
ADC
Si571 only
Ordering Information:
See page 32.
Pin Assignments:
See page 31.
(Top View)
Si5602
Si570
Si571
1
2
3
6
5
4
NC
GND
OE
VDD
CLK+
CLK–
SDA
SCL
8
7
1
2
3
6
5
4
VC
GND
OE
VDD
CLK+
CLK–
SDA
SCL
8
7
Si570/Si571
2 Rev. 1.5
Si570/Si571
Rev. 1.5 3
TABLE OF CONTENTS
Section Page
1. Detailed Block Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
2. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
3. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
3.1. Programming a New Output Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
3.2. Si570 Programming Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
3.3. Si570 Troubleshooting FAQ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
3.4. I2C Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
4. Serial Port Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
5. Si570 (XO) Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
6. Si571 (VCXO) Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
7. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
8. Si57x Mark Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
9. Outline Diagram and Suggested Pad Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
10. 8-Pin PCB Land Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
Si570/Si571
4 Rev. 1.5
1. Detailed Block Diagrams
Figure 1. Si570 Detailed Block Diagram
Figure 2. Si571 Detailed Block Diagram
Frequency
Control
Control
Interface
NVM
÷HS_DIV ÷N1
+DCO
RFREQ
CLKOUT+
CLKOUT–
VDD GND
fXTAL
fosc
M
SDA
OE
SCL RAM
Frequency
Control
Control
Interface
NVM
÷HS_DIV ÷N1
+DCOADC
RFREQ
VCADC
VCCLKOUT+
CLKOUT–
VDD GND
fXTAL
fosc
M
SDA
OE
SCL RAM
Si570/Si571
Rev. 1.5 5
2. Electrical Specifications
Table 1. Recommended Operating Conditions
Parameter Symbol Test Condition Min Typ Max Unit
Supply Voltage1VDD
3.3 V op tio n 2.97 3.3 3.63
V2.5 V op tio n 2.25 2.5 2.75
1.8 V op tio n 1.71 1.8 1.89
Supply Current IDD
Output enabled
LVPECL
CML
LVDS
CMOS
—
—
—
—
120
108
99
90
130
117
108
98
mA
TriS tate mode — 60 75
Output Enable (OE)2,
Serial Data (SDA),
Serial Clock (SCL)
VIH 0.75 x VDD ——
V
VIL ——0.5
Operating Temperature Range TA–40 — 85 ºC
Notes:
1. Selectable parameter specified by part number. See Section "7. Ordering Information" on page 32 for further details.
2. OE pin includes a 17 k pullup resistor to VDD. See “7.Ordering Information”.
Table 2. VC Control Voltage Input (Si571)
Parameter Symbol Test Condition Min Typ Max Unit
Control Volt age Tuning Slope1,2,3 KVVC 10 to 90% of VDD —
33
45
90
135
180
356
— ppm/V
Control Volt age Linearity4LVC BSL –5 ±1 +5 %
Incremental –10 ±5 +10
Modulation Bandwidth BW 9.3 10.0 10.7 kHz
VC Input Impedance ZVC 500 — — k
Nominal Control Voltage5VCNOM @ fO—V
DD/2 — V
Control Voltage Tuning Range VC0V
DD V
Notes:
1. Positive slope; selectable option by part number. See "7. Ordering Information" on page 32.
2. For best jitter and phase noise performance, always choose the smallest KV that meets the application’s minimum APR
requirements. See “AN266: VCXO Tuning Slope (KV), Stability, and Absolute Pull Range (APR)” for more information.
3. KV variation is ±10% of typical values.
4. BSL determined from deviation from best straight line fit with VC ranging from 10 to 90% of VDD. Incremental slope is
determined with VC ranging from 10 to 90% of VDD.
5. Nominal output frequency set by VCNOM = 1/2 x VDD.
Si570/Si571
6 Rev. 1.5
Table 3. CLK± Output Frequency Characteristics
Parameter Symbol Test Con di tio n Min Ty p Max Unit
Programmable Fre quency
Range1,2 fOLVPECL/LVDS/CML 10 — 1417.5 MHz
CMOS 10 — 160
Temperature Stability1,3 TA= –40 to +85 ºC
–7
–20
–50
–100
—
—
—
—
7
+20
+50
+100
ppm
Initial Accuracy —1.5—
ppm
Aging faFrequency drift over first year — — ±3 ppm
Frequency drift over 20-year life — — ±10 ppm
Total Stability
Temp stability = ±7 ppm — — ±20 ppm
Temp stability = ±20 ppm — — ±31.5 ppm
Temp stability = ±50 ppm — — ±61.5 ppm
Absolute Pull Range1,3 APR ±12 — ±375 ppm
Power up Time4tOSC ——10ms
Notes:
1. See Section "7. Ordering Information" on page 32 for further details.
2. Specified at time of order by part number. Three speed grades available:
Grade A covers 10 to 945 MHz, 970 to 1134 MHz, and 1213 to 1417.5 MHz.
Grade B covers 10 to 810 MHz.
Grade C covers 10 to 280 MHz.
3. Selectable parameter specified by part number.
4. Time from power up or tristate mode to fO.
Si570/Si571
Rev. 1.5 7
Table 4. CLK± Output Levels and Symmetry
Parameter Symbol Test C ondition Min Typ Max Unit
LVPECL Output Option1VOmid-level VDD – 1.42 — VDD – 1.25 V
VOD swing (diff) 1.1 —1.9 VPP
VSE swing (single-ended) 0.55 —0.95 VPP
LVDS Output Option2VOmid-level 1.125 1.20 1.275 V
VOD swing (diff) 0.5 0.7 0.9 VPP
CML Output Opt ion 2
VO2.5/3.3 V option mid-level — VDD – 1.30 — V
1.8 V option mid-level — VDD – 0.36 — V
VOD 2.5/3.3 V option swing (diff) 1.10 1.50 1.90 VPP
1.8 V option swing (diff) 0.35 0.425 0.50 VPP
CMOS Output Option3VOH IOH =32mA 0.8 x VDD —VDD V
VOL IOL =32mA — — 0.4 V
Rise/Fall time (20/80%) tR, tFLVPECL/LVDS/CML — — 350 ps
CMOS with CL=15pF — 1 — ns
Symmetry (duty cycle) SYM LVPECL: VDD – 1. 3 V (diff)
LVDS: 1.25 V (diff)
CMOS: VDD/2 45 — 55 %
Notes:
1. Rterm =50 to VDD – 2.0 V.
2. Rterm =100 (differential).
3. CL=15pF
Si570/Si571
8 Rev. 1.5
Table 5. CLK± Output Phase Jitter (Si570)
Parameter Symbol Test Condition Min Typ Max Unit
Phase Jitter (RMS)1
for FOUT > 500 MHz J12 kHz to 20 MHz (OC-48) — 0.25 0.40 ps
50 kHz to 80 MHz (OC-192) — 0.26 0.37
Phase Jitter (RMS)1
for FOUT of 125 to 500 MHz J12 kHz to 20 MHz (OC-48) — 0.36 0.50 ps
50 kHz to 80 MHz (OC-192)2— 0.34 0.42
Phase Jitter (RMS)
for FOUT of 10 to 160 MHz
CMOS Output Only
J12 kHz to 20 MHz (OC-48)2—0.62—ps
50 kHz to 20 MHz2—0.61—
Notes:
1. Refer to AN256 for further information.
2. Max offset frequencies:
80 MHz for FOUT > 250 MHz
20 MHz for 50 MHz < FOUT <250 MHz
2 MHz for 10 MHz < FOUT <50 MHz.
Si570/Si571
Rev. 1.5 9
Table 6. CLK± Output Phase Jitter (Si571)
Parameter Symbol Test Condition Min Typ Max Unit
Phase Jitter (RMS)1,2,3
for FOUT > 500 MHz JKv = 33 ppm/V
12 kHz to 20 MHz (OC-48)
50 kHz to 80 MHz (OC-192) —
—0.26
0.26 —
—
ps
Kv = 45 ppm/V
12 kHz to 20 MHz (OC-48)
50 kHz to 80 MHz (OC-192) —
—0.27
0.26 —
—
Kv = 90 ppm/V
12 kHz to 20 MHz (OC-48)
50 kHz to 80 MHz (OC-192) —
—0.32
0.26 —
—
Kv = 135 ppm/V
12 kHz to 20 MHz (OC-48)
50 kHz to 80 MHz (OC-192) —
—0.40
0.27 —
—
Kv = 180 ppm/V
12 kHz to 20 MHz (OC-48)
50 kHz to 80 MHz (OC-192) —
—0.49
0.28 —
—
Kv = 356 ppm/V
12 kHz to 20 MHz (OC-48)
50 kHz to 80 MHz (OC-192) —
—0.87
0.33 —
—
Notes:
1. Differential Modes: LVPECL/LVDS/CML. Refer to AN255, AN256, and AN266 for further information.
2. For best jitter and phase noise performance, always choose the smallest KV that meets the application’s minimum APR
requirements. See “AN266: VCXO Tuning Slope (kV), Stability, and Absolute Pull Range (APR)” for more information.
3. See “AN255: Replacing 622 MHz VCSO devices with the Si550 VCXO” for comparison highlighting power supply
rejection (PSR) advantage of Si55x versus SAW-based solutions.
4. Single ended mode: CMOS. Refer to the following application notes for further information:
“AN255: Replacing 622 MHz VCSO Devices with the Si55x VCXO”
“AN256: Integrated Phase Noise”
“AN266: VCXO Tuning Slope (kV), Stability, and Absolute Pull Range (APR)”
5. Max offset frequencies:
80 MHz for FOUT > 250 MHz
20 MHz for 50 MHz < FOUT <250 MHz
2 MHz for 10 MHz < FOUT <50 MHz.
Si570/Si571
10 Rev. 1.5
Phase Jitter (RMS)2,4,5
for FOUT 10 to 160 MHz
CMOS Output Only
JKv = 33 ppm/V
12 kHz to 20 MHz (OC-48)
50 kHz to 20 MHz —
—0.63
0.62 —
—
ps
Kv = 45 ppm/V
12 kHz to 20 MHz (OC-48)
50 kHz to 20 MHz —
—0.63
0.62 —
—
Kv = 90 ppm/V
12 kHz to 20 MHz (OC-48)
50 kHz to 20 MHz —
—0.67
0.66 —
—
Kv = 135 ppm/V
12 kHz to 20 MHz (OC-48)
50 kHz to 20 MHz —
—0.74
0.72 —
—
Kv = 180 ppm/V
12 kHz to 20 MHz (OC-48)
50 kHz to 20 MHz —
—0.83
0.8 —
—
Kv = 356 ppm/V
12 kHz to 20 MHz (OC-48)
50 kHz to 20 MHz —
—1.26
1.2 —
—
Table 6. CLK± Output Phase Jitter (Si571) (Continued)
Parameter Symbol Test Condition Min Typ Max Unit
Notes:
1. Differential Modes: LVPECL/LVDS/CML. Refer to AN255, AN256, and AN266 for further information.
2. For best jitter and phase noise performance, always choose the smallest KV that meets the application’s minimum APR
requirements. See “AN266: VCXO Tuning Slope (kV), Stability, and Absolute Pull Range (APR)” for more information.
3. See “AN255: Replacing 622 MHz VCSO devices with the Si550 VCXO” for comparison highlighting power supply
rejection (PSR) advantage of Si55x versus SAW-based solutions.
4. Single ended mode: CMOS. Refer to the following application notes for further information:
“AN255: Replacing 622 MHz VCSO Devices with the Si55x VCXO”
“AN256: Integrated Phase Noise”
“AN266: VCXO Tuning Slope (kV), Stability, and Absolute Pull Range (APR)”
5. Max offset frequencies:
80 MHz for FOUT > 250 MHz
20 MHz for 50 MHz < FOUT <250 MHz
2 MHz for 10 MHz < FOUT <50 MHz.
Si570/Si571
Rev. 1.5 11
Phase Jitter (RMS)1,2,3,5
for FOUT of 125 to
500 MHz
JKv = 33 ppm/V
12 kHz to 20 MHz (OC-48)
50 kHz to 80 MHz (OC-192) —
—0.37
0.33 —
—
ps
Kv = 45 ppm/V
12 kHz to 20 MHz (OC-48)
50 kHz to 80 MHz (OC-192) —
—0.37
0.33 —
—
Kv = 90 ppm/V
12 kHz to 20 MHz (OC-48)
50 kHz to 80 MHz (OC-192) —
—0.43
0.34 —
—
Kv = 135 ppm/V
12 kHz to 20 MHz (OC-48)
50 kHz to 80 MHz (OC-192) —
—0.50
0.34 —
—
Kv = 180 ppm/V
12 kHz to 20 MHz (OC-48)
50 kHz to 80 MHz (OC-192) —
—0.59
0.35 —
—
Kv = 356 ppm/V
12 kHz to 20 MHz (OC-48)
50 kHz to 80 MHz (OC-192) —
—1.00
0.39 —
—
Table 7. CLK± Output Period Jitter
Parameter Symbol Test Condition Min Typ Max Unit
Period Jitter* JPER RMS — 2 — ps
Peak-to-Peak — 14 —
*Note: Any output mode, including CMOS, LVPECL, LVDS, CML. N = 1000 cycles. Refer to “AN279: Estimating Period Jitter
from Phase Noise” for further information.
Table 6. CLK± Output Phase Jitter (Si571) (Continued)
Parameter Symbol Test Condition Min Typ Max Unit
Notes:
1. Differential Modes: LVPECL/LVDS/CML. Refer to AN255, AN256, and AN266 for further information.
2. For best jitter and phase noise performance, always choose the smallest KV that meets the application’s minimum APR
requirements. See “AN266: VCXO Tuning Slope (kV), Stability, and Absolute Pull Range (APR)” for more information.
3. See “AN255: Replacing 622 MHz VCSO devices with the Si550 VCXO” for comparison highlighting power supply
rejection (PSR) advantage of Si55x versus SAW-based solutions.
4. Single ended mode: CMOS. Refer to the following application notes for further information:
“AN255: Replacing 622 MHz VCSO Devices with the Si55x VCXO”
“AN256: Integrated Phase Noise”
“AN266: VCXO Tuning Slope (kV), Stability, and Absolute Pull Range (APR)”
5. Max offset frequencies:
80 MHz for FOUT > 250 MHz
20 MHz for 50 MHz < FOUT <250 MHz
2 MHz for 10 MHz < FOUT <50 MHz.
Si570/Si571
12 Rev. 1.5
Table 8. Typical CLK± Output Phase Noise (Si570)
Offset Frequency (f) 120.00 MHz
LVDS 156.25 MHz
LVPECL 622.08 MHz
LVPECL Unit
100 Hz
1kHz
10 kHz
100 kHz
1MHz
10 MHz
100 MHz
–112
–122
–132
–137
–144
–150
n/a
–105
–122
–128
–135
–144
–147
n/a
–97
–107
–116
–121
–134
–146
–148
dBc/Hz
Table 9. Typical CLK± Output Phase Noise (Si571)
Offset Frequency (f) 74.25 MHz
90 ppm/V
LVPECL
491.52 MHz
45 ppm/V
LVPECL
622.08 MHz
135 ppm/V
LVPECL
Unit
100 Hz
1kHz
10 kHz
100 kHz
1MHz
10 MHz
100 MHz
–87
–114
–132
–142
–148
–150
n/a
–75
–100
–116
–124
–135
–146
–147
–65
–90
–109
–121
–134
–146
–147
dBc/Hz
Table 10. Environmental Compliance
(The Si570/571 meets the following qualification test requirements.)
Parameter Conditions/Test Method
Mechanical Shock MIL-STD-883, Method 2002
Mechanical Vibration MIL-STD-883, Method 2007
Solderability MIL-STD-883, Method 2003
Gross and Fine Leak MIL- STD-883, Method 1014
Resistance to Solder Heat MIL-STD-883, Method 2036
Moisture Sensitivity Level J-STD-020, MSL1
Contact Pads Gold over Nickel
Si570/Si571
Rev. 1.5 13
Table 11. Programming Constraints and Timing
(VDD = 3.3 V ±10%, TA= –40 to 85 ºC)
Parameter Symbol Test Condition Min Typ Max Unit
Output Frequency Ra nge CKOF
HS_DIV x N1 > = 6 10 — 945 MHz
HS_DIV = 5
N1 = 1 970 — 1134 MHz
HS_DIV = 4
N1 = 1 1.2125 — 1.4175 GHz
Frequency Reprogramming
Resolution MRES fxtal = 114.285 MHz — 0.09 — ppb
Internal Oscillator Frequency fOSC 4850 — 5670 MHz
Internal Crystal Frequency
Accuracy fXTAL Maximum variation is
±2000 ppm — 114.285 — MHz
Delta Frequency for
Continuous Output From center freque ncy –3500 — +3500 ppm
Unfreeze to NewFreq
Timeout ——10ms
Settling Time for Small
Frequency Change <±3500 ppm from
center frequency ——100µs
Settling Time for Large
Frequency Change >±3500 ppm from
center frequency after
setting Ne wFreq bit
——10ms
Table 12. Thermal Characteristics
(Typical values TA = 25 ºC, VDD =3.3V)
Parameter Symbol Test Condition Min Typ Max Unit
Thermal Resistance Junction to Ambient JA Still Air — 84.6 — °C/W
Thermal Resistance Junction to Case JC Still Air — 38.8 — °C/W
Ambient Temperature TA–40 — 85 °C
Junction Temperature TJ——125°C
Si570/Si571
14 Rev. 1.5
Table 13. Absolute Maximum Ratings1,2
Parameter Symbol Rating Unit
Supply Volt age, 1.8 V Option VDD –0.5 to +1.9 V
Supply Voltage, 2.5/3.3 V Option VDD –0.5 to +3.8 V
Input Voltage VI–0.5 to VDD + 0.3 V
Storage Temperature TS–55 to +125 ºC
ESD Sensitivity (HBM, per JESD22-A114) ESD >2000 V
Soldering Temperature (Lead-free Profile) TPEAK 260 ºC
Soldering Temperature Time @ TPEAK (Lead-free Profile) tP20–40 seconds
Notes:
1. Stresses beyond the absolute maximum ratings may cause permanent damage to the device. Functional operation or
specification compliance is not implied at these conditions.
2. The device is compliant with JEDEC J-STD-020. Refer to packaging FAQ available for download at
www.siliconlabs.com/VCXO for further information, including soldering profiles.
Si570/Si571
Rev. 1.5 15
3. Functional Description
The Si570 XO and the Si571 VCXO are low-jitter
oscillators ideally suited for applications requiring
programmable frequencies. The Si57x can be
programmed to generate virtually any output clock in
the range of 10 MHz to 1.4 GHz. Output jitter
performance complies with and exceeds the strict
requirements of high-speed communication systems
including OC-192/STM-64 and 10 Gigabit Ethernet
(10 GbE).
The Si57x consists of a digitally-controlled oscillator
(DCO) based on Silicon Laboratories' third-generation
DSPLL technology, which is driven by an internal fixed-
frequency crystal reference.
The device's default output frequency is set at the
factory and can be reprogrammed through the two-wire
I2C serial port. Once the device is powered down, it will
return to its factory-set default output frequency.
While the Si570 outputs a fixed frequency, the Si571
has a pullable output frequency using the voltage
control input pin. This makes the Si571 an ideal choice
for high-performance, low-jitter, phase-locked loops.
3.1. Programming a New Output
Frequency
The output frequency (fout) is determined by
programming the DCO frequency (fDCO) and the
device's output dividers (HS_DIV, N1). The output
frequency is calculated using the following equation:
The DCO frequency is adjustable in th e range of 4.85 to
5.67 GHz by setting the high-resolution 38-bit fractional
multiplier (RFREQ). The DCO frequency is the product
of the internal fixed-frequency crystal (fXTAL) and
RFREQ.
The 38-bit resolution of RFREQ allows the DCO
frequency to have a progr ammable fr equency resolu tion
of 0.09 ppb.
As shown in Figure 3, the device allows reprogramming
of the DCO frequency up to ±3500 ppm from the center
frequency configuration without interruption to the
output clock. Changes greater than the ±3500 ppm
window will cause the device to recalibrate its internal
tuning circuitry, forcing the output clock to momentarily
stop and start at any arbitr ary point during a clock cycle.
This re-calibration process establishes a new center
frequency and can take up to 10 ms. Circuitry receiving
a clock from the Si57x device that is sensitive to glitches
or runt pulses may have to be reset once the
recalibration process is complete.
3.1.1. Reconfiguring the Output Clock for a Small
Change in Frequency
For output changes less than ±3500 ppm from the
center frequency configuration, the DCO frequency is
the only value that needs reprogramming. Since
fDCO =f
XTAL x RFREQ, and that fXTAL is fixed, changing
the DCO frequency is as simple as reconfiguring the
RFREQ value as outlined below:
1. Using the serial port, read the current RFREQ value
(addresses 7–12 for all Si571 devices and Si570
devices with 20 ppm and 50 ppm temperature
stability; or addresses 13–18 for Si570 devices with
7 ppm temperature stability).
2. Calculate the new value of RFREQ give n the change
in frequency.
3. Using the serial port, write the new RFREQ value
(addresses 7–12 for all Si571 devices and Si570
devices with 20 ppm and 50 ppm temperature
stability; or addresses 13–18 for Si570 devices with
7 ppm temperature stability).
Example:
An Si570 generating a 148.35 MHz clock must be
reconfigured "on-the-fly" to ge nerate a 148.5 MHz clock.
This represents a change of +1011.122 ppm, which is
well within the ±3500 ppm window.
Figure 3. DCO Frequency Range
fout fDCO
Output Divi ders
-----------------------------------------fXTAL RFREQ
HSDIV N1
-------------------------------------------
==
RFREQnew RFREQcurrent fout_new
fout_current
-------------------------
=
4.85 GHz 5.67 GH z
Center
Frequency
Configuration
-3500 ppm +3500 ppm
small frequency cha nges can be m ade
“on-the-fly” wi thou t int err upt ion t o the
output clock
Si570/Si571
16 Rev. 1.5
A typical frequency co nfiguration for this example:
RFREQcurrent = 0x2EBB04CE0
Fout_current =148.35MHz
Fout_new =148.50MHz
Calculate RFREQnew to change the output frequency
from 148.35 MHz to 148.5 MHz:
Note: Performing calculations with RFREQ requires a mini-
mum of 38-bit arithmetic precision.
Even relatively small changes in output frequency may
require writing more than 1 RFREQ register. Such multi-
register RFREQ writes can impact the output clock
frequency on a register-by-register basis during
updating.
Interim changes to the output clock during RFREQ
writes can be prevented by using the following
procedure:
1. Freeze the “M” value (Set Register 135 bit 5 = 1).
2. Write the new frequency configuration (RFREQ).
3. Unfreeze the “M” value (Set Register 135 bit 5 = 0)
3.1.2. Reconfiguring the Output Clock for Large
Changes in Output Frequency
For output frequency changes outside of ±3500 ppm
from the center frequency, it is likely that both the DCO
frequency and the output dividers need to be
reprogrammed. Note that changing the DCO frequency
outside of the ±3500 ppm window will cause the output
to momentarily stop and restart at any arbitrary point in
a clock cycle. Devices sensitive to glitches or runt
pulses may have to be reset once reconfiguration is
complete.
The process for reconfiguring the output frequency
outside of a ±3500 ppm window first requires reading
the current RFREQ, HSDIV, and N1 values. Next,
calculate fXTAL for the device. Note that, due to slight
variations of the internal crystal frequency from one
device to another, each device may have a different
RFREQ value or possibly even different HSDIV or N1
values to maintain the same output frequency. It is
necessary to calculate fXTAL for each device. Third,
write the new values back to the device using the
appropriate registers (addresses 7–12 for all Si571
devices and Si570 devices with 20 ppm and 50 ppm
temperature stability; or addresses 13–18 for Si570
devices with 7 ppm temperature stability) sequencing as
described in “3.1.2.1.Writing the New Frequency
Configuration”.
Once fXTAL has been determined, new values for
RFREQ, HSDIV, and N1 are calculated to generate a
new output frequency (fout_new). New values can be
calculated manually or with the Si57x-EVB software,
which provides a user-friendly application to help find
the optimum values.
The first step in manually calculating the frequency
configuration is to determine new frequency divider
values (HSDIV, N1). Given the desired ou tput fr equ ency
(fout_new), find the frequency divider values that will
keep the DCO oscillation frequency in the range of 4.85
to 5.67 GHz.
Valid values of HSDIV are 4, 5, 6, 7, 9 or 11. N1 can be
selected as 1 or any even num ber u p to 1 28 (i.e. 1 , 2, 4,
6, 8, 10 … 128). To help minimize the device's power
consumption, the divider values should be selected to
keep the DCO's oscillation frequency as low as
possible. The lowest value of N1 with the highest value
of HS_DIV also results in th e best power savings.
Once HS_DIV and N1 have been determined, the next
step is to calculate the reference frequency multiplier
(RFREQ).
RFREQ is programmable as a 38-bit binary fractional
frequency multiplier with the first 10 most significant bits
(MSBs) representing th e integer portion of the multiplier,
and the 28 least significant bits (LSBs) representing the
fractional portion.
Before entering a fractional number into the RFREQ
register, it must be converted to a 38-bit integer using a
bitwise left shift operation by 28 bits, which effectively
multiplies RFREQ by 228.
Example:
RFREQ = 46.043042064d
Multiply RFREQ by 228 = 12359584992.1
Discard the fractional portion = 12359584992
Convert to hexadecimal = 02E0B04CE0h
In the example above, the multiplication operation
requires 38-bit precision. If 38-bit arithmetic precision is
not available, then the fractional portion can be
separated from the integer and shifted to the left by 28-
bits. The result is concatenated with the integer portion
RFREQnew 0x2EBB04CE0 148.50 MHz
148.35 MHz
--------------------------------
0x2EC71D666
=
=
fXTAL Fout HSDIVN1
RFREQ
---------------------------------------------------
=
fDCO_new fout_new HSDIVnew
N1new
=
RFREQnew fDCO_new
fXTAL
-----------------------
=
Si570/Si571
Rev. 1.5 17
to form a full 38-bit word. An example of this operation is shown in Figure 4.
Figure 4. Example of RFREQ Decimal to Hexadecimal Conversion
3.1.2.1. Writing the New Frequency Configuration
Once the new valu es for RFREQ, HSDI V, and N1 are determ ined , they ca n be writ ten dir ectly in to the de vice fr om
the serial port using the following procedure:
1. Freeze the DCO (bit 4 of Register 137)
2. Write the new frequency configuration (RFREQ, HSDIV, and N1) to addresses 7–12 for all Si571 devices and
Si570 devices with 20 ppm and 50 ppm temperature st ability; or addresses 13–18 for Si570 devices with 7 ppm
temperature stability.
3. Unfreeze the DCO and assert the NewF req bit (bit 6 of Register 135) within the maximu m Unfreeze to NewFreq
Timeout specified in Table 11, “Programming Constraints and Timing,” on page 13.
The process of freezing and unfreezing the DCO will cause the output clock to momentarily stop and start at any
arbitrary point during a clock cycle. This process can take up to 10 ms. Circuitry that is sensitive to glitches or runt
pulses may have to be reset after the new frequency configuration is written.
Example:
An Si570 generating 156.25 MHz must be re-configured to generate a 161.1328125 MHz clock (156.25 MHz x 66/
64). This frequency change is greater than ±3500 ppm.
fout =156.25MHz
Read the current values for RFREQ, HS_DIV, N1:
RFREQcurrent = 0x2BC011EB8h = 11744124600d, 11744124600d x 228 = 43.7502734363d
HS_DIV = 4
N1 = 8
Calculate fXTAL, fDCO_current
46.043042064
Convert integer portion to a 10-bit binary number
46 = 00 0 01 0 11 10b
Concatenate the two results
00 0010 1110 0000 1011 0000 0100 1100 1110 0000b
Con v e rt to He x
02E0B04CE0h
Multiply the fractional portion by 228
.043042064 x 228 = 115540 16.077
Truncate the remaining fractional portion
= 11554016
Convert to a 28-bit binary number (pad 0s on the left)
0000 1011 0000 0100 1100 1 110 00 00
fDCO_current fout HSDVN15.000000000 GHz==
fXTAL fDCO_current
RFREQcurrent
---------------------------------------114.285 MHz==
Si570/Si571
18 Rev. 1.5
Given fout_new = 161.1328125 MHz, choose output dividers that will keep fDCO within the range of 4.85 to
5.67 GHz. In this case, keeping the same output dividers will still keep fDCO within its range limits:
Calculate the new value of RFREQ given the new DCO frequency:
fDCO_new fout_new HSDVnew
N1new
161.1328125 MHz 485.156250000 GHz
=
==
RFREQnew fDCO_new
fXTAL
-----------------------45.11746948
0x2D1E127AD=
==
Si570/Si571
Rev. 1.5 19
3.2. Si570 Programming Procedure
This following example was generated using Si514/70/71/98/99 Programmable Oscillator Software V4.0.1 found
under the Tools tab at the following web page.
http://www.siliconlabs.com/products/clocksoscillators/oscillators/Pages/i2c-oscillator.aspx
On that same web page, the AN334 Si57x I2C XO/VCXO ANSI C Reference Design contains example C code for
calculating register settings on the fly.
1. Read start-up frequency configuration (RFREQ, HS_DIV, and N1) from the device after power-up or register
reset.
Registers for the Current Configuration
Register Data
7 0x01
8 0xC2
9 0xBC
10 0x01
11 0x1E
12 0xB8
RFREQ = 0x2BC011EB8
= 0x2BC011EB8 / (2^28) = 43.75027344
HS_DIV = 0x0 = 4
N1 = 0x7 = 8
2. Calculate the actual nominal crystal frequency where f0 is the start-up output frequency.
fxtal = ( f0 x HS_DIV x N1 ) / RFREQ
= (156.250000000 MHz x 4 x 8) / 43.750273436
= 114.285000000 MHz
3. Choose the new output frequency (f1).
Output Frequency (f1) = 161.132812000 MHz
4. Choose the output dividers for the new frequency configuration (HS_DIV and N1) by ensuring the DCO
oscillation frequency (fdco) is between 4.85 GHz and 5.67 GHz where fdco = f1 x HS_DIV x N1. See the Divider
Combinations tab for more options.
HS_DIV = 0x0 = 4
N1 = 0x7 = 8
fdco = f1 x HS_DIV x N1
= 161.132812000 MHz x 4 x 8
= 5.156249984 GHz
Si570/Si571
20 Rev. 1.5
5. Calculate the new crystal frequency multiplica tio n ratio (RFREQ) as RFREQ = fdco / fxtal
RFREQ = fdco / fxtal
= 5.156249984 GHz / 114.285000000 MHz
= 45.11746934
= 45.11746934 x (2^28) = 0x2D1E12788
6. Freeze the DCO by setting Freeze DCO = 1 (bit 4 of register 137).
7. Write the new frequency configuration (RFREQ, HS_DIV, and N1)
Registers for the New Configuration
Register Data
7 0x01
8 0xC2
9 0xD1
10 0xE1
11 0x27
12 0x88
8. Unfreeze the DCO by setting Freeze DCO = 0 and assert the NewFreq bit (bit 6 of register 135) within 10 ms.
Si570/Si571
Rev. 1.5 21
3.3. Si570 Troubleshooting FAQ
1. Is the I2C bus working correctly and using the correct I2C address?
Probing the device I2C pins with an oscilloscope can sometimes reveal signal integrity problems. Si570/Si571 I2C
communication is normally very robust, so if other devices on the I2C bus are communicating successfully, then the
Si570/Si571 should also work.
You can confirm the specific I2C address expected by an Si570/Si571 device by using the part number lookup
utility available on the Silicon Laboratories web site.
http://www.silabs.com/custom-timing
2. Is the correct register bank being written based on device stability?
Si570/Si571 devices use different configuration registers for 7 ppm temperature stability devices than they do for
20 ppm or 50 ppm temperature stability devices. The temperature stability of a Si570/Si571 device can be
confirmed using the part number lookup utility available on the Silicon Laboratories web site or by referencing the
2nd ordering optio n code in the par t number.
http://www.silabs.com/custom-timing
2nd Ordering Option Code:
A : 50 ppm temperature stability, 61.5 ppm total stability => Configuration Registers 7-12
B : 20 ppm temperature stability, 31.5 ppm total stability => Configuration Registers 7-12
C : 7 ppm temperature stability, 20 ppm total stability => Configuration Registers 13-18
3. Is the part-to-part variation in FXTAL included in calculations?
It is required that one determine the internal crystal frequency for each individual part before calculating a new
output frequency. The procedure for determining the internal crystal frequency from the register values of a device
is described elsewhere in this data sheet. See Section 3.2.
FXTAL = (FOUT x HSDIV x N1) / RFREQ <= note that RFREQ used here is the
register value divided by 2^28
It is a common error to calculate the internal crystal frequency for one device and then use that same crystal
frequency for all later devices. This will lead to offset errors in the output frequency accuracy from part-to-part. The
internal crystal frequency must be calculated for ea ch individual device.
4. Is the Unfreeze to NewFreq timeout spec being exceeded?
The Si570/Si571 requires the DCO to be 'frozen' when changing register values and then 'unfrozen' and a
calibration initiated by writing the 'NewFreq' bit to restart it properly. If the 'unfreeze' and 'NewFreq' writes are
delayed by 10 ms or more, the internal state machine can timeout and cause the configuration to revert to default
values.
This 'unfreeze' and 'NewFreq' timing requirement is not usually a problem since the writes are done back-to-back,
but if there is an interrupt or other system delay that may cause this 10 ms timing to be exceeded, it should be
considered as a possible source of issues reprogramming the Si570/Si571.
Si570/Si571
22 Rev. 1.5
3.4. I2C Interface
The control interface to the Si570 is an I2C-compatible 2-wire bus for bidirectional communication. The bus
consists of a bidirectio nal serial dat a line (SDA) and a serial clock inp ut (SCL). Both lines must be co nnected to the
positive supply via an external pullup. Fast mode operation is supported for transfer rates up to 400 kbps as
specified in the I2C-Bus Specification standard.
Figure 5 shows the command format for both read and write access. Data is always sent MSB. Data length is 1
byte. Read and write commands support 1 or more data bytes as illustrated. The master must send a Not
Acknowledge and a Stop after the last read data byte to terminate the read command. The timing specifications
and timing diagram for the I2C bus can be found in the I2C-Bus Specification standard (fast mode operation). The
device I2C address is specified in the part number.
Figure 5. I2C Command Format
From m aster to slave From slave to m aster
A – Acknowledge (SDA LO W )
N – Not Acknowledge (SDA HIGH ).
R equired after the last data byte to signal the end of the read comand to the slave.
S – ST ART condition
P – ST O P condition
P
A
A
Byte AddressA
S Slave A ddress 0 Data
W rite C om m and
(Optional 2 nd data byte and acknowledge illustrated)
A
Byte AddressA
S Slave A ddress 0 SSlave Address 1 A
AData
A
Data Data NP
Read Com mand
(Optional data byte and acknowle dge before the last data byte and n ot acknowledge illustrated)
Si570/Si571
Rev. 1.5 23
4. Serial Port Registers
Note: Any register not listed here is reserved and must not be written. All bits are R/W unless otherwise noted.
Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
7 High Speed/
N1 Dividers HS_DIV[2:0] N1[6:2]
8 Reference
Frequency N1[1:0] RFREQ[37:32]
9 Reference
Frequency RFREQ[31:24]
10 Reference
Frequency RFREQ[23:16]
11 Reference
Frequency RFREQ[15:8]
12 Reference
Frequency RFREQ[7:0]
13 High Speed/
N1 Dividers HS_DIV_7PPM[2:0] N1_7PPM[6:2]
14 Reference
Frequency N1_7PPM[1:0] RFREQ_7PPM[37:32]
15 Reference
Frequency RFREQ_7PPM[31:24]
16 Reference
Frequency RFREQ_7PPM[23:16]
17 Reference
Frequency RFREQ_7PPM[15:8]
18 Reference
Frequency RFREQ_7PPM[7:0]
135 Reset/Freeze/
Memory Control RST_REG NewFreq Freeze M Freeze
VCADC RECALL
137 Freeze DCO Freeze
DCO
Si570/Si571
24 Rev. 1.5
Register 7. High Speed/N1 Dividers
BitD7D6D5D4D3D2D1D0
Name HS_DIV[2:0] N1[6:2]
Type R/W R/W
Bit Name Function
7:5 HS_DIV[2:0] DCO High Speed Divider.
Sets value for high speed divider that takes the DCO output fOSC as its clock input.
000 = 4
001 = 5
010 = 6
011 = 7
100 = Not used.
101 = 9
110 = Not used.
111 = 11
4:0 N1[6:2] CLKOUT Output Divider.
Sets value for CLKOUT output divider. Allowed values are [1] and [2, 4, 6, ..., 27]. Illegal
odd divider values will be rounded up to the nearest even value. The value for the N1 reg-
ister can be calculated by t aking the divider ra tio minus one. For example, to d ivide by 10,
write 0001001 (9 decimal) to the N1 registers.
0000000 = 1
1111111 = 27
Register 8. Refe ren c e Fre que n cy
BitD7D6D5D4D3D2D1D0
Name N1[1:0] RFREQ[37:32]
Type R/W R/W
Bit Name Function
7:6 N1[1:0] CLKOUT Output Divider.
Sets value for CLKOUT output divider. Allowed values are [1, 2, 4, 6, ..., 27]. Illegal odd
divider values will be rounded up to the nearest even value. The value for the N1 regis-
ter can be calculated by taking the divider ratio minus one. For example, to divide by
10, write 0001001 (9 decimal) to the N1 registers.
0000000 = 1
1111111 = 27
5:0 RFREQ[37:32] Reference Frequency.
Frequency control input to DCO.
Si570/Si571
Rev. 1.5 25
Register 9. Refe ren c e Fre que n cy
BitD7D6D5D4D3D2D1D0
Name RFREQ[31:24]
Type R/W
Bit Name Function
7:0 RFREQ[31:24] Reference Frequency.
Frequency control input to DCO.
Register 10. Reference Frequency
BitD7D6D5D4D3D2D1D0
Name RFREQ[23:16]
Type R/W
Bit Name Function
7:0 RFREQ[23:16] Reference Frequency.
Frequency control input to DCO.
Register 11. Reference Frequency
BitD7D6D5D4D3D2D1D0
Name RFREQ[15:8]
Type R/W
Bit Name Function
7:0 RFREQ[15:8] Reference Frequency.
Frequency control input to DCO.
Si570/Si571
26 Rev. 1.5
Register 12. Reference Frequency
BitD7D6D5D4D3D2D1D0
Name RFREQ[7:0]
Type R/W
Bit Name Function
7:0 RFREQ[7:0] Reference Frequency.
Frequency control input to DCO.
Register 13. High Speed/N1 Dividers
BitD7D6D5D4D3D2D1D0
Name HS_DIV_7PPM[2:0] N1_7PPM[6:2]
Type R/W R/W
Bit Name Function
7:5 HS_DIV_7PPM[2:0] DCO High Speed Divider.
Sets value for high speed divider that takes the DCO output fOSC as its clock input.
000 = 4
001 = 5
010 = 6
011 = 7
100 = Not used.
101 = 9
110 = Not used.
111 = 11
4:0 N1_7PPM[6:2] CLKOUT Output Divider.
Sets value for CLKOUT outp ut divider. Allowed values are [1] and [2, 4, 6, ..., 27]. Ille-
gal odd divider values will be rounded up to the nearest even value. The value for the
N1 register can be calculated by t aking the divider ratio minus one. For example, to
divide by 10, write 0001001 (9 decimal) to the N1 regi sters.
0000000 = 1
1111111 = 27
Register 14. Reference Frequency
BitD7D6D5D4D3D2D1D0
Name N1_7PPM[1:0] RFREQ_7PPM[37:32]
Type R/W R/W
Si570/Si571
Rev. 1.5 27
Bit Name Function
7:6 N1_7PPM[1:0] CLKOUT Output Divider.
Sets value for CLKOUT output divider. Allowed values are [1, 2, 4, 6, ..., 27]. Illegal
odd divider values will be rounded up to the nearest even value. The value for the
N1 register can be calcu lated by taking t he divider ratio minus one. For ex ample, to
divide by 10, write 0001001 (9 decimal) to the N1 registers.
0000000 = 1
1111111 = 27
5:0 RFREQ_7PPM[37:32] Reference Frequency.
Frequency control input to DCO.
Register 15. Reference Frequency
BitD7D6D5D4D3D2D1D0
Name RFREQ_7PPM[31:24]
Type R/W
Bit Name Function
7:0 RFREQ_7PPM[31:24] Reference Fre quency.
Frequency control input to DCO.
Register 16. Reference Frequency
BitD7D6D5D4D3D2D1D0
Name RFREQ_7PPM[23:16]
Type R/W
Bit Name Function
7:0 RFREQ_7PPM[23:16] Reference Freq uen cy.
Frequency control input to DCO.
Register 17. Reference Frequency
BitD7D6D5D4D3D2D1D0
Name RFREQ_7PPM[15:8]
Type R/W
Si570/Si571
28 Rev. 1.5
Bit Name Function
7:0 RFREQ_7PPM[15:8] Reference Frequency.
Frequency control input to DCO.
Register 18. Reference Frequency
BitD7D6D5D4D3D2D1D0
Name RFREQ_7PPM[7:0]
Type R/W
Bit Name Function
7:0 RFREQ_7PPM[7:0] Reference Frequency.
Frequency control input to DCO.
Si570/Si571
Rev. 1.5 29
Reset settings = 00xx xx00
Reset settings = 00xx xx00
Register 135. Reset/Freeze/Memory Control
BitD7D6D5 D4 D3D2D1D0
Name RST_REG NewFreq Freeze M Freeze VCADC N/A RECALL
Type R/W R/W R/W R/W R/W R/W
Bit Name Function
7 RST_REG Internal Reset.
0 = Normal operation.
1 = Reset of all internal logic. Output tristated during reset.
Upon completion of internal logic reset, RST_REG is internally reset to zero.
Note: Asserting RST_REG will interrupt the I2C state machine. It is not the recommended
approach for starting from initial conditions.
6 NewFreq New Frequency Applied.
Alerts the DSPLL that a new frequency configuration has been applied. This bit will
clear itself when the new frequency is applied.
5 Freeze M Freezes the M Control Word.
Prevents interi m frequency changes when writing RFREQ registers.
4Freeze
VCADC Freezes the VC ADC Output Word.
May be used to hold the nominal output frequency of an Si571.
3:1 N/A Always Zero.
0 RECALL Recall NVM into RAM.
0 = No operation.
1 = Write NVM bits into RAM. Bit is internally reset following completion of operation.
Note: Asserting RECALL reloads the NVM contents in to the operating registers without
interrupting the I2C state machine. It is the recommended approach for starting from
initial conditions.
Register 137. Freeze DCO
BitD7D6D5D4D3D2D1D0
Name Freeze
DCO
Type R/W
Bit Name Function
7:5 Reserved
4 Freeze DCO Freeze DCO.
Freezes the DSPLL so the frequency configur ation can be modified.
3:0 Reserved
Si570/Si571
30 Rev. 1.5
5. Si570 (XO) Pin Descriptions
Table 14. Si570 Pin Descriptions
Pin Name Type Function
1NC N/A No Connect. Ma ke no exte rn al connec tion to this pin.
2OE Input Output Enable:
See "7. Ordering Information" on page 32.
3GND Ground Electrical and Case Ground.
4CLK+ Output Oscillator Output.
5CLK–
(NC for CMOS*) Output
(N/A for CMOS*) Complementary Output.
(NC for CMOS*).
6 VDD Power Power Supply Voltage.
7SDA Bidirectional
Open Drain I2C Serial Data.
8SCL Input I2C Serial Clock.
*Note: CMOS output option only: make no external connection to this pin.
(Top View)
1
2
3
6
5
4
NC
GND
OE
VDD
CLK+
CLK–
SDA
SCL
8
7
Si570/Si571
Rev. 1.5 31
6. Si571 (VCXO) Pin Descriptions
Table 15. Si571 Pin Descriptions
Pin Name Type Function
1 VCAnalog Input Control Voltage
2OE Input Output Enable:
See "7. Ordering Information" on page 32.
3GND Ground Electrical and Case Ground
4CLK+ Output Oscillator Output
5CLK–
(NC for CMOS*) Output
(N/A for CMOS*) Complementary Output.
(NC for CMOS*).
6 VDD Power Power Supply Voltage
7SDA Bidirectional
Open Drain I2C Serial Data
8SCL Input I2C Serial Clock
*Note: CMOS output option only: make no external connection to this pin.
(Top View)
1
2
3
6
5
4
VC
GND
OE
VDD
CLK+
CLK–
SDA
SCL
8
7
Si570/Si571
32 Rev. 1.5
7. Ordering Information
The Si570/Si571 supports a wide variety of options including frequency range, start-up frequency, temperature
stability, tuning slope, output format, and VDD. Specific device configura tions are p rog ramme d into the Si57 0/Si571
at time of shipment. Configurations are specified using the Part Number Configuration chart shown below. Silicon
Labs provides a web browser-based part number configuration utility to simplify this process. Refer to
www.siliconlabs.com/VCXOPartNumber to access this tool and for further ordering instructions. The Si570/Si571
XO/VCXO series is supplied in an industry-standard, RoHS compliant, 8-pad, 5 x 7 mm package. Tape and reel
packaging is an or dering option.
Figure 6. Part Number Convention
570 Programmable
XO Product Family
57x X
1st Option Code
VDD Output Format Output Enable Polarity
A 3.3 LVPECL High
B 3.3 LVDS High
C 3.3 CMOS High
D3.3CML High
E 2.5 LVPECL High
F2.5LVDS High
G 2.5 CMOS High
H2.5CML High
J 1.8 CMOS High
K1.8CML High
M 3.3 LVPECL Low
N3.3LVDS Low
P3.3CMOS Low
Q3.3CML Low
R 2.5 LVPECL Low
S2.5LVDS Low
T2.5CMOS Low
U2.5CML Low
V1.8CMOS Low
W1.8CML Low
Note:
CMOS available to 160 MHz.
571 Programmable
VCXO Product Family
R = Tape & Reel
Blank = Trays
Operating Temp Range (°C)
G –40 to +85 °C
Device Revision Lette r
X D G R
Six-Digit Start -up Frequency/I2C Address Designator
The Si57x supports a user-defined start-up frequency within the following
bands of frequencies: 10–945 MHz, 970–1134 MHz, and 1213–1417 MHz.
The start-up frequency must be in the same frequency range as that
specified by the Frequency Grade 3rd option code.
The Si57x sup p orts a user-defined I2C 7-bit address. Each unique start-up
frequency/I2C address combination is assigned a six- digit numerical code.
This code can be requested during the pa rt number request process. Refer
to www.silabs.com/VCXOPartNumber to request an Si57x part number.
XXXX XXX
3rd Option Code
Frequency Grade
Code Frequency Range Supp orted (MHz)
A 10-945, 970-113 4, 1213-1417.5
B 10-810
C 10-280 (CMOS available to 160 MHz)
2nd Option Code
Temperature Tuning Slope Minimum APR
Stability Kv (±ppm) for VDD @
Code ± ppm (max) ppm/V (typ) 3.3 V 2.5 V 1.8 V
A 100 180 100 75 25
B 100 90 30 Note 6 Note 6
C 50 180 150 125 75
D50 90 803025
E 20 45 25 Not e 6 Note 6
F 50 135 100 75 50
G 20 356 375 300 235
H 20 180 185 145 105
J 20 135 130 104 70
K 100 356 295 220 155
M 20 33 12 Note 6 Note 6
Notes:
1. For best jitter an d phase noise performance, always choose the smallest Kv that meets
the applicati on’s minimum APR requirements . U nlike SAW-based solutions which
require higher hi gher Kv values to account for their higher temperature dependence,
the Si55x series provides lower Kv options to minimize noise coupling and jit ter in real-
world PLL desig ns. See AN255 and AN2 66 for more information.
2. APR is the ability of a VCXO to track a signal over the product li feti me. A VCXO with an
APR of ±25 ppm is able to lock to a clock with a ±2 5 ppm stability over 15 years over all
operating cond it ions.
3. Nominal Pull range (± ) = 0.5 x VDD x tuning slope.
4. Nominal Absolute Pull Range (±APR) = Pull range – stability – lifetime agin g
= 0.5 x VDD x tu ning slope – stability – 10 ppm
5. Minimum APR values noted above include wo rst case values for all parame ters.
6. Combinati o n not available.
Si570
Si571
2nd Option Code
Code Temperature Stability (ppm, max , ± ) Total Stablility (ppm, max, ±)
A 50 61.5
B 20 31.5
C 7 20
Si570/Si571
Rev. 1.5 33
8. Si57x Mark Specification
Figure 7 illustrates the mark specification for the Si57x. Table 16 lists the line information.
Figure 7. Mark Specification
Table 16. Si57x Top Mark Description
Line Position Description
1 1–10 “SiLabs”+ Part Family Number, 57x (First 3 characters in part number wher e x = 0
indicates a 570 device and x = 1 indicates a 571 device)
2 1–10 Si570, Si571: Option1 + Option2 + Option3 + ConfigNum(6) + Temp
3 Trace Code
Position 1 Pin 1 orientation mark (dot)
Position 2 Product Revision (D)
Position 3–6 Tiny Trace Code (4 alphanumeric characters per assembly release instructions)
Position 7 Year (least significant year digit), to be assigned by assembly site (ex: 20 07 = 7)
Position 8–9 Calendar Work Week number (1–53), to be assigned by assembly site
Position 10 “+” to indicate Pb-Free and RoHS-compliant
Si570/Si571
34 Rev. 1.5
9. Outline Diagram and Suggested Pad Layout
Figure 8 illustrates the package details for the Si570/Si571. Table 17 lists the values for the dimensions shown in
the illustration.
Figure 8. Si570/Si571 Outline Diagram
Table 17. Package Diagram Dimensions (mm)
Dimension Min Nom Max
A 1.50 1.65 1.80
b 1.30 1.40 1.50
b1 0.90 1.00 1.10
c 0.50 0.60 0.70
c1 0.30 — 0.60
D 5.00 BSC
D1 4.30 4.40 4.50
e 2.54 BSC
E 7.00 BSC
E1 6.10 6.20 6.30
H 0.55 0.65 0.75
L 1.17 1.27 1.37
L1 1.07 1.17 1.27
p 1.80 — 2.60
R0.70 REF
aaa — — 0.15
bbb — — 0.15
ccc — — 0.10
ddd — — 0.10
eee — — 0.05
Note:
1. All dimensions shown are in millimeters (mm) unl ess oth erwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
Si570/Si571
Rev. 1.5 35
10. 8-Pin PCB Land Pattern
Figure 9 illustrates the 8-pin PCB land pattern for the Si570/Si571. Table 18 lists the values for the dimensions
shown in the illustration.
Figure 9. Si570/Si571 PCB Land Pattern
Table 18. PCB Land Pattern Dimensions (mm)
Dimension Min Max
D2 5.08 REF
D3 5.705 REF
e 2.54 BSC
E2 4.20 REF
GD 0.84 —
GE 2.00 —
VD 8.20 REF
VE 7.30 REF
X1 1.70 TYP
X2 1.545 TYP
Y1 2.15 REF
Y2 1.3 REF
ZD — 6.78
ZE — 6.30
Note:
1. Dimensioning and tolerancing per th e ANSI Y14.5M-1994
specification.
2. Land pattern design follows IPC-7351 guidelines.
3. All dimensions shown are at maximum material conditio n
(MMC).
4. Controlling dimension is in millime ters (mm).
Si570/Si571
36 Rev. 1.5
DOCUMENT CHANGE LIST
Revision 1.0 to Revision 1.1
Restored programmin g constraint information on
page 15 and in Table 12, page 12.
Clarified NC (No Connect) pin designa tions in Tables
13–14 on pages 22–23.
Revision 1.1 to Revision 1.2
Replaced “Unfreeze to Newfreq Delay” with the
clearer terminology “Unfreeze to Newfreq Timeout”
on page 15 and in Table 11 on page 13.
Added Freeze M procedure on page 14 for
preventing output clock chan ges during small
frequency change multi-register RFREQ writes.
Added Freeze M, Freeze VCADC, and RST_REG
versus RECALL information to Register 135
references in "4. Serial Port Registers" on pages 17
and 20.
Added Si570 20 ppm Total Stability Ordering Option
to Figure 6 on page 32.
Updated Figure 8 and Table 17 on page 34 to
include production test sidepads. This change is for
reference only as the sidepads are raised above the
seating plane and do not impact PCB layout.
Corrected errors in Table 10 on page 12.
Revision 1.2 to Revision 1.3
Updated Table 3 on page 6 to include 7 ppm
temperature stability and 20 ppm to stability
parameters. Also changed aging test condition
(frequency drift over life) from 15 years to 20 years.
Updated 2.5 V/3.3 V and 1.8 V CML output level
specification fo r Table 4 on page 7.
Added footnote s c lar ifyin g m ax offset freque nc y tes t
conditions in Table 5 on page 8.
Updated ESD HBM sensitivity r ating and the JEDEC
standard in Note 2 in Table 13 on page 14.
Updated Table 10 on page 12 to inclu d e "Moisture
Sensitivity Level" and "Contact Pads" rows.
Added Si570 7 ppm Total S tability Ordering Option to
Figure 6 on page 32 .
Updated Figure 7 and Table 16 on p age 33 to refle ct
specific marking information. Previously, Figure 7
was generic.
Clarified "3.1.2. Reconfiguring the Output Clock for
Large Changes in Ou tput Frequency" on page 16
and added new registers 13-18 in "4. Serial Port
Registers" on pa ge 23 for the Si570 7 ppm
temperature stability / 20 ppm total stability ordering
option.
Added text to "3. Functional Description" on page 15,
paragraph 1, to state that the total output jitter
complies to and exceeds strict requirements of
various high-speed communication systems.
Revision 1.3 to Revision 1.4
Added Table 12, “Thermal Characteristics,” on
page 13.
Revision 1.4 to Revision 1.5
Added Section 3. 2 an d 3. 3.
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570AAC000107DG 570FBB000121DG 571CDC000107DG 570CAC000141DG 571MEB000105DG
571MDB000105DG 571AJA000192DG 571CHC000219DG 570TAC000285DG 570AAB000126DG
570BBB000141DG 570CAC000110DG 570ABC000110DG 571NMB000107DG 570AAA000121DG
570CAC000215DG 570ABA000164DG 570BBA000141DG 570MBA000265DG 570BBA000115DG
571BHA000107DG 570CBC000267DG 570PAC000107DG 570AAC000121DG 570ABB000121DG
570BAC000121DG 570DAC000107DG 571ECB000107DG 571ECA000107DG 571DCB000106DG
570BBB000115DG 570BBA000200DG 570NBC000142DG 570ABB000251DG 570FBB000118DG
571AHA000112DG 571CHC000107DG 570BBA000144DG 571BCA000107DG 570AAA000179DG
570CAC000310DG 571NCA000107DG 570BAC000306DG 571AHA000107DG 571BEB000107DG
570BAA000126DG 570ABA000413DG 571AMA000107DG 570BBB000422DG 570BAC000424DG
570RBA000115DG 571AMA000501DG 571FDC000159DG 570FAC000159DG 570PBC000447DG
571BBC000104DG 571AEA000444DG 571AGA000107DG 570BAA000141DG 570CBC000111DG
571JDC000371DG 571JDC000368DG 571KDC000370DG 571FDC000368DG 571BMA000107DG
571FMA000107DG 571NMA000107DG 570DBA000408DG 570ABB000116DG 570BBC000464DG
570BBC000465DG 570BBC000199DG 571BCB000103DG 570BBC000552DG 571AHA000550DG
570DAA000107DG 570ABA000571DG 570ABB000141DG 570BAB000159DG 570BBB000159DG
570CBC000573DG 571CEC000574DG 570FAA000575DG 570FAA000576DG 570MBA000517DG
571SHA000115DG 570ABA000112DG 570SBB000273DG 570MAA000547DG 571MJA000542DG
570CAC000557DG 571BHC000107DG 571BHB000107DG 571ACB000282DG 570FBB000309DG
570FBB000536DG 571BJA000107DG 570BAB000313DG 570BBA000566DG 570ABA000568DG
