Vishay Siliconix
Si3445DV
Document Number: 70820
S09-0766-Rev. C, 04-May-09
www.vishay.com
1
P-Channel 1.8-V (G-S) MOSFET
FEATURES
• Halogen-free According to IEC 61249-2-21
Definition
• TrenchFET® Power MOSFETs
• 1.8 V Rated
• Compliant to RoHS Directive 2002/95/EC
PRODUCT SUMMARY
VDS (V) RDS(on) (Ω)I
D (A)
- 8
0.042 at VGS = - 4.5 V ± 5.6
0.060 at VGS = - 2.5 V ± 4.7
0.080 at VGS = - 1.8 V ± 2.9
T
SO
P-6
Top View
6
4
1
2
3
5
2.85 mm
3 mm
Ordering Information: Si3445DV-T1-E3 (Lead (Pb)-free)
Si3445DV-T1-GE3 (Lead (Pb)-free and Halogen-free)
(4) S
(3) G
(1, 2, 5, 6) D
P-Channel MOSFET
Notes:
a. Surface Mounted on FR4 board.
b. t ≤ 5 s.
ABSOLUTE MAXIMUM RATINGS TA = 25 °C, unless otherwise noted
Parameter Symbol Limit Unit
Drain-Source Voltage VDS - 8 V
Gate-Source Voltage VGS ± 8
Continuous Drain Current (TJ = 150 °C)a, b TA = 25 °C ID
± 5.6
A
TA = 70 °C ± 4.5
Pulsed Drain Current IDM ± 20
Continuous Source Current (Diode Conduction)a, b IS- 1.7
Maximum Power Dissipationa, b TA = 25 °C PD
2.0 W
TA = 70 °C 1.3
Operating Junction and Storage Temperature Range TJ, Tstg - 55 to 150 °C
THERMAL RESISTANCE RATINGS
Parameter Symbol Typical Maximum Unit
Maximum Junction-to-Ambientat ≤ 5 s RthJA
62.5 °C/W
Steady State 106
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Document Number: 70820
S09-0766-Rev. C, 04-May-09
Vishay Siliconix
Si3445DV
Notes:
a. Pulse test; pulse width ≤ 300 µs, duty cycle ≤ 2 %.
b. Guaranteed by design, not subject to production testing.
Stresses beyond those listed under “Absolut e Maximum Ratings” may cause permanent damage to t he device. These are stress rating s only, and functiona l operation
of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
SPECIFICATIONS TJ = 25 °C, unless otherwise noted
Parameter Symbol Test Conditions Min. Typ. Max. Unit
Static
Gate Threshold Voltage VGS(th) VDS = VGS, ID = - 250 µA - 0.45 - 1.0 V
Gate-Body Leakage IGSS VDS = 0 V, VGS = ± 8 V ± 100 nA
Zero Gate Voltage Drain Current IDSS
VDS = - 8 V, VGS = 0 V - 1 µA
VDS = - 8 V, VGS = 0 V, TJ = 70 °C - 5
On-State Drain CurrentaID(on) V
DS ≥ - 5 V, VGS = - 4.5 V - 15 A
Drain-Source On-State ResistanceaRDS(on)
VGS = - 4.5 V, ID = - 5.6 A 0.034 0.042
Ω
VGS = - 2.5 V, ID = - 4.7 A 0.048 0.060
VGS = - 1.8 V, ID = - 2.0 A 0.062 0.080
Forward Transconductanceagfs VDS = - 10 V, ID = - 5.6 A 15 S
Diode Forward VoltageaVSD IS = - 1.7 A, VGS = 0 V - 0.7 - 1.2 V
Dynamicb
Total Gate Charge Qg
VDS = - 4 V, VGS = - 4.5 V, ID = - 5.6 A
15 25
nCGate-Source Charge Qgs 3
Gate-Drain Charge Qgd 2
Tur n - O n D e l ay Time td(on)
VDD = - 4 V, RL = 4 Ω
ID ≅ - 1 A, VGEN = - 4.5 V, Rg = 6 Ω
20 40
ns
Rise Time tr50 100
Turn-Off Delay Time td(off) 110 220
Fall Time tf60 120
Source-Drain Reverse Recovery Time trr IF = - 1.7 A, dI/dt = 100 A/µs 60 100
Document Number: 70820
S09-0766-Rev. C, 04-May-09
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3
Vishay Siliconix
Si3445DV
TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted
Output Characteristics
On-Resistance vs. Drain Current
Gate Charge
0
4
8
12
16
20
01234
2.5 V
2 V
1.5 V
VDS - Drain-to-Source Voltage (V)
-)A( tnerruC niarD ID
1 V
1.8 V
VGS = 5 V thru 3 V
0.00
0.04
0.08
0.12
0.16
0
.
20
04812 16 20
VGS = 4.5 V
VGS = 2.5 V
-(Ω) ecnatsi
s
eR-nO
R
)no(SD
I
D
- Drain Current
(
A
)
VGS = 1.8 V
0
1
2
3
4
5
04812 16
VDS = 4 V
ID = 5.6 A
-)
V( ega
tlo
V
ec
ruoS
-o
t
-e
ta
G
Q
g - Total Gate Charge (nC)
VSG
Transfer Characteristics
Capacitance
On-Resistance vs. Junction Temperature
0
4
8
12
16
20
0.0 0.5 1.0 1.5 2.0 2.5 3.0
TC = - 55 °C
125 °C
V
GS - Gate-to-Source Voltage (V)
-)A( tnerruC niarD I
D
25 °C
0
500
1000
1500
2000
2500
02468
Crss
Coss
Ciss
VDS - Drain-to-Source Voltage (V)
C - ) F p ( e c n a t i c
a p
a C
0.75
1.00
1.25
1.50
- 50 - 25 0 25 50 75 100 125 150
V
GS
= 4.5 V
I
D
= 5.6 A
TJ-Junction Temperature (°C)
R)
no(S
D-ecnat
s
i
s
e
R-
n
O
)
d
ez
i
l
amro
N
(
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4
Document Number: 70820
S09-0766-Rev. C, 04-May-09
Vishay Siliconix
Si3445DV
TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?70820.
Source-Drain Diode Forward Voltage
Threshold Voltage
0.00 0.25 0.50 0.75 1.00 1.25 1.50
V
SD - Source-to-Drain Voltage (V)
- ) A ( t n e r r u C e c r u o S I S
TJ = 150 °C TJ = 25 °C
20
1
10
- 0.2
0.0
0.2
0.4
- 50 - 25 0 25 50 75 100 125 150
TJ- Temperature (°C)
ID = 250 µA
)V( ecnaira
V
VGS(th)
On-Resistance vs. Gate-to-Source Voltage
Single Pulse Power
0.00
0.04
0.08
0.12
0.16
0.20
012345
-(Ω) ecnatsiseR-nO RDS(on)
VGS - Gate-to-Source Voltage (V)
ID = 5.6 A
0.01
0
1
10
25
5
10 6000.1
15
20
100
Time (s)
)W( rew
oP
Normalized Thermal Transient Impedance, Junction-to-Ambient
10-3 10-2 110 60010-1
10-4 100
2
1
0.1
0.01
e v
i
t c e f f E
d e z i
l
a
m
r
o
N t
n e
i s
n a r T
e
c n a d e p
m I
l a
m
r e h
T
0.2
0.1
0.05
0.02
Single Pulse
Duty Cycle = 0.5
1. Duty Cycle, D =
2. Per Unit Base = R
thJA
= 106 °C/W
3. T
JM
- T
A
= P
DM
Z
thJA
(t)
t
1
t
2
t
1
t
2
Notes:
4. Surface Mounted
P
DM
Square Wave Pulse Dureation (s)
Vishay Siliconix
Package Information
Document Number: 71200
18-Dec-06
www.vishay.com
1
1 2 3
Gauge Plane
L
5 4
R
R
C 0.15 M B A
b
C 0.08
0.17 Ref
Seating Plane
-C-
Seating Plane
A
1
A
2 A
-A-
D
-B-
E
1 E
L
2
(L
1
)
c
4x 1
4x 1
e
e1
1 2 3
6 5 4
C 0.15 M B A
b
-B-
E
1 E
e
e1
5-LEAD TSOP 6-LEAD TSOP
TSOP: 5/6−LEAD
JEDEC Part Number: MO-193C
MILLIMETERS INCHES
Dim Min Nom Max Min Nom Max
A 0.91 - 1.10 0.036 - 0.043
A
1 0.01 - 0.10 0.0004 - 0.004
A
2 0.90 - 1.00 0.035 0.038 0.039
b 0.30 0.32 0.45 0.012 0.013 0.018
c 0.10 0.15 0.20 0.004 0.006 0.008
D 2.95 3.05 3.10 0.116 0.120 0.122
E 2.70 2.85 2.98 0.106 0.112 0.117
E
1 1.55 1.65 1.70 0.061 0.065 0.067
e 0.95 BSC 0.0374 BSC
e
1 1.80 1.90 2.00 0.071 0.075 0.079
L 0.32 - 0.50 0.012 - 0.020
L
1 0.60 Ref 0.024 Ref
L
2 0.25 BSC 0.010 BSC
R 0.10 - - 0.004 - -
0 4 8 0 4 8
1 7 Nom 7 Nom
ECN: C-06593-Rev. I, 18-Dec-06
DWG: 5540
AN823
Vishay Siliconix
Document Number: 71743
27-Feb-04
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1
Mounting LITTLE FOOTR TSOP-6 Power MOSFETs
Surface mounted power MOSFET packaging has been based on
integrated circuit and small signal packages. Those packages
have been modified to provide the improvements in heat transfer
required by power MOSFETs. Leadframe materials and design,
molding compounds, and die attach materials have been
changed. What has remained the same is the footprint of the
packages.
The basis of the pad design for surface mounted power MOSFET
is the basic footprint for the package. For the TSOP-6 package
outline drawing see http://www.vishay.com/doc?71200 and see
http://www.vishay.com/doc?72610 for the minimum pad footprint.
In converting the footprint to the pad set for a power MOSFET, you
must remember that not only do you want to make electrical
connection to the package, but you must made thermal connection
and provide a means to draw heat from the package, and move it
away from the package.
In the case of the TSOP-6 package, the electrical connections are
very simple. Pins 1, 2, 5, and 6 are the drain of the MOSFET and
are connected together. For a small signal device or integrated
circuit, typical connections would be made with traces that are
0.020 inches wide. Since the drain pins serve the additional
function of providing the thermal connection to the package, this
level of connection is inadequate. The total cross section of the
copper may be adequate to carry the current required for the
application, but it presents a large thermal impedance. Also, heat
spreads in a circular fashion from the heat source. In this case the
drain pins are the heat sources when looking at heat spread on the
PC board.
Figure 1 shows the copper spreading recommended footprint for
the TSOP-6 package. This pattern shows the starting point for
utilizing the board area available for the heat spreading copper. To
create this pattern, a plane of copper overlays the basic pattern on
pins 1,2,5, and 6. The copper plane connects the drain pins
electrically, but more importantly provides planar copper to draw
heat from the drain leads and start the process of spreading the
heat so it can be dissipated into the ambient air. Notice that the
planar copper is shaped like a “T” to move heat away from the
drain leads in all directions. This pattern uses all the available area
underneath the body for this purpose.
FIGURE 1. Recommended Copper Spreading Footprint
0.049
1.25
0.010
0.25
0.014
0.35
0.074
1.875 0.122
3.1
0.026
0.65
0.167
4.25
0.049
1.25
Since surface mounted packages are small, and reflow soldering
is the most common form of soldering for surface mount
components, “thermal” connections from the planar copper to the
pads have not been used. Even if additional planar copper area is
used, there should be no problems in the soldering process. The
actual solder connections are defined by the solder mask
openings. By combining the basic footprint with the copper plane
on the drain pins, the solder mask generation occurs automatically.
A final item to keep in mind is the width of the power traces. The
absolute minimum power trace width must be determined by the
amount of current it has to carry. For thermal reasons, this
minimum width should be at least 0.020 inches. The use of wide
traces connected to the drain plane provides a low impedance
path for heat to move away from the device.
REFLOW SOLDERING
Vishay Siliconix surface-mount packages meet solder reflow
reliability requirements. Devices are subjected to solder reflow as a
test preconditioning and are then reliability-tested using
temperature cycle, bias humidity, HAST, or pressure pot. The
solder reflow temperature profile used, and the temperatures and
time duration, are shown in Figures 2 and 3.
Ramp-Up Rate +6_C/Second Maximum
Temperature @ 155 " 15_C120 Seconds Maximum
Temperature Above 180_C70 − 180 Seconds
Maximum Temperature 240 +5/−0_C
Time at Maximum Temperature 20 − 40 Seconds
Ramp-Down Rate +6_C/Second Maximum
FIGURE 2. Solder Reflow Temperature Profile
AN823
Vishay Siliconix
www.vishay.com
2Document Number: 71743
27-Feb-04
255 − 260_C
1X4_C/s (max) 3-6_C/s (max)
10 s (max)
Reflow Zone
Pre-Heating Zone
3_C/s (max)
140 − 170_C
Maximum peak temperature at 240_C is allowed.
FIGURE 3. Solder Reflow Temperature and Time Durations
60-120 s (min)
217_C
60 s (max)
THERMAL PERFORMANCE
A basic measure of a device’s thermal performance is the
junction-to-case thermal resistance, Rqjc, or the
junction-to-foot thermal resistance, Rqjf. This parameter is
measured for the device mounted to an infinite heat sink and
is therefore a characterization of the device only, in other
words, independent of the properties of the object to which the
device is mounted. Table 1 shows the thermal performance
of the TSOP-6.
TABLE 1.
Equivalent Steady State Performance—TSOP-6
Thermal Resistance Rqjf 30_C/W
SYSTEM AND ELECTRICAL IMPACT OF
TSOP-6
In any design, one must take into account the change in
MOSFET rDS(on) with temperature (Figure 4).
0.6
0.8
1.0
1.2
1.4
1.6
−50 −25 0 25 50 75 100 125 150
VGS = 4.5 V
ID = 6.1 A
On-Resistance vs. Junction Temperature
TJ − Junction Temperature (_C)
FIGURE 4. Si3434DV
rDS(on) − On-Resiistance
(Normalized)
Application Note 826
Vishay Siliconix
www.vishay.com Document Number: 72610
26 Revision: 21-Jan-08
APPLICATION NOTE
RECOMMENDED MINIMUM PADS FOR TSOP-6
0.119
(3.023)
Recommended Minimum Pads
Dimensions in Inches/(mm)
0.099
(2.510)
0.064
(1.626)
0.028
(0.699)
0.039
(1.001)
0.020
(0.508)
0.019
(0.493)
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Revision: 12-Mar-12 1Document Number: 91000
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