1
2
3
4
5
6
7
8
9
16
15
14
13
12
11
10
A
8
A
9
A
11
A
13
WE
CE
2
A
15
Vcc
NC
A
16
A
14
A
12
A
7
A
6
A
5
A
4
32
31
30
29
28
27
26
25
24
17
18
19
20
21
22
23
CE1
A
10
OE
I/O
8
I/O
7
I/O
6
I/O
5
I/O
4
GND
I/O
3
I/O
2
I/O
1
A
0
A
1
A
2
A
3
1024
X
1024
ROW DECODER
SENSE AMP
INPUT BUFFER
COLUMN DECODER CONTROL
CIRCUIT
I/O
7
I/O
0
OE
WE
CE1
CE2
A
9
A
10
A
11
A
12
A
13
A
14
A
15
A
16
A
8
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
SD18U128
SD18U128L
Ultra Low Power
128K x 8 CMOS SRAM
Features
•Low-power consumption
- Active: 20mA at 70ns
- Stand-by: 5 µA (CMOS input/output)
1 µA CMOS input/output, L version
•Single +1.8to 2.2V Power Supply
•Equal access and cycle time
•70/85/100/150 ns access time
•Easy memory expansion with CE1, CE2
and OE inputs
•1.0V data retention mode
•TTL compatible, Tri-state input/output
•Automatic power-down when deselected
Functional Description
The SD18U128 is a low power CMOS Static RAM orga-
nized as 131,072 words by 8 bits. Easy memory expansion
is provided by an active LOW CE1, an active HIGH CE2,
an active LOW OE, and Tri-state I/O’s. This device has
an automatic power-down mode feature when deselected.
Writing to the device is accomplished by taking Chip
Enable 1 (CE1) with Write Enable (WE) LOW, and Chip
Enable 2 (CE2) HIGH. Reading from the device is per-
formed by taking Chip Enable 1 (CE1) with Output
Enable (OE) LOW while Write Enable (WE) and Chip
Enable 2 (CE2) is HIGH. The I/O pins are placed in a
high-impedance state when the device is deselected: the
outputs are disabled during a write cycle.
The SD18U128L comes with a 1V data retention feature
and Lower Standby Power. The SD18U128 is available in
a 32-pin 8 x 20 mm TSOP1 / STSOP / 48-fpBGA pack-
ages.
32-Pin TSOP1 / STSOP (See next page)
Revised 12/2/98
20410 TOWN CENTER LANE, STE 270 s CUPERTINO, CA 95014 s TEL (408) 255-1262 s FAX (408) 255-1359
Logic Block Diagram
1024
X
1024
ROW DECODER
SENSE AMP
INPUT BUFFER
COLUMN DECODER CONTROL
CIRCUIT
I/O8
I/O1
OE
WE
CE1
CE2
A
10
A
11
A
12
A
13
A
14
A
15
A
16
A
8
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
A
9
SD18U128/SD18U128L
2
Top View
48-CSP Ball-Grid Array package(shading indicates no ball)
1 2 3 4 5 6
A
A
0
A
1
CE2
A
3
A
6
A
8
B
I/O
4
A
2
WE
A
4
A
7
0
C
I/O
5
NC
NC
A
5
NC
1
D
V
SS
NC
NC
NC
NC
V
DD
E
V
DD
NC
NC
NC
NC
V
SS
F
I/O
6
NC
NC
NC
NC
2
G
I/O
7
OE
CE
1
A
16
A
15
3
H
A
9
A
10
A
11
A
12
A
13
A
14
Soft Device, Inc. SD28U128B
TOP VIEW
6
5
4
3
2
1
A B C D E F G H
SD18U128/SD18U128L
Absolute Maximum Ratings *
* Note: Stresses greater than those listed above Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rat-
ing only and functional operation of the device at these or any conditions outside those indicated in the operational sections of this specifica-
tion is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Parameter Symbol Minimum Maximum Unit
Voltage on Any Pin Relative to Gnd Vt -0.5 4.6 V
Power Dissipation PT−1.0 W
Storage Temperature (Plastic) Tstg -55 +150 0C
Temperature Under Bias Tbias -40 +85 0C
Truth Table
* Key: X = Don’t Care, L = Low, H = High
CE1 CE2 WE OE Data Mode
HXXXHigh-Z Standby
XLX X High-Z Standby
LH H LData Out Active, Read
LHHHHigh-Z Active, Output Disable
LHLXData In Active, Write
3
Recommended Operating Conditions (TA = 00C to +700C / -400C to 850C**)
* VIL min = -1.0V for pulse width less than tRC/2.
** For Industrial Temperature.
Parameter Symbol Min Typ Max Unit
VCC 1.8 2.0 2.2 V
Gnd 0.0 0.0 0.0 V
VIH 1.6 -VCC + 0.2 V
VIL -0.5* -0.4 V
Supply Voltage
Input Voltage
AC Test Conditions
Input Pulse Level 0.4V to 1.6V
Input Rise and Fall Time 5ns
Input and Output Timing
Reference Level 50% of input level
(V
IL
+ V
IH
)/2
Output Load Condition
70ns/85 ns C
L
= 30pf + 1TTL Load
Load 100ns/150 ns C
L
= 100pf + 1TTL Load
C
L
*
Figure A. * Including Scope and Jig Capacitance
TTL
SD18U128/SD18U128L
DC Operating Characteristics (Vcc = 1.8 to 2.2V, Gnd = 0V, TA = 00C to +700C / -400C to 850C)
Input Leakage Current IILII Vcc = Max,
Vin = Gnd to Vcc
-1-1-1-1µA
Output Leakage
Current IILOI CE1 = VIH or CE2 = VIL
Vcc= Max, VOUT = Gnd to Vcc -1-1-1-1µA
Operating Power
Supply Current ICC CE1 = VIL , CE2 = VIH
VIN = VIH or VIL , IOUT = 0 mA -3-3-3-3mA
Average Operating
Current
ICC1 CE1 = VIL , CE2 = VIH
IOUT = 0mA,
Min Cycle, 100% Duty
-25 -20 -15 -15 mA
ICC2 CE1 = 0.2V,
CE2 = Vcc - 0.2V
IOUT = 0mA,
Cycle Time=1µs, 100% Duty
-3-3-3-3mA
Standby Power Supply
Current (TTL Level) ISB CE1 = VIH or CE2 = VIL -0.5 -0.5 -0.5 -0.5 mA
Standby Power Supply
Current (CMOS Level) ISB1 CE1 > Vcc - 0.2V or
CE2 < 0.2V, f = 0
VIN < 0.2V or
VIN > Vcc- 0.2V L
-
-
5
1
-
-
5
1
-
-
5
1
-
-
5
1
µA
µA
Output Low Voltage VOL IOL = 2 mA -0.4 -0.4 -0.4 -0.4 V
Output High Voltage VOH IOH = -1 mA 1.6 -1.6 -1.6 -1.6 -V
-70 -100 -150
Unit
Parameter Sym Test Conditions
Min Max Min Max Min Max Min Max
-85
4
Capacitance (f = 1MHz, TA = 250C)
Parameter* Symbol Test Condition Max Unit
Input Capacitance Cin Vin = 0V 7pF
I/O Capacitance CI/O Vin = Vout = 0V 8pF
* This parameter is guaranteed by device characterization and is not production tested.
SD18U128/SD18U128L
Parameter Symbol Unit Note
Read Cycle Time tRC 70 -85 -100 -150 -ns
Address Access Time tAA -70 -85 -100 -150 ns
Chip Enable Access Time tACE -70 -85 -100 -150 ns
Output Enable Access Time tOE -40 -40 -50 -70 ns
Output Hold from Address Change tOH 10 -10 -10 -10 -ns
Chip Enable to Output in Low-Z tCLZ 10 -10 -10 -10 -ns 4,5
Chip Disable to Output in High-Z tCHZ -30 -35 -40 -50 ns 4,5
Output Enable to Output in Low-Z tOLZ 5-5-5-5-ns 4,5
Output Disable to Output in High-Z tOHZ -25 -30 -35 -40 ns 4,5
Power-Up Time tPU 0-0-0-0-ns 5
Power-Down Time tPD -70 -85 -100 -150 ns 5
Read Cycle (3,9) (Vcc = 1.8 to 2.2V, Gnd = 0V, TA = 00C to +700C / -400C to +850C)
Write Cycle (3,11) (Vcc = 1.8 to 2.2V, Gnd = 0V, TA = 00C to +700C / -400C to +850C)
Parameter Symbol Unit Note
Write Cycle Time tWC 70 -85 -100 -150 -ns
Chip Enable to Write End tCW 60 -70 -80 -120 -ns
Address Setup to Write End tAW 60 -70 -80 -120 -ns
Address Setup Time tAS 0-0-0-0-ns
Write Pulse Width tWP 50 -60 -70 -100 -ns
Write Recovering Time tWR 0-0-0-0-ns
Data Valid to Write End tDW 30 -35 -40 -60 -ns
Data Hold Time tDH 0-0-0-0-ns
Write Enable to Output in High-Z tWZ -30 -35 -40 -50 ns 4,5
Output Active from Write End tOW 5-5-5-5-ns 4,5
Min Max Min Max Min Max Min Max
-70 -85 -100
5
Min Max Min Max Min Max Min Max
-70 -85 -100 -150
-150
Timing Waveform of Read Cycle 1
(3,6,7,9)
(Address Controlled)
t
RC
t
AA
t
OH
Data Valid
Address
D
OUT
Timing Waveform of Read Cycle 2
(5,6,8,9)
(CE1 Controlled)
50% 50%
I
CC
I
SB
t
PD
t
CHZ
t
OHZ
t
RC
t
OE
t
OLZ
t
ACE
t
CLZ
t
PU
CE1
OE
D
OUT
Supply Current
Data Valid
Timing Waveform of Read Cycle 3
(3,6,8,9)
(CE2 Controlled)
50% 50%
I
CC
I
SB
t
PD
t
CHZ
t
OHZ
t
RC
t
OE
t
OLZ
t
ACE
t
CLZ
t
PU
CE2
OE
D
OUT
Supply Current
Data Valid
SD18U128/SD18U128L
6
SD18U128/SD18U128L
Timing Waveform of Write Cycle 1
(10,11)
(WE Controlled)
Data Valid
Address
D
OUT
Timing Waveform of Write Cycle 2
(10,11)
(CE1 Controlled)
Timing Waveform of Write Cycle 3
(10,11)
(CE2 Controlled)
D
IN
WE
t
DW
t
DH
t
OW
t
WZ
t
AS
t
WP
t
WR
t
WC
t
AW
D
OUT
D
IN
WE
Address
CE1
Data Valid
t
WZ
t
DW
t
DH
t
WP
t
WC
t
CW
t
AW
t
WR
t
AS
D
OUT
D
IN
WE
Address
CE2
Data Valid
t
WZ
t
DW
t
DH
t
WP
t
WC
t
CW
t
AW
t
WR
t
AS
7
SD18U128/SD18U128L
Data Retention Characteristics (L Version Only)(1)
Parameter Symbol Test Condition Min Max Unit
VCC for Data Retention VDR CE1 > VCC - 0.2V or 1.0 -V
Data Retention Current ICCDR CE2 < + 0.2V
-1µA
Chip Deselect to Data Retention Time tCDR VIN > VCC - 0.2V or 0- ns
Operation Recovery Time(2) tRVIN < 0.2V tRC - ns
Data Retention Mode
V
DR
>
1.0V
Vcc_typ
V
IH
V
IH
V
DR
V
CC
CE
t
R
t
CDR
Vcc_typ
Data Retention Waveform (L Version Only) (TA = 00C to +700C / -400C to +850C)
8
Notes
1. L-version includes this feature.
2. This Parameter is samples and not 100% tested.
3. For test conditions, see AC Test Condition, Figure A.
4. This parameter is tested with CL = 5pF as shown in Figure B. Transition is measured + 500mV from steady-state voltage.
5. This parameter is guaranteed, but is not tested.
6. WE is HIGH for read cycle.
7. CE1 and OE are LOW and CE2 is HIGH for read cycle.
8. Address valid prior to or coincident with CE1 transition LOW or CE2 transition HIGH.
9. All read cycle timings are referenced from the last valid address to the first transtion address.
10. CE1 or WE must be HIGH or CE2 must be LOW during address transition.
11. All write cycle timings are referenced from the last valid address to the first transition address.
SD18U128/SD18U128L
Ordering Information
Device Type* Speed Package
SD18U128K-70 70 ns 8 x 20 mm 32-pin Plastic TSOP1
SD18U128K-85 85 ns
SD18U128K-100 100 ns
SD18U128K-150 150 ns
SD18U128LK-70 70 ns
SD18U128LK-85 85 ns
SD18U128LK-100 100 ns
SD18U128LK-150 150 ns
SD18U128SK-70 70 ns 8 x 13.4 mm 32-pin Plastic STSOP
SD18U128SK-85 85 ns
SD18U128SK-100 100 ns
SD18U128SK-150 150 ns
SD18U128LSK-70 70 ns
SD18U128LSK-85 85 ns
SD18U128LSK-100 100 ns
SD18U128LSK-150 150 ns
SD18U128FG-70 70 ns
SD18U128FG-85 85 ns
SD18U128FG-100 100 ns
SD18U128FG-150 150 ns
Note: Soft Device reserves the right to make changes to its products and to this data sheet at any time, without notice, to improve design or performance.
Soft Device makes no representation that circuits shown are free from patent infringments. Circuitry and other examples shown are meant only to indicate
the performance and characteristics of our products. Soft Device products are not authorized for use as critical components in life support systems without
written permission of the appropriate officer of Soft Device.
9
* For Induatrial Temperature tested devices, an “I” designator will be added to the end of the Device number.