TPS728xx Series www.ti.com SBVS095 - AUGUST 2007 200mA Low-Dropout Linear Regulator with Pin-Selectable Dual-Voltage Level Output FEATURES 1 * * * * 2 * * * * * Very Low Dropout: 230mV Typical at 200mA 3% Accuracy Over Load/Line/Temperature Low IQ: 50A in Active Mode Available in Fixed-Output Voltages From 0.9V to 3.6V Using Innovative Factory EEPROM Programming VSET Pin Toggles Output Voltage Between Two Preset Levels - Preset Output Voltage Levels Can Be EEPROM-Programmed To Any Combination High PSRR: 65dB at 1kHz Stable with a 1.0F Ceramic Capacitor Thermal Shutdown and Over-Current Protection Available in Wafer-Level Chip Scale and 2mm x 2mm SON Packages APPLICATIONS * * * * * Power Rails with Programming Mode Dual Voltage Levels for Power-Saving Mode Leakage Reduction for 90nm and 65nm Processors Wireless Handsets, Smart Phones, PDAs MP3 Players and Other Handheld Products DESCRIPTION The TPS728xx series of low-dropout linear regulators (LDOs), with a selectable dual-voltage level output, is designed specially for applications that require two levels of output voltage regulation. Programming fuses and memory cards, reducing leakage effects, and conserving power in nanometric processes are some application examples. The VSET pin is used to select one of two output voltage levels preset through innovative factory EEPROM programming. A precision bandgap and error amplifier provides an overall 3% accuracy over load, line, and temperature extremes. Ultra-small wafer chip scale (WCSP) and 2mm x 2mm SON packages make the TPS728xx series ideal for handheld applications. This family of devices is fully specified over a temperature range of TJ = -40C to +125C. TPS728xx Series DRV PACKAGE 2mm x 2mm SON-6 (TOP VIEW) TPS728xx Series YZU PACKAGE WCSP-5 (TOP VIEW) C3 C1 IN OUT OUT 1 B2 GND VSET 2 A3 VSET (1) 6 IN Thermal A1 EN Pad(1) NC 3 5 GND 4 EN It is recommended that the SON package thermal pad be connected to ground. 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright (c) 2007, Texas Instruments Incorporated TPS728xx Series www.ti.com SBVS095 - AUGUST 2007 This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ORDERING INFORMATION (1) VOUT (2) PRODUCT TPS728vvvxxxyyyz (1) (2) VVV is the nominal output voltage for VOUT1 and corresponds to VSET = Low. XXX is the nominal output voltage for VOUT2 and corresponds to VSET = High. YYY is package designator. Z is Tape and reel quantity (R = 3000, T = 250). For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com. Output voltages from 0.9V to 3.6V in 50mV increments are available through the use of innovative factory EEPROM programming; minimum order quantities may apply. Contact factory for details and availability. ABSOLUTE MAXIMUM RATINGS (1) At TJ = -40C to +125C (unless otherwise noted). All voltages are with respect to GND. PARAMETER Input voltage range, VIN Enable and VSET voltage range, VEN and VSET Output voltage range, VOUT TPS728xx Series UNIT -0.3 to +7.0 V -0.3 to VIN + 0.3 (2) V -0.3 to +7.0 V Maximum output current, IOUT Internally limited Output short-circuit duration Indefinite Total continuous power dissipation, PDISS See Dissipation Ratings Table Human body model (HBM) ESD rating 2 kV 500 V Operating junction temperature range, TJ -55 to +150 C Storage temperature range, TSTG -55 to +150 C (1) (2) Charged device model (CDM) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not implied. VEN and VSET absolute maximum rating is VIN + 0.3V or +7.0V, whichever is less. DISSIPATION RATINGS BOARD DERATING FACTOR ABOVE TA = +25C TA < +25C TA = +70C TA = +85C 20C/W 65C/W 15.4mW/C 1540mW 845mW 615mW 85C/W 268C/W 3.7mW/C 370mW 205mW 150mW RJC (1) DRV High-K (1) YZU High-K (1) 2 RJA PACKAGE The JEDEC high-K (2s2p) board used to derive this data was a 3- x 3-inch, multilayer board with 1-ounce internal power and ground planes and 2-ounce copper traces on top and bottom of the board. Submit Documentation Feedback Copyright (c) 2007, Texas Instruments Incorporated TPS728xx Series www.ti.com SBVS095 - AUGUST 2007 ELECTRICAL CHARACTERISTICS Over operating temperature range (TJ = -40C to +125C), VIN = VOUT(TYP) + 0.5V or 2.7V, whichever is greater; IOUT = 0.5mA, VSET = VEN = VIN, COUT = 1.0F, unless otherwise noted. Typical values are at TJ = +25C. PARAMETER VIN TEST CONDITIONS Input voltage range Nominal VOUT (1) DC output accuracy VOUT Load transient VO VO/VIN Over VIN, IOUT, VOUT + 0.5V VIN 6.5V, temperature 0mA IOUT 200mA, VSET = high/low Output voltage range VDO Dropout voltage ICL Output current limit ISHDN PSRR (1) (2) (3) (4) (5) -3.0 +3.0 % 60.0 Ground pin current 240 IOUT = 0mA V/V 75 V/mA 230 400 mV 340 575 mA 50 80 A 120 Shutdown current (IGND) 0.10 Power-supply rejection ratio VIN = 3.8V, VOUT = 2.8V, IOUT = 200mA f = 1kHz 65 dB f = 10kHz 55 dB f = 100kHz 40 dB VOUT_LOW = 1.8V, VOUT_HIGH = 3.15V, IOUT = 10mA tSTR Startup time (3) COUT = 1.0F tSHUT Shutdown time (4) RL = , COUT = 1.0F, VOUT = 2.8V Enable and select pin currents EN = VSET = 6.5V Undervoltage lockout VIN rising, VSET = high/low Hysteresis VIN falling, VSET = high/low TSD Thermal shutdown temperature TJ Operating junction temperature A dB Transition time (low-to-high) VOUT = VOUT_LOW to VOUT_HIGH VOUT = 97% x VOUT_HIGH VSET low (output VOUT1 selected), or enable pin low (disabled) 1.0 65 tTR VLO A f = 100Hz BW = 100Hz to 100kHz, VIN = 3.3V, VOUT = 2.8V, IOUT = 10mA VSET high (output VOUT2 selected), or enable pin high (enabled) V 130 VEN 0.4V, 2.7V VIN < 4.5V, TJ = -40C to +85C VHI mV 3.6 IOUT = 200mA Output noise voltage UVLO mV VIN = VOUT(NOM) - 0.1V, IOUT = 200mA VN IEN, IVSET V +2.5 0.9 VOUT = 0.9 x VOUT(NOM) UNIT -2.5 0mA IOUT 200mA (2) MAX 6.5 VOUT(NOM) + 0.5V VIN 6.5V, IOUT = 5mA Line regulation TYP 2.7 100A to 200mA in 1s, 200mA to 100A in 1s, COUT = 1F VO/IOUT Load regulation IGND TJ = +25C, VSET = high/low MIN 75 x VOUT VRMS 60 s 160 s 180 (5) s 1.2 VIN V 0 0.4 V 0.04 1.0 A 2.51 2.65 2.38 V 230 mV Shutdown, temperature increasing +160 C Reset, temperature decreasing +140 -40 C +125 C The output voltage for VSET = low/high is programmed at the factory. VDO is not measured for devices with VOUT(NOM) < 2.8V because minimum VIN = 2.7V. Time from VEN = 1.2V to VOUT = 97% (VOUT(NOM)). Time from VEN = 0.4V to VOUT = 5% (VOUT(NOM)). See Shutdown in the Application Information section for more details. Copyright (c) 2007, Texas Instruments Incorporated Submit Documentation Feedback 3 TPS728xx Series www.ti.com SBVS095 - AUGUST 2007 DEVICE INFORMATION IN OUT Current Limit Thermal Shutdown EEPROM EN Bandgap MUX UVLO Active PullDown VSET 60W LOGIC Figure 1. Functional Block Diagram 4 Submit Documentation Feedback Copyright (c) 2007, Texas Instruments Incorporated TPS728xx Series www.ti.com SBVS095 - AUGUST 2007 YZU PACKAGE WCSP-5 (TOP VIEW) C1 C3 IN OUT B2 GND A3 A1 EN VSET DRV PACKAGE SON-8 (TOP VIEW) OUT 1 6 IN Thermal VSET 2 NC 3 (1) Pad(1) 5 GND 4 EN It is recommended that the SON package thermal pad be connected to ground. PIN DESCRIPTIONS TPS728xx Series NAME DRV YZU DESCRIPTION OUT 1 C1 Regulated output voltage pin. A small 1F ceramic capacitor is needed from this pin to ground to assure stability. See Input and Output Capacitor Requirements in the Application Information section for more details. VSET 2 A3 Select pin. Driving VSET below 0.4V selects preset output voltage VOUT1. Driving VSET over 1.2V selects preset output voltage VOUT2. NC 3 -- No connection. EN 4 A1 Enable pin. Driving EN over 1.2V turns on the regulator. Driving EN below 0.4V puts the regulator into shutdown mode, thus reducing the operating current to 100nA, nominal. GND 5 B2 Ground pin (connect DRV thermal pad to ground) IN 6 C3 Input pin. A small capacitor is needed from this pin to ground to assure stability. See Input and Output Capacitor Requirements in the Application Information section for more details. Copyright (c) 2007, Texas Instruments Incorporated Submit Documentation Feedback 5 TPS728xx Series www.ti.com SBVS095 - AUGUST 2007 TYPICAL CHARACTERISTICS Over operating temperature range (TJ = -40C to +125C), VIN = VOUT(TYP) + 0.5V or 2.7V, whichever is greater; IOUT = 0.5mA, VEN = VSET = VIN, COUT = 1.0F, unless otherwise noted. Typical values are at TJ = +25C. LINE REGULATION IOUT = 5mA, VOUT = 0.9V (nom) LINE REGULATION IOUT = 200mA, VOUT = 0.9V (nom) 5 10 TJ = -40C TJ = +25C TJ = +85C TJ = +125C 4 3 6 4 DVOUT (mV) DVOUT (mV) 2 1 0 -1 2 0 -2 -2 -4 -3 -6 -4 -8 -5 -10 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 TJ = -40C TJ = +25C TJ = +85C TJ = +125C 8 6.5 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VIN (V) VIN (V) Figure 2. Figure 3. LINE REGULATION IOUT = 5mA, VOUT = 1.85V (nom) LINE REGULATION IOUT = 200mA, VOUT = 1.85V (nom) 6 6.0 6.5 6.0 6.5 6.0 6.5 6 3 3 0 DVOUT (mV) DVOUT (mV) 0 -3 -6 -12 -9 TJ = -40C TJ = +25C TJ = +85C TJ = +125C -15 -18 -15 -21 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VIN (V) VIN (V) Figure 4. Figure 5. LINE REGULATION IOUT = 5mA, VOUT = 3.6V (nom) LINE REGULATION IOUT = 200mA, VOUT = 3.6V (nom) 5 10 TJ = -40C TJ = +25C TJ = +85C TJ = +125C TJ = -40C TJ = +25C TJ = +85C TJ = +125C 5 0 DVOUT (mV) 0 DVOUT (mV) -6 -2 TJ = -40C TJ = +25C TJ = +85C TJ = +125C -9 -3 -5 -10 -5 -10 -15 -20 -15 -25 -20 -30 2.5 6 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 2.5 3.0 3.5 4.0 4.5 VIN (V) VIN (V) Figure 6. Figure 7. Submit Documentation Feedback 5.0 5.5 Copyright (c) 2007, Texas Instruments Incorporated TPS728xx Series www.ti.com SBVS095 - AUGUST 2007 TYPICAL CHARACTERISTICS (continued) Over operating temperature range (TJ = -40C to +125C), VIN = VOUT(TYP) + 0.5V or 2.7V, whichever is greater; IOUT = 0.5mA, VEN = VSET = VIN, COUT = 1.0F, unless otherwise noted. Typical values are at TJ = +25C. LOAD REGULATION UNDER LIGHT LOADS VOUT = 0.9V (nom) LOAD REGULATION VOUT = 0.9V (nom) 15 10 TJ = -40C TJ = +25C TJ = +85C TJ = +125C 0 DVOUT (mV) DVOUT (mV) 10 TJ = -40C TJ = +25C TJ = +85C TJ = +125C 5 5 -5 -10 -15 0 -20 -5 -25 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 0 60 80 100 120 140 Figure 8. Figure 9. LOAD REGULATION UNDER LIGHT LOADS VOUT = 1.85V (nom) LOAD REGULATION VOUT = 1.85V (nom) 160 180 200 10 TJ = -40C TJ = +25C TJ = +85C TJ = +125C 6 4 2 TJ = -40C TJ = +25C TJ = +85C TJ = +125C 5 0 DVOUT (mV) DVOUT (mV) 40 IOUT (mA) 8 0 -2 -5 -10 -15 -4 -20 -6 -25 -8 -30 -10 -35 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 0 20 40 60 80 100 120 140 IOUT (mA) IOUT (mA) Figure 10. Figure 11. LOAD REGULATION UNDER LIGHT LOADS VOUT = 3.6V (nom) LOAD REGULATION VOUT = 3.6V (nom) 25 160 180 200 25 TJ = -40C TJ = +25C TJ = +85C TJ = +125C 20 15 TJ = -40C TJ = +25C TJ = +85C TJ = +125C 20 15 10 DVOUT (mV) 10 DVOUT (mV) 20 IOUT (mA) 5 0 -5 5 0 -5 -10 -10 -15 -15 -20 -20 -25 -25 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 0 20 40 60 80 100 120 140 IOUT (mA) IOUT (mA) Figure 12. Figure 13. Copyright (c) 2007, Texas Instruments Incorporated 160 180 Submit Documentation Feedback 200 7 TPS728xx Series www.ti.com SBVS095 - AUGUST 2007 TYPICAL CHARACTERISTICS (continued) Over operating temperature range (TJ = -40C to +125C), VIN = VOUT(TYP) + 0.5V or 2.7V, whichever is greater; IOUT = 0.5mA, VEN = VSET = VIN, COUT = 1.0F, unless otherwise noted. Typical values are at TJ = +25C. DROPOUT VOLTAGE vs OUTPUT CURRENT OUTPUT VOLTAGE vs TEMPERATURE 300 3 TJ = -40C TJ = +25C TJ = +85C TJ = +125C 250 2 1 DVOUT (%) VDO (mV) 200 VOUT = 0.9V 150 100 IOUT = 0.1mA 0 IOUT = 5mA -1 IOUT = 200mA 50 -2 VOUT = 3.6V (nom) VIN = VOUT - 0.1V 0 0 20 40 60 80 100 120 140 160 180 -3 200 -40 -25 -10 5 20 IOUT (mA) 35 50 65 80 95 110 125 TJ (C) Figure 14. Figure 15. OUTPUT VOLTAGE vs TEMPERATURE GROUND PIN CURRENT vs INPUT VOLTAGE 2.0 50 IOUT = 0mA VOUT = 3.6V 1.5 45 IOUT = 0.1mA 0.5 IGND (mA) DVOUT (%) 1.0 0 IOUT = 5mA -0.5 40 35 IOUT = 200mA -1.0 TJ = -40C TJ = +25C TJ = +85C TJ = +125C 30 -1.5 25 -2.0 -40 -25 -10 5 20 35 50 65 80 95 110 125 2.5 4.0 4.5 5.0 5.5 Figure 16. Figure 17. GROUND PIN CURRENT vs OUTPUT CURRENT GROUND PIN CURRENT vs TEMPERATURE 6.0 6.5 60 IOUT = 0mA TJ = -40C TJ = +25C TJ = +85C TJ = +125C 130 55 50 IGND (mA) 110 IGND (mA) 3.5 VIN (V) 150 90 45 70 40 50 35 30 30 0 20 40 60 80 100 120 140 IOUT (mA) Figure 18. 8 3.0 TJ (C) Submit Documentation Feedback 160 180 200 -40 -25 -10 5 20 35 50 65 80 95 110 125 TJ (C) Figure 19. Copyright (c) 2007, Texas Instruments Incorporated TPS728xx Series www.ti.com SBVS095 - AUGUST 2007 TYPICAL CHARACTERISTICS (continued) Over operating temperature range (TJ = -40C to +125C), VIN = VOUT(TYP) + 0.5V or 2.7V, whichever is greater; IOUT = 0.5mA, VEN = VSET = VIN, COUT = 1.0F, unless otherwise noted. Typical values are at TJ = +25C. SHUTDOWN CURRENT vs INPUT VOLTAGE CURRENT LIMIT vs INPUT VOLTAGE 350 1600 1200 TJ = -40C TJ = +25C TJ = +85C TJ = +125C 340 Current Limit (mA) 1400 ISHDN (nA) VOUT = 0.9V (nom) TJ = -40C TJ = +25C TJ = +85C TJ = +125C 1000 800 600 330 320 310 300 290 400 280 200 IOUT = 0mA 270 0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 2.5 6.5 3.5 4.0 5.0 5.5 6.0 6.5 Figure 20. Figure 21. CURRENT LIMIT vs INPUT VOLTAGE TPS728185315 POWER-SUPPLY RIPPLE REJECTION vs FREQUENCY (VIN - VOUT = 0.85V) 90 VOUT = 3.6V (nom) TJ = -40C TJ = +25C TJ = +85C TJ = +125C 340 330 5mA VIN = 2.7V VOUT = 1.85V COUT = 1mF 80 70 PSRR (dB) 320 310 300 60 50 200mA 40 100mA 30 290 20 280 10 270 0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 10 100 1k VIN (V) 10k 100k 1M 10M Frequency (Hz) Figure 22. Figure 23. TPS728185315 POWER-SUPPLY RIPPLE REJECTION vs FREQUENCY (VIN - VOUT = 1.0V) TPS728185315 POWER-SUPPLY RIPPLE REJECTION vs FREQUENCY (VIN - VOUT = 0.5V) 90 90 5mA VIN = 2.85V VOUT = 1.85V COUT = 1mF 80 70 60 50 200mA 40 100mA 5mA 70 60 50 40 200mA 30 30 20 20 10 10 0 VIN = 3.65V VOUT = 3.15V COUT = 1mF 80 PSRR (dB) PSRR (dB) 4.5 VIN (V) 350 Current Limit (mA) 3.0 VIN (V) 100mA 0 10 100 1k 10k 100k Frequency (Hz) Figure 24. Copyright (c) 2007, Texas Instruments Incorporated 1M 10M 10 100 1k 10k 100k 1M 10M Frequency (Hz) Figure 25. Submit Documentation Feedback 9 TPS728xx Series www.ti.com SBVS095 - AUGUST 2007 TYPICAL CHARACTERISTICS (continued) Over operating temperature range (TJ = -40C to +125C), VIN = VOUT(TYP) + 0.5V or 2.7V, whichever is greater; IOUT = 0.5mA, VEN = VSET = VIN, COUT = 1.0F, unless otherwise noted. Typical values are at TJ = +25C. 90 VIN = 4.15V VOUT = 3.15V COUT = 1mF 5mA 80 PSRR (dB) 70 60 50 200mA 40 100mA 30 20 10 OUTPUT SPECTRAL NOISE DENSITY vs FREQUENCY Output spectal Noise Density (mV/OHz) TPS728185315 POWER-SUPPLY RIPPLE REJECTION vs FREQUENCY (VIN - VOUT = 1.0V) 10 1 0.1 Load IOUT = 185mA CIN = COUT = 1mF VOUT = 1.85V Noise = 141.6mVRMS 0.01 0 10 100 1k 10k 100k 1M 10M 10 100 1k Output spectal Noise Density (mV/OHz) 10k 100k Frequency (Hz) Frequency (Hz) Figure 26. Figure 27. OUTPUT SPECTRAL NOISE DENSITY vs FREQUENCY LINE TRANSIENT RESPONSE 10 VIN = 2.7V to 6.5V, Slew Rate = 1V/ms VOUT = 1.85V, IOUT = 200mA VOUT 10mV/div 1 VIN 0.1 Load IOUT = 200mA CIN = COUT = 1mF VOUT = 3.15V Noise = 217mVRMS 0.01 10 100 1k 10k Time (100ms/div) 100k Frequency (Hz) Figure 28. Figure 29. LINE TRANSIENT RESPONSE LOAD TRANSIENT RESPONSE VIN 10mV/div VOUT 10mV/div 200mA VOUT VIN = 3.8V to 6.5V, Slew Rate = 1V/ms VOUT = 3.3V, IOUT = 200mA Time (100ms/div) Figure 30. 10 Submit Documentation Feedback VIN = 2.7V VOUT = 1.85V IOUT = 5mA to 200mA tR = tF = 1ms IOUT 5mA Time (10ms/div) Figure 31. Copyright (c) 2007, Texas Instruments Incorporated TPS728xx Series www.ti.com SBVS095 - AUGUST 2007 TYPICAL CHARACTERISTICS (continued) Over operating temperature range (TJ = -40C to +125C), VIN = VOUT(TYP) + 0.5V or 2.7V, whichever is greater; IOUT = 0.5mA, VEN = VSET = VIN, COUT = 1.0F, unless otherwise noted. Typical values are at TJ = +25C. LOAD TRANSIENT RESPONSE ENABLE TRANSIENT RESPONSE VOUT 10mV/div EN VOUT 200mA VIN = 3.8V, VOUT = 3.3V, IOUT = 0mA Enable = 0.4V to 1V to 0.4V VIN = 3.8V VOUT = 3.3V IOUT = 5mA to 200mA tR = tF = 1ms IOUT 5mA 200mV/div 500mV/div Time (10ms/div) Time (100ms/div) Figure 32. Figure 33. VIN RAMP UP AND RAMP DOWN RESPONSE VSET PIN TOGGLE VOUT 1V/div 200mV/div VIN VSET VOUT Transition Time < 40ms (2% settling) VOUT VOUT Transitioning from 1.85V to 3.15V IOUT = 1mA Time (10ms/div) Time (2ms/div) Figure 34. Figure 35. VSET PIN TOGGLE VSET PIN TOGGLE VOUT Transitioning from 3.15V to 1.85V IOUT = 1mA VOUT VOUT 200mV/div 200mV/div VSET VOUT Transition Time < 40ms (2% settling) VOUT Transitioning from 1.85V to 3.15V IOUT = 10mA VSET Time (100ms/div) Time (40ms/div) Figure 36. Figure 37. Copyright (c) 2007, Texas Instruments Incorporated Submit Documentation Feedback 11 TPS728xx Series www.ti.com SBVS095 - AUGUST 2007 TYPICAL CHARACTERISTICS (continued) Over operating temperature range (TJ = -40C to +125C), VIN = VOUT(TYP) + 0.5V or 2.7V, whichever is greater; IOUT = 0.5mA, VEN = VSET = VIN, COUT = 1.0F, unless otherwise noted. Typical values are at TJ = +25C. VSET PIN TOGGLE VOUT Transitioning from 3.15V to 1.85V IOUT = 10mA 200mV/div VOUT VSET Time (20ms/div) Figure 38. 12 Submit Documentation Feedback Copyright (c) 2007, Texas Instruments Incorporated TPS728xx Series www.ti.com SBVS095 - AUGUST 2007 APPLICATION INFORMATION The TPS728xx series belongs to a family of new generation LDO regulators that use innovative circuitry to achieve ultra-wide bandwidth and high loop gain, resulting in extremely high PSRR (up to 1MHz) at very low headroom (VIN - VOUT). These features, combined with low noise, low ground pin current, and ultra-small packaging, make this device ideal for portable applications. This family of regulators offers sub-bandgap output voltages, current limit and thermal protection, and is fully specified from -40C to +125C. Figure 39 shows the basic circuit connections. 2.7V to 6.5V VIN 0.9V to 3.6V IN VOUT OUT 1m F 1m F TPS728xx On Off EN On (VOUT2) Off (VOUT1) Another area where the TPS728xx can be used effectively is in dynamic voltage scaling (DVS) applications. In DVS applications, it is required to dynamically switch between a high operational voltage to a low standby voltage in order to balance performance of processors and achieve power savings. Modern multimillion gate microprocessors fabricated with the latest sub-micron processes save on power by transitioning to a lower voltage to reduce leakage currents without losing content. This architecture enables the microprocessor to transition quickly into an operational state (wake up) without requiring reloading of the states from external memory, or a reboot. VSET GND Figure 39. Typical Application Circuit APPLICATION EXAMPLES EEPROM-based applications require the programming voltage to be higher than the operating voltage. The TPS728xx suits such applications where the maximum programming voltage of the EEPROM is higher than the operating voltage. The VSET logic pin allows the application to transition between the higher EEPROM programming voltage and the lower operating voltage. For example, the TPS728xx typically takes less than 40s to transition from a lower voltage of 1.85V to a higher voltage of 3.15V under an output load of 1mA to 10mA, as shown in Figure 35 and Figure 37, respectively. The special circuitry in the TPS728xx helps transition from the higher voltage to the lower voltage under no load. The load on the output at the end of the programming cycle is typically under 10mA. Output voltage overshoots and undershoots are minimal under this load condition. The TPS728xx typically takes less than 1ms of transition time going from 3.15V to 1.85V, as shown in Figure 36 and Figure 38, respectively. Both output states of the TPS728xx are programmable between 0.9V to 3.6V. Copyright (c) 2007, Texas Instruments Incorporated INPUT AND OUTPUT CAPACITOR REQUIREMENTS Although an input capacitor is not required for stability, it is good analog design practice to connect a 0.1F to 1.0F low equivalent series resistance (ESR) capacitor across the input supply near the regulator. This capacitor counteracts reactive input sources and improves transient response, noise rejection, and ripple rejection. A higher-value capacitor may be necessary if large, fast rise-time load transients are anticipated, or if the device is not located near the power source. If source impedance is not sufficiently low, a 0.1F input capacitor may be necessary to ensure stability. The TPS728xx is designed to be stable with standard ceramic capacitors with values of 1.0F or larger at the output. X5R- and X7R-type capacitors are best because they have minimal variation in value and ESR over temperature. Maximum ESR should be less than 1.0. BOARD LAYOUT RECOMMENDATIONS TO IMPROVE PSRR AND NOISE PERFORMANCE To improve ac performance such as PSRR, output noise, and transient response, it is recommended that the board be designed with separate ground planes for VIN and VOUT, with each ground plane connected only at the GND pin of the device. In addition, the ground connection for the output capacitor should connect directly to the GND pin of the device. High ESR capacitors may degrade PSRR. Submit Documentation Feedback 13 TPS728xx Series www.ti.com SBVS095 - AUGUST 2007 INTERNAL CURRENT LIMIT The TPS728xx internal current limits help protect the regulator during fault conditions. During current limit, the output sources a fixed amount of current that is largely independent of output voltage. For reliable operation, the device should not be operated in a current limit state for extended periods of time. The PMOS pass element in the TPS728xx has a built-in body diode that conducts current when the voltage at OUT exceeds the voltage at IN. This current is not limited, so if extended reverse voltage operation is anticipated, external limiting to 5% of rated output current may be appropriate. 2.7V to 6.5V 0.9V to 3.6V VIN IN VOUT OUT 1mF 1mF 2kW TPS728xx EN VSET2 VSET VSET1 GND Figure 40. Circuit Showing EN Tied High when Shutdown Capability is Not Required SHUTDOWN The enable pin (EN) is active high and is compatible with standard and low voltage, TTL-CMOS levels. When shutdown capability is not required, EN can be connected to the IN pin, as shown in Figure 40. Figure 41 shows when both EN and VSET are tied to IN. The TPS728xx, with internal active output pulldown circuitry, discharges the output to within 5% of VOUT with a time (t) of: t=3 60 RL 60 + RL 2.7V to 6.5V 0.9V to 3.6V VIN IN VOUT OUT 1mF 1mF 2kW TPS728xx EN VSET COUT Where: RL = output load resistance COUT = output capacitance GND Figure 41. Circuit to Tie Both EN and VSET High DROPOUT VOLTAGE UNDERVOLTAGE LOCK-OUT (UVLO) The TPS728xx uses a PMOS pass transistor to achieve low dropout. When (VIN - VOUT) is less than the dropout voltage (VDO), the PMOS pass device is in the linear region of operation and the input-to-output resistance is the RDS(ON) of the PMOS pass element. VDO approximately scales with output current because the PMOS device behaves like a resistor in dropout. The TPS728xx uses an undervoltage lock-out circuit to keep the output shut off until the internal circuitry is operating properly. The UVLO circuit has a deglitch feature so that it typically ignores undershoot transients on the input if they are less than 5s duration. The UVLO circuit triggers at approximately 2.3V on an undershooting or a falling input voltage. On the TPS728xx, the active pulldown discharges VOUT when the device is in UVLO off condition. However, the input voltage must be greater than 0.8V for the active pulldown to work. As with any linear regulator, PSRR and transient response are degraded as (VIN - VOUT) approaches dropout. This effect is shown in Figure 25 and Figure 26 in the Typical Characteristics section. TRANSIENT RESPONSE As with any regulator, increasing the size of the output capacitor reduces over/undershoot magnitude but increases duration of the transient response. 14 Submit Documentation Feedback MINIMUM LOAD The TPS728xx is stable with no output load. Traditional PMOS LDO regulators suffer from lower loop gain at very light output loads. The TPS728xx employs an innovative, low-current mode circuit under very light or no-load conditions, resulting in improved output voltage regulation performance down to zero output current. Copyright (c) 2007, Texas Instruments Incorporated TPS728xx Series www.ti.com SBVS095 - AUGUST 2007 THERMAL INFORMATION Thermal Protection Thermal protection disables the output when the junction temperature rises to approximately +160C, allowing the device to cool. When the junction temperature cools to approximately +140C the output circuitry is again enabled. Depending on power dissipation, thermal resistance, and ambient temperature, the thermal protection circuit may cycle on and off. This cycling limits the dissipation of the regulator, protecting it from damage as a result of overheating. Any tendency to activate the thermal protection circuit indicates excessive power dissipation or an inadequate heatsink. For reliable operation, junction temperature should be limited to +125C maximum. To estimate the margin of safety in a complete design (including heatsink), increase the ambient temperature until the thermal protection is triggered; use worst-case loads and signal conditions. For good reliability, thermal protection should trigger at least +35C above the maximum expected ambient condition of your particular application. This configuration produces a worst-case junction temperature of +125C at the highest expected ambient temperature and worst-case load. The internal protection circuitry of the TPS728xx has been designed to protect against overload conditions. It was not intended to replace proper heatsinking. Continuously running the TPS728xx into thermal shutdown degrades device reliability. Power Dissipation The ability to remove heat from the die is different for each package type, presenting different considerations in the printed circuit board (PCB) layout. The PCB area around the device that is free of other components moves the heat from the device to the ambient air. Performance data for JEDEC lowand high-K boards are given in the Dissipation Ratings table. Using heavier copper increases the effectiveness in removing heat from the device. The addition of plated through-holes to heat-dissipating layers also improves the heatsink effectiveness. Power dissipation depends on input voltage and load conditions. Power dissipation (PD) is equal to the product of the output current times the voltage drop across the output pass element (VIN to VOUT), as shown in Equation 1: PD = (VIN - VOUT) IOUT (1) Package Mounting Solder pad footprint recommendations for the TPS728xx are available from the Texas Instruments web site at www.ti.com. 1,025 0,975 1,395 1,345 NOTES: 1. All linear dimensions are in millimeters. 2. This drawing is subject to change without notice. Figure 42. YZU Wafer Chip-Scale Package Dimensions (in mm) Copyright (c) 2007, Texas Instruments Incorporated Submit Documentation Feedback 15 PACKAGE OPTION ADDENDUM www.ti.com 15-May-2018 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (C) Device Marking (4/5) TPS728120150DRVR ACTIVE WSON DRV 6 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 DAO TPS728120150DRVT ACTIVE WSON DRV 6 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 DAO TPS728175295YZUR ACTIVE DSBGA YZU 5 3000 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 125 AU TPS728175295YZUT ACTIVE DSBGA YZU 5 250 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 125 AU TPS728180285YZUR ACTIVE DSBGA YZU 5 3000 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 125 DT TPS728180285YZUT ACTIVE DSBGA YZU 5 250 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 125 DT TPS728180300YZUR ACTIVE DSBGA YZU 5 3000 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 125 VL TPS728180300YZUT ACTIVE DSBGA YZU 5 250 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 125 VL TPS728185295YZUR ACTIVE DSBGA YZU 5 3000 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 125 VM TPS728185295YZUT ACTIVE DSBGA YZU 5 250 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 125 VM TPS728185315DRVT ACTIVE WSON DRV 6 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 BYW TPS728185315YZUR ACTIVE DSBGA YZU 5 3000 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 125 FN TPS728185315YZUT ACTIVE DSBGA YZU 5 250 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 125 FN TPS728285180YZUR ACTIVE DSBGA YZU 5 3000 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 125 TL TPS728285180YZUT ACTIVE DSBGA YZU 5 250 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 125 TL TPS728330180YZUR ACTIVE DSBGA YZU 5 3000 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 125 DJ TPS728330180YZUT ACTIVE DSBGA YZU 5 250 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 125 DJ Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com Orderable Device 15-May-2018 Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (C) Device Marking (4/5) TPS728330185DRVR ACTIVE WSON DRV 6 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 SBD TPS728330185DRVT ACTIVE WSON DRV 6 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 SBD (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. 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Addendum-Page 2 Samples PACKAGE MATERIALS INFORMATION www.ti.com 22-May-2018 TAPE AND REEL INFORMATION *All dimensions are nominal Device TPS728120150DRVR Package Package Pins Type Drawing WSON DRV 6 TPS728120150DRVT WSON DRV TPS728175295YZUR DSBGA YZU TPS728175295YZUT DSBGA TPS728180285YZUR SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 2.2 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 2.2 1.2 4.0 8.0 Q2 3000 179.0 8.4 6 250 179.0 8.4 2.2 2.2 1.2 4.0 8.0 Q2 5 3000 180.0 8.4 1.07 1.42 0.74 4.0 8.0 Q1 YZU 5 250 180.0 8.4 1.07 1.42 0.74 4.0 8.0 Q1 DSBGA YZU 5 3000 180.0 8.4 1.07 1.42 0.74 4.0 8.0 Q1 TPS728180285YZUT DSBGA YZU 5 250 180.0 8.4 1.07 1.42 0.74 4.0 8.0 Q1 TPS728180300YZUR DSBGA YZU 5 3000 180.0 8.4 1.07 1.42 0.74 4.0 8.0 Q1 TPS728180300YZUT DSBGA YZU 5 250 180.0 8.4 1.07 1.42 0.74 4.0 8.0 Q1 TPS728185295YZUR DSBGA YZU 5 3000 180.0 8.4 1.07 1.42 0.74 4.0 8.0 Q1 TPS728185295YZUT DSBGA YZU 5 250 180.0 8.4 1.07 1.42 0.74 4.0 8.0 Q1 TPS728185315DRVT WSON DRV 6 250 179.0 8.4 2.2 2.2 1.2 4.0 8.0 Q2 TPS728185315YZUR DSBGA YZU 5 3000 180.0 8.4 1.07 1.42 0.74 4.0 8.0 Q1 TPS728185315YZUT DSBGA YZU 5 250 180.0 8.4 1.07 1.42 0.74 4.0 8.0 Q1 TPS728285180YZUR DSBGA YZU 5 3000 180.0 8.4 1.07 1.42 0.74 4.0 8.0 Q1 TPS728285180YZUT DSBGA YZU 5 250 180.0 8.4 1.07 1.42 0.74 4.0 8.0 Q1 TPS728330180YZUR DSBGA YZU 5 3000 180.0 8.4 1.07 1.42 0.74 4.0 8.0 Q1 TPS728330180YZUT DSBGA YZU 5 250 180.0 8.4 1.07 1.42 0.74 4.0 8.0 Q1 TPS728330185DRVR WSON DRV 6 3000 179.0 8.4 2.2 2.2 1.2 4.0 8.0 Q2 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 22-May-2018 Device TPS728330185DRVT Package Package Pins Type Drawing WSON DRV 6 SPQ 250 Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 179.0 8.4 2.2 B0 (mm) K0 (mm) P1 (mm) 2.2 1.2 4.0 W Pin1 (mm) Quadrant 8.0 Q2 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS728120150DRVR WSON DRV 6 3000 203.0 203.0 35.0 TPS728120150DRVT WSON DRV 6 250 203.0 203.0 35.0 TPS728175295YZUR DSBGA YZU 5 3000 182.0 182.0 20.0 TPS728175295YZUT DSBGA YZU 5 250 182.0 182.0 20.0 TPS728180285YZUR DSBGA YZU 5 3000 182.0 182.0 20.0 TPS728180285YZUT DSBGA YZU 5 250 182.0 182.0 20.0 TPS728180300YZUR DSBGA YZU 5 3000 182.0 182.0 20.0 TPS728180300YZUT DSBGA YZU 5 250 182.0 182.0 20.0 TPS728185295YZUR DSBGA YZU 5 3000 182.0 182.0 20.0 TPS728185295YZUT DSBGA YZU 5 250 182.0 182.0 20.0 TPS728185315DRVT WSON DRV 6 250 203.0 203.0 35.0 TPS728185315YZUR DSBGA YZU 5 3000 182.0 182.0 20.0 TPS728185315YZUT DSBGA YZU 5 250 182.0 182.0 20.0 TPS728285180YZUR DSBGA YZU 5 3000 210.0 185.0 35.0 TPS728285180YZUT DSBGA YZU 5 250 210.0 185.0 35.0 TPS728330180YZUR DSBGA YZU 5 3000 182.0 182.0 20.0 Pack Materials-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 22-May-2018 Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS728330180YZUT DSBGA YZU 5 250 182.0 182.0 20.0 TPS728330185DRVR WSON DRV 6 3000 203.0 203.0 35.0 TPS728330185DRVT WSON DRV 6 250 203.0 203.0 35.0 Pack Materials-Page 3 PACKAGE OUTLINE YZU0005 DSBGA - 0.625 mm max height SCALE 10.000 DIE SIZE BALL GRID ARRAY B A E BALL A1 CORNER D 0.625 MAX C SEATING PLANE 0.3 0.2 0.05 C BALL TYP SYMM C 0.5 TYP SYMM B D: Max = 1.358 mm, Min =1.297 mm E: Max = 0.99 mm, Min = 0.93 mm 0.433 A 0.35 0.25 C A B 5X 0.015 1 2 3 0.5 TYP 4222196/A 11/2015 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. www.ti.com EXAMPLE BOARD LAYOUT YZU0005 DSBGA - 0.625 mm max height DIE SIZE BALL GRID ARRAY (0.5) TYP 5X ( 0.25) 1 2 3 A (0.433) TYP SYMM B C SYMM LAND PATTERN EXAMPLE SCALE:50X 0.05 MAX ( 0.25) METAL METAL UNDER SOLDER MASK 0.05 MIN ( 0.25) SOLDER MASK OPENING SOLDER MASK OPENING NON-SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DEFINED SOLDER MASK DETAILS NOT TO SCALE 4222196/A 11/2015 NOTES: (continued) 3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints. Refer to Texas Instruments Literature No. SNVA009 (www.ti.com/lit/snva009). www.ti.com EXAMPLE STENCIL DESIGN YZU0005 DSBGA - 0.625 mm max height DIE SIZE BALL GRID ARRAY (0.5) TYP 5X ( 0.25) (R0.05) TYP 1 2 3 A (0.433) TYP SYMM B METAL TYP C SYMM SOLDER PASTE EXAMPLE BASED ON 0.1 mm THICK STENCIL SCALE:50X 4222196/A 11/2015 NOTES: (continued) 4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. www.ti.com GENERIC PACKAGE VIEW DRV 6 WSON - 0.8 mm max height PLASTIC SMALL OUTLINE - NO LEAD Images above are just a representation of the package family, actual package may vary. Refer to the product data sheet for package details. 4206925/F PACKAGE OUTLINE DRV0006A WSON - 0.8 mm max height SCALE 5.500 PLASTIC SMALL OUTLINE - NO LEAD 2.1 1.9 B A PIN 1 INDEX AREA 2.1 1.9 0.8 0.7 C SEATING PLANE 0.08 C (0.2) TYP 0.05 0.00 1 0.1 EXPOSED THERMAL PAD 3 2X 1.3 4 7 1.6 0.1 6 1 4X 0.65 PIN 1 ID (OPTIONAL) 6X 6X 0.3 0.2 0.35 0.25 0.1 0.05 C A C B 4222173/B 04/2018 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance. www.ti.com EXAMPLE BOARD LAYOUT DRV0006A WSON - 0.8 mm max height PLASTIC SMALL OUTLINE - NO LEAD 6X (0.45) (1) 1 7 6 6X (0.3) (1.6) SYMM (1.1) 4X (0.65) 4 3 SYMM (R0.05) TYP ( 0.2) VIA TYP (1.95) LAND PATTERN EXAMPLE SCALE:25X 0.07 MIN ALL AROUND 0.07 MAX ALL AROUND SOLDER MASK OPENING METAL METAL UNDER SOLDER MASK NON SOLDER MASK DEFINED (PREFERRED) SOLDER MASK OPENING SOLDER MASK DEFINED SOLDER MASK DETAILS 4222173/B 04/2018 NOTES: (continued) 4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271). 5. Vias are optional depending on application, refer to device data sheet. If some or all are implemented, recommended via locations are shown. www.ti.com EXAMPLE STENCIL DESIGN DRV0006A WSON - 0.8 mm max height PLASTIC SMALL OUTLINE - NO LEAD 6X (0.45) 1 SYMM METAL 7 6 6X (0.3) (0.45) SYMM 4X (0.65) (0.7) 4 3 (R0.05) TYP (1) (1.95) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL EXPOSED PAD #7 88% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE SCALE:30X 4222173/B 04/2018 NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. www.ti.com IMPORTANT NOTICE Texas Instruments Incorporated (TI) reserves the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright (c) 2018, Texas Instruments Incorporated Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: Texas Instruments: TPS728180300YZUR TPS728180300YZUT TPS728285180YZUR TPS728285180YZUT TPS728185295YZUR TPS728185295YZUT TPS728185315DRVR TPS728185315DRVT TPS728185315DRVRG4 TPS728185315YZUR TPS728185315YZUT TPS728330185DRVR TPS728330185DRVT TPS728330180YZUT TPS728180285YZUR TPS728180285YZUT TPS728330180YZUR