74ACT244SCX_NL - Fairchild Semiconductor

November 1988

Revised March 2005

74AC244 • 74ACT244 Octal Buffer/Line Driver with 3-STATE Outputs

74AC244 • 74ACT244

Octal Buffer/Line Driver with 3-STATE Outputs

General Descript ion

The AC/A CT244 i s an octal bu ffer and lin e driver de sign ed

to be employed as a memory address driver, clock driver

and bus-oriented transmitter/receiver which provides

improved PC board density.

Features

■ICC and IOZ reduced by 50%

■3-STATE outputs drive bus lines or buffer memory

address registers

■Outputs source/sink 24 mA

■ACT244 has TTL-compatible inputs

Ordering Code:

Device a l s o av ailable in Tape and Reel. Specify by ap pending su ffix le t te r “X” to the ordering co de.

Pb-Free package per JEDEC J-STD-020B.

Note 1: “_NL” indicat es Pb-Fre e pac k age (per JE D EC J -STD-020B). Please us e order number as i ndicated .

FACT

is a trademark of Fairchild Semiconductor Corporation.

Order Number Package Package Description

Number

74AC244SC M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide

74AC244SCX_NL

(Note 1) M20B Pb-Free 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide

74AC244SJ M20D Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

74AC244MTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide

74AC244MTCX_NL

(Note 1) MTC20 Pb-Free 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm

Wide

74AC244PC N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide

74ACT244SC M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide

74ACT244SCX_NL

(Note 1) M20B Pb-Free 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide

74ACT244SJ M20D Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

74ACT244MSA MSA20 20-Lead Shrink Small Outlin e Package (SSOP), JEDEC MO-150, 5.3mm Wide

74ACT244MTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide

74ACT244MTCX_NL

(Note 1) MTC20 Pb-Free 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm

Wide

74ACT244PC N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide

www.fairchildsemi.com 2

74AC244 • 74ACT244

Logic Symbol

IEEE/IEC

Connection Diagram

Pin Descriptions

Truth Tables

Immaterial

High Impedance

Pin Names Description

OE1, OE23-STATE Output Enable Inputs

I0–I7Inputs

O0–O7Outputs

Inputs Outputs

OE1In(Pins 12, 14, 16, 18)

LL L

LH H

HX Z

Inputs Outputs

OE2In(Pins 3, 5, 7, 9)

LL L

LH H

HX Z

3 www.fairchildsemi.com

74AC244 • 74ACT244

Absolute Maximum Ratings(Note 2) Recommended Operating

Conditions

Note 2: Absol ut e ma x i mu m rat ings are thos e v alue s beyond wh ich damag e

to the dev ice may occur. The databook specifi cations should be met, with-

out exception, to ensure that the system design is reliable over its power

supply, temperature, and output/input loading variables. Fairchild does not

recommend operation of FACT

circuits outside databook spec if ic at ions.

DC Electrical Characteristics for AC

Note 3: All outputs loaded; thresholds on input associated with output under test.

Note 4: Maximum test duration 2.0 ms, one output loaded at a time.

Note 5: IIN and ICC @ 3.0V are gu aranteed to be less t han or equa l t o th e respectiv e limit @ 5. 5V VCC.

Supply Voltage (VCC)



0.5V to



7.0V

DC Input Diode Current (IIK)



0.5V



20 mA

VCC



0.5V



20 mA

DC Input Voltage (VI)



0.5V to VCC



0.5V

DC Output Diode Current (IOK)



0.5V



20 mA

VCC



0.5V



20 mA

DC O utput Voltage (VO)



0.5V to VCC



0.5V

DC Output Source

or Sink Current (IO)

50 mA

DC VCC or Ground Current

per Output Pin (ICC or IGND)

50 mA

Storage Temperature (TSTG)



C to



150

Junction Temperature (TJ)

PDIP 140

Supply Voltage (VCC)

AC 2.0V to 6.0V

ACT 4.5V to 5.5V

Input Voltage (VI)0V to V

Output Voltage (VO)0V to V

Operating Temperature (TA)



C to



Minimum Input Edge Rate (

AC Devices

VIN from 30% to 70% of VCC

VCC @ 3.3V, 4.5V, 5.5 V 125 mV/ns

Minimum Input Edge Rate (

ACT Devices

VIN from 0.8V to 2.0V

VCC @ 4.5V, 5.5V 125 mV/ns

Symbol Parameter VCC TA





Cto



125



Cto



CUnits Conditions

(V) Typ Guaranteed Limits

VIH Minimum HIGH Level 3.0 1.5 2.1 2.1 2.1 VOUT

0.1V

Input Voltage 4.5 2.25 3.15 3.15 3.15 V or VCC



0.1V

5.5 2.75 3.85 3.85 3.85

VIL Maximum LOW Level 3.0 1.5 0.9 0.9 0.9 VOUT

0.1V

Input Voltage 4.5 2.25 1.35 1.35 1.35 V or VCC



0.1V

5.5 2.75 1.65 1.65 1.65

VOH Minimum HIGH Level 3.0 2.99 2.9 2.9 2.9

Output Voltage 4.5 4.49 4.4 4.4 4.4 V IOUT



5.5 5.49 5.4 5.4 5.4

3.0 2.56 2.4 2.46 IOH

12 mA

4.5 3.86 3.7 3.76 V IOH

24 mA

5.5 4.86 4.7 4.76 IOH

24 mA (Note 3)

VOL Maximum LOW Level 3.0 0.002 0.1 0.1 0.1

Output Voltage 4.5 0.001 0.1 0.1 0.1 V IOUT

5.5 0.001 0.1 0.1 0.1

3.0 0.36 0.50 0.44 IOL

12 mA

4.5 0.36 0.50 0.44 V IOL

24 mA

5.5 0.36 0.50 0.44 IOL

24 mA (Note 3)

IIN Maxim um In put 5.5

0.1

1.0

VCC, GND

(Note 5) Leakage Current

IOZ Maximum VI (OE)

VIL, VIH

3-STATE 5.5

0.25

5.0

2.5

VCC, VGND

Current VO

VCC, GND

IOLD Mi nimum Dynam ic 5.5 50 75 mA VOLD

1.65V Max

IOHD Output Current (Note 4) 5.5



75 mA VOHD

3.85V Min

ICC Maximum Quiescent 5.5 4.0 80.0 40.0

VCC

(Note 5) Supply Current or GND

www.fairchildsemi.com 4

74AC244 • 74ACT244

DC Electrical Characteristics for ACT

Note 6: All outputs loaded; thresholds on input associated with output under test.

Note 7: Maximum test du ration 2.0 m s, one output loaded at a time.

Symbol Parameter VCC TA





Cto



125



Cto



CUnits Conditions

(V) Typ Guaranteed Limits

VIH Minimum HIGH Level 4.5 1.5 2.0 2.0 2.0 VVOUT

0.1V

Input Voltage 5.5 1.5 2.0 2.0 2.0 or VCC



0.1V

VIL Maximum LOW Level 4.5 1.5 0.8 0.8 0.8 VVOUT

0.1V

Input Voltage 5.5 1.5 0.8 0.8 0.8 or VCC



0.1V

VOH Minimum HIGH Level 4.5 4.49 4.4 4.4 4.4 VIOUT



Output Voltage 5.5 5.49 5.4 5.4 5.4 IOH

4.5 3.86 3.70 3.76 V IOH

24 m A

5.5 4.86 4.70 4.76 IOH

24 mA (Note 6)

VOL Maximum LOW Level 4.5 0.001 0.1 0.1 0.1 VIOUT

Output Voltage 5.5 0.001 0.1 0.1 0.1 IOL

12 mA

4.5 0.36 0.50 0.44 V IOL

24 mA

5.5 0.36 0.50 0.44 IOL

24 mA (Note 6)

IIN Maximum Input 5.5

0.1

1.0

VCC, GND

Leakage Current

IOZ Maximum 3-STATE 5.5

0.25

5.0

2.5

VIL, VIH

Current VO

VCC, GND

ICCT Maximum 5.5 0.6 1.6 1.5 mA VI

VCC



2.1V

ICC/Input

IOLD Minimum Dynamic 5.5 50 75 mA VOLD

1.65V Max

IOHD Output Current (Note 7) 5.5



75 mA VOHD

3.85V Min

ICC Maximum Quiescent 5.5 4.0 80.0 40.0

VCC

Supply Curre nt or GND

5 www.fairchildsemi.com

74AC244 • 74ACT244

AC Electrical Characteristics for AC

Note 8: Voltage Rang e 3. 3 is 3. 3V

0.3V

Voltage Range 5. 0 is 5. 0V

0.5V

AC Electrical Characteristics for ACT

Note 9: Voltage Rang e 5. 0 is 5. 0V

0.5V

Capacitance

Symbol Parameter

VCC TA





C to



125

C TA



C to



Units

(V) CL

50 pF CL

50 pF

(Note 8) Min Typ Max Min Max Min Max

tPLH Propagation Delay 3.3 2.0 6.5 9.0 1.0 12.5 1.5 10.0 ns

Data to Output 5.0 1.5 5.0 7.0 1.0 9.5 1.0 7.5

tPHL Propagation Delay 3.3 2.0 6.5 9.0 1.0 12.0 2.0 10.0 ns

Data to Output 5.0 1.5 5.0 7.0 1.0 9.0 1.0 7.5

tPZH Output Enable Time 3.3 2.0 6.0 10.5 1.0 11.5 1.5 11.0 ns

5.0 1.5 5.0 7.0 1.0 9.0 1.5 8.0

tPZL Output Enable Time 3.3 2.5 7.5 10.0 1.0 13.0 2.0 11.0 ns

5.0 1.5 5.5 8.0 1.0 10.5 1.5 8.5

tPHZ Output Disable Time 3.3 3.0 7.0 10.0 1.0 12.5 1.5 10.5 ns

5.0 2.5 6.5 9.0 1.0 10.5 1.0 9.5

tPLZ Output Disable Time 3.3 2.5 7.5 10.5 1.0 13.0 2.5 11.5 ns

5.0 2.0 6.5 9.0 1.0 11.0 2.0 9.5

Symbol Parameter

VCC TA





C to



125

C TA



C to



Units

(V) CL

50 pF CL

50 pF

(Note 9) Min Typ Max Min Max Min Max

tPLH Propagation Delay 5.0 2.0 6.5 9.0 1.0 10.0 1.5 10.0 ns

Data to Output

tPHL Propagation Delay 5.0 2.0 7.0 9.0 1.0 10.0 1.5 10.0 ns

Data to Output

tPZH Output Enable Time 5.0 1.5 6.0 8.5 1.0 9.5 1.0 9.5 ns

tPZL Output Enable Time 5.0 2.0 7.0 9.5 1.0 11.0 1.5 10.5 ns

tPHZ Output Disable Time 5.0 2.0 7.0 9.5 1.0 11.0 1.5 10.5 ns

tPLZ Output Disable Time 5.0 2.5 7.5 10.0 1.0 11.5 2.0 10.5 ns

Symbol Parameter Typ Units Conditions

CIN Input Capacitance 4.5 pF VCC

OPEN

CPD Power Dissipation Capacitance 45.0 pF VCC

5.0V

www.fairchildsemi.com 6

74AC244 • 74ACT244

Physical Dimensions inches (millimeters) unless otherwise noted

20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide

Package Number M20B

7 www.fairchildsemi.com

74AC244 • 74ACT244

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

Package Number M20D

www.fairchildsemi.com 8

74AC244 • 74ACT244

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

20-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm Wide

Packag e Num b er MSA2 0

9 www.fairchildsemi.com

74AC244 • 74ACT244

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

20-Lea d Th in S hri nk Sm all Ou tlin e Pack age (TSSOP ), JED EC MO-1 53, 4.4mm Wide

Package Number MTC20

www.fairchildsemi.com 10

74AC244 • 74ACT244 Octal Buffer/Line Driver with 3-STATE Outputs

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide

Package Number N20A

Fairchild does no t assume any responsibility for use of any circui try described, no circuit patent licenses are implied and

Fairchild reserves the right at any time without notice to change said circuitry and specifications.

LIFE SUPPORT POLICY

FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT

DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD

SEMICONDUCTOR CORPORATION. As used herein:

1. Life suppor t de vices o r systems a re devices or syste ms

which, (a) are intended for surgical implant into the

body, or (b) support or sustain life, and (c) whose failure

to perform when properly used in accordance with

instructions for use provided in the labeling, can be rea-

sonably expected to result in a significant injury to the

user.

2. A critical compon ent in any componen t of a life support

device or system whose failure to perform can be rea-

sonabl y ex pect ed to cause the fa ilu re of the li fe su pp ort

device or system, or to affect its safety or effectiveness.