64-
Position
OTP Digital Potentiometer
AD5171
FEATURES
64 positions
OTP (one-time programmable)1 set-and-forget resistance
setting—low cost alternative over EEMEM
Unlimited adjustments prior to OTP activation
5 kΩ, 10 kΩ, 50 kΩ, 100 kΩ end-to-end resistance
Low tempco 5 ppm/oC in potentiometer mode
Rev. PrC
Low tempco 35 ppm/°C in rheostat mode
Compact standard SOT-23-8 package
Low power, IDD = 8 µA max
Fast settling time, ts = 5 µs typ in power-up
I2C compatible digital interface
Computer software replaces µc in factory programming
applications
Full read/write of wiper register
Extra I2C device address pin
Power-on preset to midscale
6 V one-time programming voltage
Low operating voltage, 2.7 V to 5.5 V
OTP validation check function
Automotive temperature range −40°C to +125°C
APPLICATIONS
Systems calibrations
Electronics level settings
Mechanical potentiometers and trimmers® replacements
Automotive electronics adjustments
Gain control and offset adjustments
Transducer circuits adjustments
Programmable filters up to 1.5 MHz BW
GENERAL DESCRIPTION
The AD5171 is a 64-position, one-time programmable (OTP)
digital potentiometer2, which employs fuse link technology to
achieve the memory retention of resistance setting function.
OTP is a cost-effective alternative over the EEMEM approach
for users who do not need to reprogram new memory setting in
the digital potentiometer. This device performs the same
electronic adjustment function like most mechanical trimmers
and variable resistors do. The AD5171 is programmed using a
2-wire I2C compatible digital control. It allows unlimited
adjustments before permanently setting the resistance value.
During the OTP activation, a permanent fuse blown command
is sent after the final value is determined; therefore freezing the
wiper position at a given setting (analogous to placing epoxy on
a mechanical trimmer). When this permanent setting is
achieved, the value will not change regardless of supply
variations or environmental stresses under normal operating
conditions. To verify the success of permanent programming,
Analog Devices patterned the OTP validation such that the fuse
status can be discerned from two validation bits in read mode.
For applications that program AD5171 in the factories, Analog
Devices offers a device programming software, which operates
across Windows® 95 to XP® platforms including Windows NT®.
This software application effectively replaces the need for
external I2C controllers or host processors and therefore
significantly reduces users’ development time.
An AD5171 evaluation kit is available, which includes the
software, connector, and cable that can be converted for the
factory programming applications.
The AD5171 is available in a compact SOT-23-8 package. All
parts are guaranteed to operate over the automotive
temperature range of −40°C to +125°C. Besides its unique OTP
feature, the AD5171 lends itself well to other general-purpose
digital potentiometer applications due to its temperature
performance, small form factor, and low cost.
GND
I
2
C INTERFACE
AND
CONTROL LOGIC
A
W
B
WIPER
REGISTER
FUSE
LINK
V
DD
AD0
SDA
SCL
AD5171
03437-0-001
Figure 1. Functional Block Diagram
TOP VIEW
(Not to Scale)
8
7
6
5
1
2
3
4
W
V
DD
GND
SCL
A
B
AD0
SDA
AD5171
03437-0-002
Figure 2. Pin Configuration
1One-time programmable (OTP) - Unlimited adjustments before permanent
setting.
2The terms digital potentiometer and RDAC are used interchangeably.
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.326.8703 © 2003 Analog Devices, Inc. All rights reserved.
Preliminary Technical Data
AD5171
TABLE OF CONTENTS
AD5171—Electrical Characteristics .............................................. 3
Absolute Maximum Ratings............................................................ 5
ESD Caution.................................................................................. 5
Pin Configuration and Functional Descriptions.......................... 6
Typical Performance Characteristics ............................................. 7
Theory of Operation ...................................................................... 11
One-Time Programming (OTP) .............................................. 11
Determining the Variable Resistance and Voltage ................. 11
Rheostat Mode Operation..................................................... 11
Potentiometer Mode Operation........................................... 12
ESD Protection ........................................................................... 12
Terminal Voltage Operating Range.......................................... 13
Power-Up/Power-Down Sequences......................................... 13
Power Supply Considerations................................................... 13
Controlling the AD5171 ............................................................ 14
Software Programming ......................................................... 14
I2C Controller Programming................................................ 15
Controlling Two Devices on One Bus..................................... 16
Applications..................................................................................... 17
Programmable Voltage Reference (DAC) ............................... 17
Gain Control Compensation .................................................... 17
Programmable Voltage Source with Boosted Output............ 17
Level Shifting for Different Voltage Operation ...................... 17
Resistance Scaling ...................................................................... 17
Resolution Enhancement .......................................................... 18
RDAC Circuit Simulation Model............................................. 18
AD5171 Evaluation Board ........................................................ 19
Outline Dimensions....................................................................... 20
Ordering Guide .......................................................................... 20
REVISION HISTORY
Revision 0: Initial Version
Rev. PrC | Page 2 of 20
Preliminary Technical Data
AD5171
ELECTRICAL CHARACTERISTICS
Table 1. 5 kΩ, 10 kΩ, 50 kΩ, and 100 kΩ versions, VDD = 3 V to 5 V ± 10%, VA = VDD, VB = 0 V, −40°C < TA < +125°C,
unless otherwise noted.
Parameter Symbol Conditions Min Typ1 Max Unit
DC CHARACTERISTICS RHEOSTAT MODE
Resistor Differential Nonlinearity2 R-DNL
RWB, VA = No Connect,
RAB = 10 kΩ, 50 kΩ, and 100
kΩ
–0.5 ±0.2 +0.5 LSB
RWB, VA = No Connect, RAB = 5
kΩ
–1 ±0.25 +1 LSB
Resistor Integral Nonlinearity2 R-INL
RWB, VA = No Connect,
RAB = 10 kΩ, 50 kΩ, and 100 kΩ
–1 ±0.25 +1 LSB
RWB, VA = No Connect, RAB = 5
kΩ
–1.5 ±0.5 +1.5 LSB
Nominal Resistor Tolerance3 ∆RAB/RAB –30 +30 %
Resistance Temperature Coefficient (∆RAB/RAB)/∆T 35 ppm/°C
Wiper Resistance RW V
DD = 5 V 60 115 Ω
DC CHARACTERISTICS POTENTIOMETER DIVIDER
MODE (Specifications apply to all RDACs)
Resolution N 6 Bits
Differential Nonlinearity4 DNL –0.5 ±0.1 +0.5 LSB
Integral Nonlinearity4 INL –1 ±0.2 +1 LSB
Voltage Divider Temperature Coefficient (∆VW/VW)/∆T Code = 0x20 5 ppm/°C
Full-Scale Error VWFSE Code = 0x3F –1.5 -0.5 +0 LSB
Zero-Scale Error VWZSE Code = 0x00, RAB=10 kΩ,
50 kΩ, and 100 kΩ
0 0.5 1.5 LSB
Code = 0x00, RAB = 5 kΩ 0 2 LSB
RESISTOR TERMINALS
Voltage Range5 V
A, B, W With respect to GND VDD V
Capacitance6 A, B CA, B f = 1 MHz, measured to GND,
Code = 0x20
25 pF
Capacitance6 W CW f = 1 MHz, measured to GND,
Code = 0x20
55 pF
Common-Mode Leakage ICM V
A = VB = VDD/2 1 nA
DIGITAL INPUTS
Input Logic High (SDA and SCL) VIH 0.7 VDD V
DD+0.5 V
Input Logic Low (SDA and SCL) VIL –0.5 0.3VDD V
Input Logic High (AD0) VIH V
DD = 3 V 3.0 VDD V
Input Logic Low (AD0) VIL V
DD = 3 V 0 1.0 V
Input Current IIL V
IN = 0 V or 5 V ±1 µA
Input Capacitance6 C
IL 3 pF
DIGITAL OUTPUTS
Output Logic Low (SDA) VOL I
OL = 6 mA 0.4 V
Three-State Leakage Current (SDA) IOZ V
IN = 0 V or 5 V ±1 µA
Output Capacitance6 C
OZ 3 pF
POWER SUPPLIES
Power Supply Range VDD 2.7 5.5 V
OTP Power Supply7 V
DD_OTP TA = 25°C 6 6.5 V
Supply Current IDD V
IH = 5 V or VIL = 0 V 4 8 µA
OTP Supply Current8 IDD_OTP V
DD_OTP = 6 V, TA = 25°C 100 mA
Power Dissipation9 P
DISS V
IH = 5 V or VIL = 0 V, VDD = 5 V 0.02 0.04 mW
Power Supply Sensitivity PSSR −0.025 +0.001 +0.025 %/%
Rev. PrC | Page 3 of 20
Preliminary Technical Data
AD5171
Parameter Symbol Conditions Min Typ1 Max Unit
DYNAMIC CHARACTERISTICS 6, 10, 11
Bandwidth –3 dB BW_5k RAB = 5 kΩ, Code = 0x20 1500 kHz
BW_10k RAB = 10 kΩ, Code = 0x20 600 kHz
BW_50k RAB = 50 kΩ, Code = 0x20 110 kHz
BW_100k RAB = 100 kΩ, Code = 0x20 60 kHz
Total Harmonic Distortion THD VA =1 V rms, RAB = 10 kΩ,
VB = 0 V DC, f = 1 kHz
0.05 %
Adjustment Settling Time tS1 VA= 5 V ± 1 LSB error band,
VB = 0, measured at VW
5 µs
OTP Settling Time12 t
S_OTP VA = 5 V ± 1 LSB error band,
VB = 0, measured at VW
400 ms
Power-up Settling Time—Post Fuses Blown tS2 VA = 5 V ±1 LSB error band,
VB = 0, measured at VW
5 µs
Resistor Noise Voltage eN_WB RAB = 5 kΩ, f = 1 kHz,
Code = 0x20
8 nV/√Hz
RAB = 10 kΩ, f = 1 kHz,
Code = 0x20
12 nV/√Hz
INTERFACE TIMING CHARACTERISTICS
(Applies to all parts6,12)
SCL Clock Frequency fSCL 400 kHz
tBUF Bus Free Time between Start and Stop t1 1.3 µs
tHD;STA Hold Time (Repeated Start) t2 After this period, the first
clock pulse is generated
0.6 µs
tLOW Low Period of SCL Clock t3 1.3 µs
tHIGH High Period of SCL Clock t4 0.6 50 µs
tSU;STA Setup Time for Start Condition t5 0.6 µs
tHD;DAT Data Hold Time t6 0.9 µs
tSU;DAT Data Setup Time t7 0.1 µs
tF Fall Time of Both SDA and SCL Signals t8 0.3 µs
tR Rise Time of Both SDA and SCL signals t9 0.3 µs
tSU;STO Setup Time for Stop Condition t10 0.6 µs
1Typicals represent average readings at 25°C and VDD = 5 V.
2Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions.
R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic.
3VAB = VDD, Wiper (VW) = No connect.
4INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output DAC. VA = VDD and VB = 0 V. DNL specification limits of
±1 LSB maximum are guaranteed monotonic operating conditions.
5Resistor terminals A, B, W have no limitations on polarity with respect to each other.
6Guaranteed by design and not subject to production test.
7Different from operating power supply, power supply for OTP is used one-time only.
8Different from operating current, supply current for OTP lasts approximately 400 ms for one-time needed only.
9PDISS is calculated from (IDD × VDD). CMOS logic level inputs result in minimum power dissipation.
10Bandwidth, noise, and settling time are dependent on the terminal resistance value chosen. The lowest R value results in the fastest settling time and highest
bandwidth. The highest R value result in the minimum overall power consumption.
11All dynamic characteristics use VDD = 5 V.
12Different from settling time after fuse is blown. The OTP settling time occurs once only.
SCL
S
DA
t
1
t
2
t
3
t
8
t
8
t
9
t
4
t
5
t
9
t
7
t
6
t
10
PPS
03437-0-024
Figure 3. Interface Timing Diagram
Rev. PrC | Page 4 of 20
Preliminary Technical Data
AD5171
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter Rating
VDD to GND –0.3, +7 V
VA, VB, VW to GND GND, VDD
Maximum Current
IWB, IWA Pulsed
IWB Continuous (RWB ≤ 1 kΩ, A open)1
IWA Continuous (RWA ≤ 1 kΩ, B open)1
±20 mA
±5 mA
±5 mA
Digital Inputs and Output Voltage to GND 0 V, VDD
Operating Temperature Range –40°C to +125°C
Maximum Junction Temperature (TJ max) 150°C
Storage Temperature –65°C to +150°C
Lead Temperature (Soldering, 10 sec)
Vapor Phase (60 sec)
Infrared (15 sec)
300°C
215°C
220°C
Thermal Resistance2 θJA 230°C/W
1Maximum terminal current is bounded by the maximum applied voltage
across any two of the A, B, and W terminals at a given resistance, the
maximum current handling of the switches, and the maximum power
dissipation of the package. VDD = 5 V.
2Package Power Dissipation = (TJ max – TA) / θJA
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or
any other condition s above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. PrC | Page 5 of 20
Preliminary Technical Data
AD5171
PIN CONFIGURATION AND FUNCTIONAL DESCRIPTIONS
TOP VIEW
(Not to Scale)
8
7
6
5
1
2
3
4
W
V
DD
GND
SCL
A
B
AD0
SDA
AD5171
03437-0-003
Figure 4. SOT-23-8
Table 3. Pin Function Descriptions
Pin No. Mnemonic Description
1 W Wiper Terminal W. GND ≤ VW ≤ VDD.
2 VDD Positive Power Supply. Specified for operation from 2.7 V to 5.5 V. For OTP programming, VDD needs to be a
minimum of 6 V and 100 mA driving capability.
3 GND Common Ground.
4 SCL Serial Clock Input. Requires pull-up resistor.
5 SDA Serial Data Input/Output. Requires pull-up resistor.
6 AD0 I2C Device Address Bit. Allows maximum of two AD5171s to be addressed.
7 B Resistor Terminal B. GND ≤ VB ≤ VDD.
8 A Resistor Terminal A. GND ≤ VA ≤ VDD.
Rev. PrC | Page 6 of 20
Preliminary Technical Data
AD5171
TYPICAL PERFORMANCE CHARACTERISTICS
–0.10
–0.08
–0.06
–0.04
–0.02
0
0.02
0.04
0.06
0.08
0.10
RHEOSTAT MODE INL (LSB)
32248160 40485664
CODE (DECIMAL)
03437-0-004
–40°C
+25°C
+125°C
VDD = 5V
Figure 5. R-INL vs. Code vs. Temperature
–0.10
–0.08
–0.06
–0.04
–0.02
0
0.02
0.04
0.06
0.08
0.10
RHEOSTAT MODE DNL (LSB)
32248160 40485664
CODE (DECIMAL)
03437-0-005
–40°C
+25°C
+125°C
VDD = 5V
Figure 6. R-DNL vs. Code vs. Temperature
–0.10
–0.08
–0.06
–0.04
–0.02
0
0.02
0.04
0.06
0.08
0.10
POTENTIOMETER MODE INL (LSB)
32248160 40485664
CODE (DECIMAL)
03437-0-006
–40°C
+25°C +125°C
VDD = 5V
Figure 7. INL vs. Code vs. Temperature
–0.10
–0.08
–0.06
–0.04
–0.02
0
0.02
0.04
0.06
0.08
0.10
POTENTIOMETER MODE DNL (LSB)
32248160 40485664
CODE (DECIMAL)
03437-0-007
–40°C +25°C
+125°C
VDD = 5V
Figure 8. DNL vs. Code vs. Temperature
–0.7
–0.6
–0.5
–0.4
–0.3
–0.2
–0.1
0
FSE (LSB)
–40 –20 0 20 40 60 80 100 120 140
TEMPERATURE (°C)
03437-0-008
V
DD
= 5V
V
DD
= 3V
Figure 9. Full-Scale Error
0
0.1
0.2
0.3
0.4
0.5
0.6
ZSE (LSB)
–40 –20 0 20 40 60 80 100 120 140
TEMPERATURE (°C)
03437-0-009
V
DD
= 5V
V
DD
= 3V
Figure 10. Zero-Scale Error
Rev. PrC | Page 7 of 20
Preliminary Technical Data
AD5171
I
DD
SUPPLY CURRENT (µA)
0.1
1
10
–40 –20 0 20 40 60 80 100 120 140
TEMPERATURE (°C)
03437-0-010
V
DD
= 5V
V
DD
= 3V
Figure 11. Supply Current vs. Temperature
–40
–20
20
100
140
180
60
0
80
120
160
40
RHEOSTAT MODE TEMPCO (ppm/°C)
32248160 40485664
CODE (DECIMAL)
03437-0-011
Figure 12. Rheostat Mode Tempco (∆RAB/RAB)/ ∆T vs. Code
–5
0
5
10
15
20
25
RHEOSTAT MODE TEMPCO (ppm/°C)
32248160 40485664
CODE (DECIMAL)
03437-0-012
Figure 13. Potentiometer Mode Tempco (∆VW /VW)/ ∆T vs. Code
100 1M1k 10k 100k 10M
FREQUENCY (Hz)
0
6
–6
–12
–18
–24
–30
–36
–54
–42
–48
MAGNITUDE (dB)
0x02
0x01
0x00
0x04
0x08
0x10
0x20
03437-0-013
Figure 14. Gain vs. Frequency vs. Code, RAB = 5 kΩ
100 1M1k 10k 100k
FREQUENCY (Hz)
0
6
–6
–12
–18
–24
–30
–36
–54
–42
–48
MAGNITUDE (dB)
0x3F
0x20
0x10
0x08
0x04
0x02
0x01
0x00
03437-0-001
Figure 15. Gain vs. Frequency vs. Code, RAB = 10 kΩ
100 1M1k 10k 100k
FREQUENCY (Hz)
0
6
–6
–12
–18
–24
–30
–36
–54
–42
–48
MAGNITUDE (dB)
0x3F
0x20
0x10
0x08
0x04
0x02
0x01
0x00
03437-0-015
Figure 16. Gain vs. Frequency vs. Code, RAB = 50 Ω
Rev. PrC | Page 8 of 20
Preliminary Technical Data
AD5171
FREQUENCY (Hz)
100 1k
0
–6
6
–12
–18
–24
–30
–36
–54
–42
–48
MAGNITUDE (dB)
0x3F
0x20
0x10
0x08
0x04
0x02
0x01
0x00
1M10k 100k
03437-0-016
Figure 17. Gain vs. Frequency vs. Code, RAB = 100 kΩ
FREQUENCY (Hz)
80
40
100 1M1k 10k 100k
POWER SUPPLY REJECTION RATIO (–dB)
60
20
0
T
A
= 25°C
CODE = 0x20
V
A
= 2.5V, V
B
= 0V
V
DD
= 5V DC ± 1.0V p-p AC
V
DD
= 3V DC ± 0.6V p-p AC
03437-0-017
Figure 18. PSRR vs. Frequency
10mV 5V 500ns
V
DD
= 5.5V
V
A
= 5.5V
V
B
= GND
f
CLK
= 100kHz
SCL = 5V/DIV
V
W
= 10mV/DIV
03437-0-018
Figure 19. Digital Feedthrough vs. Time
VDD = 5.5V
VA= 5.5V
VB= GND
f
CLK = 400kHz
DATA 0x00 0x3F
5V 5V 5µs
03437-0-019
SCL = 5V/DIV
VW = 5V/DIV
Figure 20. Settling Time
V
DD
= 5.5V
V
A
= 5.5V
V
B
= GND
f
CLK
= 100kHz
DATA 0x20 0x1F
5V50mV 200ns
V
W
= 50mV/DIV
SCL = 5V/DIV
03437-0-020
Figure 21. Midscale Glitch Energy
5V1V
OTP PROGRAMMED AT MS
V
DD
= 5.5V
V
A
= 5.5V
R
AB
= 10kΩ
5µs
V
DD
= 5V/DIV
V
W
= 1V/DIV
03437-0-021
Figure 22. Power-Up Settling Time, after Fuses Blown
Rev. PrC | Page 9 of 20
Preliminary Technical Data
AD5171
THEORETICAL I
WB_MAX
(mA)
0.01
1.00
0.10
10.00
32248160 40485664
CODE (DECIMAL)
03437-0-022
R
AB
= 100k
Ω
R
AB
= 50k
Ω
R
AB
= 10k
Ω
R
AB
= 5k
Ω
V
A
= V
B
= OPEN
T
A
= 25°C
Figure 23. IWB_max vs. Code
Rev. PrC | Page 10 of 20
Preliminary Technical Data
AD5171
THEORY OF OPERATION
The AD5171 allows unlimited 6-bit adjustments, except for one-
time programmable, set-and-forget resistance setting. OTP
technology is a proven cost-effective alternative over EEMEM
in one-time memory programming applications. AD5171
employs fuse link technology to achieve the memory retention
of the resistance setting function. It comprises six data fuses,
which control the address decoder for programming the RDAC,
one user mode test fuse for checking setup error, and one
programming lock fuse for disabling any further programming
once the data fuses are blown.
ONE-TIME PROGRAMMING (OTP)
Prior to OTP activation, the AD5171 presets to midscale during
power on. After the wiper is set at the desired position, the
resistance can be permanently set by programming the T bit to
high along with the proper coding (Table 7).
The device control circuit has two validation bits, E1 and E0,
that can be read back in the read mode for checking the
programming status as shown in Table 4.
Table 4. Validation Status
E1 E0 Status
0 0 Ready for Programming
0 1
Test Fuse Not Blown Successfully. (For factory
setup checking purpose only. Users should not
see these combinations.)
1 0 Error. Some fuses are not blown. Try again.
1 1 Successful. No further programming is possible.
When the OTP T bit is set, the internal clock is enabled. The
program will attempt to blow a test fuse. The operation stops if
this fuse is not blown properly. The validation Bits E1 and E0
show 01, and the users should check the setup. If the test fuse is
blown successfully, the data fuses will be programmed next. The
six data fuses will be programmed in six clock cycles. The
output of the fuses is compared with the code stored in the
DAC register. If they do not match, E1 and E0 = 10 is issued as a
error and the operation stops. Users may retry with the same
codes. If the output and stored code match, the programming
lock fuse will be blown so that no further programming is
possible. In the meantime, E1 and E0 will issue 11 indicating the
lock fuse is blown successfully. All the fuse latches are enabled at
power-on and therefore the output corresponds to the stored
setting from this point on. Figure 24 shows a detailed functional
block diagram.
SDA
SCL A
W
B
FUSES
EN
DAC
REG.
I
2
C INTERFACE
COMPARATOR
ONE-TIME
PROGRAM/TEST
CONTROL BLOCK
MUX DECODER
FUSE
REG.
03437-0-025
Figure 24. Detailed Functional Block Diagram
DETERMINING THE VARIABLE RESISTANCE
AND VOLTAGE
Rheostat Mode Operation
If only the W-to-B or W-to-A terminals are used as variable
resistors, the unused terminal can be opened or shorted with W.
This operation is called rheostat mode (Figure 25).
A
W
B
A
W
B
A
W
B
03437-0-050
Figure 25. Rheostat Mode Configuration
The nominal resistance (RAB) of the RDAC has 64 contact
points accessed by the wiper terminal, plus the B terminal
contact if RWB is considered. The 6-bit data in the RDAC latch is
decoded to select one of the 64 settings. Assuming that a 10 kΩ
part is used, the wiper’s first connection starts at the B terminal
for data 0x00. Such connection yields a minimum of 60 Ω
resistance between terminals W and B because of the 60 Ω
wiper contact resistance. The second connection is the first tap
point, which corresponds to 219 Ω (RWB = (1) × RAB/63 + RW)
for data 0x01, and so on. Each LSB data value increase moves
the wiper up the resistor ladder until the last tap point is
reached at 10060 Ω ((63) × RAB/63 + RW). Figure 26 shows a
simplified diagram of the equivalent RDAC circuit. The general
equation determining RWB is
W
AB
WB RR
D
DR +×= 63
)( (1)
where:
D is the decimal equivalent of the 6-bit binary code.
RAB is the end-to-end resistance.
RW is the wiper resistance contributed by the on-resistance of
the internal switch.
Rev. PrC | Page 11 of 20
Preliminary Technical Data
AD5171
Table 5. RWB vs. Codes; RAB = 10 kΩ and
the A Terminal Is Opened
D (Dec) RWB (Ω) Output State
63 10060 Full-Scale (RAB + RW)
32 5139 Midscale
1 219 1 LSB
0 60 Zero-Scale (Wiper Contact Resistance)
Since a finite wiper resistance of 60 Ω is present in the zero-
scale condition, care should be taken to limit the current flow
between W and B in this state to a maximum pulse current of
no more than 20 mA. Otherwise, degradation or possible
destruction of the internal switch contact can occur.
Similar to the mechanical potentiometer, the resistance of the
RDAC between the wiper W and terminal A also produces a
complementary resistance RWA . When these terminals are used,
the B terminal can be opened or shorted to W. Setting the
resistance value for RWA starts at a maximum value of resistance
and decreases as the data loaded in the latch increases in value.
The general equation for this operation is
W
R
AB
R
D
D
WA
R+×
−
=63
63
)( (2)
D
Table 6. RWA vs. Codes; RAB =10 kΩ and
B Terminal Is Opened
D (Dec) RWA (Ω) Output State
63 60 Full-Scale
32 4980 Midscale
1 9901 1 LSB
0 10060 Zero-Scale
The typical distribution of the resistance tolerance from device
to device is process lot dependent, and it is possible to have
±30% tolerance.
D5
D4
D3
D2
D1
D0
RDAC
LATCH
AND
DECODER
R
S
R
S
R
S
A
W
B
03437-0-026
Figure 26. AD5171 Equivalent RDAC Circuit
Potentiometer Mode Operation
If all three terminals are used, the operation is called the
potentiometer mode. The most common configuration is the
voltage divider operation (Figure 27).
A
V
I
W
B
V
O
03437-0-051
Figure 27. Potentiometer Mode Configuration
Ignoring the effect of the wiper resistance, the transfer function
is simply
A
WV
D
DV
63
)( = (3)
A more accurate calculation, which includes the wiper
resistance effect, yields
A
W
W
AB
WV
R
RR
DV
2R
63
)(
AB +
+
= (4)
Unlike in rheostat mode operation where the absolute tolerance
is high, potentiometer mode operation yields an almost ratio-
metric function of D/63 with a relatively small error contributed
by the RW terms, and therefore the tolerance effect is almost
cancelled. Although the thin film step resistor RS and CMOS
switches resistance RW have very different temperature coefficients,
the ratio-metric adjustment also reduces the overall temperature
coefficient effect to 5 ppm/oC, except at low value codes where RW
dominates.
Potentiometer mode operations include others such as op amp
input, feedback resistor networks, and other voltage scaling
applications. A, W, and B terminals can in fact be input or output
terminals provided that |VAB|, |VWA |, and |VWB| do not exceed
VDD to GND.
ESD PROTECTION
Digital inputs SDA and SCL are protected with a series input
resistor and parallel Zener ESD structures (Figure 28).
LOGIC
340
Ω
03437-0-027
Figure 28. ESD Protection of Digital Pins
Rev. PrC | Page 12 of 20
Preliminary Technical Data
AD5171
TERMINAL VOLTAGE OPERATING RANGE
There are also ESD protection diodes between VDD and the
RDAC terminals. The VDD of AD5171 therefore defines their
voltage boundary conditions, see Figure 29. Supply signals
present on terminals A, B, and W that exceed VDD will be
clamped by the internal forward-biased diodes and should be
avoided.
GND
A
W
B
VDD
03437-0-029
Figure 29. Maximum Terminal Voltages Set by VDD
POWER-UP/POWER-DOWN SEQUENCES
Similarly, because of the ESD protection diodes, it is important
to power VDD first before applying any voltages to terminals A,
B, and W. Otherwise, the diode will be forward-biased such that
VDD will be powered unintentionally and may affect the rest of
the users’ circuits. The ideal power-up sequence is in the
following order: GND, VDD, digital inputs, and VA/VB/VW. The
order of powering VA, VB, VW, and digital inputs is not
important as long as they are powered after VDD. Similarly, VDD
should be powered down last.
POWER SUPPLY CONSIDERATIONS
To minimize the package pin count, both the one-time
programming and normal operating voltages are applied to the
same VDD terminal of the AD5171. The AD5171 employs fuse
link technology that requires 6 V to blow the internal fuses to
achieve a given setting. On the other hand, it operates at 2.7 V to
5.5 V once the programming is complete. Such dual voltage
requires isolation between supplies. The fuse programming
supply (either an on-board regulator or rack-mount power
supply) must be rated at 6 V and be able to handle 400 ms and
100 mA of transient current for one-time programming. Once
programming is complete, the 6 V supply must be removed to
allow normal operation of 2.7 V to 5.5 V. Figure 30 shows the
simplest implementation using a jumper. This approach saves
one voltage supply, but draws additional current and requires
manual configuration.
AD5171
V
DD
C2
0.1µF
5V
CONNECT J1
HERE FOR OTP
C1
1µF
J1
R1
50kΩ
R2
250kΩ
6V
CONNECT J1
HERE AFTER OTP
03437-0-030
Figure 30. Power Supply Requirement
An alternate approach in 3.5 V to 5.5 V systems adds a signal
diode between the system supply and the OPT supply for
isolation, as shown in Figure 31.
AD5171
V
DD
C2
0.1µF
APPLY FOR OTP ONLY
C1
10µF
D1
3.5V–5.5V
6V
03437-0-031
Figure 31. Isolating the 6 V OPT Supply from the 3.5V to 5.5 V Normal
Operating Supply. The 6 V supply must be removed once OPT is complete.
AD5171
V
DD
C2
0.1µF
APPLY FOR OTP ONLY
C1
10µF
10kΩ
2.7V
6V
P1 P2
R1
P1 = P2 = FDV302P, NDS0610
03437-0-052
Figure 32. Isolating the 6 V OPT Supply from the 2.7 V Normal Operating
Supply. The 6 V supply must be removed once OPT is complete.
For users who operate their systems at 2.7 V, it is recommended
to use the bi-directional low-threshold P-Ch MOSFETs for the
supplies isolation. As shown in Figure 32 assumes the 2.7 V
system voltage is applied first but not the 6 V. The gates of P1
are P2 are pulled to ground, which turns on P1 and subse-
quently P2. As a result, VDD of AD5171 becomes 2.7 V minus a
few tenths of mV drop across P1 and P2. When the AD5171
setting is found, the factory tester applies the 6 V to VDD and
also to the gates of P1 and P2 to turn them off. While the OTP
command is executing at this time to program AD5171, the
2.7 V source is therefore protected. Once the OTP is complete,
the tester withdraws the 6 V, and AD5171 setting is permanently
fixed.
Rev. PrC | Page 13 of 20
Preliminary Technical Data
AD5171
CONTROLLING THE AD5171
There are two ways of controlling the AD5171. Users can either
program the devices with computer software or external I2C
controllers.
Software Programming
Due to the advantage of the one-time programmable feature,
users may consider programming the device in the factory
before shipping to end users. ADI offers a device programming
software, which can be implemented in the factory on PCs that
run Windows 95 to XP platforms. As a result, external control-
lers are not required, which significantly reduces development
time. The program is an executable file that does not require
any programming languages or user programming skills. It is
easy to set up and use. Figure 33 shows the software interface.
The software can be downloaded from www.analog.com.
Figure 33. AD5171 Computer Software Interface
Write
The AD5171 starts at midscale after power-up prior to the OPT
programming. To increment or decrement the resistance, the
user may simply move the scrollbar on the left. To write any
specific values, the user should use the bit pattern control in the
upper screen and press the Run button. The format of writing
data to the device is shown in Table 7. Once the desirable setting
is found, the user may press the Program Permanent button to
blow the internal fuse links for permanent setting. The user may
also set the programming bit pattern in the upper screen and
press the Run button to achieve the same result.
Read
To read the validation bits and data out from the device, the
user may simply press the Read button. The user may also set
the bit pattern in the upper screen and press the Run button.
The format of reading data out from the device is shown in
Table 8.
To apply the device programming software in the factory, users
need to modify a parallel port cable and configure Pins 2, 3, 15,
and 25 for SDA_write, SCL, SDA_read, and DGND, respectively
for the control signals (Figure 34). Users should also layout the
PCB of the AD5171 with SCL and SDA pads, as shown in
Figure 35, such that pogo pins can be inserted for the factory
programming.
13
25
12
24
11
23
10
22
9
21
8
20
7
19
6
18
5
17
4
16
3
15
2
14
1
SCL
R3
100Ω
R2
100Ω
R1
100Ω
SDA
READ
WRITE
03437-0-033
Figure 34. Parallel Port Connection. Pin 2 = SDA_write, Pin 3 = SCL,
Pin 15 = SDA_read, and Pin 25 = DGND
W
V
DD
DGND
SCL
A
B
AD0
SDA
03437-0-034
Figure 35. Recommended AD5171 PCB Layout. The SCL and SDA pads allow
pogo pins to be inserted so that signals can be communicated through the
parallel port for programming (Figure 34).
Table 7. SDA Write Mode Bit Format
S 0 1 0 1 1 0 AD0 0 A T X X X X X X X A X X D5 D4 D3 D2 D1 D0 A P
Slave Address Byte Instruction Byte Data Byte
Table 8. SDA Read Mode Bit Format
S 0 1 0 1 1 0 AD0 1 A E1 E0 D5 D4 D3 D2 D1 D0 A P
Slave Address Byte Data Byte
Rev. PrC | Page 14 of 20
Preliminary Technical Data
AD5171
Table 9. SDA Bits Definitions and Descriptions
Bit Description Bit Description
S
P
Start Condition.
Stop Condition.
D5, D4, D3,
D2, D1, D0
Data Bits.
A Acknowledge.
AD0 I2C Device Address Bit. Allows maximum of
two AD5171s to be addressed.
X Don’t Care.
T OTP Programming Bit. Logic 1 programs wiper
position permanently.
E1, E0
0, 0
0, 1
1, 0
1, 1
OTP Validation Bits.
Ready to Program.
Test Fuse Not Blown Successfully. (For Factory Setup Checking
Purpose Only. Users should not see these combinations).
Fatal Error. Try again.
Programmed Successfully. No further adjustments possible.
I2C Controller Programming
Write Bit Pattern Illustrations
SDA
FRAME 1
SLAVE ADDRESS BYTE
FRAME 2
INSTRUCTION BYTE
FRAME 1
DATA BYTE
SCL
ACK. BY
AD5171
ACK. BY
AD5171
ACK. BY
AD5171
STOP BY
MASTER
S
TART B
Y
MASTER
0
1
10110AD0 R/W 0XXXXXXXXXD5
D4 D3 D2 D1 D0
91919
03437-0-035
Figure 36. Writing to the RDAC Register
SDA
FRAME 1
SLAVE ADDRESS BYTE
FRAME 2
INSTRUCTION BYTE
FRAME 1
DATA BYTE
SCL
ACK. BY
AD5171
ACK. BY
AD5171
ACK. BY
AD5171
STOP BY
MASTER
START BY
MASTER
0
1
10110AD0 R/W 1XXXXXXXXX D5D4D3D2D1D0
91919
03437-0-036
Figure 37. Activating One-Time Programming
Read Bit Pattern Illustration
SDA
FRAME 1
SLAVE ADDRESS BYTE
FRAME 2
RDAC REGISTER
SCL
ACK. BY
AD5171
NO ACK. BY
MASTER
STOP BY
MASTER
S
TART B
Y
MASTER
0
1
10110AD0 E1 E0 D5 D4 D3 D2 D1 D0
91 9
R/W
03437-0-037
Figure 38. Reading Data from RDAC Register
For users who prefer to use external controllers, the AD5171
can be controlled via an I2C compatible serial bus and is
connected to this bus as slave device. Referring to Figure 36,
Figure 37, and Figure 38, the 2-wire I2C serial bus protocol
operates as follows:
1. The master initiates data transfer by establishing a start
condition, which is when SDA from high-to-low while SCL
is high (Figure 36 and Figure 37). The following byte is the
slave address byte, which consists of the 6 MSBs as a slave
address defined as 010110. The next bit is AD0, which is an
I2C device address bit. Depending on the states of their
AD0 bits, two AD5171 can be addressed on the same bus
(Figure 39). The last LSB is the R/W bit, which determines
whether data will be read from or written to the slave
device.
The slave whose address corresponds to the transmitted
address responds by pulling the SDA line goes low during
the 9th clock pulse (this is termed the Acknowledge bit). At
Rev. PrC | Page 15 of 20
Preliminary Technical Data
AD5171
this stage, all other devices on the bus remain idle while the
selected device waits for data to be written to or read from
its serial register.
2. The write operation contains one more instruction byte
than the read operation. The instruction byte in the write
mode follows the slave address byte. The MSB of the
instruction byte labeled T is the one-time programming
bit. After acknowledging the instruction byte, the last byte
in the write mode is the data byte. Data is transmitted over
the serial bus in sequences of nine clock pulses (eight data
bits followed by an Acknowledge bit). The transitions on
the SDA line must occur during the low period of SCL and
remain stable during the high period of SCL (Figure 36).
3. In the read mode, the data byte follows immediately after
the acknowledgment of the slave address byte. Data is
transmitted over the serial bus in sequences of nine clock
pulses (slight difference with the write mode; there are
eight data bits followed by a No Acknowledge bit).
Similarly, the transitions on the SDA line must occur
during the low period of SCL and remain stable during the
high period of SCL (Figure 38).
4. When all data bits have been read or written, a stop
condition is established by the master. A stop condition is
defined as a low-to-high transition on the SDA line while
SCL is high. In the write mode, the master will pull the
SDA line high during the 10th clock pulse to establish a stop
condition (Figure 36 and Figure 37). In the read mode, the
master will issue a No Acknowledge for the 9th clock pulse,
i.e., the SDA line remains high. The master will then bring
the SDA line low before the 10th clock pulse, which goes
high to establish a stop condition (Figure 38).
A repeated write function gives the user flexibility to update the
RDAC output a number of times, except after permanent
programming, addressing, and instructing the part only once.
During the write cycle, each data byte will update the RDAC
output. For example, after the RDAC has acknowledged its slave
address and instruction bytes, the RDAC output will update
after these two bytes. If another byte is written to the RDAC
while it is still addressed to a specific slave device with the same
instruction, this byte will update the output of the selected slave
device. If different instructions are needed, the write mode has
to be started with a new slave address, instruction, and data
bytes. Similarly, a repeated read function of the RDAC is also
allowed.
CONTROLLING TWO DEVICES ON ONE BUS
Figure 39 shows two AD5171 devices on the same serial bus.
Each has a different slave address since the state of each AD0
pin is different. This allows each device to be operated
independently. The master device output bus line drivers are
open-drain pull-downs in a fully I2C compatible interface.
MASTER
SDA SCL
AD0
AD5171
SDA SCL
AD0
AD5171
SDA
SCL
5V
Rp Rp
5V
03437-0-038
Figure 39. Two AD5171 Devices on One Bus
Rev. PrC | Page 16 of 20
Preliminary Technical Data
AD5171
APPLICATIONS
PROGRAMMABLE VOLTAGE REFERENCE (DAC)
It is common to buffer the output of the digital potentiometer
as a DAC unless the load is much larger than RWB. The buffer
serves the purpose of impedance conversion as well as
delivering higher current, which may be needed.
GND
V
IN
V
OUT
1U1
5V
2
3
V
0
AD8601
5V
A
W
B
AD1582
ADR03
A1
AD5171
U2
03437-0-039
Figure 40. Programmable Voltage Reference (DAC)
GAIN CONTROL COMPENSATION
The digital potentiometers are commonly used in gain controls
(Figure 41) or sensor transimpedance amplifier signal
conditioning applications. To avoid gain peaking or in worst-
case oscillation due to step response, a compensation capacitor
is needed. In general, C2 in the range of a few picofarads to no
more than a few tenths of a picofarad is adequate for the
compensation.
U1
C2
4.7pF
A
B
W
R2 100kΩ
VO
VI
R1
47kΩ
03437-0-040
Figure 41. Typical Noninverting Gain Amplifier
PROGRAMMABLE VOLTAGE SOURCE WITH
BOOSTED OUTPUT
For applications that require high current adjustment, such as a
laser diode driver or tunable laser, a boosted voltage source can
be considered (Figure 42).
+V
W
SIGNAL
C
C
R
BIAS
LD
V
IN
A
B
V
OUT
U1
A
D5171
U3 2N7002
AD8601
U2
–V
I
L
03437-0-041
Figure 42. Programmable Booster Voltage Source
In this circuit, the inverting input of the op amp forces the VOUT
to be equal to the wiper voltage set by the digital potentiometer.
The load current is then delivered by the supply via the N-Ch
FET N1. N1 power handling must be adequate to dissipate
(VI − VO) × IL power. This circuit can source a maximum of
100 mA with a 5 V supply. For precision applications, a voltage
reference such as ADR421, ADR03, or ADR370 can be applied
at the A terminal of the digital potentiometer.
LEVEL SHIFTING FOR DIFFERENT VOLTAGE
OPERATION
When users need to interface a 2.5 V controller with AD5171, a
proper voltage level shift must be employed so that the digital
potentiometer can be read from or written to the controller;
Figure 43 shows one of the implementations. M1 and M2
should be low threshold N-Ch power MOSFETs, such as
FDV301N.
2.5V
CONTROLLER
2.7V–5.5V
AD5171
Rp Rp Rp Rp
V
DD1
= 2.5V V
DD2
= 5V
G
G
SD
M1 SD
M2
SDA1
SCL1
SDA2
SCL2
03437-0-042
Figure 43. Level Shifting for Different Voltage Operation
RESISTANCE SCALING
The AD5171 offers 5 kΩ, 10 kΩ, 50 kΩ, and 100 kΩ nominal
resistances. For users who need to optimize the resolution with
an arbitrary full-range resistance, the following techniques can
be used. By paralleling a discrete resistor (Figure 44) a
proportion tely lower voltage appears at terminal A to B, which
is applicable to only the voltage divider mode.
This translates into a finer degree of precision because the step
size at terminal W will be smaller. The voltage can be found as
DD
A
B
AB
WV
D
RRR
RR
DV ××
+
=642||3
)2||(
)( (5)
R1
R2
B
A
V
DD
R3
W
03437-0-043
Figure 44. Lowering the Nominal Resistance
Rev. PrC | Page 17 of 20
Preliminary Technical Data
AD5171
For log taper adjustment, such as volume control, Figure 45
shows another way of resistance scaling to achieve the log taper
function. In this circuit, the smaller the R2 with respect to RAB,
the more like the pseudo log taper characteristic it behaves. The
wiper voltage is simply
I
WB
WA
WB
WV
RRR
RR
DV ×
+
=2||
)2||(
)( (6)
V
I
R1
B
A
R2
V
O
W
03437-0-044
Figure 45. Resistor Scaling with Log Adjustment Characteristics
RESOLUTION ENHANCEMENT
The resolution can be doubled in the potentiometer mode of
operation by using three digital potentiometers. Borrowed from
ADI’s patented RDAC segmentation technique, users can con-
figure three AD5171 (Figure 46) to double the resolution. First,
U3 must be parallel with a discrete resistor RP, which is chosen
to be equal to a step resistance (RP = RAB/64). One can see that
adjusting U1 and U2 together forms the coarse 6-bit adjustment
and that adjusting U3 alone forms the finer 6-bit adjustment. As a
result, the effective resolution becomes 12-bit.
U1
A1
B1
W1
U2
A2
B2
W3
W2
U3
A3
B3
R
P
COARSE
DJUSTMEN
FINE
ADJUSTMENT
03437-0-045
Figure 46. Doubling the Resolution
RDAC CIRCUIT SIMULATION MODEL
The internal parasitic capacitances and the external capacitive
loads dominate the ac characteristics of the digital potentio-
meters. Configured as a potentiometer divider, the –3 dB
bandwidth of the AD5171 (5 kΩ resistor) measures 1.5 MHz at
half scale. Figure 14 to Figure 17 provide the large signal BODE
plot characteristics of the four available resistor versions 5 kΩ
10 kΩ, 50 kΩ, and 100 kΩ. A parasitic simulation model is
shown in Figure 47. Listing 1 provides a macro model net list
for the 10 kΩ device.
55pF
C
A
25pF
C
B
25pF
AB
RDAC
10kΩ
W
C
W
03437-0-046
Figure 47. Circuit Simulation Model for RDAC = 10 kΩ
Listing 1. Macro Model Net List for RDAC
.PARAM D=64, RDAC=10E3
*
.SUBCKT DPOT (A,W,B)
*
CA A 0 25E-12
RWA A W {(1-D/64)*RDAC+60}
CW W 0 55E-12
RWB W B {D/64*RDAC+60}
CB B 0 25E-12
*
.ENDS DPOT
Rev. PrC | Page 18 of 20
Preliminary Technical Data
AD5171
AD5171 EVALUATION BOARD
8
7
6
5
4
3
2
1
J1
W
V
DD
GND
SCL
A
B
AD0
SDA
OUT1
OUT1
+IN1
V+
V–
–IN2
+IN2
OUT2
–IN1
JP8
JP7
JP4
JP6
C8
0.1µFC9
10µF
V
EE
U3A
CP4
CP2
JP5
JP3
C6
0.1µF
C7
10µF
1
2
3
4
8
5
6
7
–IN1
CP3
CP1
V
IN
1
AD5170 AD5171/AD5273
AGND
V
REF
ADR03
2
3
5
4
C1
10µF
C2
0.1µF
R1
10kΩ
R2
10kΩ
SCL
SDA
C3
0.1µF
U1
1
2
3
4
8
7
6
5
1
2
3
4
8
7
6
5
U2
C4
0.1µF
U4
TEMP
GND
V
IN
TRIM
V
OUT
C5
0.1µF
JP1
JP2
A
W
BCP6 CP7
U3B
V
DD
V
DD
W
V
DD
GND
SCL
A
B
AD0
SDA
V
DD
V
DD
V
CC
CP5
03437-0-047
Figure 48. AD5171 Evaluation Board Schematic
The AD5171 evaluation board comes with a dual op amp
AD822 and a 2.5 V reference ADR03. Users can configure many
other building block circuits with minimum components
needed. Figure 49 shows one of the examples. There is space
available on the board that users can build additional circuits
for further evaluations, see Figure 50.
A
B
WV
O
V
REF
A
B
W
V
DD
CP2
U2
JP1
JP2 JP4
JP3
JP7
4
U3A
1
OUT1
V+
V–
AD822
2
311
V
REF
03437-0-048
Figure 49. Programmable Voltage Reference
Figure 50. AD5171 Evaluation Board
Rev. PrC | Page 19 of 20
Preliminary Technical Data
AD5171
OUTLINE DIMENSIONS
13
5 6
2
8
4
7
2.90 BSC
PIN 1
1.60 BSC
1.95
BSC
0.65 BSC
0.38
0.22
0.15 MAX
1.30
1.15
0.90
SEATING
PLANE
1.45 MAX
0.22
0.08
0.60
0.45
0.30
8°
4°
0°
2.80 BSC
COMPLIANT TO JEDEC STANDARDS MO-178BA
Figure 51. 8-Lead Small Outline Transistor Package [SOT-23] (RJ-8)
Dimensions shown in millimeters
ORDERING GUIDE
Model RAB (kΩ) Package Code Package Description Full Container Quantity Branding
AD5171BRJ5-RL7 5 RJ-8 SOT-23-8 3000 D12
AD5171BRJ10-RL7 10 RJ-8 SOT-23-8 3000 D13
AD5171BRJ50-RL7 50 RJ-8 SOT-23-8 3000 D14
AD5171BRJ100-REEL7 100 RJ-8 SOT-23-8 3000 D15
AD5171BRJ5-R2 5 RJ-8 SOT-23-8 3000 D12
AD5171BRJ10-R2 10 RJ-8 SOT-23-8 3000 D13
AD5171BRJ50-R2 50 RJ-8 SOT-23-8 3000 D14
AD5171BRJ100-R2 100 RJ-8 SOT-23-8 3000 D15
AD5171EVAL* 10 1
* The evaluation board is shipped with three pieces of 10 kΩ parts. Users should order extra samples or different resistance options if needed.
Purchase of licensed I2C components of Analog Devices or one of its
sublicensed Associated Companies conveys a license for the purchaser under
the Philips I2C Patent Rights to use these components in an I2C system,
provided that the system conforms to the I2C Standard Specification as
defined by Philips.
© 2003 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
C03437-0-9/03(PrC)
Rev. PrC | Page 20 of 20
Preliminary Technical Data