1.8 V, 12-LVDS/24-CMOS Output,
Low Power Clock Fanout Buffer
ADCLK854
Rev. 0
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FEATURES
2 selectable differential inputs
Selectable LVDS/CMOS outputs
Up to 12 LVDS (1.2 GHz) or 24 CMOS (250 MHz) outputs
<12 mW per channel (100 MHz operation)
54 fs rms integrated jitter (12 kHz to 20 MHz)
100 fs rms additive broadband jitter
2.0 ns propagation delay (LVDS)
135 ps output rise/fall (LVDS)
70 ps output-to-output skew (LVDS)
Sleep mode
Pin programmable control
1.8 V power supply
APPLICATIONS
Low jitter clock distribution
Clock and data signal restoration
Level translation
Wireless communications
Wired communications
Medical and industrial imaging
ATE and high performance instrumentation
GENERAL DESCRIPTION
The ADCLK854 is a 1.2 GHz/250 MHz LVDS/CMOS fanout
buffer optimized for low jitter and low power operation. Possible
configurations range from 12 LVDS to 24 CMOS outputs,
including combinations of LVDS and CMOS outputs. Three
control lines are used to determine whether fixed blocks of
outputs (three banks of four) are LVDS or CMOS outputs.
The ADCLK854 offers two selectable inputs and a sleep mode
feature. The IN_SEL pin state determines which input is fanned
out to all the outputs. The SLEEP pin enables a sleep mode to
power down the device.
The inputs accept various types of single-ended and differential
logic levels including LVPECL, LVDS, HSTL, CML, and CMOS.
Table 8 provides interface options for each type of connection.
This device is available in a 48-pin LFCSP package. It is specified
for operation over the standard industrial temperature range of
−40°C to +85°C.
FUNCTIONAL BLOCK DIAGRAM
OUT0 (OUT0A)
OUT0 (OUT0B)
OUT1 (OUT1A)
OUT1 (OUT1B)
OUT2 (OUT2A)
OUT2 (OUT2B)
OUT3 (OUT3A)
OUT3 (OUT3B)
LVDS/
CMOS
OUT4 (OUT4A)
OUT4 (OUT4B)
OUT5 (OUT5A)
OUT5 (OUT5B)
OUT6 (OUT6A)
OUT6 (OUT6B)
OUT7 (OUT7A)
OUT7 (OUT7B)
LVDS/
CMOS
OUT8 (OUT8A)
OUT8 (OUT8B)
OUT9 (OUT9A)
OUT9 (OUT9B)
OUT10 (OUT10A)
OUT10 (OUT10B)
OUT11 (OUT11A)
OUT11 (OUT11B)
LVDS/
CMOS
CTRL_C
CTRL_B
CTRL_A
IN_SEL
SLEEP
CLK1
CLK1
CLK0
CLK0
ADCLK854
V
REF
V
S
/2
07218-001
Figure 1.
ADCLK854
Rev. 0 | Page 2 of 16
TABLE OF CONTENTS
Features .............................................................................................. 1
Applicat ions ....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Electrical Characteristics ............................................................. 3
Timing Characteristics ................................................................ 4
Clock Characteristics ................................................................... 5
Logic and Power Characteristics ................................................ 5
Absolute Maximum Ratings ............................................................ 6
Determining Junction Temperature .......................................... 6
ESD Caution .................................................................................. 6
Thermal Performance .................................................................. 6
Pin Configuration and Function Descriptions ............................. 7
Typical Performance Characteristics ..............................................9
Functional Description .................................................................. 12
Clock Inputs ................................................................................ 12
AC-Coupled Input Applications ............................................... 12
Clock Outputs ............................................................................. 12
Control and Function Pins ........................................................ 13
Power Supply ............................................................................... 13
Applications Information .............................................................. 14
Using the ADCLK854 Outputs for ADC Clock Applications
....................................................................................................... 14
LVDS Clock Distribution .......................................................... 14
CMOS Clock Distribution ........................................................ 14
Input Termination Options ....................................................... 15
Outline Dimensions ....................................................................... 16
Ordering Guide .......................................................................... 16
REVISION HISTORY
4/09—Revision 0: Initial Version
ADCLK854
Rev. 0 | Page 3 of 16
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
Typical (Typ) values are given for VS = 1.8 V and TA = 25°C, unless otherwise noted. Minimum (Min) and maximum (Max) values are given over
the full VS = 1.8 V ± 5% and TA = −40°C to +85°C variation, unless otherwise noted. Input slew rate > 1 V/ns, unless otherwise noted.
Table 1. Clock Inputs and Outputs
Parameter Symbol Min Typ Max Unit Conditions
CLOCK INPUTS Differential input
Input Frequency 0 1200 MHz
Input Sensitivity, Differential 150 mV p-p Jitter performance improves with higher slew
rates (greater voltage swing)
Input Level 1.8 V p-p Larger voltage swings can turn on the protection
diodes and degrade jitter performance
Input Common-Mode Voltage VCM V
S/2 − 0.1 VS/2 + 0.5 V Inputs are self-biased; enables ac coupling
Input Common-Mode Range VCMR 0.4 VS − 0.4 V Inputs dc-coupled with 200 mV p-p signal applied
Input Voltage Offset 30 mV
Input Sensitivity, Single-Ended 150 mV p-p CLKx ac-coupled; CLKx ac bypassed to ground
Input Resistance (Differential) 7 kΩ
Input Capacitance CIN 2 pF
Input Bias Current (Each Pin) −350 +350 µA Full input swing
LVDS CLOCK OUTPUTS Termination = 100 Ω; differential (OUTx, OUTx)
Output Frequency 1200 MHz See Figure 9 for swing vs. frequency
Output Voltage Differential VOD 247 344 454 mV
Delta VOD VOD 50 mV
Offset Voltage VOS 1.125 1.25 1.375 V
Delta VOS VOS 50 mV
Short-Circuit Current ISA, ISB 3 6 mA Each pin (output shorted to GND)
CMOS CLOCK OUTPUTS Single-ended; termination = open; OUTx and
OUTx in phase
Output Frequency 250 MHz With 10 pF load per output; see Figure 16 for
swing vs. frequency
Output Voltage High VOH V
S − 0.1 V @ 1 mA load
Output Voltage Low VOL 0.1 V @ 1 mA load
Output Voltage High VOH V
S − 0.35 V @ 10 mA load
Output Voltage Low VOL 0.35 V @ 10 mA load
Reference Voltage VREF
Output Voltage VS/2 − 0.1 VS/2 VS/2 + 0.1 V ±500 µA
Output Resistance 60 Ω
Output Current 500 µA
ADCLK854
Rev. 0 | Page 4 of 16
TIMING CHARACTERISTICS
Table 2. Timing Characteristics
Parameter Symbol Min Typ Max Unit Conditions
LVDS OUTPUTS Termination = 100 differential; 3.5 mA
Output Rise/Fall Time tR , tF 135 235 ps 20% to 80% measured differentially
Propagation Delay, Clock-to-LVDS Output tPD 1.5 2.0 2.7 ns VICM = VREF, VID = 0.5 V
Temperature Coefficient 2.0 ps/°C
Output Skew1
LVDS Outputs in the Same Bank 50 ps
All LVDS Outputs
On the Same Part 65 ps
Across Multiple Parts 390 ps
Additive Time Jitter
Integrated Random Jitter 54 fs rms BW = 12 kHz to 20 MHz; clock = 1000 MHz
74 fs rms BW = 50 kHz to 80 MHz; clock = 1000 MHz
86 fs rms BW = 10Hz to 100 MHz; clock = 1000 MHz
Broadband Random Jitter2 150 fs rms Input slew = 1 V/ns, see Figure 11
Crosstalk Induced Jitter 260 fs rms Calculated from spur energy with an
interferer 10 MHz offset from the carrier
CMOS OUTPUTS
Output Rise/Fall Time tR, tF 525 950 ps 20% to 80%; CLOAD = 10 pF
Propagation Delay, Clock-to-CMOS Output tPD 2.5 3.2 4.2 ns 10 pF load
Temperature Coefficient 2.2 ps/°C
Output Skew1
CMOS Outputs in the Same Bank 155 ps
All CMOS Outputs
On the Same Part 175 ps
Across Multiple Parts 640 ps
Additive Time Jitter
Integrated Random Jitter 56 fs rms BW = 12 kHz to 20 MHz; clock = 200 MHz
Broadband Random Jitter2
100 fs rms Input slew = 2 V/ns, see Figure 11
Crosstalk Induced Jitter 260 fs rms Calculated from spur energy with an
interferer 10 MHz offset from the carrier
LVDS-TO-CMOS OUTPUT SKEW 3
LVDS Output(s) and CMOS Output(s) on the
Same Part
0.8 1.6 ns CMOS load = 10 pF and LVDS load = 100 Ω
1 This is the difference between any two similar delay paths while operating at the same voltage and temperature.
2 Calculated from the SNR of the ADC method.
3 Measured at the rising edge of the clock signal.
ADCLK854
Rev. 0 | Page 5 of 16
CLOCK CHARACTERISTICS
Table 3. Clock Output Phase Noise
Parameter Min Typ Max Unit Conditions
CLOCK-TO-LVDS ABSOLUTE PHASE NOISE Input slew rate > 1 V/ns
1000 MHz −90 dBc/Hz @ 10 Hz offset
−108 dBc/Hz @ 100 Hz offset
−117 dBc/Hz @ 1 kHz offset
−126 dBc/Hz @ 10 kHz offset
−135 dBc/Hz @ 100 kHz offset
−141 dBc/Hz @ 1 MHz offset
−146 dBc/Hz @ 10 MHz offset
CLOCK-TO-CMOS ABSOLUTE PHASE NOISE Input slew rate > 1 V/ns
200 MHz −101 dBc/Hz @ 10 Hz offset
−119 dBc/Hz @ 100 Hz offset
−127 dBc/Hz @ 1 kHz offset
−138 dBc/Hz @ 10 kHz offset
−147 dBc/Hz @ 100 kHz offset
−153 dBc/Hz @ 1 MHz offset
−156 dBc/Hz @ 10 MHz offset
LOGIC AND POWER CHARACTERISTICS
Table 4. Control Pin Characteristics
Parameter Symbol Min Typ Max Unit Conditions
CONTROL PINS (IN_SEL, CTRL_x, SLEEP)1
Logic 1 Voltage VIH V
S − 0.4 V
Logic 0 Voltage VIL 0.4 V
Logic 1 Current IIH 5 8 20 A
Logic 0 Current IIL −5 +5 A
Capacitance 2 pF
POWER
Supply Voltage Requirement VS 1.71 1.8 1.89 V VS = 1.8 V ± 5%
LVDS Outputs Full operation
LVDS @ 100 MHz 84 100 mA All outputs enabled as LVDS and loaded, RL = 100
LVDS @ 1200 MHz 175 215 mA All outputs enabled as LVDS and loaded, RL = 100
CMOS Outputs Full operation
CMOS @ 100 MHz 115 140 mA All outputs enabled as CMOS and loaded, CL = 10 pF
CMOS @ 250 MHz 265 325 mA All outputs enabled as CMOS and loaded, CL = 10 pF
SLEEP 3 mA SLEEP pin pulled high; does not include power dissipated
in the external resistors
Power Supply Rejection2
LVDS
PD
t
PSR 0.9 ps/mV
CMOS
PD
t
PSR 1.2 ps/mV
1 These pins each have a 200 kΩ internal pull-down resistor.
2 Change in tPD per change in VS.
ADCLK854
Rev. 0 | Page 6 of 16
ABSOLUTE MAXIMUM RATINGS
Table 5.
Parameter Rating
Supply Voltage
VS to GND 2 V
Inputs
CLKx and CLKx −0.3 V to +2 V
CMOS Inputs −0.3 V to +2 V
Outputs
Maximum Voltage −0.3 V to +2 V
Voltage Reference Voltage (VREF) −0.3 to +2 V
Operating Temperature
Ambient Range −40°C to +85°C
Junction 150°C
Storage Temperature Range −65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
DETERMINING JUNCTION TEMPERATURE
To determine the junction temperature on the application
printed circuit board (PCB), use the following equation:
TJ = TCASE + (ΨJT × PD)
where:
TJ is the junction temperature (°C).
TCASE is the case temperature (°C) measured by the user at the
top center of the package.
ΨJT is from Table 6.
PD is the power dissipation.
Values of θJA are provided for package comparison and PCB
design considerations. θJA can be used for a first-order approxi-
mation of TJ by the equation
TJ = TA + (
θ
JA × PD)
where TA is the ambient temperature (°C).
Values of θJB are provided in Table 6 for package comparison
and PCB design considerations.
ESD CAUTION
THERMAL PERFORMANCE
Table 6.
Parameter Symbol Description (Using a 2S2P Test Board) Value 1Unit
Junction-to-Ambient Thermal Resistance θJA
Still Air Per JEDEC JESD51-2
0.0 m/sec Air Flow 42 °C/W
Moving Air θJMA Per JEDEC JESD51-6
1.0 m/sec Air Flow 37 °C/W
2.5 m/sec Air Flow 33 °C/W
Junction-to-Board Thermal Resistance θJB
Moving Air Per JEDEC JESD51-8
1.0 m/sec Air Flow 26 °C/W
Junction-to-Case Thermal Resistance θJC
Moving Air Per MIL-STD 883, Method 1012.1
Die-to-Heat Sink 2 °C/W
Junction-to-Top-of-Package Characterization Parameter ΨJT
Still Air Per JEDEC JESD51-2
0 m/sec Air Flow 0.5 °C/W
1 Results are from simulations. The PCB is a JEDEC multilayer type. Thermal performance for actual applications requires careful inspection of the conditions in the
application to determine if they are similar to those assumed in these calculations.
ADCLK854
Rev. 0 | Page 7 of 16
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
13
14
15
16
17
18
19
20
21
22
23
24
CTRL_C
SLEEP
OUT10 (OUT10B)
OUT10 (OUT10A)
GND
VS
OUT9 (OUT9B)
OUT9 (OUT9A)
OUT8 (OUT8B)
OUT8 (OUT8A)
GND
VS
48
47
46
45
44
43
42
41
40
39
38
37
OUT0 (OUT0A
)
OUT0 (OUT0B
)
OUT1 (OUT1A
)
OUT1 (OUT1B
)
GND
VS
OUT2 (OUT2A
)
OUT2 (OUT2B
)
OUT3 (OUT3A
)
OUT3 (OUT3B
)
GND
VS
1
2
3
4
5
6
7
8
9
10
11
12
VREF
CLK0
CLK0
GND
CLK1
CLK1
VS
OUT11 (OUT11B)
OUT11 (OUT11A)
IN_SEL
CTRL_A
CTRL_B
NC
OUT4 (OUT4A)
OUT4 (OUT4B)
OUT5 (OUT5A)
OUT5 (OUT5B)
VS
GND
OUT6 (OUT6A)
OUT6 (OUT6B)
OUT7 (OUT7A)
OUT7 (OUT7B)
35
NC36
34
33
32
31
30
29
28
27
26
25
ADCLK854
TOP VIEW
(Not to Scale)
PIN 1
INDICATOR
NOTES:
1. NC = NO CONNECT.
2. EXPOSED PADDLE MUST BE CONNECTED TO GND.
07218-002
Figure 2. Pin Configuration
Table 7. Pin Function Descriptions
Pin No. Mnemonic Description
1 VREF Reference Voltage.
2 CLK0 Input (Negative) 0.
3 CLK0 Input (Positive) 0.
7, 18, 24, 30,
37, 43
VS Supply Voltage.
5 CLK1 Input (Negative) 1.
6 CLK1 Input (Positive) 1.
8 OUT11 (OUT11B) Complementary Side of Differential LVDS Output 11, or CMOS Output 11 on Channel B.
9 OUT11 (OUT11A) True Side of Differential LVDS Output 11, or CMOS Output 11 on Channel A.
10 IN_SEL Input Select. (0 = CLK0, CLK0; 1 = CLK1, CLK1). CMOS logic input with 200 kΩ pull-down resistor.
11 CTRL_A Control for Output 3 to Output 0 (0 = LVDS, 1 = CMOS). CMOS logic input with 200 kΩ pull-down resistor.
12 CTRL_B Control for Output 7 to Output 4 (0 = LVDS, 1 = CMOS). CMOS logic input with 200 kΩ pull-down resistor.
13 CTRL_C Control for Output 11 to Output 8 (0 = LVDS, 1 = CMOS). CMOS logic input with 200 kΩ pull-down resistor.
14 SLEEP Sleep Mode Control (0 = normal operation, 1 = sleep). CMOS logic input with 200 kΩ pull down resistor.
15 OUT10 (OUT10B) Complementary Side of Differential LVDS Output 10, or CMOS Output 10 on Channel B.
16 OUT10 (OUT10A) True Side of Differential LVDS Output 10, or CMOS Output 10 on Channel A.
4, 17, 23, 29,
38, 44
GND Ground Pin.
19 OUT9 (OUT9B) Complementary Side of Differential LVDS Output 9, or CMOS Output 9 on Channel B.
20 OUT9 (OUT9A) True Side of Differential LVDS Output 9, or CMOS Output 9 on Channel A.
21 OUT8 (OUT8B) Complementary Side of Differential LVDS Output 8, or CMOS Output 8 on Channel B.
22 OUT8 (OUT8A) True Side of Differential LVDS Output 8, or CMOS Output 8 on Channel A.
25 OUT7 (OUT7B) Complementary Side of Differential LVDS Output 7, or CMOS Output 7 on Channel B.
ADCLK854
Rev. 0 | Page 8 of 16
Pin No. Mnemonic Description
26 OUT7 (OUT7A) True Side of Differential LVDS Output 7, or CMOS Output 7 on Channel A.
27 OUT6 (OUT6B) Complementary Side of Differential LVDS Output 6, or CMOS Output 6 on Channel B.
28 OUT6 (OUT6A) True Side of Differential LVDS Output 6, or CMOS Output 6 on Channel A.
31 OUT5 (OUT5B) Complementary Side of Differential LVDS Output 5, or CMOS Output 5 on Channel B.
32 OUT5 (OUT5A) True Side of Differential LVDS Output 5, or CMOS Output 5 on Channel A.
33 OUT4 (OUT4B) Complementary Side of Differential LVDS Output 4, or CMOS Output 4 on Channel B.
34 OUT4 (OUT4A) True Side of Differential LVDS Output 4, or CMOS Output 4 on Channel A.
35 NC No Connect.
36 NC No Connect.
39 OUT3 (OUT3B) Complementary Side of Differential LVDS Output 3, or CMOS Output 3 on Channel B.
40 OUT3 (OUT3A) True Side of Differential LVDS Output 3, or CMOS Output 3 on Channel A.
41 OUT2 (OUT2B) Complementary Side of Differential LVDS Output 2, or CMOS Output 2 on Channel B.
42 OUT2 (OUT2A) True Side of Differential LVDS Output 2, or CMOS Output 2 on Channel A.
45 OUT1 (OUT1B) Complementary Side of Differential LVDS Output 1, or CMOS Output 1 on Channel B.
46 OUT1 (OUT1A) True Side of Differential LVDS Output 1, or CMOS Output 1 on Channel A.
47 OUT0 (OUT0B) Complementary Side of Differential LVDS Output 0, or CMOS Output 0 on Channel B.
48 OUT0 (OUT0A) True Side of Differential LVDS Output 0, or CMOS Output 0 on Channel A.
(49) EPAD Exposed Paddle. The exposed paddle must be connected to GND.
ADCLK854
Rev. 0 | Page 9 of 16
TYPICAL PERFORMANCE CHARACTERISTICS
VS = +1.8 V, TA = 25°C, unless otherwise noted.
CH2 100mV M 200ps 10.0GS/s CH1 –36.0mV
2
0
7218-003
CH2 100mV M 1.0ns 10.0GS/s CH1 –36.0mV
2
0
7218-006
Figure 3. LVDS Output Waveform @ 1200 MHz Figure 6. LVDS Output Waveform @ 200 MHz
2.3
2.2
2.1
2.0
1.9
1.8
1.7
0.1 1.71.51.31.10.90.70.50.3
PROPATATION DELAY (ns)
INPUT DIFFERENTIAL (V p-p)
07218-004
2.4
2.3
2.2
2.1
2.0
1.9
1.8
1.7
1.6
1.5
1.4
200 1600140012001000800600400
PROPAGATION DELAY (ns)
INPUT COMMON-MODE (mV)
07218-007
Figure 4. LVDS Propagation Delay vs. Input Differential Voltage (VID) Figure 7. LVDS Propagation Delay vs. VICM
55
45
46
47
48
49
50
51
52
53
54
0 200 400 600 800 1000 1200
DUTY CYCLE (%)
FREQUENCY (MHz)
07218-005
715
675
685
695
705
1.62 1.921.821.72
DIFFERENTIAL OUTPUT SWING (mV p-p)
POWER SUPPLY (V)
07218-008
Figure 5. LVDS Output Duty Cycle vs. Frequency Figure 8. LVDS Differential Output Swing vs. Power Supply Voltage
ADCLK854
Rev. 0 | Page 10 of 16
900
400
500
600
700
800
100
200
300
400
500
600
700
800
900
1000
1100
1200
1300
1400
1500
1600
1700
DIFFERENTIAL OUTPUT SWING (mV p-p)
INPUT FREQUENCY (MHz)
07218-009
Figure 9. LVDS Differential Output Swing vs. Input Frequency
350
325
300
275
250
225
200
175
150
125
100
75
50
25
0
0 200 400 600 800 1000 1200 1400 1600 1800
CURRENT (mA)
FREQUENCY (MHz)
07218-110
Figure 10. LVDS Current vs. Frequency; All Banks Set to LVDS
500
450
400
350
300
250
200
150
100
50
0
022.01.51.00.5
JITTER (fs rms)
INPUT SLEW RATE (V/ns)
.5
07218-011
Figure 11. Additive Broadband Jitter vs. Input Slew Rate
–
80
–90
–100
–110
–120
–130
–140
–150
–160
–170
–180
10 100M10M1M100k10k1k100
PHASE NOISE (dBc/Hz)
FREQUENCY OFFSET (Hz)
07218-012
ABSOLUTE PHASE NOISE MEASURED @ 1GHz WITH AGILENT
E5052 USING WENZEL CLOCK SOURCE CONSISTING OF A
WENZEL 100MHz CRYSTAL OSCILLATOR (P/N 500-06672),
WENZEL 5× MULTIPLIER (P/N LNOM-100-5-13-14-F-A), AND A
WENZEL 2× MULTIPLIER (P/N LNDD-500-14-14-1-D).
CLOCK SOURCE
ADCLK854
Figure 12. Absolute Phase Noise LVDS @ 1000 MHz
300
0
50
100
150
200
250
25 50 75 100 125 150 175 225200 250
CURRENT (mA)
FREQUENCY (MHz)
07218-113
ALL BANKS CMOS
2 BANKS CMOS
1 BANK LVDS
1 BANK CMOS
2 BANKS LVDS
ALL BANKS LVDS
Figure 13. LVDS/CMOS Current vs. Frequency with Various Logic
Combinations
55
45
46
47
48
49
50
51
52
53
54
0 50 100 150 200 250
DUTY CYCLE (%)
FREQUENCY (MHz)
07218-014
Figure 14. CMOS Output Duty Cycle vs. Frequency (10 pF Load)
ADCLK854
Rev. 0 | Page 11 of 16
CH1 300mV 1.25ns/DIV CH1 954mV
1
0
7218-015
CH1 300mV 5.0ns/DIV CH1 954mV
1
0
7218-018
Figure 15. CMOS Output Waveform @ 200 MHz (10 pF Load) Figure 18. CMOS Output Waveform @ 50 MHz (10 pF Load)
1.9
1.8
1.7
1.6
1.5
1.4
1.3
1.2
1.1
50 100 150 200 250
OUTPUT SWING (V)
FREQUENCY (MHz)
25°C
85°C
07218-016
1.8
1.4
1.5
1.6
1.7
0220015010050
OUTPUT SWING (V)
FREQUENCY (MHz)
50
RLOAD = 1kΩ
RLOAD = 750Ω
RLOAD = 500Ω
RLOAD = 300Ω
07218-019
Figure 16. CMOS Output Swing vs. Frequency by Temperature (10 pF Load) Figure 19. CMOS Output Swing vs. Frequency by Resistive Load
2.0
1.9
1.8
1.7
1.6
1.5
1.4
1.3
1.2
1.1
1.0
0 50 100 150 200 250
CL = 5pF
CL = 10pF
CL = 20pF
OUTPUT SWING (V)
FREQUENCY (MHz)
07218-017
Figure 17. CMOS Output Swing vs. Frequency by Capacitive Load
ADCLK854
Rev. 0 | Page 12 of 16
FUNCTIONAL DESCRIPTION
The ADCLK854 accepts a clock input from one of two inputs
and distributes the selected clock to all output channels. The
outputs are grouped into three banks of four and can be set to
either LVDS or CMOS levels. This allows the selection of mul-
tiple logic configurations ranging from 12 LVDS to 24 CMOS
outputs, along with other combinations using both types of logic.
CLOCK INPUTS
The ADCLK854 differential inputs are internally self-biased.
The clock inputs have a resistor divider that sets the common-
mode level for the inputs. The complementary inputs are biased
about 30 mV lower than the true input to avoid oscillations if
the input signal stops. See Figure 20 for the equivalent input
circuit.
The inputs can be ac-coupled or dc-coupled. Table 8 displays a
guide for input logic compatibility. A single-ended input can be
accommodated by ac or dc coupling to one side of the differential
input; bypass the other input to ground with a capacitor.
Note that jitter performance degrades with low input slew rate,
as shown in Figure 11. See Figure 27 through Figure 32 for
different termination schemes.
9kΩ9.5kΩ
9kΩ10kΩ10kΩ8.5kΩ
V
S
CLKx
CLKx
GND
07218-020
Figure 20. ADCLK854 Input Stage
AC-COUPLED INPUT APPLICATIONS
The ADCLK854 offers two options for ac coupling. The first
option requires no external components (excluding the dc
blocking capacitor), it allows the user to simply couple the
reference signal onto the clock input pins. For more infor-
mation, see Figure 29.
The second option allows the use of the VREF pin to set the dc
bias level for the ADCLK854. The VREF pin can be connected to
CLKx and CLKx through resistors. This method allows lower
impedance termination of signals at the ADCLK854 (for more
information, see Figure 32). The internal bias resistors remain
in parallel with the external biasing. However, the relatively
high impedance of the internal resistors allows the external
termination to VREF to dominate. This method is also useful
when offsetting the inputs; using only the internal biasing, as
previously mentioned, is not desirable.
CLOCK OUTPUTS
Each driver consists of a differential LVDS output or two single-
ended CMOS outputs (always in phase). When the LVDS driver
is enabled, the corresponding CMOS driver is in tristate; when
the CMOS driver is enabled, the corresponding LVDS driver is
powered down and tristated. Figure 21 and Figure 22 display
the equivalent output stage.
OUTx
OUTx
3.5m
A
V
S
3.5m
A
07218-021
Figure 21. LVDS Output Simplified Equivalent Circuit
OUTA
V
S
OUTB
V
S
0
7218-022
Figure 22. CMOS Output Equivalent Circuit
Table 8. Input Logic Compatibility
Supply (V) Logic Common Mode (V) Output Swing (V) AC-Coupled DC-Coupled
3.3 CML 2.9 0.8 Yes Not allowed
2.5 CML 2.1 0.8 Yes Not allowed
1.8 CML 1.4 0.8 Yes Yes
3.3 CMOS 1.65 3.3 Not allowed Not allowed
2.5 CMOS 1.25 2.5 Not allowed Not allowed
1.8 CMOS 0.9 1.8 Yes Yes
1.5 HSTL 0.75 0.75 Yes Yes
LVDS 1.25 0.4 Yes
Yes
3.3 LVPECL 2.0 0.8 Yes Not allowed
2.5 LVPECL 1.2 0.8 Yes Yes
1.8 LVPECL 0.5 0.8 Yes Yes
ADCLK854
Rev. 0 | Page 13 of 16
CONTROL AND FUNCTION PINS
CTRL_A—Logic Select
This pin selects either CMOS (high) or LVDS (low) logic for
Output 3, Output 2, Output 1, and Output 0. This pin has an
internal 200 kΩ pull-down resistor.
CTRL_B—Logic Select
This pin selects either CMOS (high) or LVDS (low) logic for
Output 7, Output 6, Output 5, and Output 4. This pin has an
internal 200 kΩ pull-down resistor.
CTRL_C—Logic Select
This pin selects either CMOS (high) or LVDS (low) logic for
Output 11, Output 10, Output 9, and Output 8. This pin has an
internal 200 kΩ pull-down resistor.
IN_SEL—Clock Input Select
A logic low selects CLK0 and CLK0 whereas a logic high selects
CLK1 and CLK1. This pin has an internal 200 kΩ pull-down
resistor.
Sleep Mode
Sleep mode powers down the chip except for the internal band
gap. The input is active high, which puts the outputs into a
high-Z state. This pin has a 200 kΩ pull-down resistor.
POWER SUPPLY
The ADCLK854 requires a 1.8 V ± 5% power supply for VS. Best
practice recommends bypassing the power supply on the PCB
with adequate capacitance (>10 μF), and bypassing all power
pins with adequate capacitance (0.1 μF) as close to the part as
possible. The layout of the ADCLK854 evaluation board
(ADCLK854/PCBZ) provides a good layout example.
Exposed Metal Paddle
The exposed metal paddle on the ADCLK854 package is an
electrical connection as well as a thermal enhancement. For the
device to function properly, the paddle must be properly
attached to ground (GND). The ADCLK854 dissipates heat
through its exposed paddle. The PCB acts as a heat sink for the
ADCLK854. The PCB attachment must provide a good thermal
path to a larger heat dissipation area, such as the ground plane
on the PCB. This requires a grid of vias from the top layer down
to the ground plane. See Figure 23 for an example.
VIAS TO GND PLANE
07218-023
Figure 23. PCB Land for Attaching Exposed Paddle
ADCLK854
Rev. 0 | Page 14 of 16
APPLICATIONS INFORMATION
USING THE ADCLK854 OUTPUTS FOR ADC CLOCK
APPLICATIONS
Any high speed, analog-to-digital converter (ADC) is extremely
sensitive to the quality of the sampling clock provided by the
user. An ADC can be thought of as a sampling mixer, and any
noise, distortion, or timing jitter on the clock is combined with
the desired signal at the analog-to-digital output. Clock integrity
requirements scale with the analog input frequency and resolu-
tion, with higher analog input frequency applications at ≥14-bit
resolution being the most stringent. The theoretical SNR of an
ADC is limited by the ADC resolution and the jitter on the
sampling clock. Considering an ideal ADC of infinite resolution
where the step size and quantization error can be ignored, the
available SNR can be expressed approximately by
⎥
⎥
⎦
⎤
⎢
⎢
⎣
⎡
×=
J
ATf
SNR 2π
1
log20
where fA is the highest analog frequency being digitized and TJ
is the rms jitter on the sampling clock.
Figure 24 shows the required sampling clock jitter as a function
of the analog frequency and effective number of bits (ENOB).
For more information, see Application Note AN-756 and
Application Note AN-501 at www.analog.com.
f
A
FULL-SCALE SINE WAVE ANALOG FREQUENCY (MHz)
SNR (dB)
ENOB
10 1k100
30
40
50
60
70
80
90
100
110
6
8
10
12
14
16
18
T
J
= 100
f
S
200
f
S
400
f
S
1ps
2ps
10ps
SNR = 20log 1
2πf
A
T
J
07218-024
Figure 24. SNR and ENOB vs. Analog Input Frequency
Many high performance ADCs feature differential clock inputs
to simplify the task of providing the required low jitter clock on
a noisy PCB. Distributing a single-ended clock on a noisy PCB
can result in coupled noise on the sample clock. Differential
distribution has inherent common-mode rejection that can
provide superior clock performance in a noisy environment.
Consider the input requirements of the ADC (differential or
single-ended, logic level, and termination) when selecting the
best clocking/converter solution.
LVDS CLOCK DISTRIBUTION
The ADCLK854 provides clock outputs that are selectable as
either CMOS or LVDS level outputs. LVDS is a differential
output option that uses a current-mode output stage. The
nominal current is 3.5 mA, which yields 350 mV output swing
across a 100 Ω resistor. The LVDS output meets or exceeds all
ANSI/TIA/EIA-644 specifications. A recommended termination
circuit for the LVDS outputs is shown in Figure 25.
If ac coupling is necessary, place decoupling capacitors either before
or after the 100 Ω termination resistor. See Application Note
AN-586 at www.analog.com for more information on LVDS.
V
S
LVDS 100Ω
DIFFERENTIAL (COUPLED)
V
S
LVDS
100Ω
07218-025
Figure 25. LVDS Output Termination
CMOS CLOCK DISTRIBUTION
The output drivers of the ADCLK854 can be configured as
CMOS drivers. When selected as a CMOS driver, each output
becomes a pair of CMOS outputs. These outputs are 1.8 V
CMOS compatible.
When single-ended CMOS clocking is used, some of the
following guidelines apply.
Design point-to-point connections such that each driver has only
one receiver, if possible. Connecting outputs in this manner allows
for simple termination schemes and minimizes ringing due to
possible mismatched impedances on the output trace. Series termi-
nation at the source is generally required to provide transmission
line matching and/or to reduce current transients at the driver.
The value of the resistor (typically 10 Ω to 100 Ω) is dependent
on the board design and timing requirements. CMOS outputs
are also limited in terms of the capacitive load or trace length
that they can drive. Typically, trace lengths less than 3 inches are
recommended to preserve signal rise/fall times and signal integrity.
10Ω
MICROSTRIP
60.4Ω
1.0 INCH
CMOS CMOS
07218-026
Figure 26. Series Termination of CMOS Output
Termination at the far end of the PCB trace is a second option.
The CMOS outputs of the ADCLK854 do not supply enough
current to provide a full voltage swing with a low impedance
resistive, far end termination, as shown in Figure 27. The far end
termination network should match the PCB trace impedance and
provide the desired switching point. The reduced signal swing may
ADCLK854
Rev. 0 | Page 15 of 16
still meet receiver input requirements in some applications. This
can be useful when driving long trace lengths on less critical
networks.
CMOS CMOS
10Ω50Ω
100Ω
100Ω
V
S
07218-027
Figure 27. CMOS Output with Far End Termination
Because of the limitations of single-ended CMOS clocking,
consider using differential outputs when driving high speed
signals over long traces. The ADCLK854 offers LVDS outputs
that are better suited for driving long traces wherein the inherent
noise immunity of differential signaling provides superior
performance for clocking converters.
INPUT TERMINATION OPTIONS
For single-ended operation always bypass unused input to
GND, as shown in Figure 31.
Figure 32 illustrates the use of VREF to provide low impedance
termination into VS/2. In addition, a way to negate the 30 mV
input offset is with external resistor values; for example, using a
1.8 V CMOS with long traces to provide far end termination.
100Ω
CLK
CLK
100Ω
CLK
CLK
0
7218-028
Figure 28. Typical AC-Coupled or DC-Coupled LVDS or HSTL Configuration
(See Table 8 for More Information)
CLK
CLK
CLK
CLK
V
CC
V
CC
0
7218-029
Figure 29. Typical AC-Coupled or DC-Coupled CML Configuration
(See Table 8 for CML Coupling Limitations)
CLK
CLK
50Ω50Ω
V
CC
– 2V
CLK
CLK
50Ω50Ω
V
CC
– 2V
07218-030
Figure 30. Typical AC-Coupled or DC-Coupled PECL Configuration
(See Table 8 for LVPECL DC-Coupling Limitations)
CLK
CLK
CLK
CLK
CLK
CLK
07218-031
Figure 31. Typical 1.8 V CMOS Configurations for Short Trace Lengths
(See Table 8 for CMOS Compatibility)
CLK
CLK
V
REF
07218-032
Figure 32. Use of VREF to Provide Low Impedance Termination into VS/2
ADCLK854
Rev. 0 | Page 16 of 16
*COMPLIANT TO JEDEC STANDARDS MO-220-VKKD-2
WITH EXCEPTION TO EXPOSED PAD DIMENSION.
080508-A
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
OUTLINE DIMENSIONS
6.75
BSC SQ
7.00
BSC SQ
0.30
0.23
0.18
1
48
12
13
37
36
24
25
*2.90
2.80 SQ
2.70
0.50
0.40
0.30
0.80 MAX
0.65 TYP
5.50 REF
COPLANARITY
0.08
0.20 MIN
EXPOSED
PAD
(BOTTOM VIEW)
0.20 REF
1.00
0.85
0.80 0.05 MAX
0.02 NOM
SEATING
PLANE
12° MAX
TOP VIEW
0.60 MAX
0.60 MAX
PIN 1
INDICATOR
PIN 1
INDICATOR 0.50
BSC
Figure 33. 48-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
7 mm × 7 mm Body, Very Thin Quad
CP-48-6
Dimensions shown in millimeters
ORDERING GUIDE
Model Temperature Range Package Description Package Option
ADCLK854BCPZ 1−40°C to +85°C 48-Lead LFCSP_VQ CP-48-6
ADCLK854BCPZ-REEL71
−40°C to +85°C 48-Lead LFCSP_VQ CP-48-6
ADCLK854/PCBZ1
Evaluation Board
1 Z = RoHS Compliant Part.
©2009 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D07218-0-4/09(0)
