SCLS141E - DECEMBER 1982 - REVISED AUGUST 2003 D Wide Operating Voltage Range of 2 V to 6 V D High-Current 3-State True Outputs Can D D D D Drive Up To 15 LSTTL Loads D Eight D-Type Flip-Flops in a Single Package D Full Parallel Access for Loading Low Power Consumption, 80-A Max ICC Typical tpd = 14 ns 6-mA Output Drive at 5 V Low Input Current of 1 A Max SN54HC374 . . . FK PACKAGE (TOP VIEW) 1 20 2 19 3 18 4 17 5 16 6 15 7 14 8 13 9 12 10 11 VCC 8Q 8D 7D 7Q 6Q 6D 5D 5Q CLK 2D 2Q 3Q 3D 4D 4 3 2 1 20 19 18 5 17 6 16 7 15 8 14 9 10 11 12 13 8D 7D 7Q 6Q 6D 4Q GND CLK 5Q 5D OE 1Q 1D 2D 2Q 3Q 3D 4D 4Q GND 1D 1Q OE VCC 8Q SN54HC374 . . . J OR W PACKAGE SN74HC374 . . . DB, DW, N, NS, OR PW PACKAGE (TOP VIEW) description/ordering information These 8-bit flip-flops feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. The eight flip-flops of the 'HC374 devices are edge-triggered D-type flip-flops. On the positive transition of the clock (CLK) input, the Q outputs are set to the logic levels that were set up at the data (D) inputs. An output-enable (OE) input places the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without interface or pullup components. ORDERING INFORMATION PDIP - N SN74HC374N Tube of 25 SN74HC374DW Reel of 2000 SN74HC374DWR SOP - NS Reel of 2000 SN74HC374NSR HC374 SSOP - DB Reel of 2000 SN74HC374DBR HC374 Tube of 2000 SN74HC374PWR Reel of 250 SN74HC374PWT CDIP - J Tube of 20 SNJ54HC374J SNJ54HC374J CFP - W Tube of 85 SNJ54HC374W SNJ54HC374W LCCC - FK Tube of 55 SNJ54HC374FK TSSOP - PW -55C -55 C to 125 125C C TOP-SIDE MARKING Tube of 20 SOIC - DW -40C -40 C to 85 85C C ORDERABLE PART NUMBER PACKAGE TA SN74HC374N HC374 HC374 SNJ54HC374FK Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 2003, Texas Instruments Incorporated ! " #$%! " &$'(#! )!%* )$#!" # ! "&%##!" &% !+% !%" %," "!$%!" "!)) -!.* )$#! &#%""/ )%" ! %#%""(. #($)% !%"!/ (( &%!%"* &)$#!" #&(! ! 0 1 (( &%!%" % !%"!%) $(%"" !+%-"% !%)* (( !+% &)$#!" &)$#! &#%""/ )%" ! %#%""(. #($)% !%"!/ (( &%!%"* POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 1 SCLS141E - DECEMBER 1982 - REVISED AUGUST 2003 description/ordering information (continued) OE does not affect the internal operations of the flip-flops. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. FUNCTION TABLE (each flip-flop) INPUTS OE CLK D OUTPUT Q L H H L L L L H or L X Q0 H X X Z logic diagram (positive logic) OE CLK 1 11 C1 1D 3 1D 2 1Q To Seven Other Channels absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 7 V Input clamp current, IIK (VI < 0 or VI > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA Output clamp current, IOK (VO < 0 or VO > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 mA Package thermal impedance, JA (see Note 2): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70C/W DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58C/W N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69C/W NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60C/W PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65C to 150C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51-7. 2 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 SCLS141E - DECEMBER 1982 - REVISED AUGUST 2003 recommended operating conditions (see Note 3) SN54HC374 VCC VIH Supply voltage VCC = 2 V VCC = 4.5 V High-level input voltage VCC = 6 V VCC = 2 V VIL VI VO t/v MIN NOM MAX 2 5 6 Input voltage MAX 2 5 6 3.15 3.15 4.2 4.2 0 VCC = 6 V UNIT V V 0.5 0.5 1.35 1.35 1.8 1.8 VCC VCC VCC = 2 V VCC = 4.5 V Input transition rise/fall time NOM 1.5 0 Output voltage MIN 1.5 VCC = 4.5 V VCC = 6 V Low-level input voltage SN74HC374 0 VCC VCC 0 1000 1000 500 500 400 400 V V V ns TA Operating free-air temperature -55 125 -40 85 C NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VOH VOL TEST CONDITIONS VI = VCC or 0, MIN MAX SN74HC374 MIN MAX UNIT 1.9 1.998 1.9 1.9 IOH = -20 A 4.4 4.499 4.4 4.4 6V 5.9 5.999 5.9 5.9 IOH = -6 mA IOH = -7.8 mA 4.5 V 3.98 4.3 3.7 3.84 6V 5.48 5.8 5.2 5.34 2V 0.002 0.1 0.1 0.1 IOL = 20 A 4.5 V 0.001 0.1 0.1 0.1 6V 0.001 0.1 0.1 0.1 4.5 V 0.17 0.26 0.4 0.33 6V 0.15 0.26 0.4 0.33 6V 0.1 100 1000 1000 nA 6V 0.01 0.5 10 5 A 8 160 80 A 10 10 10 pF IOL = 6 mA IOL = 7.8 mA ICC Ci SN54HC374 2V VI = VIH or VIL VI = VCC or 0 VO = VCC or 0 TA = 25C MIN TYP MAX 4.5 V VI = VIH or VIL II IOZ VCC IO = 0 6V 2 V to 6 V POST OFFICE BOX 655303 3 * DALLAS, TEXAS 75265 V V 3 SCLS141E - DECEMBER 1982 - REVISED AUGUST 2003 timing requirements over recommended operating free-air temperature range (unless otherwise noted) VCC fclock Clock frequency tw Pulse duration, CLK high or low tsu Setup time, data before CLK th Hold time, data after CLK CLK TA = 25C MIN MAX SN54HC374 MIN MAX SN74HC374 MIN MAX 2V 6 4 5 4.5 V 30 20 24 6V 35 24 28 2V 80 120 100 4.5 V 16 24 20 6V 14 20 17 2V 100 150 125 4.5 V 20 30 25 6V 17 25 21 2V 10 13 12 4.5 V 5 5 5 6V 5 5 5 UNIT MHz ns ns ns switching characteristics over recommended operating free-air temperature range, CL = 50 pF (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) fmax tpd ten tdis tt 4 CLK OE OE Any Q Any Q Any Q Any Q VCC TA = 25C MIN TYP MAX SN54HC374 MIN MAX SN74HC374 MIN 2V 6 12 4 5 4.5 V 30 60 20 24 6V 35 70 24 28 MAX MHz 2V 63 180 270 225 4.5 V 17 36 54 45 6V 15 31 46 38 2V 60 150 225 190 4.5 V 16 30 45 38 6V 14 26 38 32 2V 36 150 225 190 4.5 V 17 30 45 38 6V 16 26 38 32 2V 28 60 90 75 4.5 V 8 12 18 15 6V 6 10 15 13 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 UNIT ns ns ns ns SCLS141E - DECEMBER 1982 - REVISED AUGUST 2003 switching characteristics over recommended operating free-air temperature range, CL = 150 pF (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) fmax tpd ten tt CLK OE Any Q Any Q Any Q VCC MIN TA = 25C TYP MAX SN54HC374 MIN MAX SN74HC374 MIN 2V 6 12 5 4.5 V 30 60 24 6V 35 70 28 MAX UNIT MHz 2V 80 230 345 290 4.5 V 22 46 69 58 6V 19 39 58 49 2V 70 200 300 250 4.5 V 25 40 60 50 6V 22 34 51 43 2V 45 210 315 265 4.5 V 17 42 63 53 6V 13 36 53 45 ns ns ns operating characteristics, TA = 25C PARAMETER Cpd Power dissipation capacitance per flip-flop POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 TEST CONDITIONS TYP UNIT No load 100 pF 5 SCLS141E - DECEMBER 1982 - REVISED AUGUST 2003 PARAMETER MEASUREMENT INFORMATION VCC From Output Under Test CL (see Note A) PARAMETER tPZH S1 Test Point RL ten RL tdis S2 tPZL tPHZ tPLZ 1 k 1 k Reference Input VCC 50% Data Input VCC 50% 10% 50% VCC 0V In-Phase Output 50% 10% tPHL 90% 90% tr tPHL Out-ofPhase Output 90% tf Open Closed Closed Open Open Open VCC th 90% 90% VCC 50% 10% 0 V tf 50% 10% Output Control (Low-Level Enabling) VCC 50% 50% 0V tPZL VOH 50% 10% V OL tf Output Waveform 1 (See Note B) tPLZ 90% VOH VOL Output Waveform 2 (See Note B) VCC VCC 50% 10% tPZH tPLH 50% 10% Open VOLTAGE WAVEFORMS SETUP AND HOLD AND INPUT RISE AND FALL TIMES 50% tPLH Closed tr VOLTAGE WAVEFORMS PULSE DURATIONS 50% Closed 0V 0V Input Open tsu 0V 50% 50 pF or 150 pF 50% 50% tw Low-Level Pulse S2 50 pF or 150 pF LOAD CIRCUIT High-Level Pulse S1 50 pF -- tpd or tt CL VOL tPHZ 50% 90% VOH 0 V tr VOLTAGE WAVEFORMS PROPAGATION DELAY AND OUTPUT TRANSITION TIMES VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES FOR 3-STATE OUTPUTS NOTES: A. CL includes probe and test-fixture capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following characteristics: PRR 1 MHz, ZO = 50 , tr = 6 ns, tf = 6 ns. D. For clock inputs, fmax is measured when the input duty cycle is 50%. E. The outputs are measured one at a time with one input transition per measurement. F. tPLZ and tPHZ are the same as tdis. G. tPZL and tPZH are the same as ten. H. tPLH and tPHL are the same as tpd. Figure 1. Load Circuit and Voltage Waveforms 6 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 PACKAGE OPTION ADDENDUM www.ti.com 29-Aug-2012 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp ACTIVE CDIP J 20 1 TBD A42 N / A for Pkg Type 5962-8407101VSA ACTIVE CFP W 20 1 TBD Call TI N / A for Pkg Type 84071012A ACTIVE LCCC FK 20 1 TBD Call TI Call TI 8407101RA ACTIVE CDIP J 20 1 TBD Call TI Call TI 8407101SA ACTIVE CFP W 20 1 TBD Call TI Call TI JM38510/65602BRA ACTIVE CDIP J 20 1 TBD A42 N / A for Pkg Type M38510/65602BRA ACTIVE CDIP J 20 1 TBD A42 N / A for Pkg Type A42 N / A for Pkg Type SN54HC374J ACTIVE CDIP J 20 1 TBD SN74HC374DBR ACTIVE SSOP DB 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74HC374DBRE4 ACTIVE SSOP DB 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74HC374DBRG4 ACTIVE SSOP DB 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74HC374DW ACTIVE SOIC DW 20 25 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74HC374DWE4 ACTIVE SOIC DW 20 25 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74HC374DWG4 ACTIVE SOIC DW 20 25 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74HC374DWR ACTIVE SOIC DW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74HC374DWRE4 ACTIVE SOIC DW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74HC374DWRG4 ACTIVE SOIC DW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 20 Pb-Free (RoHS) SN74HC374N ACTIVE PDIP N 20 OBSOLETE PDIP N 20 SN74HC374NE4 ACTIVE PDIP N 20 20 Pb-Free (RoHS) SN74HC374NSR ACTIVE SO NS 20 2000 Green (RoHS & no Sb/Br) TBD Addendum-Page 1 CU NIPDAU N / A for Pkg Type Call TI Samples (Requires Login) 5962-8407101VRA SN74HC374N3 (3) Call TI CU NIPDAU N / A for Pkg Type CU NIPDAU Level-1-260C-UNLIM PACKAGE OPTION ADDENDUM www.ti.com Orderable Device 29-Aug-2012 Status (1) Package Type Package Drawing Pins Package Qty 2000 Eco Plan (2) Green (RoHS & no Sb/Br) Lead/ Ball Finish MSL Peak Temp Samples (Requires Login) SN74HC374NSRG4 ACTIVE SO NS 20 SN74HC374PWLE OBSOLETE TSSOP PW 20 SN74HC374PWR ACTIVE TSSOP PW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74HC374PWRE4 ACTIVE TSSOP PW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74HC374PWRG4 ACTIVE TSSOP PW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74HC374PWT ACTIVE TSSOP PW 20 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74HC374PWTE4 ACTIVE TSSOP PW 20 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74HC374PWTG4 ACTIVE TSSOP PW 20 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SNJ54HC374FK ACTIVE LCCC FK 20 1 TBD SNJ54HC374J ACTIVE CDIP J 20 1 TBD A42 N / A for Pkg Type SNJ54HC374W ACTIVE CFP W 20 1 TBD Call TI N / A for Pkg Type TBD (3) CU NIPDAU Level-1-260C-UNLIM Call TI Call TI POST-PLATE N / A for Pkg Type (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Addendum-Page 2 PACKAGE OPTION ADDENDUM www.ti.com 29-Aug-2012 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF SN54HC374, SN54HC374-SP, SN74HC374 : * Catalog: SN74HC374, SN54HC374 * Military: SN54HC374 * Space: SN54HC374-SP NOTE: Qualified Version Definitions: * Catalog - TI's standard catalog product * Military - QML certified for Military and Defense Applications * Space - Radiation tolerant, ceramic packaging and qualified for use in Space-based application Addendum-Page 3 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant SN74HC374DBR SSOP DB 20 2000 330.0 16.4 8.2 7.5 2.5 12.0 16.0 Q1 SN74HC374DWR SOIC DW 20 2000 330.0 24.4 10.8 13.1 2.65 12.0 24.0 Q1 SN74HC374DWR SOIC DW 20 2000 330.0 24.4 10.8 13.0 2.7 12.0 24.0 Q1 SN74HC374NSR SO NS 20 2000 330.0 24.4 8.2 13.0 2.5 12.0 24.0 Q1 SN74HC374PWR TSSOP PW 20 2000 330.0 16.4 6.95 7.1 1.6 8.0 16.0 Q1 SN74HC374PWT TSSOP PW 20 250 330.0 16.4 6.95 7.1 1.6 8.0 16.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74HC374DBR SSOP DB 20 2000 367.0 367.0 38.0 SN74HC374DWR SOIC DW 20 2000 367.0 367.0 45.0 SN74HC374DWR SOIC DW 20 2000 367.0 367.0 45.0 SN74HC374NSR SO NS 20 2000 367.0 367.0 45.0 SN74HC374PWR TSSOP PW 20 2000 367.0 367.0 38.0 SN74HC374PWT TSSOP PW 20 250 367.0 367.0 38.0 Pack Materials-Page 2 MECHANICAL DATA MSSO002E - JANUARY 1995 - REVISED DECEMBER 2001 DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE 28 PINS SHOWN 0,38 0,22 0,65 28 0,15 M 15 0,25 0,09 8,20 7,40 5,60 5,00 Gage Plane 1 14 0,25 A 0-8 0,95 0,55 Seating Plane 2,00 MAX 0,10 0,05 MIN PINS ** 14 16 20 24 28 30 38 A MAX 6,50 6,50 7,50 8,50 10,50 10,50 12,90 A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12,30 DIM 4040065 /E 12/01 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0,15. Falls within JEDEC MO-150 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All semiconductor products (also referred to herein as "components") are sold subject to TI's terms and conditions of sale supplied at the time of order acknowledgment. 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