© 2000 Fairchild Semiconductor Corporation DS009935 www.fairchildsemi.com
November 1988
Revised October 2000
74AC174 • 74ACT174 Hex D-Type Flip-Flop with Master Reset
74AC174 • 74ACT174
Hex D-Type Flip-Flop with Master Reset
General Description
The AC/ACT174 is a high-speed hex D-type flip-flop. The
device is used primarily as a 6-bit edge-triggered storage
register. The information on the D inputs is transferred to
storage during the LOW-to-HIGH clock transition. The
device ha s a Master Reset t o simultaneously clea r all flip-
flops.
Features
■ICC reduced by 50%
■Outputs source/sink 24 mA
■ACT174 has TTL-compatible inputs
Ordering Code:
Device a ls o av ailable in Tape and Reel. Specify by a ppending s uffix let te r “X” to the or dering co de.
Logic Symbols
IEEE/IEC
Connection Diagram
Pin Descriptions
FACT is a trademark of Fairchild Semiconductor Corporation.
Order Number Package Number Package Description
74AC174SC M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
74AC174SJ M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74AC174MTC MTC16 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74AC174PC N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
74ACT174SC M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
74ACT174SJ M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74ACT174MTC MTC16 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74ACT174PC N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Pin Names Description
D0–D5Data Inputs
CP Clock Pulse Input
MR Master Reset Input
Q0–Q5Outputs
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74AC174 • 74ACT174
Functional Description
The AC/ ACT174 consi sts of six edge-t riggered D-t ype flip-
flops with individual D inputs and Q outputs. The Clock
(CP) and Master Reset (MR) are common to all flip-flops.
Each D input’s state is transferred to the corresponding flip-
flop’s output following th e L OW-to-HIGH Clock ( CP) transi-
tion. A LOW input to the Master Reset (MR) will force all
outputs LOW independent of Clock or Data inputs. The AC/
ACT174 is useful for applications where the true output
only is r equired an d the Clock a nd Master Reset are com-
mon to all storage elements.
Truth Table
H = HIGH Voltage Lev el
L = LOW Voltage Level
= LOW-to-HIGH Transition
X = Immaterial
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
Inputs Output
MR CP D Q
LX X L
H
HH
H
LL
HL X Q
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74AC174 • 74ACT174
Absolute Maximum Ratings(Note 1) Recommended Operating
Conditions
Note 1: Absol ut e ma x i mu m rat ings are thos e v alue s beyond wh ich damage
to the dev ice may occ ur. The databoo k specific ations sh ould be m et, with-
out exc eption, to e nsure that the system des ign is reliable over its power
supply, temperature, and output/input loading variables. Fairchild does not
recommend operation of FACT circuits outside da t abook spe c if ic at ions.
DC Electrical Characteristics for AC
Note 2: All outputs lo aded; thre sholds on input as s oc iated with outpu t un der test.
Note 3: Maximum test duration 2.0 ms, one output loaded at a time.
Note 4: IIN and ICC @ 3.0V are gu aranteed to be less t han or equa l t o th e respectiv e limit @ 5.5V VCC.
Supply Voltage (VCC)−0.5V to +7.0V
DC Input Diode Current (IIK)
VI = −0.5V −20 mA
VI = VCC + 0.5V +20 mA
DC Input Voltage (VI)−0.5V to VCC + 0.5V
DC Output Diode Current (IOK)
VO = −0.5V −20 mA
V = VCC + 0.5V +20 mA
DC Output Voltage (VO)−0.5V to V CC + 0.5V
DC Output So urce
or Sink Current (IO) ±50 mA
DC VCC or Ground Current
per Output Pin (ICC or IGND)±50 mA
Storage Temperature (TSTG)−65°C to +150°C
Junction Temp erature (T J)
PDIP 140°C
Supply Voltage (VCC)
AC 2.0V to 6.0V
ACT 4.5V to 5.5V
Input Voltage (VI)0V to V
CC
Output Voltage (VO)0V to V
CC
Operating Temperature (TA)−40°C to +85°C
Minimum Input Edge Rate (∆V/∆t)
AC Devices
VIN from 30% to 70% of VCC
VCC @ 3.3V, 4.5V, 5.5V 125 mV/ns
Minimum Input Edge Rate (∆V/∆t)
ACT Devices
VIN from 0.8V to 2.0V
VCC @ 4.5V, 5.5V 125 mV/ns
Symbol Parameter VCC TA = +25°C TA = −40°C to +85°CUnits Conditions
(V) Typ Guaranteed Limits
VIH Minimum HIGH Level 3.0 1.5 2.1 2.1 VOUT = 0.1V
Input Voltage 4.5 2.25 3.15 3.15 V or VCC − 0.1V
5.5 2.75 3.85 3.85
VIL Maximum LOW Level 3.0 1.5 0.9 0.9 VOUT = 0.1V
Input Voltage 4.5 2.25 1.35 1.35 V or VCC − 0.1V
5.5 2.75 1.65 1.65
VOH Minimum HIGH Level 3.0 2.99 2.9 2.9
Output Voltage 4.5 4.49 4.4 4.4 V IOUT = −50 µA
5.5 5.49 5.4 5.4 VIN = VIL or VIH
3.0 2.56 2.46 IOH = −12 mA
4.5 3.86 3.76 V IOH = −24 mA
5.5 4.86 4.76 IOH = −24 mA (Note 2)
VOL Maximum LOW Level 3.0 0.002 0.1 0.1
Output Voltage 4.5 0.001 0.1 0.1 V IOUT = 50 µA
5.5 0.001 0.1 0.1 VIN = VIL or VIH
3.0 0.36 0.44 IOL = 12 mA
4.5 0.36 0.44 V IOL = 24 mA
5.5 0.36 0.44 IOL = 24 mA (Note 2)
IIN Maximum Input 5.5 ±0.1 ±1.0 µAVI = VCC
(Note 4) Leakage Current or GND
IOLD Minimum Dynamic 5.5 75 mA VOLD = 1.65V Max
IOHD Output Current (Note 3) 5.5 −75 mA VOHD = 3.85V Min
ICC Maximum Quiescent 5.5 4.0 40.0 µAVIN = VCC
(Note 4) Supply Current or GND
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74AC174 • 74ACT174
DC Electrical Characteristics for ACT
Note 5: All outputs loaded; th resholds on input associate d w it h output under tes t.
Note 6: Maximum test du ration 2.0 m s, one out put loaded a t a tim e.
AC Electrical Characteristics for AC
Note 7: Voltage Range 3.3 is 3.3V ± 0.3V
Voltage Range 5. 0 is 5. 0V ± 0.5V
Symbol Parameter VCC TA = +25°CT
A = −40°C to +85°CUnits Conditions
(V) T yp Guarant eed Lim its
VIH Minimum HIGH Level 4.5 1.5 2.0 2.0 VVOUT = 0.1V
Input Voltage 5.5 1.5 2.0 2.0 or VCC − 0.1V
VIL Maximum LOW Level 4.5 1.5 0.8 0.8 VVOUT = 0.1V
Input V oltag e 5.5 1.5 0.8 0.8 or VCC − 0.1V
VOH Minimum HIGH Level 4.5 4.49 4.4 4.4 VI
OUT = −50 µA
Output Voltage 5.5 5.49 5.4 5.4 VIN = VIL or VIH
4.5 3.86 3.76 V IOH = −24 mA
5.5 4.86 4.76 IOH = −24 mA (Note 5)
VOL Maximum LOW Level 4.5 0.001 0.1 0.1 VI
OUT = 50 µA
Output Voltage 5.5 0.001 0.1 0.1 VIN = VIL or VIH
4.5 0.36 0.44 V IOL = 24 mA
5.5 0.36 0.44 IOL = 24 mA (Note 5)
IIN Maximum Input 5.5 ±0.1 ±1.0 µAV
I = VCC, GND
Leakage Current
ICCT Maximum 5.5 0.6 1.5 mA VI = VCC − 2.1V
ICC/Input
IOLD Minimum Dynamic 5.5 75 mA VOLD = 1.65V Max
IOHD Output Current (Note 6) 5.5 −75 mA VOHD = 3.85V Min
ICC Maximum Quiescent 5.5 4.0 40.0 µAVIN = VCC
Supply Current or GND
Symbol Parameter VCC
(V)
(Note 7)
TA = +25°C
CL = 50 pF TA = −40°C to +85°C
CL = 50 pF Units
Min Typ Max Min M ax
fMAX Maximum Clock 3.3 90 100 70 MHz
Frequency 5.0 100 125 100
tPLH Propagation Delay 3.3 2.0 9.0 11.5 1.5 12.5 ns
CP to Qn5.0 1.5 6.0 8.5 1.0 9.5
tPHL Propagation Delay 3.3 2.0 8.5 11.0 1.5 12.0 ns
CP to Qn5.0 1.5 6.0 8.0 1.0 9.0
tPHL Propagation Delay 3.3 2.5 9.0 11.5 2.0 12.5 ns
MR to Qn5.0 1.5 7.0 9.0 1.5 10.5
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74AC174 • 74ACT174
AC Operating Requirements for AC
Note 8: Vo lt age Range 3.3 is 3.3V ± 0.3V
Voltage Range 5. 0 is 5. 0V ± 0.5V
AC Electrical Characteristics for ACT
Note 9: Vo lt age Range 5.0 is 5.0V ± 0.5V
AC Operating Requirements for ACT
Note 10: Voltage Range 5. 0 is 5.0V ± 0.5V
Capacitance
Symbol Parameter VCC
(V)
(Note 8)
TA = +25°C
CL = 50 pF TA = −40°C to +85°C
CL = 50 pF Units
Typ Guaranteed Minimum
tSSetup Time, HIGH or LOW 3.3 2.5 6.5 7.0 ns
Dn to CP 5.0 2.0 5.0 5.5
tHHold Time, HIGH or LOW 3.3 1.0 3.0 3.0 ns
Dn to CP 5.0 0.5 3.0 3.0
tWMR Pulse Width, LOW 3.3 1.0 5.5 7.0 ns
5.0 1.0 5.0 5.0
tWCP Pulse Width 3.3 1.0 5.5 7.0 ns
5.0 1.0 5.0 5.0
tREC Recovery Time 3.3 0 2.5 2.5 ns
MR to CP 5.0 0 2.0 2.0
Symbol Param eter VCC
(V)
(Note 9)
TA = +25°C
CL = 50 pF TA = −40°C to +85°C
CL = 50 pF Units
Min Typ Max Min Max
fMAX Maximum Clock 5.0 165 200 140 MHz
Frequency
tPLH Propagation Delay 5.0 1.5 7.0 10.5 1.5 11.5 ns
CP to Qn
tPHL Propagation Delay 5.0 1.5 7.0 10.5 1.5 11.5 ns
CP to Qn
tPHL Propagation Delay 5.0 1.5 6.5 9.5 1.5 11.0 ns
MR to Qn
Symbol Parameter VCC
(V)
(Note 10)
TA = +25°C
CL = 50 pF TA = −40°C to +85°C
CL = 50 pF Units
Typ Guaranteed Minimum
tSSetup Time, HIGH or LOW 5.0 0.5 1.5 1.5 ns
Dn to CP
tHHold Time, HIGH or LOW 5.0 1.0 2.0 2.0 ns
Dn to CP
tWMR Pulse Width, LOW 5.0 1.5 3.0 3.5 ns
tWCP Pulse Width, HIGH or LOW 5.0 1.5 3.0 3.5 ns
trec Recovery Time 5.0 −1.0 0.5 0.5 ns
MR to CP
Symbol Parameter Typ Units Conditions
CIN Input Capacitance 4.5 pF VCC = OPEN
CPD Power Dissipation Capacitance 85.0 pF VCC = 5.0V
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74AC174 • 74ACT174
Physical Dimensions inches (millimeters) unless otherwise noted
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
Package Number M16A
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74AC174 • 74ACT174
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M16D
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74AC174 • 74ACT174
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package Number MTC16
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74AC174 • 74ACT174 Hex D-Type Flip-Flop with Master Reset
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Package Number N16E
Fairchild does not assume an y responsibility for u se of any circuitry descr ibed, no circuit pat ent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life suppor t de vices o r syst ems are dev ic es or syste ms
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instruct ions fo r use pr ovi de d in the l abe ling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A crit ical componen t in any com ponen t of a life s uppor t
device or system whose failure to perform can be rea-
sonabl y e xpec ted to cause th e fa i lure of the l ife s upport
device or system, or to affect its safety or effectiveness.
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