AVAILABLE
Functional Diagrams
Pin Configurations appear at end of data sheet.
Functional Diagrams continued at end of data sheet.
UCSP is a trademark of Maxim Integrated Products, Inc.
For pricing, delivery, and ordering information, please contact Maxim Direct
at 1-888-629-4642, or visit Maxim’s website at www.maximintegrated.com.
19-4652; 7/09
DS1337
GENERAL DESCRIPTION
The DS1337 serial real-time clock is a low-power
clock/calendar with two programmable time-of-day
alarms and a programmable square-wave output.
Address and data are transferred serially through an
I2C bus. The clock/calendar provides seconds,
minutes, hours, day, date, month, and year
information. The date at the end of the month is
automatically adjusted for months with fewer than 31
days, including corrections for leap year. The clock
operates in either the 24-hour or 12-hour format with
AM/PM indicator.
The device is fully accessible through the serial
interface while VCC is between 1.8V and 5.5V. I2C
operation is not guaranteed below 1.8V.
Timekeeping operation is maintained with VCC as low
as 1.3V.
APPLICATIONS
Handhelds (GPS, POS Terminal, MP3 Player)
Consumer Electronics (Set-Top Box, VCR/Digital
Recording)
Office Equipment (Fax/Printer, Copier)
Medical (Glucometer, Medicine Dispenser)
Telecommunications (Router, Switch, Server)
Other (Utility Meter, Vending Machine, Thermostat,
Modem)
TYPICAL OPERATING CIRCUIT
FEATURES
Real-Time Clock (RTC) Counts Seconds,
Minutes, Hours, Day, Date, Month, and Year
with Leap-Year Compensation Valid Up to
2100
Available in a Surface-Mount Package with an
Integrated Crystal (DS1337C)
I2C Serial Interface
Two Time-of-Day Alarms
Oscillator Stop Flag
Programmable Square-Wave Output
Defaults to 32kHz on Power-Up
Available in 8-Pin DIP, SO, or SOP
-40C to +85C Operating Temperature Range
ORDERING INFORMATION
PART TEMP RANGE PIN-PACKAGE TOP
MARK†
DS1337+ -40°C to +85°C 8 DIP (300 mils) DS1337
DS1337S+ -40°C to +85°C 8 SO (150 mils) DS1337
DS1337U+ -40°C to +85°C 8 SOP 1337
DS1337C# -40°C to +85°C 16 SO (300 mils) DS1337C
+ Denotes a lead(Pb)-free/RoHS-compliant device.
# Denotes a RoHS-compliant device that may include lead that is
exempt under the RoHS requirements. The lead finish is JESD97
category e3, and is compatible with both lead-based and lead-free
soldering processes.
† A “+” anywhere on the top mark denotes a lead-free device. A
“#” denotes a RoHS-compliant device.
Pin Configurations appear at end of data sheet.
I2C Serial Real-Time Clock
www.maxim-ic.com
DS1337 I2C Serial Real-Time Clock
ABSOLUTE MAXIMUM RATINGS
Voltage Range on Any Pin Relative to Ground…………………………………………………………...…-0.3V to +6.0V
Operating Temperature Range (Noncondensing)………………………………………………………….-40°C to +85°C
Storage Temperature Range………………………………………………………………………………..-55°C to +125°C
Soldering Temperature…………………………………………………………See IPC/JEDEC J-STD-020 Specification
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only,
and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is
not implied. Exposure to the absolute maximum rating conditions for extended periods may affect device reliability.
RECOMMENDED DC OPERATING CONDITIONS
(TA = -40°C to +85°C)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
VCC Full operation 1.8 3.3 5.5 V
VCC Supply Voltage VCCT Timekeeping (Note
5) 1.3 1.8 V
SCL, SDA 0.7 x VCC V
CC + 0.3
Logic 1 VIH INTA, SQW/INTB
5.5
V
Logic 0 VIL -0.3 +0.3 x VCC V
DC ELECTRICAL CHARACTERISTICS—Full Operation
(VCC = 1.8V to 5.5V, TA = -40°C to +85°C.) (Note 1)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Input Leakage ILI (Note 2) -1 +1 A
I/O Leakage ILO (Note 3) -1 +1 A
Logic 0 Output (VOL = 0.4V) IOL (Note 3) 3 mA
Active Supply Current ICCA (Note 4) 150 A
Standby Current ICCS (Notes 5, 6) 1.5 A
DC ELECTRICAL CHARACTERISTICS--Timekeeping
(VCC = 1.3V to 1.8V, TA = -40°C to +85°C.) (Note 1)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Timekeeping Current
(Oscillator Enabled) ICCTOSC (Notes 5, 7, 8, 9) 425 600 nA
Data-Retention Current
(Oscillator Disabled) ICCTDDR (Notes 5, 9) 100 nA
DS1337 I2C Serial Real-Time Clock
AC ELECTRICAL CHARACTERISTICS
(VCC = 1.8V to 5.5V, TA = -40°C to +85°C.) (Note 1)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Fast mode 100 400
SCL Clock Frequency fSCL Standard mode 0 100 kHz
Fast mode 1.3
Bus Free Time Between a
STOP and START Condition tBUF Standard mode 4.7 s
Fast mode 0.6
Hold Time (Repeated)
START Condition (Note 10) tHD:STA Standard mode 4.0 s
Fast mode 1.3
LOW Period of SCL Clock tLOW Standard mode 4.7 s
Fast mode 0.6
HIGH Period of SCL Clock tHIGH Standard mode 4.0 s
Fast mode 0.6
Setup Time for a Repeated
START Condition tSU:STA Standard mode 4.7 s
Fast mode 0 0.9 Data Hold Time
(Notes 11, 12) tHD:DAT Standard mode 0 s
Fast mode 100
Data Setup Time (Note 13) tSU:DAT Standard mode 250 ns
Fast mode 20 + 0.1CB 300
Rise Time of Both SDA and
SCL Signals (Note 14) tR Standard mode 20 + 0.1CB 1000
ns
Fast mode 20 + 0.1CB 300
Fall Time of Both SDA and
SCL Signals (Note 14) tF Standard mode 20 + 0.1CB 300 ns
Fast mode 0.6
Setup Time for STOP
Condition tSU:STO Standard mode 4.0 s
Capacitive Load for Each Bus
Line CB (Note 14) 400 pF
I/O Capacitance (SDA, SCL) CI/O (Note 15) 10 pF
Oscillator Stop Flag (OSF)
Delay tOSF 100 ms
Note 1: Limits at -40°C are guaranteed by design and are not production tested.
Note 2: SCL only.
Note 3: SDA, INTA, and SQW/INTB.
Note 4: ICCA—SCL clocking at max frequency = 400kHz, VIL = 0.0V, VIH = VCC.
Note 5: Specified with the I2C bus inactive, VIL = 0.0V, VIH = VCC.
Note 6: SQW enabled.
Note 7: Specified with the SQW function disabled by setting INTCN = 1.
Note 8: Using recommended crystal on X1 and X2.
Note 9: The device is fully accessible when 1.8 VCC 5.5V. Time and date are maintained when 1.3V VCC 1.8V.
Note 10: After this period, the first clock pulse is generated
Note 11: A device must internally provide a hold time of at least 300ns for the SDA signal (referred to the VIHMIN of the SCL signal) to
bridge the undefined region of the falling edge of SCL.
Note 12: The maximum tHD:DAT need only be met if the device does not stretch the LOW period (tLOW) of the SCL signal.
Note 13: A fast-mode device can be used in a standard-mode system, but the requirement tSU:DAT to 250ns must then be met. This is
automatically the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW
period of the SCL signal, it must output the next data bit to the SDA line tR max + tSU:DAT = 1000 + 250 = 1250ns before the SCL
line is released.
Note 14: CB—total capacitance of one bus line in pF.
Note 15: Guaranteed by design. Not production tested.
DS1337 I2C Serial Real-Time Clock
Note 16: The parameter tOSF is the period of time that the oscillator must be stopped for the OSF bit to be set over the
voltage range of VCC(MIN) ≤ VCC ≤ VCC(MAX)..
TYPICAL OPERATING CHARACTERISTICS
(VCC = 3.3V, TA = +25°C, unless otherwise noted.)
ICCA vs. VCC
0
25
50
75
100
125
1.8 2.3 2.8 3.3 3.8 4.3 4.8 5.3
VCC (V)
ICC (uA)
ICC vs. VCC
300
400
500
600
700
800
900
1000
1.3 1.8 2.3 2.8 3.3 3.8 4.3 4.8 5.3
VCC (V)
ICC (nA)
INTCN = 0
(Squarew ave on)
INTCN = 1
(Squarew ave of f )
ICCTOSC ICCS
ICCS vs. Temperat ure
350
400
450
500
550
600
650
700
-40.0 -20.0 0.0 20.0 40.0 60.0 80.0
VCC (V )
ICC (nA)
INTCN = 0
(Squarew ave on)
VCC = 3.0V
INTCN = 1
(Squarew ave off )
OSCILLATOR FREQUENCY vs. VCC
32768
32768.05
32768.1
32768.15
32768.2
32768.25
32768.3
32768.35
1.3 1.8 2.3 2.8 3.3 3.8 4.3 4.8
VCC (V)
FREQUENCY (Hz)
DS1337 I2C Serial Real-Time Clock
PIN DESCRIPTION
PIN
8 16 NAME FUNCTION
1 — X1
2 — X2
Connections for a Standard 32.768kHz Quartz Crystal. The internal
oscillator circuitry is designed for operation with a crystal having a specified
load capacitance (CL) of 6pF. For more information about crystal selection
and crystal layout considerations, refer to Application Note 58: Crystal
Considerations with Dalla s Real-Time Clocks. An external 32.768kHz
oscillator can also drive the DS1337. In this configuration, the X1 pin is
connected to the external oscillator signal and the X2 pin is floated.
3 14
INTA
Interrupt Output. When enabled, INTA is asserted low when the
time/day/date matches the values set in the alarm registers. This pin is an
open-drain output and requires an external pullup resistor. The pull up
voltage may be up to 5.5V, regardless of the voltage on VCC. If not used, this pin
may be left floating.
4 15 GND Ground. DC power is provided to the device on this pin.
5 16 SDA
Serial Data Input/Output. SDA is the input/output pin for the I2C serial
interface. The SDA pin is open-drain output and requires an external pullup
resistor.
6 1 SCL
Serial Clock Input. SCL is used to synchronize data movement on the serial
interface.
7 2
SQW/INTB
Square-Wave/Interrupt Output. Programmable square-wave or interrupt
output signal. It is an open-drain output and requires an external pullup
resistor. The pull up voltage may be up to 5.5V, regardless of the voltage on VCC.
If not used, this pin may be left floating.
8 3 VCC DC Power. DC power is provided to the device on this pin.
— 4–13 N.C.
No Connect. These pins are not connected internally, but must be
grounded for proper operation.
TIMING DIAGRAM
DS1337 I2C Serial Real-Time Clock
BLOCK DIAGRAM
ALARM,
TRICKLE
CHARGE, AND
CONTROL
REGISTERS
SERIAL BUS
INTERFACE AND
ADDRESS
REGISTER
CONTROL
LOGIC
X1
X2
1Hz
1Hz/4.096kHz/8.192kHz/32.768kHz MUX/
BUFFER
USER BUFFER
(7 BYTES)
CLOCK AND
CALENDAR
REGISTERS
"C" version only
N
N
SDA
SCL
SQW/INTB
INTA
DS1337
C
L
C
L
DETAILED DESCRIPTION
The Block Diagram shows the main elements of the DS1337. As shown, communications to and from the DS1337
occur serially over an I2C bus. The DS1337 operates as a slave device on the serial bus. Access is obtained by
implementing a START condition and providing a device identification code, followed by data. Subsequent
registers can be accessed sequentially until a STOP condition is executed. The device is fully accessible through
the I2C interface whenever VCC is between 5.5V and 1.8V. I2C operation is not guaranteed when VCC is below 1.8V.
The DS1337 maintains the time and date when VCC is as low as 1.3V.
OSCILLATOR CIRCUIT
The DS1337 uses an external 32.768kHz crystal. The oscillator circuit does not require any external resistors or
capacitors to operate. Table 1 specifies several crystal parameters for the external crystal. The Block Diagram
shows a functional schematic of the oscillator circuit. The startup time is usually less than 1 second when using a
crystal with the specified characteristics.
Table 1. Crystal Specifications*
PARAMETER SYMBOL MIN TYP MAX UNITS
Nominal Frequency fO 32.768 kHz
Series Resistance ESR 50 k
Load Capacitance CL 6 pF
*The crystal, traces, and crystal input pins should be isolated from RF generating signals. Refer to
Application Note 58: Crystal Considerations for Dallas Real-Time Clocks for additional specifications.
DS1337 I2C Serial Real-Time Clock
CLOCK ACCURACY
The accuracy of the clock is dependent upon the accuracy of the crystal and the accuracy of the match between
the capacitive load of the oscillator circuit and the capacitive load for which the crystal was trimmed. Crystal
frequency drift caused by temperature shifts creates additional error. External circuit noise coupled into the
oscillator circuit can result in the clock running fast. Figure 1 shows a typical PC board layout for isolating the
crystal and oscillator from noise. Refer to Application Note 58: Crystal Considerations with Dallas Real-Time
Clocks for detailed information.
Figure 1. Typical PC Board Layout for Crystal
LOCAL GROUND PLANE (LAYER 2)
X1
CRYSTAL
X2
GND
NOTE:
A
VOID ROUTING SIGNALS IN THE CROSSHATCHED
AREA (UPPER LEFT-HAND QUADRANT) OF THE PACKAGE
UNLESS THERE IS A GROUND PLANE BETWEEN THE SIGNAL
LINE AND THE PACKAGE.
DS1337C ONLY
The DS1337C integrates a standard 32,768Hz crystal in the package. Typical accuracy at nominal VCC and +25°C
is approximately +10ppm. Refer to Application Note 58 for information about crystal accuracy vs. temperature.
OPERATING MODES
The amount of current consumed by the DS1337 is determined, in part, by the I2C interface and oscillator
operation. The following table shows the relationship between the operating mode and the corresponding ICC
parameter.
Operating Mode VCC Power
I2C Interface Active 1.8V ≤ VCC ≤ 5.5V ICC Active (ICCA)
I2C Interface Inactive 1.8V ≤ VCC ≤ 5.5V ICC Standby (ICCS)
I2C Interface Inactive 1.3V ≤ VCC ≤ 1.8V Timekeeping (ICCTOSC)
I2C Interface Inactive
Oscillator Disabled 1.3V ≤ VCC ≤ 1.8V
Data Retention
(ICCTDDR)
DS1337 I2C Serial Real-Time Clock
ADDRESS MAP
Table 2 shows the address map for the DS1337 registers. During a multibyte access, when the address pointer
reaches the end of the register space (0Fh) it wraps around to location 00h. On an I2C START, STOP, or address
pointer incrementing to location 00h, the current time is transferred to a second set of registers. The time
information is read from these secondary registers, while the clock may continue to run. This eliminates the need
to re-read the registers in case of an update of the main registers during a read.
Table 2. Timekeeper Registers
ADDRESS BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 FUNCTION RANGE
00H 0 10 Seconds Seconds Seconds 00–59
01H 0 10 Minutes Minutes Minutes 00–59
AM/PM
02H 0
12/24
10 Hour
10 Hour Hour Hours
1–12
+AM/PM
00–23
03H 0 0 0 0 0 Day Day 1–7
04H 0 0 10 Date Date Date 01–31
05H Century 0 0 10 Month Month Month/
Century
01–12 +
Century
06H 10 Year Year Year 00–99
07H A1M1 10 Seconds Seconds Alarm 1
Seconds 00–59
08H A1M2 10 Minutes Minutes Alarm 1
Minutes 00–59
AM/PM
09H A1M3
12/24 10 Hour 10 Hour Hour Alarm 1
Hours
1–12 +
AM/PM
00–23
Day Alarm 1
Day 1–7
0AH A1M4
DY/DT 10 Date
Date Alarm 1
Date 01–31
0BH A2M2 10 Minutes Minutes Alarm 2
Minutes 00–59
AM/PM
0CH A2M3
12/24 10 Hour 10 Hour Hour Alarm 2
Hours
1–12 +
AM/PM
00–23
Day Alarm 2
Day 1–7
0DH A2M4
DY/DT 10 Date
Date Alarm 2
Date 01–31
0EH EOSC 0 0 RS2 RS1 INTCN A2IE A1IE Control —
0FH OSF 0 0 0 0 0 A2F A1F Status —
Note: Unless otherwise specified, the state of the registers is not defined when power is first applied or VCC falls below the VOSC.
I2C INTERFACE
The I2C interface is accessible whenever VCC is at a valid level. If a microcontroller connected to the DS1337 resets
while reading from the DS1337 during an I2C read, the two could become unsynchronized. The microcontroller must
terminate the last byte read with a Not-Acknowledge (NACK) to properly terminate the read. When the microcontroller
resets, the DS1337 I2C interface may be placed into a known state by toggling SCL until SDA is observed to be at a
high level. At that point the microcontroller should pull SDA low while SCL is high, generating a START condition.
DS1337 I2C Serial Real-Time Clock
CLOCK AND CALENDAR
The time and calendar information is obtained by reading the appropriate register bytes. The RTC registers are
illustrated in Table 2. The time and calendar are set or initialized by writing the appropriate register bytes. The
contents of the time and calendar registers are in the binary-coded decimal (BCD) format.
The day-of-week register increments at midnight. Values that correspond to the day of week are user-defined but
must be sequential (i.e., if 1 equals Sunday, then 2 equals Monday, and so on.). Illogical time and date entries
result in undefined operation.
When reading or writing the time and date registers, secondary (user) buffers are used to prevent errors when the
internal registers update. When reading the time and date registers, the user buffers are synchronized to the
internal registers on any start or stop and when the register pointer rolls over to zero.
The countdown chain is reset whenever the seconds register is written. Write transfers occur on the acknowledge
pulse from the device. To avoid rollover issues, once the countdown chain is reset, the remaining time and date
registers must be written within 1 second. The 1Hz square-wave output, if enable, transitions high 500ms after the
seconds data transfer, provided the oscillator is already running.
The DS1337 can be run in either 12-hour or 24-hour mode. Bit 6 of the hours register is defined as the 12- or
24-hour mode-select bit. When high, the 12-hour mode is selected. In the 12-hour mode, bit 5 is the AM/PM bit
with logic high being PM. In the 24-hour mode, bit 5 is the second 10-hour bit (20–23 hours). All hours values,
including the alarms, must be reinitialized whenever the 12/24-hour mode bit is changed. The century bit (bit 7 of
the month register) is toggled when the years register overflows from 99–00.
ALARMS
The DS1337 contains two time-of-day/date alarms. Alarm 1 can be set by writing to registers 07h–0Ah. Alarm 2
can be set by writing to registers 0Bh–0Dh. The alarms can be programmed (by the INTCN bit of the control
register) to operate in two different modes—each alarm can drive its own separate interrupt output or both alarms
can drive a common interrupt output. Bit 7 of each of the time-of-day/date alarm registers are mask bits (Table 2).
When all of the mask bits for each alarm are logic 0, an alarm only occurs when the values in the timekeeping
registers 00h–06h match the values stored in the time-of-day/date alarm registers. The alarms can also be
programmed to repeat every second, minute, hour, day, or date. Table 3 shows the possible settings.
Configurations not listed in the table result in illogical operation.
The DY/DT bits (bit 6 of the alarm day/date registers) control whether the alarm value stored in bits 0–5 of that
register reflects the day of the week or the date of the month. If DY/DT is written to logic 0, the alarm is the result of
a match with date of the month. If DY/DT is written to logic 1, the alarm is the result of a match with day of the
week.
When the RTC register values match alarm register settings, the corresponding alarm flag (A1F or A2F) bit is set
to logic 1. The bit(s) will remain at a logic 1 until written to a logic 0 by the user. If the corresponding alarm
interrupt enable (A1IE or A2IE) is also set to logic 1, the alarm condition activates one of the interrupt output (INTA
or SQW/INTB) signals. The match is tested on the once-per-second update of the time and date registers.
DS1337 I2C Serial Real-Time Clock
Table 3. Alarm Mask Bits
ALARM 1 REGISTER MASK BITS
(BIT 7)
DY/DT
A1M4 A1M3 A1M2 A1M1
ALARM RATE
X 1 1 1 1 Alarm once per second
X 1 1 1 0 Alarm when seconds match
X 1 1 0 0 Alarm when minutes and seconds match
X 1 0 0 0 Alarm when hours, minutes, and seconds match
0 0 0 0 0
Alarm when date, hours, minutes, and seconds
match
1 0 0 0 0 Alarm when day, hours, minutes, and seconds match
ALARM 2 REGISTER MASK BITS
(BIT 7)
DY/DT
A2M4 A2M3 A2M2
ALARM RATE
X 1 1 1 Alarm once per minute (00 seconds of every minute)
X 1 1 0 Alarm when minutes match
X 1 0 0 Alarm when hours and minutes match
0 0 0 0 Alarm when date, hours, and minutes match
1 0 0 0 Alarm when day, hours, and minutes match
SPECIAL-PURPOSE REGISTERS
The DS1337 has two additional registers (control and status) that control the RTC, alarms, and square-wave
output.
Control Register (0Eh)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
EOSC 0 0 RS2 RS1 INTCN A2IE A1IE
Bit 7: Enable Oscillator (EOSC). This active-low bit when set to logic 0 starts the oscillator. When this bit is set to
logic 1, the oscillator is stopped. This bit is enabled (logic 0) when power is first applied.
Bits 4 and 3: Rate Select (RS2 and RS1). These bits control the frequency of the square-wave output when the
square wave has been enabled. The table below shows the square-wave frequencies that can be selected with the
RS bits. These bits are both set to logic 1 (32kHz) when power is first applied.
SQW/INTB Output
INTCN RS2 RS1 SQW/INTB
OUTPUT
A2IE
0 0 0 1Hz X
0 0 1 4.096kHz X
0 1 0 8.192kHz X
0 1 1 32.768kHz X
1 X X A2F 1
Bit 2: Interrupt Control (INTCN). This bit controls the relationship between the two alarms and the interrupt output
pins. When the INTCN bit is set to logic 1, a match between the timekeeping registers and the alarm 1 registers l
activates the INTA pin (provided that the alarm is enabled) and a match between the timekeeping registers and the
alarm 2 registers activates the SQW/INTB pin (provided that the alarm is enabled). When the INTCN bit is set to
logic 0, a square wave is output on the SQW/INTB pin. This bit is set to logic 0 when power is first applied.
DS1337 I2C Serial Real-Time Clock
Bit 1: Alarm 2 Interrupt Enable (A2IE). When set to logic 1, this bit permits the alarm 2 flag (A2F) bit in the status
register to assert INTA (when INTCN = 0) or to assert SQW/INTB (when INTCN = 1). When the A2IE bit is set to
logic 0, the A2F bit does not initiate an interrupt signal. The A2IE bit is disabled (logic 0) when power is first
applied.
Bit 0: Alarm 1 Interrupt Enable (A1IE). When set to logic 1, this bit permits the alarm 1 flag (A1F) bit in the status
register to assert INTA. When the A1IE bit is set to logic 0, the A1F bit does not initiate the INTA signal. The A1IE
bit is disabled (logic 0) when power is first applied.
Status Register (0Fh)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
OSF 0 0 0 0 0 A2F A1F
Bit 7: Oscillator Stop Flag (OSF). A logic 1 in this bit indicates that the oscillator either is stopped or was stopped
for some period of time and may be used to judge the validity of the clock and calendar data. This bit is set to logic
1 anytime that the oscillator stops. The following are examples of conditions that can cause the OSF bit to be set:
1) The first time power is applied.
2) The voltage present on VCC is insufficient to support oscillation.
3) The EOSC bit is turned off.
4) External influences on the crystal (e.g., noise, leakage, etc.).
This bit remains at logic 1 until written to logic 0.
Bit 1: Alarm 2 Flag (A2F). A logic 1 in the alarm 2 flag bit indicates that the time matched the alarm 2 registers.
This flag can be used to generate an interrupt on either INTA or SQW/INTB depending on the status of the INTCN
bit in the control register. If the INTCN bit is set to logic 0 and A2F is at logic 1 (and A2IE bit is also logic 1), the
INTA pin goes low. If the INTCN bit is set to logic 1 and A2F is logic 1 (and A2IE bit is also logic 1), the SQW/INTB
pin goes low. A2F is cleared when written to logic 0. This bit can only be written to logic 0. Attempting to write to
logic 1 leaves the value unchanged.
Bit 0: Alarm 1 Flag (A1F). A logic 1 in the alarm 1 flag bit indicates that the time matched the alarm 1 registers. If
the A1IE bit is also logic 1, the INTA pin goes low. A1F is cleared when written to logic 0. This bit can only be
written to logic 0. Attempting to write to logic 1 leaves the value unchanged.
DS1337 I2C Serial Real-Time Clock
I2C SERIAL DATA BUS
The DS1337 supports the I2C bus protocol. A device that sends data onto the bus is defined as a transmitter and a
device receiving data as a receiver. The device that controls the message is called a master. The devices that are
controlled by the master are referred to as slaves. A master device that generates the serial clock (SCL), controls
the bus access, and generates the START and STOP conditions must control the bus. The DS1337 operates as a
slave on the I2C bus. Within the bus specifications a standard mode (100kHz maximum clock rate) and a fast mode
(400kHz maximum clock rate) are defined. The DS1337 works in both modes. Connections to the bus are made
through the open-drain I/O lines SDA and SCL.
The following bus protocol has been defined (Figure 2):
Data transfer may be initiated only when the bus is not busy.
During data transfer, the data line must remain stable whenever the clock line is HIGH. Changes in the data
line while the clock line is HIGH are interpreted as control signals.
Accordingly, the following bus conditions have been defined:
Bus not busy: Both data and clock lines remain HIGH.
Start data transfer: A change in the state of the data line, from HIGH to LOW, while the clock is HIGH, defines a
START condition.
Stop data transfer: A change in the state of the data line, from LOW to HIGH, while the clock line is HIGH,
defines the STOP condition.
Data valid: The state of the data line represents valid data when, after a START condition, the data line is stable
for the duration of the HIGH period of the clock signal. The data on the line must be changed during the LOW
period of the clock signal. There is one clock pulse per bit of data.
Each data transfer is initiated with a START condition and terminated with a STOP condition. The number of data
bytes transferred between START and STOP conditions are not limited, and are determined by the master device.
The information is transferred byte-wise and each receiver acknowledges with a ninth bit.
Acknowledge: Each receiving device, when addressed, is obliged to generate an acknowledge after the reception
of each byte. The master device must generate an extra clock pulse that is associated with this acknowledge bit.
A device that acknowledges must pull down the SDA line during the acknowledge clock pulse in such a way that
the SDA line is stable LOW during the HIGH period of the acknowledge-related clock pulse. Of course, setup and
hold times must be taken into account. A master must signal an end of data to the slave by not generating an
acknowledge bit on the last byte that has been clocked out of the slave. In this case, the slave must leave the data
line HIGH to enable the master to generate the STOP condition.
DS1337 I2C Serial Real-Time Clock
Figure 2. Data Transfer on I2C Serial Bus
Depending upon the state of the R/W bit, two types of data transfer are possible:
1) Data transfer from a master tr ansmitter to a slave receiver. The first byte transmitted by the master is the
slave address. Next follows a number of data bytes. The slave returns an acknowledge bit after each received
byte. Data is transferred with the most significant bit (MSB) first.
2) Data transfer from a slave transmitter to a master receiver. The master transmits the first byte (the slave
address). The slave then returns an acknowledge bit, followed by the slave transmitting a number of data
bytes. The master returns an acknowledge bit after all received bytes other than the last byte. At the end of the
last received byte, a “not acknowledge” is returned. The master device generates all of the serial clock pulses
and the START and STOP conditions. A transfer is ended with a STOP condition or with a repeated START
condition. Since a repeated START condition is also the beginning of the next serial transfer, the bus is not
released. Data is transferred with the most significant bit (MSB) first.
The DS1337 can operate in the following two modes:
1) Slave Receiver Mode (Write M ode): Serial data and clock are received through SDA and SCL. After each
byte is received an acknowledge bit is transmitted. START and STOP conditions are recognized as the
beginning and end of a serial transfer. Address recognition is performed by hardware after reception of the
slave address and direction bit (Figure 3). The slave address byte is the first byte received after the master
generates the START condition. The slave address byte contains the 7-bit DS1337 address, which is 1101000,
followed by the direction bit (R/W), which, for a write, is 0. After receiving and decoding the slave address byte
the device outputs an acknowledge on the SDA line. After the DS1337 acknowledges the slave address +
write bit, the master transmits a register address to the DS1337. This sets the register pointer on the DS1337.
The master may then transmit zero or more bytes of data, with the DS1337 acknowledging each byte received.
The address pointer will increment after each data byte is transferred. The master generates a STOP condition
to terminate the data write.
2) Slave Transmitter Mode (Read Mode): The first byte is received and handled as in the slave receiver mode.
However, in this mode, the direction bit indicates that the transfer direction is reversed. Serial data is
transmitted on SDA by the DS1337 while the serial clock is input on SCL. START and STOP conditions are
recognized as the beginning and end of a serial transfer (Figure 4 and Figure 5). The slave address byte is the
first byte received after the master generates a START condition. The slave address byte contains the 7-bit
DS1337 address, which is 1101000, followed by the direction bit (R/W), which, for a read, is 1. After receiving
and decoding the slave address byte the device outputs an acknowledge on the SDA line. The DS1337 then
begins to transmit data starting with the register address pointed to by the register pointer. If the register
pointer is not written to before the initiation of a read mode the first address that is read is the last one stored in
the register pointer. The DS1337 must receive a “not acknowledge” to end a read.
DS1337 I2C Serial Real-Time Clock
Figure 3. Data Write—Slave Receiver Mode
...AXXXXXXXXAS 0 XXXXXXXX AXXXXXXXX AXXXXXXXX A P
S - Start
A - Acknowledge (ACK)
P - Stop
<R/W>
DATA TRANSFERRED
(X+1 BYTES + ACKNOWLEDGE)
1101000
<Slave Address> <Word Address (n)> <Data(n)> <Data(n+1)> <Data(n+X)>
Master to slave
Slave to master
Figure 4. Data Read (from Current Pointer Location)—Slave Transmitter Mode
...AXXXXXXXXA1101000S 1 XXXXXXXX AXXXXXXXX XXXXXXXX AP
<Data(n+2)> <Data(n+X)>
A
S - Start
A - Acknowledge (ACK)
P - Stop
A - Not Acknowledge (NACK)
<RW>
DATA TRANSFERRED
(X+1 BYTES + ACKNOWLEDGE)
NOTE: LAST DATA BYTE IS FOLLOWED BY A NACK
<Slave Address> <Data(n)> <Data(n+1)>
Master to slave
Slave to master
Figure 5. Data Read (Write Pointer, Then Read)—Slave Receive and Transmit
...AXXXXXXXX XXXXXXXX AXXXXXXXX AXXXXXXXX AP
S - Start
Sr - Repeated Start
A - Acknowledge (ACK)
P - Stop
A - Not Acknowledge (NACK)
DATA TRANSFERRED
(X+1 BYTES + ACKNOWLEDGE)
NOTE: LAST DATA BYTE IS FOLLOWED BY A NACK
AXXXXXXXXA1101000S 0
<RW>
<Word Address (n)>
A1101000Sr 1
<RW>
<Slave Address>
<Data(n)> <Data(n+1)> <Data(n+2)> <Data(n+X)>
Master to slave
Slave to master
DS1337 I2C Serial Real-Time Clock
HANDLING, PC BOARD LAYOUT, AND ASSEMBLY
The DS1337C package contains a quartz tuning-fork crystal. Pick-and-place equipment may be used, but
precautions should be taken to ensure that excessive shocks are avoided. Ultrasonic cleaning should be avoided
to prevent damage to the crystal.
Avoid running signal traces under the package, unless a ground plane is placed between the package and the
signal line. All N.C. (no connect) pins must be connected to ground.
Moisture-sensitive packages are shipped from the factory dry-packed. Handling instructions listed on the package
label must be followed to prevent damage during reflow. Refer to the IPC/JEDEC J-STD-020 standard for
moisture-sensitive device (MSD) classifications.
PIN CONFIGURATIONS
TOP VIEW SCL SDA
DS1337C
SQW/
I
NT
B
GND
CHIP INFORMATION
TRANSISTOR COUNT: 10,950
PROCESS: CMOS
THERMAL INFORMATION
PACKAGE THETA-JA
(°C/W)
THETA-JC
(°C/W)
8 DIP 110 40
8 SO 170 40
8 μSOP 229 39
16 SO 73 23
PACKAGE INFORMATION
For the latest package outline information and land patterns, go to www.maxim-ic.com/packages.
PACKAGE TYPE PACKAGE CODE DOCUMENT NO.
8 PDIP P8+8 21-0043
8 SO S8+2 21-0041
8 MAX U8+1 21-0036
16 SO W16-H2 21-0042
DIP
I
NTA
VCC
I
NTA
VCC
X1
VCC
X1 N.C.
DS1337 N.C.
SQW/
I
NTB
X2
SQW/
I
NTB
X2 DS1337 N.C.N.C.
SCL
I
NTA
SCL
N.C. N.C.
SDA
GND
SDA
GND
N.C.N.C.
SO
,
SOP N.C. N.C.
SO (300 mils)
DS1337 I2C Serial Real-Time Clock
REVISION HISTORY
REVISION
DATE DESCRIPTION PAGES
CHANGED
Added device access details to General Description section. 1
Removed leaded ordering numbers from the Ordering Information table. 1
Added Note 5 to Timekeeping VCC EC table range. 2
Added “Full Operation” and “Timekeeping” to headers to clarify table usage. 2
Added OSF parameter to EC table. 3
Updated Pin Description to indicate max input voltage and that unused outputs
may be left open. 5
Added oscillator circuit and show open-drain transistors on Block Diagram. 6
Added Operating Mode section with details on operating mode and
corresponding Icc parameter. 7
Added I2C Interface section explaining how to synchronize a microcontroller and
the RTC. 8
080508
Corrected legend in figure 5 for not-acknowledge (add overbar to symbol). 14
071609 Removed conflicting SDA/SCL input bias statement in Pin Description. 5