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FEATURES
APPLICATIONS
PCM4104-EP
SBAS419 JUNE 2007
High-Performance, 24-Bit, 216-kHz Sampling, Four-Channel AudioDigital-to-Analog Converter
256 Steps with 0.5 dB per StepControlled Baseline Output Phase Inversion (Software Mode Only) One Assembly/Test Site, One Fabrication Zero Data Mute (Software Mode Only)Site
Audio Serial PortExtended Temperature Performance of –40 °C
Supports Left-Justified, Right-Justified,to 85 °C
I
2
S™, and TDM Data FormatsEnhanced Diminishing Manufacturing Sources
Accepts 16-, 18-, 20-, and 24-Bit Two's(DMS) Support
Complement PCM Audio DataEnhanced Product-Change Notification
Standalone or Software-ControlledQualification Pedigree
(1)
Configuration ModesFour High-Performance, Multi-Level, Four-Wire Serial Peripheral Interface (SPI™)Delta-Sigma Digital-to-Analog Converters Port Provides Control Register Access inSoftware ModeDifferential Voltage Outputs
Power Supplies: 5 V Analog, 3.3 V Digital Full-Scale Output (Differential): 6.15 V
PP
Power DissipationSupports Sampling Frequencies up to 216 kHz
203 mW typical with f
s
= 48 kHzTypical Dynamic Performance (24-Bit Data)
220 mW typical with f
s
= 96 kHz Dynamic Range (A-Weighted): 118 dB
236 mW typical with f
s
= 192 kHz THD+N: –100 dB
Power-Down ModesLinear Phase, 8 ×Oversampling DigitalInterpolation Filter Small 48-Lead TQFP PackageDigital De-Emphasis Filters for 32-kHz,44.1-kHz, and 48-kHz Sampling Rates
Digital Mixing ConsolesSoft Mute Function
Digital Audio Workstations All-Channel Mute via the MUTE Input Pin
Digital Audio Effects Processors Per-Channel Mute Available in Software
Broadcast Studio EquipmentMode
Surround-Sound ProcessorsDigital Attenuation (Software Mode Only)
High-End A/V Receivers Attenuation Range: 0 dB to –119.5 dB(1) Component qualification in accordance with JEDEC andindustry standards to ensure reliable operation over anextended temperature range. This includes, but is not limitedto, Highly Accelerated Stress Test (HAST) or biased 85/85,temperature cycle, autoclave or unbiased HAST,electromigration, bond intermetallic life, and mold compoundlife. Such qualification testing should not be viewed asjustifying use of this component beyond specifiedperformance and environmental limits.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Copyright © 2007, Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.
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DESCRIPTION
ABSOLUTE MAXIMUM RATINGS
PCM4104-EP
SBAS419 JUNE 2007
The PCM4104 is a high-performance, four-channel digital-to-analog (D/A) converter designed for use inprofessional audio applications. The PCM4104 supports 16- to 24-bit linear PCM input data, with samplingfrequencies up to 216 kHz. The PCM4104 features lower power consumption than most comparable stereoaudio D/A converters, making it ideal for use in high channel count applications by lowering the overall powerbudget required for the D/A conversion subsystem.
The PCM4104 features delta-sigma architecture, employing a high-performance multi-level modulator combinedwith a switched capacitor output filter. This architecture yields lower out-of-band noise and a high tolerance tosystem clock phase jitter. Differential voltage outputs are provided for each channel and are well-suited tohigh-performance audio applications. The differential outputs are easily converted to a single-ended output usingan external op amp IC.
The PCM4104 includes a flexible audio serial port interface, which supports standard and time divisionmultiplexed (TDM) formats. Support for TDM formats simplifies interfacing to DSP serial ports, while supportinga cascade connection for two PCM4104 devices. In addition, the PCM4104 offers two configuration modes:Standalone and Software-Controlled. The Standalone mode provides dedicated control pins for configuring asubset of the available PCM4104 functions, while Software mode utilizes a serial peripheral interface (SPI) portfor accessing the complete feature set via internal control registers.
The PCM4104 operates from a 5-V analog power supply and a 3.3-V digital power supply. The digital I/O iscompatible with 3.3-V logic families. The PCM4104 is available in a TQFP-48 package.
ORDERING INFORMATION
(1)
SPECIFIEDPACKAGE- PACKAGE PACKAGE ORDERING TRANSPORTPRODUCT TEMPERATURELEAD DESIGNATOR
(2)
MARKING NUMBER MEDIA, QUANTITYRANGE
PCM4104 TQFP-48 PFB –40 °C to 85 °C PCM4104EP PCM4104IPFBREP Tape and Reel, 2000
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TIwebsite at www.ti.com .(2) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available atwww.ti.com/sc/package.
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled withappropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may bemore susceptible to damage because very small parametric changes could cause the device not to meet its publishedspecifications.
over operating free-air temperature range (unless otherwise noted)
(1)
PCM4104 UNIT
V
CC
6.0 VSupply voltage
V
DD
3.6 VGround voltage difference Any AGND-to-AGND and AGND-to-DGND ±0.1 VFS0, FS1, FMT0, FMT1, FMT2, CDOUT, CDIN, CCLK, CS,Digital input voltage DATA0, DATA1, BCK, LRCK, SCKI, SUB, DEM0, DEM1, MUTE, –0.3 to (V
DD
+ 0.3) VRST, MODEInput current (any pin except supplies) ±10 mAOperating temperature range –40 to 85 °CStorage temperature range, T
STG
–65 to 150 °C
(1) Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to absolutemaximum conditions for extended periods may degrade device reliability. These are stress ratings only, and functional operation of thedevice at these or any other conditions beyond those specified is not implied.
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ELECTRICAL CHARACTERISTICS
PCM4104-EP
SBAS419 JUNE 2007
All parameters are specified at T
A
= 25 °C with V
CC
= 5 V, V
DD
= 3.3 V, (unless otherwise noted) and a measurementbandwidth from 10 Hz to 20 kHz, unless otherwise noted. System clock frequency is equal to 256f
S
for Single and Dual Ratesampling modes, and 128f
S
for Quad Rate sampling mode.
PCM4104PARAMETER CONDITIONS UNITSMIN TYP MAX
RESOLUTION 24 Bits
DATA FORMAT
Audio data formats Left or Right Justified, I
2
S, and TDMAudio data word length 16 24 BitsBinary data format Two’s Complement Binary, MSB First
CLOCK RATES AND TIMING
Single rate sampling mode 6.144 36.864System clock frequency f
SCLK
Dual rate sampling mode 13.824 36.864 MHzQuad rate sampling mode 13.824 36.864Single rate sampling mode 24 54Sampling frequency f
S
Dual rate sampling mode 54 108 kHzQuad rate sampling mode 108 216SPI port data clock f
CCLK
24 MHzSPI port data clock high time t
CCLKH
15 nsSPI port data clock low time t
CCLKL
15 ns
DIGITAL INPUT/OUTPUT
V
IH
2.0 VInput logic level
V
IL
0.8 VI
IH
V
IN
= 2.64 V (for –40 °C to 85 °C) 1 10 μAInput logic current
I
IL
V
IN
= 0.66 V (for –40 °C to 85 °C) 1 –10 μAV
OH
I
OH
= –2 mA (for –40 °C to 85 °C) 2.4 VOutput logic level
V
OL
I
OL
= +2 mA (for –40 °C to 85 °C) 0.4 V
ANALOG OUTPUTS
Full-scale output voltage, differential R
L
= 600 6.15 V
pp
Bipolar zero voltage 2.5 VOutput impedance 5 OhmsSwitched capacitor filter frequency
f = 20 kHz, all sampling modes –0.2 dBresponse
Gain error 0.5 % FSRGain mismatch, channel-to-channel 0.6 % FSRBipolar zero error 1 mVV
COM
1 and V
COM
2 output voltage V
CC
= 5 V 2.5 VV
COM
1 and V
COM
2 output current 200 μA
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PCM4104-EP
SBAS419 JUNE 2007
ELECTRICAL CHARACTERISTICS (continued)All parameters are specified at T
A
= 25 °C with V
CC
= 5 V, V
DD
= 3.3 V, (unless otherwise noted) and a measurementbandwidth from 10 Hz to 20 kHz, unless otherwise noted. System clock frequency is equal to 256f
S
for Single and Dual Ratesampling modes, and 128f
S
for Quad Rate sampling mode.
PCM4104PARAMETER CONDITIONS UNITSMIN TYP MAX
DYNAMIC PERFORMANCE WITH 24-BIT DATA
(1)
f
S
= 48 kHz
f = 1 kHz at 0 dBFS –100 –94Total harmonic distortion +
THD+N f = 1 kHz at 0 dBFS (for –40 °C to 85 °C) -91 dBnoise
f = 1 kHz at –60 dBFS –56f = 1 kHz at –60 dBFS 112 118 dBDynamic range, A-weighted
f = 1 kHz at –60 dBFS (for –40C to 85 °C) 109 dBIdle channel SNR, A-weighted All zero input data 119 dBIdle channel SNR, unweighted All zero input data 116 dBf = 1 kHz at 0 dBFS for active channel 100 110 dBChannel separation
f = 1 kHz at 0 dBFS for active channel (for
98 dB–40C to 85 °C)
f
S
= 96 kHz
f = 1 kHz at 0 dBFS,
–100BW = 10 Hz to 40 kHzTotal harmonic distortion +
THD+N dBnoise
f = 1 kHz at –60 dBFS,
–53BW = 10 Hz to 40 kHzDynamic range, A-weighted f = 1 kHz at –60 dBFS 118 dBIdle channel SNR, A-weighted All zero input data 119 dBIdle channel SNR, unweighted All zero input data, BW = 10 Hz to 40 kHz 113 dBChannel separation f = 1 kHz at 0 dBFS for active channel 110 dB
f
S
= 192 kHz
f = 1 kHz at 0 dBFS,
–97BW = 10 Hz to 40 kHzTotal harmonic distortion +
THD+N dBnoise
f = 1 kHz at –60 dBFS,
–53BW = 10 Hz to 40 kHzDynamic range, A-weighted f = 1 kHz at –60 dBFS 118 dBIdle channel SNR, A-weighted All zero input data 118 dBIdle channel SNR, unweighted All zero input data, BW = 10 Hz to 40 kHz 113 dBChannel separation f = 1 kHz at 0 dBFS for active channel 110 dB
DYNAMIC PERFORMANCE WITH 16-BIT DATA
f
S
= 44.1 kHz
f = 1 kHz at 0 dBFS –92Total harmonic distortion +
THD+N dBnoise
f = 1 kHz at –60 dBFS –33Dynamic Range, A-weighted f = 1 kHz at –60 dBFS 96 dBIdle channel SNR, A-weighted
(2)
All zero input data 118 dBIdle channel SNR, unweighted
(2)
All zero input data 115 dB
DIGITAL FILTERS
(1) Dynamic performance parameters are measured using an Audio Precision System Two Cascade or Cascade Plus test system. Inputdata word length is 24 bits with triangular PDF dither added for dynamic range and THD+N tests. Idle channel SNR is measured withboth the soft and zero data mute functions disabled and 0% full–scale input data with no dither applied. The measurement bandwidth islimited by using the Audio Precision 10 Hz high–pass filter in combination with either the AES17 20 kHz low-pass filter or AES17 40 kHzlow-pass filter. All A-weighted measurements are performed using the Audio Precision A-weighting filter in combination with either the22 kHz or 80 kHz low-pass filter. Measurement mode is set to RMS for all parameters. The AVERAGE measurement mode will yieldbetter typical performance numbers.(2) Idle Channel SNR is not limited by word length.
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PCM4104-EP
SBAS419 JUNE 2007
ELECTRICAL CHARACTERISTICS (continued)All parameters are specified at T
A
= 25 °C with V
CC
= 5 V, V
DD
= 3.3 V, (unless otherwise noted) and a measurementbandwidth from 10 Hz to 20 kHz, unless otherwise noted. System clock frequency is equal to 256f
S
for Single and Dual Ratesampling modes, and 128f
S
for Quad Rate sampling mode.
PCM4104PARAMETER CONDITIONS UNITSMIN TYP MAX
±0.002 dB 0.454f
S
HzPassband
–3 dB 0.487f
S
HzStop Band 0.546f
S
HzPassband ripple ±0.002 dB0.546fs –75 dBStopband attenuation
0.567fs –82 dBGroup delay 29/f
S
secDe-emphasis filter error 0.1 dB
POWER SUPPLY
Supply Range
Analog supply, V
CC
4.75 5.0 5.25 VDigital supply, V
DD
3.0 3.3 3.6 V
Power down current V
CC
= 5 V, VDD = 3.3 V
Power-down supply current, I
CC
+ I
DD
RST = low, system and audio clocks off 1 mA
Quiescent current System and audio clocks applied, all 0s data
V
CC
= 5 V, f
S
= 48 kHz ( for –40 °C to
32 4585 °C)Analog supply, I
CC
mAV
CC
= 5 V, f
S
= 96 kHz 32V
CC
= 5 V, f
S
= 192 kHz 32V
DD
= 3.3 V, f
S
= 48 kHz ( for –40 °C to
13 1785 °C)Digital supply, I
DD
mAV
DD
= 3.3 V, f
S
= 96 kHz 18V
DD
= 3.3 V, f
S
= 192 kHz 23V
CC
= 5 V, V
DD
= 3.3 Vf
S
= 48 kHz ( for –40 °C to 85 °C) 203 286Total power dissipation
f
S
= 96 kHz 220 mWf
S
= 192 kHz 236
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PIN ASSIGNMENTS
TQFP PACKAGE
(TOP VIEW)
36
35
34
33
32
31
30
29
28
27
26
25
VOUT4+
VOUT4
AGND2
VREF4
VREF4+
NC
NC
FS1
FS0
FMT2
FMT1
FMT0
VCOM1
VOUT2+
VOUT2
VCC1
VREF2+
VREF2
VREF3
VREF3+
VCC2
VOUT3
VOUT3+
VCOM2
SUB
SCKI
BCK
LRCK
DATA0
DATA1
VDD
DGND
CS
CCLK
CDIN
CDOUT
1
2
3
4
5
6
7
8
9
10
11
12
VOUT1+
VOUT1
AGND1
VREF1
VREF1+
NC
NC
MODE
RST
MUTE
DEM1
DEM0
48 47 46 45 44 43 42 41 40 39 38
13 14 15 16 17 18 19 20 21 22 23
37
24
PCM4104
PCM4104-EP
SBAS419 JUNE 2007
TERMINAL FUNCTIONS
TERMINAL
I/O DESCRIPTIONNAME NO.
V
OUT
1+ 1 Output Channel 1 Analog Output, NoninvertedV
OUT
1– 2 Output Channel 1 Analog Output, InvertedAGND1 3 Ground Analog GroundV
REF
1– 4 Input Channel 1 Low Reference Voltage; Connect to AGNDV
REF
1+ 5 Input Channel 1 High Reference Voltage; Connect to V
CC
NC 6 No Internal ConnectionNC 7 No Internal ConnectionMODE 8 Input Operating Mode (0 = Standalone, 1= Software Controlled)RST 9 Input Reset/Power Down (Active Low)MUTE 10 Input All-Channel Soft Mute (Active High)DEM1 11 Input Digital De-Emphasis Filter ConfigurationDEM0 12 Input Digital De-Emphasis Filter ConfigurationSUB 13 Input Sub-Frame Assignment (TDM Formats Only)SCKI 14 Input System ClockBCK 15 Input Audio Bit (or Data) ClockLRCK 16 Input Audio Left/Right (or Word) ClockAudio Data for Channels 1 and 2 (I
2
S, Left/Right Justified formats) or Audio Data for ChannelsDATA0 17 Input
1 Through 4 for TDM FormatsDATA1 18 Input Audio Data for Channels 3 and 4 (I
2
S, Left/Right Justified formats)
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PCM4104-EP
SBAS419 JUNE 2007
PIN ASSIGNMENTS (continued)TERMINAL FUNCTIONS (continued)
TERMINAL
I/O DESCRIPTIONNAME NO.
V
DD
19 Power Digital Power Supply, 3.3 VDGND 20 Ground Digital GroundCS 21 Input Serial Peripheral Interface (SPI) Chip Select (Active Low)CCLK 22 Input Serial Peripheral Interface (SPI) Data ClockCDIN 23 Input Serial Peripheral Interface (SPI) Data InputCDOUT 24 Output Serial Peripheral Interface (SPI) Data OutputFMT0 25 Input Audio Data Format ConfigurationFMT1 26 Input Audio Data Format ConfigurationFMT2 27 Input Audio Data Format ConfigurationFS0 28 Input Sampling Mode ConfigurationFS1 29 Input Sampling Mode ConfigurationNC 30 No Internal ConnectionNC 31 No Internal ConnectionV
REF
4+ 32 Input Channel 4 High Reference Voltage; Connect to V
CC
V
REF
4– 33 Input Channel 4 Low Reference Voltage; Connect to AGNDAGND2 34 Ground Analog GroundV
OUT
4– 35 Output Channel 4 Analog Output, InvertedV
OUT
4+ 36 Output Channel 4 Analog Output, NoninvertedV
COM
2 37 Output DC Common-Mode Voltage for Channels 3 and 4, 2.5 V nominalV
OUT
3+ 38 Output Channel 3 Analog Output, NoninvertedV
OUT
3– 39 Output Channel 3 Analog Output, InvertedV
CC
2 40 Power Analog Power Supply, 5 VV
REF
3+ 41 Input Channel 3 High Reference Voltage; Connect to V
CC
V
REF
3– 42 Input Channel 3 Low Reference Voltage; Connect to AGNDV
REF
2– 43 Input Channel 2 Low Reference Voltage; Connect to AGNDV
REF
2+ 44 Input Channel 2 High Reference Voltage; Connect to V
CC
V
CC
1 45 Power Analog Power Supply, 5 VV
OUT
2– 46 Output Channel 2 Analog Output, InvertedV
OUT
2+ 47 Output Channel 2 Analog Output, NoninvertedV
COM
1 48 Output DC Common-Mode Voltage for Channels 1 and 2, 2.5 V nominal
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TYPICAL CHARACTERISTICS
FFT PLOT
Frequency (Hz)
Amplitude (dB)
0
10
20
30
40
50
60
70
80
90
100
110
120
130
140
150
160 1k10020 10k 20k
fS= 48kHz
fIN = 1kHz
0dBFS Amplitude
24−Bit Data
FFT PLOT
Frequency (Hz)
Amplitude (dB)
0
10
20
30
40
50
60
70
80
90
100
110
120
130
140
150
160 1k10020 10k 20k
fS= 48kHz
fIN = 1kHz
20dBFS Amplitude
24−Bit Data
FFT PLOT
Frequency (Hz)
Amplitude (dB)
0
10
20
30
40
50
60
70
80
90
100
110
120
130
140
150
160 1k10020 10k 20k
fS= 48kHz
Idle Channel Input
24−Bit Data
FFT PLOT
Frequency (Hz)
Amplitude (dB)
0
10
20
30
40
50
60
70
80
90
100
110
120
130
140
150
160 1k10020 10k 20k
fS= 48kHz
fIN = 1kHz
60dBFS Amplitude
24−Bit Data
FFT PLOT
Frequency (Hz)
Amplitude (dB)
0
10
20
30
40
50
60
70
80
90
100
110
120
130
140
150
160 1k10020 10k 40k
fS= 96kHz
fIN = 1kHz
0dBFS Amplitude
24−Bit Data
FFT PLOT
Frequency (Hz)
Amplitude (dB)
0
10
20
30
40
50
60
70
80
90
100
110
120
130
140
150
160 1k10020 10k 40k
fS= 96kHz
fIN = 1kHz
20dBFS Amplitude
24−Bit Data
PCM4104-EP
SBAS419 JUNE 2007
All parameters are specified at T
A
= 25 °C with V
CC
= 5 V, V
DD
= 3.3 V, and a measurement bandwidth from 10 Hz to 20 kHz,unless otherwise noted. System clock frequency is equal to 256f
S
for Single and Dual Rate sampling modes, and 128f
S
forQuad Rate sampling mode.
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FFT PLOT
Frequency (Hz)
Amplitude (dB)
0
10
20
30
40
50
60
70
80
90
100
110
120
130
140
150
160 1k10020 10k 40k
fS= 96kHz
fIN = 1kHz
60dBFS Amplitude
24−Bit Data
FFT PLOT
Frequency (Hz)
Amplitude (dB)
0
10
20
30
40
50
60
70
80
90
100
110
120
130
140
150
160 1k10020 10k 40k
fS= 96kHz
Idle Channel Input
24−Bit Data
FFT PLOT
Frequency (Hz)
Amplitude (dB)
0
10
20
30
40
50
60
70
80
90
100
110
120
130
140
150
160 1k10020 10k 40k
fS= 192kHz
fIN = 1kHz
0dBFS Amplitude
24−Bit Data
FFT PLOT
Frequency (Hz)
Amplitude (dB)
0
10
20
30
40
50
60
70
80
90
100
110
120
130
140
150
160 1k10020 10k 40k
fS= 192kHz
fIN = 1kHz
20dBFS Amplitude
24−Bit Data
FFT PLOT
Frequency (Hz)
Amplitude (dB)
0
10
20
30
40
50
60
70
80
90
100
110
120
130
140
150
160 1k10020 10k 40k
fS= 192kHz
fIN = 1kHz
60dBFS Amplitude
24−Bit Data
FFT PLOT
Frequency (Hz)
Amplitude (dB)
0
10
20
30
40
50
60
70
80
90
100
110
120
130
140
150
160 1k10020 10k 40k
fS= 192kHz
Idle Channel Input
24−Bit Data
PCM4104-EP
SBAS419 JUNE 2007
TYPICAL CHARACTERISTICS (continued)All parameters are specified at T
A
= 25 °C with V
CC
= 5 V, V
DD
= 3.3 V, and a measurement bandwidth from 10 Hz to 20 kHz,unless otherwise noted. System clock frequency is equal to 256f
S
for Single and Dual Rate sampling modes, and 128f
S
forQuad Rate sampling mode.
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FFT PLOT
Frequency (Hz)
Amplitude (dB)
0
10
20
30
40
50
60
70
80
90
100
110
120
130
140
150
160 1k10020 10k 20k
fS= 44.1kHz
fIN = 1kHz
0dBFS Amplitude
16−Bit Data
FFT PLOT
Frequency (Hz)
Amplitude (dB)
0
10
20
30
40
50
60
70
80
90
100
110
120
130
140
150
160 1k10020 10k 20k
fS= 44.1kHz
fIN = 1kHz
20dBFS Amplitude
16−Bit Data
FFT PLOT
Frequency (Hz)
Amplitude (dB)
0
10
20
30
40
50
60
70
80
90
100
110
120
130
140
150
160 1k10020 10k 20k
fS= 44.1kHz
fIN = 1kHz
60dBFS Amplitude
16−Bit Data
FFT PLOT
Frequency (Hz)
Amplitude (dB)
0
10
20
30
40
50
60
70
80
90
100
110
120
130
140
150
160 1k10020 10k 20k
fS= 44.1kHz
Idle Channel Input
16−Bit Data
THD+N vs AMPLITUDE
Amplitude (dBFS)
THD+N (dB)
80
85
90
95
100
105
110
115
120
150
140
130
120
110
100
90
80
70
60
50
40
30
20
10
0
fS= 48kHz
fIN = 1kHz
24−Bit Data
THD+N vs AMPLITUDE
Amplitude (dBFS)
THD+N (dB)
80
85
90
95
100
105
110
115
120
150
140
130
120
110
100
90
80
70
60
50
40
30
20
10
0
fS= 96kHz
fIN = 1kHz
24−Bit Data
PCM4104-EP
SBAS419 JUNE 2007
TYPICAL CHARACTERISTICS (continued)All parameters are specified at T
A
= 25 °C with V
CC
= 5 V, V
DD
= 3.3 V, and a measurement bandwidth from 10 Hz to 20 kHz,unless otherwise noted. System clock frequency is equal to 256f
S
for Single and Dual Rate sampling modes, and 128f
S
forQuad Rate sampling mode.
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THD+N vs AMPLITUDE
Amplitude (dBFS)
THD+N (dB)
80
85
90
95
100
105
110
115
120
150
140
130
120
110
100
90
80
70
60
50
40
30
20
10
0
fS= 192kHz
fIN = 1kHz
24−Bit Data
THD+N vs AMPLITUDE
Amplitude (dBFS)
THD+N (dB)
80
85
90
95
100
105
110
115
120
150
140
130
120
110
100
90
80
70
60
50
40
30
20
10
0
fS= 44.1kHz
fIN = 1kHz
16−Bit Data
0
20
40
60
80
100
120
140
160
FREQUENCY RESPONSE
0 1 2 3 4
Frequency (x fS)
Amplitude (dB)
0.0
1.0
2.0
3.0
4.0
5.0
6.0
7.0
8.0
9.0
10.0
DE−EMPHASIS FILTER RESPONSE (fS= 32kHz)
0 2 4 6 8 10 12 14
Frequency (kHz)
Level (dB)
0.5
0.4
0.3
0.2
0.1
0.0
0.1
0.2
0.3
0.4
0.5
DE−EMPHASIS ERROR (fS= 32kHz)
0 2 4 6 8 10 12 14
Frequency (kHz)
Error (dB)
PCM4104-EP
SBAS419 JUNE 2007
TYPICAL CHARACTERISTICS (continued)All parameters are specified at T
A
= 25 °C with V
CC
= 5 V, V
DD
= 3.3 V, and a measurement bandwidth from 10 Hz to 20 kHz,unless otherwise noted. System clock frequency is equal to 256f
S
for Single and Dual Rate sampling modes, and 128f
S
forQuad Rate sampling mode.
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0.0
1.0
2.0
3.0
4.0
5.0
6.0
7.0
8.0
9.0
10.0
DE−EMPHASIS FILTER RESPONSE (fS= 44.1kHz)
0 2 4 6 8 10 12 14 16 18 20
Frequency (kHz)
Level (dB)
0.5
0.4
0.3
0.2
0.1
0.0
0.1
0.2
0.3
0.4
0.5
DE−EMPHASIS ERROR (fS= 44.1kHz)
0 2 4 6 8 10 12 14 16 18 20
Frequency (kHz)
Error (dB)
0.0
1.0
2.0
3.0
4.0
5.0
6.0
7.0
8.0
9.0
10.0
DE−EMPHASIS FILTER RESPONSE (fS= 48kHz)
0 2 4 6 8 10 12 14 16 18 22
Frequency (kHz)
Level (dB)
0.5
0.4
0.3
0.2
0.1
0.0
0.1
0.2
0.3
0.4
0.5
DE− EMPHASIS ERROR (fS= 48kHz)
0 2 4 6 8 10 12 14 16 18 22
Frequency (kHz)
Error (dB)
PCM4104-EP
SBAS419 JUNE 2007
TYPICAL CHARACTERISTICS (continued)All parameters are specified at T
A
= 25 °C with V
CC
= 5 V, V
DD
= 3.3 V, and a measurement bandwidth from 10 Hz to 20 kHz,unless otherwise noted. System clock frequency is equal to 256f
S
for Single and Dual Rate sampling modes, and 128f
S
forQuad Rate sampling mode.
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PRODUCT OVERVIEW
Digital
Filtering
and
Functions
Audio
Serial
Port
Control
VREF1+
VOUT1+
VOUT1
VREF1
VREF2+
VOUT2+
VOUT2
VREF2
VCOM1
VREF3+
VOUT3+
VOUT3
VREF3
VREF4+
VOUT4+
VOUT4
VREF4
VCOM2
Digital
Power Analog
Power
System Clock
and
Timing
VCC1
AGND1
VCC21
AGND2
VDD
DGND
D/A Converter
and
Output Filter
D/A Converter
and
Output Filter
D/A Converter
and
Output Filter
D/A Converter
and
Output Filter
LRCK
BCK
DATA0
DATA1
SCKI
RST
MUTE
DEM0
DEM1
SUB
FMT0
FMT1
FMT2
FS0
FS1
MODE
PCM4104-EP
SBAS419 JUNE 2007
The PCM4104 is a high-performance, four-channel D/A converter designed for professional audio systems. ThePCM4104 supports 16- to 24-bit linear PCM input data and sampling frequencies up to 216 kHz. The PCM4104utilizes an 8 ×oversampling digital interpolation filter, followed by a multi-level delta-sigma modulator with asingle pole switched capacitor output filter. This architecture provides excellent dynamic and sonic performance,as well as high tolerance to clock phase jitter. Functional block diagrams, showing both Standalone andSoftware modes, are shown in Figure 1 and Figure 2 .
The PCM4104 incorporates a flexible audio serial port, which accepts 16- to 24-bit PCM audio data in bothstandard audio formats (Left Justified, Right Justified, and Philips I
2
S) and TDM data formats. The TDM formatsare especially useful for interfacing to the synchronous serial ports of digital signal processors. The TDM formatssupport daisy-chaining of two PCM4104 devices on a single three-wire serial interface (for sampling frequenciesup to 108 kHz), forming a high-performance eight-channel D/A conversion system.
The PCM4104 offers two modes for configuration control: Software and Standalone. Software mode makes useof a four-wire SPI port to access internal control registers, allowing configuration of the full PCM4104 feature set.Standalone mode offers a more limited subset of the functions available in Software mode, while allowing for asimplified pin-programmed configuration mode.
Figure 1. Functional Block Diagram for Standalone Mode
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LRCK
BCK
DATA0
DATA1
SCKI
RST
MUTE
SUB
CS
CCLK
CDIN
CDOUT
MODE
VREF1+
VOUT1+
VOUT1
VREF1
VREF2+
VOUT2+
VOUT2
VREF2
VCOM1
VREF3+
VOUT3+
VOUT3
VREF3
VREF4+
VOUT4+
VOUT4
VREF4
VCOM2
Digital
Filtering
and
Functions
Audio
Serial
Port
Control
and
SPI Port
Digital
Power Analog
Power
System Clock
and
Timing
VCC1
AGND1
VCC21
AGND2
VDD
DGND
VDD
D/A Converter
and
Output Filter
D/A Converter
and
Output Filter
D/A Converter
and
Output Filter
D/A Converter
and
Output Filter
ANALOG OUTPUTS
PCM4104-EP
SBAS419 JUNE 2007
PRODUCT OVERVIEW (continued)
Figure 2. PCM4104 Functional Block Diagram for Software Mode
The PCM4104 provides four differential voltage outputs, corresponding to audio channels 1 through 4. V
OUT
1+(pin 1) and V
OUT
1– (pin 2) correspond to Channel 1. V
OUT
2+ (pin 47) and V
OUT
2– (pin 46) correspond to Channel2. V
OUT
3+ (pin 38) and V
OUT
3– (pin 39) correspond to Channel 3. V
OUT
4+ (pin 36) and V
OUT
4– (pin 35)correspond to Channel 4.
Each differential output is typically capable of providing 6.15-V full-scale (differential) into a 600 output load.The output pins are internally biased to the common-mode (or bipolar zero) voltage, which is nominally V
CC
/2.The output section of each D/A converter channel includes a single-pole, switched capacitor low-pass filtercircuit. The switched capacitor filter response tracks with the sampling frequency of the D/A converter andprovides attenuation of the out-of-band noise produced by the delta-sigma modulator. An external two-polecontinuous time filter is recommended to further reduce the out-of-band noise energy and to band limit theoutput spectrum to frequencies suitable for audio reproduction. Refer to the Applications Information section ofthis data sheet for recommended output filter circuits.
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VOLTAGE REFERENCES
(1) Capacitor(s) required for each of the four reference pairs.
VREF+(1)
VCOM1
0.01µF
0.1µF0.1µF
0.1µF to 10µF
VCC
VCOM2
VREF(1)
SAMPLING MODES
PCM4104-EP
SBAS419 JUNE 2007
PRODUCT OVERVIEW (continued)
The PCM4104 includes high and low reference pins for each output channel. V
REF
1+ (pin 5) and V
REF
1– (pin 4)correspond to Channel 1. V
REF
2+ (pin 44) and V
REF
2– (pin 43) correspond to Channel 2. V
REF
3+ (pin 41) andV
REF
3– (pin 42) correspond to Channel 3. V
REF
4+ (pin 32) and V
REF
4– (pin 33) correspond to Channel 4.
The high reference (+) pin may be connected to the corresponding V
CC
supply or an external 5-V reference,while the low reference (–) pin is connected to analog ground. A 0.01- μF bypass capacitor should be placedbetween the corresponding high and low reference pins. An X7R ceramic chip capacitor is recommended for thispurpose. In some cases, a larger capacitor may need to be placed in parallel with the 0.01- μF capacitor, with thevalue of the larger capacitor being dependent upon the low-frequency power-supply noise present in the system.Typical values may range from 1 μF to 10 μF. Low ESR tantalum or multilayer ceramic chip capacitors arerecommended. Figure 3 illustrates the recommended connections for the reference pins.
Figure 3. Recommended Connections for Voltage Reference and Common-Mode Output Pins
In addition to the reference pins, there are two common-mode voltage output pins, V
COM
1 (pin 48) and V
COM
2(pin 37). These pins are nominally set to a value equal to V
CC
/2 by internal voltage dividers. The V
COM
1 pin iscommon to both Channels 1 and 2, while the V
COM
2 pin is common to Channels 3 and 4. A 0.1- μF X7R ceramicchip capacitor should be connected between the common-mode output pin and analog ground. Thecommon-mode outputs are used primarily to bias external output circuitry.
The PCM4104 can operate in one of three sampling modes: Single Rate, Dual Rate, or Quad Rate. Samplingmodes are selected by using the FS[1:0] bits in Control Register 6 in Software mode, or by using the FS0 (pin28) and FS1 (pin 29) inputs in Standalone mode.
The Single Rate mode allows sampling frequencies up to and including 54 kHz. The D/A converter performs128 ×oversampling of the input data in Single Rate mode.
The Dual Rate mode allows sampling frequencies greater than 54 kHz, up to and including 108 kHz. The D/Aconverter performs 64 ×oversampling of the input data in Dual Rate mode.
The Quad Rate mode allows sampling frequencies greater than 108 kHz, up to and including 216 kHz. The D/Aconverter performs 32 ×oversampling of the input data in Quad Rate mode.
Refer to Table 1 for examples of system clock requirements for common sampling frequencies.
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SYSTEM CLOCK REQUIREMENTS
SCKI
tSCKI
tSCKIH
tSCKIL
PARAMETER DESCRIPTION MIN MAX UNITS
System Clock Period 26 ns
tSCKIH System Clock High Pulse Time 12 ns
tSCKIL System Clock Low Pulse Time 12 ns
tSCKI
PCM4104-EP
SBAS419 JUNE 2007
PRODUCT OVERVIEW (continued)
The PCM4104 requires a system clock, applied at the SCKI (pin 14) input. The system clock operates at aninteger multiple of the input sampling frequency, or f
S
. The multiples supported include 128f
S
, 192f
S
, 256f
S
,384f
S
, 512f
S
, or 768f
S
. The system clock frequency is dependent upon the sampling mode. Table 1 shows therequired system clock frequencies for common audio sampling frequencies. Figure 4 shows the system clocktiming requirements.
Although the architecture of the PCM4104 is tolerant to phase jitter on the system clock, it is recommended thatthe user provide a low jitter clock (100 picoseconds or less) for optimal performance.
Table 1. Sampling Modes and System Clock Frequencies for Common Audio Sampling Rates
SAMPLING SYSTEM CLOCK FREQUENCY (MHz)SAMPLING
FREQUENCY, f
SMODE
128f
S
192f
S
256f
S
384f
S
512f
S
768f
S(kHz)
Single Rate 32 n/a n/a 8.192 12.288 16.384 24.576Single Rate 44.1 n/a n/a 11.2896 16.9344 22.5792 33.8688Single Rate 48 n/a n/a 12.288 18.432 24.576 36.864Dual Rate 88.2 n/a n/a 22.5792 33.8688 n/a n/aDual Rate 96 n/a n/a 24.576 36.864 n/a n/aQuad Rate 176.4 22.5792 33.8688 n/a n/a n/a n/aQuad Rate 192 24.576 36.864 n/a n/a n/a n/a
Figure 4. System Clock Timing Requirements
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RESET OPERATION
1024 System Clock Periods
Required for Initialization
System Clock
Indeterminate
or Inactive
SCKI
~ 2.0V
~ 4.0V
0V
0V
0V
0V
Internal
Reset
VCC1
VCC2
VDD
PCM4104-EP
SBAS419 JUNE 2007
The PCM4104 includes three reset functions: power-on, external, and software-controlled. This sectiondescribes each of the three reset functions.
On power up, the internal reset signal is forced low, forcing the PCM4104 into a reset state. The power-on resetcircuit monitors the V
DD
, V
CC
1, and V
CC
2 power supplies. When V
DD
exceeds 2 V (margin of error is ±400 mV)and V
CC
1 and V
CC
2 exceed 4 V (margin of error is ±400 mV), the internal reset signal is forced high. ThePCM4104 then waits for the system clock input (SCKI) to become active. Once the system clock has beendetected, the initialization sequence begins. The initialization sequence requires 1024 system clock periods forcompletion. When the initialization sequence is completed, the PCM4104 is ready to accept audio data at theaudio serial port. Figure 5 shows the power-on reset sequence timing.
If the PCM4104 is configured for Software mode control via the SPI port, all control registers will be reset to theirdefault state during the initialization sequence. In both Standalone and Software modes, the analog outputs forall four channels are muted during the reset and initialization sequence. While in mute state, the analog outputpins are driven to the bipolar zero voltage, or V
CC
/2.
The user may force a reset initialization sequence at any time while the system clock input is active by utilizingthe RST input (pin 9). The RST input is active low, and requires a minimum low pulse width of 40 nanoseconds.The low-to-high transition of the applied reset signal will force an initialization sequence to begin. As in the caseof the power-on reset, the initialization sequence requires 1024 system clock periods for completion. Figure 6illustrates the reset sequence initiated when using the RST input.
A reset initialization sequence is available in Software mode, using the RST bit in Control Register 6. The RSTbit is active high. When RST is set to 1, a reset sequence is initiated in the same fashion as an external resetapplied at the RST input.
Figure 7 shows the state of the analog outputs for the PCM4104 before, during and after the reset operations.
Figure 5. Power-Up Reset Timing
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1024 System Clock Periods
Required for Initialization
SCKI
Internal
Reset
0V
0V
0V
tRSTL> 40ns
RST
Internal
Reset
Analog
Outputs Outputs are On Outputs are Muted
for 1024 SCKI Periods Outputs are OnOutputs are Muted
Initialization
Period
HI
LO
POWER-DOWN OPERATION
PCM4104-EP
SBAS419 JUNE 2007
Figure 6. External Reset Timing
Figure 7. Analog Output State for Reset Operations
The PCM4104 can be forced to a power-down state by applying a low level to the RST input for a minimum of65,536 system clock cycles. In power-down mode, all internal clocks are stopped, and analog outputs are set toa high-impedance state. The system clock can then be removed to conserve additional power. In the case ofsystem clock restart when exiting the power-down state, the clock should be restarted prior to a low-to-hightransition of the reset signal at the RST input. The low-to-high transition of the reset signal initiates a resetsequence, as described in the Reset Operation section of this data sheet.
In Software mode, two additional power-down controls are provided. The PDN12 and PDN34 bits are located inControl Register 6 and may be used to power-down channel pairs, with PDN12 corresponding to channels 1 and2, and PDN34 corresponding to channels 3 and 4. This allows the user to conserve power when a channel pairis not in use. The power-down function is the same as described in the previous paragraph for thecorresponding channel pair. Unlike the power-down function implemented using the RST input, setting apower-down bit will immediately power down the corresponding channel pair.
When exiting power-down mode, either by forcing the RST input high or by setting the PDN12 or PDN34 bitslow, the analog outputs will transition from the high-impedance state to the mute state, with the output level setto the bipolar zero voltage. There may be a small transient created by this transition, since internal capacitorcharge can initially force the output to a voltage above or below bipolar zero, or external circuitry can pull theoutputs to some other voltage level. Figure 8 illustrates the state of the analog outputs before, during, and aftera power-down event.
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Analog
Outputs
65,536
SCKI Periods
Outputs are On
Outputs are
Muted
RST
0V
VDD
Analog
Outputs
1024
SCKI Periods
Required for
Initialization
1024
SCKI Periods
Required for
Initialization
Outputs are On
Outputs are On
Outputs are On
Outputs are
High Impedance
Outputs are
High Impedance
Outputs Transition
from High Impedance
to Muted State
Outputs Transition
from High Impedance
to Muted State
PDN12
PDN34 LO
HI
Outputs are On
Transitioning
to Driven State
AUDIO SERIAL PORT
LRCK
BCK
DATA0
DATA1
FSX
CLKX
DX0
DX1
System Clock
PCM4104
DSP
SCKI
PCM4104-EP
SBAS419 JUNE 2007
Figure 8. Analog Output State for Power-Down Operations
The audio serial port provides a common interface to digital signal processors, digital interface receivers (AES3,S/PDIF), and other digital audio devices. The port operates as a slave to the processor, receiver, or other clockgeneration circuitry. Figure 9 illustrates a typical audio serial port connection to a processor or receiver. Theaudio serial port is comprised of four signal pins: BCK (pin 15), LRCK (pin 16), DATA0 (pin 17), and DATA1 (pin18).
Figure 9. Audio Serial Port Connections for Left Justified, Right Justified, and I
2
S Formats
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MSB LSB MSB LSB
M S B LSB MSB LSB
LSBMSB LSBMSB
LRCK
BCK
DATA0
DATA1
LRCK
BCK
DATA0
DATA1
LRCK
BCK
DATA0
DATA1
(a) Left−Justified Data Format
(b) Right−Justified Data Format
(c) I2S Data Format
1/fS
Ch. 1 (DATA0) or Ch. 3 (DATA1) Ch. 2 (DATA0) or Ch. 4 (DATA1)
PCM4104-EP
SBAS419 JUNE 2007
The LRCK pin functions as either the left/right word clock or the frame synchronization clock, depending uponthe data format selected. The LRCK frequency is equal to the input sampling frequency (44.1 kHz, 48 kHz, 96kHz, etc.).
The BCK pin functions as the serial data clock input. This input is referred to as the bit clock. The bit clock runsat an integer multiple of the input sampling frequency. Typical multiples include 32, 48, 64, 96, 128, 192, and256, depending upon the data format, word length, and system clock frequency selected.
The DATA0 and DATA1 pins are the audio data inputs. When using Left Justified, Right Justified, or I
2
S dataformats, the DATA0 pin carries the audio data for channels 1 and 2, while the DATA1 pin carries the audio datafor channels 3 and 4. When using TDM data formats, DATA0 carries the audio data for all four channels, whilethe DATA1 input is ignored.
The audio serial port data formats are shown in Figure 10 ,Figure 13 , and Figure 14 . Data formats are selectedby using the FMT[2:0] bits in Control Register 7 in Software mode, or by using the FMT0 (pin 25), FMT1 (pin26), and FMT2 (pin 27) inputs in Standalone mode. In Software mode, the user may also select the phase(normal or inverted) for the LRCK input, as well as the data sampling edge for the BCK input (either rising orfalling edge). The reset default conditions for the Software mode are normal phase for LRCK and rising edgedata sampling for BCK.
The Left Justified, Right Justified, and I
2
S data formats are similar to one another, with differences in datajustification and word length. The PCM audio data must be two's complement binary, MSB first. Figure 10provides illustrations for these data formats.
The TDM formats carry the information for four or eight channels on a single data line. The DATA0 input (pin 17)is used as the data input for the TDM formats. The data is carried in a time division multiplexed fashion; hence,the TDM acronym used to describe this format. Figure 12 shows the TDM connection of two PCM4104 devices.The data for each channel is assigned one of the time slots in the TDM frame, as shown in Figure 13 andFigure 14 . The sub-frame assignment for each PCM4104 is determined by the state of the SUB input (pin 13).When SUB is forced low, the device is assigned to sub-frame 0. When SUB is forced high, the device isassigned to sub-frame 1.
Figure 10. Left Justified, Right Justified, and I
2
S Data Formats
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LRCK
BCK
(BCKE = 0)
DATA0
DATA1
tDS tDH
tBKLRD
BCK
(BCKE = 1)
tLRBKD
tBCKP
tBCKHL
PARAMETER DESCRIPTION MIN MAX UNITS
70 ns
30 ns
10 ns
10 ns
10 ns
10 ns
50 %
BCK Cycle Time
BCK High/Low Time
LRCK Edge to BCK Sampling Edge Delay
BCK Sampling Edge to LRCK Edge Delay
Data Setup Time
Data Hold Time
LRCK Duty Cycle
tBCKP
tBCKHL
tLRBKD
tBKLRD
tDS
tDH
PCM4104-EP
SBAS419 JUNE 2007
Figure 11. Audio Serial Port Timing for Left Justified, Right Justified, and I
2
S Data Formats
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System Clock
SUB
SUB
PCM4104
PCM4104
Device #1
(Sub−Frame 0)
Device #2
(Sub−Frame 1)
SCKI
VCC
FSX
CLKX
DX
LRCK
BCK
DATA0
LRCK
BCK
DATA0
DSP
SCKI
LRCK
Normal, Zero BCK Delay
LRCK
Normal, One BCK Delay
LRCK
Inverted, Zero BCK Delay
LRCK
Inverted, One BCK Delay
DATA0
Supports 8 Channels, or
two PCM4104 devices. Slot 1 Slot 2 Slot 3 Slot 4 Slot 5 Slot 6 Slot 7 Slot 8
Ch. 1 Ch. 2 Ch. 3 Ch. 4 Ch. 1 Ch. 2 Ch. 3 Ch. 4
Sub−Frame 0
(SUB = 0) Sub−Frame 1
(SUB = 1)
One Frame
BCK = 192fSor 256fS
In the case of BCK = 192fS, each time slot is 24 bits long and contains the 24−bit audio data for the corresponding channel.
In the case of BCK = 256fS, each time slot is 32 bits long and contains the 24−bit audio data for the corresponding channel.
The audio data is left justified in the time slot, with the the least significant 8 bits of each time slot being dont care bits.
Audio data is always presented in two’s complement, MSB−first format.
TDM Data Formats Long Frame
Supported for Single and Dual Rate Sampling Modes Only
PCM4104-EP
SBAS419 JUNE 2007
Figure 12. TDM Connection
Figure 13. TDM Data Formats: Long Frame
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Slot 1 Slot 2 Slot 3 Slot 4
Ch. 1 Ch. 2 Ch. 3 Ch. 4
In the case of BCK = 96fS, each time slot is 24 bits long and contains the 24−bit audio data for the corresponding channel.
In the case of BCK = 128fS, each time slot is 32 bits long and contains the 24−bit audio data for the corresponding channel.
The audio data is left justified in the time slot, with the the least significant 8 bits of each time slot being dont care bits.
Audio data is always presented in two’s complement, MSB−first format.
LRCK
Normal, Zero BCK Delay
LRCK
Normal, One BCK Delay
LRCK
Inverted, Zero BCK Delay
LRCK
Inverted, One BCK Delay
DATA0
Supports 4 Channels, or
one PCM4104 device.
One Frame
BCK = 96fSor 128fS
(the SUB pin is ignored when using a Short Frame)
TDM Data Formats Short Frame
All Sampling Modes Supported
LRCK
BCK
(BCKE = 0)
DATA0
tDS tDH
tLRBKD
tLRCKP tBNF
tBKBF
One Frame
BCK
(BCKE = 1)
PARAMETER DESCRIPTION MIN MAX UNITS
1/fBCK
1/fBCK
12
10
10
12
ns
ns
ns
ns
ns
ns
tLRCKP
tLRBKD
tDS
tDH
tBNF
tBKBF
LRCK pulse width
LRCK active edge to BCK sampling edge delay
Data setup time
Data hold time
LRCK transition before new frame
BCK sampling edge to new frame delay
PCM4104-EP
SBAS419 JUNE 2007
Figure 14. TDM Data Formats: Short Frame
Figure 15. TDM Timing
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STANDALONE MODE CONFIGURATION
Sampling Mode
Audio Data Format
Soft Mute Function
PCM4104-EP
SBAS419 JUNE 2007
Standalone mode is selected by forcing the MODE input (pin 8) low. Standalone mode operation provides asubset of the functions available in Software mode, while providing an option for a simplified control model.Standalone configuration is accomplished by either hardwiring or driving a small set of input pins with externallogic or switches. Standalone mode functions include sampling mode and audio data format selection, anall-channel soft mute function, and digital de-emphasis filtering. The following paragraphs provide a briefdescription of each function available when using Standalone mode.
The sampling mode is selected using the FS0 (pin 28) and FS1 (pin 29) inputs. A more detailed discussion ofthe sampling modes was provided in an earlier section of this data sheet. Table 2 summarizes the samplingmode configuration for Standalone mode.
Table 2. Sampling Mode Configuration
FS1 FS0 SAMPLING MODE
0 0 Single Rate0 1 Dual Rate1 0 Quad Rate1 1 - Not Used -
The audio data format is selected using the FMT0 (pin 25), FMT1 (pin 26), and FMT2 (pin 27) inputs. A detaileddiscussion of the audio serial port operation and the corresponding data formats was provided in the AudioSerial Port section on page 19. For Standalone mode, the LRCK polarity is always normal, while the serial audiodata is always sampled on the rising edge of the BCK clock. Table 3 shows the audio data format configurationfor Standalone mode.
Table 3. Audio Data Format Configuration
FMT2 FMT1 FMT0 AUDIO DATA FORMAT
0 0 0 24-bit left justified0 0 1 24-bit I2S0 1 0 TDM with zero BCK delay0 1 1 TDM with one BCK delay1 0 0 24-bit right justified1 0 1 20-bit right justified1 1 0 18-bit right justified1 1 1 16-bit right justified
The MUTE input (pin 10) may be used in either the Standalone or Software modes to simultaneously mute thefour output channels. The soft mute function slowly ramps the digital output attenuation from its current setting tothe mute level, minimizing or eliminating audible artifacts. Table 4 summarizes MUTE function operation.
Table 4. Mute Function Configuration
MUTE ANALOG OUTPUTS
0 On (mute disabled)1 Muted
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Digital De-Emphasis
SOFTWARE MODE CONFIGURATION
Digital Attenuation
Digital De-Emphasis
Soft Mute
Zero Data Mute
PCM4104-EP
SBAS419 JUNE 2007
This is a global digital function (common to all four channels) and provides de-emphasis of the higher frequencycontent within the 20-kHz audio band. De-emphasis is required when the input audio data has beenpre-emphasized. Pre-emphasis entails increasing the amplitude of the higher frequency components in the20-kHz audio band using a standardized filter function in order to enhance the high-frequency response. ThePCM4104 de-emphasis filters implement the standard 50/15 μs de-emphasis transfer function commonly used indigital audio applications.
De-emphasis filtering is available for three input sampling frequencies in Single Rate sampling mode: 32 kHz,44.1 kHz, and 48 kHz. De-emphasis is not available when operating in Dual or Quad Rate sampling modes. Thede-emphasis filter is selected using the DEM0 (pin 12) and DEM1 (pin 11) inputs. Table 5 illustrates thede-emphasis filter configuration for Standalone mode.
Table 5. Digital De-Emphasis Configuration
DEM1 DEM0 DIGITAL DE-EMPHASIS MODE
0 0 Off (de-emphasis disabled)0 1 48 kHz1 0 44.1 kHz1 1 32 kHz
Software mode is selected by forcing the MODE input(pin 8) high. Software mode operation provides full accessto the features of the PCM4104 by allowing the writing and reading of on-chip control registers. This isaccomplished using the four-wire SPI port. The following paragraphs provide a brief description of each functionavailable when using Software mode.
The audio signal for each channel can be attenuated in the digital domain using this function. Attenuationsettings from 0 dB (unity gain) to –119.5 dB are provided in 0.5 dB steps. In addition, the attenuation level maybe set to the mute state. The rate of change for the digital attenuation function is one 0.5 dB step for every eightLRCK periods. Each channel has its own independent attenuation control, accessed using control registers 1through 4. The reset default setting for all channels is 0 dB, or unity gain (no attenuation applied).
The de-emphasis function is accessed through Control Register 5 using the DEM[1:0] bits. The reset defaultsetting is that the de-emphasis is disabled for all four channels. De-emphasis filter operation is described in theStandalone Mode Configuration section of this data sheet.
Each of the four D/A converter channels has its own independent soft mute control, located in Control Register5.
The reset default is normal output for all four channels with the soft mute function disabled. The MUTE input (pin10) also functions in Software mode, with a high input forcing soft mute on all four channels.
The PCM4104 includes a zero data detection and mute function in Software mode. This function automaticallymutes a given channel when 1024 consecutive LRCK periods of all zero data are detected for that channel. Thezero data mute function is enabled and disabled using the ZDM bit in Control Register 5. The zero data mutefunction is disabled by default on power up or reset.
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Output Phase Reversal
Sampling Mode
Power-Down Modes
Software Reset
Audio Data Formats, LRCK Polarity, and BCK Sampling Edge
SERIAL PERIPHERAL INTERFACE (SPI) PORT OPERATION
Control Byte (or Byte 0)
PCM4104-EP
SBAS419 JUNE 2007
The PCM4104 includes an output phase reversal function, which provides the ability to invert the output phasefor all four channels, either for testing or for matching various output circuit configurations. This function iscontrolled using the PHASE bit, located within Control Register 5. The output phase is set to noninverted bydefault on power up or reset.
Sampling mode configuration was discussed earlier in this data sheet, with Table 1 providing a reference forcommon sampling and system clock frequencies. The FS0 and FS1 bits located in Control Register 6 are usedto set the sampling mode. The sampling mode defaults to Single Rate on power up or reset.
The power-down control bits are located in Control Register 6. These bits are used to power down pairs of D/Aconverters within the PCM4104. The PDN12 bit is used to power down channels 1 and 2, while the PDN34 bit isused to power down channels 3 and 4. When a channel pair is powered down, it ignores the audio data inputsand sets its outputs to a high-impedance state. By default, the power-down bits are disabled on power up orreset.
This reset function allows a reset sequence to be initiated under software control. All control registers are resetto their default state. The reset bit, RST, is located in Control Register 6. Setting this bit to 1 initiates a one-timereset sequence. The RST bit is cleared by the initialization sequence.
Control Register 7 is used to configure the PCM4104 audio serial port. Audio serial port operation wasdiscussed previously in this data sheet; refer to that section for more details regarding the functions controlled bythis register. The control register definitions provide additional information regarding the register functions andtheir default settings.
The SPI port is a four-wire synchronous serial interface that is used to access the on-chip control registers whenthe PCM4104 is configured for Software mode operation. The CDIN input (pin 23) is the serial data input for theport, while CDOUT (pin 24) is used for reading back control register contents in a serial fashion. The CS input(pin 21) functions as the chip select input, and must be forced low for register write or read access. The CCLKinput (pin 22) functions as the serial data clock, used to clock data in and out of the port. Data is clocked into theport on the rising edge of CCLK, while data is clocked out of the port on the falling edge of CCLK.
There are three modes of operation supported for the SPI port: Single Register, Continuous, andAuto-Increment.
The Single Register and Continuous modes are similar to one another. In Continuous mode, instead of bringingthe CS input high after writing or reading a single register, the CS input is held low and a new control byte isissued with a new address for the next write or read operation. Continuous mode allows multiple, sequential ornonsequential register addresses to be read or written in succession, as shown in Figure 16 .
Auto-Increment mode is designed for writing or reading multiple sequential register addresses. After the firstregister is written or read, the register address is automatically incremented by 1, so the next write or readoperation is performed without issuing another control byte, as shown in Figure 17 .
The control byte, or byte 0, is the first byte written to the PCM4104 SPI port when performing a write or readoperation. The control byte includes bits that define the operation to be performed (read or write), theauto-increment mode status, and the control register address.
The Read/Write bit, R/ W, is set to 0 to indicate a register write operation, or set to 1 for a register readoperation.
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CS
CDIN
CCLK
Set CS = 1 here for Single Register Operations Keep CS = 0 for writing or reading multiple registers in Continuous mode
byte 0 byte 1 byte 0 byte 1 byte N
Auto Increment Control: Set to 0 for Single Register or Continuous Operation
Read/WriteControl: 0 = Write
1 = Read
Register DataControl Byte Register DataControl Byte
CDOUT High Impedance byte 1 High Impedance byte 2 byte N
Register Data Register Data
R/W INC 1 0 A3 A2 A1 A0
Register Address
MSB LSB
Control Byte Definition (Byte 0)
PCM4104-EP
SBAS419 JUNE 2007
The Increment bit, INC, enables or disables the Auto-Increment mode of operation. When this bit is set to a 0,auto-increment operation is disabled, and the operation performed is either Single Register or Continuous.Setting the INC bit to 1 enables Auto-Increment operation.
A two-bit key code, 10
B
, follows the INC bit and must be present in order for any operation to take place on thecontrol port. Any other combination for these bits will result in the port ignoring the write or read request.
The four-bit address field, A[3:0], is used to specify the control register address for the read or write operation, orthe starting address for an Auto-Increment write or read operation.
Figure 16. Single Register and Continuous Write or Read Operation
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CS
CDIN
CCLK
Keep CS = 0 for Auto−Increment Operation
byte 0 byte 1 byte 2 byte 3 byte N
R/W INC 1 0 A3 A2 A1 A0
Auto−Increment Control: Set to 1 for Auto−Increment Operation
Read/WriteControl: 0 = Write
1 = Read
MSB LSB
Control Byte Definition (Byte 0)
Register DataControl Byte
CDOUT High Impedance byte 1 byte 2 byte 3 byte N
Register Data
Register Address
High Impedance (Hi Z) Hi Z
CCLK
CDIN
CDOUT
MSB
MSB LSB
tDO
tDS tDH tCH
tCSZ
PARAMETER DESCRIPTION MIN MAX UNIT
CDIN Data Setup Time 5
2
2
5
5
ns
CDIN Data Hold Time ns
Hold Time ns
CDOUT Data Delay Time ns
High to CDOUT Hi Z
tDS
tDH
tCH
tDO
tCSZ ns
CS
CS
CS
PCM4104-EP
SBAS419 JUNE 2007
Figure 17. Auto-Increment Write or Read Operation
Figure 18. SPI Port Timing
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CONTROL REGISTER DEFINITIONS (Software Mode Only)
Register 1: Attenuation Control Register Channel 1
Register 2: Attenuation Control Register Channel 2
Register 3: Attenuation Control Register Channel 3
PCM4104-EP
SBAS419 JUNE 2007
The PCM4104 includes a small set of control registers, which are utilized to configure the full set of on-chipfunctions in Software mode. The register map is shown in Table 6 . Register 0 is reserved for factory use andshould not be written to for normal operation. Register 0 defaults to all zero data on power up or reset.
Table 6. Control Register Map
CONTROL
REGISTER MSB LSBBIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1ADDRESS BIT 7 BIT 0(Hex)
0 0 0 0 0 0 0 0 01 AT17 AT16 AT15 AT14 AT13 AT12 AT11 AT102 AT27 AT26 AT25 AT24 AT23 AT22 AT21 AT203 AT37 AT36 AT35 AT34 AT33 AT32 AT31 AT304 AT47 AT46 AT45 AT44 AT43 AT42 AT41 AT405 MUT4 MUT3 MUT2 MUT1 ZDM PHASE DEM1 DEM06 RST 0 0 0 PDN34 PDN12 FS1 FS07 0 0 BCKE LRCKP 0 FMT2 FMT1 FMT0
BIT 7 (MSB) BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 (LSB)
AT17 AT16 AT15 AT14 AT13 AT12 AT11 AT10
This register controls the digital output attenuation for Channel 1.
Default: AT1[7:0] = 255, or 0 dB
Let N = AT1[7:0].
For N = 16 to 255, Attenuation (dB) = 0.5 ×(255 N)
or N = 0 to 15, Attenuation (dB) = Infinite (Muted)
BIT 7 (MSB) BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 (LSB)
AT27 AT26 AT25 AT24 AT23 AT22 AT21 AT20
This register controls the digital output attenuation for Channel 2.
Default: AT2[7:0] = 255, or 0 dB
Let N = AT2[7:0].
For N = 16 to 255, Attenuation (dB) = 0.5 ×(255 N)
or N = 0 to 15, Attenuation (dB) = Infinite (Muted)
BIT 7 (MSB) BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 (LSB)
AT37 AT36 AT35 AT34 AT33 AT32 AT31 AT30
This register controls the digital output attenuation for Channel 3.
Default: AT3[7:0] = 255, or 0 dB
Let N = AT3[7:0].
For N = 16 to 255, Attenuation (dB) = 0.5 ×(255 N)
or N = 0 to 15, Attenuation (dB) = Infinite (Muted)
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Register 4: Attenuation Control Register Channel 4
Register 5: Function Control Register
DEM[1:0] Digital De-Emphasis
PHASE Output Phase
ZDM Zero Data Mute
MUT[4:1] Soft Mute
PCM4104-EP
SBAS419 JUNE 2007
BIT 7 (MSB) BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 (LSB)
AT47 AT46 AT45 AT44 AT43 AT42 AT41 AT40
This register controls the digital output attenuation for Channel 4.
Default: AT4[7:0] = 255, or 0 dB
Let N = AT4[7:0].
For N = 16 to 255, Attenuation (dB) = 0.5 ×(255 N)
or N = 0 to 15, Attenuation (dB) = Infinite (Muted)
BIT 7 (MSB) BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 (LSB)
MUT4 MUT3 MUT2 MUT1 ZDM PHASE DEM1 DEM0
This register controls various D/A converter functions, including de-emphasis filtering, output phase reversal,zero data mute, and per-channel soft muting.
De-emphasis is available for Single Rate mode only.
De-emphasis is disabled for Dual and Quad Rate modes.
DEM1 DEM0 De-Emphasis Selection0 0 De-emphasis disabled (default)0 1 De-emphasis for f
S
= 48 kHz1 0 De-emphasis for f
S
= 44.1 kHz1 1 De-emphasis for f
S
= 32 kHz
PHASE Output Phase0 Noninverted (default)1 Inverted
ZDM Zero Mute0 Disabled (default)1 Enabled
MUTx D/A Converter Output0 On (default)1 MutedNOTE: x = channel number.
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Register 6: System Control Register
FS[1:0] Sampling Mode
PDN12 Power-Down for Channels 1 and 2
PDN34 Power-Down for Channels 3 and 4
RST Software Reset (value defaults to 0)
PCM4104-EP
SBAS419 JUNE 2007
BIT 7 (MSB) BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 (LSB)
RST 0 0 0 PDN34 PDN12 FS1 FS0
This register controls various system level functions of the PCM4104, including sampling mode, power down,and soft reset.
FS1 FS0 Sampling Mode0 0 Single Rate (default)0 1 Dual Rate1 0 Quad Rate1 1 - Not Used -
PDN12 Power Down For Channels 1 And 20 Disabled (default)1 Enabled
PDN34 Power Down For Channels 3 And 40 Disabled (default)1 Enabled
Setting this bit to 1 will initiate a logic reset of the PCM4104. This bit functions the same as an external resetapplied at the RST input (pin 9).
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Register 7: Audio Serial Port Control Register
FMT[2:0] Audio Data Format
PCM4104-EP
SBAS419 JUNE 2007
BIT 7 (MSB) BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 (LSB)
0 0 BCKE LRCKP 0 FMT2 FMT1 FMT0
This register is used to control the data format and clock polarity for the PCM4104 audio serial port.
FMT2 FMT1 DEM0 Data Format0 0 0 24-bit left justified (default)0 0 1 24-bit I
2
S0 1 0 TDM with zero BCK delay0 1 1 TDM with one BCK delay1 0 0 24-bit right justified1 0 1 20-bit right justified1 1 0 18-bit right justified1 1 1 16-bit right justified
LRCKP LRCK Polarity (0 = Normal, 1 = Inverted). Defaults to 0.
BCKE BCK Sampling Edge (0 = Rising Edge, 1 = Falling Edge), Defaults to 0.
32
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APPLICATION INFORMATION
Basic Circuit Configurations
Analog Output Filter Circuits
PCM4104-EP
SBAS419 JUNE 2007
This section provides practical information for system and hardware engineers that are designing in thePCM4104.
Figure 19 and Figure 20 show typical circuit configurations for the PCM4104 operated in Standalone andSoftware modes. Power supply bypass and reference decoupling capacitors should be placed as close to thecorresponding PCM4104 pins as possible. A common ground is shown in both figures, with the analog anddigital ground pins connected to a common plane. Separate power supplies are utilized for the analog and digitalsections, with 5 V required for the PCM4104 analog supplies and 3.3 V required for the digital supply.
The 5 V analog supply may be derived from a higher valued, positive analog power supply using a linear voltageregulator, such as the REG103 available from Texas Instruments. The 3.3 V digital supply can be derived from aprimary 5 V digital supply using a linear voltage regulator, such as the REG1117, also from TI. ThePCM4104EVM evaluation module provides an example of how the common ground with separate supplyapproach can be successfully implemented. The PCM4104EVM User's Guide includes schematics and PCBlayout plots for reference. The evaluation module is available through Texas Instruments' distributors and salesrepresentatives, or may be ordered online through the TI eStore, which can be accessed through the TI homepage at http://www.ti.com.
The master clock generator supplies the system clock for the PCM4104, as well as the audio data source, suchas a digital signal processor. The LRCK and BCK audio clocks should be derived from the system clock, in orderto ensure synchronous operation.
An external output filter is recommended for each differential output pair. The external output filter furtherreduces the out-of-band noise energy produced by the delta-sigma modulator, while providing band limitingsuitable for audio reproduction. A 2nd-order Butterworth low-pass filter circuit with a –3 dB corner frequencyfrom 50 kHz to 180 kHz is recommended.
The configuration of the output filter circuit is dependent upon whether a single-ended or differential output isrequired. Single-ended outputs are commonly used in consumer playback systems, while differential or balancedoutputs are used in many professional audio applications, such as recording or broadcast studios and live soundsystems.
Figure 21 illustrates an active filter circuit that uses a single op amp to provide both 2nd-order low-pass filteringand differential to single-ended signal conversion. This circuit is used on the PCM4104EVM evaluation circuitand meets the published typical Electrical Characteristics for dynamic performance. The single-ended output isconvenient for connecting to both headphone and power amplifiers when used for listening tests.
The quality of the op amp used is this circuit is important, as many devices will degrade the dynamic rangeand/or total harmonic distortion plus noise (THD+N) specifications for the PCM4104. An NE5534A is shown inFigure 21 and provides both low noise and distortion. Bipolar input op amps with equivalent specificationsshould produce similar measurement results. Devices that exhibit higher equivalent input noise voltage, such asthe Texas Instruments OPA134 or OPA604 families, will produce lower dynamic range measurements(approximately 1 dB to 2 dB lower than the typical PCM4104 specification), while having little or no impact onthe THD+N specification when measuring a full-scale output level.
Figure 22 illustrates a fully-differential output filter circuit suitable for use with the PCM4104. The OPA1632 fromTexas Instruments provides the fully differential signal path in this circuit. The OPA1632 features very low noiseand distortion, making it suitable for high-end audio applications.
Texas Instruments provides a free software tool, FilterProt, used to assist in the design of active filter circuits.The software supports design of multiple feedback (MFB), Sallen-Key, and fully differential filter circuits. FilterProis available from the TI web site. Additionally, TI document number SBAF001A, also available from the TI website, provides pertinent application information regarding the proper usage of the FilterPro program.
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36
35
34
33
32
31
30
29
28
27
26
25
VOUT4+
VOUT4
AGND2
VREF4
VREF4+
NC
NC
FS1
FS0
FMT2
FMT1
FMT0
VCOM1
VOUT2+
VOUT2
VCC1
VREF2+
VREF2
VREF3
VREF3+
VCC2
VOUT3
VOUT3+
VCOM2
SUB
SCKI
BCK
LRCK
DATA0
DATA1
VDD
DGND
CS
CCLK
CDIN
CDOUT
1
2
3
4
5
6
7
8
9
10
11
12
VOUT1+
VOUT1
AGND1
VREF1
VREF1+
NC
NC
MODE
RST
MUTE
DEM1
DEM0
48 47 46 45 44 43 42 41 40 39 38
13 14 15 16 17 18 19 20 21 22 23
37
24
PCM4104
Audio Data Source
Master
Clock
Generator
From
Logic,
µP,
or DSP
From
Logic,
µP,
or DSP
To Analog Output Filters(1)
(2)
(2)
0.1µF 10µF
+5.0V
Pin 40 Pin 45 +
0.1µF 10µF
+
(2)
+3.3V
Pin 19 0.1µF 10µF
+
(1) Refer to and in this document.
(2) Refer to in this document for external connection requirements.
NO TAG NO TAG
NO TAG
PCM4104-EP
SBAS419 JUNE 2007
APPLICATION INFORMATION (continued)
Figure 19. Typical Standalone Mode Configuration
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36
35
34
33
32
31
30
29
28
27
26
25
VOUT4+
VOUT4
AGND2
VREF4
VREF4+
NC
NC
FS1
FS0
FMT2
FMT1
FMT0
VCOM1
VOUT2+
VOUT2
VCC1
VREF2+
VREF2
VREF3
VREF3+
VCC2
VOUT3
VOUT3+
VCOM2
SUB
SCKI
BCK
LRCK
DATA0
DATA1
VDD
DGND
CS
CCLK
CDIN
CDOUT
1
2
3
4
5
6
7
8
9
10
11
12
VOUT1+
VOUT1
AGND1
VREF1
VREF1+
NC
NC
MODE
RST
MUTE
DEM1
DEM0
48 47 46 45 44 43 42 41 40 39 38
13 14 15 16 17 18 19 20 21 22 23
37
24
PCM4104
Audio Data Source
Master
Clock
Generator
From
Logic or
Host Control
To Analog Output Filters(1)
(2)
(2)
0.1µF 10µF
+5.0V
Pin 40 Pin 45 +
0.1µF 10µF
+
Host Control
(2)
+3.3V
+3.3V
Pin 19 0.1µF 10µF
+
(1) Refer to and in this document.
(2) Refer to in this document for external connection requirements.
NO TAG NO TAG
NO TAG
PCM4104-EP
SBAS419 JUNE 2007
APPLICATION INFORMATION (continued)
Figure 20. Typical Software Mode Configuration
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499
604
1k
100
Filtered
Output
RCA or 1/4−inch
Phone Jack
NE5534A
PCM4104
560pF
100µF
499
1k560pF
604
100µF2200pF22pF
0.1µF
10µF
+12V
VOUTn
VOUTn+
n = 1, 2, 3, or 4
2
3
7
6
4
10µF
0.1µF
12V
+
+
+
+
PCM4104-EP
SBAS419 JUNE 2007
APPLICATION INFORMATION (continued)
Figure 21. Single-Ended Output Filter Circuit
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499
604100
100
1k
1k
Filtered
Output
Male XLR
Connector
OPA1632
PCM4104
560pF
560pF
100µF
499
604
100µF2200pF22pF
0.1µF
10µF15V
VOUTn
VOUTn+
n = 1, 2, 3, or 4
2
1
8EN
VOCM 2
31
7
6
3
4
5
0.1µF
10µF
+15V
+
+
+
+
PCM4104-EP
SBAS419 JUNE 2007
APPLICATION INFORMATION (continued)
Figure 22. Differential Output Filter Circuit
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PACKAGE OPTION ADDENDUM
www.ti.com 15-Dec-2016
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
V62/07643-01XE OBSOLETE TQFP PFB 48 TBD Call TI Call TI -40 to 85 PCM4104EP
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com 15-Dec-2016
Addendum-Page 2
OTHER QUALIFIED VERSIONS OF PCM4104-EP :
Catalog: PCM4104
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
MECHANICAL DATA
MTQF019A – JANUARY 1995 – REVISED JANUARY 1998
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
PFB (S-PQFP-G48) PLASTIC QUAD FLATPACK
4073176/B 10/96
Gage Plane
0,13 NOM
0,25
0,45
0,75
Seating Plane
0,05 MIN
0,17
0,27
24
25
13
12
SQ
36
37
7,20
6,80
48
1
5,50 TYP
SQ
8,80
9,20
1,05
0,95
1,20 MAX 0,08
0,50 M
0,08
0°–7°
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026
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