dsPIC30F3014/4013
DS70138F-page 216 © 2008 Microchip Technology Inc.
Data Address Space...........................................................28
Alignment....................................................................30
Alignment (Figure) ......................................................30
Effect of Invalid Memory Accesses (Table).................30
MCU and DSP (MAC Class)
Instructions Example...........................................29
Memory Map...............................................................28
Near Data Space ........................................................31
Softwa re Stack....... ............... ........................... ...........31
Spaces........................................................................30
Width...........................................................................30
Data Converter Interface (DCI) Module ............................119
Data EEPROM Memory......................................................47
Erasing........................................................................48
Erasing, Block.............................................................48
Erasing, Word.............................................................48
Protection Agains t Spurious Write....... ..................... ..51
Reading.......................................................................47
Write Verify .................................................................51
Writing.........................................................................49
Writing , Block............. ..................... ..................... .......49
Writing , Wo rd ..... ............... ..................... .....................49
DC Characteristics............................................................169
BOR..........................................................................177
I/O Pin Input Specifications.......................................175
I/O Pin Output Specifications....................................175
Idle Current (IIDLE) ....................................................172
LVDL.........................................................................176
Operating Current (IDD).............................................171
Power-Down Current (IPD)........................................173
Program and EEPROM.............................................177
Temperature and Voltage Specifications..................169
DCI Module
Bit Clock Generator...................................................123
Buffer Alignment with Data Frames ..........................125
Buffe r Con trol...................... ..................... .................119
Buffe r Data Alignment............... ..................... ...........119
Buffer Length Control............................. .... .. .... .... .....125
COFS Pin............. ..................... ..................... ...........119
CSCK Pin............. ..................... ..................... ...........119
CSDI Pin.................... ............... ..................... ...........119
CSDO Mode Bit ........................................................126
CSDO Pin .................................................................119
Data Justification Control Bit.....................................124
Device Frequencies for Common Codec
CSCK Frequencies (Table)...............................123
Digital Loopback Mode .............................................126
Enable.......................................................................121
Frame Sync Generator .............................................121
Frame Sync Mode Control Bits.................................121
I/O Pi n s.................. ............................ .......................119
Interrupts...................................................................126
Introduction ...............................................................119
Master Frame Sync Operation..................................121
Operation ..................................................................121
Operation During CPU Idle Mode.............................126
Operation During CPU Sleep Mode..........................126
Receive Slot Enable Bits.................................... .. .....124
Receive Status Bits...................................................125
Register Map...... ............... ..................... ...................128
Sample Clock Edge Control Bit.................................124
Slave Frame Sync Operation....................................122
Slot Enable Bits Operation with Frame Sy nc............124
Slot Status Bits.............. ................................. ...........126
Synchronous Data Transfers ....................................124
Timing Requirements
AC-Link Mode................................................... 192
Multichannel, I2S Modes.................... .. ....... .. .. .. 190
Transmit Slot Enable Bits ......................................... 124
Transmit Status Bits.................................................. 125
Transmit/Receive Shift Register............................... 119
Underflow Mode Control Bit.................................. ....126
Word-Size Selection Bits.......................................... 121
Development Support.......................................................165
Device Configuration
Register Map ..... ..................... ..................... ............. 156
Device Configuration Registers
FBORPOR................................................................ 154
FGS .......................................................................... 154
FOSC........................................................................ 154
FWDT ....................................................................... 154
Device Overview................................................................... 9
Disabling the UART... ............... ......... ........ ........ ......... ...... 103
Divide Support .................. .... .. .... .... ....... .... .. .... .... ....... .... .... 16
Instructions (Table)..................................................... 16
DSP Engine ........................................................................ 17
Multiplier ..................................................................... 19
Dual Output Compare Match Mode.................................... 86
Continuous Pulse Mode............................... ......... .... .. 86
Single Pulse Mode......................................................86
E
Elect r i ca l C h a ra c t e r i stics ... .. ...... ...... ..... ...... .. ...... ..... ...... ... 169
AC............................................................................. 178
DC ............................................................................ 169
Enabling and Setting Up UART
Altern a te I/O ................. ........................... ................. 1 0 3
Enabling and Setting up UART
Setting up Data, Parity and
Stop Bit Selections ........................................... 103
Enabling the UART........................................................... 103
Equations
ADC Conversion Clock............................................. 131
Baud Rate................................................................. 105
Bit Clock Frequency.................................................. 123
COFSG Perio d...... ..................... . .................... .......... 121
Serial Clock Rate........................................................ 94
Time Quantum for Clock Generation........................ 115
Errata.................................................................................... 8
Exception Sequence
Trap Sou rces............................. ........................... ...... 62
Exter n a l C l o ck T iming Re quireme n t s ... ...... .......... ..... ...... . 179
Type A Timer............................................................ 185
Type B Timer............................................................ 186
Type C Timer............................................................ 186
External Interrupt Requests................................................ 64
F
Fast Context Saving ........................................................... 64
Flash Program Memory.. ........................... ......................... 41
I
I/0 Ports
Register Map ..... ..................... ..................... ............... 55
I/O Pin Specifications
Input.......................................................................... 175
Output....................................................................... 175
I/O Ports................................ .................................. ............ 53
Parallel (PIO).............................................................. 53