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L6388
May 2005
1 FEATURES
■HIGH VOLTAGE RAIL UP TO 600 V
■dV/dt IMMUNITY ± 50 V/nsec IN FULL
TEMPERATURE RANGE
■DRIVER CURRENT CAPABILITY:400 mA
SOURCE,650 mA SINK
■SWITCHING TIMES 70/40 nsec RISE/FALL
WITH 1nF LOAD
■3.3V, 5V, 15V CMOS/TTL INPUTS
COMPARATORS WITH HYSTERESYS AND
PULL DOWN
■INTERNAL BOOTSTRAP DIODE
■OUTPUTS IN PHASE WITH INPUTS
■DEAD TIME AND INTERLOCKING FUNCTION
2 DESCRIPTION
The L6388 is an high-voltage device, manufac-
tured with the BCD"OFF-LINE" technology.
It has a Driver structure that enables to drive inde-
pendent referenced N Channel Power MOS or IG-
BT. The Upper (Floating) Section is enabled to
work with voltage Rail up to 600V.
The Logic Inputs are CMOS/TTL compatible for
ease of interfacing with controlling devices.
HIGH-VOLTAGE HIGH AND LOW SIDE DRIVER
Figure 2. Block Diagram
LOGIC
UV
DETECTION
LEVEL
SHIFTER
BOOTSTRAP DRIVER
R
S
VCC
LVG
DRIVER
VCC
8
7
6
5
4
HIN
LIN
HVG
DRIVER HVG
H.V.
TO LOAD
OUT
LVG
GND
Vboot
3
2
1
Cboot
SHOOT
THROUGH
PREVENTION
UV
DETECTION R
Rev. 2
Fi
gure 1.
P
ac
k
age
Table 1. Order Codes
Part Number Package
L6388 DIP8
L6388D SO8
L6388D013TR SO8 in Tape & Reel
SO8 DIP8
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Table 2. Absolute Maximum Rating
Note: ESD immunity for pins 6, 7 and 8 is guaranteed up to 900V (Human Body Model)
Figure 3. Pin Connection (Top view)
Table 3. Pin Description
(*) The circuit guarantees 0.3V maximum on the pin (@ Isink = 10mA). This allows to omit the "bleeder" resistor connected between the gate
and the source of the external MOSFET normally used to hold the pin low.
Table 4. Thermal Data
Symbol Parameter Value Unit
Vout Output Voltage -3 to V
boot
- 18 V
Vcc Supply Voltage - 0.3 to +18 V
Vboot Floating Supply Voltage - 1 to 618 V
Vhvg High Side Gate Output Voltage - 1 to Vboot V
Vlvg Low Side Gate Output Voltage -0.3 to Vcc +0.3 V
ViLogic Input Voltage -0.3 to Vcc +0.3 V
dVout/dt Allowed Output Slew Rate 50 V/ns
Ptot Total Power Dissipation (Tj = 85°C) 750 mW
TjJunction Temperature 150 °C
Tstg Storage Temperature -50 to 150 °C
N. Name Type Function
1 LIN I Low Side Driver Logic Input
2 HIN I High Side Driver Logic Input
3 Vcc I Low Voltage Power Supply
4 GND Ground
5 LVG (*) O Low Side Driver Output
6 OUT O High Side Driver Floating Reference
7 HVG (*) O High Side Driver Output
8 Vboot Bootstrap Supply Voltage
Symbol Parameter SO8 Minidip Unit
Rth j-amb Thermal Resistance Junction to Ambient 150 100 °C/W
VCC
HIN
LIN
GND
1
3
2
4 LVG
OUT
HVG
Vboot
8
7
6
5
D97IN517A
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L6388
Table 5. Recommended Operating Conditions
Note 1: If the condition Vboot - Vout < 18V is guaranteed, Vout can range from -3 to 580V
(*): V
BS
= Vboot - Vout
Symbol Pin Parameter Test Condition Min. Typ. Max. Unit
Vout 6 Output Voltage Note 1 580 V
VBS (*) 8 Floating Supply Voltage Note 1 17 V
fsw Switching Frequency HVG,LVG load CL = 1nF 400 kHz
Vcc 3 Supply Voltage 17 V
TjJunction Temperature -45 125 °C
Table 6.
Electrical Characteristics
(V
cc
= 15V; T
j
= 25°C)
Symbol Pin Parameter Test Condition Min. Typ. Max. Unit
AC OPERATION
ton
1 vs 5
2 vs 7
High/Low Side Driver Turn-On
Propagation Delay
Vout = 0V 225 300 ns
toff High/Low Side Driver Turn-Off
Propagation Delay
Vout = 0V 160 220 ns
tr7,5 Rise Time CL = 1000pF 70 100 ns
tf7,5 Fall Time CL = 1000pF 40 80 ns
DT 7,5 Dead Time 220 320 420 ns
DC OPERATION
Low Supply Voltage Section
Vccth1 3V
cc UV Turn On Threshold 9.1 9.6 10.1 V
Vccth2 Vcc UV Turn Off Threshold 7.9 8.3 8.8 V
Vcchys Vcc UV Hysteresis 0.9 V
Iqccu Undervoltage Quiescent Supply
Current
Vcc ≤ 9V 250 330 µA
Iqcc Quiescent Current Vcc = 15V 350 450 µA
Rdson
Bootstrap Driver on Resistance
(**)
Vcc 125 Ω
Bootstrapped Supply Voltage Section
V
BSth1
8V
BS
UV Turn On Threshold 8.5 9.5 10.5 V
V
BSth2
V
BS
UV Turn Off Threshold 7.2 8.2 9.2 V
V
BShys
V
BS
UV Hysteresis 0.9 V
IQ
BS
V
BS
Quiescent Current HVG ON 250 µA
ILK High Voltage Leakage Current Vhvg = Vout = Vboot = 600V 10 µA
High/Low Side Driver
Iso 5,7 Source Short Circuit Current VIN = Vih (tp < 10µs) 300 400 mA
Isi Sink Short Circuit Current VIN = Vil (tp < 10µs) 500 650 mA
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(**) RDSON is tested in the following way:
where I1 is pin 8 current when VCBOOT = VCBOOT1, I2 when VCBOOT = VCBOOT2.
Figure 4. Dead Time Waveforms Definitions
Figure 5. Propagation Delay Waveform Definitions
Logic Inputs
Vil 1, 2 Low Level Logic Input Voltage 1.1 V
Vih High Level Logic Input Voltage 1.8 V
Iih High Level Logic Input Current VIN = 15V 20 70 µA
Iil Low Level Logic Input Current VIN = 0V -1 µA
Table 6.
Electrical Characteristics
(continued)
(V
cc
= 15V; T
j
= 25°C)
Symbol Pin Parameter Test Condition Min. Typ. Max. Unit
RDSON
VCC VCBOOT1
–()VCC VCBOOT2
–()–
I1VCC VCCBOOT1
,()I2
–VCC VCCBOOT2
,()
--------------------------------------------------------------------------------------------------------------=
DT DT
DT
LIN
HIN
LVG
HVG
Interlocking function
50%
50% 50%
> DT
50% 50%
10%
90%
ton
toff
> DT
10%
90%
ton
toff
LIN
HIN
LVG
HVG
50%50%
50% 50%50%
> DT
50% 50%50%
10%
90%
ton
toff
> DT
10%
90%
ton
toff
LIN
HIN
LVG
HVG
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L6388
3 INPUT LOGIC
Input logic is provided with an interlocking circuitry which avoids the two outputs (LVG, HVG) to be active at the
same time when both the logic input pins (LIN, HIN) are at a high logic level. In addition, to prevent cross con-
duction of the external MOSFETs, after each output is turned-off the other output cannot be turned-on before a
certain amount of time (DT) (see Figure 4).
Figure 6. Typical Rise and Fall Times vs. Load
Capacitance
Figure 7. Quiescent Current vs. Supply
Voltage
For both high and low side buffers @25˚C Tamb
0 1 2 3 4 5 C (nF)
0
50
100
150
200
250
time
(nsec)
Tr
D99IN1054
Tf
0246810121416V
S(V)
10
10
2
10
3
10
4
Iq
(µA)
D99IN1055
3.1 BOOTSTRAP DRIVER
A bootstrap circuitry is needed to supply the high voltage section. This function is normally accomplished by a
high voltage fast recovery diode (fig. 8a). In the L6388 a patented integrated structure replaces the external di-
ode. It is realized by a high voltage DMOS, driven synchronously with the low side driver (LVG), with in series
a diode, as shown in fig. 8b
An internal charge pump (fig. 8b) provides the DMOS driving voltage .
The diode connected in series to the DMOS has been added to avoid undesirable turn on of it.
3.2 CBOOT selection and charging
To choose the proper C
BOOT
value the external MOS can be seen as an equivalent capacitor. This capacitor
C
EXT
is related to the MOS total gate charge :
The ratio between the capacitors C
EXT
and C
BOOT
is proportional to the cyclical voltage loss .
It has to be:
CBOOT>>>CEXT
e.g.: if Q
gate
is 30nC and V
gate
is 10V, C
EXT
is 3nF. With C
BOOT
= 100nF the drop would be 300mV.
If HVG has to be supplied for a long time, the CBOOT selection has to take into account also the leakage losses.
e.g.: HVG steady state consumption is lower than 200
µ
A, so if HVG T
ON
is 5ms, CBOOT has to supply 1
µ
C to
C
EXT
. This charge on a 1
µ
F capacitor means a voltage drop of 1V.
The internal bootstrap driver gives great advantages: the external fast recovery diode can be avoided (it usually
has great leakage current). This structure can work only if V
OUT
is close to GND (or lower) and in the meanwhile
the LVG is on. The charging time (T
charge
) of the C
BOOT
is the time in which both conditions are fulfilled and it
CEXT
Qgate
Vgate
---------------=
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has to be long enough to charge the capacitor.
The bootstrap driver introduces a voltage drop due to the DMOS RDSON (typical value: 125 Ohm). At low fre-
quency this drop can be neglected. Anyway increasing the frequency it must be taken in to account.
The following equation is useful to compute the drop on the bootstrap DMOS:
where Q
gate
is the gate charge of the external power MOS, R
dson
is the on resistance of the bootstrap DMOS,
and T
charge
is the charging time of the bootstrap capacitor.
For example: using a power MOS with a total gate charge of 30nC the drop on the bootstrap DMOS is about
1V, if the T
charge
is 5
µ
s. In fact:
V
drop
has to be taken into account when the voltage drop on C
BOOT
is calculated: if this drop is too high, or the
circuit topology doesn't allow a sufficient charging time, an external diode can be used.
Figure 8. Bootstrap Driver.
Vdrop Ich earg Rdson Vdrop
→Qgate
Tch earg
--------------------Rdson
==
Vdrop
30nC
5µs
---------------125Ω0.8V∼⋅=
TO LOAD
H.V.
HVG
a
b
LVG
HVG
LVG
C
BOOT
TO LOAD
H.V.
C
BOOT
D
BOOT
V
BOOT
V
S
V
S
V
OUT
V
BOOT
V
OUT
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L6388
Figure 9. VBOOT UV Turn On Threshold vs.
Temperature
Figure 10. VBOOT UV Turn Off Threshold vs.
Temperature
Figure 11. VCC UV Turn On Threshold vs.
Temperature
Figure 12. VCC UV Turn Off Threshold vs.
Temperature
Figure 13. Output Source Current vs.
Temperature
Figure 14. Output Sink Current vs.
Temperature
-45 -25 0 25 50 75 100 125
5
6
7
8
9
10
11
12
13
VBSth1(V)
T
j
(
˚C
)
T
y
p.
@ Vcc = 15V
-45 -25 0 25 50 75 100 125
6
7
8
9
10
11
12
13
14
T
y
p.
@ Vcc = 15V
V
BSth2
(V)
-45 -25 0 25 50 75 100 125
7
8
9
10
11
12
13
Vccth1(V)
T
j
(
˚C
)
T
y
p.
-45 -25 0 25 50 75 100 125
6
7
8
9
10
11
Vccth2(V)
T
˚C
T
y
p.
-45-250 255075100125
0
200
400
600
800
1000
current (mA)
T
j
(
˚C
)
T
y
p.
@ Vcc = 15V
-45 -25 0 25 50 75 100 125
0
200
400
600
800
1000
current (mA)
T
j
(
˚C
)
T
y
p.
@ Vcc = 15V
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Figure 15. DIP8 Mechanical Data & Package Dimensions
OUTLINE AND
MECHANICAL DATA
DIM.
mm inch
MIN. TYP. MAX. MIN. TYP. MAX.
A3.32 0.131
a1 0.51 0.020
B 1.15 1.65 0.045 0.065
b 0.356 0.55 0.014 0.022
b1 0.204 0.304 0.008 0.012
D 10.92 0.430
E 7.95 9.75 0.313 0.384
e2.54 0.100
e3 7.62 0.300
e4 7.62 0.300
F 6.6 0.260
I 5.08 0.200
L 3.18 3.81 0.125 0.150
Z 1.52 0.060
DIP-8
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Figure 16. SO8 Mechanical Data & Package Dimensions
OUTLINE AND
MECHANICAL DATA
DIM.
mm inch
MIN. TYP. MAX. MIN. TYP. MAX.
A 1.35 1.75 0.053 0.069
A1 0.10 0.25 0.004 0.010
A2 1.10 1.65 0.043 0.065
B 0.33 0.51 0.013 0.020
C 0.19 0.25 0.007 0.010
D (1) 4.80 5.00 0.189 0.197
E 3.80 4.00 0.15 0.157
e 1.27 0.050
H 5.80 6.20 0.228 0.244
h 0.25 0.50 0.010 0.020
L 0.40 1.27 0.016 0.050
k 0˚ (min.), 8˚ (max.)
ddd 0.10 0.004
Note: (1) Dimensions D does not include mold flash, protru-
sions or gate burrs.
Mold flash, potrusions or gate burrs shall not exceed
0.15mm (.006inch) in total (both side).
SO-8
0016023 C
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Table 7. Revision History
Date Revision Description of Changes
January 2005 1 First Issue
May 2005 2 Changed from Preliminary Data to Final
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