MCP23016-I/SO - MICROCHIP

MCP23016

Features

• 16-bit remote bidirectional I/O port

- 16 I/O pins default to 16 inputs

•Fast I

2C™ bus clock frequency (0 - 400 kbits/s)

• Three hardware address pins allow use of up to

eight devices

• High-current drive capability per I/O: ±25 mA

• Open-drain interrupt output on input change

• Interrupt port capture register

• Internal Power-On Reset (POR)

• Polarit y i nv ersi on re gis te r to con fig ure the po lari ty

of the input port data

• Compatible with most microcontrollers

• Available temperature range:

- Industrial (I): -40°C to +85°C

CMOS Technology

• Operating Supply Voltage: 2.0V to 5.5V

• Low standby current

Packages

• 28-pin PDIP, 300 mil; 28-pin SOIC, 300 mil

• 28-pin SSOP, 209 mil; 28-pin QFN, 6x6 mm

Package Types

Block Diagram

Vss

GP1.0

GP1.1

GP1.2

GP1.3

INT

GP1.4

VSS

CLK

GP1.5

GP1.6

GP1.7

SCL

GP0.7

GP0.6

GP0.5

GP0.4

GP0.3

GP0.2

GP0.1

GP0.0

VDD

VSS

SDA

• 1

PDIP, SOIC, SSOP

QFN

GP1.2

GP1.3

INT

GP1.4

VSS

CLK

TP 15

21 GP0.3

GP0.2

GP0.1

GP0.0

VDD

VSS

GP1.5

GP1.6

GP1.7

SCL

SDA

232425262728 22

GP1.1

GP1.0

Vss

GP0.7

GP0.6

GP0.5

GP0.4

10118 9 121314

MCP23016

16 Bits GP0.0 to GP0.7

GP1.0 to GP1.7

Write pulse

Read pulse

Low Pass

Filter

Interrupt

Logic

I2C™ Bus

Control

Address

Decoder

Power-on

Reset

I/O

Port

Deserializer

Serializer/

Control

Clock

Gen

I2C™ Bus

Interface/

Protocol

Handler

INT

SCL

SDA

CLKIN

VDD

VSS Configuration

Registers Control

8-Bit

IARES

16-Bit I2C™ I/O Expander

MCP23016

NOTES:

MCP23016

1.0 DEVICE OVERVIEW

The MCP23016 device provides 16-bit, general

purpose, parallel I/O expansion for I2C bus

applications.

This device includes high-current drive capability, low

supply current and individual I/O configuration. I/O

expanders provide a simple solution when additional

I/Os are needed for ACPI, power switches, sensors,

push buttons, LEDs and so on.

The MCP23016 consists of multiple 8-bit configuration

registers for input, output and polarity selection. The

system master can enable the I/Os as either inputs or

outputs by writing the I/O configuration bits. The data

for each input or output is kept in the corresponding

input or output register. The polari ty of the re ad regist er

can be inve rted with the po lari ty inversi on regis ter (see

Section 1.7.3, “Input Polarity Registers”). All

registers can be read by the system master.

The open-drain interrupt output is activated when any

input state differs from its corresponding input port

master that an input state has changed. The interrupt

capture register captures port value at this time. The

Power-on Reset sets the registers to their default val-

ues and initializes the device state machine.

Three device inputs (A0 - A2) determine the I2C

address and allow up to eight I/O expander devices to

share the same I2C bus.

1.1 Pin Descriptions

TABLE 1-1: PINOUT DESCRIPTION

Pin Name

PDIP,

SOIC,

SSOP

Pin No.

QFN

Pin No. I/O/P

Type Buffer

Type Description

CLK 9 6 I ST Clock source input

TP 10 7 O — Test Pin (This pin must be left floating)

GP1.0 2 27 I/O TTL D0 digital input/output for GP1

GP1.1 3 28 I/O TTL D1 digital input/output for GP1

GP1.2 4 1 I/O TTL D2 digital input/output for GP1

GP1.3 5 2 I/O TTL D3 digital input/output for GP1

GP1.4 7 4 I/O TTL D4 digital input/output for GP1

GP1.5 11 8 I/O ST D5 digital input/output for GP1

GP1.6 12 9 I/O ST D6 digital input/output for GP1

GP1.7 13 10 I/O ST D7 digital input/output for GP1

GP0.0 21 18 I/O TTL D0 digital input/output for GP0

GP0.1 22 19 I/O TTL D1 digital input/output for GP0

GP0.2 23 20 I/O TTL D2 digital input/output for GP0

GP0.3 24 21 I/O TTL D3 digital input/output for GP0

GP0.4 25 22 I/O TTL D4 digital input/output for GP0

GP0.5 26 23 I/O TTL D5 digital input/output for GP0

GP0.6 27 24 I/O TTL D6 digital input/output for GP0

GP0.7 28 25 I/O TTL D7 digital input/output for GP0

SCL 14 11 I ST Serial clock input

SDA 15 12 I/O ST Serial data I/O

INT 6 3 O OD Interr upt out put

A0 16 13 I ST Address input 1

A1 17 14 I ST Address input 2

A2 18 15 I ST Address input 3

VSS 1, 8, 19 5, 16, 26 P — Ground reference for logic and I/O pins

VDD 20 17 P — Positive supply for logic and I/O pins

MCP23016

1.2 Power-on Reset (POR)

The on-chip POR circuit holds the chip in RESET until

VDD has reac hed a high eno ug h l eve l to d eac tivate the

POR circuit (i.e., release RESET). A maximum rise

time fo r VDD is specified in the electrical specifications.

When the device starts normal operation (exits the

RESET condition), device operating parameters

(voltage, frequency, temperature) must be met to

ensure proper operation.

1.3 Power-up Timer (PWRT)

The Power-up Timer provides a 72 ms nominal time-

out on power-up, keeping the device in RESET and

allowing VDD to rise to an acceptable level.

The power-up time delay will vary from chip-to-chip due

to VDD, temperature and process variation. See

Table 2-4 for details (TPWRT, parameter 3).

1.4 Clock Generator

The MCP23016 uses an external RC circuit to

determine the internal clock speed. The user must

connect R and C to the MCP23016, as shown in

Figure 1-1.

FIGURE 1-1: CLOCK CONFIGURATION

A 1 MHz (t yp.) i nternal clock is needed for the device to

function properly. The internal clock can be measured

on the TP pin. Recommended REXT and CEXT values

are shown in Table 1-2.

1.5 I2C Bus Interface/ Protocol

Handler

This block manages the functionality of the I2C bus

interface and protocol handling. The MCP23016

supports the following commands:

TABLE 1-3: COMMAND BYTE TO

1.6 Address Decoder

The last three LSb of the 7-bit add ress are user-defined

(see Table 1-4). Th ree hardware pin s (<A2:A0>) define

these bits.

TABLE 1-4: DEVICE ADDRESS

Internal Clock

MCP23016

VDD

REXT

CEXT

VSS

CLK

Note: Set IARES = 1 to measure the clock

output on TP.

TABLE 1-2: RECOMMENDED VALUES

REXT CEXT

3.9 kΩ33 pF

Command Byte Result

0h Access to GP0

1h Access to GP1

2h Access to OLAT0

3h Access to OLAT1

4h Access to IPOL0

5h Access to IPOL1

6h Access to IODIR0

7h Access to IODIR1

8h Access to INTCAP0 (Read-Only)

9h Access to INTCAP1 (Read-Only)

Ah Access to IOCON0

Bh Access to IOCON1

0100A2A1A0

MCP23016

1.7 Register Block

The register block contains the Configuration and Port registers, as shown in Table 1-5.

TABLE 1-5: REGISTER SUMMARY

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on

POR

Port Registers

GP0 GP0.7 GP0.6 GP0.5 GP0.4 GP0.3 GP0.2 GP0.1 GP0.0 0000 0000

GP1 GP1.7 GP1.6 GP1.5 GP1.4 GP1.3 GP1.2 GP1.1 GP0.0 0000 0000

OLAT0 OL0.7 OL0.6 OL0.5 OL0.4 OL0.3 OL0.2 OL0.1 OL0.0 0000 0000

OLAT1 OL1.7 OL1.6 OL1.5 OL1.4 OL1.3 OL1.2 OL1.1 OL1.0 0000 0000

Configuration Registers

IPOL0 IGP0.7 IGP0.6 IGP0.5 IGP0.4 IGP0.3 IGP0.2 IGP0.1 IGP0.0 0000 0000

IPOL1 IGP1.7 IGP1.6 IGP1.5 IGP1.4 IGP1.3 IGP1.2 IGP1.1 IGP1.0 0000 0000

IODIR0 IOD0.7 IOD0.6 IOD0.5 IOD0.4 IOD0.3 IOD0.2 IOD0.1 IOD0.0 1111 1111

IODIR1 IOD1.7 IOD1.6 IOD1.5 IOD1.4 IOD1.3 IOD1.2 IOD1.1 IOD1.0 1111 1111

INTCAP0 ICP0.7 ICP0.6 ICP0.5 ICP0.4 ICP0.3 ICP0.2 ICP0.1 ICP0.0 xxxx xxxx

INTCAP1 ICP1.7 ICP1.6 ICP1.5 ICP1.4 ICP1.3 ICP1.2 ICP1.1 ICP1.0 xxxx xxxx

IOCON0 — — — — — — — IARES ---- ---0

IOCON1 — — — — — — — IARES ---- ---0

Legend: ‘1’ bit is set, ‘0’ bit is cleared, x = unknown, — = unimplemented.

MCP23016

1.7.1 DATA PORT REGISTERS

Two registers provide access to the two GPIO ports:

• GP0 (provides access to data port GP0)

• GP1 (provides access to data port GP1)

A read from this register provides status on pins of

these ports. A write to these registers will modify the

output latch registers (OLA T0, OLA T1) and data output.

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

GP0.7GP0.6GP0.5GP0.4GP0.3GP0.2GP0.1GP0.0

bit 7 bit 0

bit 7-0 GP0.0:GP0.7: Reflects the logic level on the pins.

1 = Logic ‘1’

0 = Logic ‘0’

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

GP1.7GP1.6GP1.5GP1.4GP1.3GP1.2GP1.1GP1.0

bit 7 bit 0

bit 7-0 GP1.0:GP1.7: Reflects the logic level on the pins.

1 = Logic ‘1’

0 = Logic ‘0’

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

MCP23016

1.7.2 OUTPUT LATCH REGISTERS

Two registers provide access to the two port output

latches:

• OLAT0 (provides access to the output latch for

port GP0)

• OLAT1 (provides access to the output latch for

port GP1)

A read from these regist ers results i n a read of the l atch

that controls the output and not the actual port. A write

to these registers updates t he output latc h that con trols

the output.

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

OL0.7 OL0.6 OL0.5 OL0.4 OL0.3 OL0.2 OL0.1 OL0.0

bit 7 bit 0

bit 7-0 OL0.0:O0.7: Reflects the logic level on the output latch.

1 = Logic ‘1’

0 = Logic ‘0’

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

OL1.7 OL1.6 OL1.5 OL1.4 OL1.3 OL1.2 OL1.1 OL1.0

bit 7 bit 0

bit 7-0 OL1.0:O1.7: Reflects the logic level on the output latch.

1 = Logic ‘1’

0 = Logic ‘0’

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

MCP23016

1.7.3 INPUT POLARITY REGISTERS

These registers allow the user to configure the polarity

of the in put port da ta (GP0 and GP1). If a bit in this reg-

ister is set, the corresponding input port (GPn) data bit

polarity will be inverted.

• IPOL0 (controls the polarity of GP0)

• IPOL1 (controls the polarity of GP1)

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

IGP0.7 IGP0.6 IGP0.5 IGP0.4 IGP0.3 IGP0.2 IGP0.1 IGP0.0

bit 7 bit 0

bit 7-0 IGP0.0:IGP0.7: Controls the polarity inversion for the in put pins

1 = Corresponding GP0 bit is inverted

0 = Corresponding GP0 bit is not inverted

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

IGP1.7 IGP1.6 IGP1.6 IGP1.4 IGP1.3 IGP1.2 IGP1.1 IGP1.0

bit 7 bit 0

bit 7-0 IGP1.0:IGP1.7: Controls the polarity inversion for the input pins

1 = Corresponding GP1 bit is inverted

0 = Corresponding GP1 bit is not inverted

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

MCP23016

1.7.4 I/O DIRECTION REGISTERS

Two registers control the direction of data I/O:

• IODIR0 (controls GP0)

• IODIR1 (controls GP1)

When a bit in these registers is set, the corresponding

pin becomes an input. Otherwise, it becomes an

output. At Power-on Reset, the device ports are

configured as inputs.

R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1

IOD0.7 IOD0.6 IOD0.5 IOD0.4 IOD0.3 IOD0.2 IOD0.1 IOD0.0

bit 7 bit 0

bit 7-0 IOD0.0:IO0.7: Controls the direction of data I/O

1 = Input

0 = Output

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1

IOD1.7 IOD1.6 IOD1.5 IOD1.4 IOD1.3 IOD1.2 IOD1.1 IOD1.0

bit 7 bit 0

bit 7-0 IOD1.0:IO1.7: Controls the direction of data I/O

1 = Input

0 = Output

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

MCP23016

1.7.5 INTERRUPT CAPTURE REGISTERS

Two registers contain the value of the port that

generated the interrupt:

• INTCAP0 contains the value of GP0 at time of

GP0 change interrupt

• INTCAP1 contains the value of GP1 at time of

GP1 change interrupt

These registers are ‘read-only’ registers (A write to

these registers is ignored).

R-x R-x R-x R-x R-x R-x R-x R-x

ICP0.7 ICP0.6 ICP0.5 ICP0.4 ICP0.3 ICP0.2 ICP0.1 ICP0.0

bit 7 bit 0

bit 7-0 ICP0.0:ICP0.7: Reflects the logic level on the GP0 pins at the time of interrupt due to pin

change

1 = Logic ‘1’

0 = Logic ‘0’

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

R-x R-x R-x R-x R-x R-x R-x R-x

ICP1.7 ICP1.6 ICP1.5 ICP1.4 ICP1.3 ICP1.2 ICP1.1 ICP1.0

bit 7 bit 0

bit 7-0 ICP1.0:ICP1.7: Reflects the logic level on the GP1 pins at the time of interrupt due to pin

change

1 = Logic ‘1’

0 = Logic ‘0’

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

MCP23016

1.7.6 I/O EXPANDER CONTROL

• IOCON0 controls the functionality of the

MCP23016.

The IARES (Interrupt Activity Resolution) bit controls

the sam pling freque ncy of the GP port pins . The h igher

the sampling frequency, the higher the device current

requirements. If this bit is ‘0’ (default), the maximum

time to detect the activity on the port is 32 ms (max.),

which results in lower standby current. If this bit is ‘1’,

the maximum time to detect activity on the port is

200 µsec. (max.) and results in higher standby current.

U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0

——————— IARES

bit 7 bit 0

bit 1-7 Unimplemented bit: Read as ‘0’

bit 0 IARES: Interrupt Activity Resolution

1 = Fast sample rate

0 = Normal sample rate

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

IOCON1 is a shadow register for IOCON0. Access to IOCON1 results in access to IOCON0.

MCP23016

1.8 Serializer/Deserializer

The Serializer/Deserializer block converts and

transfers dat a betw e en the I2C bus and GPIO.

1.9 Interrupt Logic

The MCP2 3016 assert s the open -drain interrup t output

(INT) low when one of the port pins changes st ate. Only

those p ins that are c onfigured as an input can cause an

interrupt. Pins defined as an output have no effect on

INT. The interrupt will remain active until a read from

either th e port (GPn) o n which the i nterr upt oc curred or

the INTCAPn register is performed. If the input returns

to its pre vious sta te before a read operati on, it will reset

the interrupt and the INT pin output will tri-state. Each

8-bit port is read separately, so reading GP0 or

INTCAP0 will not clear the interrupt generated by GP1

or INTCAP1, and vice versa.

Input change activity on each port will generate an

interrupt and the value of the particular port will be

captured and copied into INTCAP0/INTCAP1. The

INTCAPn registers are only updated when an interrupt

occur s on INT. These values will stay unchanged until

the user clears the interrupt by reading the port or the

INTCAPn register.

If the in put po rt v alu e c ha nge s bac k to normal before a

user-read, the INT output will be reset. However, the

INTCAP0/INTCAP1 will still contain the value of the

port at the interrupt change. If the port value changes

again, it will re-activat e the int errup t an d the new v alu e

will be ca ptured.

The first interrupt on change event following an

interrupt RESET will result in a capture event. Any fur-

ther change event that occurs before the interrupt is

reset will not result in a capture event.

1.9.1 INTERRUPT EVENT DETECTION

The IARES bit controls the resolution for detecting an

interrupt-on-change event. If this bit is ‘0’ (default), the

maximum time for detecting a change of event is high,

which res ult s i n lower s tand by cu rrent. If th is bit is ‘1’, it

ta kes less time for sc anning the ac tivity on the port and

results in higher standby current.

FIGURE 1-2: READING PORTX AFTER

INTERRUPT EVENT

Port value

PORT X PORT X

GPx

INT

is captured

and written to

INTCAPn

Port value

is captured

and written to

INTCAPn

Read GPx

or INTCAPn

MCP23016

1.9.2 WRITING THE REGISTERS

To write t o a MCP23016 registe r , the M aster I2C dev ice

needs to follow the requirements, as illustrated in

Figure 1-3. First, the device is selected by sending the

slave address and setting the R/W bit to logic ‘0’. The

command byte is sent after the address and

determines which register will be written. Table 1-3

shows the relationship of the command byte and

The MCP23016 has twelve 8-bit registers. They are

configured to operate as six 16-bit register pairs,

supporting the device’s 16-bit port. These pairs are

formed based on their functions (e.g., GP0 and GP1

are grouped together). The I2C commands a pply to one

following a command byte is written into the register

pointed to b y the com mand by te, while the second da ta

is written into another register in the same pair. For

example, if the first byte is sent to OLAT1 (command

byte 03h), the next data byte will be written into the sec-

ond register of that pair, OLAT0. If the first byte is writ-

ten to OLAT0 (command byte 02h), the second byte

will be written to OLAT1.

There is no limitation on the number of data bytes in

one write transmission. Figure 1-4 shows the case of

multipl e byte wr ites in one wr ite ope ration. In this c ase,

the multiple writes are made to the same data pair.

FIGURE 1-3: WRITE TO CONFIGURATION

REGISTERS (CASE 1)

Note: The bus must remain free until after the

ninth clock pulse for a minimum of 12 µs

(see Table 2-5 and Figure 2-4).

1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9

1 0 0 A2 A1 A0 D0

R/W=0

ACK D6 D5 D4 D3 D2 D1

1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9

D0D6 D5 D4 D3 D2 D1D7 ACK D0D6 D5 D4 D3 D2 D1D7 ACK

Address Command Byte Data 1 Data 2

ACK

SCL held low until

data is processed

MCP23016

FIGURE 1-4: WRITE TO CONFIGURATION

REGISTERS (CASE 2) FIGURE 1-5: WRITE TO OUTPUT PORTS

1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9

1 0 0 A2 A1 A0 D0

R/W=0

ACK D6 D5 D4 D3 D2 D1

D7 ACK

1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9

D0 D6 D5 D4 D3 D2 D1

D7 ACK D0 D6 D5 D4 D3 D2 D1

D7 ACK

Address Command Byte Data 1 Data 2

1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9

D0 D6 D5 D4 D3 D2 D1

D7 ACK D0 D6 D5 D4 D3 D2 D1

D7 ACK

Data 1 Data 2

SCL held low until

data is processed

SCL held low until

data is processed

1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9

1 0 0 A2 A1 A0 D0

0R/W=0 ACK D6 D5 D4 D3 D2 D1D7 ACK

1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9

D0D6 D5 D4 D3 D2 D1D7 ACK D0D6 D5 D4 D3 D2 D1D7 ACK

Address Command Byte Data 1 Data 2

DATA V ALI D

tGPV0

DATA

VALID

tGPV1

SDA

SCL

Data on GP0

Data on GP1

SCL held low until

data is processed

MCP23016

1.9.3 READING THE REGISTERS

To read a MCP23016 register, the Master needs to

follow the requirements shown in Figure 1-6. First, the

device is selected by sending the slave address and

setting the R/W bit to logic ‘0’. The command byte is

sent after the address and determines which register

will be read. A restart condition is generated and the

device address is sent again with the R/W bit set to

logic ‘1’. The data register defined by the command

byte will be sent first, followed by the other register in

the register pair. The logic for register selection is the

same as explained in Write mode (Section 1.9.2,

“Writing the Registers”).

The falling edge of the ninth clock initiates the register

read action. The SCL clock will be held low while the

data is read from the register and is transferred to the

I2C bus control block by the Serializer/Deserializer

block.

The MCP23016 holds the clock low after the falling

edge of the ninth clock pulse. The configuration

registers (or port control registers) are read and the

value is stored. Finally, the clock is released to enable

the next transmission.

There is no limitation on the number of data bytes in

one read transmission. Figure 1-8 shows the case of

multiple byte read in one read operation. In this case,

the multiple writes are made to the same data pair.

FIGU RE 1-6 : READ FROM

CONFIGURATION

Note: The bus must remain free until after the

ninth clock pulse for a minimum of 12 µs

(see Table 2-5 and Figure 2-4).

1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9

1 0 0 A2 A1 A0 D0

0R/

ACK

D6 D5 D4 D3 D2 D1

ACK

Address Command Byte

1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9

1 0 0 A2 A1 A0 D0

ACK

D6 D5 D4 D3 D2 D1

ACK

Address Data from LSB or

MSB of register

1 2 3 4 5 6 7 8 9

D0D6 D5 D4 D3 D2 D1

ACK

Data from MSB or

LSB of register

SDA

SCL

SCL held low until

data is processed

SCL held low until

data is processed

MCP23016

FIGURE 1-7: READ FROM INPUT PORTS (CASE 1)

Note: It is assumed that command byte is already set to ‘00’.

123456789 123456789

1 0 0 A2 A1 A0 D0

R/W=0

ACK D6 D5 D4 D3 D2 D1

D7 ACK

Address Data from LSB or

MSB of register

1 2 3 4 5 6 7 8 9

D0D6 D5 D4 D3 D2 D1

D7 ACK

Data from MSB or

LSB of register

Read signal (Internal) for GP0

Read signal (Internal) for GP1

tRDd0

tRDd1

tIcd0

tIsd tIcd1

Data in GP0

Data in GP1

INT

SDA

SCL

SCL held low until

data is processed

MCP23016

FIGURE 1-8: READ FROM INPUT PORTS

(CASE 2)

1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9

1 0 0 A2 A1 A0 D0

R/W=0 ACK D6 D5 D4 D3 D2 D1

D7 ACK

Address Data from GP0

1 2 3 4 5 6 7 8 9

D0D6 D5 D4 D3 D2 D1

D7 ACK

Data fr o m GP 1

1 2 3 4 5 6 7 8 9

D0D6 D5 D4 D3 D2 D1

D7 ACK

Data from GP0

1 2 3 4 5 6 7 8 9

D0D6 D5 D4 D3 D2 D1

D7 ACK

Da ta fro m GP 1

Note: It is assumed that command byte is already set to 00.

SDA

SCL

MCP23016

NOTES:

MCP23016

2.0 ELECTRICAL CHARACTERISTICS

Absolute Maximum Ratings †

Ambient temperature under bias................................................................................................................ -55 to +125°C

Storage temperature.............................................................................................................................. -65°C to +150°C

Voltage on any pin with respect to VSS ......................................................................................... -0.3V to (VDD + 0.3V)

Volta ge on VDD with respect to VSS ......................................................................................................... -0.3V to +6.5 V

Total pow er dissipa tion (Note 1) ............................................................................................................................ 1.0 W

Maximum curr ent out of VSS pin .......................................................................................................................... 300 mA

Maximum curr ent into VDD pin............................................................................................................................. 250 mA

Input clamp current, IIK (VI < 0, or VI > VDD)....................................................................................................... ± 20 mA

Output clamp current, IOK (VO < 0, or VO > VDD)................................................................................................ ± 20 mA

Maximum output current sunk by any I/O pin............................................................................................... ...... .... 25 mA

Maximum output current sourced by any I/O pin......................................................................................... ...... .... 25 mA

Maximum curr ent sunk by combined POR TS.......... ...... ..... ...... ...... ............................ ..... ...... ..... ...... ................... 200 mA

Maximum current sourced by combined PORTS ................................................................................................ 20 0 mA

Note 1: Power diss ipation is calcula ted as follows :

Pdis = VDD x {IDD - ∑ IOH} + ∑ {(VDD-VOH) x IOH} + ∑(VOl x IOL)

† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the

device. This is a stress rating only and functional operation of the device at those or any other conditions above those

indicated in the operation listings of this specification is no t implied. Exposure to maximum rating conditions for

extended periods may affect device reliability.

MCP23016

2.1 DC Characteristics

TABLE 2-1: DC CHARACTERISTICS

DC CHARACTERISTICS Standard Operating Conditions (unless otherwise stated)

Operating temperature: -40°C ≤ TA ≤ +85°C for industrial

Param

No. Characteristic Sym Min Typ† Max Units Conditions

D001 Suppl y Voltage VDD 2.0 — 5.5 V

D002 Standby Current IDD — 0.4 mA IARES = 1

D003 Standby Current IPD — 25 µA IARES = 0

Input Low Voltage

I/O ports VIL

D004 TTL buffer Vss — 0.15 VDD V For entire VDD range

D004A Vss — 0.8V 4.5V ≤ VDD ≤ 5.5V

D005 Schmitt Trigger buf fer Vss — 0.2 VDD V

Inpu t Hi gh Voltage

I/O ports VIH —

D006 TTL buffer 2.0 — VDD V4.5V ≤ VDD ≤ 5.5V

D006A 0.25 VDD

+ 0.8V —VDD V For enti re VDD range

D007 Schmitt Trigger buf fer 0.8 VDD —VDD V For enti re VDD range

Input Leakage Current

D008 I/ O ports IIL ——±1.0 µA Vss ≤ VPIN ≤ VDD,

Pin at hi-impedance

D009 CLK — — ±5.0 µA Vss ≤ VPIN ≤ VDD

Output Low Voltage

D010 I/O Ports VOL ——0.6VIOL = 8.5 mA, VDD = 4.5V

Output High Voltage

D010 I/O Ports VOH VDD-0.7 — — V IOH = 3.0 mA, VDD = 4.5V

D011 VDD start voltage to ensure

internal POR signal VPOR —Vss— V

D012 VDD rise rate to ensure

internal POR signal SVDD 0.05 - — V/ms Note 1

DC Tr ip Point VTPOR 1.5 1.7 1.9 V DC Slow Ramp

D012 VDD rise rate to ensure

internal POR signal with

PWRT enabled

SVDD 0.05 — — V/ms Note 1

DC Current Draw IPOR — 5.0 — µA At 5.0V (1 µ/Volt typical)

Note 1: These parameters are characterized but not tested.

2: Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance

only and are not tested.

3: Standby current is measured with all I/O in hi-impedance state and tied to VDD and VSS.

4: For RC CLK, current through REXT is not included. The current through the resistor can be estimated by

the formul a

Ir = VDD/2 REXT (mA) with REXT in kohm.

5: Negative current is defined as coming out of the pin.

MCP23016

FIGURE 2-1: RESPONSE TIME

TABLE 2-2: RESPONSE TIME

FIGURE 2-2: TEST POINT CLOCK TIMING

TABLE 2-3: TEST POINT CLOCK TIMING

TABLE 2-4: POWER-UP TIMER REQUIREMENTS

VDD

Parameter

No. Symbol Characteristic Min Typ† Max Units Conditions

1 Response Time 100 — — ns Minimum time where a VDD

transition from 5.0V to 0.0V to

5.0V will cause a RESET. All

times less than 100 ns will be

filtered.

Parameter

No. Symbol Characteristic Min Typ†Max Units Conditions

FTP TP pin Frequency — 1.0 — MHz Measured at TP pin,

IARES = ‘1’.

2TTP TP pin CLK Period — 1.0 — µs Measured at TP pin,

IARES = ‘1’.

†Data in "Typ" column is at 5V, +25°C unless otherwise stated. These parameters are for design guidance

only and are not tested.

TTP

Parameter

No. Symbol Characteristic Min Typ†Max Units Conditions

PWRT Power-up Timer Period — 72 — ms

†Data in "Typ" column is at 5V, +25°C unless otherwise stated. These parameters are for design guidance

only and are not tested.

MCP23016

FIGURE 2-3: I2C BUS START/STOP BIT S T IMING

TABLE 2-5: I2C BUS START/STOP BITS REQUIREMENTS

Param

No. Symbol Characteristic Min Ty

pMax Units Conditions

90 TSU:STA START condition 100 kHz mode 4700 — — ns Only relevant for Repeated

START conditio n (Note 1)

Setup time 400 kHz mode 600 — —

91 THD:STA START condition 100 kHz mode 4000 — — ns After this period, the first

clock pulse is generated

(Note 1)

Hold time 400 kHz mode 600 — —

92 TSU:STO STOP condi tion 100 kHz mode 4700 — — ns

Setup time 400 kHz mode 600 — —

93 THD:STO STOP condi tion 100 kHz mode 4000 — — ns

Hold time 400 kHz mode 600 — —

Note 1: These parameters are characterized but not tested.

SCL

SDA

START

Condition STOP

Condition

MCP23016

FIGURE 2-4: I2C BUS DA T A T IMIN G

91 92

100 101

103

106 107

109 109 110

102

SCL

SDA

Out

111

MCP23016
DS20090C-page 24 © 2007 Microchip Technology Inc.
TABLE 2-5: I2C BUS DATA REQUIREMENTS
Param
No. Symbol Characteristic Min Max Units Conditions
100 THIGH Clock High Time 100 kHz mode 4.0 — µs (Note 1)
400 kHz m ode 0.6 — µs
101 TLOW Clock Low Time 100 kHz mode 4.7 — µs (Note 1)
400 kHz m ode 1.3 — µs
102 TRSDA and SCL  Ris e 
Time 100 kHz mode  — 1000 ns (Note 1)
400 kHz  mode 20 + 0.1 C B300 ns CB is specified to be from  
10 - 400 pF
103 TFSDA and SCL Fall 
Time 100 kHz mode  — 300 ns (Note 1)
400 kHz  mode 20 + 0.1 C B300 ns CB is specified to be from  
10 - 400 pF 
90 TSU:STA START Condition 
Set up Time 100 kHz mode 4.7 — µs Only relevant for repeated 
START condition (Note 1)
400 kHz m ode 0.6 — µs
91 THD:STA START Condition 
Hold Time  100 kHz mode 4.0 — µs After this period, the first 
clo ck pulse is generated 
(Note 1)
400 kHz m ode 0.6 — µs
106 THD:DAT Data Input Hold 
Time 100 kHz mode  0 — ns (Note 1)
400 kHz mode 0 0.9 µs
107 TSU:DAT Data Inpu t Setup 
Time 100 kHz mode 250 — ns (Note 1) (Note 3)
400 kHz mode 100 — ns
92 TSU:STO STOP Condition 
Set up Time 100 kHz m ode 4.7 — µs (Note 1)
400 kHz m ode 0.6 — µs
109 TAA Output Valid from 
Clock 100 kHz mode — 3500 ns (Note 1) (Note 2)
400 kHz mode — — ns
110 TBUF Bus Free T ime 100 kHz mode 4.7 — µs Time the  bus must be fre e 
before a new transmis-
sion can start (Note 1)
400 kHz m ode 1.3 — µs
CBBus  Capacitive Loading —  400 pF
111 TWAIT Clock wait time 
after ninth pulse 100 kHz mode 12 µs — µs T ime the bus must re main 
free after the ninth clock 
pulse before a new 
transmission can start.
400 kHz mode 12 µs — µ s
Note 1: These parameters are characterized but not tested.
2: As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region 
(min. 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions.
3: A Fast mode  (400 kHz) I2C bus  device ca n be used in a Standa rd mode (100 kHz ) I2C bu s system, but  the 
requirem ent  TSU:DAT ≥ 250 ns mus t then be met. Th is  wil l au tom at ica lly be the case i f th e device does no t 
stretch  the LO W period  of the  SCL sign al.  If such a d evic e does  stretc h the LOW p eriod o f the SC L signal , 
it mus t outpu t th e next  dat a bit  to the S DA  line TR max.+TSU:DAT = 1000 +  250 =  1250 ns  (accord ing to  the 
Standard mode I2C bus spec ification), before the SCL line is released.

MCP23016

TABLE 2-7: GP0 AND GP1 TIMING REQUIREMENTS

Param

No. Symbol Characteristic Min Typ. Max Units Conditions

tGPV0 GP0 output data

valid time —40—µsTP = 1MHz

tGPV1 GP1 output data

valid time —50—µs

tRDd0 GP0 data read

delay time —40—µs

tRDd1 GP1 data read

delay time —50—µs

tISD0 GP0 Interrupt set

delay time — — 200 µs IARES = 1, TP = 1 MHz

— — 32 ms IARES = 0, TP = 1 MHz

tISD1 GP1 Interrupt set

delay time — — 200 µs IARES = 1, TP = 1 MHz

— — 32 ms IARES = 0, TP = 1 MHz

tLCD0 GP0 Inter rupt clear

delay time (for

read)

—100— µsTP = 1MHz

tLCD1 GP1 Inter rupt clear

delay time (for

read)

—100— µs

Note 1: These parameters are characterized but not tested.

MCP23016

FIGURE 2-5: GP0 AND GP1 PORT TIMINGS

Note: It is assumed that command byte is already set to ‘00’.

1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9

1 0 0 A2 A1 A0 D0

0R/W=0

ACK D6 D5 D4 D3 D2 D1

D7 ACK

Address Data from LSB or

MSB of register

123456789

D0D6 D5 D4 D3 D2 D1

D7 ACK

Data from MSB or

LSB of register

Read signal(Internal) for GP0

Read signal(Internal) for GP1

tRDd0

tRDd1

tIcd0

tIsd tIcd1

Data in GP 0

Data in GP1

INT

SDA

SCL

SCL held low until

data is processed

MCP23016

3.0 PACKAGE INFORMATION

3.1 Package Marking Information

Legend: XX...X Customer-specific information

Y Year code (last digit of calendar year)

YY Year code (last 2 digits of calendar year)

WW Week code (week of January 1 is week ‘01’)

NNN Alphanumeric traceability code

Pb-free JEDEC designator for Matte Tin (Sn)

*This package is Pb-free. The Pb-free JEDEC designator ( )

can be found on the outer packaging for this package.

Note: In the even t the full Microchip part number c annot be marked on one line, it w ill

be carried over to the next line, thus limiting the number of available

characters for customer-specific information.

28-Lead SOIC

YYWWNNN

Example:

XXXXXXXXXXXXXXXXX

YYWWNNN

28-Lead PDIP (Skinny DIP) Example:

XXXXXXXXXXXXXXXXX

0717017

MCP23016-I/SP

0710017

MCP23016-I/SO

28-Lead SSOP

YYWWNNN

XXXXXXXXXXXX

Example:

0720017

MCP23016

28-Lead QFN Example:

XXXXXXXX

YYWWNNN

MCP23016

-I/ML

0710017

-I/SS

MCP23016

28-Lead Skinny Plasti c Dual In-Li ne (SP) – 300 mil Body [SPDIP]

otes:

. Pin 1 visual index feature may vary, but must be located within the hatched area.

. § Significant Characteristic.

. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" per side.

4. Dimensioning and tolerancing per ASME Y14.5M.

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

Units INCHES

Dimension Limits MIN NOM MAX

Number of Pins N 28

Pitch e .100 BSC

Top to Seating Plane A – – .200

Molded Package Thickness A2 .120 .135 .150

Base to Seating Plane A1 .015 – –

Shoulder to Shoulder Width E .290 .310 .335

Molded Package Width E1 .240 .285 .295

Overall Length D 1.345 1.365 1.400

Tip to Seating Plane L .110 .130 .150

Lead Thickness c .008 .010 .015

Upper Lead Width b1 .040 .050 .070

Lower Lead Width b .014 .018 .022

Overall Row Spacing § eB – – .430

NOTE 1

MCP23016

28-Lead Plastic Small Outline (SO) – Wide, 7.50 mm Body [SOIC]

otes:

. Pin 1 visual index feature may vary, but must be located within the hatched area.

. § Significant Characteristic.

. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15 mm per side.

. Dimensioning and tolerancing per ASME Y14.5M.

BSC: Basic Dimension. Theoretically exact value shown without tolerances.

REF: Reference Dimension, usually without tolerance, for information purposes only.

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

Units MILLMETERS

Dimension Limits MIN NOM MAX

Number of Pins N 28

Pitch e 1.27 BSC

Overall Height A – – 2.65

Molded Package Thickness A2 2.05 – –

Standoff § A1 0.10 – 0.30

Overall Width E 10.30 BSC

Molded Package Width E1 7.50 BSC

Overall Length D 17.90 BSC

Chamfer (optional) h 0.25 – 0.75

Foot Length L 0.40 – 1.27

Footprint L1 1.40 REF

Foot Angle Top φ0° – 8°

Lead Thickness c 0.18 – 0. 33

Lead Width b 0.31 – 0.51

Mold Draft Angle Top α5° – 15°

Mold Draft Angle Bottom β5° – 15°

NOTE 1

123

Microchip Technology Drawing C04-052

MCP23016

28-Lead Plastic Shrink Small Outline (SS) – 5.30 mm Body [SSOP]

otes:

. Pin 1 visual index feature may vary, but must be located within the hatched area.

. Dimens ions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.20 mm per side.

. Dimens ioning and tolerancing per ASME Y14.5M.

BSC: Basic Dimension. Theoretically exact value shown without tolerances.

REF: Reference Dimension, usually without tolerance, for information purposes only.

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

Units MILLIMETERS

Dimension Limits MIN NOM MAX

Number of Pins N 28

Pitch e 0.65 BSC

Overall Height A – – 2.00

Molded Package Thickness A2 1.65 1.75 1.85

Standoff A1 0.05 – –

Overall Width E 7.40 7.80 8. 20

Molded Package Width E1 5.00 5.30 5.60

Overall Length D 9.90 10.20 10.50

Foot Length L 0.55 0.75 0.95

Footprint L1 1.25 REF

Lead Thickness c 0.09 – 0.25

Foot Angle φ0° 4° 8°

Lead Width b 0.22 – 0.38

NOTE 1

Microchip Technology Drawing C04-073

MCP23016

28-Lead Plastic Quad Flat, No Lead Package (ML) – 6x6 mm Body [QFN]

ith 0.55 mm Contact Length

otes:

. Pin 1 visual index feature may vary, but must be located within the hatched area.

. Package is saw singulated.

. Dimensioning and tolerancing per ASME Y14.5M.

BSC: Basic Dimension. Theoretically exact value shown without tolerances.

REF: Reference Dimension, usually without tolerance, for information purposes only.

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

Units MILLIMETERS

Dimension Limits MIN NOM MAX

Number of Pins N 28

Pitch e 0.65 BSC

Overall Height A 0.80 0.90 1.00

Standoff A1 0.00 0.02 0.05

Contact Thickness A3 0. 20 REF

Overall Width E 6.00 BSC

Exposed Pad Width E2 3.65 3.70 4.20

Overall Length D 6.00 BSC

Exposed Pad Length D2 3.65 3.70 4.20

Contact Width b 0.23 0.30 0.35

Contact Length L 0.50 0.55 0.70

Contact-to-Exposed Pad K 0.20 – –

DEXPOSED D2

NOTE 1

TOP VIEW BOTTOM VIEW

PAD

Microchip Technology Drawing C04-105

MCP23016

NOTES:

MCP23016

APPENDIX A: REVISION HISTORY

Revision A (December 2002)

Original data sheet for MCP23016 device.

Revision B (September 2003)

1. Addition of Output Low Voltage section to

Table 2-1 in Electrical Charac teristics.

2. Addition of Output High Voltage section to

Table 2-1 in Electrical Charac teristics.

Revision C (January 2007)

This revision includes updates to the packaging

diagrams.

MCP23016

NOTES:

MCP23016

PRODUCT IDENTIFICATION SYSTEM

To order or obtain information (e.g., on pricing or delivery) refer to the factory or the listed sales office.

PART NO. X/XX

PackageTemperature

Range

Device

Device: DSTEMP: 16-Bit I2C I/O Expander

Temperature

Range: I= -40°C to +85°C

Package: SP = Plastic DIP (300 mil Body), 28-lead

SO = Plastic SOIC, Wide (300 mil Body), 28-lead

SS = Plastic SOIC, (209 mil, 5.30mm), 28-lead

ML = Plast ic Quad, Flat No Leads (QFN), 28-lead

Examples:

a) DSTEMP-I/P: Industrial Temperature,

PDIP package.

a) DSTEMP-I/SO: Industrial Temperature,

SOIC package.

a) DSTEMP-I/SS: Industrial Temperature,

SOIC package.

a) DSTEMP-I/ML: Industrial Temperature,

QFN package.

MCP23016

NOTES:

Information contained in this publication regarding device

applications a nd the lik e is provid ed only for your c on ve nience

and may be supers eded by u pdates. I t is your r es po n s ibility to

ensure that your application meets with your specifications.

MICROCHIP MAKES NO REPRESENTATIONS OR

WARRANTIES OF ANY KIND WHETHER EXPRESS OR

IMPLIED, WRITTEN OR ORAL, STATUTORY OR

OTHERWISE, RELATED TO THE INFORMATION,

INCLUDING BUT NOT LIMITED TO ITS CONDITION,

QUALITY, PERFORMANCE, MERCHANTABILITY OR

FITNESS FOR PURPOSE. Microchip disclaims all liability

arising from this information and its use. Use of Microchip

devices in life support and/or safety applications is entirely at

the buyer’s risk, and the buyer agrees to defend, indemnify and

hold harmless Microchip from any and all damages, claims,

suits, or expenses resulting from such use. No licenses are

conveyed, implicitly or otherwise, under any Microchip

intellectual property rights.

Trademarks

The Microchip name and logo, the Microchip logo, Accuron,

dsPIC, KEELOQ, microID, MPLAB, PIC, PICmicro, PICST ART ,

PRO MATE, PowerSmart, rfPIC, and SmartShunt are

registered trademarks of Microchip Technology Incorporated

in the U.S.A. and other countries.

AmpLab, FilterLab, Migratable Memory, MXDEV, MXLAB,

SEEV AL, SmartSensor and The Embedded Control Solutions

Company are registered trademarks of Microchip Technology

Incorporated in the U.S.A.

Analog-for-the-Digital Age, Application Maestro, CodeGuard,

dsPICDEM, dsPICDEM.net, dsPICworks, ECAN,

ECONOMONITOR, FanSense, FlexROM, fuzzyLAB,

In-Circuit Serial Programming, ICSP, ICEPIC , Linear Active

Thermistor, Mindi, MiWi, MPASM, MPLIB, MPLINK, PIC kit,

PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal,

PowerInf o, PowerMate, PowerTool, REAL ICE, rfLAB,

rfPICDEM, Select Mode, Smart Serial, SmartTel, Total

Endurance, UNI/O, WiperLock and ZENA are trademarks of

Microchip Technology Incorporated in the U.S.A. and other

countries.

SQTP is a service mark of Microchip Technology Incorporated

in the U.S.A.

All other trademarks mentioned herein are property of their

respective companies.

Printed on recycled paper.

Note the following details of the code protection feature on Microchip devices:

• Microchip products meet the specification contained in t heir particular Microchip Data Sheet.

• Microchip believes that its family of products is one of the most secure famili es of its kind on the market today, when used in the

intended manner and under normal conditions.

• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our

knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data

Sheets. Most likely, the person doing so is engaged in theft of int ellectual property.

• Microchip is willing to work with the customer who is concerned about the integrity of their code.

• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not

mean that we are guaranteeing the product as “unbreakable.”

Code protection is c onstantly evolving. We a t Microchip are commit ted to continuously improving the code protect ion f eatures of our

products. Attempts to break Microchip’ s code protection f eature may be a violati on of t he Digit al Millennium Copyright Act. If such act s

allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Microchip received ISO/TS-16949:2002 certification for its worldwide

headquarters, design and wafer fabrication facilities in Chandler and

T empe, Arizona, Gresham, Oregon and Mountain View , California. The

Company’s quality system processes and procedures are for its PIC®

MCUs and dsPIC DSCs, KEELOQ® code hopping devices, Serial

EEPROMs, microperipherals, nonvolatile memory and analog

products. In addition, Microchip’s quality system for the design and

manufacture of development systems is ISO 9001:2000 certified.

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Taiwan - Taipei

Tel: 886-2-2500-6610

Fax: 886-2-2508-0102

Thail a nd - Bangkok

Tel: 66-2-694-1351

Fax: 66-2-694-1350

EUROPE

Austria - Wels

Tel: 43-7242-2244-39

Fax: 43-7242-2244-393

Denmark - Copenhage n

Tel: 45-4450-2828

Fax: 45-4485-2829

France - Paris

Tel: 33-1-69-53-63-20

Fax: 33-1-69-30-90-79

Germany - Munich

Tel: 49-89-627-144-0

Fax: 49-89-627-14 4-44

Italy - Milan

Tel: 39-0331-742611

Fax: 39-0331-466781

Netherlands - Drunen

Tel: 31-416-690399

Fax: 31-416-690340

Sp ain - Madr i d

Tel: 34-91-708-08-90

Fax: 34-91-708-08 -91

UK - Wokingham

Tel: 44-118-921- 5869

Fax: 44-118-921-5820

WORLDWIDE SALES AND SERVICE

12/08/06