1. General description
The 74HC2G04; 74HCT2G04 is a high-speed Si-gate CMOS device.
The 74HC2G04; 74HCT2G04 provides two inverting buffers.
2. Features
nWide supply voltage range from 2.0 V to 6.0 V
nComplies with JEDEC standard no. 7A
nHigh noise immunity
nESD protection:
uHBM JESD22-A114-D exceeds 2000 V
uMM JESD22-A115-A exceeds 200 V
nLow power dissipation
nBalanced propagation delays
nUnlimited input rise and fall times
nMultiple package options
nSpecified from −40 °Cto+85°C and −40 °C to +125 °C
3. Ordering information
4. Marking
74HC2G04; 74HCT2G04
Dual inverter
Rev. 01 — 15 November 2006 Product data sheet
Table 1. Ordering information
Type number Package
Temperature range Name Description Version
74HC2G04GW −40 °C to +125 °C SC-88 plastic surface-mounted package; 6 leads SOT363
74HC2G04GV −40 °C to +125 °C SC-74 plastic surface-mounted package (TSOP6); 6 leads SOT457
74HCT2G04GW −40 °C to +125 °C SC-88 plastic surface-mounted package; 6 leads SOT363
74HCT2G04GV −40 °C to +125 °C SC-74 plastic surface-mounted package (TSOP6); 6 leads SOT457
Table 2. Marking
Type number Marking code
74HC2G04GW H4
74HC2G04GV H04
74HCT2G04GW T4
74HCT2G04GV T04
74HC_HCT2G04_1 © NXP B.V. 2006. All rights reserved.
Product data sheet Rev. 01 — 15 November 2006 2 of 14
NXP Semiconductors 74HC2G04; 74HCT2G04
Dual inverter
5. Functional diagram
6. Pinning information
6.1 Pinning
6.2 Pin description
Fig 1. Logic symbol Fig 2. IEC logic symbol Fig 3. Logic diagram (one gate)
mnb079
1A 1Y
16
2A 2Y
34
116
mnb080
314
mna110
AY
Fig 4. Pin configuration
74HC2G04
74HCT2G04
1A 1Y
GND
2A 2Y
001aaf304
1
2
3
6
VCC
5
4
Table 3. Pin description
Symbol Pin Description
1A 1 data input
GND 2 ground (0 V)
2A 3 data input
2Y 4 data output
VCC 5 supply voltage
1Y 6 data output
74HC_HCT2G04_1 © NXP B.V. 2006. All rights reserved.
Product data sheet Rev. 01 — 15 November 2006 3 of 14
NXP Semiconductors 74HC2G04; 74HCT2G04
Dual inverter
7. Functional description
[1] H = HIGH voltage level;
L = LOW voltage level.
8. Limiting values
[1] The minimum input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] For SC-88 and SC-74 packages: above 87.5 °C the value of Ptot derates linearly with 4.0 mW/K.
9. Recommended operating conditions
Table 4. Function table[1]
Input Output
nA nY
LH
HL
Table 5. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Min Max Unit
VCC supply voltage −0.5 +7.0 V
IIK input clamping current VI < −0.5 V or VI>V
CC + 0.5 V [1] -±20 mA
IOK output clamping current VO<−0.5 V or VO>V
CC + 0.5 V [1] -±20 mA
IOoutput current VO = −0.5 V to VCC + 0.5 V [1] -±25 mA
ICC supply current [1] - +50 mA
IGND ground current [1] -−50 mA
Tstg storage temperature −65 +150 °C
Ptot total power dissipation [2] - 250 mW
Table 6. Recommended operating conditions
Symbol Parameter Conditions Min Typ Max Unit
Type 74HC2G04
VCC supply voltage 2.0 5.0 6.0 V
VIinput voltage 0 - VCC V
VOoutput voltage 0 - VCC V
Tamb ambient temperature −40 +25 +125 °C
trrise time except for Schmitt trigger inputs
VCC = 2.0 V - - 1000 ns
VCC = 4.5 V - - 500 ns
VCC = 6.0 V - - 400 ns
tffall time except for Schmitt trigger inputs
VCC = 2.0 V - - 1000 ns
VCC = 4.5 V - - 500 ns
VCC = 6.0 V - - 400 ns
74HC_HCT2G04_1 © NXP B.V. 2006. All rights reserved.
Product data sheet Rev. 01 — 15 November 2006 4 of 14
NXP Semiconductors 74HC2G04; 74HCT2G04
Dual inverter
10. Static characteristics
Type 74HCT2G04
VCC supply voltage 4.5 5.0 5.5 V
VIinput voltage 0 - VCC V
VOoutput voltage 0 - VCC V
Tamb ambient temperature −40 +25 +125 °C
trrise time except for Schmitt trigger inputs
VCC = 4.5 V - - 500 ns
tffall time except for Schmitt trigger inputs
VCC = 4.5 V - - 500 ns
Table 6. Recommended operating conditions
…continued
Symbol Parameter Conditions Min Typ Max Unit
Table 7. Static characteristics for 74HC2G04
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Min Typ Max Unit
Tamb = 25 °C
VIH HIGH-level input voltage VCC = 2.0 V 1.5 1.2 - V
VCC = 4.5 V 3.15 2.4 - V
VCC = 6.0 V 4.2 3.2 - V
VIL LOW-level input voltage VCC = 2.0 V - 0.8 0.5 V
VCC = 4.5 V - 2.1 1.35 V
VCC = 6.0 V - 2.8 1.8 V
VOH HIGH-level output voltage VI= VIH or VIL
IO=−20 µA; VCC = 2.0 V 1.9 2.0 - V
IO=−20 µA; VCC = 4.5 V 4.4 4.5 - V
IO=−20 µA; VCC = 6.0 V 5.9 6.0 - V
IO=−4.0 mA; VCC = 4.5 V 4.18 4.32 - V
IO=−5.2 mA; VCC = 6.0 V 5.68 5.81 - V
VOL LOW-level output voltage VI= VIH or VIL
IO= 20 µA; VCC = 2.0 V - 0 0.1 V
IO= 20 µA; VCC = 4.5 V - 0 0.1 V
IO= 20 µA; VCC = 6.0 V - 0 0.1 V
IO= 4.0 mA; VCC = 4.5 V - 0.15 0.26 V
IO= 5.2 mA; VCC = 6.0 V - 0.16 0.26 V
Ilinput leakage current VI= GND or VCC; VCC = 6.0 V - - ±0.1 µA
ICC supply current VI= GND or VCC; IO= 0 A;
VCC = 6.0 V - - 1.0 µA
CIinput capacitance - 1.5 - pF
74HC_HCT2G04_1 © NXP B.V. 2006. All rights reserved.
Product data sheet Rev. 01 — 15 November 2006 5 of 14
NXP Semiconductors 74HC2G04; 74HCT2G04
Dual inverter
Tamb = −40 °C to +85 °C
VIH HIGH-level input voltage VCC = 2.0 V 1.5 - - V
VCC = 4.5 V 3.15 - - V
VCC = 6.0 V 4.2 - - V
VIL LOW-level input voltage VCC = 2.0 V - - 0.5 V
VCC = 4.5 V - - 1.35 V
VCC = 6.0 V - - 1.8 V
VOH HIGH-level output voltage VI= VIH or VIL
IO=−20 µA; VCC = 2.0 V 1.9 - - V
IO=−20 µA; VCC = 4.5 V 4.4 - - V
IO=−20 µA; VCC = 6.0 V 5.9 - - V
IO=−4.0 mA; VCC = 4.5 V 4.13 - - V
IO=−5.2 mA; VCC = 6.0 V 5.63 - - V
VOL LOW-level output voltage VI= VIH or VIL
IO= 20 µA; VCC = 2.0 V - - 0.1 V
IO= 20 µA; VCC = 4.5 V - - 0.1 V
IO= 20 µA; VCC = 6.0 V - - 0.1 V
IO= 4.0 mA; VCC = 4.5 V - - 0.33 V
IO= 5.2 mA; VCC = 6.0 V - - 0.33 V
Ilinput leakage current VI= GND or VCC; VCC = 6.0 V - - ±1.0 µA
ICC supply current VI= GND or VCC; IO= 0 A;
VCC = 6.0 V - - 10.0 µA
Tamb = −40 °C to +125 °C
VIH HIGH-level input voltage VCC = 2.0 V 1.5 - - V
VCC = 4.5 V 3.15 - - V
VCC = 6.0 V 4.2 - - V
VIL LOW-level input voltage VCC = 2.0 V - - 0.5 V
VCC = 4.5 V - - 1.35 V
VCC = 6.0 V - - 1.8 V
VOH HIGH-level output voltage VI= VIH or VIL
IO=−20 µA; VCC = 2.0 V 1.9 - - V
IO=−20 µA; VCC = 4.5 V 4.4 - - V
IO=−20 µA; VCC = 6.0 V 5.9 - - V
IO=−4.0 mA; VCC = 4.5 V 3.7 - - V
IO=−5.2 mA; VCC = 6.0 V 5.2 - - V
Table 7. Static characteristics for 74HC2G04
…continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Min Typ Max Unit
74HC_HCT2G04_1 © NXP B.V. 2006. All rights reserved.
Product data sheet Rev. 01 — 15 November 2006 6 of 14
NXP Semiconductors 74HC2G04; 74HCT2G04
Dual inverter
VOL LOW-level output voltage VI= VIH or VIL
IO= 20 µA; VCC = 2.0 V - - 0.1 V
IO= 20 µA; VCC = 4.5 V - - 0.1 V
IO= 20 µA; VCC = 6.0 V - - 0.1 V
IO= 4.0 mA; VCC = 4.5 V - - 0.4 V
IO= 5.2 mA; VCC = 6.0 V - - 0.4 V
Ilinput leakage current VI= GND or VCC; VCC = 6.0 V - - ±1.0 µA
ICC supply current VI= GND or VCC; IO= 0 A;
VCC = 6.0 V - - 20.0 µA
Table 7. Static characteristics for 74HC2G04
…continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Min Typ Max Unit
Table 8. Static characteristics for 74HCT2G04
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Min Typ Max Unit
Tamb = 25 °C
VIH HIGH-level input voltage VCC = 4.5 V to 5.5 V 2.0 1.6 - V
VIL LOW-level input voltage VCC = 4.5 V to 5.5 V - 1.2 0.8 V
VOH HIGH-level output voltage VI= VIH or VIL
IO=−20 µA; VCC = 4.5 V 4.4 4.5 - V
IO=−4.0 mA; VCC = 4.5 V 4.18 4.32 - V
VOL LOW-level output voltage VI= VIH or VIL
IO= 20 µA; VCC = 4.5 V - 0 0.1 V
IO= 4.0 mA; VCC = 4.5 V - 0.15 0.26 V
Ilinput leakage current VI= GND or VCC; VCC = 5.5 V - - ±0.1 µA
ICC supply current VI= GND or VCC; IO= 0 A;
VCC = 5.5 V - - 1.0 µA
∆ICC additional supply current VI= VCC − 2.1 V;
VCC = 4.5 V to 5.5 V; IO = 0 A - - 300 µA
CIinput capacitance - 1.5 - pF
Tamb = −40 °C to +85 °C
VIH HIGH-level input voltage VCC = 4.5 V to 5.5 V 2.0 - - V
VIL LOW-level input voltage VCC = 4.5 V to 5.5 V - - 0.8 V
VOH HIGH-level output voltage VI= VIH or VIL
IO=−20 µA; VCC = 4.5 V 4.4 - - V
IO=−4.0 mA; VCC = 4.5 V 4.13 - - V
VOL LOW-level output voltage VI= VIH or VIL
IO= 20 µA; VCC = 4.5 V - - 0.1 V
IO= 4.0 mA; VCC = 4.5 V - - 0.33 V
Ilinput leakage current VI= GND or VCC; VCC = 5.5 V - - ±1.0 µA
ICC supply current VI= GND or VCC; IO= 0 A;
VCC = 5.5 V - - 10.0 µA
∆ICC additional supply current VI= VCC − 2.1 V;
VCC = 4.5 V to 5.5 V; IO = 0 A - - 375 µA
74HC_HCT2G04_1 © NXP B.V. 2006. All rights reserved.
Product data sheet Rev. 01 — 15 November 2006 7 of 14
NXP Semiconductors 74HC2G04; 74HCT2G04
Dual inverter
11. Dynamic characteristics
Tamb = −40 °C to +125 °C
VIH HIGH-level input voltage VCC = 4.5 V to 5.5 V 2.0 - - V
VIL LOW-level input voltage VCC = 4.5 V to 5.5 V - - 0.8 V
VOH HIGH-level output voltage VI= VIH or VIL
IO=−20 µA; VCC = 4.5 V 4.4 - - V
IO=−4.0 mA; VCC = 4.5 V 3.7 - - V
VOL LOW-level output voltage VI= VIH or VIL
IO= 20 µA; VCC = 4.5 V - - 0.1 V
IO= 4.0 mA; VCC = 4.5 V - - 0.4 V
Ilinput leakage current VI= GND or VCC; VCC = 5.5 V - - ±1.0 µA
ICC supply current VI= GND or VCC; IO= 0 A;
VCC = 5.5 V - - 20.0 µA
∆ICC additional supply current VI= VCC − 2.1 V;
VCC = 4.5 V to 5.5 V; IO = 0 A - - 410 µA
Table 8. Static characteristics for 74HCT2G04
…continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Min Typ Max Unit
Table 9. Dynamic characteristics
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 6.
Symbol Parameter Conditions 25 °C−40 °C to +125 °C Unit
Min Typ Max Min Max
(85 °C) Max
(125 °C)
74HC2G04
tpd propagation delay nA to nY; see Figure 5 [1]
VCC = 2.0 V; CL= 50 pF - 22 75 - 90 110 ns
VCC = 4.5 V; CL= 50 pF - 8 15 - 18 22 ns
VCC = 6.0 V; CL= 50 pF - 6 13 - 16 20 ns
tttransition time nY; see Figure 5 [2]
VCC = 2.0 V; CL= 50 pF - 18 75 - 95 125 ns
VCC = 4.5 V; CL= 50 pF - 6 15 - 19 25 ns
VCC = 6.0 V; CL= 50 pF - 5 13 - 16 20 ns
CPD power dissipation
capacitance VI= GND to VCC [3] -9-- - -pF
74HC_HCT2G04_1 © NXP B.V. 2006. All rights reserved.
Product data sheet Rev. 01 — 15 November 2006 8 of 14
NXP Semiconductors 74HC2G04; 74HCT2G04
Dual inverter
[1] tpd is the same as tPLH and tPHL.
[2] tt is the same as tTLH and tTHL.
[3] CPD is used to determine the dynamic power dissipation (PD in µW).
PD=C
PD ×VCC2×fi×N+Σ(CL×VCC2×fo) where:
fi= input frequency in MHz;
fo= output frequency in MHz;
CL= output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
Σ(CL×VCC2×fo) = sum of the outputs.
12. Waveforms
74HCT2G04
tpd propagation delay nA to nY; see Figure 5 [1]
VCC = 4.5 V; CL= 50 pF - 10 18 - 23 29 ns
tttransition time nY; see Figure 5 [2]
VCC = 4.5 V; CL= 50 pF - 6 15 - 19 22 ns
CPD power dissipation
capacitance VI= GND to VCC − 1.5 V [3] -9-- - -pF
Table 9. Dynamic characteristics
…continued
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 6.
Symbol Parameter Conditions 25 °C−40 °C to +125 °C Unit
Min Typ Max Min Max
(85 °C) Max
(125 °C)
Measurement points are given in Table 10.
VOL and VOH are typical voltage output drop that occur with the output load.
Fig 5. The data input (nA) to output (nY) propagation delays and output transition times
mna722
tPLH
tPHL
VM
VM
90%
10%
VMVM
nY output
nA input
VI
GND
VOH
VOL
tTLH
tTHL
Table 10. Measurement points
Type Input Output
VMVItr = tfVM
74HC2G04 0.5VCC GND to VCC 6.0 ns 0.5VCC
74HCT2G04 1.3 V GND to 3.0 V 6.0 ns 1.3 V
74HC_HCT2G04_1 © NXP B.V. 2006. All rights reserved.
Product data sheet Rev. 01 — 15 November 2006 9 of 14
NXP Semiconductors 74HC2G04; 74HCT2G04
Dual inverter
Test data is given in Table 11.
Definitions test circuit:
RL = Load resistance.
CL = Load capacitance including jig and probe capacitance.
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
Fig 6. Load circuitry for switching times
mgk563
D.U.T
VCC VCC
VIVO
RT
RL = 1 kΩ
CL50 pF
open
PULSE
GENERATOR
Table 11. Test data
Type Input Test
VItr, tftPHL, tPLH
74HC2G04 GND to VCC 6 ns open
74HCT2G04 GND to 3.0 V 6 ns open
74HC_HCT2G04_1 © NXP B.V. 2006. All rights reserved.
Product data sheet Rev. 01 — 15 November 2006 10 of 14
NXP Semiconductors 74HC2G04; 74HCT2G04
Dual inverter
13. Package outline
Fig 7. Package outline SOT363 (SC-88)
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
SOT363 SC-88
wBM
bp
D
e1
e
pin 1
index A
A1
Lp
Q
detail X
HE
E
vMA
AB
y
0 1 2 mm
scale
c
X
132
456
Plastic surface-mounted package; 6 leads SOT363
UNIT A1
max bpcDEe1HELpQywv
mm 0.1 0.30
0.20 2.2
1.8
0.25
0.10 1.35
1.15 0.65
e
1.3 2.2
2.0 0.2 0.10.2
DIMENSIONS (mm are the original dimensions)
0.45
0.15 0.25
0.15
A
1.1
0.8
04-11-08
06-03-16
74HC_HCT2G04_1 © NXP B.V. 2006. All rights reserved.
Product data sheet Rev. 01 — 15 November 2006 11 of 14
NXP Semiconductors 74HC2G04; 74HCT2G04
Dual inverter
Fig 8. Package outline SOT457 (SC-74)
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
SOT457 SC-74
wBM
bp
D
e
pin 1
index A
A1
Lp
Q
detail X
HE
E
vMA
AB
y
scale
c
X
132
4
56
0 1 2 mm
Plastic surface-mounted package (TSOP6); 6 leads SOT457
UNIT A1bpcDEHELpQywv
mm 0.1
0.013 0.40
0.25 3.1
2.7
0.26
0.10 1.7
1.3
e
0.95 3.0
2.5 0.2 0.10.2
DIMENSIONS (mm are the original dimensions)
0.6
0.2 0.33
0.23
A
1.1
0.9
05-11-07
06-03-16
74HC_HCT2G04_1 © NXP B.V. 2006. All rights reserved.
Product data sheet Rev. 01 — 15 November 2006 12 of 14
NXP Semiconductors 74HC2G04; 74HCT2G04
Dual inverter
14. Abbreviations
15. Revision history
Table 12. Abbreviations
Acronym Description
CMOS Complementary Metal Oxide Semiconductor
ESD ElectroStatic Discharge
HBM Human Body Model
MM Machine Model
DUT Device Under Test
Table 13. Revision history
Document ID Release date Data sheet status Change notice Supersedes
74HC_HCT2G04_1 20061115 Product data sheet - -
74HC_HCT2G04_1 © NXP B.V. 2006. All rights reserved.
Product data sheet Rev. 01 — 15 November 2006 13 of 14
NXP Semiconductors 74HC2G04; 74HCT2G04
Dual inverter
16. Legal information
16.1 Data sheet status
[1] Please consult the most recently issued document before initiating or completing a design.
[2] The term ‘short data sheet’ is explained in section “Definitions”.
[3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
16.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
16.3 Disclaimers
General — Information in this document is believed to be accurate and
reliable. However, NXP Semiconductors does not give any representations or
warranties, expressed or implied, as to the accuracy or completeness of such
information and shall have no liability for the consequences of use of such
information.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or
malfunction of a NXP Semiconductors product can reasonably be expected to
result in personal injury, death or severe property or environmental damage.
NXP Semiconductors accepts no liability for inclusion and/or use of NXP
Semiconductors products in such equipment or applications and therefore
such inclusion and/or use is at the customer’s own risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) may cause permanent
damage to the device. Limiting values are stress ratings only and operation of
the device at these or any other conditions above those given in the
Characteristics sections of this document is not implied. Exposure to limiting
values for extended periods may affect device reliability.
Terms and conditions of sale — NXP Semiconductors products are sold
subject to the general terms and conditions of commercial sale, as published
at http://www.nxp.com/profile/terms, including those pertaining to warranty,
intellectual property rights infringement and limitation of liability, unless
explicitly otherwise agreed to in writing by NXP Semiconductors. In case of
any inconsistency or conflict between information in this document and such
terms and conditions, the latter will prevail.
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or the
grant, conveyance or implication of any license under any copyrights, patents
or other industrial or intellectual property rights.
16.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
17. Contact information
For additional information, please visit: http://www.nxp.com
For sales office addresses, send an email to: salesaddresses@nxp.com
Document status[1][2] Product status[3] Definition
Objective [short] data sheet Development This document contains data from the objective specification for product development.
Preliminary [short] data sheet Qualification This document contains data from the preliminary specification.
Product [short] data sheet Production This document contains the product specification.
NXP Semiconductors 74HC2G04; 74HCT2G04
Dual inverter
© NXP B.V. 2006. All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 15 November 2006
Document identifier: 74HC_HCT2G04_1
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
18. Contents
1 General description. . . . . . . . . . . . . . . . . . . . . . 1
2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
3 Ordering information. . . . . . . . . . . . . . . . . . . . . 1
4 Marking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
5 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
6 Pinning information. . . . . . . . . . . . . . . . . . . . . . 2
6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 2
7 Functional description . . . . . . . . . . . . . . . . . . . 3
8 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 3
9 Recommended operating conditions. . . . . . . . 3
10 Static characteristics. . . . . . . . . . . . . . . . . . . . . 4
11 Dynamic characteristics . . . . . . . . . . . . . . . . . . 7
12 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
13 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 10
14 Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 12
15 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 12
16 Legal information. . . . . . . . . . . . . . . . . . . . . . . 13
16.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 13
16.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
16.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 13
16.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 13
17 Contact information. . . . . . . . . . . . . . . . . . . . . 13
18 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
