LP5521 LP5521 Programmable Three Channel LED Driver Literature Number: SNVS441D LP5521 Programmable Three Channel LED Driver General Description Features The LP5521 is a three channel LED driver designed to produce variety of lighting effects for mobile devices. High efficiency charge pump enables LED driving over full Li-Ion battery voltage range. The device has a program memory for creating variety of lighting sequences. When program memory has been loaded, LP5521 can operate independently without processor control. LP5521 maintains excellent efficiency over a wide operating range by automatically selecting proper charge pump gain based on LED forward voltage requirements. LP5521 is able to automatically enter power-save mode, when LED outputs are not active and thus lowering current consumption. Three independent LED channels have accurate programmable current sources and PWM control. Each channel has program memory for creating desired lighting sequences with PWM control. LP5521 has a flexible digital interface. Trigger I/O and 32 kHz clock input allow synchronization between multiple devices. Interrupt output can be used to notify processor, when LED sequence has ended. LP5521 has four pin selectable I2C addresses. This allows connecting up to four parallel devices in one I2C bus. GPO and INT pins can be used as a digital control pin for other devices. LP5521 requires only four small and low cost ceramic capacitors. LP5521 is available in tiny 2.1x1.7x0.6 mm microSMD-20 package and in 4.0x5.0x0.8 mm bumped LLP-24 package. Comprehensive application tools are available, including command compiler for easy LED sequence programming. Adaptive charge pump with 1x and 1.5x gain provides up to 95% LED drive efficiency Charge pump with soft start and overcurrent/short circuit protection Low input ripple and EMI Very small solution size, no inductor or resistors required 200 nA typical shutdown current Automatic power save mode I2C compatible interface Independently programmable constant current outputs with 8-bit current setting and 8-bit PWM control Typical LED output saturation voltage 50 mV and current matching 1% Three program execution engines with flexible instruction set Autonomous operation without external control Large SRAM program memory Two general purpose digital outputs microSMD-20 package, 0.4 mm pitch Bumped LLP-24 package, 0.5 mm pitch Applications Fun / indicator lights LCD sub-display backlighting Keypad RGB backlighting and phone cosmetics Vibra, speakers, waveform generator Typical Application 20186270 (c) 2008 National Semiconductor Corporation 201862 www.national.com LP5521 Programmable Three Channel LED Driver May 6, 2008 LP5521 Connection Diagrams and Package Mark Information Thin microSMD-20 Package (2.1 x 1.7 x 0.6 mm, 0.4 mm pitch) NS Package Number TMD20ECA 20186271 20186272 Top View Bottom View Package Mark 20186296 Package Mark - Top View www.national.com 2 LP5521 Connection Diagrams and Package Mark Information Bumped LLP-24 Package (5 x 4 x 0.8 mm, 0.5 mm pitch) NS Package Number YQA24A 20186201 20186202 Package Mark - Top View Bottom View U = Fab Z = Assembly XY = 2 Digit Date Code TT = Die Traceability L5521YQ = Product Identification Ordering Information Order Number Package Package Marking Supplied As Spec/Flow LP5521TM SMD 5521 250 units, Tape-and-Reel NoPb LP5521TM X SMD 5521 3000 units, Tape-and-Reel NoPb LP5521YQ bumped LLP L5521YQ 1000 units, Tape-and-Reel NoPb LP5521YQ X bumped LLP L5521YQ 4500 units, Tape-and-Reel NoPb 3 www.national.com LP5521 Pin Descriptions LP5521TM Pin # Name Type 1A B A Current source output Description 1B G A Current source output 1C R A Current source output 1D SCL I I2C Serial interface clock input 1E SDA I/OD 2A VOUT A Charge pump output 2B ADDR_SEL1 I I2C address select input 2C ADDR_SEL0 I I2C address select input 2D GPO O General purpose output 2E EN I Chip enable 3A CFLY2N A Negative terminal of charge pump fly capacitor 2 3B CFLY1N A Negative terminal of charge pump fly capacitor 1 3C GND G Ground 3D CLK_32K I 32 kHz clock input 3E INT OD/O 4A CFLY2P A Positive terminal of charge pump fly capacitor 2 I2C Serial interface data input/output Interrupt output / General Purpose Output 4B CFLY1P A Positive terminal of charge pump fly capacitor 1 4C VDD P Power supply pin 4D GND G Ground 4E TRIG I/OD Trigger input/output A: Analog Pin, G: Ground Pin, P: Power Pin, I: Input Pin, I/O: Input/Output Pin, O: Output Pin, OD: Open Drain Pin www.national.com 4 LP5521 Pin Descriptions LP5521YQ Pin # Name Type 1 CFLY2P A Positive terminal of charge pump fly capacitor 2 Description 2 CFLY1P A Positive terminal of charge pump fly capacitor 1 3 VDD P Power supply pin 4 GND G Ground 5 CLK_32K I 32 kHz clock input 6 INT OD/O Interrupt output / General purpose output 7 TRIG I/OD Trigger input/output 8 N/C 9 N/C 10 N/C 11 N/C 12 N/C 13 SDA I/OD I2C Serial interface data input/output 14 EN I Chip enable 15 SCL I I2C Serial interface clock input 16 GPO O General purpose output 17 R A Current source output 18 G A Current source output 19 B A Current source output 20 ADDR_SEL0 I I2C address select input 21 ADDR_SEL1 I I2C address select input 22 VOUT A Charge pump output 23 CFLY2N A Negative terminal of charge pump fly capacitor 2 24 CFLY1N A Negative terminal of charge pump fly capacitor 1 A: Analog Pin, G: Ground Pin, P: Power Pin, I: Input Pin, I/O: Input/Output Pin, O: Output Pin, OD: Open Drain Pin, N/C: Not Connected 5 www.national.com LP5521 Operating Ratings Absolute Maximum Ratings (Notes 1, 2) (Notes 1, 2) VDD 2.7 to 5.5V Recommended Charge Pump Load Current IOUT 0 to 100 mA Junction Temperature (TJ) Range -30C to +125C Ambient Temperature (TA) Range (Note 6) -30C to +85C If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. V(VDD , VOUT, R, G, B) Voltage on Logic Pins Continuous Power Dissipation (Note 3) Junction Temperature (TJ-MAX) Storage Temperature Range Maximum Lead Temperature (Soldering) ESD Rating (Note 5) Human Body Model: Machine Model: -0.3V to +6.0V -0.3V to VDD +0.3V with 6.0V max Internally Limited Thermal Properties Junction-to-Ambient Thermal Resistance (JA), TMD20 Package (Note 7) Junction-to-Ambient Thermal Resistance (JA), YQA24A Package (Note 7) 125C -65C to +150C (Note 4) 2 kV 200V 50 - 90C/W 37 - 90C/W Electrical Characteristics (Notes 2, 8) Limits in standard typeface are for TJ = 25C. Limits in boldface type apply over the operating ambient temperature range (-30C < TA < +85C). Unless otherwise noted, specifications apply to the LP5521 Block Diagram with: 2.7V VDD 5.5V, COUT= CIN = 1 F, CFLY1 = CFLY2 = 0.47 F. (Note 9). Symbol IVDD Parameter Standby supply current Normal mode supply current Powersave mode supply current fOSC Typ Max Units EN = 0 (pin), CHIP_EN = 0 (bit), external 32 kHz clock running or not running Condition Min 0.2 2 A EN = 1 (pin), CHIP_EN = 0 (bit), external 32 kHz clock not running 1.0 EN = 1 (pin), CHIP_EN = 0 (bit), external 32 kHz clock running 1.4 A Charge pump and LED drivers disabled 0.25 mA Charge pump in 1x mode, no load, LED drivers disabled 0.70 mA Charge pump in 1.5x mode, no load, LED drivers disabled 1.5 mA Charge pump in 1x mode, no load, LED drivers enabled 1.2 mA External 32 kHz clock running 10 A 0.25 mA Internal oscillator running Internal oscillator frequency accuracy -4 -7 Charge Pump Electrical Characteristics Symbol ROUT Parameter Charge pump output resistance 4 7 Condition Min Gain = 1.5x Switching frequency Typ Units 1 MHz % 1.25 7 Gain = 1.5x 1.2 mA Gain = 1x 0.5 mA tON VOUT turn-on time from charge pump VDD = 3.6V, CHIP_EN = H off to 1.5x mode IOUT = 60 mA 100 s VOUT Charge pump output voltage 4.55 V www.national.com Ground current Max 3.5 -7 IGND % (Note 10) Gain = 1x fSW A VDD = 3.6V, no load, Gain = 1.5x 6 LP5521 LED Driver Electrical Characteristics (R, G, B Outputs) Symbol Parameter Condition Min Typ Max Units 0.1 1 A ILEAKAGE R, G, B pin leakage current IMAX Maximum Source Current Outputs R, G, B IOUT Accuracy of output current Output current set to 17.5 mA, VDD = 3.6V IMATCH Matching (Note 11) IOUT = 17.5 mA, VDD = 3.6V fLED LED PWM switching frequency PWM_HF = 1 Frequency defined by internal oscillator 558 Hz PWM_HF = 0 Frequency defined by 32 kHz clock (internal or external) 256 Hz IOUT set to 17.5 mA 50 VSAT Saturation voltage (Note 12) 25.5 mA -4 -5 1 4 5 % 2 % 100 mV Logic Interface Characteristics (V(EN) = 1.65V...VDD unless otherwise noted) Symbol Parameter Conditions Min Typ Max Units 0.5 V LOGIC INPUT EN VIL Input Low Level VIH Input High Level 1.2 II Logic Input Current -1.0 tDELAY Input delay V A 1.0 2 s LOGIC INPUT SCL, SDA, TRIG, CLK_32K VIL Input Low Level VIH Input High Level II Input Current fCLK_32K Clock frequency fSCL Clock frequency 0.2xV(EN) V V 0.8xV(EN) -1.0 A 1.0 32 kHz kHz 400 LOGIC OUTPUT SDA, TRIG, INT VOL Output Low Level IL Output Leakage Current IOUT = 3 mA (pull-up current) 0.3 0.5 V 1.0 A 0.2xVDD V LOGIC INPUT ADDR_SEL0, ADDR_SEL1 VIL Input Low Level VIH Input High Level II Input Current 0.8xVDD V -1.0 1.0 A 0.5 V LOGIC OUTPUT GPO, INT (in GPO state) VOL Output Low Level IOUT = 3 mA VOH Output High Level IOUT = -2 mA IL Output leakage current 0.3 VDD - 0.5 VDD - 0.3 V 1.0 7 A www.national.com LP5521 I2C Timing Parameters (SDA, SCL) Symbol fSCL (Note 13) Limit Parameter Min Clock Frequency Max 400 Units kHz 1 Hold Time (repeated) START Condition 0.6 s 2 Clock Low Time 1.3 s 3 Clock High Time 600 ns 4 Setup Time for a Repeated START Condition 600 ns 5 Data Hold Time 50 ns 6 Data Setup Time 7 Rise Time of SDA and SCL 20+0.1Cb 300 ns 8 Fall Time of SDA and SCL 15+0.1Cb 300 ns 100 ns 9 Set-up Time for STOP condition 600 ns 10 Bus Free Time between a STOP and a START Condition 1.3 s Cb Capacitive Load for Each Bus Line 10 200 pF 20186298 Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the component may occur. Operating Ratings are conditions under which operation of the device is guaranteed. Operating Ratings do not imply guaranteed performance limits. For guaranteed performance limits and associated test conditions, see the Electrical Characteristics tables. Note 2: All voltages are with respect to the potential at the GND pins. Note 3: Internal thermal shutdown circuitry protects the device from permanent damage. Thermal shutdown engages at TJ = 150C (typ.) and disengages at TJ = 130C (typ.). Note 4: For detailed soldering specifications and information, please refer to National Semiconductor Application Note AN1112 : Micro SMD Wafer Level Chip Scale Package or AN1187 : Leadless Leadframe Package (LLP). Note 5: The Human body model is a 100 pF capacitor discharged through a 1.5 k resistor into each pin. The machine model is a 200 pF capacitor discharged directly into each pin. MIL-STD-883 3015.7 Note 6: In applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature may have to be derated. Maximum ambient temperature (TA-MAX) is dependent on the maximum operating junction temperature (TJ-MAX-OP = 125C), the maximum power dissipation of the device in the application (PD-MAX), and the junction-to ambient thermal resistance of the part/package in the application (JA), as given by the following equation: TA-MAX = TJ-MAX-OP - (JA x PD-MAX). Note 7: Junction-to-ambient thermal resistance is highly application and board-layout dependent. In applications where high maximum power dissipation exists, special care must be paid to thermal dissipation issues in board design. Note 8: Min and Max limits are guaranteed by design, test, or statistical analysis. Typical numbers are not guaranteed, but do represent the most likely norm. Note 9: Low-ESR Surface-Mount Ceramic Capacitors (MLCCs) used in setting electrical characteristics. Note 10: Input, output, and fly capacitors should be of the type X5R or X7R low ESR ceramic capacitor. Note 11: Matching is the maximum difference from the average of the three output's currents. Note 12: Saturation voltage is defined as the voltage when the LED current has dropped 10% from the value measured at VOUT - 1V. Note 13: Guaranteed by design. www.national.com 8 LP5521 Typical Performance Characteristics Unless otherwise specified: VDD = 3.6V LED Drive Efficiency vs. Input Voltage Automatic Gain Change LED Current vs. Output Pin Headroom Voltage 20186222 20186221 LED Current vs. Current Register Code LED Current vs. Supply Voltage 20186223 20186207 Charge Pump Efficiency vs. Load Current Charge Pump Efficiency vs. Input Voltage 1.5x Mode 20186208 20186209 9 www.national.com LP5521 Charge Pump Output Voltage vs. Load Current Charge Pump Output Voltage vs. Input Voltage Automatic Gain Change from 1x to 1.5x 20186210 20186211 Charge Pump Automatic Gain Change Hysteresis Charge Pump Startup in 1.5x Mode No Load 20186212 20186213 Charge Pump Load Transient Response in 1.5x Mode (0 to 25.5 mA) Charge Pump Line Transient Response 1.5x Mode (VIN 3.5V to 4.0V) 20186214 20186215 www.national.com 10 LP5521 Charge Pump Automatic Gain Change (LED VF = 3.6V) Standby Current vs. Input Voltage 20186217 20186216 11 www.national.com LP5521 Block Diagram 20186274 www.national.com 12 RESET: In the RESET mode all the internal registers are reset to the default values. Reset is done always if Reset Register (0DH) is written FFH or internal Power On Reset is activated. Power On Reset (POR) will activate when supply voltage is connected or when the supply voltage VDD falls below 1.5V. Once VDD rises above 1.5V, POR will inactivate and the chip will continue to the STANDBY mode. CHIP_EN control bit is low after POR by default. STANDBY: The STANDBY mode is entered if the register bit CHIP_EN or EN pin is LOW and Reset is not active. This is the low power consumption mode, when all circuit functions are disabled. Registers can be written in this mode if EN pin is high. Control bits are effective after start up. STARTUP: When CHIP_EN bit is written high and EN pin is high, the INTERNAL STARTUP SEQUENCE powers up all the needed internal blocks (VREF, Bias, Oscillator etc.). Startup delay is 500 s. If the chip temperature rises too high, the Thermal Shutdown (TSD) disables the chip operation and the chip state is in STARTUP mode, until no thermal shutdown event is present.(Note 3) NORMAL: During NORMAL mode the user controls the chip using the Control Registers. If EN pin is set low, the CHIP_EN bit is reset to 0. POWER SAVE: In POWER SAVE mode analog blocks are disabled to minimize power consumption. See chapter Power Save Mode for further information. 20186275 13 www.national.com LP5521 Modes of Operation LP5521 Charge Pump Operational Description OVERVIEW The LP5521 includes a pre-regulated switched-capacitor charge pump with a programmable voltage multiplication of 1 and 1.5x. On 1.5x mode by combining the principles of a switched-capacitor charge pump and a linear regulator, it generates a regulated 4.5V output from Li-Ion input voltage range. A twophase non-overlapping clock generated internally controls the operation of the charge pump. During the charge phase, both flying capacitors (CFLY1 and CFLY2) are charged from input voltage. In the pump phase that follows, the flying capacitors are discharged to output. A traditional switched capacitor charge pump operating in this manner will use switches with very low on-resistance, ideally 0, to generate an output voltage that is 1.5x the input voltage. The LP5521 regulates the output voltage by controlling the resistance of the input-connected pass-transistor switches in the charge pump. OUTPUT RESISTANCE At lower input voltages, the charge pump output voltage may degrade due to effective output resistance (ROUT) of the charge pump. The expected voltage drop can be calculated by using a simple model for the charge pump illustrated in following figure. CONTROLLING CHARGE PUMP Charge pump is controlled with two CP_MODE bits in register 08H. When both bits are low, charge pump is disabled and output voltage is pulled down with 300 k. Charge pump can be forced to bypass mode, so battery voltage is going directly to RGB outputs. In 1.5x mode output voltage is boosted to 4.5V. In automatic mode, charge pump operation mode is defined by LED outputs saturation like described in LED Forward Voltage Monitoring. In following table are listed operation modes and selection bits. CONFIG register (08H): Name Bit Description CP_MODE 4:3 Charge Pump Operation Mode 00b = OFF 01b = Forced to bypass mode (1x) 10b = Forced to 1.5x mode 11b = Automatic mode selection LED FORWARD VOLTAGE MONITORING When charge pump automatic mode selection is enabled, voltages over LED drivers are monitored. If drivers do not have enough headroom, charge pump gain is set to 1.5x. Driver saturation monitor does not have a fixed voltage limit, since saturation voltage is a function of temperature and current. Charge pump gain is set to 1x, when battery voltage is high enough to supply all LEDs. In automatic gain change mode, charge pump is switched to bypass mode (1x), when LEDs are inactive for over 50 ms. Charge pump gain control utilizes digital filtering to prevent supply voltage disturbances from triggering gain changes. If R driver current source is connected to battery (address 08H, bit R_TO_BATT = 1) voltage monitoring is disabled in R output, but still functional in B and G output. LED forward voltage monitoring and gain control block diagram is shown below. 20186297 The model shows a linear pre-regulation block (REG), a voltage multiplier (1.5x), and an output resistance (ROUT). Output resistance models the output voltage drop that is inherent to switched capacitor converters. The output resistance is 3.5 (typ), and is function of switching frequency, input voltage, flying capacitors' capacitance value, internal resistances of switches and ESR of flying capacitors. When the output voltage is in regulation, the regulator in the model controls the voltage V' to keep the output voltage equal to 4.5V (typ). With increased output current, the voltage drop across ROUT increases. To prevent drop in output voltage, the voltage drop across the regulator is reduced, V' increases, and VOUT remains at 4.5V. When the output current increases to the point that there is zero voltage drop across the regulator, V' equals the input voltage, and the output voltage is "on the edge" of regulation. Additional output current causes the output voltage to fall out of regulation, so that the operation is similar to a basic open-loop 1.5x charge pump. In this mode, output current results in output voltage drop proportional to the output resistance of the charge pump. The out-of-regulation output voltage can be approximated by: VOUT= 1.5 x VIN - IOUT x ROUT. 20186255 Voltage monitoring block diagram for one output www.national.com 14 LP5521 LED Driver Operational Description The LP5521 LED drivers are constant current sources with 8bit PWM control. Output current can be programmed with I2C register up to 25.5 mA. Current setting resolution is 100 A (8-bit control). R driver has two modes: current source can be connected to battery (VDD) or to charge pump output. If current source is connected to battery, automatic charge pump gain control is not used for this output. This approach provides better efficiency when LED with low VF is connected to R driver, and battery voltage is high enough to drive this LED in all conditions. R driver mode can be selected with I2C register bit. When address 08H, bit R_TO_BATT = 1, R current source is connected to battery. When it is 0 (default), R current source is connected to charge pump same way as in G and B drivers. G and B drivers are always connected to charge pump output. Some LED configuration examples are given in table below. When LEDs with low VF are used, charge pump can be operating in bypass mode (1x). This eliminates the need of having double drivers for all outputs; one connected to battery and another connected to charge pump output. When LP5521 is driving a RGB LED, R channel can be configured to use battery power. This configuration increases power efficiency by minimizing the voltage drop across the LED driver. LED configuration examples Configuration R output to BATT RGB LED with low VF red R output to CP X CP Mode Auto (1x or 1.5x) 3 x low VF LED X 1x 3 x white LED X Auto (1x or 1.5x) 1 x low VF LED (R output) X Disabled PWM frequency is either 256 Hz or 558 Hz, frequency is set with PWM_HF bit in register 08H. When PWM_HF is 0, then the frequency is 256 Hz, and when bit is 1 then the PWM frequency is 558 Hz. Brightness adjustment is either linear or logarithmic. This can be set with register 00H LOG_EN bit. When LOG_EN = 0 linear adjustment scale is used, and when LOG_EN = 1 logarithmic scale is used. By using logarithmic scale the visual effect seems linear to the eye. Register control bits are presented in following tables: R_CURRENT register (05H), G_CURRENT register (06H), B_CURRENT register (07H): Name Bit Description CURRENT 7:0 Current setting bin hex dec mA 0000 0000 0000 0001 0000 0010 0000 0011 0000 0100 0000 0101 0000 0110 ... 1010 1111 ... 1111 1011 1111 1100 1111 1101 1111 1110 1111 1111 00 01 02 03 04 05 06 ... AF ... FB FC FD FE FF 0 1 2 3 4 5 6 ... 175 ... 251 252 253 254 255 0.0 0.1 0.2 0.3 0.4 0.5 0.6 ... 17.5 (def) ... 25.1 25.2 25.3 25.4 25.5 ENABLE register (00H): Name Bit LOG_EN 7 Description Logarithmic PWM adjustment enable bit 0 = Linear adjustment 1 = Logarithmic adjustment CONFIG register (08H): Name Bit PWM_HF 6 Description PWM clock frequency 0 = 256 Hz, frequency defined by 32 kHz clock (internal or external) 1 = 558 Hz, frequency defined by internal oscillator 15 www.national.com LP5521 Logarithmic and Linear PWM Adjustment Curves 20186218 separately. MODE registers are synchronized to 32 kHz clock. Delay between consecutive I2C writes to OP_MODE register (01H) need to be longer than 153 s (typ). LED Controller Operation Modes Operation modes are defined in register address 01H. Each output channel (R, G, B) operation mode can be configured OP_MODE register (01H): www.national.com Name Bit Description R_MODE 5:4 R channel operation mode 00b = Disabled, reset R channel PC 01b = Load program to SRAM, reset R channel PC 10b = Run program defined by R_EXEC 11b = Direct control, reset R channel PC G_MODE 3:2 G channel operation mode 00b = Disabled, reset G channel PC 01b = Load program to SRAM, reset G channel PC 10b = Run program defined by G_EXEC 11b = Direct control, reset G channel PC B_MODE 1:0 B channel operation mode 00b = Disabled, reset B channel PC 01b = Load program to SRAM, reset B channel PC 10b = Run program defined by B_EXEC 11b = Direct control, reset B channel PC 16 R Channel PC register (09H), G CHANNEL PC register (0AH), B CHANNEL PC register (0BH) Name Bit Description PC 3:0 Program counter value from 0 to 15d ENABLE register (00H) Name Bit Description R_EXEC 5:4 R channel program execution 00b = Hold: Wait until current command is finished then stop while EXEC mode is hold. PC can be read or written only in this mode. 01b = Step: Execute instruction defined by current R channel PC value, increment PC and change R_EXEC to 00b (Hold) 10b = Run: Start at program counter value defined by current R channel PC value 11b = Execute instruction defined by current R channel PC value and change R_EXEC to 00b (Hold) G_EXEC 3:2 G channel program execution 00b = Hold: Wait until current command is finished then stop while EXEC mode is hold. PC can be read or written only in this mode. 01b = Step: Execute instruction defined by current G channel PC value, increment PC and change G_EXEC to 00b (Hold) 10b = Run: Start at program counter value defined by current G channel PC value 11b = Execute instruction defined by current G channel PC value and change G_EXEC to 00b (Hold) B_EXEC 1:0 B channel program execution 00b = Hold: Wait until current command is finished then stop while EXEC mode is hold. PC can be read or written only in this mode. 01b = Step: Execute instruction defined by current B channel PC value, increment PC and change B_EXEC to 00b (Hold) 10b = Run: Start at program counter value defined by current B channel PC value 11b = Execute instruction defined by current B channel PC value and change B_EXEC to 00b (Hold) EXEC registers are synchronized to 32 kHz clock. Delay between consecutive I2C writes to ENABLE register (00H) need to be longer than 488 s (typ.). 17 www.national.com LP5521 tion continues when all channels are out of LOAD program mode. LOAD Program mode resets respective channel's PC. RUN PROGRAM RUN Program mode executes the commands defined in program memory for respective channel (R, G, B). Execution register bits in ENABLE register define how program is executed. Program start position can be programmed to Program Counter register (see the following tables). By manually selecting the PC start value, user can write different lighting sequences to the memory, and select appropriate sequence with the PC register. If program counter runs to end (15) the next command will be executed from program location 0. If internal clock is used in the RUN program mode, operation mode needs to be written disabled (00b) before disabling the chip (with CHIP_EN bit or EN pin) to ensure that the sequence starts from the correct program counter (PC) value when restarting the sequence. PC registers are synchronized to 32 kHz clock. Delay between consecutive I2C writes to PC registers (09H, 0AH, 0BH) need to be longer than 153 s (typ.). DISABLED Each channel can be configured to disabled mode. LED output current will be 0 during this mode. Disabled mode resets respective channel's PC. LOAD Program LP5521 can store 16 commands for each channel (R, G, B). Each command consists of 16 bits. Because one register has only 8 bits, one command requires two I2C register addresses. In order to reduce program load time LP5521 supports address auto incrementation. Register address is incremented after each 8 data bits. Whole program memory can be written in one I2C write sequence. Program memory is defined in the LP5521 register table, 10H to 2FH for R channel, 30H to 4FH for G channel and 50H to 6FH for B channel. In order to be able to access program memory at least one channel operation mode needs to be LOAD Program. Memory writes are allowed only to the channel in LOAD mode. All channels are in hold while one or several channels are in LOAD program mode, and PWM values are frozen for the channels which are not in LOAD mode. Program execu- LP5521 control register. With output current control register is set what is the maximum output current with 8-bit resolution, step size is 100 A. Duty cycle can be set with 8-bit resolution. Direct control mode resets respective channel's PC. PWM control bits are presented in following table: DIRECT Control When R, G or B channel mode is set to 00b, the LP5521 drivers work in direct control mode. LP5521 LED channels can be controlled independently through I2C. For each channel there is a PWM control register and a output current R_PWM register (02H), G_PWM register (03H), B_PWM register (04H): Name Bit Description PWM 7:0 LED PWM value during direct control operation mode 0000 0000b = 0% 1111 1111b = 100% If charge pump automatic gain change is used in this mode, then PWM values need to be written 0 before changing the www.national.com drivers' operation mode to disabled (00b) to ensure proper automatic gain change operation. 18 LP5521 has three independent programmable channels (R, G, B). Trigger connections between channels are common for all channels. All channels have own program memories for storing complex patterns. Brightness control and patterns are done with 8-bit PWM control (256 steps) to get accurate and smooth color control. Program execution is timed with 32 768 Hz clock. This clock can be generated internally or external 32 kHz clock can be connected to CLK_32K pin. Using external clock enables synchronization of LED timing to this clock rather than internal Command 15 14 Ramp Wait 0 Prescale 13 12 11 10 Step time Set PWM 0 1 0 Go to Start 0 0 Branch 1 0 1 End 1 1 0 Trigger 1 1 1 clock. Selection of the clock is made with address 08H bits INT_CLK_EN and CLK_DET_EN. See External Clock Detection for details. Supported commands are listed in the table below. Command compiler is available for easy sequence programming. With Command compiler it is possible to write sequences with simple ASCII commands, which are then converted to binary or hex format. See application note "LP5521 Programming Considerations" for examples of Command compiler usage. 9 8 7 6 Sign 4 3 2 1 0 Increment (number of steps) PWM Value 0 0 0 Loop count Int 5 0 0 x 0 0 0 0 Step / command number Reset X Wait for trigger on channels 5-0 Send trigger on channels 5-0 X X means do not care whether 1 or 0. Ramp/Wait Ramp command generates a PWM ramp starting from current value. At each ramp step the output is incremented by one. Time for one step is defined with Prescale and Step time bits. Minimum time for one step is 0.49 ms and maximum time is 63 x 15.6 ms = 1 second/step, so it is possible to program very fast and also very slow ramps. Increment value defines how many steps are taken in one command. Number of actual steps is Increment + 1. Maximum value is 127d, which corresponds to half of full scale (128 steps). If during ramp command PWM reaches minimum/maximum (0/255) ramp command will be executed to the end and PWM will stay at minimum/maximum. This enables ramp command to be used as combined ramp and wait command in a single instruction. Ramp command can be used as wait instruction when increment is zero. Setting register 00H bit LOG_EN sets the scale from linear to logarithmic. When LOG_EN = 0 linear scale is used, and when LOG_EN = 1 logarithmic scale is used. By using logarithmic scale the visual effect of the ramp command seems linear to the eye. Ramp/Wait command 15 14 0 Prescale Name Prescale Step time Sign Increment 13 12 11 10 9 8 7 Step time Sign 6 5 4 3 2 1 0 Increment Value(d) Description 0 Divides master clock (32 768Hz) by 16 = 2048 Hz, 0.49 ms cycle time 1 Divides master clock (32 768Hz) by 512 = 64 Hz, 15.6 ms cycle time 1-63 One ramp increment done in (step time) x (clock after prescale) Note: 0 means Set PMW command. 0 Increase PWM output 1 Decrease PWM output 0-127 The number of steps is Increment + 1. Note: 0 is a wait instruction. 19 www.national.com LP5521 LED Controller Programming Commands LP5521 Ramp command will be: 0100 0010 0000 0100b = 4204H If current PWM value is 3, and the first command is as described above and next command is a ramp with otherwise same parameters, but with Sign = 1 (Command = 4284H), the result will be like in the following figure: Application example: For example if following parameters are used for ramp: * Prescale = 1 => cycle time = 15.6 ms * Step time = 2 => time = 15.6 ms x 2 = 31.2 ms * Sign = 0 => rising ramp * Increment = 4 => 5 cycles 20186219 Example of 2 sequential ramp commands. Set PWM Set PWM output value from 0 to 255. Command takes sixteen 32 kHz clock cycles (= 488 s). Setting register 00H bit LOG_EN sets the scale from linear to logarithmic. Set PWM command 15 14 13 12 11 10 9 8 0 1 0 0 0 0 0 0 7 6 5 4 3 2 1 0 PWM value mand takes sixteen 32 kHz clock cycles. Note that default value for all program memory registers is 0000H, which is Go to start command. Go to start Go to start command resets Program Counter register and continues executing program from the 00H location. ComGo to start command 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 parameter. Nested looping is supported (loop inside loop). The number of nested loops is not limited. Command takes sixteen 32kHz clock cycles. Branch When branch command is executed, the 'step number' value is loaded to PC and program execution continues from this location. Looping is done by the number defined in loop count Branch command 15 14 13 1 0 1 12 11 10 9 8 7 Loop count 6 5 4 X X X 3 2 1 0 Step number Name Value(d) loop count 0-63 The number of loops to be done. 0 means infinite loop. Description step number 0-15 The step number to be loaded to program counter. End End program execution, resets the program counter and sets the corresponding EXEC register to 00b (hold). Command takes sixteen 32 kHz clock cycles. End command 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 1 0 int reset X X X X X X X X X X X www.national.com 20 Value int reset LP5521 Name Description 0 No interrupt will be sent. 1 Send interrupt to processor by pulling the INT pin down and setting corresponding status register bit high to notify that program has ended. Interrupt can only be cleared by reading interrupt status register 0CH. 0 Keep the current PWM value. 1 Set PWM value to 0. X means do not care whether 1 or 0. Trigger Wait or send triggers can be used to e.g. synchronize operation between different channels. Send trigger command takes sixteen 32 kHz clock cycles and wait for trigger takes at least sixteen 32 kHz clock cycles. The receiving channel stores sent triggers. Received triggers are cleared by wait for trigger command if received triggers match to channels defined in the command. Channel waits for until all defined triggers have been received. External trigger input signal must be at least two 32 kHz clock cycles (= 61 s typ.) long to be recognized. Trigger output signal is three 32 kHz clock cycles (92 s typ.) long. External trigger signal is active low, i.e. when trigger is sent/received the pin is pulled to GND. Sent external trigger is masked, i.e. the device which has sent the trigger will not recognize it. If send and wait external trigger are used on the same command, the send external trigger is executed first, then the wait external trigger. Trigger command 15 14 13 1 1 1 12 11 10 9 8 7 6 5 G R EXT wait trigger <5:0> EXT X B 4 3 2 1 G R send trigger <5:0> X B Name Value(d) Description wait trigger<5:0> 0-31 Wait for trigger for the channel(s) defined. Several triggers can be defined in the same command. Bit 0 is R, bit 1 is G, bit 2 is B and bit 5 is external trigger I/O. Bits 3 and 4 are not in use. send trigger<5:0> 0-31 Send trigger for the channel(s) defined. Several triggers can be defined in the same command. Bit 0 is R, bit 1 is G, bit 2 is B and bit 5 is external trigger I/O. Bits 3 and 4 are not in use. 0 X X means do not care whether 1 or 0. 21 www.national.com LP5521 Power Save Mode Automatic power save mode is enabled when PWRSAVE_EN bit in register address 08H is 1. Almost all analog blocks are powered down in power save, if external clock is used. Only charge pump protection circuits remain active. However if internal clock has been selected only charge pump and led drivers are disabled during power save since digital part of the LED controller need to remain active. In both cases charge pump enters 'weak 1x' mode. In this mode charge pump utilizes a passive current limited keepalive switch, which keeps the output voltage at battery level. During program execution LP5521 can enter power save if there is no PWM activity in R, G and B outputs. To prevent short power save sequences during program execution, LP5521 has command look-ahead filter. In every instruction cycle R, G, B commands are analyzed, and if there is sufficient time left with no PWM activity, device will enter power save. In power save program execution continues uninterruptedly. When a command that requires PWM activity is executed, fast internal start-up sequence will be started automatically. Following tables describe commands and conditions that can activate power save. All channels (R,G,B) need to meet power save condition in order to enable power save. LED controller operation mode (R,G,B_MODE) Power save condition 00b Disabled mode enables power save 01b Load program to SRAM mode prevents power save 10b Run program mode enables power save if there is no PWM activity and command look-ahead filter condition is met 11b Direct control mode enables power save if there is no PWM activity Command Power save condition Wait No PWM activity and current command wait time longer than 50 ms. If prescale = 1 then wait time needs to be longer than 80 ms. Ramp Ramp Command PWM value reaches minimum 0 and current command execution time left more than 50 ms. If prescale = 1 then time left needs to be more than 80 ms. Trigger No PWM activity during wait for trigger command execution. End No PWM activity or Reset bit = 1 Enables power save if PWM set to 0 and next command generates at least 50 ms wait Set PWM Other commands No effect to power save See application note "LP5521 Power Efficiency Considerations" for more information. External Clock Detection The presence of external clock can be detected by the LP5521. Program execution is clocked with internal 32 kHz clock or with external clock. Clocking is controlled with register address 08H bits, INT_CLK_EN and CLK_DET_EN as seen on the following table. External clock can be used if clock is present at CLK_32K pin. External clock frequency must be 32 kHz for the program execution / PWM timing to be like specified. If higher or lower frequency is used, it will affect the program engine execution speed. If other than 32kHz clock frequency is used, the program execution timings must be scaled accordingly. The external clock detector block only detects too low clock frequency (<15 kHz). If external clock frequency is higher than specified, the external clock detector notifies that external clock is present. External clock status can be checked with read only bit EXT_CLK_USED in register address 0CH, when the external clock detection is enabled (CLK_DET_EN bit = high). If EXT_CLK_USED = 1, then the external clock is detected and it is used for timing, if automatic clock selection is enabled (see table below). If external clock is stuck-at-zero or stuck-at-one, or the clock frequency is too low, the clock detector indicates that external clock is not present. If external clock is not used on the application, CLK_32K pin should be connected to GND to prevent floating of this pin and extra current consumption. CONFIG register (08H): Name CLK_DET_EN, INT_CLK_EN www.national.com Bit 1:0 Description LED Controller clock source 00b = External clock source (CLK_32K) 01b = Internal clock 10b = Automatic selection 11b = Internal clock 22 LP5521 Logic Interface Operational Description LP5521 features a flexible logic interface for connecting to processor and peripheral devices. Communication is done with I2C compatible interface and different logic input/output pins makes it possible to synchronize operation of several devices. IO Levels I2C interface, CLK_32K and TRIG pins input levels are defined by EN pin. Using EN pin as voltage reference for logic inputs simplifies PWB routing and eliminates the need for dedicated VIO pin. In the following block diagram is described EN pin connections. GPO register (0EH) Name Bit INT_AS_GPO 2 Enable INT pin GPO function 0 = INT pin functions as a INT pin 1 = INT pin functions as a GPO pin GPO 1 0 = GPO pin state is low 1 = GPO pin state is high 0 0 = INT pin state is low (INT_AS_GPO=1) 1 = INT pin state is high (INT_AS_GPO=1) INT Description TRIG pin TRIG pin can function as an external trigger input or output. External trigger signal is active low, i.e. when trigger is sent/ received the pin is pulled to GND. TRIG is an open drain pin and external pull-up resistor is needed for trigger line. External trigger input signal must be at least two 32 kHz clock cycles long to be recognized. Trigger output signal is three 32 kHz clock cycles long. If TRIG pin is not used on application, it should be connected to GND to prevent floating of this pin and extra current consumption. ADDR_SEL0,1 pins ADDR_SEL0,1 pins define the chip I2C address. Pins are referenced to VDD signal level. See I2C Compatible Serial Bus Interface chapter for I2C address definitions. CLK_32K pin CLK_32K pin is used for connecting external 32 kHz clock to LP5521. External clock can be used to synchronize the sequence engines of several LP5521. Using external clock can also improve automatic power save mode efficiency, because internal clock can be switched off automatically when device has entered power save mode, and external clock is present. See application note "LP5521 Power Efficiency Considerations" for more information. Device can be used without the external clock. If external clock is not used on the application, CLK_32K pin should be connected to GND to prevent floating of this pin and extra current consumption. 20186254 Using EN pin as digital IO voltage reference ADDR_SEL0/1 are referenced to VDD voltage. GPO pin level is defined by VDD voltage. GPO/INT pins LP5521 has one General Purpose Output pin (GPO) and also INT pin can be configured as a GPO pin. When INT is configured as GPO output, it's level is defined by the VDD voltage. State of the pins can be controlled with GPO register (0EH). GPO pins are digital CMOS outputs and no pull-up/down resistors are needed. When INT pin GPO function is disabled, it operates as an open drain pin. INT signal is active low, i.e. when interrupt signal is sent, the pin is pulled to GND. External pull-up resistor is needed for proper functionality. 23 www.national.com LP5521 The Master device on the bus always generates the Start and Stop Conditions (control codes). After a Start Condition is generated, the bus is considered busy and it retains this status until a certain time after a Stop Condition is generated. A high-to-low transition of the data line (SDA) while the clock (SCL) is high indicates a Start Condition. A low-to-high transition of the SDA line while the SCL is high indicates a Stop Condition. I2C Compatible Serial Bus Interface Interface Bus Overview The I2C compatible synchronous serial interface provides access to the programmable functions and registers on the device. This protocol uses a two-wire interface for bidirectional communications between the IC's connected to the bus. The two interface lines are the Serial Data Line (SDA), and the Serial Clock Line (SCL). These lines should be connected to a positive supply, via a pull-up resistor and remain HIGH even when the bus is idle. Every device on the bus is assigned a unique address and acts as either a Master or a Slave depending on whether it generates or receives the serial clock (SCL). Data Transactions One data bit is transferred during each clock pulse. Data is sampled during the high state of the serial clock (SCL). Consequently, throughout the clock's high period, the data should remain stable. Any changes on the SDA line during the high state of the SCL and in the middle of a transaction, aborts the current transaction. New data should be sent during the low SCL state. This protocol permits a single data line to transfer both command/control information and data using the synchronous serial clock. 20186250 Start and Stop Conditions In addition to the first Start Condition, a repeated Start Condition can be generated in the middle of a transaction. This allows another device to be accessed, or a register read cycle. Acknowledge Cycle The Acknowledge Cycle consists of two signals: the acknowledge clock pulse the master sends with each byte transferred, and the acknowledge signal sent by the receiving device. The master generates the acknowledge clock pulse on the ninth clock pulse of the byte transfer. The transmitter releases the SDA line (permits it to go high) to allow the receiver to send the acknowledge signal. The receiver must pull down the SDA line during the acknowledge clock pulse and ensure that SDA remains low during the high period of the clock pulse, thus signaling the correct reception of the last data byte and its readiness to receive the next byte. 20186249 Data Validity "ACKNOWLEDGE AFTER EVERY BYTE" RULE The master generates an acknowledge clock pulse after each byte transfer. The receiver sends an acknowledge signal after every byte received. There is one exception to the "acknowledge after every byte" rule. When the master is the receiver, it must indicate to the transmitter an end of data by not-acknowledging ("negative acknowledge") the last byte clocked out of the slave. This "negative acknowledge" still includes the acknowledge clock pulse (generated by the master), but the SDA line is not pulled down. Each data transaction is composed of a Start Condition, a number of byte transfers (set by the software) and a Stop Condition to terminate the transaction. Every byte written to the SDA bus must be 8 bits long and is transferred with the most significant bit first. After each byte, an Acknowledge signal must follow. The following sections provide further details of this process. ADDRESSING TRANSFER FORMATS Each device on the bus has a unique slave address. The LP5521 operates as a slave device with the 7-bit address. LP5521 I2C address is pin selectable from four different choices. If 8-bit address is used for programming, the 8th bit is 1 for read and 0 for write. In the following table is represented the 8-bit I2C addresses. 20186220 Acknowledge Signal www.national.com 24 ADDR_SEL [1:0] I2C address write (8 bits) I2C address read (8 bits) 00 01 10 11 0110 0100 = 64H 0110 0110 = 66H 0110 1000 = 68H 0110 1010 = 6AH 0110 0101 = 65H 0110 0111 = 67H 0110 1001 = 69H 0110 1011 = 6BH Control Register Read Cycle * Master device generates a start condition. * Master device sends slave address (7 bits) and the data direction bit (r/w = 0). * Slave device sends acknowledge signal if the slave address is correct. * Master sends control register address (8 bits). * Slave sends acknowledge signal. * Master device generates repeated start condition. * Master sends the slave address (7 bits) and the data direction bit (r/w = 1). * Slave sends acknowledge signal if the slave address is correct. * Slave sends data byte from addressed register. * If the master device sends acknowledge signal, the control register address will be incremented by one. Slave device sends data byte from addressed register. * Read cycle ends when the master does not generate acknowledge signal after data byte and generates stop condition. Address Mode I2C chip address 20186251 Control Register Write Cycle * Master device generates start condition. * Master device sends slave address (7 bits) and the data direction bit (r/w = 0). * Slave device sends acknowledge signal if the slave address is correct. * Master sends control register address (8 bits). * Slave sends acknowledge signal. * Master sends data byte to be written to the addressed register. * Slave sends acknowledge signal. * If master will send further data bytes the control register address will be incremented by one after acknowledge signal. * Write cycle ends when the master creates stop condition. Data Read <Start Condition> <Slave Address><r/w = 0>[Ack] <Register Addr.>[Ack] <Repeated Start Condition> <Slave Address><r/w = 1>[Ack] [Register Data]<Ack or NAck> ... additional reads from subsequent register address possible <Stop Condition> Data Write <Start Condition> <Slave Address><r/w='0'>[Ack] <Register Addr.>[Ack] <Register Data>[Ack] ... additional writes to subsequent register address possible <Stop Condition> <>Data from master [ ] Data from slave 25 www.national.com LP5521 Before any data is transmitted, the master transmits the address of the slave being addressed. The slave device should send an acknowledge signal on the SDA line, once it recognizes its address. The slave address is the first seven bits after a Start Condition. The direction of the data transfer (R/W) depends on the bit sent after the slave address -- the eighth bit. When the slave address is sent, each device in the system compares this slave address with its own. If there is a match, the device considers itself addressed and sends an acknowledge signal. Depending upon the state of the R/W bit (1:read, 0:write), the device acts as a transmitter or a receiver. LP5521 20186293 Register Write Format When a READ function is to be accomplished, a WRITE function must precede the READ function, as show in the Read Cycle waveform 20186294 Register Read Format w = write (SDA = 0) r = read (SDA = 1) ack = acknowledge (SDA pulled down by either master or slave) rs = repeated start id = 7-bit chip address www.national.com 26 wide capacitance tolerance (+80%, -20%) and vary significantly over temperature (Y5V: +22%, -82% over -30C to +85C range; Z5U: +22%, -56% over +10C to +85C range). Under some conditions, a nominal 1 F Y5V or Z5U capacitor could have a capacitance of only 0.1 F. Such detrimental deviation is likely to cause Y5V and Z5U capacitors to fail to meet the minimum capacitance requirements of the LP5521. The minimum voltage rating acceptable for all capacitors is 6.3V. The recommended voltage rating of the output capacitor is 10V to account for DC bias capacitance losses. Some ceramic capacitors, especially those in small packages, exhibit a strong capacitance reduction with the increased applied voltage (DC bias effect). The capacitance value can fall below half of the nominal capacitance. Choose output and input capacitor with DC bias voltage effect better than -50% at 5V voltage (0.5 F at 5V). CAPACITOR SELECTION The LP5521 requires 4 external capacitors for proper operation (CIN = COUT = 1 F, CFLY1 = CFLY2 = 470 nF). Surfacemount multi-layer ceramic capacitors are recommended. These capacitors are small, inexpensive and have very low equivalent series resistance (ESR < 20 m typ.). Tantalum capacitors, OS-CON capacitors, and aluminum electrolytic capacitors are not recommended for use with the LP5521 due to their high ESR, as compared to ceramic capacitors. For most applications, ceramic capacitors with X7R or X5R temperature characteristic are preferred for use with the LP5521. These capacitors have tight capacitance tolerance (as good as 10%) and hold their value over temperature (X7R: 15% over -55C to 125C; X5R: 15% over -55C to 85C). Capacitors with Y5V or Z5U temperature characteristic are generally not recommended for use with the LP5521. Capacitors with these temperature characteristics typically have List of Recommended External Components Model Type Vendor Voltage Rating Size inch (mm) Ceramic X5R TDK 10 V 0402 (1005) ECJ0EB1A105M Ceramic X5R Panasonic 10 V 0402 (1005) ECJUVBPA105M Ceramic X5R, array of two Panasonic 10 V 0504 1 F for COUT and CIN C1005X5R1A105K 470 nF for CFLY1-2 C1005X5R1A474K Ceramic X5R TDK 10 V 0402 (1005) ECJ0EB0J474K Ceramic X5R Panasonic 10 V 0402 (1005) User Defined LEDs 27 www.national.com LP5521 Recommended External Components LP5521 Program Load and Execution Example Startup Device and Configure Device to SRAM Write Mode: * * * * * * Supply e.g. 3.6V to VDD Supply e.g. 1.8V to EN Generate 32 kHz clock to CLK_32K pin Write to address 00H 0100 0000b (enable LP5521) Wait 500 s (start-up delay) Write to address 01H 0001 0000b (Configure R channel into "Load program to SRAM" mode) Program Load to SRAM (see figure below): * * * * * * * * Write to address 10H 0000 0011b (1st ramp command 8 MSB) Write to address 11H 0111 1111b (1st ramp command 8 LSB) Write to address 12H 0100 1101b (1st wait command 8 MSB) Write to address 13H 0000 0000b (1st wait command 8 LSB) Write to address 14H 0000 0011b (2nd ramp command 8 MSB) Write to address 15H 1111 1111b (2nd ramp command 8 LSB) Write to address 16H 0110 0000b (2nd wait command 8 MSB) Write to address 17H 0000 0000b (2nd wait command 8 LSB) Enable Powersave, charge pump automatic mode (1x / 1.5x) and use external 32 kHz clock: * Write to address 08H 0011 1000b Run program: * * Write to address 01H 0010 0000b (Configure LED controller operation mode to "Run program" in R channel Write to address 00H 0110 0000b (Configure program execution mode from "Hold" to "Run" in R channel LP5521 will generate 1100 ms long LED pattern which will be repeated infinitely. LED pattern is illustrated on the figure below. 20186224 Sequence diagram www.national.com 28 LP5521 Direct PWM Control Example Startup device: * * * * Supply e.g. 3.6V to VDD Supply e.g. 1.8V to EN Write to address 00H 0100 0000b (enable LP5521) Wait 500 s (start-up delay) Enable charge pump 1.5x mode and use internal clock: * Write to address 08H 0001 0001b Direct PWM control: * Write to address 01H 0011 1111b (Configure R, G and B channels into "Direct PWM control mode") Write PWM values: * * * Write to address 02H 1000 0000b (R driver PWM 50% duty cycle) Write to address 03H 1100 0000b (G driver PWM 75% duty cycle) Write to address 04H 1111 1111b (B driver PWM 100% duty cycle) LEDs are turned on after the PWM values are written. Changes to the PWM value registers are reflected immediately to the LED brightness. Default LED current (17.5 mA) is used for LED outputs, if no other values are written. See application note "LP5521 Programming Considerations" for more information. 29 www.national.com www.national.com 30 B CURRENT CONFIG R PC G PC B PC STATUS RESET GPO 06 07 08 09 0A 0B 0C 0D 0E PROG MEM R PROG MEM G PROG MEM G PROG MEM G PROG MEM G PROG MEM B PROG MEM B PROG MEM B PROG MEM B 2F 30 31 4E 4F 50 51 6E 6F PROG MEM R G CURRENT 05 2E R CURRENT 04 PROG MEM R B PWM 03 11 G PWM 02 PROG MEM R R PWM 01 10 ENABLE OP MODE 00 REGISTER ADDR (HEX) CHIP_EN LOG_EN PWM_HF D6 D7 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 CMD_R16[7:0] CMD_G1[15:8] CMD_G1[7:0] 0000 0000 0000 0000 0000 0000 CMD_G16[7:0] CMD_B1[15:8] CMD_B1[7:0] 0000 0000 0000 0000 CMD_B16[15:8] CMD_B16[7:0] ... 0000 0000 CMD_G16[15:8] ... 0000 0000 CMD_R16[15:8] ... 0000 0000 INT CMD_R1[7:0] GPO 0000 0000 INT_AS_GPO 0000 0000 0000 0000 B_INT B_PC[3:0] R_INT 0000 0000 G_PC[3:0] CMD_R1[15:8] RESET[7:0] EXT_CLK_USED 0000 0000 R_PC[3:0] G_INT 1010 1111 B_CURRENT[7:0] 0000 0000 1010 1111 G_CURRENT[7:0] INT_CLK_EN 1010 1111 CLK_DET_EN 0000 0000 R_CURRENT[7:0] CP_MODE[1:0] 0000 0000 0000 0000 0000 0000 DEFAULT B_PWM[7:0] R_TO_BATT B_EXEC[1:0] B_MODE[1:0] D0 G_PWM[7:0] D1 0000 0000 D2 R_PWM[7:0] G_EXEC[1:0] G_MODE[1:0] D3 R_EXEC[1:0] D4 R_MODE[1:0] PWRSAVE_EN D5 LP5521 Control Register Names and Default Values LP5521 LP5521 Enable Register (ENABLE) Address 00H Reset value 00H Enable Register 7 6 5 4 3 2 1 0 LOG_EN CHIP_EN R_EXEC[1] R_EXEC[0] G_EXEC[1] G_EXEC[0] B_EXEC[1] B_EXEC[0] Name Bit Access Active LOG_EN 7 R/W High Logarithmic PWM adjustment generation enable CHIP_EN 6 R/W High Master chip enable. Enables device internal start-up sequence. See Modes of Operation for further information. Setting EN pin low resets the CHIP_EN state to 0. R_EXEC G_EXEC B_EXEC 5:4 3:2 1:0 Description R/W R channel program execution. 00b = Hold: Wait until current command is finished then stop while EXEC mode is hold. PC can be read or written only in this mode. 01b = Step: Execute instruction defined by current R channel PC value, increment PC and change R_EXEC to 00b (Hold) 10b = Run: Start at program counter value defined by current R Channel PC value 11b = Execute instruction defined by current R channel PC value and change R_EXEC to 00b (Hold) R/W G channel program execution 00b = Hold: Wait until current command is finished then stop while EXEC mode is hold. PC can be read or written only in this mode. 01b = Step: Execute instruction defined by current G channel PC value, increment PC and change G_EXEC to 00b (Hold) 10b = Run: Start at program counter value defined by current G Channel PC value 11b = Execute instruction defined by current G channel PC value and change G_EXEC to 00b (Hold) R/W B channel program execution 00b = Hold: Wait until current command is finished then stop while EXEC mode is hold. PC can be read or written only in this mode. 01b = Step: Execute instruction defined by current B channel PC value, increment PC and change B_EXEC to 00b (Hold) 10b = Run: Start at program counter value defined by current B Channel PC value 11b = Execute instruction defined by current B channel PC value and change B_EXEC to 00b (Hold) EXEC registers are synchronized to 32 kHz clock. Delay between consecutive I2C writes to ENABLE register (00H) need to be longer than 488 s (typ). 31 www.national.com LP5521 Operation Mode Register (OP MODE) Address 01H Reset value 00H OP Mode Register 7 6 Name Bit R_MODE 3:2 B_MODE 4 3 2 1 0 R_MODE[0] G_MODE[1] G_MODE[0] B_MODE[1] B_MODE[0] Access 5:4 G_MODE 5 R_MODE[1] 1:0 Active Description R/W R channel operation mode 00b = Disabled 01b = Load program to SRAM, reset R channel PC 10b = Run program defined by R_EXEC 11b = Direct control R/W G channel operation mode 00b = Disabled 01b = Load program to SRAM, reset G channel PC 10b = Run program defined by G_EXEC 11b = Direct control R/W B channel operation mode 00b = Disabled 01b = Load program to SRAM, reset B channel PC 10b = Run program defined by B_EXEC 11b = Direct control MODE registers are synchronized to 32 kHz clock. Delay between consecutive I2C writes to OP_MODE register (01H) need to be longer than 153 s (typ). R channel PWM control (R_PWM) Address 02H Reset value 00H R PWM Register 7 6 5 4 3 2 1 0 R_PWM[7:0] Name Bit Access R_PWM 7:0 R/W Active Description R Channel PWM value during direct control operation mode G Channel PWM Control (G_PWM) Address 03H Reset value 00H G PWM Register 7 6 5 4 3 2 1 G_PWM[7:0] Name Bit Access G_PWM 7:0 R/W www.national.com Active Description G Channel PWM value during direct control operation mode 32 0 LP5521 B Channel PWM Control (B_PWM) Address 04H Reset value 00H B PWM Register 7 6 5 4 3 2 1 0 B_PWM[7:0] Name Bit Access B_PWM 7:0 R/W Active Description B Channel PWM value during direct control operation mode R Channel Current (R_CURRENT) Address 05H Reset Value AFH R CURRENT Register 7 6 5 4 3 2 1 0 R_CURRENT[7:0] Name R_CURRENT Bit 7:0 Access R/W Active Description Current setting 0000 0000b = 0.0 mA 0000 0001b = 0.1 mA 0000 0010b = 0.2 mA 0000 0011b = 0.3 mA 0000 0100b = 0.4 mA 0000 0101b = 0.5 mA 0000 0110b = 0.6 mA ... 1010 1111b = 17.5 mA (default) ... 1111 1011b = 25.1 mA 1111 1100b = 25.2 mA 1111 1101b = 25.3 mA 1111 1110b = 25.4 mA 1111 1111b = 25.5 mA 33 www.national.com LP5521 G Channel Current (G_CURRENT) Address 06H Reset Value AFH G CURRENT Register 7 6 5 4 3 2 1 0 1 0 G_CURRENT[7:0] Name G_CURRENT Bit 7:0 Access Active Description Current setting 0000 0000b = 0.0 mA 0000 0001b = 0.1 mA 0000 0010b = 0.2 mA 0000 0011b = 0.3 mA 0000 0100b = 0.4 mA 0000 0101b = 0.5 mA 0000 0110b = 0.6 mA ... 1010 1111b = 17.5 mA (default) ... 1111 1011b = 25.1 mA 1111 1100b = 25.2 mA 1111 1101b = 25.3 mA 1111 1110b = 25.4 mA 1111 1111b = 25.5 mA R/W B Channel Current (B_CURRENT) Address 07H Reset value AFH B CURRENT Register 7 6 5 4 3 2 B_CURRENT[7:0] Name B_CURRENT www.national.com Bit 7:0 Access R/W Active Description Current setting 0000 0000b = 0.0 mA 0000 0001b = 0.1 mA 0000 0010b = 0.2 mA 0000 0011b = 0.3 mA 0000 0100b = 0.4 mA 0000 0101b = 0.5 mA 0000 0110b = 0.6 mA ... 1010 1111b = 17.5 mA (default) ... 1111 1011b = 25.1 mA 1111 1100b = 25.2 mA 1111 1101b = 25.3 mA 1111 1110b = 25.4 mA 1111 1111b = 25.5 mA 34 LP5521 Configuration Control (CONFIG) Address 08H Reset value 00H CONFIG Register 7 6 5 PWM_HF PWRSAVE_EN 4 3 2 CP_MODE[1:0] R_TO_BATT 1 0 CLK_DET_EN INT_CLK_EN Name Bit Access Active PWM_HF 6 R/W High PWM clock 0 = 256 Hz PWM clock used (CLK_32K) 1 = 558 Hz PWM clock used (internal oscillator) PWRSAVE_EN 5 R/W High Power save mode enable CP_MODE 4:3 R/W R_TO_BATT 2 R/W CLK_DET_EN, INT_CLK_EN 1:0 Description Charge pump operation mode 00b = OFF 01b = Forced to bypass mode (1x) 10b = Forced to 1.5x mode 11b = Automatic mode selection R channel supply connection 0 = R output connected to charge pump 1 = R output connected to battery High LED Controller clock source 00b = External clock source (CLK_32K) 01b = Internal clock 10b = Automatic selection 11b = Internal clock R/W R Channel Program Counter Value (R channel PC) Address 09H Reset value 00H R Channel PC Register 7 6 5 Name Bit Access R_PC 3:0 R/W 4 Active 3 2 1 0 R_PC[3] R_PC[2] R_PC[1] R_PC[0] Description R channel program counter value PC registers are synchronized to 32 kHz clock. Delay between consecutive I2C writes to PC registers needs to be longer than 153 s (typ.). PC register can be read or written only when EXEC mode is 'hold'. 35 www.national.com LP5521 G Channel Program Counter Value (G channel PC) Address 0AH Reset value 00H G Channel PC Register 7 6 5 Name Bit Access G_PC 3:0 R/W 4 Active 3 2 1 0 G_PC[3] G_PC[2] G_PC[1] G_PC[0] Description G channel program counter value PC registers are synchronized to 32 kHz clock. Delay between consecutive I2C writes to PC registers needs to be longer than 153 s (typ.). PC register can be read or written only when EXEC mode is 'hold'. B Channel Program Counter Value (B channel PC) Address 0BH Reset value 00H B Channel PC Register 7 6 5 Name Bit Access B_PC 3:0 R/W 4 Active 3 2 1 0 B_PC[3] B_PC[2] B_PC[1] B_PC[0] Description B channel program counter value PC registers are synchronized to 32 kHz clock. Delay between consecutive I2C writes to PC registers needs to be longer than 153 s (typ.). PC register can be read or written only when EXEC mode is 'hold'. STATUS/INTERRUPT Register Address 0CH Reset value 00H STATUS/INTERRUPT Register 7 6 5 Name Bit Access EXT_CLK USED 3 R 4 Active 3 2 1 0 EXT_CLK USED R_INT G_INT B_INT Description External clock state 0 = Internal 32kHz clock used 1 = External 32kHz clock used R_INT 2 R High Interrupt from R channel G_INT 1 R High Interrupt from G channel B_INT 0 R High Interrupt from B channel Note: Register INT bits will be cleared when read operation to Status/Interrupt register occurs. INT output pin (active low) will go high after read operation. www.national.com 36 LP5521 RESET Register Address 0DH Reset value 00H RESET Register 7 6 5 4 3 2 1 0 RESET RESET RESET RESET RESET RESET RESET RESET Name Bit Access RESET 7:0 W Active Description Reset all register values when FFH is written. No acknowledge from LP5521 after write. GPO Register Address 0EH Reset value 00H GPO Register 7 6 5 4 3 2 1 0 INT_AS_GPO GPO INT Name Bit Access Active INT_AS_GPO 2 R/W High Description Enable INT pin GPO function GPO 1 R/W High GPO pin state: 0 = LOW 1 = HIGH INT 0 R/W High INT pin state (when INT_AS_GPO=1): 0 = LOW 1 = HIGH PROGRAM MEMORY Address 10H - 6FH Reset values 00H Please see chapter LED Controller Programming Commands for further information. Command 15 14 Ramp Wait 0 Prescale 13 12 11 10 Step time Set PWM 0 1 0 Go toStart 0 0 Branch 1 0 1 End 1 1 0 Trigger 1 1 1 9 8 6 5 4 Sign 3 2 1 0 0 0 0 Increment PWM Value 0 0 Loop Count Int 7 0 0 X Reset 0 0 Step number X Wait for trigger on channels 5-0 37 Send trigger on channels 5-0 X www.national.com LP5521 Physical Dimensions inches (millimeters) unless otherwise noted The dimension for X1 ,X2 and X3 are as given: X1=1.717 mm 0.03 mm X2=2.066 mm 0.03 mm X3=0.600 mm 0.075 mm TMD20ECA: Thin microSMD-20, Small Bump YQA24A: Bumped LLP-24 www.national.com 38 LP5521 Notes 39 www.national.com LP5521 Programmable Three Channel LED Driver Notes For more National Semiconductor product information and proven design tools, visit the following Web sites at: Products Design Support Amplifiers www.national.com/amplifiers WEBENCH www.national.com/webench Audio www.national.com/audio Analog University www.national.com/AU Clock Conditioners www.national.com/timing App Notes www.national.com/appnotes Data Converters www.national.com/adc Distributors www.national.com/contacts Displays www.national.com/displays Green Compliance www.national.com/quality/green Ethernet www.national.com/ethernet Packaging www.national.com/packaging Interface www.national.com/interface Quality and Reliability www.national.com/quality LVDS www.national.com/lvds Reference Designs www.national.com/refdesigns Power Management www.national.com/power Feedback www.national.com/feedback Switching Regulators www.national.com/switchers LDOs www.national.com/ldo LED Lighting www.national.com/led PowerWise www.national.com/powerwise Serial Digital Interface (SDI) www.national.com/sdi Temperature Sensors www.national.com/tempsensors Wireless (PLL/VCO) www.national.com/wireless THE CONTENTS OF THIS DOCUMENT ARE PROVIDED IN CONNECTION WITH NATIONAL SEMICONDUCTOR CORPORATION ("NATIONAL") PRODUCTS. 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