CY7C1010DV33
2-Mbit (256 K × 8) Static RAM
Cypress Semiconductor Corporation • 198 Champion Court • San Jose,CA 95134-1709 • 408-943-2600
Document Number: 001-00062 Rev. *D Revised June 7, 2011
2-Mbit (256 K × 8) Static RAM
Features
■Pin and function compatible with CY7C1010CV33
■High speed
❐tAA = 10 ns
■Low active power
❐ICC = 90 mA at 10 ns
■Low CMOS standby power
❐ISB2 = 10 mA
■2.0 V data retention
■Automatic power down when deselected
■TTL-compatible inputs and outputs
■Easy memory expansion with CE and OE features
■Available in Pb-free 36-pin SOJ and 44-pin TSOP II packages
Functional Description
The CY7C1010DV33 is a high performance CMOS Static RAM
organized as 256 K words by 8 bits. Easy memory expansion is
provided by an active LOW Chip Enable (CE), an active LOW
Output Enable (OE), and three-state drivers. Writing to the
device is accomplished by taking Chip Enable (CE) and Write
Enable (WE) inputs LOW. Data on the eight I/O pins (I/O0
through I/O7) is then written into the location specified on the
address pins (A0 through A17).
Reading from the device is accomplished by taking Chip Enable
(CE) and Output Enable (OE) LOW while forcing Write Enable
(WE) HIGH. Under these conditions, the contents of the memory
location specified by the address pins will appear on the I/O pins.
The eight input and output pins (I/O0 through I/O7) are placed in
a high impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), or during a Write
operation (CE LOW, and WE LOW).
The CY7C1010DV33 is available in 36-pin SOJ and 44-pin
TSOP II packages with center power and ground (revolutionary)
pinout.
A0
IO0
IO7
IO1
IO2
IO3
IO4
IO5
IO6
A1
A2
A3
A4
A5
A6
A7
A8
A9
SENSE AMPS
POWER
DOWN
CE
WE
OE
A12
A13
A14
A15
A16
ROW DECODER
COLUMN DECODER
256K x 8
ARRAY
INPUT BUFFER
A10
A17
A11
Logic Block Diagram
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CY7C1010DV33
Document Number: 001-00062 Rev. *D Page 2 of 15
Contents
Selection Guide .................................................................3
Pin Configuration ..............................................................3
Maximum Ratings .............................................................4
Operating Range ...............................................................4
Electrical Characteristics .................................................4
Capacitance .......................................................................4
Thermal Resistance ..........................................................4
AC Test Loads and Waveforms .......................................5
AC Switching Characteristics ..........................................6
Data Retention Characteristics ........................................7
Data Retention Waveform ................................................7
Switching Waveforms .......................................................7
Truth Table ........................................................................9
Ordering Information ......................................................10
Ordering Code Definitions .........................................10
Package Diagrams ..........................................................11
Acronyms ........................................................................13
Document Conventions .................................................13
Units of Measure .......................................................13
Document History Page .................................................14
Sales, Solutions, and Legal Information ......................15
Worldwide Sales and Design Support .......................15
Products ....................................................................15
PSoC Solutions .........................................................15
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CY7C1010DV33
Document Number: 001-00062 Rev. *D Page 3 of 15
Selection Guide
Description -10 Unit
Maximum Access Time 10 ns
Maximum Operating Current 90 mA
Maximum CMOS Standby Current 10 mA
Pin Configuration
Figure 1. 36-pin SOJ [1] Figure 2. 44-pin TSOP II [1]
1
2
3
4
5
6
7
8
9
11
14
31
32
36
35
34
33
12
13
16
15
29
30
18
17 20
19
27
28
25
26
22
21
23
24
NC
A
4
A
3
A
2
A
14
A
15
A
12
NC
NC
A
13
A
5
A
6
A
7
A
1
A
16
A
0
CE
IO
0
IO
1
IO
2
IO
3
WE
A
17
A
10
A
9
IO
4
IO
5
IO
6
IO
7
OE
A
8
V
CC
V
CC
GND
GND
A
11
10
1
2
3
4
5
6
7
8
9
11
14 31
32
36
35
34
33
37
40
39
38
12
13
41
44
43
42
16
15
29
30
NC
18
17
20
19
27
28
25
26
22
21
23
24
NC
NC
NC
NC
A
4
A
3
A
2
A
14
A
15
A
12
NC
NC
NC
NC
A
13
NC NC
A
5
A
6
A
7
A
1
A
16
A
0
CE
IO
0
IO
1
IO
2
IO
3
WE
A
17
A
10
A
9
IO
4
IO
5
IO
6
IO
7
OE
A
8
V
CC
V
CC
V
SS
V
SS
A
11
10
Note
1. NC pins are not connected on the die.
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CY7C1010DV33
Document Number: 001-00062 Rev. *D Page 4 of 15
Maximum Ratings
Exceeding the maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Storage Temperature ............................... –65 C to +150 C
Ambient Temperature with
Power Applied ......................................... –55 C to +125 C
Supply Voltage on
VCC Relative to GND [2] ...............................–0.5 V to +4.6 V
DC Voltage Applied to Outputs
in High Z State [2] ................................–0.3 V to VCC + 0.3 V
DC Input Voltage [2] ............................ –0.3 V to VCC + 0.3 V
Current into Outputs (LOW) ........................................ 20 mA
Static Discharge Voltage ........................................ > 2001 V
(MIL-STD-883, Method 3015)
Latch Up Current ...................................................> 200 mA
Operating Range
Range Ambient
Temperature VCC
Industrial –40C to +85C3.3V 0.3V
Electrical Characteristics
Over the Operating Range
Parameter Description Test Conditions -10
UnitMin Max
VOH Output HIGH Voltage VCC = Min; IOH = –4.0 mA 2.4 – V
VOL Output LOW Voltage VCC = Min; IOL = 8.0 mA – 0.4 V
VIH Input HIGH Voltage 2.0 VCC + 0.3 V
VIL Input LOW Voltage[2] –0.3 0.8 V
IIX Input Leakage Current GND < VI < VCC –1 +1 A
IOZ Output Leakage Current GND < VOUT < VCC, Output Disabled –1 +1 A
ICC VCC Operating Supply Current VCC = Max, f = fMAX = 1/tRC 100 MHz – 90 mA
83 MHz – 80
66 MHz – 70
40 MHz – 60
ISB1 Automatic CE Power-down
Current —TTL Inputs
Max VCC, CE > VIH; VIN > VIH or
VIN < VIL, f = fMAX
–20mA
ISB2 Automatic CE Power-down
Current —CMOS Inputs
Max VCC, CE > VCC – 0.3 V,
VIN > VCC – 0.3 V, or VIN < 0.3 V, f = 0
–10mA
Capacitance
Parameter [3] Description Test Conditions 36-pin SOJ 44-pin TSOP II Unit
CIN Input Capacitance TA = 25C, f = 1 MHz, VCC = 3.3V 8 8 pF
COUT IO Capacitance 8 8 pF
Thermal Resistance
Parameter [3] Description Test Conditions 36-pin SOJ 44-pin TSOP II Unit
JA Thermal Resistance
(Junction to Ambient)
Still air, soldered on a 3 × 4.5 inch, four
layer printed circuit board
59.17 50.66 C/W
JC Thermal Resistance
(Junction to Case)
32.63 17.77 C/W
Notes
2. VIL (min.) = –2.0V and VIH (max.) = VCC + 2.0V for pulse durations of less than 20 ns.
3. Tested initially and after any design or process changes that may affect these parameters.
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CY7C1010DV33
Document Number: 001-00062 Rev. *D Page 5 of 15
AC Test Loads and Waveforms
Figure 3. AC Test Loads and Waveforms[4]
90%
10%
3.0 V
GND
90%
10%
ALL INPUT PULSES
* CAPACITIVE LOAD CONSISTS
OF ALL COMPONENTS OF THE
TEST ENVIRONMENT
Rise Time: 1 V/ns Fall Time: 1 V/ns
30 pF*
OUTPUT
Z = 50
50
1.5 V
(b)
(a)
3.3 V
OUTPUT
5 pF
(c)
R 317
R2
351
High-Z characteristics:
Note
4. AC characteristics (except High Z) are tested using the load conditions shown in Figure 3 (a). High-Z characteristics are tested for all speeds using the test load shown
in Figure 3 (c).
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CY7C1010DV33
Document Number: 001-00062 Rev. *D Page 6 of 15
AC Switching Characteristics
Over the Operating Range
Parameter [5] Description
-10
UnitMin Max
Read Cycle
tpower[6] VCC(typical) to the first access 100 – s
tRC Read Cycle Time 10 – ns
tAA Address to Data Valid – 10 ns
tOHA Data Hold from Address Change 3 – ns
tACE CE LOW to Data Valid – 10 ns
tDOE OE LOW to Data Valid – 5 ns
tLZOE OE LOW to Low Z [7] 0–ns
tHZOE OE HIGH to High Z[7, 8] –5ns
tLZCE CE LOW to Low Z[7] 3–ns
tHZCE CE HIGH to High Z[7, 8] –5ns
tPU CE LOW to Power-up 0 – ns
tPD CE HIGH to Power-down – 10 ns
Write Cycle[9, 10]
tWC Write Cycle Time 10 – ns
tSCE CE LOW to Write End 7 – ns
tAW Address Set-up to Write End 7 – ns
tHA Address Hold from Write End 0 – ns
tSA Address Set-up to Write Start 0 – ns
tPWE WE Pulse Width 7–ns
tSD Data Set-up to Write End 5 – ns
tHD Data Hold from Write End 0 – ns
tLZWE WE HIGH to Low Z[7] 3–ns
tHZWE WE LOW to High Z[7, 8] –5ns
Notes
5. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5 V, input pulse levels of 0 to 3.0 V.
6. tPOWER gives the minimum amount of time that the power supply should be at stable, typical VCC values until the first memory access can be performed.
7. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device.
8. tHZOE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in part (d) of Figure 3 on page 5. Transition is measured when the outputs enter a high
impedance state.
9. The internal Write time of the memory is defined by the overlap of CE LOW, and WE LOW. CE and WE must be LOW to initiate a Write, and the transition of either of
these signals can terminate the Write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the Write.
10. The minimum Write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD.
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Document Number: 001-00062 Rev. *D Page 7 of 15
Data Retention Characteristics
Over the Operating Range
Parameter [11] Description Conditions Min Max Unit
VDR VCC for Data Retention 2 – V
ICCDR Data Retention Current VCC = VDR = 2.0 V, CE > VCC – 0.3 V,
VIN > VCC – 0.3 V or VIN < 0.3 V
–10mA
tCDR [12] Chip Deselect to Data Retention Time 0 – ns
tR [13] Operation Recovery Time tRC –ns
Data Retention Waveform
3.0V3.0V
tCDR
VDR > 2V
DATA RETENTION MODE
tR
CE
VCC
Switching Waveforms
Figure 4. Read Cycle No. 1 [14, 15]
PREVIOUS DATA VALID DATA VALID
RC
tAA
tOHA
tRC
ADDRESS
DATA OUT
Notes
11. No inputs may exceed VCC + 0.3 V.
12. Tested initially and after any design or process changes that may affect these parameters.
13. Full device operation requires linear VCC ramp from VDR to VCC(min.) > 50 s or stable at VCC(min.) > 50 s.
14. The device is continuously selected. OE, CE = VIL.
15. WE is HIGH for read cycle.
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CY7C1010DV33
Document Number: 001-00062 Rev. *D Page 8 of 15
Figure 5. Read Cycle No. 2 (OE Controlled) [16, 17]
Figure 6. Write Cycle No. 1 (WE Controlled, OE HIGH During Write) [18, 19]
Switching Waveforms (continued)
50%
50%
DATA VALID
tRC
tACE
tDOE
tLZOE
tLZCE
tPU
HIGH IMPEDANCE
tHZOE
tHZCE
tPD
HIGH
OE
CE
ICC
ISB
IMPEDANCE
ADDRESS
DATA OUT
VCC
SUPPLY
CURRENT
tHD
tSD
tPWE
tSA
tHA
tAW
tSCE
tWC
tHZOE
DATAIN VALID
CE
ADDRESS
WE
DATA I/O
OE
NOTE 20
Notes
16. WE is HIGH for read cycle.
17. Address valid before or similar to CE transition LOW.
18. Data IO is high impedance if OE = VIH.
19. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high impedance state.
20. During this period, the I/Os are in output state and input signals should not be applied.
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CY7C1010DV33
Document Number: 001-00062 Rev. *D Page 9 of 15
Figure 7. Write Cycle No. 2 (WE Controlled, OE LOW) [21]
Switching Waveforms (continued)
DATA VALID
tHD
tSD
tLZWE
tPWE
tSA
tHA
tAW
tSCE
tWC
tHZWE
CE
ADDRESS
WE
DATA I/O NOTE 22
Truth Table
CE OE WE IO0–IO7IO8–IO15 Mode Power
H X X High Z High Z Power Down Standby (ISB)
L L H Data Out Data Out Read All Bits Active (ICC)
L X L Data In Data In Write All Bits Active (ICC)
L H H High Z High Z Selected, Outputs Disabled Active (ICC)
Notes
21. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high impedance state.
22. During this period, the I/Os are in output state and input signals should not be applied.
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CY7C1010DV33
Document Number: 001-00062 Rev. *D Page 10 of 15
Ordering Information
Speed
(ns) Ordering Code Package
Diagram Package Type Operating
Range
10 CY7C1010DV33-10VXI 51-85090 36-pin (400-Mil) Molded SOJ (Pb-free) Industrial
CY7C1010DV33-10ZSXI 51-85087 44-pin TSOP II (Pb-free)
Ordering Code Definitions
Temperature Range:
I = Industrial
Package Type: XXX = VX or ZSX
VX = 36-pin (400-Mil) Molded SOJ (Pb-free)
ZSX = 44-pin TSOP II (Pb-free)
Speed: 10 ns
V33 = Voltage range (3 V to 3.6 V)
D = C9, 90 nm Technology
0 = Data width × 8-bits
01 = 2-Mbit density
1 = Fast Asynchronous SRAM family
Technology Code: C = CMOS
7 = SRAM
Company ID: CY = Cypress
CCY 1 V33 - 10 XXX701 0 D I
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Document Number: 001-00062 Rev. *D Page 11 of 15
Package Diagrams
Figure 8. 36-pin (400-Mil) SOJ V36.4 (Molded), 51-85090
51-85090 *E
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Document Number: 001-00062 Rev. *D Page 12 of 15
Figure 9. 44-pin TSOP Z44-II, 51-85087
Package Diagrams (continued)
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Document Number: 001-00062 Rev. *D Page 13 of 15
Acronyms Document Conventions
Units of Measure
Acronym Description
CE chip enable
CMOS complementary metal oxide semiconductor
I/O input/output
OE output enable
SOJ small outline J-lead
SRAM static random access memory
TSOP thin small outline package
TTL transistor-transistor logic
WE write enable
Symbol Unit of Measure
°C degree Celsius
MHz Mega Hertz
Amicro Amperes
smicro seconds
mA milli Amperes
mm milli meter
mW milli Watts
ns nano seconds
ohms
%percent
pF pico Farad
VVolts
WWatts
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Document Number: 001-00062 Rev. *D Page 14 of 15
Document History Page
Document Title: CY7C1010DV33, 2-Mbit (256 K × 8) Static RAM
Document Number: 001-00062
REV. ECN NO. Submission
Date
Orig. of
Change Description of Change
** 342195 See ECN PCI New Data sheet
*A 459073 See ECN NXR Converted Preliminary to Final.
Removed Commercial Operating Range from product offering.
Removed -8 ns and -12 speed bin
Removed the Pin definitions table.
Modified Maximum Ratings for DC input voltage from -0.5V to -0.3V and VCC +
0.5V to VCC + 0.3V
Changed ICC max from 65 mA to 90 mA
Changed the description of IIX from “Input Load Current” to “Input Leakage Current”
Updated the Thermal Resistance table.
Updated footnote #7 on High-Z parameter measurement
Added footnote #12
Updated the Ordering Information and replaced Package Name column with
Package Diagram in the Ordering Information table.
*B 2602853 11/07/08 VKN/PYRS Added 36-pin SOJ package and its related information
*C 3059211 10/14/2010 PRAS Added Ordering Code Definitions.
Updated Package Diagrams.
*D 3272897 06/07/2011 AJU Updated Functional Description (Removed “Refer to the Cypress application note
AN1064, SRAM System Guidelines for best practice recommendations.”).
Added Acronyms and Units of Measure.
Updated in new template.
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Document Number: 001-00062 Rev. *D Revised June 7, 2011 Page 15 of 15
All products and company names mentioned in this document may be the trademarks of their respective holders.
CY7C1010DV33
© Cypress Semiconductor Corporation, 2005-2011. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
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