SmartRF a CC1000 CC1000 Single Chip Very Low Power RF Transceiver Applications * Very low power UHF wireless data transmitters and receivers * 315 / 433 / 868 and 915 MHz ISM/SRD band systems * * * * * * RKE - Two-way Remote Keyless Entry Home automation Wireless alarm and security systems AMR - Automatic Meter Reading Low power telemetry Toys Product Description CC1000 is a true single-chip UHF transceiver designed for very low power and very low voltage wireless applications. The circuit is mainly intended for the ISM (Industrial, Scientific and Medical) and SRD (Short Range Device) frequency bands at 315, 433, 868 and 915 MHz, but can easily be programmed for operation at other frequencies in the 300-1000 MHz range. CC1000 is based on Chipcon's SmartRFa technology in 0.35 m CMOS. The main operating parameters of CC1000 can be programmed via an easy-tointerface serial bus, thus making CC1000 a very flexible and easy to use transceiver. In a typical system CC1000 will be used together with a microcontroller and a few external passive components. Features * * * * * * * * * * * * True single chip UHF RF transceiver Very low current consumption Frequency range 300 - 1000 MHz Integrated bit synchroniser High sensitivity (typical -109 dBm) Programmable output power -20 to 10 dBm Small size (TSSOP-28 package) Low supply voltage (2.3 V to 3.6 V) Very few external components required No external RF switch / IF filter required RSSI output Single port antenna connection * FSK data rate up to 19.2 kBaud * Complies with EN 300 220 and FCC FCR47 part 15 * FSK modulation spectrum shaping * Programmable frequency in 250 Hz steps makes crystal temperature drift compensation possible without TCXO * Suitable for frequency hopping protocols * Development kit available * Easy-to-use software for generating the CC1000 configuration data This document contains information on a pre-production product. Specifications and information herein are subject to change without notice. Chipcon AS SmartRFa CC1000 PRELIMINARY Datasheet (rev. 1.0) 2001-09-05 Page 1 of 39 SmartRF a CC1000 Pin Assignment Pin no. 1 2 3 4 5 6 7 8 9 10 11 12 Pin name AVDD AGND RF_IN RF_OUT AVDD AGND AGND AGND AVDD L1 L2 CHP_OUT (LOCK) Pin type Power (A) Ground (A) RF Input RF output Power (A) Ground (A) Ground (A) Ground (A) Power (A) Analog input Analog input Analog output 13 14 15 16 17 18 19 20 21 22 23 R_BIAS AGND AVDD AGND XOSC_Q2 XOSC_Q1 AGND DGND DVDD DGND DIO 24 25 26 DCLK PCLK PDATA 27 28 PALE RSSI/IF Analog output Ground (A) Power (A) Ground (A) Analog output Analog input Ground (A) Ground (D) Power (D) Ground (D) Digital input/output Digital output Digital input Digital input/output Digital input Analog output Description Power supply (3 V) for analog modules (mixer and IF) Ground connection (0 V) for analog modules (mixer and IF) RF signal input from antenna RF signal output to antenna Power supply (3 V) for analog modules (LNA and PA) Ground connection (0 V) for analog modules (LNA and PA) Ground connection (0 V) for analog modules (PA) Ground connection (0 V) for analog modules (VCO and prescaler) Power supply (3 V) for analog modules (VCO and prescaler) Connection no 1 for external VCO tank inductor Connection no 2 for external VCO tank inductor Charge pump current output The pin can also be used as PLL Lock indicator. Output is high when PLL is in lock. Connection for external precision bias resistor (82 k, 1%) Ground connection (0 V) for analog modules (backplane) Power supply (3 V) for analog modules (general) Ground connection (0 V) for analog modules (general) Crystal, pin 2 Crystal, pin 1, or external clock input Ground connection (0 V) for analog modules (guard) Ground connection (0 V) for digital modules (substrate) Power supply (3 V) for digital modules Ground connection (0 V) for digital modules Data input/output. Data input in transmit mode. Data output in receive mode Data clock for data in both receive and transmit mode Programming clock for 3-wire bus Programming data for 3-wire bus. Programming data input for write operation, programming data output for read operation Programming address latch enable for 3-wire bus The pin can be used as RSSI or 10.7 MHz IF output to optional external IF and demodulator. If not used, the pin should be left open (not connected). A=Analog, D=Digital (Top View) Chipcon AS SmartRFa CC1000 PRELIMINARY Datasheet (rev. 1.0) 2001-09-05 Page 2 of 39 SmartRF a CC1000 Absolute Maximum Ratings Parameter Min. Max. Units -0.3 -0.3 5.0 VDD+0.3, max 5.0 10 150 85 V V dBm C C 260 C Supply voltage, VDD Voltage on any pin Input RF level Storage temperature range Operating ambient temperature range Lead temperature -50 -40 Under no circumstances the absolute maximum ratings given above should be violated. Stress exceeding one or more of Condition T = 10 s the limiting values may cause permanent damage to the device. Caution! ESD sensitive device. Precaution should be used when handling the device in order to prevent permanent damage. Electrical Specifications Tc = 25C, VDD = 3.0 V if nothing else stated Parameter Min. Typ. Max. Unit Condition / Note 300 1000 MHz Programmable in steps of 250 Hz 0.6 19.2 kBaud NRZ or Manchester encoding. See page 13. The frequency corresponding to the digital "0" is denoted f0, while f1 corresponds to a digital "1". The frequency separation is f1-f0. The RF carrier frequency, fc, is then given by fc=(f0+f1)/2. (The frequency deviation is given by fd=+/-(f1-f0)/2 ) The frequency separation is programmable in 250 Hz steps. Overall RF Frequency Range Transmit Section Transmit data rate Binary FSK frequency separation Output power 433/868 MHz RF output impedance 433/868 MHz Harmonics Chipcon AS 1 10 65 kHz -20 0 10/5 dBm Delivered to 50 load. The output power is programmable. 140 / 80 Transmit mode. For matching details see "Input/ output matching" p.21. -20 dBc An external LC or SAW filter should be used to reduce harmonics emission to comply with SRD requirements. See p.26. SmartRFa CC1000 PRELIMINARY Datasheet (rev. 1.0) 2001-09-05 Page 3 of 39 SmartRF a CC1000 Parameter Min. Typ. Max. Unit Condition / Note -109/ -106 -107/ -105 dBm 2.4 kBaud, Manchester coded data, 64 kHz frequency separation, BER = 10-3 30 kHz 10/11 dB Receive Section Receiver Sensitivity 433/868 MHz (9.5/12 mA) 433/868 MHz (7.7/9.9 mA) System noise bandwidth Cascaded noise figure 433/868 MHz Saturation dBm 10 2.4 kBaud, Manchester coded data dBm 2.4 kBaud, Manchester coded data, BER = 10-3 Input IP3 -18 dBm From LNA to IF output Blocking 40 dBc At +/- 1 MHz LO leakage -57 dBm Input impedance 88-j26 70-j26 52-j7 52-j4 Turn on time 11 Receive mode, series equivalent at 315 MHz At 433 MHz At 868 MHz. At 915 MHz For matching details see "Input/ output matching" p. 21. 128 Baud The turn-on time is determined by the demodulator settling time, which is programmable. See p. 16 10.7 kHz MHz Internal IF filter External IF filter IF Section Intermediate frequency (IF) 150 IF bandwidth 175 RSSI dynamic range -105 kHz -50 dBm RSSI accuracy 6 dB RSSI linearity 2 dB See p.22 for details Frequency Synthesiser Section Crystal Oscillator Frequency Crystal frequency accuracy requirement Chipcon AS 3 16 50 MHz Crystal frequency can be 3-4, 6-8 or 9-16 MHz. Recommended frequencies are 3.6864, 7.3728, 11.0592 and 14.7456. See page 24 for details. ppm The crystal frequency accuracy and drift (ageing and temperature dependency) will determine the frequency accuracy of the transmitted signal. SmartRFa CC1000 PRELIMINARY Datasheet (rev. 1.0) 2001-09-05 Page 4 of 39 SmartRF a CC1000 Parameter Min. Crystal operation Crystal load capacitance Typ. Max. Unit Parallel 12 12 12 22 16 16 Condition / Note C171 and C181 are loading capacitors, see page 24 30 30 16 pF pF pF 3-8 MHz, 22 pF recommended 6-8 MHz, 16 pF recommended 9-16 MHz, 16 pF recommended 3.6864 MHz, 16 pF load 7.3728 MHz, 16 pF load 16 MHz, 16 pF load Crystal oscillator start-up time 5 1.5 2 ms ms ms Output signal phase noise -85 dBc/Hz PLL lock time (RX / TX turn time) 150 s PLL turn-on time, crystal oscillator on in power down mode 250 s At 100 kHz offset from carrier Crystal oscillator running Digital Inputs/Outputs Logic "0" input voltage 0 0.7*VDD 0.3*VD D VDD Logic "1" input voltage V V Logic "0" output voltage 0 0.4 V Logic "1" output voltage 2.5 VDD V Logic "0" input current NA -1 A Output current -2.5 mA, 3.0 V supply voltage Output current 2.5 mA, 3.0 V supply voltage Input signal equals GND Logic "1" input current NA 1 A Input signal equals VDD V Recommended operation voltage V Operating limits Power Supply Supply voltage 3.0 2.3 3.6 Current Consumption, receive mode 433/868 MHz 7.7/9.9 mA Current Consumption, average in receive mode using polling 433/868 MHz 77/99 A P=0.01mW (-20dBm) 5.3/8.6 mA P=0.3mW (-5dBm) 8.0/13.9 mA P=1mW (0dBm) 11.6/16.4 mA P=3mW (5dBm) 14.6/25.2 mA P=10mW (10dBm) 27.8/NA mA 30 A Current is programmable and can be increased for improved sensitivity 1:100 receive to power down ratio Current Consumption, transmit mode 433/868 MHz: Current Consumption, Power Down mode 0.2 Chipcon AS 1 A The ouput power is delivered to a 50 load Oscillator core on, 3.6864 MHz, 16 pF load Oscillator core off SmartRFa CC1000 PRELIMINARY Datasheet (rev. 1.0) 2001-09-05 Page 5 of 39 SmartRF a CC1000 Circuit Description Figure 1. Simplified block diagram of the CC1000. A simplified block diagram of CC1000 is shown in Figure 1. Only signal pins are shown. In receive mode CC1000 is configured as a traditional superheterodyne receiver. The RF input signal is amplified by the lownoise amplifier (LNA) and converted down to the intermediate frequency (IF) by the mixer (MIXER). In the intermediate frequency stage (IF STAGE) this downconverted signal is amplified and filtered before being fed to the demodulator (DEMOD). As an option a RSSI signal, or the IF signal after the mixer is available at the RSSI/IF pin. After demodulation CC1000 outputs the digital demodulated data on the pin DIO. Synchronisation is done on-chip providing data clock at DCLK. Chipcon AS In transmit mode the voltage controlled oscillator (VCO) output signal is fed directly to the power amplifier (PA). The RF output is frequency shift keyed (FSK) by the digital bit stream fed to the pin DIO. The internal T/R switch circuitry makes the antenna interface and matching very easy. The frequency synthesiser generates the local oscillator signal which is fed to the MIXER in receive mode and to the PA in transmit mode. The frequency synthesiser consists of a crystal oscillator (XOSC), phase detector (PD), charge pump (CHARGE PUMP), VCO, and frequency dividers (/R and /N). An external crystal must be connected to XOSC, and only an external inductor is required for the VCO. The 3-wire digital serial interface (CONTROL) is used for configuration. SmartRFa CC1000 PRELIMINARY Datasheet (rev. 1.0) 2001-09-05 Page 6 of 39 SmartRF a CC1000 Application Circuit Very few external components are required for the operation of CC1000. A typical application circuit is shown in Figure 2. Component values are shown in Table 1. Input / output matching C31/L32 is the input match for the receiver, and L32 is also a DC choke for biasing. C41, L41 and C42 are used to match the transmitter to 50 Ohm. An internal T/R switch circuit makes it possible to connect the input and output together and match the CC1000 to 50 in both RX and TX mode. See "Input/output matching" p.21 for details. VCO inductor The VCO is completely integrated except for the inductor L101. Component values for the matching network and VCO inductor are easily calculated using the SmartRF Studio software. Additional filtering Additional external components (e.g. RF LC or SAW-filter) may be used in order to improve the performance in specific applications. See also "Optional LC filter" p.26 for further information. Voltage supply decoupling C10-C16 are voltage supply de-coupling capacitors. These capacitors should be placed as close as possible to the voltage supply pins of CC1000. Figure 2. Typical CC1000 application circuit Chipcon AS SmartRFa CC1000 PRELIMINARY Datasheet (rev. 1.0) 2001-09-05 Page 7 of 39 SmartRF a CC1000 Item C10 C11 C12 C13 C14 C15 C16 C31 C41 C42 C131 C141 C151 L32 315 MHz 33 nF, 10%, X7R, 0805 1 nF, 10%, X7R, 0603 1 nF, 10%, X7R, 0603 220 pF, 10%, C0G, 0603 220 pF, 10%, C0G, 0603 1 nF, 10%, X7R, 0603 33 nF, 10%, X7R, 0805 TBD pF, 5%, C0G, 0603 TBD pF, 5%, C0G, 0603 TBD pF, 5%, C0G, 0603 4.7 pF, 10%, C0G, 0603 15 pF, 5%, C0G, 0603 15 pF, 5%, C0G, 0603 TBD nH, 10%, 0805 L41 TBD nH, 10%, 0805 L101 TBD nH, 5%, 0805 R131 XTAL 82 k, 1%, 0603 11.0592 MHz crystal, 16 pF load 433 MHz 33 nF, 10%, X7R, 0805 1 nF, 10%, X7R, 0603 1 nF, 10%, X7R, 0603 220 pF, 10%, C0G, 0603 220 pF, 10%, C0G, 0603 1 nF, 10%, X7R, 0603 33 nF, 10%, X7R, 0805 15 pF, 5%, C0G, 0603 8.2 pF, 5%, C0G, 0603 5.6 pF, 5%, C0G, 0603 4.7 pF, 10%, C0G, 0603 15 pF, 5%, C0G, 0603 15 pF, 5%, C0G, 0603 68 nH, 10%, 0805 868 MHz 33 nF, 10%, X7R, 0805 1 nF, 10%, X7R, 0603 1 nF, 10%, X7R, 0603 220 pF, 10%, C0G, 0603 220 pF, 10%, C0G, 0603 1 nF, 10%, X7R, 0603 33 nF, 10%, X7R, 0805 10 pF, 5%, C0G, 0603 Not used 4.7 pF, 5%, C0G, 0603 4.7 pF, 10%, C0G, 0603 15 pF, 5%, C0G, 0603 15 pF, 5%, C0G, 0603 120 nH, 10%, 0805 (Coilcraft 0805CS-680XKBC) (Coilcraft 0805CS-121XKBC) 6.2 nH, 10%, 0805 2.5 nH, 10%, 0805 (Coilcraft 0805HQ-6N2XKBC) (Coilcraft 0805HQ-2N5XKBC) 27 nH, 5%, 0805 (Koa KL732ATE27NJ) 82 k, 1%, 0603 11.0592 MHz crystal, 16 pF load 4.7 nH, 5%, 0805 (Koa KL732ATE4N7J) 82 k, 1%, 0603 11.0592 MHz crystal, 16 pF load 915 MHz 33 nF, 10%, X7R, 0805 1 nF, 10%, X7R, 0603 1 nF, 10%, X7R, 0603 220 pF, 10%, C0G, 0603 220 pF, 10%, C0G, 0603 1 nF, 10%, X7R, 0603 33 nF, 10%, X7R, 0805 TBD pF, 5%, C0G, 0603 Not used TBD pF, 5%, C0G, 0603 4.7 pF, 10%, C0G, 0603 15 pF, 5%, C0G, 0603 15 pF, 5%, C0G, 0603 TBD nH, 10%, 0805 TBD nH, 10%, 0805 TBD nH, 5%, 0805 82 k, 1%, 0603 11.0592 MHz crystal, 16 pF load Note: Items shaded are different for different frequencies Table 1. Bill of materials for the application circuit Chipcon AS SmartRFa CC1000 PRELIMINARY Datasheet (rev. 1.0) 2001-09-05 Page 8 of 39 SmartRF a CC1000 Configuration Overview CC1000 can be configured to achieve the best performance for different applications. Through the programmable configuration registers the following key parameters can be programmed: * Receive / transmit mode. * RF output power. * Frequency synthesiser key parameters: RF output frequency, FSK frequency separation (deviation), crystal oscillator reference frequency. * Power-down / power-up mode. * Crystal oscillator power-up / power down. * Data rate and data format (NRZ, Manchester coded or UART interface). * Synthesiser lock indicator mode. * Optional RSSI or external IF * Modulation spectrum shaping for narrow band systems Configuration Software Chipcon provides users of CC1000 with a software program, SmartRF Studio (Windows interface) that generates all necessary CC1000 configuration data based on the user's selections of various parameters. These hexadecimal numbers will then be the necessary input to the microcontroller for the configuration of CC1000. In addition the program will provide the user with the component values needed for the input/output matching circuit and the VCO inductor. Figure 3 shows the user interface of the CC1000 configuration software. Figure 3. SmartRF Studio user interface Chipcon AS SmartRFa CC1000 PRELIMINARY Datasheet (rev. 1.0) 2001-09-05 Page 9 of 39 SmartRF a CC1000 3-wire Serial Configuration Interface CC1000 is configured via a simple 3-wire interface (PDATA, PCLK and PALE). There are 36 8-bit configuration registers, each addressed by a 7-bit address. A Read/Write bit initiates a read or write operation. A full configuration of CC1000 requires sending 29 data frames of 16 bits each (7 address bits, R/W bit and 8 data bits). With a clock rate of 10 MHz the time needed for a full configuration will be less than 60 s. Setting the device in power down mode requires sending one frame only and will take less than 2 s. All registers are also readable. In each write-cycle 16 bits are sent on the PDATA-line. The seven most significant bits of each data frame (A6:0) are the address-bits. A6 is the MSB (Most Significant Bit) of the address and is sent as the first bit. The next bit is the R/W bit (high for write, low for read). During address and R/W bit transfer the PALE (Program Address Latch Enable) must be kept low. The 8 data-bits are then transferred (D7:0). See Figure 4. The timing for the programming is also shown in Figure 4 with reference to Table 2. The clocking of the data on PDATA is done on the negative edge of PCLK. When the last bit, D0, of the 8 data-bits has been loaded, the data word is loaded in the internal configuration register. The configuration data will be valid after a programmed power-down mode, but not when the power-supply is turned off. The registers can be programmed in any order. The configuration registers can also be read by the microcontroller via the same configuration interface. The seven address bits are sent first, then the R/W bit set low to initiate the data read-back. CC1000 then returns the data from the addressed register. PDATA is in this case used as an output and must be tri-stated (or set high n the case of an open collector pin) by the microcontroller during the data read-back (D7:0). The read operation is illustrated in Figure 5. Figure 4. Configuration registers write operation Chipcon AS SmartRFa CC1000 PRELIMINARY Datasheet (rev. 1.0) 2001-09-05 Page 10 of 39 SmartRF a CC1000 Figure 5. Configuration registers read operation Parameter Symbol Min Max Units Conditions CLOCK, clock frequency FCLOCK - 10 MHz CLOCK low pulse duration TCL,min 50 ns The minimum time CLOCK must be low. CLOCK high pulse duration TCH,min 50 ns The minimum time CLOCK must be high. PALE setup time TSA 10 - ns The minimum time PALE must be low before negative edge of CLOCK. PALE hold time THA 10 - ns The minimum time PALE must be held low after the positive edge of CLOCK. PDATA setup time TSD 10 - ns The minimum time data on PDATA must be ready before the negative edge of CLOCK. PDATA hold time THD 10 - ns The minimum time data must be held at PDATA, after the negative edge of CLOCK. PALE setup time TSA 10 - ns The minimum time PALE must be ready before negative edge of CLOCK. Rise time Trise 100 ns The maximum rise time for CLOCK and STROBE Fall time Tfall 100 ns The maximum fall time for CLOCK and STROBE Note: The set-up- and hold-times refer to 50% of VDD. Table 2. Serial interface, timing specification Chipcon AS SmartRFa CC1000 PRELIMINARY Datasheet (rev. 1.0) 2001-09-05 Page 11 of 39 SmartRF a CC1000 Microcontroller Interface Used in a typical system, CC1000 will interface to a microcontroller. This microcontroller must be able to: * * Program CC1000 into different modes via the 3-wire serial configuration interface (PDATA, PCLK and PALE). Interface to the bi-directional synchronous data signal interface (DIO and DCLK). Connecting the microcontroller The microcontroller uses 3 output pins for the configuration interface (PDATA, PCLK and PALE. PDATA should be a bidirectional pin for data read-back. A bidirectional pin is used for data (DIO) to be transmitted and data received. DCLK providing the data timing should be connected to a microcontroller input. CC1000 * * * Optionally the microcontroller can do data encoding / decoding. Optionally the microcontroller can monitor the frequency lock status from pin CHP_OUT (LOCK). Optionally the microcontroller can monitor the RSSI output for signal strength acquisition. Optionally another pin can be used to monitor the LOCK signal (available at the CHP_OUT pin). This signal is logic level high when the PLL is in lock. See Figure 6. Also the RSSI signal can be connected to the microcontroller if it has an analogue ADC input. PDATA PCLK PALE Microcontroller DIO DCLK CHP_OUT (LOCK) (Optional) (Optional) RSSI/IF ADC Figure 6. Microcontroller interface Chipcon AS SmartRFa CC1000 PRELIMINARY Datasheet (rev. 1.0) 2001-09-05 Page 12 of 39 SmartRF a CC1000 Signal interface The signal interface consists of DIO and DCLK and is used for the data to be transmitted and data received. DIO is the bi-directional data line and DCLK provides a synchronous clock both during data transmission and data reception. The CC1000 can be used with NRZ (NonReturn-to-Zero) data or Manchester (also known as bi-phase-level) encoded data. CC1000 can also synchronise the data from the demodulator and provide the data clock at DCLK. CC1000 can be configured for three different data formats: Synchronous NRZ mode. In transmit mode CC1000 provides the data clock at DCLK, and DIO is used as data input. Data is clocked into CC1000 at the rising edge of DCLK. The data is modulated at RF without encoding. CC1000 can be configured for the data rates 0.6, 1.2, 2.4, 4.8, 9.6 or 19.2 kbit/s. In receive mode CC1000 does the synchronisation and provides received data clock at DCLK and data at DIO. The data should be clocked into the interfacing circuit at the rising edge of DCLK. See Figure 7. Synchronous Manchester encoded mode. In transmit mode CC1000 provides the data clock at DCLK, and DIO is used as data input. Data is clocked into CC1000 at the rising edge of DCLK and should be in NRZ format. The data is modulated at RF with Manchester code. The encoding is done by CC1000. In this mode CC1000 can be configured for the data rates 0.3, 0.6, 1.2, 2.4, 4.8 or 9.6 kbit/s. The 9.6 kbit/s rate corresponds to the maximum 19.2 kBaud due to the Manchester encoding. In CC1000 does the receive mode synchronisation and provides received data clock at DCLK and data at DIO. Chipcon AS CC1000 does the decoding and NRZ data is presented at DIO. The data should be clocked into the interfacing circuit at the rising edge of DCLK. See Figure 8. Transparent Asynchronous UART mode. In transmit mode DIO is used as data input. The data is modulated at RF without synchronisation or encoding. In receive mode the raw data signal from the demodulator is sent to the output. No synchronisation or decoding of the signal is done in CC1000 and should be done by the interfacing circuit. The DCLK pin is used as data output in this mode. Data rates in the range from 0.6 to 19.2 kBaud can be used. See Figure 9. Manchester encoding and decoding In the Synchronous Manchester encoded mode CC1000 uses Manchester coding when modulating the data. The CC1000 also performs the data decoding and synchronisation. The Manchester code is based on transitions; a "0" is encoded as a low-to-high transition, a "1" is encoded as a high-to-low transition. See Figure 10. The CC1000 can detect a Manchester decoding violation and will set a Manchester Violation Flag when such a violation is detected in the incoming signal. The threshold limit for the Manchester Violation can be set in the MODEM1 register. The Manchester Violation Flag can be monitored at the CHP_OUT (LOCK) pin, configured in the LOCK register. The Manchester code ensures that the signal has a constant DC component, which is necessary in some FSK demodulators. Using this mode also ensures compatibility with CC400/CC900 designs. SmartRFa CC1000 PRELIMINARY Datasheet (rev. 1.0) 2001-09-05 Page 13 of 39 SmartRF a CC1000 Figure 7. Synchronous NRZ mode Figure 8. Synchronous Manchester encoded mode Chipcon AS SmartRFa CC1000 PRELIMINARY Datasheet (rev. 1.0) 2001-09-05 Page 14 of 39 SmartRF a CC1000 Figure 9. Transparent Asynchronous UART mode 10110001101 TX data Time Figure 10. Manchester encoding Chipcon AS SmartRFa CC1000 PRELIMINARY Datasheet (rev. 1.0) 2001-09-05 Page 15 of 39 SmartRF a CC1000 Bit synchroniser and data decision The built-in bit synchroniser extracts the data rate and performs data decision. The data decision is done using over-sampling and digital filtering of the incoming signal. This improves the reliability of the data transmission. Using the synchronous modes simplifies the data-decoding task substantially. All modes need a DC balanced preamble for the data slicer to acquire correct comparison level from an averaging filter. The minimum length of the preamble depends on the acquisition mode selected. The locking of the averaging filter value can be done through the configuration interface, or it can be done automatically Settling SETTLING* Manual Lock NRZ mode LOCK_AVG_MODE =1 LOCK_AVG_IN = 01** 14 25 46 89 after a predefined (LOCK_AVG_MODE in MODEM1). time The minimum number of balanced bauds depends on the settling time of the averaging filter which is set by SETTLING in MODEM1. Table 3 gives the minimum recommended number of bauds (chips) for the preamble in NRZ and UART modes. If Manchester coding is used, there is no need to lock the averaging filter and it can be left free-running (LOCK_AVG_IN in MODEM1). Table 4 gives the the minimum recommended number of bauds (chips) for the preamble in Manchester mode. Manual Lock UART mode LOCK_AVG_MODE =1 LOCK_AVG_IN = 01** 11 22 43 86 Automatic Lock NRZ mode LOCK_AVG_MODE =0 LOCK_AVG_IN = X*** 16 32 64 128 Automatic Lock UART mode LOCK_AVG_MODE =0 LOCK_AVG_IN = X*** 16 32 64 128 00 01 10 11 Notes: *All configuration bits are in the MODEM1 register ** The averaging filter is locked when LOCK_AVG_IN is set to 1 *** X = Do not care. The timer for the automatic lock is started when RX mode is set in the MAIN register Table 3. Minimum number of balanced bauds (chips) in the preamble in NRZ and UART modes Settling Free-running Manchester mode LOCK_AVG_MODE =1 SETTLING* LOCK_AVG_IN = 0 00 23 01 34 10 55 11 98 Note: *All configuration bits are in the MODEM1 register Table 4. Minimum number of balanced bauds (chips) in the preamble in Manchester mode Chipcon AS SmartRFa CC1000 PRELIMINARY Datasheet (rev. 1.0) 2001-09-05 Page 16 of 39 SmartRF a CC1000 Frequency programming The operation frequency is set by programming the frequency word in the configuration registers. There are two frequency words registers, termed A and B, which can be programmed to two different frequencies. One of the frequency words can be used for RX (local oscillator frequency) and other for TX (transmitting frequency) in order to be able to switch very fast between RX mode and TX mode. They can also be used for RX (or TX) at two different channels. Frequency word A or B is selected by the F_REG bit in the MAIN register. The frequency word is 24 bits (3 bytes) located in FREQ_2A:FREQ_1A:FREQ_0A and FREQ_2B:FREQ_1B:FREQ_0B for the A and B word respectively. The FSK frequency programmed in the registers (10 bits). separation is FSEP1:FSEP0 fVCO = f ref FREQ + 8192 16384 where the reference frequency is the crystal oscillator clock divided by REFDIV (4 bits in the PLL register), a number between 2 and 15: f ref = f xosc REFDIV The equation above gives the VCO frequency, that is, fVCO is the LO frequency for receive mode, and the f0 frequency for transmit mode (lower FSK frequency). The upper FSK frequency is given by: f1 = f0 + fsep where fsep is set by the separation word: f sep = f ref FSEP 16384 The frequency word FREQ is calculated by: Chipcon AS SmartRFa CC1000 PRELIMINARY Datasheet (rev. 1.0) 2001-09-05 Page 17 of 39 SmartRF a CC1000 Recommended settings for ISM frequencies Shown in Table 5 are the recommended frequency synthesiser settings for a few operating frequencies in the popular ISM bands. These settings ensure optimum spur-free performance of the synthesiser in receive mode. For some settings of the synthesiser, spurious signals can degrade the receiver's performance. The transmitter is not affected by spurious ISM Frequency [MHz] Actual frequency [MHz] 315 315.037200 433.3 433.302000 433.6 433.616400 433.9 433.916400 434.2 434.230800 434.5 434.530800 868.3 868.297200 868.95 868.918800 869.525 869.525000 869.85 869.840400 915 914.998800 Crystal frequency [MHz] 7.3728 11.0592 3.6864 7.3728 11.0592 3.6864 7.3728 11.0592 3.6864 7.3728 11.0592 3.6864 7.3728 11.0592 3.6864 7.3728 11.0592 3.6864 7.3728 11.0592 3.6864 7.3728 11.0592 3.6864 7.3728 11.0592 3.6864 7.3728 11.0592 3.6864 7.3728 11.0592 Low-side / high- side LO* High-side Low-side High-side Low-side High-side Low-side Low-side High-side Low-side High-side High-side signals, but recommended transmitter settings are included for completeness. The FSK frequency separation is set to 64 kHz. A spreadsheet is available from Chipcon generating configuration data for any frequency giving spurious-free settings. Reference divider Frequency word RX mode Frequency word TX mode Frequency seperation REFDIV FREQ FREQ FSEP 7 10 3 6 9 3 6 9 3 6 9 3 6 9 3 6 9 2 4 5 2 4 6 3 6 9 2 4 6 2 4 6 4894720 4661248 5767168 5767168 5767168 5775360 5775360 5775360 5775360 5775360 5775360 5783552 5783552 5783552 5783552 5783552 5783552 7708672 7708672 6422528 7716864 7716864 7716864 11583488 11583488 11583488 7725056 7725056 7725056 8126464 8126464 8126464 4891888 4658551 5768741 5768741 5768741 5772933 5772933 5772933 5776933 5776933 5776933 5781125 5781125 5781125 5785125 5785125 5785125 7709720 7709720 6423402 7715246 7715246 7715246 11585061 11585061 11585061 7723438 7723438 7723438 8124846 8124846 8124846 995 948 853 853 853 853 853 853 853 853 853 853 853 853 853 853 853 568 568 474 568 568 568 853 853 853 568 568 568 568 568 568 *Note: When using low-side LO injection the data at DIO will be inverted. Table 5. Recommended settings for ISM frequencies Chipcon AS SmartRFa CC1000 PRELIMINARY Datasheet (rev. 1.0) 2001-09-05 Page 18 of 39 SmartRF a CC1000 VCO Only one external inductor (L101) is required for the VCO. The inductor will determine the operating frequency range of the circuit. It is important to place the inductor as close to the pins as possible in order to reduce stray inductance. It is recommended to use a high Q, low tolerance inductor for best performance. Item L101 315 MHz TBD nH, 5%, 0805 433 MHz 27 nH, 5%, 0805 (Koa KL732ATE27NJ) Typical tuning range for the integrated varactor is 20-25%. Component values for various frequencies are given in Table 6. Component values for other frequencies can be found using the SmartRF Studio software. 868 MHz 4.7 nH, 5%, 0805 (Koa KL732ATE4N7J) 915 MHz TBD nH, 5%, 0805 Table 6. VCO inductor component value VCO and PLL self-calibration To compensate for supply voltage, temperature and process variations the VCO and PLL must be calibrated. The calibration is done automatically and sets maximum VCO tuning range and optimum charge pump current for PLL stability. After setting up the device at the operating frequency, the self-calibration can be initiated by setting the CAL_START bit. The calibration result is stored internally in the chip, and is valid as long as power is not turned off. If large supply voltage variations (more than 0.5 V) or temperature variations (more than 40 degrees) occur after calibration, a new calibration should be performed. The self-calibration is controlled through the CAL register (see configuration registers description p. 29). The CAL_COMPLETE bit indicates complete calibration. The user can poll this bit, or simply wait for 28 ms (calibration wait time when CAL_WAIT = 1). The CAL_COMPLETE bit can also be monitored at the CHP_OUT (LOCK) pin (configured by LOCK_SELECT3:0) and used as an interrupt input to the microcontroller. There are separate calibration values for the two frequency registers. If the two frequencies, A and B, differ more than 2 MHz, or different charge pump currents are used (VCO_CURRENT in the CURRENT register) the calibration should be done separately. When using a 10.7 MHz external IF the LO is 10.7 MHz below/above the transmit frequency, hence separate calibration must be done. The CAL_DUAL bit in the CAL register controls dual or separate calibration. Power management CC1000 offers great flexibility for power management in order to meet strict power consumption requirements in battery operated applications. Power Down mode is controlled through the MAIN register. There are separate bits to control the RX part, the TX part, the frequency synthesiser and the crystal oscillator (see page 29). This individual control can be used to optimise for lowest possible Chipcon AS current consumption application. in a certain A typical power-on sequence for minimum power consumption is shown in Figure 11. The VCO current is programmable and should be set according to operating frequency and output power. Recommended settings for the SmartRFa CC1000 PRELIMINARY Datasheet (rev. 1.0) 2001-09-05 Page 19 of 39 SmartRF a CC1000 VCO_CURRENT bits in the CURRENT register are shown in the tables page 29ff. Power Off Power turned on Initialise and reset CC1000 RX_PD = 0 TX_PD = 1 FS_PD = 0 CORE_PD = 0 BIAS_PD = 0 RXTX = 0 F_REG = 0 RESET_N = 0, then RESET_N=1 Frequency register A is used for RX mode, register B for TX Program all registers except MAIN Calibrate VCO and PLL Calibration is performed in RX mode Power Down If RX then RXTX = 0, F_REG = 0 If TX then RXTX = 1, F_REG = 1 Turn on crystal oscillator core CORE_PD = 0 Wait 2 ms* *Time to wait depends on crystal frequency and load capacitance Turn on bias generator BIAS_PD = 0 Wait 200 s Turn on frequency synthesiser FS_PD = 0 Wait 250 s RX or TX? Turn on RX RX_PD = 0 RX ready depends on demodulator Turn on TX TX_PD = 0 Wait 20 s Figure 11. Power-on sequence Chipcon AS SmartRFa CC1000 PRELIMINARY Datasheet (rev. 1.0) 2001-09-05 Page 20 of 39 SmartRF a CC1000 Input / Output Matching A few passive external components combined with the internal T/R switch circuitry ensures match in both RX and TX mode. The matching network is shown in Figure 12. Component values for various frequencies are given in Table 7. Component values for other frequencies can be found using the configuration software. Figure 12. Input/output matching network Item C31 C41 C42 L32 315 MHz TBD pF, 5%, C0G, 0603 TBD pF, 5%, C0G, 0603 TBD pF, 5%, C0G, 0603 TBD nH, 10%, 0805 433 MHz 15 pF, 5%, C0G, 0603 8.2 pF, 5%, C0G, 0603 5.6 pF, 5%, C0G, 0603 68 nH, 10%, 0805 868 MHz 10 pF, 5%, C0G, 0603 Not used 4.7 pF, 5%, C0G, 0603 120 nH, 10%, 0805 (Coilcraft 0805CS-680XKBC) (Coilcraft 0805CS-121XKBC) L41 TBD nH, 10%, 0805 6.2 nH, 10%, 0805 2.5 nH, 10%, 0805 (Coilcraft 0805HQ-6N2XKBC) (Coilcraft 0805HQ-2N5XKBC) 915 MHz TBD pF, 5%, C0G, 0603 Not used TBD pF, 5%, C0G, 0603 TBD nH, 10%, 0805 TBD nH, 10%, 0805 Table 7. Matching network component values Chipcon AS SmartRFa CC1000 PRELIMINARY Datasheet (rev. 1.0) 2001-09-05 Page 21 of 39 SmartRF a CC1000 RSSI output CC1000 has a built-in RSSI (Received Signal Strength Indicator) giving an analogue output signal at the RSSI/IF pin. The IF_RSSI bits in the FRONT_END register enable the RSSI. When the RSSI function is enabled, the output current of this pin is inversely proportional to the input signal level. The output should be terminated in a resistor to convert the current output into a voltage. A capacitor is used in order to low-pass filter the signal. P = -51.3 VRSSI- 49.2 [dBm] at 433 MHz P = -50.0 VRSSI- 45.5 [dBm] at 868 MHz The external network for RSSI operation is shown in Figure 13. R281 = 27 k, C281 = 1nF. A typical plot of RSSI voltage as function of input power is shown in Figure 14. Voltage The RSSI voltage range from 0 - 1.2 V when using a 27 k terminating resistor, giving approximately 50 dB/V. This RSSI voltage can be measured by an A/D converter. Note that a higher voltage means a lower input signal. The RSSI measures the power referred to the RF_IN pin. The input power can be calculated using the following equations: 1.3 1.2 1.1 1 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 -105 -100 -95 433Mhz 868Mhz -90 -85 -80 -75 -70 -65 -60 -55 dBm Figure 13. RSSI circuit Chipcon AS Figure 14. RSSI voltage vs. input power SmartRFa CC1000 PRELIMINARY Datasheet (rev. 1.0) 2001-09-05 Page 22 of 39 -50 SmartRF a CC1000 IF output CC1000 has a built-in 10.7 MHz IF output buffer. This buffer could be applied in narrow-band applications with requirements on mirror image filtering. The system is then built with CC1000, a 10.7 MHz ceramic filter and an external 10.7 MHz demodulator. The external network for IF output operation is shown in Figure 15. R281 = 470 , C281 = 3.3nF. The external network provides 330 source impedance for the 10.7 MHz ceramic filter. Figure 15. IF Output Chipcon AS SmartRFa CC1000 PRELIMINARY Datasheet (rev. 1.0) 2001-09-05 Page 23 of 39 SmartRF a CC1000 Crystal oscillator An external clock signal or the internal crystal oscillator can be used as main frequency reference. An external clock signal should be connected to XOSC_Q1, while XOSC_Q2 should be left open. The XOSC_BYPASS bit in the CURRENT register should be set when an external clock signal is used. The crystal frequency should be in the range 3-4, 6-8 or 9-16 MHz. Because the crystal frequency is used as reference for the data rate (as well as other internal functions), the following frequencies are recommended: 3.6864, 7.3728, 11.0592 or 14.7456 MHz. These frequencies will give accurate data rates. The crystal frequency range is selected by XOSC_FREQ1:0 in the MODEM0 register. Using the internal crystal oscillator, the crystal must be connected between XOSC_Q1 and XOSC_Q2. The oscillator is designed for parallel mode operation of the crystal. In addition loading capacitors (C171 and C181) for the crystal are required. The loading capacitor values depend on the total load capacitance, CL, specified for the crystal. The total load capacitance seen between the crystal terminals should equal CL for the crystal to oscillate at the specified frequency. CL = 1 1 1 + C171 C181 + C parasitic The parasitic capacitance is constituted by pin input capacitance and PCB stray capacitance. Typically the total parasitic capacitance is 8 pF. A trimming capacitor may be placed across C171 for initial tuning if necessary. The crystal oscillator circuit is shown in Figure 16. Typical component values for different values of CL are given in Table 8. The initial tolerance, temperature drift, ageing and load pulling should be carefully specified in order to meet the required frequency accuracy in a certain application. By specifying the total expected frequency accuracy in SmartRF Studio together with data rate and frequency separation, the software will calculate the total bandwidth and compare to the available IF bandwidth. Any contradictions will be reported by the software and a more accurate crystal will be recommended if required. Figure 16. Crystal oscillator circuit Item C171 C181 CL= 12 pF 6.8 pF 6.8 pF CL= 16 pF 15 pF 15 pF CL= 22 pF 27 pF 27 pF Table 8. Crystal oscillator component values Chipcon AS SmartRFa CC1000 PRELIMINARY Datasheet (rev. 1.0) 2001-09-05 Page 24 of 39 SmartRF a CC1000 Frequency spectrum shaping and dithering The CC1000 has the unique possibility of frequency spectrum shaping and dithering. The inherent abrupt frequency change using FSK modulation gives a broad RF spectrum. By using a smooth frequency shift, the spectrum broadening can be reduced, see Figure 17. This smooth frequency shift can be implemented by stepping through several intermediate frequencies between the two FSK frequencies. CC1000 use 16 intermediate frequencies that are specified in the seven FSHAPE registers. The frequency steps are made anti-symmetrical, hence only seven values are specified to define the 16 steps, see Figure 18. The data shaping is turned on using the SHAPE bit in the FSCTRL register. equal spacing of steps through one baud period, use FSDELAY = f ref 16 BaudRate -1 where the reference frequency, fref, is the crystal oscillator clock divided by REFDIV. Shorter time-steps could also be used. The default values after reset correspond to a raised cosine frequency change for maximum deviation. Dithering of the PLL can be used to reduce spurious signals originating from internal reference frequencies. The dithering is turned on by the DITHER1 and DITHER0 bits in the FSCTRL register. The maximum frequency separation using frequency shaping is FSEP = 63. The time-step is programmed in the FSDELAY register. This value should correspond to the data rate used. For Figure 17. FSK spectrum shaping by smooth frequency transitions Chipcon AS SmartRFa CC1000 PRELIMINARY Datasheet (rev. 1.0) 2001-09-05 Page 25 of 39 SmartRF a CC1000 Figure 18. Stepwise frequency shaping Optional LC Filter An optional LC filter may be added between the antenna and the matching network in certain applications. The filter will reduce the emission of harmonics and increase the receiver selectivity. The filter topology is shown in Figure 19. Component values are given in Table 9. The filter is designed for 50 terminations. The component values may have to be tuned to compensate for layout parasitics. Figure 19. LC filter Item C71 C72 L71 315 MHz 30 pF 30 pF 15 nH 433 MHz 20 pF 20 pF 12 nH 868 MHz 10 pF 10 pF 5.6 nH 915 MHz 10 pF 10 pF 4.7 nH Table 9. LC filter component values Chipcon AS SmartRFa CC1000 PRELIMINARY Datasheet (rev. 1.0) 2001-09-05 Page 26 of 39 SmartRF a CC1000 System Considerations and Guidelines SRD regulations International regulations and national laws regulate the use of radio receivers and transmitters. SRDs (Short Range Devices) for licence free operation are allowed to operate in the 433 and 868-870 MHz bands in most European countries. In the United States such devices operate in the 260-470 and 902-928 MHz bands. CC1000 is designed to meet the requirements for operation in all these bands. A summary of the most important aspects of these regulations can be found in Application Note AN001 SRD regulations for licence free transceiver operation, available from Chipcon's web site. Low cost systems In systems where low cost is of great importance the CC1000 is the ideal choice. Very few external components keeps the total cost at a minimum. The oscillator crystal can then be a low cost crystal with 50 ppm frequency tolerance. Battery operated systems In low power applications the power down mode should be used when not being active. Depending on the start-up time requirement, the oscillator core can be powered during power down. See page 19 for information on how effective power management can be implemented. Narrow band systems CC1000 can also be used in narrow band systems, but CC400 and CC900 are recommended for best performance in such applications. The phase noise of CC400 / CC900 is superior and for systems with 25 kHz channel spacing with strict requirements to ACP (Adjacent Channel Power) low phase noise is important. If CC1000 is used in a narrow band receiver, an external ceramic filter and demodulator is recommended. A unique feature in CC1000 is the very fine frequency resolution of 250 Hz. This can be used to do the temperature compensation of the crystal if the temperature drift curve is known and a temperature sensor is included in the system. Even initial adjustment can be Chipcon AS done using the frequency programmability. This eliminates the need for an expensive TCXO and trimming in some applications. In less demanding applications a crystal with low temperature drift and low ageing could be used without further compensation. A trimmer capacitor in the crystal oscillator circuit (in parallel with C171) could be used to set the initial frequency accurately. CC1000 also exhibits a unique spectrumshaping feature in order to improve the ACP even for large data rates. In `true' FSK systems with abrupt frequency shifting the spectrum is inherently broad. By making the frequency shift `softer' the spectrum can be made significantly narrower. Thus, higher data rates can be transmitted in the same bandwidth. High reliability systems Using a SAW filter as a preselector will improve the communication reliability in harsh environments by reducing the probability of blocking. The receiver sensitivity and the output power will be reduced due to the filter insertion loss. By inserting the filter in the RX path only, together with an external RX/TX switch, only the receiver sensitivity is reduced, and output power is remained. The CHP_OUT (LOCK) pin can be configured to control an external LNA, RX/TX switch or power amplifier. This is controlled by LOCK_SELECT in the LOCK register. Frequency hopping spread spectrum systems Due to the very fast frequency shift properties of the PLL, the CC1000 is also suitable for frequency hopping systems. Hop rates of 1-100 hops/s are usually used depending on the bit rate and the amount of data to be sent during each transmission. The two frequency registers (FREQ_A and FREQ_B) are designed such that the `next' frequency can be programmed while the `present' frequency is used. The switching between the two frequencies is done through the MAIN register. SmartRFa CC1000 PRELIMINARY Datasheet (rev. 1.0) 2001-09-05 Page 27 of 39 SmartRF a CC1000 PCB Layout Recommendations A two layer PCB is highly recommended. The bottom layer of the PCB should be the "ground-layer". Precaution should be used when placing the microcontroller in order to avoid interference with the RF circuitry. The top layer should be used for signal routing, and the open areas should be filled with metallisation connected to ground using several vias. The ground pins should be connected to ground as close as possible to the package pin using individual vias. The decoupling capacitors should also be placed as close as possible to the supply pins and connected to the ground plane by separate vias. In certain applications where the ground plane for the digital circuitry is expected to be noisy, the ground plane may be split in an analogue and a digital part. All AGND pins and AVDD de-coupling capacitors should be connected to the analogue ground plane. All DGND pins and DVDD de-coupling capacitors should be connected to the digital ground. The connection between the two ground planes should be implemented as a star connection with the power supply ground. The external components should be as small as possible and surface mount devices are preferred. A development kit with a fully assembled PCB is available, and can be used as a guideline for layout. Antenna Considerations CC1000 can be used together with various types of antennas. The most common antennas for short range communication are monopole, helical and loop antennas. Monopole antennas are resonant antennas with a length corresponding to one quarter of the electrical wavelength (/4). They are very easy to design and can be implemented simply as a "piece of wire" or even integrated into the PCB. Non-resonant monopole antennas shorter than /4 can also be used, but at the expense of range. In size and cost critical applications such an antenna may very well be integrated into the PCB. Helical antennas can be thought of as a combination of a monopole and a loop antenna. They are a good compromise in size critical applications. But helical antennas tend to be more difficult to optimise than the simple monopole. difficult impedance matching because of their very low radiation resistance. For low power applications the /4monopole antenna is recommended giving the best range and because of its simplicity. The length of the /4-monopole antenna is given by: L = 7125 / f where f is in MHz, giving the length in cm. An antenna for 869 MHz should be 8.2 cm, and 16.4 cm for 434 MHz. The antenna should be connected as close as possible to the IC. If the antenna is located away from the input pin the antenna should be matched to the feeding transmission line (50 ). For a more thorough primer on antennas, please refer to Application Note AN003 SRD Antennas available from Chipcon's web site. Loop antennas are easy to integrate into the PCB, but are less effective due to Chipcon AS SmartRFa CC1000 PRELIMINARY Datasheet (rev. 1.0) 2001-09-05 Page 28 of 39 SmartRF a CC1000 Configuration registers The configuration of CC1000 is done by programming the 29 8-bit configuration registers. The configuration data based on selected system parameters are most easily found by using the SmartRF Studio software. A complete description of the registers are given in the following tables. After a RESET is programmed all the registers have default values. The TEST registers are also set to default values after a RESET, and should not be altered by the user. REGISTER OVERVIEW ADDRESS 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 40h 41h 42h 43h 44h 45h 46h Chipcon AS Byte Name MAIN FREQ_2A FREQ_1A FREQ_0A FREQ_2B FREQ_1B FREQ_0B FSEP1 FSEP0 CURRENT FRONT_END PA_POW PLL LOCK CAL MODEM2 MODEM1 MODEM0 MATCH FSCTRL FSHAPE7 FSHAPE6 FSHAPE5 FSHAPE4 FSHAPE3 FSHAPE2 FSHAPE1 FSDELAY PRESCALER TEST6 TEST5 TEST4 TEST3 TEST2 TEST1 TEST0 Description MAIN Register Frequency Register 2A Frequency Register 1A Frequency Register 0A Frequency Register 2B Frequency Register 1B Frequency Register 0B Frequency Separation Register 1 Frequency Separation Register 0 Current Consumption Control Register Front End Control Register PA Output Power Control Register PLL Control Register LOCK Status Register and signal select to CHP_OUT (LOCK) pin VCO Calibration Control and Status Register Modem Control Register 2 Modem Control Register 1 Modem Control Register 0 Match Capacitor Array Control Register for RX and TX impedance matching Frequency Synthesiser Control Register Frequency Shaping Register 7 Frequency Shaping Register 6 Frequency Shaping Register 5 Frequency Shaping Register 4 Frequency Shaping Register 3 Frequency Shaping Register 2 Frequency Shaping Register 1 Frequency Shaping Delay Register Prescaler and IF-strip test control register Test register for PLL LOOP Test register for PLL LOOP Test register for PLL LOOP Test register for VCO Test register for Calibration Test register for Calibration Test register for Calibration SmartRFa CC1000 PRELIMINARY Datasheet (rev. 1.0) 2001-09-05 Page 29 of 39 SmartRF a CC1000 MAIN Register REGISTER NAME MAIN[7] MAIN[6] RXTX F_REG Default value - MAIN[5] RX_PD - H MAIN[4] MAIN[3] MAIN[2] MAIN[1] TX_PD FS_PD CORE_PD BIAS_PD - H H H H MAIN[0] RESET_N - L FREQ_2A Register REGISTER FREQ_2A[7:0] FREQ_1A Register REGISTER FREQ_1A[7:0] FREQ_0A Register REGISTER FREQ_0A[7:0] FREQ_2B Register REGISTER FREQ_2B[7:0] FREQ_1B Register REGISTER FREQ_1B[7:0] FREQ_0B Register REGISTER NAME FREQ_A[23:16] NAME FREQ_A[15:8] NAME FREQ_A[7:0] NAME FREQ_B[23:16] NAME FREQ_B[15:8] NAME FREQ_0B[7:0] FREQ_B[7:0] FSEP1 Register REGISTER NAME FSEP1[7:3] FSEP1[2:0] FSEP_MSB[2:0] Chipcon AS Active - Description RX/TX switch, 0 : RX , 1 : TX Selection of Frequency Register, 0 : Register A, 1 : Register B Power Down of LNA, Mixer, IF, Demodulator, RX part of Signal Interface Power Down of TX part of Signal Interface, PA Power Down of Frequency Synthesiser Power Down of Crystal Oscillator Core Power Down of BIAS (Global_Current_Generator) and Crystal Oscillator Buffer Reset, active low. Writing RESET_N low will write default values to all other registers than MAIN. Bits in MAIN do not have a default value, and will be written directly through the configurations interface. Must be set high to complete reset. Default value 01110101 Active Default value 10100000 Active Default value 11001011 Active Default value 01110101 Active Default value 10100101 Active Default value 01001110 Active Default value 000 Active - - - - - - - Description 8 MSB of frequency control word A Description Bit 15 to 8 of frequency control word A Description 8 LSB of frequency control word A Description 8 MSB of frequency control word B Description Bit 15 to 8 of frequency control word B Description 8 LSB of frequency control word B Description Not used 3 MSB of frequency separation control SmartRFa CC1000 PRELIMINARY Datasheet (rev. 1.0) 2001-09-05 Page 30 of 39 SmartRF a CC1000 FSEP0 Register REGISTER NAME FSEP0[7:0] FSEP_LSB[7:0] CURRENT Register REGISTER CURRENT[7:4] Default value 01011001 NAME VCO_CURRENT[3:0] Default value 1100 Active - Description 8 LSB of frequency separation control Active - Description Control of current in VCO core for TX and RX 0000 : 150A 0001 : 250A 0010 : 350A 0011 : 450A 0100 : 950A, use for RX, f<500 MHz 0101 : 1050A 0110 : 1150A 0111 : 1250A 1000 : 1450A, use for RX, f>500 MHz 1001 : 1550A 1010 : 1650A 1011 : 1750A 1100 : 2250A 1101 : 2350A 1110 : 2450A 1111 : 2550A, use for TX CURRENT[3:2] LO_DRIVE[1:0] 10 Control of current in VCO buffer for LO drive 00 : 0.5mA, use for RX, f<500 MHz 01 : 1.0mA 10 : 1.5mA 11 : 2.0mA, use for RX, f>500 MHz CURRENT[1:0] PA_DRIVE[1:0] 10 Control of current in VCO buffer for PA 00 : 1mA 01 : 2mA, use for TX, f<500 MHz 10 : 3mA 11 : 4mA, use for TX, f>500 MHz FRONT_END Register REGISTER NAME Default value 00 0 Active - Not used Control of current in the LNA_FOLLOWER 0 : 520uA, use for f<500 MHz 1 : 690uA, use for f>500 MHz Control of current in LNA 00 : 0.8mA, use for f<500 MHz 01 : 1.4mA 10 : 1.8mA, use for f>500 MHz 11 : 2.2mA Control of IF_RSSI pin 00 : Internal IF and demodulator, RSSI inactive 01 : RSSI active, RSSI/IF is analog RSSI output 10 : External IF and demodulator, RSSI/IF is mixer output. Internal IF in power down mode. 11 : RSSI calibration mode (for zeroing) 0 : Internal XOSC enabled 1 : Power-Down of XOSC, external CLK used FRONT_END[7:6] FRONT_END[5] BUF_CURRENT FRONT_END[4:3] LNA_CURRENT [1:0] 01 - FRONT_END[2:1] IF_RSSI[1:0] 00 - FRONT_END[0] XOSC_BYPASS 0 - Chipcon AS Description SmartRFa CC1000 PRELIMINARY Datasheet (rev. 1.0) 2001-09-05 Page 31 of 39 SmartRF a CC1000 PA_POW Register REGISTER PA_POW[7:4] PA_POW[3:0] PLL Register REGISTER PLL[7] PLL[6:3] NAME Default value 0000 1111 Active NAME Default value Active EXT_FILTER 0 - PA_HIGHPOWER[3:0] PA_LOWPOWER[3:0] REFDIV[3:0] - 0010 - Description Control of output power in high power array Control of output power in low power array Description 1 : External loop filter 0 : Internal loop filter 1-to-0 transition samples F_COMP comparator when BREAK_LOOP=1 (TEST3) Reference divider 0000 : Not allowed 0001 : Not allowed 0010 : Divide by 2 0011 : Divide by 3 ........... PLL[2] ALARM_DISABLE 0 h PLL[1] ALARM_H - - PLL[0] ALARM_L - - LOCK Register REGISTE NAME R LOCK[7:4] LOCK_SELECT[3:0] Default value 0000 Active - 1111 : Divide by 15 0 : Alarm function enabled 1 : Alarm function disabled Status bit for tuning voltage out of range (too close to VDD) Status bit for tuning voltage out of range (too close to GND) Description Selection of signals to CHP_OUT (LOCK) pin 0000 : Normal, pin can be used as CHP_OUT 0001 : LOCK_CONTINUOUS 0010 : LOCK_INSTANT 0011 : ALARM_H 0100 : ALARM_L 0101 : CAL_COMPLETE 0110 : IF_OUT 0111 : REFERENCE_DIVIDER Output 1000 : TX_PDB (activates external PA) 1001 : Manchester Violation 1010 : RX_PDB (activates external LNA) 1011 : Not defined 1100 : Not defined 1101 : LOCK_AVG_FILTER 1110 : N_DIVIDER Output 1111 : F_COMP LOCK[3] PLL_LOCK_ ACCURACY 0 - LOCK[2] PLL_LOCK_ LENGTH LOCK_INSTANT 0 - - - LOCK[1] Chipcon AS 0 : Sets Lock Threshold = 127, Reset Lock Threshold = 111. Corresponds to a worst case accuracy of 0.7% 1 : Sets Lock Threshold = 31, Reset Lock Threshold =15. Corresponds to a worst case accuracy of 2.8% 0 : PLL_LOCK_WINDOW is 4 PRE_CLK cycles 1 : PLL_LOCK_WINDOW is 8 PRE_CLK cycles Status bit from Lock Detector SmartRFa CC1000 PRELIMINARY Datasheet (rev. 1.0) 2001-09-05 Page 32 of 39 SmartRF a CC1000 LOCK[0] LOCK_CONTINUOUS CAL Register REGISTER NAME - - Status bit from Lock Detector CAL[7] CAL_START Default value 0 CAL[6] CAL_DUAL 0 H CAL[5] CAL_WAIT 0 H CAL[4] CAL_CURRENT 0 H CAL[3] CAL_COMPLETE 0 H CAL[2:0] CAL_ITERATE 101 H MODEM2 Register REGISTER MODEM2[7] PEAKDETECT Default value 1 MODEM2[6:0] PEAK_LEVEL_OFFSET[6:0] 0010110 Chipcon AS NAME Active Description 1 : Calibration started 0 : Calibration inactive 1 : Store calibration in both A and B 0 : Store calibration in A or B defined by MAIN[6] 1 : Normal Calibration Wait Time Doubled 0 : Half Calibration Wait Time 1 : Calibration Current Doubled 0 : Normal Calibration Current Status bit defining that calibration is complete Iteration start value for calibration DAC 000 : 1 001 : 2 010 : 3 011 : 4 100 : 5 101 : 6 110 : 7 111 : 8 Active - H Description Peak Detector and Remover disabled or enabled 0 : Peak detector and remover is disabled 1 : Peak detector and remover is enabled Threshold level for Peak Remover in Demodulator. Correlated to frequency deviation SmartRFa CC1000 PRELIMINARY Datasheet (rev. 1.0) 2001-09-05 Page 33 of 39 SmartRF a CC1000 MODEM1 Register REGISTER NAME MODEM1[7:5] MLIMIT Default value 011 Active - Description Sets the limit for the Manchester Violation Flag. A Manchester Value = 14 is a perfect bit and a Manchester Value = 0 is a constant level (an unbalanced corrupted bit) 000 : No Violation Flag is set 001 : Violation Flag is set for Manchester Value < 1 010 : Violation Flag is set for Manchester Value < 2 011 : Violation Flag is set for Manchester Value < 3 100 : Violation Flag is set for Manchester Value < 4 101 : Violation Flag is set for Manchester Value < 5 110 : Violation Flag is set for Manchester Value < 6 111 : Violation Flag is set for Manchester Value < 7 MODEM1[4] MODEM1[3] LOCK_AVG_IN LOCK_AVG_MODE MODEM1[2:1] SETTLING[1:0] 0 0 11 H Lock control bit of Average Filter - 0 : Average Filter is free-running 1 : Average Filter is locked Automatic lock of Average Filter - 0 : Lock of Average Filter is controlled automatically 1 : Lock of Average Filter is controlled by LOCK_AVG_IN Settling Time of Average Filter 00 : 11 baud settling time, worst case 1.2dB loss in sensitivity 01 : 22 baud settling time, worst case 0.6dB loss in sensitivity 10 : 43 baud settling time, worst case 0.3dB loss in sensitivity 11 : 86 baud settling time, worst case 0.15dB loss in sensitivity MODEM1[0] MODEM_RESET_N MODEM0 Register REGISTER NAME 1 L Separate reset of MODEM MODEM0[7] MODEM0[6:4] BAUDRATE[2:0] Default value 010 Active MODEM0[3:2] DATA_FORMAT[1:0] 01 - MODEM0[1:0] XOSC_FREQ[1:0] 00 - - Description Not used 000 : 0.6 kbaud 001 : 1.2 kbaud 010 : 2.4 kbaud 011 : 4.8 kbaud 100 : 9.6 kbaud 101 : 19.2kbaud 110 : Not used 111 : Not used 00 : NRZ operation. 01 : Manchester operation 10 : Transparent Asyncronous UART operation 11 : Not used Selection of XTAL frequency range 00 : 3MHz - 4MHz crystal, 3.6864MHz recommended 01 : 6MHz - 8MHz crystal, 7.3728MHz recommended 10 : 9MHz - 12MHz crystal, 11.0592 MHz recommended 11 : 12MHz - 16MHz crystal, 14.7456MHz recommended Chipcon AS SmartRFa CC1000 PRELIMINARY Datasheet (rev. 1.0) 2001-09-05 Page 34 of 39 SmartRF a CC1000 MATCH Register REGISTER MATCH[7:4] RX_MATCH[3:0] Default value 0000 MATCH[3:0] TX_MATCH[3:0] 0000 FSCTRL Register REGISTER NAME - - FSCTRL[7:4] FSCTRL[3] FSCTRL[2] DITHER1 DITHER0 Default value 0 0 FSCTRL[1] FSCTRL[0] SHAPE FS_RESET_N 0 1 H L NAME Default value 00001 Active Default value 00011 Active Default value 00110 Active Default value 01010 Active Default value 10000 Active Default value 10110 Active FSHAPE1 Register REGISTER FSHAPE1[7:5] FSHAPE1[4:0] -FSHAPE1 FSHAPE2 Register REGISTER FSHAPE2[7:5] FSHAPE2[4:0] FSHAPE3[7:5] FSHAPE3[4:0] NAME FSHAPE3 FSHAPE4 Register REGISTER FSHAPE4[7:5] FSHAPE4[4:0] NAME FSHAPE4 FSHAPE5 Register REGISTER FSHAPE5[7:5] FSHAPE5[4:0] NAME FSHAPE5 FSHAPE6 Register REGISTER Chipcon AS NAME FSHAPE2 FSHAPE3 Register REGISTER FSHAPE6[7:5] FSHAPE6[4:0] NAME Active NAME FSHAPE6 Active H H - - - - - - Description Selects matching capacitor array value for RX Selects matching capacitor array value for TX Description Not used Enable dithering when transmitting '1' Enable dithering during RX, and when transmitting '0' Enable data shaping Separate reset of shaping sequencer Description Not used Frequency shape register 1, used when SHAPE in FSCTRL is active. Description Not used Frequency shape register 2, used when SHAPE in FSCTRL is active. Description Not used Frequency shape register 3, used when SHAPE in FSCTRL is active. Description Not used Frequency shape register 4, used when SHAPE in FSCTRL is active. Description Not used Frequency shape register 5, used when SHAPE in FSCTRL is active. Description Not used Frequency shape register 6, used when SHAPE in FSCTRL is active. SmartRFa CC1000 PRELIMINARY Datasheet (rev. 1.0) 2001-09-05 Page 35 of 39 SmartRF a CC1000 FSHAPE7 Register REGISTER NAME FSHAPE7[7:5] FSHAPE7[4:0] FSHAPE7 FSDELAY Register REGISTER NAME FSDELAY[7:0] FSDELAY[7:0] PRESCALER Register REGISTER PRESCALER[7:6] PRESCALER[5:4] Default value 11100 Active Default value 00101111 Active NAME PRE_SWING[1:0] PRE_CURRENT [1:0] - Not used Frequency shape register 7, used when SHAPE in FSCTRL is active. Description - Default value 00 00 Sets the number of clock cycles delay between the use of the FSHAPE registers during frequency shaping Active Description - Prescaler swing. Fractions for PRE_CURRENT[1:0] = 00 00 : 1 * Nominal Swing 01 : 2/3 * Nominal Swing 10 : 7/3 * Nominal Swing 11 : 5/3 * Nominal Swing Prescaler current scaling - PRESCALER[3] IF_INPUT 0 - PRESCALER[2] IF_FRONT 0 - PRESCALER[1:0] - 00 - TEST6 Register (for test only) REGISTER NAME Description 00 : 1 * Nominal Current 01 : 2/3 * Nominal Current 10 : 1/2 * Nominal Current 11 : 2/5 * Nominal Current 0 : Nominal setting 1 : RSSI/IF pin is input to IF-strips 0 : Nominal setting 1 : Output of IF_Front_amp is switched to RSSI/IF pin Not used TEST6[7] LOOPFILTER_TP1 Default value 0 TEST6 [6] LOOPFILTER_TP2 0 - TEST6 [5] CHP_OVERRIDE 0 - TEST6[4:0] CHP_CO[4:0] 10000 - Active TEST5 Register (for test only) REGISTER NAME Active - TEST5[7:6] TEST5[5] CHP_DISABLE Default value 0 TEST5[4] VCO_OVERRIDE 0 - TEST5[3:0] VCO_AO[3:0] 1000 - Chipcon AS - Description 1 : Select testpoint 1 to CHP_OUT 0 : CHP_OUT tied to GND 1 : Select testpoint 2 to CHP_OUT 0 : CHP_OUT tied to GND 1 : use CHP_CO[4:0] value 0 : use calibrated value Charge_Pump Current DAC override value Description Not used 1 : CHP up and down pulses disabled 0 : normal operation 1 : use VCO_AO[2:0] value 0 : use calibrated value VCO_ARRAY override value SmartRFa CC1000 PRELIMINARY Datasheet (rev. 1.0) 2001-09-05 Page 36 of 39 SmartRF a CC1000 TEST4 Register (for test only) REGISTER NAME TEST4[7:6] TEST4[5:0] L2KIO[5:0] TEST3 Register (for test only) REGISTER NAME Default value 100101 Active Active h TEST3[7:5] TEST3[4] BREAK_LOOP Default value 0 TEST3[3:0] CAL_DAC_OPEN 0100 - Default value - Active Default value - Active Default value - Active TEST2 Register (for test only) REGISTER NAME TEST2[7:5] TEST2[4:0] CHP_CURRENT [4:0] TEST1 Register (for test only) REGISTER NAME TEST1[7:4] TEST1[3:0] CAL_DAC[3:0] TEST0 Register (for test only) REGISTER NAME TEST0[7:4] TEST0[3:0] Chipcon AS VCO_ARRAY[3:0] - - - - Description Not used Constant setting charge pump current scaling/rounding factor. Sets Bandwidth of PLL Description Not used 1 : PLL loop open 0 : PLL loop closed Calibration DAC override value, active when BREAK_LOOP =1 Description Not used Status vector defining applied CHP_CURRENT value Description Not used Status vector defining applied Calibration DAC value Description Not used Status vector defining applied VCO_ARRAY value SmartRFa CC1000 PRELIMINARY Datasheet (rev. 1.0) 2001-09-05 Page 37 of 39 SmartRF a CC1000 Package Description (TSSOP-28) Note: The figure is an illustration only. TSSOP 28 Min Max All dimensions in mm Thin Shrink Small Outline Package (TSSOP) D E1 E A A1 E B 0.19 9.60 4.30 0.05 6.40 0.65 0.30 9.80 4.50 1.20 0.15 L 0.45 Copl. 0 0.75 0.10 8 Soldering information Recommended soldering profile is according to CECC 00 802, Edition 3 Tape and reel specification Tape and reel is in accordance with EIA Specification 481. Package Tape Width TSSOP 28 16 mm Chipcon AS Tape and Reel Specification Component Hole Reel Pitch Pitch Diameter 8 mm 4 mm 13" SmartRFa CC1000 PRELIMINARY Datasheet (rev. 1.0) 2001-09-05 Units per Reel 4500 Page 38 of 39 SmartRF a CC1000 Ordering Information Ordering part number CC1000 CC1000/T&R CC1000DK CC1000SK Description Single Chip RF Transceiver Single Chip RF Transceiver CC1000 Development Kit CC1000 Sample Kit (5 pcs) MOQ 50 (tube) 4500 (tape and reel) 1 1 MOQ = Minimum Order Quantity Address: Chipcon AS Gaustadalleen 21 N-0349 Oslo, NORWAY Telephone Fax E-mail Web site : : : : (+47) 22 95 85 44 (+47) 22 95 85 46 wireless@chipcon.com http://www.chipcon.com General Information Chipcon AS believes the furnished information is correct and accurate at the time of this printing. However, Chipcon AS reserves the right to make changes to this product without notice. Chipcon AS does not assume any responsibility for the use of the described product. Please refer to Chipcon's web site for the latest update. SmartRFa is a registered trademark of Chipcon AS. SmartRF is Chipcon's RF technology platform with RF library cells, modules and design expertise. Based on SmartRF Chipcon develops standard component RF-circuits as well as full custom ASICs based on customers' requirements. Life Support Policy This Chipcon product is not designed for use in life support appliances, devices, or systems where malfunction can reasonably be expected to result in a significant personal injury to the user, or as a critical component in any life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. Chipcon AS customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Chipcon AS for any damages resulting from such improper use or sale. Chipcon AS SmartRFa CC1000 PRELIMINARY Datasheet (rev. 1.0) 2001-09-05 Page 39 of 39