1
Precision Edge®
SY89833L
Micrel, Inc.
M9999-082407
hbwhelp@micrel.com or (408) 955-1690
August 2007
DESCRIPTION
■Guaranteed AC performance over temperature
and voltage:
•DC-to > 2GHz throughput
•<600ps propagation delay (IN-to-Q)
•<20ps within-device skew
•<190ps rise/fall times
■Ultra-low jitter design
•<1psRMS cycle-to-cycle jitter
•<10psPP total jitter
•<1psRMS random jitter
•<10psPP deterministic jitter
■Unique input termination and VT pin accepts DC-
and AC-coupled inputs
■High-speed LVDS outputs
■3.3V power supply operation
■Industrial temperature range: –40°C to +85°C
■Available in 16-pin (3mm x 3mm) MLF® package
FEATURES
3.3V ULTRA-PRECISION 1:4 LVDS
FANOUT BUFFER/TRANSLATOR
WITH INTERNAL TERMINATION
Precision Edge®
SY89833L
APPLICATIONS
■Processor clock distribution
■SONET clock distribution
■Fibre Channel clock distribution
■Gigabit Ethernet clock distribution
1
The SY89833L is a 3.3V, high-speed 2GHz differential
Low Voltage Differential Swing (LVDS) 1:4 fanout buffer
optimized for ultra-low skew applications. Within device skew
is guaranteed to be less than 20ps over supply voltage and
temperature.
The differential input buffer has a unique internal
termination design that allows access to the termination
network through a VT pin. This feature allows the device to
easily interface to different logic standards. A VREF-AC
reference is included for AC-coupled applications.
The SY89833L is part of Micrel’s high-speed clock
synchronization family. For 2.5V applications, the SY89832U
provides similar functionality while operating from a 2.5V
±5% supply. For applications that require a different I/O
combination, consult the Micrel website at: www.micrel.com,
and choose from a comprehensive product line of high-
speed, low-skew fanout buffers, translators and clock
generators.
FUNCTIONAL BLOCK DIAGRAM TYPICAL PERFORMANCE
Precision Edge is a registered trademark of Micrel, Inc.
Micro
LeadFrame and MLF are registered trademarks of Amkor Technology, Inc.
622MHz Output
TIME (321.9ps/div.)
–15mV Offset
(50mV/div.)
IN
/IN
DQ
Q3
/Q3
Q2
/Q2
Q1
/Q1
Q0
/Q0
EN
(LVTTL/CMOS)
VT 50Ω
50Ω
VREF-AC
1:4
Precision Edge®
2
Precision Edge®
SY89833L
Micrel Inc.
M9999-082407
hbwhelp@micrel.com or (408) 955-1690
August 2007
PACKAGE/ORDERING INFORMATION
Ordering Information(1)
Package Operating Package Lead
Part Number Type Range Marking Finish
SY89833LMI MLF-16 Industrial 833L Sn-Pb
SY89833LMITR(2) MLF-16 Industrial 833L Sn-Pb
SY89833LMG(3) MLF-16 Industrial 833L with Pb-Free NiPdAu
bar line indicator Pb-Free
SY89833LMGTR(2, 3) MLF-16 Industrial 833L with Pb-Free NiPdAu
bar line indicator Pb-Free
Notes:
1. Contact factory for die availability. Dice are guaranteed at TA = 25°C, DC Electricals only.
2. Tape and Reel.
3. Pb-Free package is recommended for new designs.
Pin Number Pin Name Pin Function
15, 16 Q0, /Q0 LVDS Differential (Outputs): Normally terminated with 100Ω across the pair (Q, /Q). See “LVDS
1, 2 Q1, /Q1 Outputs” section, Figure 2a. Unused outputs should be terminated with a 100Ω resistor across
3, 4 Q2, /Q2 each pair.
5, 6 Q3, /Q3
8ENThis single-ended TTL/CMOS-compatible input functions as a synchronous output enable. The
synchronous enable ensures that enable/disable will only occur when the outputs are in a logic
LOW state. Note that this input is internally connected to a 25kΩ pull-up resistor and will default
to logic HIGH state (enabled) if left open.
9, 12 /IN, IN Differential Inputs: These input pairs are the differential signal inputs to the device. Inputs
accept AC- or DC-Coupled differential signs as small as 100mV. Each pin of a pair internally
terminates to a VT pin through 50Ω. Note that these inputs will default to an intermediate state if
left open. Pleae refer to the “Input Interface Applications” section for more details.
10 VREF–AC Reference Voltage: These outputs bias to VCC–1.4V. They are used when AC coupling the
inputs (IN, /IN). For AC-Coupled applications, connect VREF-AC to VT pin and bypass with
0.01µF low ESR capacitor to VCC. See “Input Interface Applications” section for more details.
Maximum sink/source current is ±1.5mA. Due to the limited drive capability, each VREF-AC pin
is only intended to drive its respective VT pin.
11 VT Input Termination Center-Tap: Each side of the differential input pair terminates to a VT pin. The
VT pins provide a center-tap to a termination network for maximum interface flexibility. See “Input
Interface Applications” section for more detaiils.
13 GND Ground. GND pins and exposed pad must be connected to the most negative potential of the
device ground.
7, 14 VCC Positive Power Supply: Bypass with 0.1µF//0.01µF low ESR capacitors and place as close to
each VCC pin as possible.
PIN DESCRIPTION
13141516
12
11
10
9
1
2
3
4
8765
Q1
/Q1
Q2
/
Q2
IN
VT
VREF-AC
/IN
/Q0
Q0
VCC
GND
Q3
/Q3
VCC
EN
16-Pin MLF® (MLF-16)
IN /IN EN Q /Q
01101
10110
XX00
(1) 1(1)
Note 1. On next negative transition of the input signal (IN).
TRUTH TABLE
3
Precision Edge®
SY89833L
Micrel, Inc.
M9999-082407
hbwhelp@micrel.com or (408) 955-1690
August 2007
Absolute Maximum Ratings(1)
Supply Voltage (VCC).................................. –0.5V to +4.0V
Input Voltage (VIN)...............................–0.5V to VCC +0.3V
LVDS Output Current (IOUT).....................................±10mA
Input Current
Source or Sink Current on (IN, /IN) ..................±50mA
VREF-AC Current
Source or Sink Current on (IVT) ..........................±2mA
Maximum Operating Junction Temperature .............. 125°C
Lead Temperature (Soldering, 20 sec.)..................... 260°C
Storage Temperature (TS) ....................... –65°C to +150°C
Operating Ratings(2)
Supply Voltage Range .............................. +3.0V to +3.60V
Ambient Temperature (TA).........................–40°C to +85°C
Package Thermal Resistance(3)
MLF® (θJA)
Still-Air .............................................................60°C/W
MLF® (ψJB)..........................................................33°C/W
TA = –40°C to +85°C, unless otherwise stated.
Symbol Parameter Condition Min Typ Max Units
VCC Power Supply Voltage Range 3.0 3.3 3.6 V
ICC Power Supply Current No load, max. VCC.75100 mA
RIN Input Resistance (IN-to-VT) 45 50 55 Ω
RDIFF-IN Differential Input Resistance 90 100 110 Ω
(IN-to-/IN)
VIH Input HIGH Voltage 0.1 VCC+0.3 V
(IN, /IN)
VIL Input LOW Voltage –0.3 VIH – 0.1 V
(IN, /IN)
VIN Input Voltage Swing Note 3, see Figure 2c. 0.1 VCC V
(IN, /IN)
VDIFF_IN Differential Input Voltage Note 3, see Figure 2d. 0.2 V
|IIN| Input Current 45 mA
IN, /IN
VREF–AC Reference Voltage Note 5 VCC–1.525 VCC–1.425 VCC–1.325 V
Notes:
1. Permanent device damage may occur if absolute maximum ratings are exceeded. This is a stress rating only and functional operation is not implied
at conditions other than those detailed in the operational sections of this data sheet. Exposure to absolute maximum ratlng conditions for extended
periods may affect device reliability.
2. The data sheet limits are not guaranteed if the device is operated beyond the operating ratings.
3. Package thermal resistance assumes exposed pad is soldered (or equivalent) to the device's most negative potential on the PCB. ψJB and θJA values
are determined for a 4-layer board in still-air number, unless otherwise stated.
4. The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established.
5. Due to the internal termination (see "Input Buffer Structure" section) the input current depends on the applied voltages at IN, /IN and VT inputs. Do
not apply a combination of voltages that causes the input current to exceed the maximum limit!
DC ELECTRICAL CHARACTERISTICS(4)
4
Precision Edge®
SY89833L
Micrel Inc.
M9999-082407
hbwhelp@micrel.com or (408) 955-1690
August 2007
VCC = 3.3V ±10%, RL = 100Ω across the outputs; TA = –40°C to +85°C
Symbol Parameter Condition Min Typ Max Units
VOUT Output Voltage Swing See Figure 2c. 250 325 mV
VDIFF_OUT Differential Output Voltage Swing See Figure 2d. 500 650 mV
VOCM Output Common Mode Voltage 1.125 1.275 V
∆VOCM Change in Common Mode Voltage –50 50 mV
VCC = 3.3V ±10%, TA = –40°C to +85°C
Symbol Parameter Condition Min Typ Max Units
VIH Input HIGH Voltage 2.0 VCC V
VIL Input LOW Voltage 0 0.8 V
IIH Input HIGH Current –125 30 µA
IIL Input LOW Current –300 µA
Note:
6. The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established.
LVDS OUTPUTS DC ELECTRICAL CHARACTERISTICS(6)
LVTTL/CMOS DC ELECTRICAL CHARACTERISTICS(6)
5
Precision Edge®
SY89833L
Micrel, Inc.
M9999-082407
hbwhelp@micrel.com or (408) 955-1690
August 2007
TIMING DIAGRAM
tS
IN
/Q
Q
tpd
tH
EN VCC/2 VCC/2
tpd
VIN
VOUT
/IN
VCC = +3.3V ±10%; RL = 100Ω across the outputs; TA = –40°C to +85°C unless otherwise stated.
Symbol Parameter Condition Min Typ Max Units
fMAX Maximum Frequency VOUT ≥ 200mV 2.0 GHz
tpd Propagation Delay IN-to-Q VIN < 400mV 400 500 600 ps
IN-to-Q VIN ≥400mV 330 440 530 ps
tSKEW Within-Device Skew Note 8 520ps
Part-to-Part Skew Note 9 200 ps
tSSet-Up Time EN to IN, /IN Note 10 300 ps
tHHold Time EN to IN, /IN Note 10 500 ps
tJITTER Data
Random Jitter (RJ) Note 11 1ps
RMS
Deterministic Jitter (DJ) Note 12 10 psPP
Clock
Cycle-to-Cycle Jitter Note 13 1ps
RMS
Total Jitter (TJ) Note 14 10 psPP
tr, tfOutput Rise/Fall Times At full output swing. 60 110 190 ps
(20% to 80%)
Notes:
7. High-frequency AC parameters are guaranteed by design and characterization.
8. Within device skew is measured between two different outputs under identical input transitions.
9. Part-to-part skew is defined for two parts with identical power supply voltages at the same temperature and no skew at the edges at the respective
inputs.
10. Set-up and hold times apply to synchronous applications that intend to enable/disable before the next clock cycle. For asynchronous applications,
set-up and hold times do not apply.
11. Random jitter is measured with a K28.7 pattern, measured at ≤fMAX.
12. Deterministic jitter is measured at 2.5Gbps with both K28.5 and 223–1 PRBS pattern.
13. Cycle-to-cycle jitter definition: The variation period between adjacent cycles over a random sample of adjacent cycle pairs. tJITTER_CC = Tn–Tn+1,
where T is the time between rising edges of the output signal.
14. Total jitter definition: with an ideal clock input frequency of ≤ fMAX (device), no more than one output edge in 1012 output edges will deviate by more
than the specified peak-to-peak jitter value.
AC ELECTRICAL CHARACTERISTICS(7)
6
Precision Edge®
SY89833L
Micrel Inc.
M9999-082407
hbwhelp@micrel.com or (408) 955-1690
August 2007
TYPICAL OPERATING CHARACTERISTICS
0
100
200
300
400
500
600
0 200 400 600 800
PROPAGATION DELAY (ps)
INPUT VOLTAGE SWING (mV)
Propagation Delay
vs. Input Voltage Swing
0
50
100
150
200
250
300
350
0 0.5 1 1.5 2 2.5
AMPLITUDE (mV)
FREQUENCY (GHz)
Output Swing
vs. Frequency
VCC = 3.3V, GND = 0V, VIN = 400mV, RL = 100Ω across the outputs, TA = 25°C, unless otherwise stated.
7
Precision Edge®
SY89833L
Micrel, Inc.
M9999-082407
hbwhelp@micrel.com or (408) 955-1690
August 2007
155MHz Output
TIME (1.29ns/div.)
–15mV Offset
(150mV/div.)
FUNCTIONAL CHARACTERISTICS
622MHz Output
TIME (321.9ps/div.)
–15mV Offset
(150mV/div.)
1GHz Output
TIME (200ps/div.)
–10mV Offset
(150mV/div.)
VCC = 3.3V, GND = 0V, VIN = 400mV, RL = 100Ω across the outputs; TA = 25°C, unless otherwise stated.
8
Precision Edge®
SY89833L
Micrel Inc.
M9999-082407
hbwhelp@micrel.com or (408) 955-1690
August 2007
INPUT STAGE
1.86k
9
GND
V
CC
/IN
1.86k
9
50
9
1.86k
9
1.86k
9
IN
V
T
50
9
Figure 1. Simplified Differential Input Buffer
LVDS OUTPUTS
LVDS specifies a small swing of 325mV typical, on a
nominal 1.20V common mode above ground. The common
100Ω
GND
vOUT
vOH, vOL vOH, vOL
Figure 2a. LVDS Differential Measurement
VOUT, VIN
325mV
(typical)
Figure 2c. Single-Ended Swing
50Ω
GND
vOCM,
∆vOCM
50Ω
Figure 2b. LVDS Common Mode Measurement
650mV
V
DIFF_IN,
V
DIFF_OUT
Figure 2d. Differential Swing
mode voltage has tight limits to permit large variations in
ground noise between an LVDS driver and receiver.
9
Precision Edge®
SY89833L
Micrel, Inc.
M9999-082407
hbwhelp@micrel.com or (408) 955-1690
August 2007
RELATED PRODUCT AND SUPPORT DOCUMENTS
INPUT INTERFACE APPLICATIONS
NC
CML IN
/IN
VTNC
SY89833L
V
CC
= 3.3V V
CC
= 3.3V
VREF-AC
Figure 3a. DC-Coupled CML
Input Interface
CML IN
/IN
VT
VCC = 3.3V VCC = 3.3V
VCC
SY89833L
VREF-AC
0.01µF
Figure 3b. AC-Coupled CML
Input Interface
LVPECL
IN
/IN
VT
VCC = 3.3V VCC = 3.3V
SY89833L
VREF-AC
VCC–2V
NC
50Ω
0.01µF
VCC
Figure 3c. DC-Coupled LVPECL
Input Interface
IN
/IN
VT
Rpd
100Ω
Rpd
100Ω
V
CC
= 3.3V V
CC
= 3.3V
SY89833L
VREF-AC
V
CC
0.01µF
LVPECL
Figure 3d. AC-Coupled LVPECL
Input Interface
NC
LVDS IN
/IN
VTNC
SY89833L
V
CC
= 3.3V V
CC
= 3.3V
VREF-AC
Figure 3e. LVDS
Input Interface
Part Number Function Data Sheet Link
SY89830U 2.5V/3.3V/5V 2.5GHz 1:4 PECL/ECL http://www.micrel.com/product-info/products/sy89830u.shtml
Clock Driver with 2:1 Differential Input MUX
SY89831U Ultra-Precision 1:4 LVPECL Fanout Buffer/ http://www.micrel.com/product-info/products/sy89831u.shtml
Translator with Internal Termination
SY89832U 2.5V Ultra-Precision 1:4 LVDS Fanout Buffer/ http://www.micrel.com/product-info/products/sy89832u.shtml
Translator with Internal Termination
SY89834U 2.5/3.3V Two Input, 1GHz LVTTL/CMOS-to-LVPECL http://www.micrel.com/product-info/products/sy89834u.shtml
1:4 Fanout Buffer/Translator
16-MLF® Manufacturing Guidelines
http://www.amkor.com/products/notes_papers/MLF_appnote_0301.pdf
Exposed Pad Application Note
HBW Solutions New Products and Termination App. Note http://www.micrel.com/product-info/as/solutions.shtml
10
Precision Edge®
SY89833L
Micrel Inc.
M9999-082407
hbwhelp@micrel.com or (408) 955-1690
August 2007
16-PIN EPAD MicroLeadFrame® (MLF-16)
Package
EP- Exposed Pad
Die
CompSide Island
Heat Dissipation
Heavy Copper Plane
Heavy Copper Plane
VEE
VEE
Heat Dissipation
PCB Thermal Consideration for 16-Pin MLF® Package
(Always solder, or equivalent, the exposed pad to the PCB)
Package Notes:
1. Package meets Level 2 moisture sensitivity classification, and are shipped in dry-pack form.
2. Exposed pads must be soldered to a ground for proper thermal management.
MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA
TEL + 1 (408) 944-0800 FAX + 1 (408) 474-1000 WEB http://www.micrel.com
The information furnished by Micrel in this datasheet is believed to be accurate and reliable. However, no responsibility is assumed by Micrel for its use.
Micrel reserves the right to change circuitry and specifications at any time without notification to the customer.
Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can
reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant into
the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A Purchaser’s
use or sale of Micrel Products for use in life support appliances, devices or systems is at Purchaser’s own risk and Purchaser agrees to fully indemnify
Micrel for any damages resulting from such use or sale.
© 2005 Micrel, Incorporated.
