ky SGS-THOMSON Sf ucRoELecrRoMICS M8438A SERIAL INPUT LCD DRIVER DRIVES UP TO 32 LCD SEGMENTS a DATA TRANSFER : FIXED ENABLE MODE FOR DIP-40, ENABLE AND LATCH-MODE FOR 44PLCC s INPUTS ARE CMOS, NMOS AND TTL COMPA- TIBLE B c a CASCADABLE DIP-40 44 PLCC a REQUIRES ONLY 3 CONTROL LINES (Plastic) (Plastic Chip Carrier) a ON CHIP OSCILLATOR ORDER CODE : M8438A_ DIE 1 s CMOS TECHNOLOGY FOR WIDE SUPPLY M8438A B6 VOLTAGE RANGE M8438A C6 = 40 TO 85 C TEMPERATURE RANGE PIN CONNECTIONS "pp 1 V so) cock t 2 39) SEG 5 SEG 22 9 3 3a) Sec2 SEG H J 37) SEGI SEG 309 5 YN Veg SEG 294 6 3p 00 SEG zal 7 Pp oF SEG 27] 8 33) SEG4 SEG 269 9 322) SEG 5 SEG 2510 HD ose secagu 300 ap SEG 23412 25) secs SEG 77413 26) SEG7 SEG 2191s 270 seca DESCRIPTION SEG 20015 260) SEGS The M8438A is a CMOS integrated circuit that drives ste ed . pace an LCD dispiay, usually under microprocessor 56617 doa ah seow control. The part acts as a smart peripheral that Se 1 19 27) seo13 drives up to 32 LCD segments. It needs only three sec 15 qz0 2p seo contro! lines due to its serial input construction. It latches the data to be displayed and relieves the microprocessor from the task of generating the re- quired waveforms. The M8438A can drive any standard or custom pa- ralle! drive LCD whether it be field effect or dynamic scattering. Several drivers can be cascaded, if more than 32 segments are to be driven. The AC frequen- cy of the LCD waveforms can be supplied by the user or can be generated by attaching a capacitor to the OSC input which determines the frequency of an internal oscillator. The M8438A is available in DIE form and assem- bled in 40 pin dual-in line plastic or 44 PLCC packages. 5-605 September 1988 1/7 705M8438A BLOCK DIAGRAM osc. O LCD AC GENERATOR O BP [sone OUTPUTS > SEG. g | 6 32 SEGMENT DRIVERS 32 LATCHES EL O_+ LATCH crock O-_{_ MODE CONTROL I sR CLOCK MS O+ pi O 32 BIT STATIC SHIFT REG. F}O DO POR S 8307 OSC : Oscillator (capacitor or drive signal) DO: Serial data output EL: Enable / Latch control input BP: Backplane output MS: Mode select input (not available in 40 Pin DIL) SEG : Segment output signal DI : Serial data input 2/7 706 ky SGS-THOMSON I Seem icrmamncsABSOLUTE MAXIMUM RATINGS M8438A Symbol Parameter Value Unit (Vpp-Vss) | Supply Voltage 0.3 to+12 Vv Vv) Input Voltage Vss 0.3 to Vop + 0.3 Vv Vo Output Voltage Vss 0.3 to Vop + 0.3 Vv Pp Power Dissipation 250 mw Tstg Storage Temperature - 55 to + 125 C Ta Operating Temperature 40 to + 85 C Stresses in excess of those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions in excess of those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (Tamp = 25 C and Vpp = 5 V unless otherwise noted) [Symbol | Parameter Test conditions l Min. | Max. | Unit | STATIC ELECTRICAL CHARACTERISTICS Vppb Supply Voltage 3 10 Vv lbp Supply Current Oscillator f < 15 kHz 60 HA la Quiescent Current Vpp = 10 V 10 pA Vin Input High Level 5 Vop Voo Vv Vii__| Input Low Level jor 0 2Voo| Vv lin Input Current EL +5 HA Ci Input Capacitance 5 pF Vin Input High Level Driven Mode 9 Voo Vv Vit Input Low Level }ose Driven Mode 1 Vop Vv lin Input Current Driven Mode +10 A Ron Segment Output Impedance ht= 10 pA 40 kQ Ron Backplane Output IL = 100 pA 3 kQ Impedance Vorr | Output Offset Voltage C_ = 250 pF between Each + 50 mV SEG Output and BP Ron Data Output Impedance IL = 100 pA 3 kQ DYNAMIC ELECTRICAL CHARACTERISTICS ttr Transition Time OSC Driven Mode 500 ns tsp Data Set-up Time Fig. 1 and 2 150 ns tHD Data Hold Time Fig. 1 and 2 50 ns tse EL Set-up Time Fig. 1 100 ns tHe EL Hold Time Fig. 1 100 ns twe EL Pulse Width Fig. 2 175 ns* tce Clock to EL Time Fig. 2 250 ns tog DO Propagation Delay Fig. 1,2;C,_ =55 pF 500 ns f Clock Rate Vop = 10 50 % Duty Cycle ; DC 15 MHz L577 SGS:THOMsoN 37 MICROELECTRONICS 707M8438A FONCTIONAL DESCRIPTION LCD-AC-Generator This block generates a 50 % duty cycle signal for the backplane output. The circuit can be used in two dif- ferent modes : oscillator or driven. OSCILLATOR MODE : In this mode the backplane frequency is determined by the internal RC oscilla- tor together with an 8-stage frequency divider. For generating the backplane output signal of 50 % du- ty cycle the oscillator frequency is divided by 256. The RC oscillator requires an external capacitor to be connected between input OSC and Vss. A value of 18 pF gives a backplane frequency of 80 Hz + 30 % at Vop = 5 V. The variation of the backplane frequency over the entire temperature and supply voltage range is + 50 %. DRIVEN MODE : In this mode the signal at the back- plane output BP is in phase with an external driving signal applied to input OSC. This mode is used to synchronize the LCD drive of two or more cascaded driver circuits. DETECTION LOGIC The circuitis able to distinguish between the conditions for oscillator or driven mode. If the circuit is to be in the oscillator mode, the OSC pin has a capacitor connected to it. The oscillator will start as soon as the supply voltage exceed a certain minimum value. The signal at pin OSC swings within a range from 0.3 Vpp to 0.7 Vpp. If the circuit is to be in the driven mode, the OSC pin has to be forced to logic levels by an external source. The transition time between the logic ievels must be short, so that the circuit does not react on the voltage level in be- tween. In the driven mode the 8-stage frequency di- vider is by-passed. Segment outputs A logic 0 at the data input DI causes a segment out- put signal to be in phase with the backplane signal and turns the segment off. A logic 1 causes a seg- ment output to be in opposite phase to the backplane signal and turns the segment on. Microprocessor interface The circuit can operate in two different data transfer modes : Enable mode and latch mode. One of either mode can be chosen with the mode select input MS. An internal pull up device is provided between this input and Vpp. Enable mode is selected if MS is left open or connected to Vpp. Latch mode is selected if MS is connected to Vss. The input MS is not available, if the device is as- sembled in the 40 pin package, and is internally fixed to operate in ENABLE MODE. 47 L577 SGS:THOMSON ENABLE MODE Fig. 3 shows a timing diagram o' the enable mode. Data is serially shifted in and ou of the shift register on the negative transition of the clock. Serial entry into the shift register is permittec when the enable/latch control EL is high. When El is low it causes the shift register clock to be inhibi ted and the content of the shift register to be loadec into the latches that control the segment drivers. LATCH MODE Fig. 4 shows a timing diagram of the latch mode. Data is serially shifted in and out of the shift register on the negative transition of the clock Serial entry into the shift register is permitted inde pendently of the enable/latch control EL. When EL is high it causes a parallel load of the content in the shift register into the latches. It is acceptable to lie the EL line high. Then the latches are transparen and only two lines, clock and data input, would ther be needed for data transfer. Power-on logic A power on reset pulse is generated internally wher the supply voltage is being turned on. The genera tion of the reset pulse is level dependent and will oc cur even on a slowly rising supply voltage. The po wer on reset pulse resets all shift register stages anc the latches that control the segment drivers. There fore all segment outputs are initially in phase witt the backplane output. This causes the display to be blanked and no arbitrary data to show up. Thi: condition is maintained until data is shifted into the register and loaded into the latches. CONDITIONS FOR POWER-ON RESET FUNC. TION ; The POR circuit triggers on the rising slope of the positive supply voltage Vpp. A reset pulse wil be generated, if conditions a) through d) are given a) Level er Rising slope from VitoV2 fe v V1 max=0.5V V2 min = 3.0 V Yow b) Rise time tr min = 10 us , TTT Ow tpmax=15 bal tp c) Rise function "ow The function of Vpp between t1 and t2 may be nonlinear, but should not show a maximum and should not exceed 0.25 Vius. d) Recovery time The minimum time between turn-off and turn-on of Vpop is 1s. MICROELECTRONICS 708FONCTIONAL DESCRIPTION (continued) Cascade configuration SeveralLCD drivers can be cascaded if a liquid crys- tal display with more than 32 segments is to be connected. The phase correlation between all segment outputs is achieved by using the second (and any other) de- vice in the driven mode. M8438A Two different cascade configurations can be cho- sen depending whether the LCD frequency is to be determined by the internal RC oscillator or by an ex- ternal signal. Figure 3 shows the connection scheme for a self os- cillating configuration, figure 4 shows the connec- tion of an externally controlled one. Figure 1 : Timing Diagram of Enable Mode : Set-up and Hold Time. CLOCK Sf \__ ---./ YX ENABLE /LATCH tse tHE be DATA IN tso | tHo DATA OUT x _ t pd _e $-8310/1 Figure 2 : Timing Diagram of Latch Mode : Set-up and Hold Time. tce CLOCK S/S \__ ---- ENABLESLATCH (ee ; K We DATA IN DATA OUT _ xX tod 5-311 57 S&S:THOMsON ll MICROELECTRONICS 709M8438A Figure 3 : Timing Diagram of Enable Mode : Serial Load into SR and Parallel Transfer to LCD. ENABLE? LATCH / \ ' cvoen LLL ELLE nate in Con _| SEGMENTS / \ / \ / \ J \ / x x S-82/1 Figure 4 : Timing Diagram of Latch Mode : Serial Load into SR and Parallel Transfer to LCD. ENABLE/ LATCH A \ CLOCK Ut TET DATA IN Pitt TTT TT | BACKPLANE 7 ee A eee A ee A ee S-BU13N 6/7 ka7 SGS-THOMSO Tf SS THOMSON 710Figure 5 : Cascade Configuration, Self Oscillating. M8438A DEVICE 1 DEVICE 2 LCD [L! osc BP v Osc BP BP q i 4 L ; DEVICE n ' LeJ osc BP/-O NC S- 83146 Figure 6 : Cascade Configuration, Drive by External Signal. DEVICE 1 LCD LCO DRIVING osc BP BP SIGNAL DEVICE 2 Osc BP}ONC 1 I 1 DEVICE n 1 Ls ose BpL- -ONC 5- 8364 77 ky SGS-THOMSON 7 sickomeciromes 7114