General Description
The MAX1761 dual pulse-width-modulation (PWM),
step-down controller provides high efficiency, excellent
transient response, and high DC output accuracy in an
extremely compact circuit topology. These features are
essential for stepping down high-voltage batteries to
generate low-voltage CPU core, I/O, and chipset RAM
supplies in PC board area critical applications, such as
notebook computers and smart phones.
Maxim’s proprietary Quick-PWM™ quick-response,
constant-on-time PWM control scheme handles wide
input/output voltage ratios with ease and provides
“instant-on” response to load transients while maintain-
ing a relatively constant switching frequency.
The MAX1761 achieves high efficiency at reduced cost
by eliminating the current-sense resistor found in tradi-
tional current-mode PWMs. Efficiency is further
enhanced by its ability to drive large synchronous-recti-
fier MOSFETs. The MAX1761 employs a complemen-
tary MOSFET output stage, which reduces component
count by eliminating external bootstrap capacitors and
diodes.
Single-stage buck conversion allows this device to
directly step down high-voltage batteries for the highest
possible efficiency. Alternatively, two-stage conversion
(stepping down the +5V system supply instead of the
battery) at a higher switching frequency allows the mini-
mum possible physical size.
The MAX1761 is intended for CPU core, chipset,
DRAM, or other low-voltage supplies. The MAX1761 is
available in a 16-pin QSOP package. For applications
requiring greater output power, refer to the MAX1715
data sheet. For a single-output version, refer to the
MAX1762/MAX1791 data sheet.
________________________Applications
Notebooks and PDAs
Digital Cameras
Handy-Terminals
Smart Phones
1.8V/2.5V Logic and I/O Supplies
Features
Free-Running On-Demand PWM
Selectable Light-Load Pulse-Skipping Operation
±1% Total DC Error in Forced-PWM Mode
5V to 20V Input Range
Flexible Output Voltages
OUT1: Dual Mode™ Fixed 2.5V or 1V to 5.5V
Adjustable
OUT2: Dual Mode Fixed 1.8V or 1V to 5.5V
Adjustable
Output Undervoltage Protection
Complementary Synchronous Buck
No Current-Sense Resistor
4.65V at 25mA Linear Regulator Output
4µA V+ Shutdown Supply Current
5µA VL Shutdown Supply Current
950µA Quiescent Supply Current
Tiny 16-Pin QSOP Package
MAX1761
Small, Dual, High-Efficiency
Buck Controller for Notebooks
________________________________________________________________ Maxim Integrated Products 1
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
FB1 DH1
CS1
DL1
VL
GND
DL2
CS2
DH2
TOP VIEW
MAX1761
QSOP
OUT1
REF
ON1
ON2
V+
OUT2
FB2
Pin Configuration
19-1835; Rev 0; 10/00
For price, delivery, and to place orders, please contact Maxim Distribution at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
EVALUATION KIT
AVAILABLE
Ordering Information
16 QSOP
PIN-PACKAGETEMP. RANGE
-40°C to +85°CMAX1761EEE
PART
Quick-PWM and Dual Mode are trademarks of
Maxim Integrated Products.
MAX1761
Small, Dual, High-Efficiency
Buck Controller for Notebooks
2 _______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
(Circuit of Figure 1, V+ = 15V, CVL = 4.7µF, CREF = 0.1µF, VL not externally driven unless otherwise noted, TA= 0°C to +85°C, unless
otherwise noted.) (Note 1)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
V+ to GND ..............................................................-0.3V to +22V
VL to GND ................................................................-0.3V to +6V
VL to V+ .............................................................................+0.3V
OUT_, ON2 to GND ..................................................-0.3V to +6V
ON1, DH_ to GND ........................................-0.3V to (V+ + 0.3V)
FB_, REF, DL_ to GND.................................-0.3V to (VL + 0.3V)
CS_ to GND .....................................................-2V to (V+ + 0.3V)
REF Short Circuit to GND ...........................................Continuous
Continuous Power Dissipation
16-Pin QSOP (derate 8.3mW/°C above +70°C) ......….667mW
Operating Temperature Range ...........................-40°C to +85°C
Junction Temperature......................................................+150°C
Storage Temperature.........................................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
PWM CONTROLLERS
Input Voltage Range V+ (Note 2) 4.5 20 V
FB_ = OUT_ 0.99 1 1.01
FB1 = GND 2.475 2.5 2.525 V
DC Output Voltage Accuracy
(Note 3) VOUT_
V+ = 4.5V to 20V,
VL = 4.75V to 5.25V,
ON2 = VL FB2 = GND 1.782 1.8 1.818
Output Voltage Adjust Range 1 5.5 V
OUT_ Input Resistance 80 160 300 k
FB_ Input Bias Current VFB_ = 1V, VL = 5V -0.1 0.1 µA
CS_ Input Bias Current VCS_ = 0, VL = 5V -1 1 µA
Soft-Start Ramp Time Zero to full ILIM 1700 µs
OUT1 661 735 809
On-Time (Note 4) tON V+ = 10V, VOUT1 = 2.5V,
VOUT2 = 1.8V OUT2 648 720 792 ns
Minimum Off-Time (Note 4) tOFF 400 500 ns
BIAS AND REFERENCE
IL FB1 = FB2 = GND, VL = 5V, VOUT1 and
VOUT2 forced above regulation point 0.60 1.20 mA
VL undriven 0.95 1.70
Quiescent Supply Current
I+
FB1 = FB2 = GND, VOUT1
and VOUT2 forced
above regulation point VL = 5V 0.38 0.65
mA
IL VL = 5V, ON1 = ON2 = GND 5 10 µA
Shutdown Supply Current I+ VL = 0, 5V 4 10 µA
VL Output Voltage VL ILOAD = 0 to 25mA, V+ = 5V to 20V 4.5 4.65 4.75 V
Reference Voltage VREF V+ = 5V to 20V, no load 1.98 2 2.02 V
Reference Load Regulation IREF IREF = 0 to 50µA 8 mV
REF Sink Current REF in regulation 10 µA
Falling edge 1.6
REF Fault Lockout Voltage Rising edge 1.94 V
MAX1761
Small, Dual, High-Efficiency
Buck Controller for Notebooks
_______________________________________________________________________________________ 3
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
FAULT PROTECTION
Output Undervoltage Threshold
(Foldback) VFB
,
UVFB With respect to the regulation point, no load 60 70 80 %
Output Undervoltage Blanking
Time VFB
,
UVLO
(
t
)
Measured from ON_ signal going high 10 32 ms
GND - CS_, positive direction 92 100 108
GND - CS_, negative direction, ON2 = floating -135 -120 -105
Current-Limit Threshold
GND - CS_, zero crossing, ON2 = 5V 2.5
mV
Thermal Shutdown Threshold Hysteresis = 10oC 160 oC
VL Undervoltage Lockout
Threshold VVL
,
UVLO Rising edge, hysteresis = 20mV, PWM is
disabled below this voltage 4.1 4.4 V
GATE DRIVERS
DH_ Gate Driver On-Resistance
(Pullup) V+ = 6V to 20V, DH_, high state 3.7 8
DH_ Gate Driver On-Resistance
(Pulldown) DH_, low state 6.2 10
DL_ Gate Driver On-Resistance
(Pullup) DL_ , high state 3.4 8
DL_ Gate Driver On-Resistance
(Pulldown) DL_, low state 2.0 5
DH_ Gate Driver Source/Sink
Current VDH_ = 3V, V+ = 6V 0.6 A
DL_ Gate Drive Sink Current VDL_ = 2.5V 0.9 A
DL_ Gate Drive Source Current VDL_ = 2.5V 0.5 A
LOGIC CONTROLS
ON_ Logic Input High Voltage 2.05 V
ON2 Logic Input Float Voltage
(Forced-PWM Mode) 2.0V < VON1 < VL 1.3 1.7 1.95 V
ON_ Logic Input Low Voltage 0.5 V
ON1 Logic Input Current -1 1 µA
ON2 Logic High Input Current VON2 > 2.0V 0 1 3 µA
ON2 Logic Low Input Current VON2 < 0.5V, VON1 > 2.0V -2 -1 0 µA
FB_ Dual Mode Threshold 50 100 150 mV
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 1, V+ = 15V, CVL = 4.7µF, CREF = 0.1µF, VL not externally driven unless otherwise noted, TA= 0°C to +85°C, unless
otherwise noted.) (Note 1)
MAX1761
Small, Dual, High-Efficiency
Buck Controller for Notebooks
4 _______________________________________________________________________________________
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
PWM CONTROLLERS
V+ (Note 2) 4.5 20 V
Input Voltage Range VL VL externally driven (Note 2) 4.75 5.25
FB_ = OUT_ 0.99 1.01
FB1 = GND 2.475 2.525 V
DC Output Voltage Accuracy
(Note 3) VOUT_
V+ = 4.5V to 20V,
VL = 4.75V to 5.25V,
ON2 = VL FB2 = GND 1.782 1.818
Output Voltage Adjust Range 1 5.5 V
OUT_ Input Resistance 80 300 k
FB_ Input Bias Current VFB_ = 1V, VL = 5V -0.1 0.1 µA
CS_ Input Bias Current VCS_ = 0, VL = 5V -1 1 µA
Soft-Start Ramp Time Zero to full ILIM µs
OUT1 661 809
On-Time (Note 4) tON V+ = 10V, VOUT1 = 2.5V,
VOUT2 = 1.8V OUT2 648 792 ns
Minimum Off-Time (Note 4) tOFF Above regulation point 500 ns
BIAS AND REFERENCE
IL FB1 = FB2 = GND, VL = 5V, VOUT1 and
VOUT2 forced above regulation point 1.2 mA
VL undriven 1.7
Quiescent Supply Current
I+
FB1 = FB2 = GND, VOUT1
and VOUT2 forced above
regulation point VL = 5V 0.5
mA
IL VL = 5V, ON1 = ON2 = GND 10 µA
Shutdown Supply Current I+ VL = 0, 5V 10 µA
VL Output Voltage VL ILOAD = 0 to 25mA, V+ = 5V to 20V 4.5 4.75 V
Reference Voltage VREF V+ = 5V to 20V, no load 1.98 2.02 V
Reference Load Regulation IREF IREF = 0 to 50µA 8 mV
REF Sink Current REF in regulation 10 µA
FAULT PROTECTION
Output Undervoltage Threshold
(Foldback) VFB
,
UVFB With respect to the regulation point, no load 60 80 %
Output Undervoltage Lockout
Timer VFB
,
UVLO
(
t
)
Measured from ON_ signal going high 10 32 ms
GND CS_, positive direction 92 108
Current-Limit Threshold GND CS_, negative direction, ON2 = floating -135 -105 mV
VL Undervoltage Lockout
Threshold VVL
,
UVLO Rising edge, hysteresis = 20mV, PWM is
disabled below this voltage 4.1 4.4 V
ELECTRICAL CHARACTERISTICS
(Circuit of Figure 1, V+ = 15V, CVL = 4.7µF, CREF = 0.1µF, VL not externally driven unless otherwise noted, TA= -40°C to +85°C,
unless otherwise noted.) (Note 1)
MAX1761
Small, Dual, High-Efficiency
Buck Controller for Notebooks
_______________________________________________________________________________________ 5
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
GATE DRIVERS
DH_ Gate Driver On-Resistance
(Pullup) V+ = 6V to 20V, DH_, high state 8
DH_ Gate Driver On-Resistance
(Pulldown) DH_, low state 10
DL_ Gate Driver On-Resistance
(Pullup) DL_, high state 8
DL_ Gate Driver On-Resistance
(Pulldown) DL_, low state 5
DH_ Gate Driver Source/Sink
Current VDH_ = 3V, V+ = 6V A
DL_ Gate Drive Sink Current VDL_ = 2.5V A
DL_ Gate Driver Source Current VDL_ = 2.5V A
LOGIC CONTROLS
ON_ Logic Input High Voltage 2.05 V
ON2 Logic Input Float Voltage
(Forced-PWM Mode) VON1 > 2.0V 1.3 1.95 V
ON_ Logic Input Low Voltage 0.5 V
ON1 Logic Input Current -1 1 µA
ON2 Logic High Input Current VON2 > 2.0V 0 3 µA
ON2 Logic Low Input Current VON2 < 0.5V, VON1 > 2.0V -2 0 µA
FB_ Dual Mode Threshold 50 150 mV
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 1, V+ = 15V, CVL = 4.7µF, CREF = 0.1µF, VL not externally driven unless otherwise noted, TA= -40°C to +85°C,
unless otherwise noted.) (Note 1)
Note 1: Specifications to -40°C are guaranteed by design, not production tested.
Note 2: If V+ is less than 5V, V+ must be connected to VL. If VL is connected to V+, V+ must be between 4.5V and 5.5V.
Note 3: DC output accuracy specifications refer to the trip-level error of the error amplifier. The output voltage will have a DC regula-
tion higher than the trip level by 50% of the ripple. In PFM mode, the output will rise by approximately 1.5% when transition-
ing from continuous conduction to no load.
Note 4: One-shot times are measured at the DH pin (V+ = 15V, CDH = 400pF, 90% point to 90% point). Actual in-circuit times may
be different due to MOSFET switching speeds.This effect can also cause the switching frequency to vary.
MAX1761
Small, Dual, High-Efficiency
Buck Controller for Notebooks
6 _______________________________________________________________________________________
Typical Operating Characteristics
(TA = +25°C, unless otherwise noted.)
100
0
1 10 100 1000 10,000
EFFICIENCY vs. LOAD CURRENT
(VOUT = 2.5V, SKIP MODE)
20
MAX1761 toc01
LOAD CURRENT (mA)
EFFICIENCY (%)
40
60
80
70
50
30
10
90 V+ = +5V = VL
V+ = +18V
V+ = +7V
V+ = +12V
100
0
1 10 100 1000 10,000
EFFICIENCY vs. LOAD CURRENT
(3.3V, SKIP MODE)
20
MAX1761 toc05
LOAD CURRENT (mA)
EFFICIENCY (%)
40
60
80
70
50
30
10
90
V+ = +5V = VL
V+ = +7V
V+ = +12V
V+ = +18V
100
0
1 10 100 1000 10,000
EFFICIENCY vs. LOAD CURRENT
(3.3V, PWM MODE)
20
MAX1761 toc06
LOAD CURRENT (mA)
EFFICIENCY (%)
40
60
80
70
50
30
10
90 V+ = +5V = VL
V+ = +7V
V+ = +12V
V+ = +18V
0
100
50
200
150
300
250
350
0 800400 1200 1600 2000
FREQUENCY vs. LOAD CURRENT
MAX1761 toc08
LOAD CURRENT (mA)
FREQUENCY (kHz)
SKIP MODE
PWN MODE
VOUT = + 2.5V
VOUT = + 1.8V
VOUT = + 2.5V
VOUT = + 1.8V
-0.45
-0.35
-0.40
-0.20
-0.25
-0.30
-0.05
-0.10
-0.15
0
010155 20253035
VL VOLTAGE vs. OUTPUT CURRENT
MAX1761 toc09
VL CURRENT (mA)
VL ERROR (%)
VOUT1 = 2.5V, IOUT1 = 2A,
VOUT2 = 1.8V, IOUT2 = 2A
100
0
1 10 100 1000 10,000
EFFICIENCY vs. LOAD CURRENT
(1.8V, PWM MODE)
20
MAX1761 toc04
LOAD CURRENT (mA)
EFFICIENCY (%)
40
60
80
70
50
30
10
90
V+ = +5V = VL
V+ = +7V
V+ = +12V
V+ = +18V
100
0
1 10 100 1000 10,000
EFFICIENCY vs. LOAD CURRENT
(2.5V, SKIP MODE, 3.5A COMPONENTS)
20
MAX1761 toc07
LOAD CURRENT (mA)
EFFICIENCY (%)
40
60
80
70
50
30
10
90 V+ = +5V
V+ = +7V
V+ = +12V
V+ = +18V
100
0
1 10 100 1000 10,000
EFFICIENCY vs. LOAD CURRENT
(1.8V, SKIP MODE)
20
MAX1761 toc03
LOAD CURRENT (mA)
EFFICIENCY (%)
40
60
80
70
50
30
10
90
V+ = +18V
V+ = +12V
V+ = +7V
V+ = +5V = VL
MAX1761
Small, Dual, High-Efficiency
Buck Controller for Notebooks
_______________________________________________________________________________________ 7
Typical Operating Characteristics (continued)
(TA = +25°C, unless otherwise noted.)
0
0.1
0.3
0.2
0.5
0.6
0.4
0.7
4.5 8.5 10.56.5 12.5 14.5 16.5 18.5 20.5
SUPPLY CURRENT vs. INPUT VOLTAGE
(SKIP MODE)
MAX1761 toc10
INPUT VOLTAGE (V)
SUPPLY CURRENT (mA)
ON1 = VL, ON2 = VL
NO LOAD
C
B
A
20 µs/div
LOAD-TRANSIENT RESPONSE
(2.5A COMPONENTS, VOUT = 1.8V)
MAX1761 toc14
A: VOUT, AC-COUPLED, 5mV/div
B: INDUCTOR CURRENT, 1A/div
C: DL1, 5V/div
C
B
OUTPUT OVERLOAD WAVEFORMS
(IOUT = 4V, VOUT = 2.5V)
MAX1761 toc15
A: VOUT, 1V/div
B: INDUCTOR CURRENT, 2A/div
C: DL1, 2V/div
A
100 µs/div
C
B
A
STARTUP AND SHUTDOWN WAVEFORMS
(VOUT = 2.5V)
MAX1761 toc17
A: VOUT, 2V/div
B: INDUCTOR CURRENT, 2A/div
C: DL1, 5V/div
500 µs/div
C
B
A
20 µs/div
LOAD-TRANSIENT RESPONSE
(2.5A COMPONENTS, VOUT = 2.5V)
MAX1761 toc13
A: VOUT, AC-COUPLED, 10mV/div
B: INDUCTOR CURRENT, 1A/div
C: DL1, 5V/div
C
B
A
STARTUP AND SHUTDOWN WAVEFORMS
(VOUT = 1.8V)
MAX1761 toc16
A: VOUT, 2V/div
B: INDUCTOR CURRENT, 2A/div
C: DL1, 5V/div
500 µs/div
0
5
10
15
20
25
30
4.5 8.56.5 10.5 12.5 14.5 16.5 18.5 20.5
SUPPLY CURRENT vs. INPUT VOLTAGE
(PWM MODE)
MAX1761 toc11
INPUT VOLTAGE (V)
SUPPLY CURRENT (mA)
ON1 = VL, ON2 = FLOAT
NO LOAD
0
2
1
4
3
5
6
7
8
4.5 8.5 10.56.5 12.5 14.5 16.5 18.5 20.5
NO-LOAD SUPPLY CURRENT vs.
INPUT VOLTAGE (SHUTDOWN)
MAX1761 toc12
INPUT VOLTAGE (V)
SUPPLY CURRENT (µA)
ON1 = GND, 0N2 = VL
MAX1761
Small, Dual, High-Efficiency
Buck Controller for Notebooks
8 _______________________________________________________________________________________
PIN NAME FUNCTION
1 FB1 Feed b ack Inp ut for the 2.5V P WM . C onnect FB1 to GN D for a fi xed 2.5V outp ut. C onnect a r esi sti ve
vol tag e- d i vi d er to FB1 to ad j ust OU T1 fr om 1V to 5.5V . FB1 r eg ul ates to 1V ( see Ad j usti ng V
OUT secti on) .
2 OUT1 Output Voltage Connection for PWM1. OUT1 senses the output voltage to set the regulator on-time
and is connected internally to a 160k feedback input in fixed-output mode.
3 REF 2V Reference Voltage Output. Bypass REF to GND with 0.1µF (min) capacitor. Can supply 50µA for
external loads.
When ON1 = High, Normal/Forced PWM Mode Selection and OUT2 On/Off Control Input
ON2 CONDITION MODE SELECTED
LOW (ON2 < 0.5V) OUT1 is enabled in normal mode; OUT2 is shut down.
HIGH (2V < ON2 < VL) Both outputs are enabled in normal mode.
4 ON2
Floating Both outputs are enabled in forced-PWM mode.
5V+
Battery Voltage. V+ is the input for the VL regulator and DH gate drivers and is also used for PWM
one-shot timing.
6 ON1 On/Off Control Input. Drive ON1 high to enable the device. Drive ON1 low to enter micropower
shutdown mode. Both REF and VL are disabled in shutdown. ON1 may be pinstrapped to V+.
7 OUT2 Output Voltage Connection for PWM2. OUT2 senses the output voltage to set the regulator on-time
and is connected internally to a 160k feedback input in fixed-output mode.
8 FB2 Feed b ack Inp ut for the 1.8V P WM . C onnect FB2 to GN D for a fi xed 1.8V outp ut. C onnect a r esi sti ve
vol tag e- d i vi d er to FB2 to ad j ust OU T2 fr om 1V to 5.5V . FB2 r eg ul ates to 1V ( see Ad j usti ng V
OU T
secti on) .
9 DH2 High-Side Gate Driver Output for PWM2. Swings between GND and V+.
10 CS2 Current-Sense Connection for PWM2. Connect CS2 to the drain of the low-side driver. Alternatively,
connect CS2 to the junction of the source of the low-side FET and a current-sense resistor to GND.
11 DL2 Low-Side Gate Driver Output for PWM2. DL2 swings between GND and VL.
12 GND Combined Power and Analog Ground
13 VL
Linear Regulator Output. VL is the output of the 4.65V internal linear regulator, capable of supplying
25mA for external loads. The VL pin also serves as the supply input for the DL gate driver and the
analog/logic blocks. VL can be overdriven by an external 5V supply to improve efficiency. Bypass
VL to GND with a 4.7µF ceramic capacitor.
14 DL1 Low-Side Gate Driver Output for PWM1. DL1 swings between GND and VL.
15 CS1 Current-Sense Connection for PWM1. Connect CS1 to the drain of the low-side driver. Alternatively,
connect CS1 to the junction of the source of the low-side FET and a current-sense resistor to GND.
16 DH1 High-Side Gate Driver Output for PWM1. DH1 swings between GND and V+.
Pin Description
MAX1761
Small, Dual, High-Efficiency
Buck Controller for Notebooks
_______________________________________________________________________________________ 9
Typical Application Circuit
The typical application circuit in Figure 1 generates two
low-voltage rails for general-purpose use in notebook
and subnotebook computers (I/O supply, fixed CPU
core supply, DRAM supply). This DC-DC converter
steps down a battery or AC adapter voltage to voltages
from 1.0V to 5.5V with high efficiency and accuracy.
See Table 1 for a list of components for common appli-
cations. Table 2 lists component manufacturers.
Detailed Description
The MAX1761 dual buck controller is designed for low-
voltage power supplies in notebook and subnotebook
computers. Maxims proprietary Quick-PWM pulse-
width modulation circuit (Figure 2) is specifically
designed for handling fast load steps while maintaining
a relatively constant operating frequency over a wide
range of input voltages. The Quick-PWM architecture
circumvents the poor load-transient timing problems of
fixed-frequency current-mode PWMs while preventing
problems caused by widely varying switching frequen-
cies in conventional constant-on-time and constant-off-
time PWM schemes.
This MAX1761 controls two synchronously rectified out-
puts with complementary N- and P-channel MOSFETs.
Using the P-channel for the high-side MOSFET elimi-
nates external boost capacitors and diodes, reducing
PC board area and cost. The MAX1761 can step down
input voltages from 5V to 20V, to outputs ranging from
1V to 5.5V on either output. Dual Mode feedback inputs
allow fixed output voltages of 2.5V and 1.8V for OUT1
and OUT2, respectively; or, a resistive voltage-divider
can be used to adjust the output voltages from 1V to
5.5V. Other appropriate applications for this device are
digital cameras, large PDAs, and handy-terminals.
V+ Input and VL +5V Logic Supplies
The MAX1761 has a 5V to 20V input voltage supply
range. A linear regulator powers the control logic and
other internal circuitry from the input supply pin (V+).
The linear regulators 4.65V output is available at VL
and can supply 25mA to external circuitry. When used
as an external supply, bypass VL to GND with a 4.7µF
capacitor. VL is turned off when the device is in shut-
down, and drops to approximately 4V when the device
experiences an output voltage fault.
The MAX1761 includes an input undervoltage lockout
(UVLO) circuit that prevents the device from switching
until VL > 4.25V (max). UVLO ensures there is sufficient
drive for the external MOSFETs, prevents the high-side
MOSFET from being turned on for near 100% duty
cycle, and keeps the output in regulation. The UVLO
DL1
CS1
OUT1
DH1
R3
R4
R1
R2
FB1 GND
ON2
VL REF
DL2
OUT2
CS2
DH2
FB2
V+ ON1
2.5V +1.8V
220µF
10µF
7µH
4.7µF
0.1µF
7µH
LX2
LX1
220µF
VOUT1
5V < VBATT < 20V
VOUT2
0.1µF
MAX1761
10
Figure 1. Typical Application Circuit
MAX1761
Small, Dual, High-Efficiency
Buck Controller for Notebooks
10 ______________________________________________________________________________________
comparator has 40mV hysteresis to prevent startup
oscillations on slowly rising input voltages.
If VL is not driven externally, then V+ should be at least
5V to ensure proper operation. If V+ is running from a
5V (±10%) supply, V+ should be externally connected
to VL. Overdriving the VL regulator with an external 5V
supply also increases the MAX1761s efficiency.
Voltage Reference (REF)
The internal 2V reference is accurate to ±1% (max)
over temperature and can supply a 50µA load current.
Bypass REF to GND with a 0.1µF capacitor when REF
is unloaded. Use a 0.22µF capacitor when applying an
external load.
Free-Running Constant-On-Time PWM
Controller with Input Feed-Forward
The Quick-PWM control architecture is a constant-on-
time, current-mode type with voltage feed-forward
(Figure 3). This architecture relies on the output ripple
voltage to provide the PWM ramp signal. Thus, the out-
put filter capacitors ESR acts as a feedback resistor.
The control algorithm is simple: the high-side switch on-
time is determined solely by a one-shot whose period is
inversely proportional to input voltage and directly pro-
portional to output voltage (see the On-Time One-Shot
section). Another one-shot sets a minimum off-time
(400ns typical). The on-time one-shot is triggered if the
error comparator is low, the low-side switch current is
below the current-limit threshold, and the minimum off-
time one-shot has timed out.
Table 1. Component Selection for Standard Applications
COMPONENT 2.5V AT 2.0A 2.5V AT 3.5A 1.8V AT 2.0A 3.3V AT 2A
Input Range 5V to 18V 5V to 18V 5V to 18V 5V to 18V
Frequency 350kHz 350kHz 250kHz 350kHz
Complementary
P- and N-Channel
MOSFETs
Fairchild FDS8958A Siliconix IRF7319 Fairchild FDS8958A Fairchild FDS8958A
Inductor
7µH
Sumida CDRH104-
7R0NC
3.5µH
Sumida CDRH127-
3R5NC
7µH
Sumida CDRH104-
7R0NC
10µH
Sumida CDRH104-
100NC
Input Capacitor
10µF, 25V
Taiyo Yuden
TMK432BJ106KM
2 x 10µF, 25V
Taiyo Yuden
TMK432BJ106KM
10µF, 25V
Taiyo Yuden
TMK432BJ106KM
10µF, 25V
Taiyo Yuden
TMK432BJ106KM
Output Capacitor
330µF, 10V
Kemet
T510X 337K101
2 x 330µF, 10V
Kemet
T510X 337K010
330µF, 10V
Kemet
T510X 337K010
330µF, 10V
Kemet
T510X 337K010
R1 = Short R1 = 1k R3 = Short R1 = Short
C urr ent- S ense
Feed b ack Resi stor sR2 = Open R2 = 1k R4 = Open R2 = Open
Table 2. Component Suppliers
SUPPLIER PHONE WEB
Fairchild
Semiconductor 408-822-2181 www.fairchildsemi.com
Kemet 408-986-0424 www.kemet.com
Panasonic 847-468-5624 ww w.p anasonic. com
Rohm 760-929-2100 www.rohmelectronics.
com
Sanyo 619-661-6835 www.secc.co.jp
Siliconix 408-988-8000 www.vishay.com
Sumida 847-956-0666 www.sumida.com
Taiyo Yuden 408-573-4150 www.t-yuden.com
MAX1761
Small, Dual, High-Efficiency
Buck Controller for Notebooks
______________________________________________________________________________________ 11
On-Time One-Shot
The heart of the PWM core is the one-shot that sets the
high-side switch on-time for both controllers. This fast,
low-jitter, adjustable one-shot includes circuitry that
varies the on-time in response to battery and output
voltage. The high-side switch on-time is inversely pro-
portional to the battery voltage as measured by the V+
input, and proportional to the output voltage. This algo-
rithm results in a nearly constant switching frequency
despite the absence of a fixed-frequency clock genera-
tor. The benefits of a constant switching frequency are
twofold: first, the switching noise occurs at a known fre-
quency and is easily filtered; second, the inductor rip-
ple current remains relatively constant, resulting in
predictable output voltage ripple and a relatively sim-
ple design procedure. The difference in frequencies
between OUT1 and OUT2 prevents audio-frequency
beating and minimizes crosstalk between the two
SMPS. The on-times can be calculated by using the
equation below that references the K values listed in
Table 3.
The 0.1V offset term accounts for the expected drop
across the low-side MOSFET switch.
On - Time = K V + 0.1V
V
OUT_
IN
OUT1 OUT2
ON1 ON2
CIN1 CIN2
DL1 DL2
DL1 DL2
ZCC1 ZCC2
ILIM1 ILIM2 VOS
Q2 Q4
Q1 Q3
D1 D2
L1 L2
COUT1 COUT2
-0.1V -0.1V
PWM
CONTROL
BLOCK
PWM
CONTROL
BLOCK
LINEAR
REG
2V
VREF
MAX1761
OUT1 VL
DH1 DH2
DH DH
DL DL
OUT OUT
GND
SHDN
V+
VL REF
CS1 CS2
ILIM ILIM
ZERO
CROSSING
ZERO
CROSSING
DL1 DH2
ON1
DRIVER DRIVER
DRIVER DRIVER
OUT1 VIN
VIN
CLCREF
VL
VIN
ON1 SHDN
VIN
VL
REF
OUT2
ON2
Figure 2. Functional Diagram
Table 3. On-Time One-Shot
DEVICE K
(µs)
MIN
(kHz)
TYP
(kHz)
MAX
(kHz)
OUT1 2.857 318 350 428
OUT2 4.000 227 250 278
MAX1761
Small, Dual, High-Efficiency
Buck Controller for Notebooks
12 ______________________________________________________________________________________
The maximum on-time and minimum off-time, tOFF(MIN),
one-shots restrict the continuous-conduction output
voltage. The worst-case dropout performance occurs
with the minimum on-time and the maximum off-time, so
the worst-case duty cycle for VIN = 6V, VOUT1 = 5V is
given by:
The duty cycle is ideally determined by the ratio of
input-to-output voltage (Duty Cycle = VOUT/VIN).
Voltage losses in the loop cause the actual duty cycle
to deviate from this relationship. See the Dropout
Performance section for more information. Equate the
off-time duty cycle restriction to the nonideal input/out-
put voltage duty cycle ratio. Typical units will exhibit
better performance. Operation of any power supply in
dropout will greatly reduce the circuits transient
response, and some additional bulk capacitance may
be required to support fast load changes.
Resistive voltage drops in the inductor loop and the
dead-time effect cause switching-frequency variations.
Parasitic voltage losses decrease the effective voltage
applied to the inductor. The MAX1761 compensates by
shifting the duty cycle to maintain the regulated output
voltage. The resulting change in frequency is:
VDROP1 is the sum of the parasitic voltage drops in the
inductor discharge path, including synchronous rectifi-
er, inductor, and PC board resistances; VDROP2 is the
sum of the resistances in the charging path; and tON is
the on-time calculated by the MAX1761.
In forced PWM mode, the dead-time effect increases
the effective on-time, reducing the switching frequency
as one or both dead times. This occurs only at light or
negative loads when the inductor current reverses.
Under these conditions, the inductors EMF causes the
switching node of the inductor to go high during the
dead time, extending the effective on-time.
ƒ= V+V
(V + V )
OUT DROP1
ON IN DROP2
t
Duty Cycle t
t+ t
ON(MIN)
ON(MIN) OFF(MAX)
==
+=
2 054
2 054 500 80 4
.
..%
µ
µ
s
sns
OUT
REF
UVP
FROM ZERO-CROSSING DETECTOR
FROM CURRENT-LIMIT COMPARATOR
ERROR
AMP
TOFF
TON
REF
-30%
FEEDBACK
MUX
(SEE FIGURE 12)
x2
TO DL DRIVER INPUT
FROM OUT
FROM FEEDBACK
TO DH DRIVER INPUT
ON-TIME
COMPUTE
TON
1-SHOT
1-SHOT
1-SHOT
TRIG
TRIG
Q
Q
Q
S
R
FB
OUT
GAIN
DRIVER
Q
TIMER
SHDN
SHDN ON/OFF
CONTROL
VIN
S
R
Q
UVP
LATCH
MAX1761
Figure 3. PWM Controller (One Side Only)
MAX1761
Small, Dual, High-Efficiency
Buck Controller for Notebooks
______________________________________________________________________________________ 13
Automatic Pulse-Skipping Switchover
In normal operation, the MAX1761s PWM control algo-
rithm automatically skips pulses at light loads.
Comparators at each CS_ input in the MAX1761 trun-
cate the low-side switchs on-time at the point where
the inductor current drops to zero. This occurs when
the inductor current is operating at the boundary
between continuous and discontinuous conduction
mode (Figure 4). This threshold is equal to 1/2 the
peak-to-peak ripple current, which is inversely propor-
tional to the inductor value:
where K is the on-time scale factor listed in Table 3. For
example, in the typical application circuit (Figure 1),
with VOUT1 = 2.5V, V+ = 15V, L = 9µH, and K =
2.857µs (Table 3), switchover to pulse-skipping opera-
tion occurs at ILOAD = 0.33A or about 1/8 full load. The
crossover point occurs at an even lower value if a
swinging (soft-saturation) inductor is used.
The switching waveforms may appear noisy and asyn-
chronous when light loading causes pulse-skipping
operation; this is a normal operating condition that
improves light-load efficiency. Trade-offs in PFM noise
vs. light-load efficiency are made by varying the induc-
tor value. Generally, lower inductor values produce a
broader efficiency vs. load curve, while higher values
result in higher full-load efficiency (assuming that the
coil resistance remains fixed) and less output voltage
ripple. Penalties for using higher inductor values
include larger physical size and degraded load-tran-
sient response (especially at low input-voltage levels).
Forced PWM Operation (ON2 floating)
The low-noise, forced-PWM mode (ON2 floating) dis-
ables the zero-crossing current comparator that con-
trols the low-side switch on-time. The resulting low-side
gate-drive waveform is forced to become the comple-
ment of the high-side gate-drive waveform. This, in turn,
causes the inductor current to reverse at light loads as
the PWM loop strives to maintain a constant duty ratio
of VOUT/V+. The benefit of forced-PWM mode is that it
keeps the switching frequency nearly constant, but it
results in a higher no-load battery current that can be
10mA to 40mA, depending on the gate capacitance of
the external MOSFETs.
Forced-PWM mode is most useful for reducing audio-
frequency noise, improving load-transient response,
and providing sink-current capability for dynamic out-
put voltage adjustment. Multiple-output applications
that use a flyback transformer or coupled inductor also
benefit from forced-PWM operation because the contin-
uous switching action improves cross-regulation.
Low-Side Current-Limit Sensing
The current-limit circuit employs a unique valley cur-
rent-sensing algorithm that uses the on-state resistance
of the low-side MOSFET as a current-sensing element.
If the current-sense signal is above the current-limit
threshold, the PWM is not allowed to initiate a new
cycle (Figure 5). The actual peak current is greater than
the current-limit threshold by an amount equal to the
inductor ripple current. Therefore, the exact current-
limit characteristic and maximum load capability are a
function of the MOSFET on-resistance, inductor value,
and input voltage. The reward for this uncertainty is
robust, lossless overcurrent sensing. When combined
with the undervoltage protection circuit, this current-
limit method is effective in almost every circumstance.
There is also a negative current limit that prevents
excessive reverse inductor currents when VOUT is sink-
ing current (forced PWM mode only). The negative cur-
rent-limit threshold is set to approximately 120% of the
positive current limit.
Carefully observe the PC board layout guidelines to
ensure that noise and DC errors do not corrupt the cur-
rent-sense signals seen by CS_. Mount or place the IC
close to the low-side MOSFET with short, direct traces,
making a Kelvin-sense connection to the source and
drain terminals.
If greater current-limit accuracy is desired, CS can be
connected to an external sense resistor inserted
between the source of the low-side switch and ground
(Figure 6). The resulting current limit will be ILIM = 0.1V
/ RSENSE, and it will have ±8% error.
IKV
2L
V+ - V
V+
LOAD(SKIP) OUT OUT
×
INDUCTOR CURRENT
ILOAD = IPEAK/2
ON-TIME0 TIME
-IPEAK
L
V + -VOUT
i
t=
Figure 4. Pulse-Skipping/Discontinuous Crossover Point
MAX1761
Small, Dual, High-Efficiency
Buck Controller for Notebooks
14 ______________________________________________________________________________________
MOSFET Gate Drivers
The DH and DL outputs are optimized for driving mod-
erate-sized power MOSFETs. The MOSFET drive capa-
bility is stronger for the low-side switch. This is
consistent with the low duty factor seen in the notebook
computer environment where a large V+ to VOUT differ-
ential exists. An adaptive dead-time circuit monitors the
DL output and prevents the high-side FET from turning
on until DL is fully off. There must be a low-resistance,
low-inductance path from the DL driver to the MOSFET
gate for the adaptive dead-time circuit to work properly.
Otherwise, the sense circuitry in the MAX1761 will inter-
pret the MOSFET gate as off while there is still charge
left on the gate. Use very short, wide traces measuring
10 to 20 squares or less (50mils to 100mils wide if the
MOSFET is 1 inch from the device). Similar to the DL
output, an adaptive dead-time circuit also monitors the
DH output and prevents the low-side FET from turning
on until DH is fully off. The same considerations should
be used for routing the DH signal to the high-side FET.
Since the transition time for a P-channel switch can be
much longer than an N-channel switch, the dead time
prior to the high-side PMOS turning on will be more
pronounced than in other synchronous step-down reg-
ulators, which use high-side N-channel switches. On
the high-to-low transition, the voltage on the inductors
"switched" terminal flies below ground until the low-side
switch turns on. A similar dead-time spike occurs on
the opposite low-to-high transition. Depending upon the
magnitude of the load current, these spikes usually
have a minor impact on efficiency.
The high-side drivers (DH_) swing from V+ to GND and
will typically source/sink 0.6A from the gate of the P-
channel MOSFET. The low-side driver (DL_) swings
from VL to ground and will typically source 0.5A and
sink 0.9A from the gate of the N-channel FET.
The internal pulldown transistors that drive DL low are
robust, with a 2.0(typ) on-resistance. This helps pre-
vent DL from being pulled up when the high-side
switch turns on, due to capacitive coupling from the
drain to the gate of the low-side MOSFET. This places
some restrictions on the FETs that can be used. Using
a low-side FET with smaller gate-to-drain capacitance
can prevent these problems.
Shutdown and Mode Control Inputs
The MAX1761 has two inputs (ON1, ON2) that control
the operating modes of the two regulators. Asserting
ON1 low places both regulators in micropower shut-
down mode, in which both VL and REF are disabled.
When ON1 is high, OUT1 is enabled, with VL and REF
active. ON2 serves a dual function: it is a shutdown
control for OUT2, and it determines the switching mode
for both regulators. When ON2 is low (ON2 < 0.5V),
OUT2 is disabled and OUT1 operates in normal mode.
Floating ON2 places both outputs in forced PWM
mode. When ON2 is high (2V < ON2 < VL), both regula-
tors run in normal operating mode. Toggling ON1 from
low to high resets the fault latch (Table 4).
Output Undervoltage Protection
The output undervoltage protection function is similar to
foldback current limiting but employs a timer rather
than a variable current limit. If the MAX1761 output volt-
age is under 70% (typ) of the nominal output voltage
20ms after coming out of shutdown, then both PWMs
are latched off and will not restart until V+ is cycled or
ON1 is toggled low to high.
INDUCTOR CURRENT
ILIMIT
ILOAD
0 TIME
IPEAK
Figure 5. Valley Current-Limit Threshold Point
Figure 6. Using a Low-Side Current-Sense Resistor
DL
OUT
CS
DH
FB
V+
VOUT
MAX1761
MAX1761
Small, Dual, High-Efficiency
Buck Controller for Notebooks
______________________________________________________________________________________ 15
Thermal Fault Protection
The MAX1761 features a thermal fault protection circuit.
When the temperature rises above +160°C, the DL low-
side gate-driver outputs latch high until ON1 is toggled
or V+ is cycled. The fault threshold has 10°C of thermal
hysteresis, which prevents the regulator from restarting
until the die cools off.
POR and Soft-Start
Power-on reset (POR) occurs when V+ falls below
approximately 2V, resetting the fault latch and prepar-
ing the PWM for operation once the power is cycled. VL
undervoltage lockout (UVLO) circuitry inhibits switching
and forces the DL gate driver low until VL rises above
4.25V, whereupon an internal digital soft-start timer
begins to ramp up the maximum allowed current limit.
The ramp occurs in five steps: 20%, 40%, 60%, 80%,
and 100%; 100% current is available after 1.7ms.
Design Procedure
Firmly establish the input voltage range and the maxi-
mum load current before choosing the inductor operat-
ing point (ripple current ratio). The following three
factors determine the SMPS design using the
MAX1761:
1) Input Voltage Range. The maximum value
(V+(max)) must accommodate the worst-case high
AC adapter voltage. The minimum value (V+(min))
must account for the lowest battery voltage after
drops due to connectors, fuses, and battery selec-
tor switches. If there is a choice at all, lower input
voltages result in better efficiency.
2) Maximum Load Current. There are two values to
consider, the peak load current (ILOAD(MAX)) and
the continuous load current (ILOAD). The peak load
current determines the instantaneous component
stresses and filtering requirements and thus drives
output capacitor selection, inductor saturation rat-
ing, and the design of the current-limit circuit. The
continuous load current determines the thermal
stresses and thus drives the selection of input
capacitors, MOSFETs, and other critical heat-con-
tributing components. Modern notebook CPUs gen-
erally exhibit ILOAD = ILOAD(MAX) 80%.
3) Inductor Operating Point. This choice provides
trade-offs between size and efficiency. Low induc-
tor values cause large ripple currents, resulting in
the smallest size, but poor efficiency and high out-
put noise. The minimum practical inductor value is
one that causes the circuit to operate at the edge of
critical conduction (where the inductor current just
touches zero with every cycle at maximum load).
Inductor values lower than this grant no further size-
reduction benefit.
The MAX1761s pulse-skipping algorithm initiates skip
mode at the critical conduction point. So, the inductor
operating point also determines the load-current value
at which PWM/skip mode switchover occurs. The opti-
mum point is usually found between 20% and 50% rip-
ple current.
The inductor ripple current also impacts transient-
response performance, especially at low VIN - VOUT dif-
ferentials. Low inductor values allow the inductor
current to slew faster, replenishing charge removed
from the output filter capacitors by a sudden load step.
The amount of output sag is also a function of the maxi-
mum duty factor, which can be calculated from the on-
time and minimum off-time:
Inductor Selection
The switching frequency (on-time) and operating point
(% ripple or LIR) determine the inductor value as fol-
lows:
Example: ILOAD(MAX) = 2.5A, V+(max) = 20V, VOUT1 =
2.5V, f = 350kHz, 35% ripple current or LIR = 0.35:
LV(- )
V+ LIR I
OUT OUT
LOAD(MAX)
=+
×ƒ× ×
VV
V(I ) L
2C - V
SAG
LOAD(MAX)
F (MIN) OUT
2
=×
×+
DUTY V()
Table 4. Operating Mode Control Summary
MODE ON1 ON2 DESCRIPTION
Shutdown ON1 < 0.5V X Both OUT1 and OUT2 off, VL and REF disabled
ON1 Enabled 2.0V < ON1 < V+ ON2 < 0.5V OUT1 on in normal mode, OUT2 off
Forced PWM 2.0V < ON1 < V+ Floating Both OUT1 and OUT2 on in forced PWM mode
Normal Operation 2.0V < ON1 < V+ 2.0V < ON2 VL Both OUT1 and OUT2 on in normal mode
MAX1761
Small, Dual, High-Efficiency
Buck Controller for Notebooks
16 ______________________________________________________________________________________
Find a low-loss inductor having the lowest possible DC
resistance that fits in the allotted dimensions. Ferrite
cores are often the best choice, although powdered
iron is inexpensive and works well at 250kHz. The core
must be large enough not to saturate at the peak induc-
tor current (IPEAK):
IPEAK = ILOAD(MAX) - 1/2 LIR ILOAD(MAX) =
(1 - 0.5 LIR) ILOAD(MAX)
Setting Current Limit
The minimum current-limit threshold must be great
enough to support the maximum load current plus
some safety margin. For the circuit in Figure 1, with a
desired 2.5A maximum load current, the worst-case
current limit is set at 3.0A, providing a 20% safety mar-
gin. Under these conditions, the valley of the inductor
current waveform occurs at:
IVALLEY = ILOAD(MAX) - 1/2 LIR ILOAD(MAX) =
(1 - 0.5 LIR) ILOAD(MAX)
The required valley current is IVALLEY = 3A - 1/2 (0.35)
2.5A = 2.56A. Next, the current-sense feedback volt-
age must be scaled taking into account the tolerance of
the CS_ current-limit threshold and the maximum MOS-
FET drain-source on-resistance (RDS(ON)) variation
over temperature. The minimum current-limit threshold
at the CS_ pins is 92mV. The worst-case maximum
value for (RDS(ON)) over temperature is 50m. At
2.56A, the voltage developed across the low-side
switch is 128mV. A resistive voltage-divider with a
0.703 attenuation ratio is necessary to scale this volt-
age to the 92mV CS_ threshold.
A current-sense resistor can be used if a more accu-
rate current limit is needed than is available when using
the MOSFET (RDS(ON) (Figure 6). Placing the sense
resistor between the source of the low-side MOSFET
and ground provides a very accurate sense point for
the CS_ inputs. Alternatively, a small sense resistor can
be used in series with the low-side MOSFET to ballast
the device and reduce the temperature coefficient of
the current limit when sensing at the inductors
switched node. This provides a compromise between
sensing across the MOSFET device alone or using a
large sense resistor.
Output Capacitor Selection
The output filter capacitor must have low enough effec-
tive series resistance (ESR) to meet output ripple and
load-transient requirements, yet have high enough ESR
to satisfy the stability criterion.
In CPU VCORE converters and other applications where
the output is subject to violent load transients, the out-
put capacitors size depends on how much ESR is
needed to prevent the output from dipping too low
under a load transient. Ignoring the sag due to finite
capacitance:
In non-CPU applications, the output capacitors size
depends on how much ESR is needed to maintain an
acceptable level of output voltage ripple:
The actual required µF capacitance value relates to the
physical size needed to achieve low ESR as well as to
the chemistry of the capacitor technology. Thus, the
capacitor is usually selected by ESR and voltage rating
rather than by capacitance value (this is true of tanta-
lums, SP, POS, and other electrolytics).
When using low-capacitance filter capacitors, such as
ceramic or polymer types, capacitor size is usually
determined by the capacitance needed to prevent
VSAG and VSOAR from causing problems during load
transients. Generally, once enough capacitance is
added to meet the VSOAR requirement, undershoot at
the rising load edge is no longer a problem (see the
VSAG equation in Design Procedure). The amount of
overshoot due to stored inductor energy can be calcu-
lated as:
where IPEAK is the peak inductor current.
Stability Considerations
Stability is determined by the value of the ESR zero rel-
ative to the switching frequency. The point of instability
is given by the following equation:
ƒ=
ƒ
ESR π
VL
×(I
2CV
PEAK
OUT
2)
RVp - p
LIR I
ESR LOAD(MAX)
×
RV
I
ESR DIP
LOAD(MAX)
L-
=×××
=
25 20 25
20 350 0 35 2 5 71
.( .)
.. .
VV V
V kHz A Hµ
MAX1761
Small, Dual, High-Efficiency
Buck Controller for Notebooks
______________________________________________________________________________________ 17
where:
For a typical 350kHz application, the ESR zero frequen-
cy must be well below 100kHz, preferably below
50kHz. Tantalum and OS-CON capacitors have typical
ESR zero frequencies of 15kHz. Sanyo POS capacitors
have typical ESR zero frequencies of 20kHz. In the
design example used for inductor selection, the ESR
needed to support 50mVp-p ripple is 50mV / LIR(2.5A)
= 57.1m. A single150µF/6.3V Sanyo POS capacitor
provides 55m(max) ESR. This ESR results in a zero at
19.3kHz, well within the bounds of stability.
Dont put high-value ceramic capacitors directly across
the fast feedback inputs (FB_/OUT_ to GND) without
taking precautions to ensure stability. Large ceramic
capacitors can have a high-ESR zero frequency and
may cause erratic, unstable operation. However, its
easy to add enough series resistance by placing the
capacitors a couple of inches downstream from the
junction of the inductor and FB_/OUT_ pin.
Unstable operation manifests itself in two related but
distinctly different ways: double-pulsing and fast-feed-
back loop instability.
Double-pulsing occurs due to noise on the output or
because the ESR is so low that there isnt enough volt-
age ramp in the output voltage signal. This fools the
error comparator into triggering a new cycle immedi-
ately after the 500ns minimum off-time period has
expired. Double-pulsing is more annoying than harmful,
resulting in nothing worse than increased output ripple.
However, it can indicate the possible presence of loop
instability, which is caused by insufficient ESR. Loop
instability can result in oscillations at the output after
line or load perturbations that can cause the output
voltage to go outside the tolerance limit.
The easiest method for checking stability is to apply a
very fast zero-to-max load transient (refer to the
MAX1761 EV kit manual) and carefully observe the out-
put voltage ripple envelope for overshoot and ringing. It
can help to simultaneously monitor the inductor current
with an AC current probe. Dont allow more than one
cycle of ringing after the initial step-response under- or
overshoot.
Input Capacitor Selection
The input capacitor must meet the ripple current
requirement (IRMS) imposed by the switching currents.
Nontantalum chemistries (ceramic, aluminum, or OS-
CON) are preferred due to their resilience to power-up
surge currents.
Power MOSFET Selection
DC bias and output power considerations dominate the
selection of the power MOSFETs used with the
MAX1761. Care should be taken not to exceed the
devices maximum voltage ratings. In general, both
switches are exposed to the supply voltage, so select
MOSFETs with VDS(MAX) greater than V+(max). Gate
drive to the N-channel and P-channel MOSFETs is not
symmetrical. The N-channel device is driven from
ground to the logic supply VL. The P-channel device is
driven from V+ to ground. The maximum rating for VGS
for the N-channel device is usually not an issue.
However, VGS(MAX) for the P-channel must be at least
V+(max). Since VGS(MAX) is usually lower than
VDS(MAX), gate-drive constraints often dictate the
required P-channel breakdown rating.
For moderate input-to-output differentials, the high-side
MOSFET (Q1) can be sized smaller than the low-side
MOSFET (Q2) without compromising efficiency. The
high-side switch operates at a very low duty cycle
under these conditions, so most conduction losses
occur in Q2. For maximum efficiency, choose a high-
side MOSFET (Q1) that has conduction losses (I2RD)
equal to the switching losses (fCV+2). Make sure that
the conduction losses at the minimum input voltage
dont exceed the package thermal limits or violate the
overall thermal budget. Similarly check for rating viola-
tions for conduction and switching losses at the maxi-
mum input voltage (see MOSFET Power Dissipation).
The MAX1761 has an adaptive dead-time circuitry that
prevents the high-side and low-side MOSFETs from
conducting at the same time (see MOSFET Gate
Drivers). Even with this protection, it is still possible for
delays internal to the MOSFET to prevent one MOSFET
from turning off when the other is turned on. The maxi-
mum mismatch time that can be tolerated is 60ns.
Select devices that have low turn-off times, and make
sure that NFET(tDOFF(MAX)) - PFET(tDON(MIN)) < 60ns,
and PFET(tDOFF(MAX)) - NFET(tDON(MIN)) < 60ns.
Failure to do so may result in efficiency-killing shoot-
through currents.
MOSFET selection also affects PC board layout. There
are four possible combinations of MOSFETs that can
be used with this switcher. The designs include:
Two dual complementary MOSFETs (Figure 7)
IV(V-V)
RMS LOAD OUT OUT
=+
+
I V
ƒ=
××
ESR ESR F
1
2πRC
MAX1761
Small, Dual, High-Efficiency
Buck Controller for Notebooks
18 ______________________________________________________________________________________
A dual N-channel and a dual P-channel MOSFET
(Figure 8)
Two single N-channels and a dual P-channel
(Figure 9)
Two single N-channels and two single P-channels
(Figure 10)
There are trade-offs to each approach. Complementary
devices have appropriately scaled N- and P-channel
RDS(ON) and matched turn-on/turn-off characteristics.
However, there are relatively few manufacturers of
these specialized devices. Selection may be limited.
Dual N- and P-channel MOSFETs are more widely
available. As such, more efficient designs that benefit
from the large low-side MOSFETs can be realized. This
approach is most useful when the output power
requirements for both regulators are about the same.
This limitation can be sidestepped by using a dual P-
channel and two single N-channels. Using four single
MOSFETs gives the greatest design flexibility but will
require the most board area.
MOSFET Power Dissipation
Worst-case conduction losses occur at the duty factor
extremes. For the high-side MOSFET, the worst-case
power dissipation (PD) due to resistance occurs at the
minimum battery voltage:
Generally, a small high-side MOSFET is desired to
reduce switching losses at high input voltages.
However, the RDS(ON) required to stay within package
power-dissipation limits often limits how small the MOS-
FET can be. The optimum occurs when the switching
(AC) losses equal the conduction (RDS(ON)) losses.
High-side switching losses dont usually become an
issue until the input is greater than approximately 15V.
Switching losses in the high-side MOSFET can become
an insidious heat problem when maximum AC adapter
voltages are applied, due to the squared term in the
CV2F switching-loss equation. If the high-side MOSFET
youve chosen for adequate RDS(ON) at low battery volt-
ages becomes extraordinarily hot when subjected to
V+(MAX), reconsider your MOSFET choice.
Calculating the power dissipation in Q1 due to switch-
ing losses is difficult since it must allow for difficult
quantifying factors that influence the turn-on and turn-
off times. These factors include the internal gate resis-
tance, gate charge, threshold voltage, source
inductance, and PC board layout characteristics. The
following switching-loss calculation provides only a
very rough estimate and is no substitute for breadboard
evaluation, preferably including a verification using a
thermocouple mounted on Q1:
where CRSS is the reverse transfer capacitance of Q1,
and IGATE is the peak gate-drive source/sink current
(1A typ).
For the low-side MOSFET (Q2) the worst-case power
dissipation always occurs at maximum battery voltage:
The absolute worst case for MOSFET power dissipation
occurs under heavy overloads that are greater than
ILOAD (MAX) but are not quite high enough to exceed the
current limit and cause the fault latch to trip. To protect
against this possibility, the circuit must be overdesigned
to tolerate:
ILOAD = ILIMIT (MAX) + 1/2 LIR ILOAD (MAX)
P (Q2) V
V+ IRs
DOUT
(MAX) OAD2
=−
××1L
P (Q1 switching) CV+ I
I
DRSS (MAX) LOAD
GATE
2
=×׃×
P (Q1 resistance) V
V+ IR
DOUT
(MIN) OAD2DS(ON)
=
××
L
P-CHANNEL
LX1
DH1
V+
DL1
DG
DS
DG
DS
N-CHANNEL
1
P-CHANNEL
LX2
DH2
V+
DL2
DG
DS
DG
DS
N-CHANNEL
1
Figure 7. Dual Complementary MOSFET Design
MAX1761
Small, Dual, High-Efficiency
Buck Controller for Notebooks
______________________________________________________________________________________ 19
where ILIMIT(MAX) is the maximum valley current
allowed by the current-limit circuit, including threshold
tolerance and on-resistance variation. This means that
the MOSFETs must be very well heatsinked. If short-cir-
cuit protection without overload protection is enough, a
normal ILOAD value can be used for calculating compo-
nent stresses.
Choose a Schottky diode (D1, Figure 2) having a for-
ward voltage low enough to prevent the Q2 MOSFET
body diode from turning on during the dead time. As a
general rule, a diode having a DC current rating equal
to 1/3 of the load current is sufficient. This diode is
optional and can be removed if efficiency isnt critical.
Applications Issues
Dropout Performance
The output voltage adjust range for continuous-conduc-
tion operation is restricted by the nonadjustable 500ns
(max) minimum off-time one-shot. For best dropout per-
formance, use the side with the lower switching fre-
quency, FB2 (250kHz). When working with low input
voltages, the duty-factor limit must be calculated using
worst-case values for on- and off-times. Manufacturing
DH2
DH1
S
G
S
D
D
D
DG
DL1
V+
DG
DS
DS
DS
P-CHANNEL
P-CHANNEL
LX1
LX2
N-CHANNEL
1
1
DL2DG
DS
DS
DS
N-CHANNEL
1
Figure 9. Two Single N-Channel MOSFETs and a Dual P-Channel
MOSFET Design
DH1
S
S
S
D
D
D
DG
LX1
DL1
V+
DG
DS
DS
DS DH2
S
S
S
D
D
D
DG
LX2
DL2
V+
DG
DS
DS
DS
P-CHANNEL N-CHANNEL P-CHANNEL N-CHANNEL
1
1
1
1
Figure 10. Two Single N-Channel MOSFETs and Two Single P-Channel MOSFETs Design
P-CHANNEL
DH1
V+
LX1
SD
GD
SD
GD
P-CHANNEL
DH2
1
LX2
N-CHANNEL
DL1
DL2
DG
DS
DG
DS
N-CHANNEL
1
Figure 8. Dual N- and P-Channel MOSFET Design
MAX1761
Small, Dual, High-Efficiency
Buck Controller for Notebooks
20 ______________________________________________________________________________________
tolerances and internal propagation delays introduce
an error to the tON K-factor. Also, keep in mind that
transient response performance of buck regulators
operated close to dropout is poor, and bulk output
capacitance must often be added (see the VSAG equa-
tion in Design Procedure).
Dropout design example: VIN = 6.5V (min), VOUT =
5V, f = 350kHz, 250kHz. The required duty is (VOUT +
VSW) / (V+ - VSW) = (5V + 0.1V) / (6.5V - 0.1V) = 79.7%.
The worst-case on-time for f = 350kHz is (VOUT + 0.1V)
/ V+ K = 5.1V / 6.5V 2.857µs-V 90% = 2.017µs.
The IC duty-factor limitation is:
Thus, operation at 350kHz meets the required duty
cycle. A similar analysis with f = 250kHz (K = 4µs-V)
shows that at f = 250kHz, the maximum duty cycle is
85.0%, also meeting the required duty cycle.,
Remember to include inductor resistance and MOSFET
on-state voltage drops (VSW) when doing worst-case
dropout duty-factor calculations.
Fixed Output Voltages
The MAX1761s dual-mode operation allows the selec-
tion of common voltages without requiring external
components (Figure 11). Connect FB1 to GND for a
fixed +2.5V output at OUT1; otherwise, connect FB1 to
a resistive voltage-divider for an adjustable output.
Connect FB2 to GND for a +1.8V output; otherwise,
connect FB2 to a resistive voltage-divider for an
adjustable output.
Adjusting VOUT
The output voltage can be adjusted with a resistive volt-
age-divider if desired (Figure 12). The equation for
adjusting the output voltage is:
where VFB is 1.0V, and R2 is about 10k.
Low Input Voltage Operation (V+ = +5V)
The MAX1761 can be used in applications using a 5V
±10% input supply by overdriving VL with the input
supply voltage, V+. This not only enables operation of
the MAX1761 down to V+ = 4.5V but has the added
benefit of increasing overall efficiency. Overdriving the
VL regulator will increase the drive on the low-side
MOSFETs, thereby lowering their RDS(ON) and reduc-
ing power consumption. Note that VL should not be
higher than 5.5V if connected to VL. Also note, V+
should not be brought below 5V unless VL is connect-
ed directly to V+.
PC Board Layout Guidelines
Careful PC board layout is critical to achieving low
switching losses and clean, stable operation. This is
especially true for dual converters, where one channel
can affect the other. The switching power stages
require particular attention (Figure 13). Refer to the
MAX1761 EV kit data sheet for a specific layout exam-
ple. If possible, mount all of the power components on
the top side of the board with their ground terminals
flush against one another. Follow these guidelines for
good PC board layout:
Isolate the top-side power components from the
sensitive analog components on the bottom side
with a ground shield. Use a separate PGND plane
under the OUT1 and OUT2 sides (called PGND1
and PGND2). Avoid the introduction of AC currents
into the PGND1 and PGND2 ground planes. Run
the power plane ground currents on the top side
only, if possible.
Use a star ground connection on the power plane
to minimize the crosstalk between OUT1 and OUT2.
Keep the high-current paths short, especially at the
ground terminals. This practice is essential for sta-
ble, jitter-free operation.
Connect AGND and PGND together close to the IC.
Do not connect them together anywhere else.
Carefully follow the grounding instructions under
Step 4 of the Layout Procedure.
Keep the power traces and load connections short.
This practice is essential for high efficiency. Using
thick copper PC boards (2oz vs. 1oz) can enhance
full-load efficiency by 1% or more. Correctly routing
PC board traces is a difficult task that must be
approached in terms of fractions of centimeters,
where a single mof excess trace resistance caus-
es a measurable efficiency penalty.
CS_ and PGND connections to the synchronous
rectifiers for current limiting must be made using
Kelvin sensed connections to guarantee the cur-
rent-limit accuracy. With SO-8 MOSFETs, this is
best done by routing power to the MOSFETs from
outside, using the top copper layer, while connect-
ing PGND and CS_ inside (underneath) the SO-8
package.
VV R
R
OUT FB 1
2
+
1
Duty t
t+t
ON(MAX)
ON(MAX) OFF(MIN)
==
+=
2 017
2 017 500 80 1
.
..%
µ
µ
s
sns
MAX1761
Small, Dual, High-Efficiency
Buck Controller for Notebooks
______________________________________________________________________________________ 21
When trade-offs in trace lengths must be made, its
preferable to allow the inductor charging path to be
made longer than the discharge path. For example,
its better to allow some extra distance between the
input capacitors and the high-side MOSFET than to
allow distance between the inductor and the low-
side MOSFET or between the inductor and the out-
put filter capacitor.
Ensure that the OUT connection to COUT is short
and direct. However, in some cases it may be
desirable to deliberately introduce some trace
length between the OUT inductor node and the out-
put filter capacitor (see Stability Considerations).
Route high-speed switching nodes (CS_, DH_, and
DL_) away from sensitive analog areas (REF, FB_).
Use a PGND as an EMI shield to keep radiated
switching noise away from the IC, feedback
dividers, and analog bypass capacitors.
Avoid coupling switching noise into control input
connections (ON1, ON2, etc.). These pins should
be referenced to a quiet analog ground plane.
Layout Procedure
1) Place the power components first, with ground ter-
minals adjacent (Q2 source, CIN_, COUT_). If possi-
ble, make all these connections on the top layer
with wide, copper-filled areas.
2) Mount the controller IC adjacent to the synchronous
rectifier MOSFETs, preferably on the back side in
order to keep CS_, PGND_, and the DL_ gate-drive
line short and wide. The DL_ gate trace must be
short and wide, measuring 10 to 20 squares (50mils
to 100mils wide if the MOSFET is 1 inch from the
controller IC).
3) Place the VL capacitor near the IC controller.
4) Make the DC-DC controller ground connections as
follows: near the IC, create a small analog ground
plane. Use this plane for the ground connection for
the REF and VL bypass capacitor, and FB_
dividers. Create another small ground island for
PGND, and use it for the V+ bypass capacitor,
placed very close to the IC. Connect the AGND and
the PGND together under the IC (this is the only
connection between AGND and PGND).
5) On the boards top side (power planes), make a
star ground to minimize crosstalk between the two
sides. The top-side star ground is a star connection
of the input capacitors, side 1 low-side MOSFET,
and side 2 low-side MOSFET. Keep the resistance
low between the star ground and the sources of the
low-side MOSFETs for accurate current limit.
Connect the top-side star ground (used for MOS-
FET, input, and output capacitors) to the small
PGND island with a short, wide connection (prefer-
ably just a via). If multiple layers are available (high-
ly recommended), create PGND1 and PGND2
islands on the layer just below the top-side layer
(refer to the MAX1761 EV kit for an example) to act
as an EMI shield. Connect each of these individual-
ly to the star ground via, which connects the top
side to the PGND plane. Add one more solid
ground plane under the IC to act as an additional
shield, and also connect that to the star ground via.
6) Connect the output power planes directly to the out-
put filter capacitor positive and negative terminals
with multiple vias.
DL
CS
OUT
GND
DH
1/2
FB
V+
VOUT
R1
R2
MAX1761
Figure 12. Setting VOUT with a Resistive Voltage-Divider
MAX1761
TO ERROR
AMP1
TO ERROR
AMP2
OUT2
FB2
0.1V
0.1V
FB1
FIXED
1.8V
FIXED
2.5V
OUT1
Figure 11. Feedback MUX
MAX1761
Small, Dual, High-Efficiency
Buck Controller for Notebooks
22 ______________________________________________________________________________________
Chip Information
TRANSISTOR COUNT: 6045
USE AGND PLANE TO:
- BYPASS VL AND REF
- TERMINATE EXTERNAL FB
DIVIDER (IF USED)
- PIN-STRAP CONTROL
INPUTS
USE PGND PLANE TO:
- BYPASS V+
- CONNECT PGND TO THE TOPSIDE
STAR GROUND
VIA TO PGND
NOTE: EXAMPLE SHOWN IS FOR DUAL COMPLEMENTARY MOSFET.
CONNECT PGND TO AGND
BENEATH THE MAX1761 AT
ONE POINT ONLY AS SHOWN.
AGND
VBATT
GND
L1 L2
P2 N2P1 N1
VOUT1 VOUT2
C3 C4
C2 C1
VL
D1
D2
Figure 13. PC Board Layout Example
Small, Dual, High-Efficiency
Buck Controller for Notebooks
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 23
© 2000 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.
MAX1761
Package Information
QSOP.EPS
MAX1761
Note: The MAX1761 does not have a heat slug.