STSPIN32F0251, STSPIN32F0252 250 V three-phase controller with MCU Datasheet - production data Applications TQFP 10x10 64L pitch 0.5 Battery operated and 110 Vac supplied power and garden tools Industrial fans and pumps Home appliances Industrial and home automation Features Description Three-phase gate drivers - High voltage rail up to 250 V - Driver current capability: STSPIN32F0251: 200/350 mA source/sink current STSPIN32F0252: 1/0.85 A source/sink current - dV/dt transient immunity 50 V/ns - Gate driving voltage range from 9V to 20V The STSPIN32F025x system-in-package is an extremely integrated solution for driving threephase applications, helping designers to reduce PCB area and overall bill-of-material. 32-bit ARM(R) Cortex(R)-M0 core: - Up to 48 MHz clock frequency - 4-Kbyte SRAM with HW parity - 32-Kbyte Flash memory with option bytes used for write/readout protection 21 general-purpose I/O ports (GPIO) 6 general-purpose timers 12-bit ADC converter (up to 10 channels) I2C, USART and SPI interfaces Matched propagation delay for all channels Integrated bootstrap diodes Comparator for fast over current protection It embeds an STM32F031x6x7 featuring an ARM(R) 32-bit Cortex(R)-M0 CPU and a 250 V triple half-bridge gate driver, able to drive N-channel power MOSFETs or IGBTs. A comparator featuring advanced smartSD function is integrated, ensuring fast and effective protection against overload and overcurrent. The high-voltage bootstrap diodes are also integrated, as well as anti cross-conduction, deadtime and UVLO protection on both the lower and upper driving sections, which prevents the power switches from operating in low efficiency or dangerous conditions. Matched delays between low and high-side sections guarantee no cycle distortion. The integrated MCU allows performing FOC, 6-step sensorless and other advanced driving algorithms including the speed control loop. UVLO, Interlocking and deadtime functions Smart shutdown (smartSD) function Product label Standby mode for low power consumption On-chip debug support via SWD Extended temperature range: -40 to +125 C September 2019 This is information on a product in full production. DS13048 Rev 2 1/29 www.st.com Contents STSPIN32F0251, STSPIN32F0252 Contents 1 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 Pin description and connection diagram . . . . . . . . . . . . . . . . . . . . . . . . 4 3 Electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.3 Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 5 Device description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.1 5.2 5.3 6 Gate driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.1.1 Inputs and outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.1.2 Deadtime . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.1.3 VCC UVLO protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5.1.4 VBO UVLO protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.1.5 Comparator and Smart shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Microcontroller unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5.2.1 Memories and boot mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5.2.2 Power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5.2.3 High-speed external clock source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Advanced-control timer (TIM1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 6.1 TQFP 10x10 64L package information . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 6.2 Suggested land pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 7 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 8 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 2/29 DS13048 Rev 2 STSPIN32F0251, STSPIN32F0252 1 Block diagram Block diagram Figure 1. STSPIN32F025x SiP block diagram s W W s^^ W W W W W W W KKd W s 7$$ 67-0 %&5&$5*0/ 67-0 7$$ 67 -FWFM4IJGUFS 7 )*/ 7 )*/ 7 W W W W W W W KKd W W s^^ s s sd 'MPBUJOHTUSVDUVSF 7$$ 7 KKd ,s' 67 -FWFM4IJGUFS Khd 'MPBUJOHTUSVDUVSF 7$$ -0(*$ 4)005 5)306() 13&7&/5*0/ -*/ 7 % KKd ,s' 67 -FWFM4IJGUFS 'MPBUJOHTUSVDUVSF 7$$ Khd >s' %&"%5*.& 7$$ -*/ >s' 7 -M/ 7$$ >s' '"6-5 s s^^ zW^^Z' s^^ W W W EWKZ s W W W W W W W& W& W W W W W W W W W W s % )M/ s W W W W ^dD& s W W W W W W W W& W& EZ^d s^^ zW^^Z' KKd ,s' Khd &/ W W W W& W& EZ^d s^^ % *0% 4."35 4% 0% $*/ W'E 7 73&' 67-0 ^'E /E K s^^ s W W W W W W DS13048 Rev 2 3/29 29 Pin description and connection diagram 2 STSPIN32F0251, STSPIN32F0252 Pin description and connection diagram Figure 2. STSPIN32F025x pin connection (Top view) 1& 5(6 9&& 5(6 5(6 5(6 %227 966 +9* 9'' 287 3& 1& 3& 1& 3& 1& 3) %227 3) +9* 1567 287 966$ 1& 9''$ 1& 3$ 1& 287 1& *1' 2' &,1 966 3% 9'' 3% 3$ 3$ 3$ 5(6 +9* 3$ /9* 3$ /9* 3$ /9* 1& %227 3*1' 3$ 4/29 3$ 3$ 3$ 3$ 3% 3% 3% 3% 3% 3% %227 DS13048 Rev 2 STSPIN32F0251, STSPIN32F0252 Pin description and connection diagram Table 1. Legend/abbreviations used in the pin description table Name Abbreviation Definition Unless otherwise specified in brackets below the pin name, the pin function during and after reset is the same as the actual pin name Pin name Pin type I/O structure AO Gate Driver Analog Output P Gate Driver Supply \ GND pin S Supply pin I Input-only pin I/O Input / output pin FT 5 V-tolerant I/O FTf 5 V-tolerant I/O, FM+ capable TTa 3.3 V-tolerant I/O directly connected to ADC TC Standard 3.3V I/O B Dedicated BOOT0 pin Bidirectional reset pin with embedded weak pull-up resistor RST Unless otherwise specified by a note, all I/Os are set as floating inputs during and after reset Notes Pin functions Alternate functions Functions selected through GPIOx_AFR registers Additional functions Functions directly selected/enabled through peripheral registers Table 2. Pin description N. Name Type Function 1 PB8 I/O - FTf MCU PB8 2 VSS Supply MCU digital ground 3 VDD Supply MCU digital power supply 4 PC13 I/O - TC MCU PC13 5 PC14 I/O - TC MCU PC14 6 PC15 I/O - TC MCU PC15 7 PF0 I/O - FT MCU PF0 8 PF1 I/O - FT MCU PF1 9 NRST I/O - RST MCU Reset pin 10 VSSA Supply MCU analog ground 11 VDDA Supply MCU analog power supply 12 PA0 I/O - TTa MCU PA0 13 PA1 I/O - TTa MCU PA1 DS13048 Rev 2 5/29 29 Pin description and connection diagram STSPIN32F0251, STSPIN32F0252 Table 2. Pin description (continued) N. 6/29 Name Type Function 14 PA2 I/O - TTa MCU PA2 15 PA3 I/O - TTa MCU PA3 16 PA4 I/O - TTa MCU PA4 17 PA5 I/O - TTa MCU PA5 18 PA6 I/O - TTa MCU PA6 19 PA7 I/O - TTa MCU PA7 20 PB0 I/O - TTa MCU PB0 21 PB1 I/O - TTa MCU PB1 22 VDD Supply MCU digital power supply 23 VSS Supply MCU digital ground 24 OD Analog OD Output Open Drain comparator output 25 CIN Analog Input Comparator positive input 26 SGND Power Driver signal ground 27 PGND Power Driver power ground Analog Out Phase 1 low-side driver output (1) 28 LVG1 29 LVG2 Analog Out Phase 2 low-side driver output 30 LVG3 Analog Out Phase 3 low-side driver output 31 RES4 Reserved Pin must be left floating 33 OUT1 Power Phase 1 high-side (floating) common voltage 34 HVG1(1) Analog Out Phase 1 high-side driver output 35 BOOT1 Power Phase 1 bootstrap supply voltage 40 OUT2 Power Phase 2 high-side (floating) common voltage 41 HVG2(1) Analog Out Phase 2 high-side driver output 42 BOOT2 Power Phase 2 bootstrap supply voltage 46 OUT3 Power Phase 3 high-side (floating) common voltage 47 HVG3(1) Analog Out Phase 3 high-side driver output 48 BOOT3 Power Phase 3 bootstrap supply voltage 50 RES5 Reserved Pin must be left floating 51 VCC Power Driver low-side and logic supply voltage 52 RES1 Reserved Pin must be left floating 53 RES2 Reserved Pin must be left floating 54 RES3 Reserved Pin must be left floating 55 PA12 I/O - FT MCU PA12 DS13048 Rev 2 STSPIN32F0251, STSPIN32F0252 Pin description and connection diagram Table 2. Pin description (continued) N. Name Type Function 56 PA13 I/O - FT MCU PA13/SWDIO (System debug data) 57 PA14 I/O - FT MCU PA14/SWDCLK (System debug clock) 58 PA15 I/O - FT MCU PA15 59 PB3 I/O - FT MCU PB3 60 PB4 I/O - FT MCU PB4 61 PB5 I/O - FT MCU PB5 62 PB6 I/O - FTf MCU PB6 63 PB7 I/O - FTf MCU PB7 64 BOOT0 I-B Boot memory selection 32, 36, 37, 38, 39, 43, 44, 45, 49 NC Not Connected 1. The circuit guarantees less than 1 V on the LVG and HVG pins (at Isink = 10 mA), with VCC > 3 V. This allows omitting the "bleeder" resistor connected between the gate and the source of the external MOSFETs normally used to hold the pin low. When the EN is set low, gate driver outputs are forced low and assure low impedance. Table 3. STSPIN32F025x MCU-Driver internal connections Note: MCU pad Type Controller pad Function PB12 I/O - FT FAULT PB13 I/O - FT LIN1 Gate Driver Low-Side input driver 1 PB14 I/O - FT LIN2 Gate Driver Low-Side input driver 2 PB15 I/O - FT LIN3 Gate Driver Low-Side input driver 3 PA8 I/O - FT HIN1 Gate Driver High-Side input driver 1 PA9 I/O - FTf HIN2 Gate Driver High-Side input driver 2 PA10 I/O - FTf HIN3 Gate Driver High-Side input driver 3 PA11 I/O - FT EN Gate Driver Fault output Gate Driver shutdown input Each unused GPIO inside the SiP should be configured in OUTPUT mode low level after startup by software. DS13048 Rev 2 7/29 29 Electrical data STSPIN32F0251, STSPIN32F0252 3 Electrical data 3.1 Absolute maximum ratings Table 4. Absolute maximum ratings(1) Symbol Parameter Test condition Min. Max. Unit -0.3 21 V VCC Power supply voltage VPGND Low-side driver ground VCC - 21 VCC + 0.3 V VPS(2) Low-side driver ground -21 21 V VOUT Output voltage VBOOT - 21 VBOOT + 0.3 V VBOOT Bootstrap voltage -0.3 270 V VHVG High-side gate output voltage VOUT - 0.3 VBOOT + 0.3 V VLVG Low-side gate output voltage VPGND - 0.3 VCC + 0.3 V VCIN Comparator input voltage -0.3 20 V VOD Open-drain voltage (OD, FAULT) -0.3 21 V dVOUT/dt Common mode transient Immunity 50 V/ns VIO MCU logic input voltage TTa type(3) -0.3 (3) 4 V 4(4) Logic input voltage FT, FTf type -0.3 VDD + MCU I/O output current (3) -25 25 mA IIO MCU I/O total output current (3) -80 80 mA VDD MCU digital supply voltage (3) -0.3 4 V VDDA MCU analog supply voltage (3) -0.3 4 V Tstg Storage temperature -50 150 C TJ Junction temperature -40 150 C PTOT Total power dissipation 4.5 W IIO ESD Human Body Model 2 (5) V kV 1. Each voltage referred to SGND unless otherwise specified. 2. VPS = VPGND - VSGND 3. For details see Table 15 and 16 in the STM32F031x6x7 datasheet. 4. Valid only if the internal pull-up/pull-down resistors are disabled. If the internal pull-up or pull-down resistor is enabled, the maximum limit is 4 V. 5. Pins 33 to 48 have HBM ESD rating 1C conforming to ANSI/ESDA/JEDEC JS-001-2014. 8/29 DS13048 Rev 2 STSPIN32F0251, STSPIN32F0252 3.2 Electrical data Thermal data Table 5. Thermal data Symbol Parameter Thermal resistance junction to ambient(1) Rth(JA) Value Unit 27.6 C/W 1. JEDEC 2s2p PCB in still air. 3.3 Recommended operating conditions Table 6. Recommended operating conditions Symbol Parameter Test Condition Min. Typ. Max. Unit VCC Power supply voltage (VCCthON)MAX 20 V VLS(1) Low-side driver supply voltage 4 20 V VPS(2) Low-side driver ground -5 5 V VBO(3) Floating supply voltage (VBOthON)MAX 20 V VCIN Comparator input voltage 0 15 V VOUT DC Output voltage -10(4) 230 V FSW Maximum switching frequency(5) 800 kHz VDD Standard MCU operating voltage 3.6 V VDD 3.6 V VDDA MCU analog operating voltage (ADC not used) Must have a potential equal to or higher than MCU analog operating VDD voltage (ADC used) VDD 3.6 V -40 125 C TJ 3.0 Operating junction temperature 3.3 1. VLS = VCC - VPGND 2. VPS = VPGND - VSGND 3. VBO = VBOOT - VOUT 4. LVG off. VCC = 9 V. Logic is operational if VBOOT > 5 V. 5. Actual maximum FSW depends on power dissipation. DS13048 Rev 2 9/29 29 Electrical characteristics 4 STSPIN32F0251, STSPIN32F0252 Electrical characteristics (VCC=15 V; VDD=3.3 V; PGND = SGND; TJ = +25 C, unless otherwise specified.) Table 7. Electrical characteristics Symbol Parameter Test Condition Min. Typ. Max. Unit Power supply and standby mode IQCCU VCC undervoltage quiescent supply current VCC = 7 V; EN = 5 V; CIN = SGND 430 744 A IQCC VCC quiescent supply current EN = 5 V; CIN = SGND LVG & HVG: OFF 950 1450 A VCCthON VCC UVLO turn-on threshold 8 8.5 9 V VCCthOFF VCC UVLO turn-off threshold 7.5 8 8.5 V VCChys VCC UVLO threshold hysteresis 0.4 0.5 0.6 V IDD(1) VDD current consumption (Supply current in Run mode, code executing from Flash memory) IDDA(1) VDDA current consumption VDD = 3.6 V HSE bypass, PLL off fHCLK = 1 MHz 0.8 VDD = 3.6 V HSI clock, PLL on fHCLK = 48 MHz 18.9 VDD = 3.6 V HSE bypass, PLL off fHCLK = 1 MHz 2.0 VDD = 3.6 V HSI clock, PLL on fHCLK = 48 MHz 220 VPOR VDD Power on reset Rising edge threshold VPDR VDD Power down reset threshold VPDRhyst VDD PDR hysteresis Falling edge mA A 1.84(2) 1.92 2.00 V 1.80 1.88 1.96(2) V 40 mV High-side floating section supply(3) IQBOU VBO under-voltage quiescent supply current VCC = VBO = 6.5 V; EN = 5 V; CIN = SGND 25 62 A IQBO VBO quiescent supply current VBO = 15 V EN = 5 V; CIN = SGND LVG OFF; HVG = ON 84 150 A 10/29 DS13048 Rev 2 STSPIN32F0251, STSPIN32F0252 Electrical characteristics Table 7. Electrical characteristics (continued) Symbol Parameter Test Condition Min. Typ. Max. Unit VBOthON VBO UVLO turn-on threshold 7.5 8 8.5 V VBOthOff VBO UVLO turn-off threshold 7 7.5 8 V VBOhys VBO UVLO threshold hysteresis 0.4 0.5 0.6 V ILK High voltage leakage current BOOT = HVG = OUT = 270 V 15 A RDboot Bootstrap diode on resistance TJ = 25 C LVG ON 215 240 LVG OFF 215 250 200 300 mA 350 mA 1.33 A 1.48 A 430 mA 500 mA 1.02 A 1.15 A 46 56 7.6 10.3 21 27 8 11.2 Output driving buffers Source peak current ISO STSPIN32F0251 STSPIN32F0252 TJ = 25 C 160 Full temperature range(3) 130 TJ = 25 C 0.88 (3) Full temperature range 0.72 TJ = 25 C 230 1.0 Sink peak current ISI STSPIN32F0251 STSPIN32F0252 Source RDSon RDSonON STSPIN32F0251 STSPIN32F0252 Sink RDSon RDSonOFF STSPIN32F0251 STSPIN32F0252 (3) Full temperature range 200 TJ = 25 C 0.71 (3) Full temperature range 350 0.85 0.51 I = 10mA TJ = 25 C 24 Full temperature range(3) TJ = 25 C 20 5 Full temperature range(3) 35 6.4 4.2 I = 10mA TJ = 25 C 11 Full temperature range(3) TJ = 25 C 8 5.5 Full temperature range(3) DS13048 Rev 2 16 4.5 6.7 11/29 29 Electrical characteristics STSPIN32F0251, STSPIN32F0252 Table 7. Electrical characteristics (continued) Symbol Parameter Test Condition Min. Typ. Max. Unit 0.3*VDD + 0.07 V 0.475 *VDD 0.2 V Logic Inputs TTa type(4) Low level logic threshold voltage Vil FT, FTf type(4) TTa type(4) 0.45 *VDDIOx +0.398 V FT, FTf type(4) 0.5 *VDDIOx +0.2 V 200 mV 100 mV High level logic threshold voltage Vih Vhyst Schmitt trigger hysteresis TTa type(4) FT, FTf type (4) TC, FT and FTf I/O TTa in digital mode VSS VIN VDDIOx Input leakage current Ilkg VSSDlh SmartSD restart threshold VSSDl SmartSD unlatch threshold 0.1 TTa in digital mode VDDIOx VIN VDDA 1 A TTa in analog mode VSS VIN VDDA 0.1 FT and FTf I/O VDDIOx VIN 5 V 10 3.5 3.8 4.3 V 0.56 0.75 V 510 mV Sense Comparator and FAULT(5) VREF Internal voltage reference 410 460 CINhyst Comparator input hysteresis 40 70 CINPD Comparator input pull-down current 7 10 13 A IOD OD internal current source 2.5 5 7.5 A RON_OD OD On resistance IOD = 16 mA 19 25 36 ISAT_OD OD saturation current VOD = 5 V VFLOAT_OD OD floating voltage level OD connected only to an external capacitance 12/29 VCIN = 1 V mV 95 DS13048 Rev 2 4.2 4.8 mA 5.2 V STSPIN32F0251, STSPIN32F0252 Electrical characteristics Table 7. Electrical characteristics (continued) Symbol Parameter Test Condition Min. Typ. Max. Unit 11 16 21 mA 50 100 8 12 mA IOL_OD OD low level sink current VOD = 400 mV RON_F FAULT On resistance IFAULT = 8 mA IOL_F FAULT low level sink VFAULT = 400 mV current tOD Comparator propagation delay Rpu = 1 k to 5 V; 0 to 3.3 V voltage step on CIN 50% CIN to 90% OD 350 500 ns tCIN-F Comparator triggering to FAULT 0 to 3.3 V voltage step on CIN; 50% CIN to 90% FAULT 350 500 ns tCINoff Comparator triggering to high/low-side driver propagation delay 0 to 3.3 V voltage step on CIN 50% CIN to 90% LVG/HVG 360 510 ns tFCIN Comparator input filter time 200 300 400 ns SR Slew rate 4 7.7 10.3 V/s 45 85 120 ns 45 85 120 ns 245 345 520 ns CL = 1 nF; Rpu = 1 k to 5 V; 90% to 10% OD 4 Driver dynamic characteristics ton toff tEN High/Low-side driver turn-on propagation delay OUT = 0 V High/Low-side driver BOOT = VCC turn-off propagation CL = 10 nF delay Vin = 0 to 3.3 V Enable to high/low- See Figure 3 side driver propagation delay Rise time tr STSPIN32F0251 120 STSPIN32F0252 19 Fall time tf CL= 1 nF ns CL= 1 nF STSPIN32F0251 50 STSPIN32F0252 17 MT Delay matching high/low-side turnon/off(6) 0 30 ns DT Deadtime CL= 1 nF 300 400 ns MDT Matching deadtime(7) CL= 1 nF 0 50 ns 200 DS13048 Rev 2 ns 13/29 29 Electrical characteristics STSPIN32F0251, STSPIN32F0252 1. The current consumption depends on the firmware loaded in the microcontroller. See STM32F031x6x7 datasheet. 2. Data based on characterization results, not tested in production. 3. Values provided by characterization, not tested. 4. Data based on design simulation only. Not tested in production. 5. Comparator is disabled when VCC is in UVLO condition. 6. MT = max. (|ton(LVG) - toff(LVG)|, |ton(HVG) - toff(HVG)|, |toff(LVG) - ton(HVG)|, |toff(HVG) - ton(LVG)|) 7. MDT = | DTLH - DTHL |, refer to Figure 3. Figure 3. Propagation delay timing definition /,1 W!'7 +,1 W!'7 WU WI /9* W RQ WU W RII WI +9* W RQ (1 W RII /9*+9* W (1 14/29 DS13048 Rev 2 W (1 STSPIN32F0251, STSPIN32F0252 Electrical characteristics Figure 4. Deadtime timing definitions W!'7 /,1 +,1 WU WI +9* W RII WI /9* W RII '7/+ '7+/ Figure 5. Deadtime and interlocking waveforms definition /,1 ,17(5/2&.,1* &21752/6,*1$/('*(6 29(5/$33(')25 025(7+$1'($'7,0( ,17(5/2&.,1* ,17(5/2&.,1* +,1 /9* '7+/ '7/+ +9* JDWHGULYHURXWSXWV2)) +$/)%5,'*(75,67$7( JDWHGULYHURXWSXWV2)) +$/)%5,'*(75,67$7( */5& */5& +,1 3-0 $,*/ 3-0 $,*/ ( ( /,1 &21752/6,*1$/('*(6 29(5/$33(' ,17(5/2&.,1*'($'7,0( /9* '7+ +/ '7//+ +9* JDWHGULYHURXWSXWV2)) +$/)%5,'*(75,67$7( JDWHGULYHURXWSXWV2)) +$/)%5,'*(75,67$7( /,1 &21752/6,*1$/6('*(6 6<1&+521286 '($'7,0( +,1 /9* '7/+ '7+/ +9* JDWHGULYHURXWSXWV2)) +$/)%5,'*(75,67$7( JDWHGULYHURXWSXWV2)) +$/)%5,'*(75,67$7( /,1 &21752/6,*1$/6('*(6 12729(5/$33(' %87,16,'(7+('($'7,0( '($'7,0( +,1 /9* '7/+ '7+/ +9* JDWHGULYHURXWSXWV2)) +$/)%5,'*(75,67$7( JDWHGULYHURXWSXWV2)) +$/)%5,'*(75,67$7( /,1 &21752/6,*1$/6('*(6 12729(5/$33(' 2876,'(7+('($'7,0( ',5(&7'5,9,1* +,1 /9* '7/+ '7+/ +9* JDWHGULYHURXWSXWV2)) +$/)%5,'*(75,67$7( DS13048 Rev 2 JDWHGULYHURXWSXWV2)) +$/)%5,'*(75,67$7( 15/29 29 Device description 5 STSPIN32F0251, STSPIN32F0252 Device description The STSPIN32F025x is a system-in-package providing an integrated solution suitable for driving high-voltage 3-phase applications. 5.1 Gate driver The STSPIN32F025x integrates a triple half-bridge gate driver able to drive N-channel power MOSFETs or IGBTs. The high-side section is supplied by a bootstrapped voltage technique with integrated bootstrap diode. All the inputs lines are connected to a pull-down resistor with typical value of 60 k. The high- and low-side outputs of same half-bridge cannot be simultaneously driven high thanks to an integrated interlocking function. 5.1.1 Inputs and outputs The device is controlled through the following logic inputs: EN: enable input, active high; LIN: low-side driver inputs, active low; HIN: high-side driver inputs, active low. Table 8. Inputs truth table (applicable when device is not in UVLO or SmartSD protection) Input pins Interlocking Output pins EN LIN HIN LVG HVG L X X Low Low H H H Low Low H L H HIGH Low H H L Low HIGH H L L Low Low 1. X: don't care The FAULT and OD pins are open-drain outputs. The FAULT signal is set low in case VCC UVLO is detected, or in case the SmartShutDown comparator triggers an event. It is only used to signal a UVLO or SmartSD activation to external circuits, and its state does not affect the behavior of other functions or circuits inside the driver. The OD behavior is explained in Section 5.1.5. 5.1.2 Deadtime The deadtime feature, in companion with the interlocking feature, guarantees that driver outputs of the same channel are not high simultaneously and at least a DT time passes between the turn-off of one driver's output and the turn-on of the companion output of the same channel. If a deadtime longer than the internal DT is applied to LIN and HIN inputs by 16/29 DS13048 Rev 2 STSPIN32F0251, STSPIN32F0252 Device description the external controller, the internal DT is ignored and the outputs follow the deadtime determined by the inputs. Refer to Figure 4 for the deadtime and interlocking waveforms. 5.1.3 VCC UVLO protection Undervoltage protection is available on VCC and BOOT supply pins. In order to avoid intermittent operation, a hysteresis sets the turn-off threshold with respect to the turn-on threshold. When VCC voltage goes below the VCCthOFF threshold all the outputs are switched off, both LVG and HVG. When VCC voltage reaches the VCCthON threshold the driver returns to normal operation and sets the LVG outputs according to actual input pins status; HVG is also set according to input pin status if the corresponding VBO section is not in UVLO condition. The FAULT output is kept low when VCC is in UVLO condition. The following figures show some examples of typical operation conditions. Figure 6. VCC power ON and UVLO, LVG timing DS13048 Rev 2 17/29 29 Device description STSPIN32F0251, STSPIN32F0252 Figure 7. VCC power ON and UVLO, HVG timing 7$$UI0/ 7$$UI0'' 7$$ '"6-5 5.1.4 7 7 67-07$$ -*/ 7 /9* 7 VBO UVLO protection Dedicated undervoltage protection is available on each bootstrap section between BOOTx and OUTx supply pins. In order to avoid intermittent operation, a hysteresis sets the turn-off threshold with respect to the turn-on threshold. When VBO voltage goes below the VBOthOFF threshold, the HVG output of the corresponding bootstrap section is switched off. When VBO voltage reaches the VBOthON threshold the device returns to normal operation and the output remains off up to the next input pins transition that requests HVG to turn on. 18/29 DS13048 Rev 2 STSPIN32F0251, STSPIN32F0252 Device description Figure 8. VBO Power-ON and UVLO timing 7$$UI0/ 7$$UI0'' 9&& 7 )$8/7 67-07$$ +,1 7 7 9#0UI0/ 9#0UI0'' 7%2 7 +9*287 5.1.5 Comparator and Smart shutdown The STSPIN32F025x integrates a comparator committed to the fault protection function, thanks to the SmartShutDown (SmartSD) circuit. The SmartSD architecture allows immediate turn-off of the gate driver outputs in the case of overload or overcurrent condition, by minimizing the propagation delay between the fault detection event and the actual output switch-off. In fact, the time delay between the fault detection and the output turn-off is not dependent on the value of the external components connected to the OD pin, which are only used to set the duration of disable time after the fault. This provides the possibility to increase the duration of the output disable time after the fault event up to very large values without increasing the delay time of the protection. The duration of the disable time is determined by the values of the external capacitor COD and of the optional pull-up resistor connected to the OD pin. The comparator has an internal voltage reference VREF connected to the inverting input, while the non-inverting input is available on the CIN pin. The comparator's CIN input can be connected to an external shunt resistor in order to implement a fast and simple overcurrent protection function. The output signal of the comparator is filtered from glitches shorter than tFCIN and then fed to the SmartSD logic. If the impulse on the CIN pin is higher than VREF and wider than tFCIN, the SmartSD logic is triggered and immediately sets all of the driver outputs to low-level (OFF). At the same time, FAULT is forced low to signal the event (for example to a MCU input) and OD starts to discharge the external COD capacitor used to set the duration of the output disable time of the fault event. The FAULT pin is released and driver outputs restart following the input pins as soon as the output disable time expires. DS13048 Rev 2 19/29 29 Device description STSPIN32F0251, STSPIN32F0252 The overall disable time is composed of two phases: The OD unlatch time (t1 in Figure 9), which is the time required to discharge the COD capacitor down to the VSSDl threshold. The discharge starts as soon as the SSD comparator is triggered. The OD Restart time (t2 in Figure 9), which is the time required to recharge the COD capacitor up to the VSSDh threshold. The recharge of COD starts when the OD internal MOSFET is turned-off, which happens when the fault condition has been removed (CIN < VREF - CINhyst) and the voltage on OD reaches the VSSDl threshold. This time normally covers most of the overall output disable time. If no external pull-up is connected to OD, the external COD capacitor is discharged with a time constant defined by COD and the internal MOSFET's characteristic (Equation 1), and the Restart time is determined by the internal current source IOD and by COD (Equation 2). Equation 1 V OD t 1 R ON _OD C OD In ------------ V SSDl Equation 2 C OD V SSDh V SSDl - V OD t 2 ------------------------------ In -------------------------------V I OD SSDh - V OD Where VOD = VFLOAT_OD In case the OD pin is connected to VCC by an external pull-up resistor ROD_ext, the OD discharge time is determined by the external network ROD_ext COD and by the internal MOSFET's RON_OD (Equation 3), while the Restart time is determined by current in ROD_ext (Equation 4). Equation 3 V OD - V on t 1 C OD R OD_ext // R ON _OD In -----------------------------V - V SSDl on Equation 4 V SSDl - V OD t 2 C OD R OD_ext In ------------------------------- V SSDh - V OD where R ON _OD Von = --------------------------------------------- VCC ; R OD_ext + R ON _OD 20/29 V OD = VCC DS13048 Rev 2 STSPIN32F0251, STSPIN32F0252 Device description Figure 9. Smart shutdown timing waveforms 95() &,1 U'$*/ U'$*/ )DVWVKXWGRZQ U$*/PGG WKHGULYHURXWSXWVDUHVZLWFKHGRII LPPHGLDWHO\DIWHUWKHFRPSDUDWRUWULJJHULQJ /9*+9* 70% 2' 744%I 744%M 2'JDWH LQWHUQDO U U GLVDEOHWLPH )$8/7 60$576+87'2:1&,5&8,7 H[WHUQDOSXOOXS 9&& 7 7 52'BH[W *0% 2' 2' 60$57 6' /2*,& &2' 60$57 6' /2*,& &2' 521B2' 521B2' 5.2 *0% Microcontroller unit The integrated MCU is the STM32F031x6 with the following main characteristics: Core: ARM(R) 32-bit Cortex(R) -M0 CPU, frequency up to 48 MHz Memories: 4kB of SRAM, 32 kB of Flash Memory CRC calculation unit Up to 21 fast I/Os Advanced-control timer dedicated for PWM generation Up to 6 general purpose timers 12-bit ADC (up to 10 channels) DS13048 Rev 2 21/29 29 Device description STSPIN32F0251, STSPIN32F0252 Communication interfaces: I2C, USART, SPI Serial Wire Debug (SWD) Extended temperature range: -40 to 125C Note: For more details refer to the STM32F031x6 datasheet on www.st.com. 5.2.1 Memories and boot mode The device has the following features: 4 Kbytes of embedded SRAM accessed (read/write) at CPU clock speed with 0 wait states and featuring embedded parity checking with exception generation for fail-critical applications. The non-volatile memory is divided into two arrays: - 32 Kbytes of embedded Flash memory for programs and data - Option bytes The option bytes are used to write-protect the memory (with 4 KB granularity) and/or readout-protect the whole memory with the following options: - Level 0: no readout protection - Level 1: memory readout protection, the Flash memory cannot be read from or written to if either debug features are connected or boot in RAM is selected - Level 2: chip readout protection, debug features (Cortex(R)-M0 serial wire) and boot in RAM selection disabled. At startup, the boot pin and boot selector option bit are used to select one of the three boot options: boot from User Flash memory boot from System Memory boot from embedded SRAM The boot loader is located in System Memory, programmed by ST during production. It is used to reprogram the Flash memory by using USART on pins PA14/PA15. 5.2.2 Power management The VDD pin is the power supply for I/Os and the internal regulator. The VDDA pin is power supply for ADC, Reset blocks, RCs and PLL. The VDDA voltage is provided externally through VDDA pin. Note: The VDDA voltage level must be always greater or equal to the VDD voltage level and must be established first. The MCU has integrated power-on reset (POR) and power-down reset (PDR) circuits. They are always active, and ensure proper operation above a threshold of 2 V. The device remains in reset mode when the monitored supply voltage is below a specified threshold, VPOR/PDR, without the need for an external reset circuit. The POR monitors only the VDD supply voltage. During the startup phase it is required that VDDA should arrive first and be greater than or equal to VDD. The PDR monitors both the VDD and VDDA supply voltages, however the VDDA power supply supervisor can be disabled (by programming a dedicated Option bit) to reduce the 22/29 DS13048 Rev 2 STSPIN32F0251, STSPIN32F0252 Device description power consumption if the application design ensures that VDDA is higher than or equal to VDD. The device features an embedded programmable voltage detector (PVD) that monitors the VDD power supply and compares it to the VPVD threshold. An interrupt can be generated when VDD drops below the VPVD threshold and/or when VDD is higher than the VPVD threshold. The interrupt service routine can then generate a warning message and/or put the MCU into a safe state. The PVD is enabled by software. The MCU supports three low-power modes to achieve the best compromise between low power consumption, short startup time and available wakeup sources: Sleep mode In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can wake up the CPU when an interrupt/event occurs. Stop mode Stop mode achieves very low power consumption while retaining the content of SRAM and registers. All clocks in the 1.8 V domain are stopped, the PLL, the HSI RC and the HSE crystal oscillators are disabled. The voltage regulator can also be put either in normal or in low power mode. The device can be woken up from Stop mode by any of the EXTI lines (one of the 16 external lines, the PVD output, RTC, I2C1 or USART1). Standby mode The Standby mode is used to achieve the lowest power consumption. The internal voltage regulator is switched off so that the entire 1.8 V domain is powered off. The PLL, the HSI RC and the HSE crystal oscillators are also switched off. After entering Standby mode, SRAM and register contents are lost except for registers in the RTC domain and Standby circuitry. The device exits Standby mode when an external reset (NRST pin), an IWDG reset, a rising edge on the WKUP pins, or an RTC event occurs. 5.2.3 High-speed external clock source The high-speed external (HSE) clock can be generated from external clock signal or supplied with a 4 to 32 MHz crystal/ceramic resonator oscillator (see Figure 10). In the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. Figure 10. Typical application with 8 MHz crystal DS13048 Rev 2 23/29 29 Device description 1. 2. STSPIN32F0251, STSPIN32F0252 The REXT value depends on the crystal characteristics (refer to the crystal resonator manufacturer for more details on them). The external clock signal has to respect the I/O characteristics and follows recommended clock input waveform (refer to Figure 11). Figure 11. HSE clock source timing diagram 5.3 Advanced-control timer (TIM1) The advanced-control timer (TIM1) can be seen as a three-phase PWM multiplexed on six channels. It has complementary PWM outputs with programmable inserted deadtimes. This timer is used to generate the PWM signal for the three half-bridge gate drivers as shown in Table 9. Table 9. TIM1 channel configuration 24/29 MCU I/O ASIC input TIM1 channel PB13 LIN1 TIM1_CH1N PB14 LIN2 TIM1_CH2N PB15 LIN3 TIM1_CH3N PA8 HIN1 TIM1_CH1 PA9 HIN2 TIM1_CH2 PA10 HIN3 TIM1_CH3 DS13048 Rev 2 STSPIN32F0251, STSPIN32F0252 6 Package information Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK(R) packages, depending on their level of environmental compliance. ECOPACK(R) specifications, grade definitions and product status are available at: www.st.com. ECOPACK(R) is an ST trademark. 6.1 TQFP 10x10 64L package information Figure 12. TQFP mechanical data DS13048 Rev 2 25/29 29 Package information STSPIN32F0251, STSPIN32F0252 Table 10. TQFP package dimensions(1) Symbol Min. Nom. Max. TOTAL THICKNESS A --- --- 1.2 STAND OFF A1 0.05 --- 0.15 MOLD THICKNESS A2 0.95 --- 1.05 LEAD WIDTH(PLATING) b 0.17 0.22 0.27 LEAD WIDTH b1 0.17 0.2 0.23 L/F THICKNESS(PLATING) c 0.09 --- 0.2 L/F THICKNESS c1 0.09 --- 0.16 X D --- 12 --- Y E --- 12 --- X D1 --- 10 --- Y E1 --- 10 --- e --- 0.5 --- L 0.45 0.6 0.75 0 3.5 7 1 0 --- --- 2 11 12 13 3 11 12 13 R1 0.08 --- --- R2 0.08 --- 0.2 S 0.2 --- --- X M 5.85 5.95 6.05 Y N 5.85 5.95 6.05 BODY SIZE LEAD PITCH EP SIZE PACKAGE LEAD TOLERANCE aaa 0.2 LEAD EDGE TOLERANCE bbb 0.2 COPLANARITY ccc 0.08 LEAD OFFSET ddd 0.08 MOLD FLATNESS eee 0.05 1. All dimensions are mm unless otherwise stated. 26/29 DS13048 Rev 2 STSPIN32F0251, STSPIN32F0252 Suggested land pattern Figure 13. TQFP 10x10 64L suggested land pattern 6.2 Package information 1. All dimensions are mm unless otherwise stated. DS13048 Rev 2 27/29 29 Ordering information 7 STSPIN32F0251, STSPIN32F0252 Ordering information Table 11. Order codes Order code Package Package marking Packaging STSPIN32F0251 TQFP 10x10 64L STSPIN32F0 251 Tray STSPIN32F0251TR TQFP 10x10 64L STSPIN32F0 251 Tape and Reel STSPIN32F0252 TQFP 10x10 64L STSPIN32F0 252 Tray STSPIN32F0252TR TQFP 10x10 64L STSPIN32F0 252 Tape and Reel 8 Revision history Table 12. Document revision history Date Revision 29-Aug-2019 1 Initial release. 04-Sept-2019 2 Changed Figure 2 and 11. 28/29 Changes DS13048 Rev 2 STSPIN32F0251, STSPIN32F0252 IMPORTANT NOTICE - PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries ("ST") reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST's terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers' products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. (c) 2019 STMicroelectronics - All rights reserved DS13048 Rev 2 29/29 29