DW82801HR S LJA9 - Intel

Document Number: 313056-004

Intel® I/O Controller Hub 8 (ICH8)

Family

Datasheet

– For the Intel® 82801HB ICH8, 82801HR ICH8R, 82801HDH ICH8DH,

82801HDO ICH8DO, 82801HBM ICH8M, and 82801HEM ICH8M-E

I/O Controller Hubs

May 2014

2Intel® ICH8 Family Datasheet

INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR

OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS

OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELA TING

TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE,

MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Intel products are not intended for

use in medical, life saving, or life sustaining applications.

Intel may make changes to specifications and product descriptions at any time, without notice.

Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined .” Intel reserves these for

future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.

The Intel® I/O Controller Hub 8 (ICH8) F amily chipset component may contain design defects or errors known as errata which may cause the product to

deviate from published specifications. Current characterized errata are available on request.

Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.

I2C is a two-wire communications bus/protocol developed by Philips. SMBus is a subset of the I2C bus/protocol and was developed by Intel.

Implementations of the I2C bus/protocol may require licenses from various entiti es, including Philips Electronics N.V. and North American Philips

Corporation.

Intel® Active M anagem ent Technology re quire s the pl atfo rm hav e an Int el® AMT-enabled chipset and network hardware and software, be plugged into a

power source, and have a network connection.

Alert on LAN is a result of the Intel-IBM Advanced Manageability Alliance and a trademark of IBM.

Intel, Intel SpeedStep and the Intel logo are trademarks of Intel Corporation in the U.S. and other countries.

*Other names and brands may be claimed as the property of others.

Intel® ICH8 Family Datasheet 3

Contents

1Introduction............................................................................................................45

1.1 Overview .........................................................................................................48

1.2 Intel® ICH8 Family High-Level Component Differences...........................................55

2 Signal Description ...................................................................................................57

2.1 Direct Media Interface (DMI) to Host Controller.....................................................60

2.2 PCI Express* ....................................................................................................60

2.3 LAN Connect Interface .......................................................................................61

2.4 Gigabit LAN Connect Interface ... .. .. .. ....................... ....................... .....................61

2.5 Firmware Hub Interface.... .. .. .. .................................................................. ..........62

2.6 PCI Interface ....................................................................................................63

2.7 Serial ATA Interface.................. .. ............................... .. .. ... ..................... .. .. .. ......66

2.8 IDE Interface (Mobile Only) ................................................................................68

2.9 LPC Interface....................................................................................................69

2.10 Interrupt Interface ............................................................................................70

2.11 USB Interface.... ........... .. .. ........... .. .. .......... ... .. .......... .. ........... .. .. ........... .. .. ........71

2.12 Power Management Interface..............................................................................72

2.13 Processor Interface............................................................................................75

2.14 SMBus Interface................................................................................................77

2.15 System Management Interface............................................................................77

2.16 Real Time Clock Interface...................................................................................78

2.17 Other Clocks.....................................................................................................79

2.18 Miscellaneous Sig n als ...... .. .. ..................... .. ... ..................... .. .. ..................... .. .. ..79

2.19 Intel® High Definition Audio Link.........................................................................80

2.20 Serial Peripheral Interface (SPI)..........................................................................81

2.21 Intel® Quick Resume Technology (Intel® ICH8DH On ly)............................. .. .. ........82

2.22 Controller Link..................................................................................................82

2.23 Intel® Quiet System Technology (Desktop Only) ...................................................83

2.24 General Purpose I/O Signals ...............................................................................83

2.25 Power and Ground.............................................................................................86

2.26 Pin Straps ........................................................................................................88

2.26.1 Functional Straps .............. .......... .. .. ... ..................... .. .. .. ..................... .. ..88

2.26.2 External RTC Circuitry.............................................................................90

3Intel

® ICH8 Pin States.............................................................................................91

3.1 Integrated Pull-Ups and Pull-Downs. ....................................................................91

3.2 IDE Integrated Series Termination Resistors (Mobile Only)......................................92

3.3 Output and I/O Signals Planes and States.............................................................92

3.4 Power Planes for Input Signals.......................................................................... 102

4Intel

® ICH8 and System Clock Domains................................................................. 107

5 Functional Description........................................................................................... 109

5.1 PCI-to-PCI Bridge (D30:F0 )............................................................. ................. 109

5.1.1 PCI Bus Interface................................................................................. 109

5.1.2 PCI Bridge As an Initiator...................................................................... 109

5.1.2.1 Memory Reads and Writes........................................................ 110

5.1.2.2 Configuratio n Reads and Writes ................. .. .. ..................... .. .. .. 110

5.1.2.3 Locked Cycles ........................................................................ 110

5.1.2.4 Target / Master Aborts............................................................. 110

5.1.2.5 Secondary Master Latency Timer............................................... 110

5.1.2.6 Dual Address Cycle (DAC)........................................................ 110

5.1.2.7 Memory and I/O Decode to PCI................................................. 111

5.1.3 Parity Error Detection and Generation ..................................................... 111

4Intel® ICH8 Family Datasheet

5.1.4 PCIRST# .............................................................................................111

5.1.5 Peer Cycles..........................................................................................112

5.1.6 PCI-to-PCI Bridge Model ........................................................................112

5.1.7 IDSEL to Device Number Mapping...........................................................112

5.1.8 Standard PCI Bus Configuration Mechanism..............................................113

5.2 PCI Express* Root Ports (D28:F0,F1,F2,F3,F4,F5)................................................113

5.2.1 Interrupt Generation.............................................................................113

5.2.2 Power Mana ge me nt.......... .......... .. .. ........... .. .. ........... .. .. ..................... .. ..114

5.2.2.1 S3/S4/S5 Support...................................................................114

5.2.2.2 Resuming from Suspended State...............................................114

5.2.2.3 Device Initiated PM_PME Message .............................................114

5.2.2.4 SMI/SCI Generation.................................................................115

5.2.3 SERR# Generation................................................................................115

5.2.4 Hot-Plug..............................................................................................115

5.2.4.1 Presence Detection..................................................................115

5.2.4.2 Message Generation ................................................................116

5.2.4.3 Attention Button Detection .......................................................116

5.2.4.4 SMI/SCI Generation.................................................................117

5.3 Gigabit Ethernet Controller (B0:D25:F0) .............................................................118

5.3.1 GbE PCI Bus Interface............ .. ................................ .. .. .. ..................... ..118

5.3.1.1 Transaction Layer....................................................................118

5.3.1.2 Data Alignment.......................................................................118

5.3.1.3 Configuration Request Retry Status ...........................................119

5.3.2 Error Events and Error Reporting ............................................................119

5.3.2.1 Data Parity Error.....................................................................119

5.3.2.2 Completion with Unsuccessful Completio n Statu s............... .. .. .. .. ..119

5.3.3 Ethernet Interface ................................................................................119

5.3.3.1 MAC/LAN Connect Interface......................................................119

5.3.4 PCI Power Management.........................................................................120

5.3.4.1 Wake-Up................................................................................120

5.3.5 Configurable LEDs.................................................................................122

5.3.6 Intel® Auto Connect Battery Save r (Mobile Only)...... ... .. .. .. .. .. .. ............. .. ..122

5.3.6.1 Partial and Full Power Down Options ..........................................123

5.3.6.2 Intel® ACBS Signal Configurations.............................................123

5.4 LPC Bridge (w/ System and Management Functions) (D31:F0)...............................124

5.4.1 LPC Interface .......................................................................................124

5.4.1.1 LPC Cycle Types......................................................................125

5.4.1.2 Start Field Definition................................................................125

5.4.1.3 Cycle Type / Direction (CYCTYPE + DIR).....................................126

5.4.1.4 Size.......................................................................................126

5.4.1.5 SYNC.....................................................................................127

5.4.1.6 SYNC Time-Out.......................................................................127

5.4.1.7 SYNC Error Indication ..............................................................127

5.4.1.8 LFRAME# Usage........................ .. .. .......... ... .. .......... .. .. ........... ..127

5.4.1.9 I/O Cycles..............................................................................128

5.4.1.1 0 Bus Master Cycles .......... .. ........... .. .. ........... .. .. ..................... .. ..128

5.4.1.11 LPC Power Management...........................................................128

5.4.1.12 Configuration and Intel® ICH8 Implications.......... .. .. .. .. ............. ..128

5.5 DMA Operation (D31:F0 ) ............. .. .. .......... .. .. ... .......... .. .. ..................... ... .. .. ......129

5.5.1 Channel Priority....................................................................................129

5.5.1.1 Fixed Priority..........................................................................130

5.5.1.2 Rotating Priority......................................................................130

5.5.2 Address Compatibility Mode ...................................................................130

5.5.3 Summary of DMA Transfer Sizes.............................................................131

5.5.3.1 Address Shifting When Programmed for 16-Bit I/O Count by Words131

5.5.4 Autoinitialize........................................................................................131

5.5.5 Software Commands.............................................................................132

Intel® ICH8 Family Datasheet 5

5.6 LPC DMA........................................................................................................ 132

5.6.1 Asserting DMA Requests........................................................................ 132

5.6.2 Abandoning DMA Re q u e s ts ............... ... ..................... .. .. ..................... .. .. 133

5.6.3 General Flow of DMA Transfers............................................................... 133

5.6.4 Terminal Count.................................................................................... 133

5.6.5 Verify Mode......................................................................................... 134

5.6.6 DMA Request Deassertion...................................................................... 134

5.6.7 SYNC Field / LDRQ# Rules..................................................................... 135

5.7 8254 Timers (D31:F0) ..................................................................................... 135

5.7.1 Timer Programming.............................................................................. 136

5.7.2 Reading from the Interval Timer............................................................. 137

5.7.2.1 Simple Read........................................................................... 137

5.7.2.2 Counter Latch Command. .. .. ... ..................... .. .. .. ..................... .. 137

5.7.2.3 Read Back Command .............................................................. 138

5.8 8259 Interrupt Controllers (PIC) (D31:F0).......................................................... 139

5.8.1 Interrupt Handling................................................................................ 140

5.8.1.1 Generating Interrupts.............................................................. 140

5.8.1.2 Acknowledging Interrupts ........................................................ 140

5.8.1.3 Hardware/Software Interrupt Sequence..................................... 141

5.8.2 Initialization Command Words (ICWx)..................................................... 141

5.8.2.1 ICW1 .................................................................................... 141

5.8.2.2 ICW2 .................................................................................... 142

5.8.2.3 ICW3 .................................................................................... 142

5.8.2.4 ICW4 .................................................................................... 142

5.8.3 Operation Command Words (OCW)......................................................... 142

5.8.4 Modes of Operation ................. .. .. .. ..................... ... .. .. ..................... .. .. .. 143

5.8.4.1 Fully Nested Mode................................................................... 143

5.8.4.2 Special Fully-Nested Mode........................................................ 143

5.8.4.3 Automatic Rotation Mode (Equal Priority Devices)........................ 143

5.8.4.4 Specific Rotation Mode (Specific Priority).................................... 143

5.8.4.5 Poll Mode..... ... .. .......... .. .. ........... .. .. ........... .. .. .......... ... .. .......... 144

5.8.4.6 Cascade Mode......... .. .. ........... .. .. .......... ... .. .......... .. .. ........... .. .. 144

5.8.4.7 Edge and Level Triggered Mode ................................................ 144

5.8.4.8 End of Interrupt (EOI) Operations ............................................. 144

5.8.4.9 Normal End of Interrupt........................................................... 144

5.8.4.10 Automatic End of Interrupt Mode .............................................. 145

5.8.5 Masking Interrupts ............................................................................... 145

5.8.5.1 Masking on an Individual Interrupt Request................................ 145

5.8.5.2 Special Mask Mode.................................................................. 145

5.8.6 Steering PCI Interrupts......................................................................... 145

5.9 Advanced Programmable Interrupt Controller (APIC) (D31:F0) .............................. 146

5.9.1 Interrupt Handling................................................................................ 146

5.9.2 Interrupt Mapping ................................................................................ 146

5.9.3 PCI / PCI Express* Message-Based Interrupts.......................................... 147

5.9.4 Front Side Bus Interrupt Delivery ......... .. ............ ............. ............. .......... 147

5.9.4.1 Edge-Trig ge re d Ope ration......................... .. .. ..................... .. .. .. 148

5.9.4.2 Level-Trigge r e d Ope ration............ ..................... .. .. ................... 148

5.9.4.3 Registers Associated with Front Side Bus Interrupt Delivery.......... 148

5.9.4.4 Interrupt Message Format............ .. .. .. ...................................... 148

5.10 Serial Interrupt (D31:F0 ) ....... ... .. .......... .. .. .. ........... .. .. ..................... .. ... ............ 149

5.10.1 Start Frame......................................................................................... 150

5.10.2 Data Frames........................................................................................ 150

5.10.3 Stop Frame ....... .. ........... .. .. .......... .. ... .......... .. .. ........... .. .. ........... .. .. .. .... 150

5.10.4 Specific Interrupts Not Supported via SERIRQ.......................................... 151

5.10.5 Data Frame Format .............................................................................. 151

6Intel® ICH8 Family Datasheet

5.11 Real Time Clock (D31:F0).................................................................................152

5.11.1 Update Cycles ......................................................................................152

5.11.2 Interrupts............................................................................................153

5.11.3 Lockable RAM Ranges............................................................................153

5.11.4 Century Rollover.................. .......... .. .. ........... .. .. ........... .. .. ........... .. ........153

5.11.5 Clearing Battery-Backed RTC RAM...........................................................153

5.12 Processor Interface (D31:F0) ............................................................................155

5.12.1 Processor Interface Signals ....................................................................155

5.12.1. 1 A20M# (Mask A20)..... .. .. ........... .. .. ..................... .. .. ........... .. .. ..155

5.12.1.2 INIT# (Initialization)................................................................156

5.12.1.3 FERR#/IGNNE# (Numeric Coprocessor Error/ Ignore

Numeric Error)........................................................................157

5.12.1.4 NMI (Non-Maskable Interrupt) ..................................................157

5.12.1.5 Stop Clock Request and CPU Sleep (STPCLK# and

CPUSLP#) ..............................................................................157

5.12.1.6 CPU Power Good (CPUPWRGOOD) .............................................157

5.12.1.7 Deeper Sleep (DPSL P #) (Mob ile Only)................. .. .. ............. .. ....158

5.12.2 Dual-Processor Issues (Desktop Only) .....................................................158

5.12.2.1 Signal Differen ce s .......... .. ..................... .. ... .. .......... .. .. .............158

5.12.2.2 Power Management .................................................................158

5.13 Power Mana ge me nt (D3 1:F0 )........... .. .. .......... ... .. ..................... .. .. .....................159

5.13.1 Features..............................................................................................159

5.13.2 Intel® ICH8 and System Power States......... .......................................... ..160

5.13.3 System Power Plan es ................... .. .. ........... .. .. ........... .. .. ..................... ..162

5.13.4 SMI#/SCI Generation............................................................................162

5.13.4.1 PCI Express* SCI ....................................................................165

5.13.4.2 PCI Express* Hot-Plug .............................................................165

5.13.5 Dynamic Processor Clock Control ............................................................165

5.13.5.1 Slow C4 Exit (Mobile Only) .......................................................166

5.13.5.2 Transition Rules among S0/Cx and Throttling States ....................167

5.13.5.3 Deferred C3/C4 (Mobile Only) ...................................................167

5.13.5.4 POPUP (Auto C3/C4 to C2) (Mobile Only)....................................167

5.13.5.5 POPDOWN (Auto C2 to C3/C4) (Mobile Only)................... ............168

5.13.6 Dynamic PCI Clock Control (Mobile Only) .................................................168

5.13.6.1 Conditions for Checking the PCI Clock........................................168

5.13.6.2 Conditions for Maintaining the PCI Clock.....................................168

5.13.6.3 Conditions for Stopping the PCI Clock ........................................168

5.13.6.4 Conditions for Re-Starting the PCI Clock.....................................169

5.13.6.5 LPC Devices and CLKRUN#.......................................................169

5.13.7 Sleep States ........................................................................................169

5.13.7.1 Sleep State Overview...............................................................169

5.13.7.2 Initiating Sleep State...............................................................169

5.13.7.3 Exiting Sleep States.................................................................170

5.13.7.4 PCI Express* WAKE# Signal and PME Even t Messag e......... .. .. .. .. ..172

5.13.7.5 Sx-G3-Sx, Handling Power Failures............................................172

5.13.8 Thermal Manage me nt................. ..................... .. .. .. ........... .. .. .................173

5.13.8. 1 THRM# Signal................ .. .. ........... .. .. ........... .. .. .......... ... .. ........173

5.13.8.2 Software Initiated Passive Cooling .............................................173

5.13.8.3 THRM# Override Softw are Bit ........................................... ........173

5.13.8.4 Active Cooling.........................................................................173

5.13.9 Event Input Signals and Their Usage .......................................................174

5.13.9.1 PWRBTN# (Power Button) ........................................................174

5.13.9.2 RI# (Ring Indicator)........... .. ... ............ ............. ............. ..........175

5.13.9.3 PME# (PCI Power Management Event) .......................................175

5.13.9.4 SYS_RESET# Signal ................................................................175

5.13.9.5 THRMTRIP# Signal ..................................................................176

5.13.9.6 BMBUSY# (Mobile Only)...........................................................176

Intel® ICH8 Family Datasheet 7

5.13.10ALT Access Mode.................................................................................. 177

5.13.10.1Write Only Re g isters with Read Paths in ALT Access Mode ............ 177

5.13.10.2PIC Reserved Bits ................................................................... 179

5.13.10.3Read Only Registers with Write Paths in ALT Access Mode ....... .. ... 180

5.13.11System Power Supplies, Planes, and Signals ............................................ 180

5.13.11.1Power Plane Control with SLP_S3#, SLP_S4#, SLP_S5#

and SLP_M# .......................................................................... 180

5.13.11.2SL P _S 4 # and Susp e nd-T o -RA M Se q ue n cing .......... .. ................... 181

5.13.11.3PWROK Signal........................................................................ 181

5.13.11.4CPUPWRGD Signal .................................................................. 181

5.13.11.5VRMPWRGD Signal.................................................................. 181

5.13.11.6BA TLO W# (Battery Lo w) (Mob ile Only)............. .. .. .. .. .. ............. .. 182

5.13.11.7Controlling Leakage and Power Consumption

during Low-Po we r States ............. .......... ... .. .. .......... .. ... ............ 182

5.13.12Clock Generators.................................................................................. 182

5.13.12.1Clock Control Signals from Intel® ICH8 to Clock

Synthesizer (Mobile Only) ........................................................ 183

5.13.13Legacy Power Management Theory of Operation....................................... 183

5.13.13.1APM Power Management (Desktop Only).................................... 183

5.13.13.2Mobile AP M Pow er Management (Mobile Only) .................. .. .. ...... 183

5.14 System Management (D31:F0).......................................................................... 184

5.14.1 Theory of Operation.............................................................................. 184

5.14.1.1 Detecting a System Lockup...................................................... 184

5.14.1.2 Handling an Intruder............................................................... 184

5.14.1.3 Detecting Improper Firmware Hub Programming. ........................ 185

5.14.2 TCO Modes....................... .. .......... .. ... .......... .. ........... .. .. ........... .. .......... 185

5.14.2.1 TCO Legacy/Compatible Mode .................................................. 185

5.14.2.2 Advanced TCO Mode ............................................................... 187

5.14.2.3 Advanced TCO BMC Mode ........................................................ 187

5.15 IDE Controller (D31:F1) (Mobile Only)................................................................ 189

5.15.1 PIO Transfers ...................................................................................... 189

5.15.1.1 PIO IDE Timing Modes............................................................. 189

5.15.1.2 IORDY Masking. ...................................................................... 190

5.15.1.3 PIO 32-Bit IDE Data Port Accesses ............... .. .. ............. .. .. ........ 190

5.15.1.4 PIO IDE Data Port Prefetching and Posting ................................. 190

5.15.2 Bus Master Function ............................................................................. 191

5.15.2.1 Physical Region Descriptor Format ............................................ 191

5.15.2.2 Bus Master IDE Timings........................................................... 192

5.15.2.3 Interrupts.............................................................................. 192

5.15.2.4 Bus Master IDE Operation........................................................ 192

5.15.2.5 Error Conditions....... .. .. ............. .............................................. 193

5.15.3 Ultra ATA/100/66/33 Protocol ................................................................ 194

5.15.3.1 Operation .............................................................................. 194

5.15.4 Ultra ATA/33/66/100 Timing.................................................................. 195

5.15.5 ATA Swap Bay ..................................................................................... 195

5.15.6 SMI Trapping.................. .......... .. .. ........... .. .. ........... .. .. .......... ... .......... .. 195

5.16 SATA Host Controller (D31:F2, F5) ... ....................... ....................... ................... 196

5.16.1 Theory of Operation.............................................................................. 197

5.16.1.1 Standard ATA Emulation .......................................................... 197

5.16.1.2 48-Bit LBA Operation............... .. .. ............. ............................... 197

5.16.2 SATA Swap Bay Sup p o rt ....................... .. .. .......... ... .......... .. .. ........... .. .. .. 198

5.16.3 Intel® Matrix Storage Technology Configuration (Intel® IC H8 R,

ICH8DH, ICH8DO, and ICH8M-E Only) .................................................... 198

5.16.3.1 Intel® Matrix Storage Manager RAID Option ROM........................ 199

5.16.4 Power Management Operation................................................................ 199

5.16.4.1 Power State Mappings ............................................................. 199

5.16.4.2 Power State Transitions........................................................... 200

8Intel® ICH8 Family Datasheet

5.16.4.3 SMI Trapping (AP M ).................................... .. .. ..................... .. ..201

5.16.5 SATA LED............................................................................................201

5.16.6 AHCI Operation ....................................................................................201

5.16.7 Serial ATA Reference Clock Low Power Request (SATACLKREQ#) ................202

5.16.8 SGPIO Signals......................................................................................202

5.16.9 External SATA (Intel® ICH8R, ICH8DH, and ICH8DO Only).........................202

5.17 High Precision Event Timers ..............................................................................203

5.17.1 Timer Accuracy ....................................................................................203

5.17.2 Interrupt Mapping.................................................................................203

5.17.3 Periodic vs. Non-Periodic Modes..............................................................204

5.17.4 Enabling the Tim er s ................. .. ........... .. .. .......... .. ... .. .......... .. .. ........... ..204

5.17.5 Interrupt Levels....................................................................................205

5.17.6 Handling Interrupts...............................................................................205

5.17.7 Issues Related to 64-Bit Timers with 32-Bit Processors ..............................205

5.18 USB UHCI Host Controllers (D29:F0, F1, F2 and D26:F0, F1).................................206

5.18.1 Data Structures in Main Memory.............................................................206

5.18.2 Data Transfers to/from Main Memory ......................................................206

5.18.3 Data Encoding and Bit Stuffing ...............................................................206

5.18.4 Bus Protocol .........................................................................................206

5.18.4.1 Bit Ordering................................ .. .. ..................... .. .. ...............206

5.18.4.2 SYNC Field .............................................................................206

5.18.4.3 Packet Field Formats................................................................206

5.18.4.4 Address Fields.........................................................................207

5.18.4.5 Frame Number Field ................................................................207

5.18.4.6 Data Field ..............................................................................207

5.18.4.7 Cyclic Redundancy Check (CRC)................................................207

5.18.5 Packet Formats ....................................................................................207

5.18.6 USB Interrupts .....................................................................................207

5.18.6.1 Transaction-Based Interrupts....................................................207

5.18.6.2 Non-Transaction Based Interrupts ............................ .. ............. ..209

5.18.7 USB Power Management........................................................................210

5.18.8 USB Legacy Keyboard Operation.............................................................210

5.19 USB EHCI Host Controllers (D29:F7 and D26:F7).................................................213

5.19.1 EHC Initialization..................................................................................213

5.19.1.1 BIOS Initialization ...................................................................213

5.19.1.2 Driver Initialization..................................................................213

5.19.1. 3 EHC Resets ................... .. .. .. ........... .. .. ........... .. .. ........... .. .. ......214

5.19.2 Data Structures in Main Memory.............................................................214

5.19.3 USB 2.0 Enhanced Host Controller DMA ...................................................214

5.19.4 Data Encoding and Bit Stuffing ...............................................................214

5.19.5 Packet Formats ....................................................................................214

5.19.6 USB 2.0 Interrupts and Error Conditions ..................................................215

5.19.6.1 Aborts on USB 2.0-Initiated Me mory Re ad s........................... .. ....215

5.19.7 USB 2.0 Power Management ..................................................................216

5.19.7.1 USB Pre-Fetch Pause Feature.............. ....................... ...............216

5.19.7.2 Suspend Feature.....................................................................216

5.19.7.3 ACPI Device States..................................................................216

5.19.7.4 ACPI System States.................................................................217

5.19.7.5 Mobile Considerations ..............................................................217

5.19.8 Interaction with UHCI Host Controllers......... .. .. .. ............. .. ............. .. ........217

5.19.8.1 Port-Routing Logic...................................................................217

5.19.8.2 Device Connects ................ .. ........... .. .. ..................... .. ... ..........218

5.19.8.3 Device Disconnects........... .. ................................ .. .. .. ...............219

5.19.8.4 Effect of Resets on Port-Routing Logic........................................219

5.19.9 USB 2.0 Legacy Keyboard Operation .......................................................219

5.19.10USB 2.0 Based Debug Port.....................................................................220

Intel® ICH8 Family Datasheet 9

5.19.10.1 Theory of Operation ............................................................... 220

5.20 SMBus Controller (D31:F3)............................................................................... 225

5.20.1 Host Controller..................................................................................... 225

5.20.1.1 Command Protocols ................................................................ 226

5.20.2 Bus Arbitration..................................................................................... 229

5.20.3 Bus Timing.......................................................................................... 230

5.20.3.1 Clock Stretching ..................................................................... 230

5.20.3.2 Bus Time Out (Intel® ICH8 as SMBus Master)............................. 230

5.20.4 Interrupts / SMI#................................................................................. 230

5.20.5 SMBALERT# ........................................................................................ 232

5.20.6 SMBus CRC Generation and Checking...................................................... 232

5.20.7 SMBus Slave Interface .......................................................................... 232

5.20.7.1 Format of Slave Write Cycle ..................................................... 233

5.20.7.2 Format of Read Command........................................................ 235

5.20.7.3 Format of Host Notify Command ............................................... 237

5.21 Intel® High Definition Audio Overview................................................................ 238

5.21.1 Intel® High Definition Audio Docking (Mobile Only)................................... 238

5.21.1.1 Dock Sequence....................................................................... 238

5.21.1.2 Exiting D3/CRST# when Docked ............................................... 239

5.21.1.3 Cold Boot/Resume from S3 When Docked .................................. 240

5.21.1.4 Undock Sequen ce ................. .. .. .. .......... ... .. .......... .. .. ........... .. .. 240

5.21.1.5 Interaction Between Dock/Undock and Power Management States. 241

5.21.1.6 Relationship between HDA_DOCK_RST# and HDA_RST# .... ......... 241

5.22 Intel® Active Man a gement Technology (Intel® AM T) (Intel® ICH8DO and

ICH8M-E Only)) .............................................................................................. 242

5.22.1 Intel® AMT Features............................................................................. 242

5.22.2 Intel® AMT Requirements...................................................................... 242

5.23 Serial Peripheral Interface (SPI)........................................................................ 243

5.23.1 SPI Supported Feature Overview............................................................ 243

5.23.1.1 Flash Descriptor...................................................................... 244

5.23.1.2 Flash Access .......................................................................... 245

5.23.1.3 Program Register Software Sequencing...................................... 245

5.23.1.4 Direct Access Security ............................................................. 245

5.23.1.5 Register Access Security.......................................................... 245

5.23.2 SPI Device Compatibility Requirements ................................................... 246

5.23.2.1 Device Requirements for System BIOS Storage Only ................... 246

5.23.2.2 Device Requirements for Intel® AMT, ASF and AFSC

Firmware............................................................................... 246

5.23.2.3 Device Requirements for GbE ................................................... 247

5.23.3 Serial Flash Command Set..................................................................... 247

5.23.3.1 Required Command Set for Interoperability................................ 247

5.23.3.2 Recommended Command Set and Opcodes................................ 248

5.23.3.3 JEDEC Device Identification...................................................... 248

5.23.3.4 Multiple Page Write Usage Model............................................... 248

5.24 Intel® Quiet System Technology (Desktop Only) ................................................. 249

5.24.1 PWM Outputs..... ........... .. .. .......... .. .. ........... .. .. ........... .. .. .. ........... .. .. ...... 249

5.24.2 TACH Inputs............ .. ........... .. ........... .. .. .......... .. ... .......... .. .. ........... .. .... 249

5.25 Thermal Sensors ............................................................................................. 249

5.26 Intel® Quick Resume Technology (Intel® ICH8DH On ly)........ .. .. .. .......... ... .. .......... 250

5.26.1 5.26.1 Visual Off.................................................................................. 250

5.26.2 5.26.2 CE-like On/Off ........................................................................... 250

5.26.3 Intel® Quick Resume Technology Signals................................................. 250

5.26.4 Power Button Sequence ........................................................................ 251

5.27 Feature Capability Mechanism........................................................................... 251

5.28 Serial POST Codes Over GPIO........................................................................... 252

5.28.1 Theory of operation.............................................................................. 252

10 Intel® ICH8 Family Datasheet

5.28.2 Serial Message Format ..........................................................................253

6 Register and Memory Mapping...............................................................................255

6.1 PCI Devices and Functions ................................................................................255

6.2 PCI Configuration Map......................................................................................257

6.3 I/O Map..........................................................................................................257

6.3.1 Fixed I/O Address Ranges......................................................................257

6.3.2 Variable I/O Decode Ranges...................................................................260

6.4 Memory Map...................................................................................................261

6.4.1 Boot-Block Update Scheme....... .. ............. .. .. ............. ............ ............. ....263

7 Chipset Configuration Registers.............................................................................265

7.1 Chipset Configuration Registers (Memory Space) .................................................265

7.1.1 VCH—Virtual Channel Capability Header Register ......................................268

7.1.2 VCAP1—Virtual Channel Capability #1 Register.........................................268

7.1.3 VCAP2—Virtual Channel Capability #2 Register.........................................268

7.1.4 PVC—Port Virtual Channel Control Register...............................................269

7.1.5 PVS—Port Virtual Channel Status Register................................................269

7.1.6 V0CAP—Virtual Channel 0 Resource Capability Register..............................269

7.1.7 V0CTL—Virtual Channel 0 Resource Control Register .................................270

7.1.8 V0STS—Virtual Channel 0 Resource Status Reg ister ..... .. .. .. .. .. .. ............. .. ..270

7.1.9 V1CAP—Virtual Channel 1 Resource Capability Register..............................271

7.1.10 V1CTL—Virtual Channel 1 Resource Control Register .................................271

7.1.11 V1STS—Virtual Channel 1 Resource Status Register ..................................272

7.1.12 PAT—Port Arb itration Ta b le ........... .. ..................... .. ... .. ...........................272

7.1.13 CIR1—Chipset Initialization Register 1 .....................................................272

7.1.14 RCTCL—Root Complex Topology Capabilities List Register ........ ..................273

7.1.15 ESD—Element Self Description Register...................................................273

7.1.16 ULD—Upstream Link De scriptor Reg i ste r............ .. ............. .. ............. .. ......273

7.1.17 ULBA—Upstream Link Base Address Register............................................274

7.1.18 RP1D—Root Port 1 Descriptor Register.....................................................274

7.1.19 RP1BA—Root Port 1 Base Address Register...............................................274

7.1.20 RP2D—Root Port 2 Descriptor Register.....................................................275

7.1.21 RP2BA—Root Port 2 Base Address Register...............................................275

7.1.22 RP3D—Root Port 3 Descriptor Register.....................................................275

7.1.23 RP3BA—Root Port 3 Base Address Register...............................................276

7.1.24 RP4D—Root Port 4 Descriptor Register.....................................................276

7.1.25 RP4BA—Root Port 4 Base Address Register...............................................276

7.1.26 HDD—Intel® High Definition Audio Descriptor Register...............................277

7.1.27 HDBA—Intel® High Definition Audio Base Address Register.........................277

7.1.28 RP5D—Root Port 5 Descriptor Register.....................................................277

7.1.29 RP5BA—Root Port 5 Base Address Register...............................................278

7.1.30 RP6D—Root Port 6 Descriptor Register.....................................................278

7.1.31 RP6BA—Root Port 6 Base Address Register...............................................278

7.1.32 ILCL—Internal Link Capabilities List Register ............................................279

7.1.33 LCAP—Link Capabilities Register .............................................................279

7.1.34 LCTL—Link Control Register ...................................................................280

7.1.35 LSTS—Link Status Register ....................................................................280

7.1.36 CIR2 — Chipset Initialization Register 2...................................................280

7.1.37 CIR3 — Chipset Initialization Register 3...................................................281

7.1.38 CIR4 — Chipset Initialization Register 4...................................................281

7.1.39 BCR — Backbone Configuration Register ..................................................281

7.1.40 RPC—Root Port Configuration Register.....................................................282

7.1.41 DMIC—DMI Contro l Reg i ste r................... .......................................... .. .. ..282

7.1.42 RPFN—Root Port Function Number for PCI Express* Root Ports...................283

7.1.43 CIR5—Chipset Initialization Register 5 .....................................................284

Intel® ICH8 Family Datasheet 11

7.1.44 TRSR—Trap Status Register................................................................... 284

7.1.45 TRCR—Trapped Cycle Register ............................................................... 284

7.1.46 TWDR—Trapped Write Data Register....................................................... 285

7.1.47 IOTRn — I/O Trap Register (0–3) ........................................................... 285

7.1.48 DMC—DMI Miscellaneous Control Register (Mobile Only)............................ 286

7.1.49 CIR6—Chipset Initialization Regi ster 6 (Mobile Only)............. ............... ..... 286

7.1.50 CIR 7—Chipset Initialization Register 7..................................................... 286

7.1.51 TCTL—TCO Configuration Register .......................................................... 287

7.1.52 D31IP—Device 31 Interrupt Pin Register.................................................. 288

7.1.53 D30IP—Device 30 Interrupt Pin Register.................................................. 289

7.1.54 D29IP—Device 29 Interrupt Pin Register.................................................. 289

7.1.55 D28IP—Device 28 Interrupt Pin Register.................................................. 290

7.1.56 D27IP—Device 27 Interrupt Pin Register.................................................. 291

7.1.57 D26IP—Device 26 Interrupt Pin Register.................................................. 291

7.1.58 D25IP—Device 25 Interrupt Pin Register.................................................. 292

7.1.59 D31IR—Device 31 Interrupt Route Register ............................................. 292

7.1.60 D30IR—Device 30 Interrupt Route Register ............................................. 293

7.1.61 D29IR—Device 29 Interrupt Route Register ............................................. 293

7.1.62 D28IR—Device 28 Interrupt Route Register ............................................. 295

7.1.63 D27IR—Device 27 Interrupt Route Register ............................................. 296

7.1.64 D26IR—Device 26 Interrupt Route Register ............................................. 297

7.1.65 D25IR—Device 25 Interrupt Route Register ............................................. 298

7.1.66 OIC—Other Interrupt Control Register..................................................... 299

7.1.67 RC—RTC Configuration Register ............................................................. 299

7.1.68 HPTC—High Precision Timer Configuration Register................................... 300

7.1.69 GCS—General Control and Status Register............................................... 301

7.1.70 BUC—Backed Up Control Register........................................................... 303

7.1.71 FD—Function Disable Register................................................................ 303

7.1.72 CG—Clock Gating (Mobile Only)....... ............. ............. ............ ............. .... 306

7.1.73 FDSW—Function Disable SUS Well.......................................................... 307

7.1.74 CIR 8—Chipset Initialization Register 8..................................................... 308

7.1.75 CIR 9—Chipset Initialization Register 9..................................................... 308

8 Gigabit LAN Configuration Registers...................................................................... 309

8.1 Gigabit LAN Configuration Registers

(Gigabit LAN — D25:F0)................................................................................... 309

8.1.1 VID—Vendor Identification Register

(Gigabit LAN—D25:F0)................... ........................................... .. .. .. ...... 310

8.1.2 DID—Device Identification Register

(Gigabit LAN—D25:F0)................... ........................................... .. .. .. ...... 310

8.1.3 PCICM D—PCI Command Register

(Gigabit LAN—D25:F0)................... ........................................... .. .. .. ...... 311

8.1.4 PCISTS—PCI Status Register

(Gigabit LAN—D25:F0)................... ........................................... .. .. .. ...... 312

8.1.5 RID —Revision Identification Register

(Gigabit LAN—D25:F0)................... ........................................... .. .. .. ...... 313

8.1.6 CC—Class Code Register

(Gigabit LAN—D25:F0)................... ........................................... .. .. .. ...... 313

8.1.7 CLS—Cache Line Size Register

(Gigabit LAN—D25:F0)................... ........................................... .. .. .. ...... 313

8.1.8 PLT—Primary Latency Timer Register

(Gigabit LAN—D25:F0)................... ........................................... .. .. .. ...... 313

8.1.9 HT—Header Type Register

(Gigabit LAN—D25:F0)................... ........................................... .. .. .. ...... 313

8.1.10 MBARA—Memory Base Address Register A

(Gigabit LAN—D25:F0)................... ........................................... .. .. .. ...... 314

12 Intel® ICH8 Family Datasheet

8.1.11 MBARB—Memory Base Address Register B

(Gigabit LAN—D25:F0) ..........................................................................314

8.1.12 MBARC—Memory Base Address Register C

(Gigabit LAN—D25:F0) ..........................................................................315

8.1.13 SID—Subsystem ID Register

(Gigabit LAN—D25:F0) ..........................................................................315

8.1.14 SVID—Subsystem Vendor ID Regist er

(Gigabit LAN—D25:F0) ..........................................................................315

8.1.15 ERBA—Expansion ROM Base Address Register

(Gigabit LAN—D25:F0) ..........................................................................316

8.1.16 CAPP—Capabilities List Pointer Register

(Gigabit LAN—D25:F0) ..........................................................................316

8.1.17 INTR—Interrupt Information Register

(Gigabit LAN—D25:F0) ..........................................................................316

8.1.18 MLMG—Maximum Latency/Minimum Grant Register

(Gigabit LAN—D25:F0) ..........................................................................316

8.1.19 CLIST 1—Capabilities List Register 1

(Gigabit LAN—D25:F0) ..........................................................................317

8.1.20 PMC—PCI Power Management Capabilities Register

(Gigabit LAN—D25:F0) ..........................................................................317

8.1.21 PMCS—PCI Power Management Control and Status

8.1.22 DR—Data Register

(Gigabit LAN—D25:F0) ..........................................................................318

8.1.23 CLIST 2—Capabilities List Register 2

(Gigabit LAN—D25:F0) ..........................................................................319

8.1.24 MCTL—Message Control Register

(Gigabit LAN—D25:F0) ..........................................................................319

8.1.25 MADDL—Message Address Low Register

(Gigabit LAN—D25:F0) ..........................................................................319

8.1.26 MADDH—Message Address High Register

(Gigabit LAN—D25:F0) ..........................................................................320

8.1.27 MDAT—Message Data Register

(Gigabit LAN—D25:F0) ..........................................................................320

8.2 GBAR0—Gigabit LAN Base Address Register 0 Registers. .......................................321

8.2.1 LDCR1—LAN Device Control Register 1

(Gigabit LAN Memory Mapped Base Address Register) ............................ ...321

8.2.2 LDCR2—LAN Device Control Register 2

(Gigabit LAN Memory Mapped Base Address Register) ............................ ...321

8.2.3 LDR1—LAN Device Initialization Register 1

(Gigabit LAN Memory Mapped Base Address Register) ............................ ...321

8.2.4 EXTCNF_CTRL—Extended Configuration Control Register

(Gigabit LAN Memory Mapped Base Address Register) ............................ ...322

8.2.5 LDR2—LAN Device Initialization Register 2

(Gigabit LAN Memory Mapped Base Address Register) ............................ ...322

9 LPC Interface Bridge Registers (D31:F0) ...............................................................323

9.1 PCI Configuration Registers (LPC I/F—D31:F0) ....................................................323

9.1.1 VID—Vendor Identification Register (LPC I/F—D31:F0) ..............................324

9.1.2 DID—Device Identification Register (LPC I/F—D31:F0)...............................324

9.1.3 PCICMD—PCI COMMAND Register (LPC I/F—D31:F0).................................325

9.1.4 PCISTS—PCI Status Register (LPC I/F—D31:F0)........................................325

9.1.5 RID—Revision Identification Register (LPC I/F—D31:F0) ............... ... ..........326

9.1.6 PI—Programming Interf ace Register (LPC I/F—D31:F0) ..... ........................326

9.1.7 SCC—Sub Class Cod e Register (LPC I/F—D31 : F0 ) ............ .. .......................327

9.1.8 BCC—Base Class Code Register (LPC I/F—D31:F0)....................................327

9.1.9 PLT—Primary Latency Timer Register (LPC I/F—D31:F0)............................327

Intel® ICH8 Family Datasheet 13

9.1.10 HEADTYP—Header Type Register (LPC I/F—D31:F0) ................................. 327

9.1.11 SS—Sub System Identifiers Register (LPC I/F—D31:F0) ............................ 328

9.1.12 PMBASE—ACPI Base Address Register (LPC I/F—D31:F0) .......................... 328

9.1.13 ACPI_CNTL—ACPI Control Register (LPC I/F — D31:F0)............................. 329

9.1.14 GPIOBASE—GPIO Base Add ress Re g ister (LP C I/F — D31: F0)........... .. .. .. .. .. 329

9.1.15 GC—GPIO Control Register (LPC I/F — D31:F0)......... ............ .. .. ............. .. 330

9.1.16 PIRQ[n]_ROUT—PIRQ[A,B,C,D] Routing Control Register

(LPC I/F—D31:F0)................................................................................ 330

9.1.17 SIRQ_CNTL—Serial IRQ Control Register

(LPC I/F—D31:F0)................................................................................ 331

9.1.18 PIRQ[n]_ROUT—PIR Q[E,F,G,H] Routing Control Register

(LPC I/F—D31:F0)................................................................................ 332

9.1.19 LPC_I/O_DEC—I/O De code Ranges Register

(LPC I/F—D31:F0)................................................................................ 333

9.1.20 LPC_EN—LPC I/F Enables Register (LPC I/F—D31:F0) ............................... 334

9.1.21 GEN1_DEC—LPC I/F Generic Decode Range 1 Register

(LPC I/F—D31:F0)................................................................................ 335

9.1.22 GEN2_DEC—LPC I/F Generic Decode Range 2Register

(LPC I/F—D31:F0)................................................................................ 335

9.1.23 GEN3_DEC—LPC I/F Generic Decode Range 3Register

(LPC I/F—D31:F0)................................................................................ 336

9.1.24 GEN4_DEC—LPC I/F Generic Decode Range 4Register

(LPC I/F—D31:F0)................................................................................ 336

9.1.25 FWH_SEL1—Firmware Hub Select 1 Register

(LPC I/F—D31:F0)................................................................................ 337

9.1.26 FWH_SEL2—Firmware Hub Select 2 Register

(LPC I/F—D31:F0)................................................................................ 338

9.1.27 FWH_DEC_EN1—Firmware Hub Decode Enable Register

(LPC I/F—D31:F0)................................................................................ 338

9.1.28 BIOS_CNTL—BIOS Control Register

(LPC I/F—D31:F0)................................................................................ 341

9.1.29 FDCAP—Feature Detection Capability ID

(LPC I/F—D31:F0)................................................................................ 341

9.1.30 FDLEN—Feature Detection Capability Length

(LPC I/F—D31:F0)................................................................................ 342

9.1.31 FDVER—Feature Detection Version

(LPC I/F—D31:F0)................................................................................ 342

9.1.32 FDVCT—Feature Vector

(LPC I/F—D31:F0)................................................................................ 342

9.1.33 RCBA—Root Complex Base Address Register

(LPC I/F—D31:F0)................................................................................ 343

9.2 DMA I/O Registers (LPC I/F—D31:F0) .......................... .. .. ...................... .. .. .. ...... 344

9.2.1 DMABASE_CA—DMA Base and Current Address

Registers (LPC I/F—D31:F0).................................................................. 345

9.2.2 DMABASE_CC—DMA Base and Current Count Registers

(LPC I/F—D31:F0)................................................................................ 346

9.2.3 DMAMEM_LP—DMA Memory Low Page Registers

(LPC I/F—D31:F0)................................................................................ 346

9.2.4 DMACMD—DMA Command Register (LPC I/F—D31:F0).............................. 347

9.2.5 DMASTA—DMA Status Register (LPC I/F—D31:F0).................................... 347

9.2.6 DMA_WRSMSK—DMA Write Single Mask Register

(LPC I/F—D31:F0)................................................................................ 348

9.2.7 DMACH_MODE—DMA Channel Mode Register

(LPC I/F—D31:F0)................................................................................ 349

9.2.8 DMA Clear Byte Pointer Register (LPC I/F—D31:F0) .................................. 350

9.2.9 DMA Master Clear Register (LPC I/F—D31:F0).......................................... 350

9.2.10 DMA_CLMSK—DMA Clear Mask Register (LPC I/F—D31:F0)........................ 351

14 Intel® ICH8 Family Datasheet

9.2.11 DMA_WRMSK—DMA Write All Mask Register

(LPC I/F—D31:F0) ................................................................................351

9.3 Timer I/O Registers (LPC I/F—D31:F0)...............................................................352

9.3.1 TCW—Timer Control Word Register (LPC I/F—D31:F0)...............................353

9.3.2 SBYTE_FMT—Interval Timer Status Byte Format Register

(LPC I/F—D31:F0) ................................................................................355

9.3.3 Counter Access Ports Register (LPC I/F—D31:F0)......................................356

9.4 8259 Interrupt Controller (PIC) Registers

(LPC I/F—D31:F0) ...........................................................................................356

9.4.1 Interrupt Controlle r I/O MAP (LP C I/F—D31:F0)............... .. .. .. ............. ......356

9.4.2 ICW1—Initialization Command Word 1 Register

(LPC I/F—D31:F0) ................................................................................357

9.4.3 ICW2—Initialization Command Word 2 Register

(LPC I/F—D31:F0) ................................................................................358

9.4.4 ICW3—Master Controller Initialization Command

Word 3 Register (LPC I/F—D31:F0). ........................................................358

9.4.5 ICW3 —Slave Controller Initialization Command

Word 3 Register (LPC I/F—D31:F0). ........................................................359

9.4.6 ICW4—Initialization Command Word 4 Register

(LPC I/F—D31:F0) ................................................................................359

9.4.7 OCW1—Operation al Control W ord 1 (I nterr u pt Mask )

9.4.8 OCW2—Operational Control Word 2 Register

(LPC I/F—D31:F0) ................................................................................360

9.4.9 OCW3—Operational Control Word 3 Register

(LPC I/F—D31:F0) ................................................................................361

9.4.10 ELCR1—Master Controller Edge/Level Triggered Register

(LPC I/F—D31:F0) ................................................................................362

9.4.11 ELCR2—Slave Controller Edge/Level Triggered Register

(LPC I/F—D31:F0) ................................................................................363

9.5 Advanced Programmable Interrupt Controller (APIC)(D31:F0)................................364

9.5.1 APIC Register Map (LPC I/F—D31:F0)......................................................364

9.5.2 IND—Index Register (LPC I/F—D31:F0)...................................................364

9.5.3 DAT—Data Register (LPC I/F—D31:F0)....................................................365

9.5.4 EOIR—EOI Register (LPC I/F—D3 1 : F0) ................................. ...................365

9.5.5 ID—Identification Register (LPC I/F—D31:F0)...........................................366

9.5.6 VER—Version Register (LPC I/F—D31:F0) ................................................366

9.5.7 REDIR_TBL—Redirection Table (LPC I/F—D31:F0).....................................367

9.6 Real Time Clock Registers (LPC I/F—D31:F0).......................................................369

9.6.1 I/O Register Address Map (LPC I/F—D31:F0)............................................369

9.6.2 Indexed Registers (LPC I/F—D31:F0) ......................................................370

9.6.2.1 RTC_REGA—Register A (LPC I/F—D31:F0)..................................371

9.6.2.2 RTC_REGB—Register B (General Configuration)

(LPC I/F—D31:F0)...................................................................372

9.6.2.3 RTC_REGC—Register C (Flag Register)

(LPC I/F—D31:F0)...................................................................373

9.6.2.4 RTC_REGD—Register D (Flag Register)

(LPC I/F—D31:F0)...................................................................373

9.7 Processor Interface Registers (LPC I/F—D31:F0)..................................................374

9.7.1 NMI_SC—NMI Status and Control Register

(LPC I/F—D31:F0) ................................................................................374

9.7.2 NMI_EN—NMI Enable (and Real Time Clock Index)

9.7.3 PORT92—Fast A20 and Init Register (LPC I/F—D31:F0) ...................... .......37 5

9.7.4 COPROC_ERR—Coprocessor Error Register

(LPC I/F—D31:F0) ................................................................................376

9.7.5 RST_CNT—Reset Control Register (LPC I/F—D31:F0).................................376

Intel® ICH8 Family Datasheet 15

9.8 Power Management Registers (PM—D31:F0)....................................................... 377

9.8.1 Power Management PCI Configuration Registers

(PM—D31:F0)...................................................................................... 377

9.8.1.1 GEN_PMCON_1—General PM Configuration 1 Register

(PM—D31:F0) ........................................................................ 378

9.8.1.2 GEN_PMCON_2—General PM Configuration 2 Register

(PM—D31:F0) ........................................................................ 380

9.8.1.3 GEN_PMCON_3—General PM Configuration 3 Register

(PM—D31:F0) ........................................................................ 381

9.8.1.4 GEN_PMCON_LOCK—General Power Management

Configuration Lock Register383

9.8.1.5 Cx-STATE_CNF—Cx State Configuration Register

(PM—D31:F0) (Mobile Only)..................................................... 384

9.8.1.6 C4-TIMING_CNT—C4 Timing Control Register

(PM—D31:F0) (Mobile Only)..................................................... 385

9.8.1.7 BM_BREAK_EN Register (PM—D31:F0) (Mobile Only)................... 386

9.8.1.8 PMIR—Power Management Initialization Register......................... 387

9.8.1.9 QRT_STS (PM—D31:F0): Quick Resume Technology Status

9.8.1.10 QRT_CNT1 (PM—D31:F0): Quick Resume Technology

Control 1 Register (Intel® ICH8DH Only)388

9.8.1.11 QRT_CNT2 (PM—D31:F0): Quick Resume Technology

Control 2 Register (Intel® ICH8DH Only)389

9.8.1.12 GPIO_ROUT—GPIO Routing Control Register

(PM—D31:F0) ........................................................................ 389

9.8.2 APM I/O Decode................................................................................... 390

9.8.2.1 APM_CNT—Advanced Power Management Control Port

9.8.2.2 APM_STS—Advanced Power Management Status Port

9.8.3 Power Management I/O Registers........................................................... 391

9.8.3.1 PM1_STS—Powe r Manage me nt 1 Status Reg ister.............. .. ........ 393

9.8.3.2 PM1_EN—Power Management 1 Enable Register ......................... 396

9.8.3.3 PM1_CNT—Power Management 1 Control................................... 397

9.8.3.4 PM1_TMR—Power Management 1 Timer Register......................... 398

9.8.3.5 PROC_CNT—Processor Control Register...................................... 398

9.8.3.6 LV2 — Level 2 Register (Mobile Only) ........................................ 400

9.8.3.7 LV3—Level 3 Register (Mobile Only) .......................................... 400

9.8.3.8 LV4—Level 4 Register (Mobile Only) .......................................... 400

9.8.3.9 LV5—Level 5 Register (Mobile Only) .......................................... 401

9.8.3.10 LV6—Level 6 Register (Mobile Only) .......................................... 401

9.8.3.11 PM2_CNT—Power Management 2 Control (Mobile Only)................ 401

9.8.3.12 GPE0_STS—General Purpose Event 0 Status Register ....... .. ......... 402

9.8.3.13 GPE0_EN—General Purpose Event 0 Enables Register .................. 405

9.8.3.14 SMI_EN—SMI Control and Enable Registe r ........ .. .. .. ............. .. .. .. 407

9.8.3.15 SMI_STS—SMI Status Register................................................. 409

9.8.3.16 ALT_GP_SMI_EN—Alternate GPI SMI Enable Register .................. 411

9.8.3.17 ALT_GP_SMI_STS—Alternate GPI SMI Status Register ................. 412

9.8.3.18 GPE_CNTL— General Purpose Control Register............................ 412

9.8.3.19 DEVACT_STS — Dev i ce Activity Status Regi ste r .............. ............ 413

9.8.3.20 SS_CNT— Intel SpeedStep® Technology

Control Register (Mobile Only).................................................. 414

9.8.3.21 C3_RES— C3 Residency Register (Mobile Only)........................... 414

9.8.3.22 C5_RES— C5 Residency Register (Mobile Only)........................... 415

9.9 System Management TCO Registers (D31:F0)..................................................... 416

9.9.1 TCO_RLD—TCO Timer Reload and Current Value Register .......................... 416

9.9.2 TCO_DAT_IN—TCO Data In Register....................................................... 417

9.9.3 TCO_DAT_OUT—TCO Data Out Register .................................................. 417

9.9.4 TCO1_STS—TCO1 Status Register .......................................................... 417

16 Intel® ICH8 Family Datasheet

9.9.5 TCO2_STS—TCO2 Status Register...........................................................419

9.9.6 TCO1_CNT—TCO1 Control Register .........................................................420

9.9.7 TCO2_CNT—TCO2 Control Register .........................................................421

9.9.8 TCO_MESSAGE1 and TCO_MESSAGE2 Registers .......................................421

9.9.9 TCO_WDCNT—TCO Watchdog Control Register .........................................422

9.9.10 SW_IRQ_GEN—Software IRQ Generation Register.....................................422

9.9.11 TCO_TMR—TCO Time r Initial Value Register ............. ... .. ............ .. .............422

9.10 General Purpose I/O Registers (D31:F0) .............................................................423

9.10.1 GPIO_USE_SE L—GPI O Us e Se le ct Reg iste r............. .. ... .. .. .. ............. ..........424

9.10.2 GP_IO_SEL—GPIO Input/Output Select Register .......................................424

9.10.3 GP_LVL—GPIO Level for Input or Output Register......................................425

9.10.4 GPIO_USE_SEL Override Register (LOW)—GPIO Use Select Override

9.10.5 GPO_BLINK—GPO Blink Enable Register...................................................426

9.10.6 GP_SER_BLINK[31:0]—GP Serial Blink ....................................................426

9.10.7 GP_SB_CMDS TS[31:0]—GP Serial Blink Command Status ........ ..................42 7

9.10.8 GP_SB_DATA[31:0]—GP Serial Blink Data ................................................427

9.10.9 GPI_INV—GPIO Signal Invert Register.....................................................428

9.10.10GPIO_USE_SEL2—GPIO Use Select 2 Register[63:32]................................428

9.10.11GP_IO_SEL2—GPIO Input/Output Select 2 Register[63:32]........................429

9.10.12GP_LVL2—GPIO Level for Input or Output 2 Register[63:32] ......................429

9.10.13GPIO_USE_SEL Override Register (HIGH)—GPIO Use Select

Override Register High ..........................................................................430

10 PCI-to-PCI Bridge Registers (D30:F0)....................................................................431

10.1 PCI Configuration Registers (D30:F0) .................................................................431

10.1.1 VID— Vendor Identification Register (PCI-P CI—D30:F0)......... ....................43 2

10.1.2 DID— Device Identification Register (PCI-PCI—D30:F0).............................432

10.1.3 PCICMD—PC I Command (PCI-PCI—D30:F0 )... .. .. .. .. .. ... ............ ............. ....432

10.1.4 PSTS—PCI Status Register (PCI-PCI—D30:F0)..........................................433

10.1.5 RID—Revision Identification Register (PCI-PCI—D30:F0)............................435

10.1.6 CC—Class Code Register (PCI-PCI—D30:F0).............................................435

10.1.7 PMLT—Primary Master Latency Timer Register

(PCI-PCI—D30:F0)................................................................................436

10.1.8 HEADTYP—Head er Ty pe Reg ister (PCI-PCI—D30:F0) ............ .. .. .. .. ... ..........436

10.1.9 BNUM—Bus Number Register (PCI-PCI—D 30 :F0 ) ...... ... .. ............ .. ... .. .. ......436

10.1.10SMLT—Seco ndary Master Latency Timer Re g is ter

(PCI-PCI—D30:F0)................................................................................437

10.1.11IOBASE_LIMIT—I/O Base and Limit Register

(PCI-PCI—D30:F0)................................................................................437

10.1.12SECSTS—Sec ond ary Status Reg ister (PCI-PCI—D30:F0) ............... ... .. ........438

10.1.13MEMBASE_LIMIT—Memory Base and Limit Register

(PCI-PCI—D30:F0)................................................................................439

10.1.14PREF_MEM_BASE_LIMIT—Prefetchable Memory Base

and Limit Register (PC I-PCI—D30:F0) ........................................ .............439

10.1.15PMBU32—Prefetchable Memory Base Upper 32 Bits

10.1.16PMLU32—Prefetchable Memory Limit Upper 32 Bits

10.1.17CAPP—Capability List Pointer Register (PCI-PCI—D30:F0) ..........................440

10.1.18INTR—Interrupt Information Register (PCI-PCI—D30:F0)...........................440

10.1.19BCTRL—Bridge Control Register (PCI-PCI—D30:F0)...................................441

10.1.20SPDH—Secondary PCI Device Hiding Register

(PCI-PCI—D30:F0)................................................................................442

10.1.21DTC—Delayed Transaction Control Register

(PCI-PCI—D30:F0)................................................................................443

Intel® ICH8 Family Datasheet 17

10.1.22BPS—Bridge Proprietary Status Register

(PCI-PCI—D30:F0) ............................................................................... 444

10.1.23BPC—Bridge Policy Configuration Register

(PCI-PCI—D30:F0) ............................................................................... 445

10.1.24SVCAP—Subsystem Vendor Capability Register

(PCI-PCI—D30:F0) ............................................................................... 446

10.1.25SVID—Subsystem Vendor IDs Register (PCI-PCI—D30:F0) ................... ..... 446

11 IDE Controller Registers (D31:F1) (Mobile Only) ................................................... 447

11.1 PCI Configuration Registers (IDE—D31:F1)......................................................... 447

11.1.1 VID—Vendor Identification Register (IDE—D31:F1)................................... 448

11.1.2 DID—Device Identification Register (IDE—D31:F1) ................................... 448

11.1.3 PCICMD—PCI Command Register (IDE—D31:F1)...................................... 449

11.1.4 PCISTS — PCI Status Register (IDE—D31:F1) .......................................... 450

11.1.5 RID —Revision Identification Register (IDE—D31:F1)................................. 451

11.1.6 PI—Programming Interface Register (IDE—D31:F1).................................. 451

11.1.7 SCC—Sub Class Code Register (IDE—D31:F1).......................................... 451

11.1.8 BCC—Base Class Code Register (IDE—D31:F1) ........................................ 452

11.1.9 CLS—Cache Line Size Register (IDE—D31:F1).......................................... 452

11.1.10PMLT—Primary Master Latency Timer Register

(IDE—D31:F1)..................................................................................... 452

11.1.11PCMD_BAR—Primary Command Block Base Address

11.1.12PCNL_BAR—Primary Control Block Base Address

11.1.13SCMD_BAR—Secondary Command Block Base Address

11.1.14SCNL_BAR—Secondary Control Block Base Address

11.1.15BM_BASE — Bus Master Base Address Register

(IDE—D31:F1)..................................................................................... 454

11.1.16IDE_SVID — Subsystem Vendor Identification

(IDE—D31:F1)..................................................................................... 454

11.1.17IDE_SID — Subsystem Identification Register

(IDE—D31:F1)..................................................................................... 454

11.1.18INTR_LN—Interrupt Line Register (IDE—D31:F1)...................................... 455

11.1.19INTR_PN—Interrupt Pin Register (IDE—D31:F1)....................................... 455

11.1.20IDE_TIMP — IDE Primary Timing Register (IDE—D31:F1) .......................... 455

11.1.21IDE_TIMS — IDE Secondary Timing Register

(IDE—D31:F1)..................................................................................... 457

11.1.22SLV_IDETIM—Slave (Drive 1) IDE Timing Register

(IDE—D31:F1)..................................................................................... 457

11.1.23SDMA_CNT—Synchronous DMA Control Register

(IDE—D31:F1)..................................................................................... 458

11.1.24SDMA_TIM—Synchronous DMA Timing Register

(IDE—D31:F1)..................................................................................... 459

11.1.25IDE_CONFIG—IDE I/O Configuration Register

(IDE—D31:F1)..................................................................................... 460

11.1.26ATC—APM Trapping Control Register (IDE—D31:F1) ......... ........... ............. 461

11.1.27ATS—APM Trapping Status Register (IDE—D31:F1)................................... 461

11.2 Bus Master IDE I/O Registers (IDE—D31:F1) ...................................................... 462

11.2.1 BMICP—Bus Master IDE Command Register

(IDE—D31:F1)..................................................................................... 462

11.2.2 BMISP—Bus Master IDE Status Register (IDE—D31:F1)............................. 463

11.2.3 B MIDP—Bus Master IDE Descriptor Table Pointer Register

(IDE—D31:F1)..................................................................................... 463

18 Intel® ICH8 Family Datasheet

12 SATA Controller Registers (D3 1: F2) .......................................................................465

12.1 PCI Configuration Registers (SATA–D31:F2)........................................................465

12.1.1 VID—Vendor Identification Register (SATA—D31:F2).................................466

12.1.2 DID—Device Identification Register (SATA—D31:F2) .................................467

12.1.3 PCICMD—PCI Command Register (SATA–D31:F2) .....................................467

12.1.4 PCISTS — PCI Status Register (SATA–D31:F2) .........................................468

12.1.5 RID—Revision Identification Register (SATA—D31:F2) ...............................468

12.1.6 PI—Programming Interface Register (SATA–D31:F2) .................................469

12.1.6.1 When Sub Class Code Register (D31:F2:Offset 0Ah) = 01h........ ...469

12.1.6.2 When Sub Class Code Register (D31:F2:Offset 0Ah) = 04h........ ...469

12.1.6.3 When Sub Class Code Register (D31:F2:Offset 0Ah) = 06h........ ...470

12.1.7 SCC—Sub Class Code Re g i ster (SA T A– D3 1 :F2)..... ............. .......................470

12.1.8 BCC—Base Class Code Register

(SATA–D31:F2SATA–D31:F2).................................................................470

12.1.9 PMLT—Primary Master Latency Timer Register

(SATA–D31:F2)....................................................................................471

12.1.10PCMD_BAR—Primary Command Block Base Address

12.1.11PCNL_BAR—Primary Control Block Base Address Register

(SATA–D31:F2)....................................................................................471

12.1.12SCMD_BAR—Secondary Command Block Base Address

12.1.13SCNL_BAR—Secondary Control Block Base Address

12.1.14BAR — Legacy Bus Master Base Address Register

(SATA–D31:F2)....................................................................................473

12.1.15ABAR/SIDPBA1 — AHCI Base Address Register/Serial ATA Index

Data Pair Base Address (SATA–D31:F2)...................................................473

12.1.15. 1Whe n CC. SCC is not 01h ................................. .. .. .....................473

12.1.15.2When CC.SCC is 01 h....... .. .. ........... .. .. ........... .. .. .......... ... .. ........474

12.1.16SVID—Subsystem Vendor Identification Register

(SATA–D31:F2)....................................................................................474

12.1.17SID—Subsystem Identification Register (SATA–D31:F2).............................474

12.1.18CAP—Capabilities Pointer Register (SATA–D31:F2)....................................474

12.1.19INT_LN—Interrupt Line Register (SATA–D31:F2).......................................475

12.1.20INT_PN—Interrupt Pin Register (SATA–D31:F2)........................................475

12.1.21IDE_TIM — IDE Timing Register (SATA–D31:F2).......................................475

12.1.22SIDETIM—Slave IDE Timing Register (SATA–D31:F2)................................477

12.1.23SDMA_CNT—Synchronous DMA Control Register

(SATA–D31:F2)....................................................................................478

12.1.24SDMA_TIM—Synchronous DMA Timing Register

(SATA–D31:F2)....................................................................................478

12.1.25IDE_CONFIG—IDE I/O Configuration Register

(SATA–D31:F2)....................................................................................480

12.1.26PID—PCI Power Management Capability Identification

12.1.27PC—PCI Power Management Capabilities Register

(SATA–D31:F2)....................................................................................482

12.1.28PMCS—PCI Power Management Control and Status

12.1.29MSICI—Message Signaled Interrupt Capability Identification (SATA–D31:F2) 483

12.1.30MSIMC—Message Signaled Interrupt Message Control

(SATA–D31:F2)....................................................................................483

12.1.31MSIMA— Message Signaled Interrupt Message Address

(SATA–D31:F2)....................................................................................485

12.1.32MSIMD—Message Signaled Interrupt Message Data (SATA–D31:F2) ..... .......485

Intel® ICH8 Family Datasheet 19

12.1.33MAP—Address Map Register (SATA–D31:F2)............................................ 486

12.1.34PCS—Port Control and Status Register (SATA–D31:F2).............................. 487

12.1.35SCLKCG—SATA Clock Gating Control Register .......................................... 489

12.1.36SCLKGC—SATA Clock General Conf iguration Register .... ............ ............. ... 490

12.1.37SIRI—SATA Indexed Registers Index Register.......................................... 490

12.1.38STRD—SATA Indexed Register Data Register ........................................... 490

12.1.39STTT1—SATA Indexed Registers Index 00h

(SATA TX Termination Test Register 1).................................................... 492

12.1.40SIR18—SATA Indexed Registers Index 18h

(SATA Initialization Register 18h)............... ............. .. ............ .. ............. .. 492

12.1.41STME—SATA Indexed Registers Index 1Ch

(SATA Test Mode Enable Register).......................................................... 492

12.1.42SIR28—SATA Indexed Registers Index 28h

(SATA Initialization Register 28h)............... ............. .. ............ .. ............. .. 493

12.1.43SIR40—SATA Indexed Registers Index 40h

(SATA Initialization Register 40h)............... ............. .. ............ .. ............. .. 493

12.1.44STTT2—SATA Indexed Registers Index 74h

(SATA TX Termination Test Register 2).................................................... 493

12.1.45SIR78—SATA Indexed Registers Index 78h

(SATA Initialization Register 78h)............... ............. .. ............ .. ............. .. 494

12.1.46SIR84—SATA Indexed Registers Index 84h

(SATA Initialization Register 84h)............... ............. .. ............ .. ............. .. 494

12.1.47SIR88—SATA Indexed Registers Index 88h

(SATA Initialization Register 88h)............... ............. .. ............ .. ............. .. 494

12.1.48SIR8C—SATA Indexed Registers Index 8Ch

(SATA Initialization Register 8Ch).... .. ... .. .. ............ ............. .. ............. .. .... 494

12.1.49STTT3—SATA Indexed Registers Index 90h

(SATA TX Termination Test Register 3).................................................... 495

12.1.50SIR94—SATA Indexed Registers Index 94h

(SATA Initialization Register 94h)............... ............. .. ............ .. ............. .. 495

12.1.51SIRA0—SATA Indexed Registers Index A0h

(SATA Initialization Register A0h)........... .. .. ............. ............ .. ............. .. .. 495

12.1.52SIRA8—SATA Indexed Registers Index A8h

(SATA Initialization Register A8h)........... .. .. ............. ............ .. ............. .. .. 495

12.1.53SIRAC—SATA Indexed Registers Index ACh

(SATA Initialization Register ACh).... .. ... .. .. ............ ............. .. ............. .. .... 496

12.1.54SATACR0—SATA Capability Register 0 (SATA–D31:F2).............................. 496

12.1.55SATACR1—SATA Capability Register 1 (SATA–D31:F2).............................. 497

12.1.56ATC—APM Trapping Control Register (SATA–D31:F2)................................ 498

12.1.57ATS—APM Trapping Status Register (SATA–D31:F2) ... .............................. 498

12.1.58SP Scratch Pad Register (SATA–D31:F2) ................................................. 498

12.1.59BFCS—BIST FIS Control/Status Register (SATA–D31:F2)........................... 499

12.1.60BFTD1—BIST FIS Transmit Data1 Register (SATA–D31:F2)........................ 501

12.1.61BFTD2—BIST FIS Transmit Data2 Register (SATA–D31:F2)........................ 501

12.2 Bus Master IDE I/O Registers (D31:F2).............................................................. 502

12.2.1 BMIC[P,S]—Bus Master IDE Command Register (D31:F2).......................... 503

12.2.2 BMIS[P,S]—Bus Master IDE S t atus Register (D31:F2) ............................... 504

12.2.3 B MID[P,S]—Bus Master IDE Descriptor Table Pointer

12.2.3.1 PxSSTS—Serial AT A Status Registe r (D31: F5) ........... .. ... .. .......... 505

12.2.3.2 PxSCTL — Serial ATA Control Register (D31:F5).......................... 507

12.2.3.3 PxSERR—Serial ATA Error Register (D31:F5) .. ............ ................ 508

12.2.4 AIR—AHCI Index Register (D31:F2)........................................................ 509

12.2.5 AIDR—AHCI Index Data Register (D31:F2) .............................................. 510

12.3 Serial ATA Index/Data Pair Supe rset Registers .................................................... 510

12.3.1 SINDX—SATA Index Register (D31:F5) ................................................... 510

20 Intel® ICH8 Family Datasheet

12.3.2 SDATA—SATA Index Data Register (D31:F5)............................................511

12.4 AHCI Registers (D31:F2) (Intel® ICH8R, ICH8DH, ICH8DO, and ICH8M-E

Only) .............................................................................................................512

12.4.1 AHCI Generic Host Control Registers (D31:F2)..........................................513

12.4.1.1 CAP—Host Capabilities Register (D31:F2) ...................................513

12.4.1.2 GHC—Global ICH8 Control Register (D31:F2)........................... ...515

12.4.1.3 IS—Interrupt Status Register (D31:F2) ......................................516

12.4.1.4 PI—Ports Implemented Register (D31:F2) ..................................517

12.4.1.5 VS—AHCI Version (D31:F2)......................................................518

12.4.1.6 CCC_CTL—Command Completion Coalescing Control

12.4.1.7 CCC_Ports—Command Completion Coalescing Ports

12.4.1.8 EM_LOC—Enclosure Management Location Register

(D31:F2)................................................................................519

12.4.1.9 EM_CTL—Enclosure Management Control Register (D31:F2)..........520

12.4.2 Port Registers (D31 : F2 ).......... .. .. ........... .. .. ..................... .. .. ...................521

12.4.2.1 PxCLB—Port [5:0] Command List Base Address Register

(D31:F2)................................................................................524

12.4.2.2 PxCLBU—Port [5:0] Command List Base Address Upper

32-Bits Register (D31:F2) ........................................................524

12.4.2.3 PxFB—Port [5:0] FIS Base Address Register (D31:F2)..................525

12.4.2.4 PxFBU—Port [5:0] FIS Base Address Upper 32-Bits

12.4.2.5 PxIS—Port [5:0] Interru pt Status Regi ster (D3 1: F2 ) .................. ..526

12.4.2.6 PxIE—Port [5:0] Interrupt Enable Register (D31:F2)....................527

12.4.2.7 PxCMD—Port [5:0] Command Register (D31:F2) .........................529

12.4.2.8 PxTFD—Port [5:0] Task File Data Register (D31:F2).....................532

12.4.2.9 PxSIG—Port [5:0] Signature Register (D31:F2)...........................532

12.4.2.10PxSSTS—Port [5:0] Serial ATA Status Register (D31:F2) ..............533

12.4.2.11PxSCTL — Port [5:0] Serial ATA Control Register (D31:F2) ........ .. .534

12.4.2.12PxSERR—Port [5:0] Serial ATA Error Reg ister (D31:F2)........... .. ...535

12.4.2.13PxSACT—Port [5:0] Serial ATA Active (D31:F2). ............ ..............537

12.4.2.14PxCI—Port [5:0] Command Issue Register (D31: F2)....................537

13 SATA Controller Registers (D3 1: F5) .......................................................................539

13.1 PCI Configuration Registers (SATA–D31:F5)........................................................539

13.1.1 VID—Vendor Identification Register (SATA—D31:F5).................................540

13.1.2 DID—Device Identification Register (SATA—D31:F5) .................................541

13.1.3 PCICMD—PCI Command Register (SATA–D31:F5) .....................................541

13.1.4 PCISTS — PCI Status Register (SATA–D31:F5) .........................................542

13.1.5 RID—Revision Identification Register (SATA—D31:F5) ...............................542

13.1.6 PI—Programming Interface Register (SATA–D31:F5) .................................543

13.1.7 SCC—Sub Class Code Re g i ster (SA T A– D3 1 :F5)..... ............. .......................543

13.1.8 BCC—Base Class Code Register

(SATA–D31:F5SATA–D31:F5).................................................................543

13.1.9 PMLT—Primary Master Latency Timer Register

(SATA–D31:F5)....................................................................................543

13.1.10PCMD_BAR—Primary Command Block Base Address

13.1.11PCNL_BAR—Primary Control Block Base Address Register

(SATA–D31:F5)....................................................................................544

13.1.12SCMD_BAR—Secondary Command Block Base Address

13.1.13SCNL_BAR—Secondary Control Block Base Address

13.1.14BAR — Legacy Bus Master Base Address Register

(SATA–D31:F5)....................................................................................545

Intel® ICH8 Family Datasheet 21

13.1.15SIDPBA — SATA Index/Data Pair Base Address Register

(SATA–D31:F5).................................................................................... 546

13.1.16SVID—Subsystem Vendor Identification Register

(SATA–D31:F5).................................................................................... 546

13.1.17SID—Subsystem Identification Register (SATA–D31:F5)............................ 546

13.1.18CAP—Capabilities Pointer Register (SATA–D31:F5).................................... 546

13.1.19INT_LN—Interrupt Line Register (SATA–D31:F5) ...................................... 547

13.1.20INT_PN—Interrupt Pin Register (SATA–D31:F5)........................................ 547

13.1.21IDE_TIM — IDE Timing Register (SATA–D31:F5) ...................................... 547

13.1.22D1TIM—Device 1 IDE Timing Register (SATA–D31:F5) .............................. 549

13.1.23SDMA_CNT—Synchronous DMA Control Register

(SATA–D31:F5).................................................................................... 549

13.1.24SDMA_TIM—Synchronous DMA Timing Register

(SATA–D31:F5).................................................................................... 550

13.1.25IDE_CONFIG—IDE I/O Configuration Register

(SATA–D31:F5).................................................................................... 551

13.1.26PID—PCI Power Management Capability Identification

13.1.27PC—PCI Power Management Capabilities Register

(SATA–D31:F5).................................................................................... 552

13.1.28PMCS—PCI Power Management Control and Status

13.1.29MAP—Address Map Register (SATA–D31:F5)............................................ 553

13.1.30PCS—Port Control and Status Register (SATA–D31:F5).............................. 554

13.1.31ATC—APM Trapping Control Register (SATA–D31:F5)................................ 555

13.1.32ATS—APM Trapping Status Register (SATA–D31:F5) ... .............................. 555

13.2 Bus Master IDE I/O Registers (D31:F5).............................................................. 556

13.2.1 BMIC[P,S]—Bus Master IDE Command Register (D31:F5).......................... 557

13.2.2 BMIS[P,S]—Bus Master IDE S t atus Register (D31:F5) ............................... 558

13.2.3 B MID[P,S]—Bus Master IDE Descriptor Table Pointer

13.2.3.1 PxSSTS—Serial AT A Status Registe r (D31: F5) ........... .. ... .. .......... 559

13.2.3.2 PxSCTL — Serial ATA Control Register (D31:F5).......................... 560

13.2.3.3 PxSERR—Serial ATA Error Register (D31:F5) .. ............ ................ 561

13.3 Serial ATA Index/Data Pair Supe rset Registers .................................................... 563

13.3.1 SINDX—SATA Index Register (D31:F5) ................................................... 563

13.3.2 SDATA—SATA Index Data Register (D31:F5)............................................ 563

14 UHCI Controllers Registers.................................................................................... 565

14.1 PCI Configuration Registers

(USB—D29:F0/F1/F2, D26:F0/F1) ..................................................................... 565

14.1.1 VID —Vendor Identification Register

(USB—D29:F0/F1/F2, D26:F0/F1) .......................................................... 566

14.1.2 DID—Device Identification Register

(USB—D29:F0/F1/F2, D26:F0/F1) .......................................................... 566

14.1.3 PCICMD—PCI Command Register (USB—D29:F0/F1/F2, D26:F0/F1) ........... 567

14.1.4 PCISTS—PCI Status Register

(USB—D29:F0/F1/F2, D26:F0/F1) .......................................................... 568

14.1.5 RID—Revision Identification Register

(USB—D29:F0/F1/F2, D26:F0/F1) .......................................................... 568

14.1.6 PI—Prog ramming Interface Register

(USB—D29:F0/F1/F2, D26:F0/F1) .......................................................... 569

14.1.7 SCC—Sub Class Code Register

(USB—D29:F0/F1/F2, D26:F0/F1) .......................................................... 569

14.1.8 B CC—Base Class Code Register

(USB—D29:F0/F1/F2, D26:F0/F1) .......................................................... 569

22 Intel® ICH8 Family Datasheet

14.1.9 MLT—Master Latency Timer Register

(USB—D29:F0/F1/F2, D26:F0/F1)...........................................................569

14.1.10HEADTYP — He ad er Ty pe Re g is t er

(USB—D29:F0/F1/F2, D26:F0/F1)...........................................................570

14.1.11BASE—Base Address Register

(USB—D29:F0/F1/F2, D26:F0/F1)...........................................................570

14.1.12SVID — Subsystem Vendor Identification Register

(USB—D29:F0/F1/F2, D26:F0/F1)...........................................................570

14.1.13SID — Subsystem Identification Register

(USB—D29:F0/F1/F2/F3, D26:F0/F1)......................................................571

14.1.14INT_LN—Interrupt Line Register

(USB—D29:F0/F1/F2, D26:F0/F1)...........................................................571

14.1.15INT_PN—Interrupt Pin Register

(USB—D29:F0/F1/F2/F3, D26:F0/F1)......................................................571

14.1.16USB_RELNUM—Serial Bus Release Number Register

(USB—D29:F0/F1/F2, D26:F0/F1)...........................................................572

14.1.17USB_LEGKEY—USB Legacy Keyboard/Mouse Control

14.1.18USB_RES—USB Resume Enable Register

(USB—D29:F0/F1/F2, D26:F0/F1)...........................................................574

14.1.19CWP—Core Well Policy Register

(USB—D29:F0/F1/F2, D26:F0/F1)...........................................................574

14.2 USB I/O Registers............................................................................................575

14.2.1 USBCMD—USB Command Register..........................................................576

14.2.2 USBSTS—USB Status Register................................................................579

14.2.3 USBINTR—USB Inte rrupt Enab le Registe r.................... ............ .. .. ... .. ........580

14.2.4 FRNUM—Frame Number Registe r .............. .. .. .. ............. ............ ............. ..580

14.2.5 FRBASEADD— Frame List Base Address Register................. .. ............. ........581

14.2.6 SOFMOD—Start of Frame Modify Register ................................................581

14.2.7 PORTSC[0,1]—Port Status and Control Register........................................582

15 EHCI Control ler Registers (D29:F7, D2 6:F 7)...........................................................585

15.1 USB EHCI Configuration Registers

(USB EHCI—D29:F7, D26:F7)............................................................................585

15.1.1 VID—Vendor Identification Register

(USB EHCI—D29:F7, D26:F7).................................................................586

15.1.2 DID—Device Identification Register

(USB EHCI—D29:F7, D26:F7).................................................................586

15.1.3 PCICMD—PCI Command Register

(USB EHCI—D29:F7, D26:F7).................................................................587

15.1.4 PCISTS—PCI Status Register

(USB EHCI—D29:F7, D26:F7).................................................................588

15.1.5 RID—Revision Identification Register

(USB EHCI—D29:F7, D26:F7).................................................................589

15.1.6 PI—Programming Interface Register

(USB EHCI—D29:F7, D26:F7).................................................................589

15.1.7 SCC—Sub Class Code Register

(USB EHCI—D29:F7, D26:F7).................................................................589

15.1.8 BCC—Base Class Code Register

(USB EHCI—D29:F7, D26:F7).................................................................589

15.1.9 PMLT—Primary Master Latency Timer Register

(USB EHCI—D29:F7, D26:F7).................................................................590

15.1.10MEM_BASE—Memory Base Address Register

(USB EHCI—D29:F7, D26:F7).................................................................590

15.1.11SVID—USB EHCI Subsystem Vendor ID Register

(USB EHCI—D29:F7, D26:F7).................................................................590

Intel® ICH8 Family Datasheet 23

15.1.12SID—USB EHCI Subsystem ID Register

(USB EHCI—D29 :F7, D26:F7)......... .. ...................... .. .. ..................... .. .. .. 591

15.1.13CAP_PTR—Capabilities Pointer Register

(USB EHCI—D29 :F7, D26:F7)......... .. ...................... .. .. ..................... .. .. .. 591

15.1.14INT_LN—Interrupt Line Register

(USB EHCI—D29 :F7, D26:F7)......... .. ...................... .. .. ..................... .. .. .. 591

15.1.15INT_PN—Interrupt Pin Register

(USB EHCI—D29 :F7, D26:F7)......... .. ...................... .. .. ..................... .. .. .. 591

15.1.16PWR_CAPID—PCI Power Management Capability ID

15.1.17NXT_PTR1—Next Item Pointer #1 Register

(USB EHCI—D29 :F7, D26:F7)......... .. ...................... .. .. ..................... .. .. .. 592

15.1.18PWR_CAP—Power Management Capabilities Register

(USB EHCI—D29 :F7, D26:F7)......... .. ...................... .. .. ..................... .. .. .. 593

15.1.19PWR_CNTL_STS—Power Management Control/

Status Register (USB EHCI—D29:F7, D26:F7).......................................... 594

15.1.20DEBUG_CAPID—Debug Port Capability ID Register

(USB EHCI—D29 :F7, D26:F7)......... .. ...................... .. .. ..................... .. .. .. 595

15.1.21NXT_PTR2—Next Item Pointer #2 Register

(USB EHCI—D29 :F7, D26:F7)......... .. ...................... .. .. ..................... .. .. .. 595

15.1.22DEBUG_BASE—Debug Port Base Offset Register

(USB EHCI—D29 :F7, D26:F7)......... .. ...................... .. .. ..................... .. .. .. 595

15.1.23USB_RELNUM—USB Release Number Register

(USB EHCI—D29 :F7, D26:F7)......... .. ...................... .. .. ..................... .. .. .. 595

15.1.24FL_ADJ—Frame Length Adjustment Register

(USB EHCI—D29 :F7, D26:F7)......... .. ...................... .. .. ..................... .. .. .. 596

15.1.25PWAKE_ CAP—Port Wake Capability Register

(USB EHCI—D29 :F7, D26:F7)......... .. ...................... .. .. ..................... .. .. .. 597

15.1.26LEG_EXT_CAP—USB EHCI Legacy Support Extended

Capability Register (USB EHCI—D29:F7, D26:F7) ..................................... 597

15.1.27LEG_EXT_CS—USB EHCI Legacy Support Extended

Control / Status Register (USB EHCI—D29:F7, D26:F7)............................. 598

15.1.28SPECIAL_SMI—Intel Specific USB 2.0 SMI Register

(USB EHCI—D29 :F7, D26:F7)......... .. ...................... .. .. ..................... .. .. .. 600

15.1.29ACCESS_CNTL—Access Control Register

(USB EHCI—D29 :F7, D26:F7)......... .. ...................... .. .. ..................... .. .. .. 601

15.1.30EHCIIR1—EHCI Initialization Register 1 (Mobile Only)

(USB EHCI—D29 :F7, D26:F7)......... .. ...................... .. .. ..................... .. .. .. 602

15.1.31EHCIIR2—EHCI Initialization Register 2

(USB EHCI—D29 :F7, D26:F7)......... .. ...................... .. .. ..................... .. .. .. 602

15.2 Memory-Mapped I/O Registers.......................................................................... 603

15.2.1 Host Controller Capability Registers ........................................................ 603

15.2.1.1 CAPLENGTH—Capability Registers Length................................... 604

15.2.1.2 HCIVERSION—Host Controller Interface Version Number.............. 604

15.2.1.3 HCSPARAMS—Host Controller Structural Parameters.................... 605

15.2.1.4 HCCPARAMS—Host Controller Capability Parameters

15.2.2 Host Controller Operational Registers...................................................... 607

15.2.2.1 USB2.0_CMD—USB 2.0 Command Reg i ster .......... ............. ......... 6 08

15.2.2.2 USB2.0_STS—USB 2.0 Status Register ...................................... 610

15.2.2.3 USB2.0_INTR—USB 2.0 Interrupt Enable Register....................... 612

15.2.2.4 FRINDEX—Frame Index Register............................................... 613

15.2.2.5 CTRLDSSEGMENT—Control Data Structure Segment

15.2.2.6 PERIODICLISTBASE—Periodic Frame List Base Address

15.2.2.7 ASYNCLISTADDR—Current Asynchronous List Address

24 Intel® ICH8 Family Datasheet

15.2.2.8 CONFIGFLAG—Configure Flag Register .......................................615

15.2.2.9 PORTSC—Port N Status and Control Register...............................616

15.2.3 USB 2.0-Based De b u g Port Reg i ste r ............................... .. .. .. ...................620

15.2.3.1 CNTL_STS—Control/Status Register...........................................621

15.2.3.2 USBPID—USB PIDs Register .....................................................622

15.2.3.3 DATABUF[7:0]—Data Buffer Bytes[7:0] Register .........................623

15.2.3.4 CONFIG—Configuration Register................................................623

16 SMBus Co n t roller Regist ers (D31:F3).....................................................................625

16.1 PCI Configuration Registers (SMBUS—D31:F3) ....................................................625

16.1.1 VID—Vendor Identification Register (SMBUS—D31:F3) ...... ........................625

16.1.2 DID—Device Identification Reg ister (SMBUS—D31:F3)............................ ...626

16.1.3 PCICMD—PCI Command Register (SMBUS—D31:F3)..................................626

16.1.4 PCISTS—PCI Status Register (SMBUS—D31:F3)........................................627

16.1.5 RID—Revision Identification Register (SMBUS—D31:F3).............................627

16.1.6 PI—Programming Interface Register (SMBUS—D31:F3)..............................628

16.1.7 SCC—Sub Class Code Reg i ster (SM BU S—D 3 1:F3) ........................ ... .. ........628

16.1.8 BCC—Base Class Code Register (SMBU S—D 3 1:F3)................. .. .. .. ... .. ........628

16.1.9 SMBMBAR0 – D31_F3_SMBus Memory Base Address 0 ..............................628

16.1.10SMB_BASE—SMBUS Base Address Register

(SMBUS—D31:F3) ................................................................................629

16.1.11SVID — Subsystem Vendor Identification Register

(SMBUS—D31:F2/F4)............................................................................629

16.1.12SID — Subsystem Identification Register

(SMBUS—D31:F2/F4)............................................................................629

16.1.13INT_LN—Interrupt Line Register (SMBUS—D31:F3)...................................630

16.1.14INT_PN—Interrupt Pin Register (SMBUS—D31:F3) ....................................630

16.1.15HOSTC—Host Configuration Register (SMBUS—D31:F3).............................630

16.2 SMBus I/O and Memory Mapped I/O Registers.....................................................631

16.2.1 HST_STS—Host Status Register (SMBUS—D 3 1:F3 ) .................... .. ... ..........632

16.2.2 HST_CNT—Host Control Register (SMBUS—D31:F3)..................................633

16.2.3 HST_CMD—Host Comm and Reg iste r (SMBUS—D31:F3) .............. .. ... .. .. .. .. ..635

16.2.4 XMIT_SLVA—Transmit Slave Address Register

(SMBUS—D31:F3) ................................................................................635

16.2.5 HST_D0—Host Data 0 Register (SMBUS—D31:F3).....................................635

16.2.6 HST_D1—Host Data 1 Register (SMBUS—D31:F3).....................................635

16.2.7 Host_BLOCK_DB—Host Block Data Byte Register

(SMBUS—D31:F3) ................................................................................636

16.2.8 PEC—Packet Error Check (PEC) Register

(SMBUS—D31:F3) ................................................................................636

16.2.9 RCV_SLVA—Receive Slave A ddress Register

(SMBUS—D31:F3) ................................................................................637

16.2.10SLV_DATA—Receive Slave Data Register (SMBUS—D31:F3) .......................637

16.2.11AUX_STS—Auxiliary Status Register (SMBUS—D31:F3)..............................637

16.2.12AUX_CTL—Auxiliary Control Register (SMBUS—D31:F3).............................638

16.2.13SMLINK_PIN_CTL—SMLink Pin Control Register

(SMBUS—D31:F3) ................................................................................638

16.2.14SMBUS_PIN_CTL—SMBus Pin Control Register

(SMBUS—D31:F3) ................................................................................639

16.2.15SLV_STS—Slav e Status Re g ister (SM BUS—D31:F3) ..................................639

16.2.16SLV_CMD—Slave Command Register (SMBUS—D31:F3) ................... .........640

16.2.17NOTIFY_DADDR—Notify Device Address Register

(SMBUS—D31:F3) ................................................................................640

16.2.18NOTIFY_DLOW—Notify Data Low Byte Register

(SMBUS—D31:F3) ................................................................................641

16.2.19NOTIFY_DHIGH—Notify Data High Byte Register

(SMBUS—D31:F3) ................................................................................641

Intel® ICH8 Family Datasheet 25

17 Intel® High Definition Audio Controller Registers (D27:F0) ................................... 643

17.1 Intel® High Definition Audio PCI Configuration Space (Intel® High Definition

Audio— D27:F0) ............................................................................................. 643

17.1.1 VID —Vendor Identification Register

(Intel® High Definition Audio Controller—D27:F0)..................................... 645

17.1.2 DID—Device Identification Register

(Intel® High Definition Audio Controller—D27:F0)..................................... 645

17.1.3 PCICMD—PCI Command Register

(Intel® High Definition Audio Controller—D27:F0)..................................... 646

17.1.4 PCISTS—PCI Status Register

(Intel® High Definition Audio Controller—D27:F0)..................................... 647

17.1.5 RID—Revision Identification Register

(Intel® High Definition Audio Controller—D27:F0)..................................... 647

17.1.6 PI—Prog ramming Interface Register

(Intel® High Definition Audio Controller—D27:F0)..................................... 648

17.1.7 SCC—Sub Class Code Register

(Intel® High Definition Audio Controller—D27:F0)..................................... 648

17.1.8 B CC—Base Class Code Register

(Intel® High Definition Audio Controller—D27:F0)..................................... 648

17.1.9 CLS—Cache Line Size Reg ister

(Intel® High Definition Audio Controller—D27:F0)..................................... 648

17.1.10LT—Latency Timer Register

(Intel® High Definition Audio Controller—D27:F0)..................................... 648

17.1.11HEADTYP—Header Type Register

(Intel® High Definition Audio Controller—D27:F0)..................................... 649

17.1.12HDBARL—Intel® High Definition Audio Lower Base Address Register

(Intel® High Definition Audio—D27:F0) ................................................... 649

17.1.13HDBARU—Intel® High Definition Audio Upper Base Address Register

(Intel® High Definition Audio Controller—D27:F0)..................................... 649

17.1.14SVID—Subsystem Vendor Identification Register

(Intel® High Definition Audio Controller—D27:F0)..................................... 650

17.1.15SID—Subsystem Identification Register

(Intel® High Definition Audio Controller—D27:F0)..................................... 650

17.1.16CAPPTR—Capabilities Pointer Register (Audio—D30:F2)............................. 650

17.1.17INTLN—Interrupt Line Register

(Intel® High Definition Audio Controller—D27:F0)..................................... 651

17.1.18INTPN—Interrupt Pin Register

(Intel® High Definition Audio Controller—D27:F0)..................................... 651

17.1.19HDCTL—Intel® High Definition Audio Control Register

(Intel® High Definition Audio Controller—D27:F0)..................................... 651

17.1.20TCSEL—Traffic Class Select Register

(Intel® High Definition Audio Controller—D27:F0)..................................... 652

17.1.21DCKCTL—Docking Control Register

(Intel® High Definition Audio Controller—D27:F0) (Mobile Only)................. 652

17.1.22DCKSTS—Docking Status Register

(Intel® High Definition Audio Controller—D27:F0) (Mobile Only)................. 653

17.1.23PID—PCI Power Management Capability ID Register

(Intel® High Definition Audio Controller—D27:F0)..................................... 653

17.1.24PC—Power Management Capabilities Register

(Intel® High Definition Audio Controller—D27:F0)..................................... 654

17.1.25PCS—Power Management Control and Status Register

(Intel® High Definition Audio Controller—D27:F0)..................................... 654

17.1.26MID—MSI Capability ID Register

(Intel® High Definition Audio Controller—D27:F0)..................................... 655

17.1.27MMC—MSI Message Control Register

(Intel® High Definition Audio Controller—D27:F0)..................................... 655

26 Intel® ICH8 Family Datasheet

17.1.28MMLA—MSI Message Lower Address Register

(Intel® High Definition Audio Controller—D27:F0).....................................656

17.1.29MMUA—MSI Message Upper Address Register

(Intel® High Definition Audio Controller—D27:F0).....................................656

17.1.30MMD—MSI Message Data Register

(Intel® High Definition Audio Controller—D27:F0).....................................656

17.1.31PXID—PCI Express* Capability ID Register

(Intel® High Definition Audio Controller—D27:F0).....................................656

17.1.32PXC—PCI Express* Capabilities Register

(Intel® High Definition Audio Controller—D27:F0).....................................657

17.1.33DEVCAP—Device Capabilities Register

(Intel® High Definition Audio Controller—D27:F0).....................................657

17.1.34DEVC—Device Control Register

(Intel® High Definition Audio Controller—D27:F0).....................................658

17.1.35DEVS—Device Status Register

(Intel® High Definition Audio Controller—D27:F0).....................................659

17.1.36VCCAP—Virtual Channel Enhanced Capability Header

(Intel® High Definition Audio Controller—D27:F0).....................................659

17.1.37PVCCAP1—Port VC Capability Register 1

(Intel® High Definition Audio Controller—D27:F0).....................................660

17.1.38PVCCAP2 — Port VC Capability Register 2

(Intel® High Definition Audio Controller—D27:F0).....................................660

17.1.39PVCCTL — Port VC Control Register

(Intel® High Definition Audio Controller—D27:F0).....................................660

17.1.40PVCSTS—Port VC Status Register

(Intel® High Definition Audio Controller—D27:F0).....................................661

17.1.41VC0CAP—VC0 Resource Capability Register

(Intel® High Definition Audio Controller—D27:F0).....................................661

17.1.42VC0CTL—VC0 Resource Control Register

(Intel® High Definition Audio Controller—D27:F0).....................................661

17.1.43VC0STS—VC0 Resource Status Register

(Intel® High Definition Audio Controller—D27:F0).....................................662

17.1.44VCiCAP—VCi Resource Capability Register

(Intel® High Definition Audio Controller—D27:F0).....................................662

17.1.45VCiCTL—VCi Resource Control Register

(Intel® High Definition Audio Controller—D27:F0).....................................663

17.1.46VCiSTS—VCi Resource Status Register

(Intel® High Definition Audio Controller—D27:F0).....................................663

17.1.47RCCAP—Root Complex Link Declaration Enhanced

Capability Header Register (Intel® High Definition Audio Controller—D27:F0)664

17.1.48ESD—Element Self Description Register

(Intel® High Definition Audio Controller—D27:F0).....................................664

17.1.49L1DESC—Link 1 Description Register

(Intel® High Definition Audio Controller—D27:F0).....................................664

17.1.50L1ADDL—Link 1 Lower Address Register

(Intel® High Definition Audio Controller—D27:F0).....................................665

17.1.51L1ADDU—Link 1 Upper Address Register

(Intel® High Definition Audio Controller—D27:F0).....................................665

17.2 Intel® High Definition Audio Memory Mapped Configuration Registers

(Intel® High Definition Audio— D27:F0)..............................................................666

17.2.1 GCAP—Global Capabilitie s Register

(Intel® High Definition Audio Controller—D27:F0).....................................670

17.2.2 VMIN—Minor Version Register

(Intel® High Definition Audio Controller—D27:F0).....................................670

17.2.3 VMAJ—Major Version Register

(Intel® High Definition Audio Controller—D27:F0).....................................670

Intel® ICH8 Family Datasheet 27

17.2.4 OUTPAY—Output Payload Capability Register

(Intel® High Definition Audio Controller—D27:F0)..................................... 671

17.2.5 INPAY—Input Payload Capability Register

(Intel® High Definition Audio Controller—D27:F0)..................................... 671

17.2.6 GCTL—Global Control Register

(Intel® High Definition Audio Controller—D27:F0)..................................... 672

17.2.7 WAKEEN—Wake Enable Register

(Intel® High Definition Audio Controller—D27:F0)..................................... 673

17.2.8 STATESTS—State Change Status Register

(Intel® High Definition Audio Controller—D27:F0)..................................... 673

17.2.9 GSTS—Global Status Register

(Intel® High Definition Audio Controller—D27:F0)..................................... 674

17.2.10ECAP—Extende d Capabilities

(Intel® High Definition Audio Controller—D27:F0)..................................... 675

17.2.11OUTSTRMPAY—Output Stream Payload Capability

(Intel® High Definition Audio Controller—D27:F0)..................................... 675

17.2.12INSTRMPAY—Input Stream Payload Capability

(Intel® High Definition Audio Controller—D27:F0)..................................... 676

17.2.13INTCTL—Interrupt Control Register

(Intel® High Definition Audio Controller—D27:F0)..................................... 677

17.2.14INTSTS—Interrupt Status Register

(Intel® High Definition Audio Controller—D27:F0)..................................... 678

17.2.15WALCLK—Wall Clock Counter Register

(Intel® High Definition Audio Controller—D27:F0)..................................... 679

17.2.16SSYNC—Stream Synchronization Register

(Intel® High Definition Audio Controller—D27:F0)..................................... 679

17.2.17CORBLBASE—CORB Lower Base Address Register

(Intel® High Definition Audio Controller—D27:F0)..................................... 680

17.2.18CORBUBASE—CORB Upper Base Address Register

(Intel® High Definition Audio Controller—D27:F0)..................................... 680

17.2.19CORBWP—CORB Write Pointer Register

(Intel® High Definition Audio Controller—D27:F0)..................................... 680

17.2.20CORBRP—CORB Read Pointer Register

(Intel® High Definition Audio Controller—D27:F0)..................................... 681

17.2.21CORBCTL—CORB Control Register

(Intel® High Definition Audio Controller—D27:F0)..................................... 681

17.2.22CORBST—CORB Status Register

(Intel® High Definition Audio Controller—D27:F0)..................................... 682

17.2.23CORBSIZE—CORB Size Register

Intel® High Definition Audio Controller—D27:F0)...................................... 682

17.2.24RIRBLBASE—RIRB Lower Base Address Register

(Intel® High Definition Audio Controller—D27:F0)..................................... 682

17.2.25RIRBUBASE—RIRB Upper Base Address Register

(Intel® High Definition Audio Controller—D27:F0)..................................... 683

17.2.26RIRBWP—RIRB Write Pointer Register

(Intel® High Definition Audio Controller—D27:F0)..................................... 683

17.2.27RINTCNT—Response Interrupt Count Register

(Intel® High Definition Audio Controller—D27:F0)..................................... 684

17.2.28RIRBCTL—RIRB Control Register

(Intel® High Definition Audio Controller—D27:F0)..................................... 684

17.2.29RIRBSTS—RIRB Status Register

(Intel® High Definition Audio Controller—D27:F0)..................................... 685

17.2.30RIRBSIZE—RIRB Size Register

(Intel® High Definition Audio Controller—D27:F0)..................................... 685

17.2.31IC—Immediate Command Register

(Intel® High Definition Audio Controller—D27:F0)..................................... 685

28 Intel® ICH8 Family Datasheet

17.2.32IR—Immediate Response Register

(Intel® High Definition Audio Controller—D27:F0).....................................686

17.2.33IRS—Immediate Command Status Register

(Intel® High Definition Audio Controller—D27:F0).....................................686

17.2.34DPLBASE—DMA Position Lower Base Address Register

(Intel® High Definition Audio Controller—D27:F0).....................................687

17.2.35DPUBASE—DMA Position Upper Base Address Register

(Intel® High Definition Audio Controller—D27:F0).....................................687

17.2.36SDCTL—Stream Descriptor Control Register

(Intel® High Definition Audio Controller—D27:F0).....................................688

17.2.37SDSTS—Stream Descriptor Status Register

(Intel® High Definition Audio Controller—D27:F0).....................................690

17.2.38SDLPIB—Stream Descriptor Link Position in Buffer

17.2.39SDCBL—Stream Descriptor Cyclic Buffer Length Register

(Intel® High Definition Audio Controller—D27:F0).....................................691

17.2.40SDLVI—Stream Descriptor Last Valid Index Register

(Intel® High Definition Audio Controller—D27:F0).....................................692

17.2.41SDFIFOW—Stream Descriptor FIFO Watermark Register

(Intel® High Definition Audio Controller—D27:F0).....................................692

17.2.42SDFIFOS—Stream Descriptor FIFO Size Register

(Intel® High Definition Audio Controller—D27:F0).....................................693

17.2.43SDFMT—Stream Descriptor Format Register

(Intel® High Definition Audio Controller—D27:F0).....................................694

17.2.44SDBDPL—Stream Descriptor Buffer Descriptor List Pointer Lower

Base Address Register

(Intel® High Definition Audio Controller—D27:F0).....................................695

17.2.45SDBDPU—Stream Descriptor Buffer Descriptor List Pointer

Upper Base Address Register (Intel® High Definition Audio

Controller—D27:F0)..............................................................................695

18 PCI Express* Configuration Registers....................................................................697

18.1 PCI Express* Configuration Registers

(PCI Express—D28:F0/F1/F2/F3/F4/F5)..............................................................697

18.1.1 VID—Vendor Identification Register

(PCI Express—D28:F0/F1/F2/F3/F4/F5)...................................................700

18.1.2 DID—Device Identification Register

(PCI Express—D28:F0/F1/F2/F3/F4/F5)...................................................700

18.1.3 PCICMD—PCI Command Register

(PCI Express—D28:F0/F1/F2/F3/F4/F5)...................................................701

18.1.4 PCISTS—PCI Status Register

(PCI Express—D28:F0/F1/F2/F3/F4/F5)...................................................702

18.1.5 RID—Revision Identification Register

(PCI Express—D28:F0/F1/F2/F3/F4/F5)...................................................703

18.1.6 PI—Programming Interface Register

(PCI Express—D28:F0/F1/F2/F3/F4/F5)...................................................703

18.1.7 SCC—Sub Class Code Register

(PCI Express—D28:F0/F1/F2/F3/F4/F5)...................................................703

18.1.8 BCC—Base Class Code Register

(PCI Express—D28:F0/F1/F2/F3/F4/F5)...................................................703

18.1.9 CLS—Cache Line Size Register

(PCI Express—D28:F0/F1/F2/F3/F4/F5)...................................................704

18.1.10PLT—Primary Latency Timer Register

(PCI Express—D28:F0/F1/F2/F3/F4/F5)...................................................704

18.1.11HEADTYP — He ad er Ty pe Re g is t er

(PCI Express—D28:F0/F1/F2/F3/F4/F5)...................................................704

18.1.12BNUM—Bus Number Register

(PCI Express—D28:F0/F1/F2/F3/F4/F5)...................................................704

Intel® ICH8 Family Datasheet 29

18.1.13SLT—Secondary Latency Timer

(PCI Express—D28:F0/F1/F2/F3/F4/F5)................................................... 705

18.1.14IOBL—I/O Base and Limit Register

(PCI Express—D28:F0/F1/F2/F3/F4/F5)................................................... 705

18.1.15SSTS—Secondary Status Register

(PCI Express—D28:F0/F1/F2/F3/F4/F5)................................................... 706

18.1.16MBL—Memory Base and Limit Register

(PCI Express—D28:F0/F1/F2/F3/F4/F5)................................................... 707

18.1.17PMBL—Prefetchable Memory Base and Limit Register

(PCI Express—D28:F0/F1/F2/F3/F4/F5)................................................... 707

18.1.18PMBU32—Prefetchable Memory Base Upper 32 Bits

18.1.19PMLU32—Prefetchable Memory Limit Upper 32 Bits

18.1.20CAPP—Capabilities List Pointer Register

(PCI Express—D28:F0/F1/F2/F3/F4/F5)................................................... 708

18.1.21INTR—Interrupt Information Register

(PCI Express—D28:F0/F1/F2/F3/F4/F5)................................................... 709

18.1.22BCTRL—Bridge Control Register

(PCI Express—D28:F0/F1/F2/F3/F4/F5)................................................... 709

18.1.23CLIST—Capabilities List Register

(PCI Express—D28:F0/F1/F2/F3/F4/F5)................................................... 710

18.1.24XCAP—PCI Express* Capabilities Register

(PCI Express—D28:F0/F1/F2/F3/F4/F5)................................................... 710

18.1.25DCAP—Device Capabilities Register

(PCI Express—D28:F0/F1/F2/F3/F4/F5)................................................... 711

18.1.26DCTL—Device Control Register

(PCI Express—D28:F0/F1/F2/F3/F4/F5)................................................... 712

18.1.27DSTS—Device Status Register

(PCI Express—D28:F0/F1/F2/F3/F4/F5)................................................... 713

18.1.28LCAP—Link Capabilities Register

(PCI Express—D28:F0/F1/F2/F3/F4/F5)................................................... 713

18.1.29LCTL—Link Control Register

(PCI Express—D28:F0/F1/F2/F3/F4/F5)................................................... 715

18.1.30LSTS—Link Status Register

(PCI Express—D28:F0/F1/F2/F3/F4/F5)................................................... 716

18.1.31SLCAP—Slot Capabilit ies Register

(PCI Express—D28:F0/F1/F2/F3/F4/F5)................................................... 717

18.1.32SLCTL—Slot Control Register

(PCI Express—D28:F0/F1/F2/F3/F4/F5)................................................... 718

18.1.33SLSTS—Slot Status Register

(PCI Express—D28:F0/F1/F2/F3/F4/F5)................................................... 719

18.1.34RCTL—Root Control Register

(PCI Express—D28:F0/F1/F2/F3/F4/F5)................................................... 720

18.1.35RSTS—Root Status Register

(PCI Express—D28:F0/F1/F2/F3/F4/F5)................................................... 720

18.1.36MID—Message Signaled Interrupt Identifiers Register

(PCI Express—D28:F0/F1/F2/F3/F4/F5)................................................... 721

18.1.37MC—Message Signaled Interrupt Message Control Register

(PCI Express—D28:F0/F1/F2/F3/F4/F5)................................................... 721

18.1.38MA—Message Signaled Interrupt Message Address

18.1.39MD—Message Signaled Interrupt Message Data Register

(PCI Express—D28:F0/F1/F2/F3/F4/F5)................................................... 722

18.1.40SVCAP—Subsystem Vendor Capa bility Register

(PCI Express—D28:F0/F1/F2/F3/F4/F5)................................................... 722

30 Intel® ICH8 Family Datasheet

18.1.41SVID—Subsystem Vendor Identification Register

(PCI Express—D28:F0/F1/F2/F3/F4/F5)...................................................722

18.1.42PMCAP—Power Management Capability Register

(PCI Express—D28:F0/F1/F2/F3/F4/F5)...................................................722

18.1.43PMC—PCI Power Management Capabilities Register

(PCI Express—D28:F0/F1/F2/F3/F4/F5)...................................................723

18.1.44PMCS—PCI Power Management Control and Status

18.1.45MPC—Miscellaneous Port Configuration Register

(PCI Express—D28:F0/F1/F2/F3/F4/F5)...................................................725

18.1.46SMSCS—SMI/SCI Status Register

(PCI Express—D28:F0/F1/F2/F3/F4/F5)...................................................727

18.1.47RPDCGEN—Root Port Dynamic Clock Gating Enable

(PCI Express-D28:F0/F1/F2/F3/F4/F5) (Mobile Only) ....................................................... 728

18.1.48IPWS—Intel® PRO/Wireless 3945ABG Status

(PCI Express—D28:F0/F1/F2/F3/F4/F5)...................................................728

18.1.49VCH—Virtual Channel Capability Header Register

(PCI Express—D28:F0/F1/F2/F3/F4/F5)...................................................729

18.1.50VCAP2—Virtual Channel Capability 2 Register

(PCI Express—D28:F0/F1/F2/F3/F4/F5)...................................................729

18.1.51PVC—Port Virtual Channel Control Register

(PCI Express—D28:F0/F1/F2/F3/F4/F5)...................................................729

18.1.52PVS — Port Virtual Channel Status Register

(PCI Express—D28:F0/F1/F2/F3/F4/F5)...................................................729

18.1.53V0CAP — Virtual Channel 0 Resource Capability Register

(PCI Express—D28:F0/F1/F2/F3/F4/F5)...................................................730

18.1.54V0CTL — Virtual Channel 0 Resource Control Register

(PCI Express—D28:F0/F1/F2/F3/F4/F5)...................................................731

18.1.55V0STS — Virtual Channel 0 Resource Status Register

(PCI Express—D28:F0/F1/F2/F3/F4/F5)...................................................731

18.1.56UES — Uncorrectable Error Status Register

(PCI Express—D28:F0/F1/F2/F3/F4/F5)...................................................732

18.1.57UEM — Uncorrectable Error Mask

(PCI Express—D28:F0/F1/F2/F3/F4/F5)...................................................733

18.1.58UEV — Uncorrectable Error Severity

(PCI Express—D28:F0/F1/F2/F3/F4/F5)...................................................734

18.1.59CES — Correctable Error Status Register

(PCI Express—D28:F0/F1/F2/F3/F4/F5)...................................................735

18.1.60CEM — Correctable Error Mask Register

(PCI Express—D28:F0/F1/F2/F3/F4/F5)...................................................736

18.1.61AECC — Advanced Error Capabilities and Control Register

(PCI Express—D28:F0/F1/F2/F3/F4/F5)...................................................736

18.1.62RES — Root Error Status Register

(PCI Express—D28:F0/F1/F2/F3/F4/F5)...................................................737

18.1.63RCTCL — Root Complex Topology Capability List Register

(PCI Express—D28:F0/F1/F2/F3/F4/F5)...................................................737

18.1.64ESD — Element Self Description Register

(PCI Express—D28:F0/F1/F2/F3/F4/F5)...................................................738

18.1.65ULD — Upstream Link De scription Register

(PCI Express—D28:F0/F1/F2/F3/F4/F5)...................................................738

18.1.66ULBA — Upstream Link Base Address Register

(PCI Express—D28:F0/F1/F2/F3/F4/F5)...................................................739

18.1.67PEETM — PCI Express* Extended Test Mode Register

(PCI Express—D28:F0/F1/F2/F3/F4/F5)...................................................739

19 High Precision Event Timer Registers.....................................................................741

19.1 Memory-Mapped Registers................................................................................741

19.1.1 GCAP_ID—General Capabilities and Identification Register .........................742

Intel® ICH8 Family Datasheet 31

19.1.2 GEN_CONF—General Configuration Register............................................. 743

19.1.3 GINTR_STA—General Interrupt Status Register ........................................ 743

19.1.4 MAIN_CNT—Main Counter Value Register ................................................ 744

19.1.5 TIMn_CONF—Timer n Configuration and Capabilities Register..................... 744

19.1.6 TIMn_COMP—Tim er n Comparator Value Regi ster............................. .. .. .. .. 746

20 Serial Peripheral Interface (SPI) ........................................................................... 747

20.1 Serial Peripheral Interface Memory-Mapped Configuration Registers....................... 747

20.1.1 B FPR—BIOS Flash Primary Region Register

(SPI Memory Mapped Conf iguration Registers).............. ............ ... .. .. .. ...... 748

20.1.2 HSFS—Hardware Sequencing Flash Status Register

(SPI Memory Mapped Conf iguration Registers).............. ............ ... .. .. .. ...... 749

20.1.3 HSFC—Hardware Sequencing Flash Control Register

(SPI Memory Mapped Conf iguration Registers).............. ............ ... .. .. .. ...... 750

20.1.4 FADDR—Flash Address Register

(SPI Memory Mapped Conf iguration Registers).............. ............ ... .. .. .. ...... 751

20.1.5 FDATA0—Flash Data 0 Register

(SPI Memory Mapped Conf iguration Registers).............. ............ ... .. .. .. ...... 751

20.1.6 FDATAN—Flash Data [N] Register

(SPI Memory Mapped Conf iguration Registers).............. ............ ... .. .. .. ...... 751

20.1.7 FRAP—Flash Regions Access Permissions Register

(SPI Memory Mapped Conf iguration Registers).............. ............ ... .. .. .. ...... 752

20.1.8 FREG0—Flash Region 0 (Flash Descriptor) Register

(SPI Memory Mapped Conf iguration Registers).............. ............ ... .. .. .. ...... 752

20.1.9 FREG1—Flash Region 1 (BIOS Descriptor) Register

(SPI Memory Mapped Conf iguration Registers).............. ............ ... .. .. .. ...... 753

20.1.10FREG2—Flash Region 2 (ME) Register

(SPI Memory Mapped Conf iguration Registers).............. ............ ... .. .. .. ...... 753

20.1.11FREG3—Flash Region 3 (GbE) Register

(SPI Memory Mapped Conf iguration Registers).............. ............ ... .. .. .. ...... 754

20.1.12PR0—Protected Range 0 Register

(SPI Memory Mapped Conf iguration Registers).............. ............ ... .. .. .. ...... 754

20.1.13PR1—Protected Range 1 Register

(SPI Memory Mapped Conf iguration Registers).............. ............ ... .. .. .. ...... 755

20.1.14PR2—Protected Range 2 Register

(SPI Memory Mapped Conf iguration Registers).............. ............ ... .. .. .. ...... 755

20.1.15PR3—Protected Range 3 Register

(SPI Memory Mapped Conf iguration Registers).............. ............ ... .. .. .. ...... 756

20.1.16PR4—Protected Range 4 Register

(SPI Memory Mapped Conf iguration Registers).............. ............ ... .. .. .. ...... 756

20.1.17SSFS—Software Sequencing Flash Status Register

(SPI Memory Mapped Conf iguration Registers).............. ............ ... .. .. .. ...... 757

20.1.18SSFC—Software Sequencing Flash Control Register

(SPI Memory Mapped Conf iguration Registers).............. ............ ... .. .. .. ...... 758

20.1.19PREOP—Prefix Opcode Configuration Register

(SPI Memory Mapped Conf iguration Registers).............. ............ ... .. .. .. ...... 759

20.1.20OPTYPE—Opcode Type Configuration Register

(SPI Memory Mapped Conf iguration Registers).............. ............ ... .. .. .. ...... 759

20.1.21OPMENU—Opcode Menu Configuration Register

(SPI Memory Mapped Conf iguration Registers).............. ............ ... .. .. .. ...... 760

20.1.22FDOC—Flash Descriptor Observability Control Register

(SPI Memory Mapped Conf iguration Registers).............. ............ ... .. .. .. ...... 761

20.1.23FDOD—Flash Descriptor Observability Data Register

(SPI Memory Mapped Conf iguration Registers).............. ............ ... .. .. .. ...... 761

20.1.24VSCC—Vendor Specific Component Capabilities Register

(SPI Memory Mapped Conf iguration Registers).............. ............ ... .. .. .. ...... 762

20.2 Flash Descriptor Registers ................................................................................ 763

32 Intel® ICH8 Family Datasheet

20.2.1 Flash Descriptor Content............... .. .. .. ...................................................763

20.2.1.1 FLVALSIG—Flash Valid Signature Register

(Flash Descriptor Memory Mapped Configuration Registers) ..........763

20.2.1.2 FLMAP0—Flash Map 0 Register

(Flash Descriptor Memory Mapped Configuration Registers) ..........763

20.2.1.3 FLMAP1—Flash Map 1 Register

(Flash Descriptor Memory Mapped Configuration Registers) ..........764

20.2.1.4 FLMAP2—Flash Map 2 Register

(Flash Descriptor Memory Mapped Configuration Registers) ..........764

20.2.2 Flash Descriptor Component Section ................... .. ............. .. ............. .. .. ..765

20.2.2.1 FLCOMP—Flash Compone n ts Register

(Flash Descriptor Memory Mapped Configuration Registers) ..........765

20.2.2.2 FLILL—Flash Invalid Instructions Register

(Flash Descriptor Memory Mapped Configuration Registers) ..........766

20.2.3 Flash Descriptor Region Section........................ ............. .. ............. ..........767

20.2.3.1 FLREG0—Flash Region 0 (Flash Descriptor) Register

(Flash Descriptor Memory Mapped Configuration Registers) ..........767

20.2.3.2 FLREG1—Flash Region 1 (BIOS) Register

(Flash Descriptor Memory Mapped Configuration Registers) ..........767

20.2.3.3 FLREG2—Flash Region 2 (ME) Register

(Flash Descriptor Memory Mapped Configuration Registers) ..........768

20.2.3.4 FLREG3—Flash Region 3 (GbE) Register

(Flash Descriptor Memory Mapped Configuration Registers) ..........768

20.2.4 Flash Descriptor Master Se ction................ ............ ............. ............. ........769

20.2.4.1 FLMSTR1—Flash Master 1 (Host Processor/ BIOS)................ .. .. .. ..769

20.2.4.2 FLMSTR2—Flash Master 2 (ME) .................................................769

20.2.4.3 FLMSTR3—Flash Master 3 (GbE)................................................770

20.2.5 Flash Descriptor Strap............ .. ....................... ....................... ...............771

20.2.5.1 STRP0—Strap 0 Register

(Flash Descriptor Memory Mapped Configuration Registers) ..........771

20.2.5.2 STRP1—Strap 1 Register

(Flash Descriptor Memory Mapped Configuration Registers) ..........772

20.2.5.3 FLUMAP1—Flash Upper Map 1...................................................773

20.2.5.4 JID0—JEDEC-ID 0 Register.......................................................773

20.2.5.5 VSCC0—Vendor Specific Component Capabilities 0.......................773

20.2.5.6 JID0—JEDEC-ID n Register.......................................................774

20.2.5.7 VSCC0n—Vendor Specific Component Capabilities n. ....................775

20.2.5. 8 OEM Section.............. .. .. ........... .. .. .......... ... .. .......... .. ........... .. ..776

20.3 GbE SPI Flash Program Registers.......................................................................776

20.3.1 GLFPR—Gigabit LAN Flash Primary Region Register

(GbE LAN Memory Mapped Configuration Registers) ..................................777

20.3.2 HSFS—Hardware Sequencing Flash Status Register

(GbE LAN Memory Mapped Configuration Registers) ..................................778

20.3.3 HSFC—Hardware Sequencing Flash Control Register

(GbE LAN Memory Mapped Configuration Registers) ..................................779

20.3.4 FADDR—Flash Address Register

(GbE LAN Memory Mapped Configuration Registers) ..................................780

20.3.5 FDATA0—Flash Data 0 Register

(GbE LAN Memory Mapped Configuration Registers) ..................................780

20.3.6 FRAP—Flash Regions Access Permissions Register

(GbE LAN Memory Mapped Configuration Registers) ..................................781

20.3.7 FREG0—Flash Region 0 (Flash Descriptor) Register

(GbE LAN Memory Mapped Configuration Registers) ..................................782

20.3.8 FREG1—Flash Region 1 (BIOS Descriptor) Register

(GbE LAN Memory Mapped Configuration Registers) ..................................782

20.3.9 FREG2—Flash Region 2 (ME) Register

(GbE LAN Memory Mapped Configuration Registers) ..................................783

Intel® ICH8 Family Datasheet 33

20.3.10FREG3—Flash Region 3 (GbE) Register

(GbE LAN Memory Mapped Configuration Registers).................................. 783

20.3.11PR0—Protected Range 0 Register

(GbE LAN Memory Mapped Configuration Registers).................................. 784

20.3.12PR1—Protected Range 1 Register

(GbE LAN Memory Mapped Configuration Registers).................................. 784

20.3.13SSFS—Software Sequencing Flash Status Register

(GbE LAN Memory Mapped Configuration Registers).................................. 785

20.3.14SSFC—Software Sequencing Flash Control Register

(GbE LAN Memory Mapped Configuration Registers).................................. 786

20.3.15PREOP—Prefix Opcode Configuration Register

(GbE LAN Memory Mapped Configuration Registers).................................. 787

20.3.16OPTYPE—Opcode Type Configuration Register

(GbE LAN Memory Mapped Configuration Registers).................................. 787

20.3.17OPMENU—Opcode Menu Configuration Register

(GbE LAN Memory Mapped Configuration Registers).................................. 788

21 Thermal Sensor Registers (D31:F6)....................................................................... 789

21.1 PCI Bus Configuration Registers ........................................................................ 789

21.1.1 VID—Vendor Identification..................................................................... 790

21.1.2 DID—Device Identification.... .. .. .. ........................................................... 790

21.1.3 CMD—Command .................................................................................. 790

21.1.4 STS—Status ........................................................................................ 791

21.1.5 RID—Revision Identification................................................................... 791

21.1.6 PI— Programming Interface................................................................... 791

21.1.7 SCC—Sub Class Code ........................................................................... 792

21.1.8 BCC—Base Class Code ............... ........... .. .. ..................... .. .. ................... 792

21.1.9 CLS—Cache Line Size............................................................................ 792

21.1.10LT—Latency Tim er................... .. ........... .. .. .......... ... .. .......... .. .. ... .......... .. 792

21.1.11HTYPE—Header Type ............................................................................ 792

21.1.12BIST—Built-in Self Test......................................................................... 793

21.1.13TBAR—Thermal Base ............................................................................ 793

21.1.14TBARH—Thermal Base High DWord......................................................... 793

21.1.15SVID—Subsyste m Ve nd or ID .... .. .. ..................... .. ... .. ..................... .. .. .. .. 794

21.1.16SID—Subsystem ID.............................................................................. 794

21.1.17CAP_PTR —Capabilities Pointer............................................................... 794

21.1.18INTLN—Interrupt Line........................................................................... 794

21.1.19INTPN—Interrupt Pin ....... .. .. .......................................... .. .. .. ................. 795

21.1.20TBARB—BIOS Assigned Thermal Base Address ......................................... 795

21.1.21TBARBH—BIOS Assigned Thermal Base High DWord ................................. 795

21.1.22PID—PCI Power Management Capability ID.............................................. 796

21.1.23PC—Power Management Capabilities....................................................... 796

21.1.24PCS—Power Management Control And Status........................................... 797

21.2 Thermal Memory Mapped Configuration Registers

(Thermal Sensor - D31:F26)............................................................................. 798

21.2.1 TSxE—Thermal Sensor [1:0] Enable ....................................................... 798

21.2.2 TSxS—Thermal Se nsor[1 :0 ] Status............... .. .. .. ............. ............. .......... 798

21.2.3 TSxTTP—Thermal Sensor [1:0] Catastrophic Trip Point.............................. 798

21.2.4 TSxCO—Thermal Sensor [1:0] Catastrophic Lock-Down............................. 799

21.2.5 TSxPC—Thermal Sensor [1:0] Policy Control............................................ 799

21.2.6 TSxLOCK—Thermal Sensor [1:0] Register Lock Control ............................. 799

22 Ballout Definition................................................................................................... 801

22.1 Ballout (Desktop Only)..................................................................................... 801

22.2 Ballout (Mobile Only) ....................................................................................... 810

23 Electrical Characteristics ....................................................................................... 819

34 Intel® ICH8 Family Datasheet

23.1 Thermal Spe cifications.......... .. .. ................................ .. .. .. ..................... ... .. .. ......819

23.2 Absolute Maximum Ratings4 .............................................................................819

23.3 DC Characteristics ............. .. .. ..................... .. ... .. .......... .. .. ... ..................... .. .. .. ..820

23.4 AC Characteristics................................. .. .. .. ..................... ... .. .. .......... .. ... .. ........832

23.5 Timing Diagrams ................... ........... .. .. ........... .. .. ..................... .. .. ........... .. .. ....851

24 Package Information .............................................................................................867

24.1 Package Dimensions (Desktop Only)...................................................................867

24.2 Package Dimensions (Mobile Only).....................................................................869

A Register Bit Index..................................................................................................872

Intel® ICH8 Family Datasheet 35

Figures

Note:Desktop Configuration.............................................................................................43

Note:Mobile Configuration ...............................................................................................43

1Intel

® ICH8 Interface Signals Block Diagram (Desktop).................................................58

2Intel

® ICH8 Interface Signals Block Diagram (Mobile)...................................................59

3 Example External RTC Circuit.....................................................................................90

4 Desktop Conceptual System Clock Diagram .......... ..................................................... 108

5 Mobile Conceptual Clock Diagram........ .. .. .. .. .. .. .. ....................................................... 108

6 Generation of SERR# to Platform ............................................................................. 115

7 LPC Interface Diagram............................................................................................ 124

8Intel

® ICH8 DMA Controller..................................................................................... 129

9 DMA Request Assertion through LDRQ# .................................................................... 132

10 Coprocessor Error Timing Diagram ........................................................................... 157

11 Advanced TCO Intel® AMT Mode SMBus/SMLink Configuration..................................... 187

12 Advanced TCO BMC Mode SMBus/SMLink Configuration............................................... 188

13 Physical Region Descriptor Table Entry...................................................................... 191

14 SATA Power States................................................................................................. 200

15 USB Legacy Keyboard Flow Di agram...... ............ .. ........................ ............................. 211

16 Intel® ICH8-USB Port Connections .......................................................................... 218

17 Flash Descriptor..................................................................................................... 244

18 Ballout (Top View–Left Side) (Desktop Only).............................................................. 802

19 Ballout (Top View–Right Side) (Desktop Only)............................................................ 803

20 Ballout (Top View–Left Side) (Mobile Only)................................................................ 810

21 Ballout (Top View–Right Side) (Mobile Only).............................................................. 811

22 Clock Timing ......................................................................................................... 851

23 Valid Delay from Rising Clock Edge........................................................................... 851

24 Setup and Hold Times ............................................................................................. 852

25 Float Delay............................................................................................................ 852

26 Pulse Width.............. ... .......... .. .. ........... .. .......... ... .. .......... .. ........... .. ........... .. .. ........ 852

27 Output Enable Delay............................................................................................... 852

28 IDE PIO Mode (Mobile Only) .................................................................................... 853

29 IDE Multiword DMA (Mobile Only)............................................................................. 853

30 Ultra ATA Mode (Drive Initiating a Burst Read) (Mobile Only) ....................................... 854

31 Ultra ATA Mode (Sustained Burst) (Mobile Only)......................................................... 854

32 Ultra ATA Mode (Pausing a DMA Burst) (Mobile Only).................................................. 855

33 Ultra ATA Mode (Terminating a DMA Burst) (Mobile Only)............................................ 855

34 USB Rise and Fall Times.......................................................................................... 856

35 USB Jitter ............................................................................................................. 856

36 USB EOP Width...................................................................................................... 856

37 SMBus Tran saction.... ... .......... .. .. ........... .. .......... ... .......... .. .. ........... .. ........... .. .. ........ 857

38 SMBus Timeou t.................... .. ........... .. .. .......... .. ........... .. .. ........... .. .......... ... .......... .. 857

39 Power Sequencing and Reset Signal Timings.............................................................. 858

40 G3 (Mechanical Off) to S0 Timings............................................................................ 859

41 S0 to S1 to S0 Timing............................................................................................. 860

42 S0 to S5 to S0 Timings, S3 (Desktop Only) ............................................................... 860

43 S0 to S5 to S0 Timings, S3 (Mobile Only) .................................................................. 861

44 C0 to C2 to C0 Timings (Mobile Only) ....................................................................... 861

45 C0 to C3 to C0 Timings (Mobile Only) ....................................................................... 862

46 C0 to C4 to C0 Timings (Mobile Only) ....................................................................... 862

47 Intel® High Definition Audio Input and Output Timings................................................ 863

48 SPI Timings........................................................................................................... 863

49 Sleep control signal relationship – Host boots and ME off............................................. 864

50 Sleep control signal relationship – Host and ME boot after G3 ...................................... 864

36 Intel® ICH8 Family Datasheet

51 Sleep Control Signal Relationship – Host stays in S5 and ME boots after

G3865

52 S0 to G3 PWROK and Vcc Timing..............................................................................865

53 S0 to G3 Timings (Mobile Only)................................................................................865

54 Package Dimensions (Top View) (Desktop Only) .........................................................867

55 Package Dimensions (Bottom View) (Desktop Only) ............ ............. .. .. .. ............. .. .. .. ..868

56 Package Dimensions (Side View) (Desktop Only) ........................................................868

57 Package Dimensions (Top View) (Mobile Only)............................................................869

58 Package Dimensions (Bottom View) (Mobile Only)............. .. .. .. .. .. ............. .. .. .. ... ..........870

59 Package Dimensions (Side View) (Mobile Only)...........................................................870

Tables

1 Industry Specifications........ .......... .. ... .. ..................... .. .. .. ..................... .. .. .. ...............45

2 PCI Devices and Functions.........................................................................................49

3Intel

® ICH8 Desktop/Server Family ............................................................................55

4Intel

® ICH8 Mobile Family .........................................................................................55

5 Direct Media Interface Signals....................................................................................60

6 PCI Express* Signals ................................................................................................60

7 LAN Connect Interface Signals....................................................................................61

8 Gigabit LAN Connect Interface Signals........ .. .. .. .. .. .. ... ............ ............. .. ............. .. ........61

9 Firmware Hub Interface Signals..................................................................................62

10 PCI Interface Signals ................................................................................................63

11 Serial ATA Interface Signals........................ .. .............................................................66

12 IDE Interface Signals (Mobile Only).............................................................................68

13 LPC Interface Signals................................................................................................69

14 Interrupt Signals ......................................................................................................70

15 USB Interface Signals ............... ........... .. .. ..................... .. .. ..................... .. .. ...............71

16 Power Management Interface Signals..........................................................................72

17 Processor Interface Signals........................................................................................75

18 SM Bus Interface Signals...........................................................................................77

19 System Management Interface Signals........................................................................77

20 Real Time Clock Interface..........................................................................................78

21 Other Clocks............................................................................................................ 79

22 Miscellaneous Sign als.......... .......... .. ... .......... .. .. ........... .. .. ........... .. .. ..................... .. .. ..79

23 Intel® High Definition Audio Link Signals ..................................................................... 80

24 Serial Peripheral Interface (SPI) Signals ......................................................................81

25 Intel® Quick Resume Technology Signals.....................................................................82

26 Controller Link Signals ..............................................................................................82

27 Intel® Quiet System Technology Signals....... .. .. .. ........... .. .. ........... .. .. .......... .. ... .......... ..83

28 General Purpose I/O Signals ......................................................................................83

29 Power and Ground Signals.........................................................................................86

30 Functional Strap Definitions .......................................................................................88

31 Integrated Pull-Up and Pull-Down Resistors..................................................................91

32 IDE Series Termination Resistors................................................................................92

33 Power Plane and States for Output and I/O Signals for Desktop

Configurations93

34 Power Plane and States for Output and I/O Signals for Mobile

Configurations98

35 Power Plane for Input Signals for Desktop Configurations.............................................102

36 Power Plane for Input Signals for Mobile Configurations...............................................104

37 Intel® ICH8 and System Clock Domains ....................................................................107

38 PCI Bridge Initiator Cycle Types ...............................................................................109

39 Type 1 Address Format ...........................................................................................112

40 MSI vs. PCI IRQ Actions ...... .. .. .. ............. ....................................................... ..........113

Intel® ICH8 Family Datasheet 37

41 LAN Mode Support ................................................................................................. 120

42 LPC Cycle Types Supported ..................................................................................... 125

43 Start Field Bit Definitions ................... .. .. .. .. .. ........................................................... 125

44 Cycle Type Bit Definitions........ .. .......................................... .. ... .. ..................... .. .. .. .. 126

45 Transfer Size Bit Definition...................................................................................... 126

46 SYNC Bit Definition................................................................................................. 127

47 DMA Transfer Size.................................................................................................. 131

48 Address Shifting in 16-Bit I/O DMA Transfers............................................................. 131

49 Counter Operating Modes...... .. .. .. ........... .. .. .. ........... .. .. ..................... .. .. ................... 137

50 Interrupt Controller Core Connections....................................................................... 139

51 Interrupt Status Registers....................................................................................... 140

52 Content of Interrupt Vector Byte.............................................................................. 140

53 APIC Interrupt Mapping ................ ... .......... .. .. ..................... .. ... ..................... .. .. .. .... 146

54 Interrupt Message Address Format........................................................................... 148

55 Interrupt Message Data Format................................................................................ 149

56 Stop Frame Explanation.......................................................................................... 150

57 Data Frame Format................ .. .. ..................... .. ... ..................... .. .. .. ........... .. .. ........ 151

58 Configuration Bits Reset by RTCRST# Assertion ......................................................... 154

59 INIT# Going Active ................................................................................................ 156

60 NMI Sources............. ........... .. ........... .. .. .......... .. ........... .. .. ........... .. .......... ... .......... .. 157

61 DP Signal Differences ............................................................................................. 158

62 General Power States for Systems Using Intel® ICH8.... .. .. ........... .. .......... .. ........... .. .... 160

63 State Transition Rules for Intel® ICH8 ...................................................................... 161

64 System Power Plane............................................................................................... 162

65 Causes of SMI# and SCI......................................................................................... 163

66 Break Events (Mobile Only) ..................................................................................... 166

67 Sleep Types ......... .. ........... .. ........... .. .. .......... .. ........... .. .. ........... .. .......... .. ........... .. .. 170

68 Causes of Wake Events........................................................................................... 170

69 GPI Wake Events .... ........... .. .. ........... .. .. .......... .. ... .......... .. .. .. ........... .. .. ........... .. .. .... 171

70 Transitions Due to Power Failure .............................................................................. 172

71 Transitions Due to Power Button .............................................................................. 174

72 Transitions Due to RI# Signal.................................................................................. 175

73 Write Only Registers with Read Paths in ALT Access Mode ........................................... 178

74 PIC Reserved Bits Return Values .............................................................................. 180

75 Register Write Accesses in ALT Access Mode.............................................................. 180

76 Intel® ICH8 Clock Inputs ........................................................................................ 182

77 TCO Legacy/Compatible Mode SMBus Configuration.................................................... 186

78 Event Transitions that Cause Messages..................................................................... 186

79 IDE Transaction Timings (PCI Clocks) ...................................................................... 190

80 Interrupt/Active Bit Interaction Definition.................................................................. 193

81 SATA Feature Support ............................................................................................ 196

82 SATA Feature Support ............................................................................................ 197

83 Legacy Replacement Routing................................................................................... 203

84 Bits Maintained in Low Power States......................................................................... 210

85 USB Legacy Keyboard State Transitions ....... .. ........................................................... 211

86 UHCI vs. EHCI....................................................................................................... 213

87 Debug Port Behavior .............................................................................................. 221

88 I2C Block Read ...................................................................................................... 228

89 Enable for SMBALERT#........................................................................................... 231

90 Enables for SMBus Slave Write and SMBus Host Events............................................... 231

91 Enables for the Host Notify Command....................................................................... 231

92 Slave Write Registers ................. .. ... .......... .. .. .. ........... .. .. ........... .. .. .......... ... .. .......... 233

93 Command Types.................................................................................................... 234

94 Slave Read Cycle Format ........................................................................................ 235

95 Data Values for Slave Read Registers........................................................................ 235

38 Intel® ICH8 Family Datasheet

96 Host Notify Format .................................................................................................237

97 Required Commands and Opcodes. ...........................................................................247

98 Recommended Command and Opcode Associations............... .. .. ............. .. .. .. .. .............248

99 PCI Devices and Functions.......................................................................................256

100 Fixed I/O Ranges Decoded by Intel® ICH8.................................................................258

101 Variable I/O Decode Range s... .. .. .. .. .. ........................................................................260

102 Memory Decode Ranges from Processor Perspective....................................................261

103 Chipset Configuration Register Memory Map (Memory Space).......................................265

104 Gigabit LAN Configuration Registers Address Map

(Gigabit LAN —D25:F0)................................................. .. .. .. ........... .. .. .. ...................309

105 LPC Interface PCI Register Address Map (LPC I/F—D31:F0)..........................................323

106 DMA Registers .......................................................................................................344

107 PIC Registers (LPC I/F—D31:F0).......... .......... .. .. ..................... .. ... ..................... .. .. ....356

108 APIC Direct Registers (LPC I/F—D31:F0)....................................................................364

109 APIC Indirect Registers (LPC I/F—D31:F0).................................................................364

110 RTC I/O Registers (LPC I/F—D31:F0) ........................................................................369

111 RTC (Standard) RAM Bank (LPC I/F—D31:F0).............................................................370

112 Processor Interface PCI Register Address Map (LPC I/F—D31:F0)..................................374

113 Power Management PCI Register Address Map (PM—D31:F0) .......................................377

114 APM Register Map...................................................................................................390

115 ACPI and Legacy I/O Register Map............................................................................391

116 TCO I/O Register Address Map .................................................................................416

117 Registers to Control GPIO Address Map ................ .. ... .. .. .. .. ............. .. .. ............. .. .. .. ....423

118 PCI Bridge Register Address Map (PCI-PCI—D30:F0)...................................................431

119 IDE Controller PCI Register Address Map (IDE-D31:F1) ...............................................447

120 Bus Master IDE I/O Registers...................................................................................462

121 SATA Controller PCI Register Address Map (SATA–D31:F2) ..........................................465

122 SATA Indexed Registers ..........................................................................................491

123 Bus Master IDE I/O Register Address Map..................................................................502

124 AHCI Register Address Map......................................................................................512

125 Generic Host Controller Register Address Map ............................................................513

126 Port [3:0] DMA Register Address Map........................................................................521

127 SATA Controller PCI Register Address Map (SATA–D31:F5) ..........................................539

128 Bus Master IDE I/O Register Address Map..................................................................556

129 UHCI Controller PCI Conf igu r ation Map.............................. ............. ....................... ....565

130 UHCI Controller PCI Register Address Map (USB—D29:F0/F1/F2,

D26:F0/F1)565

131 USB I/O Registers ............ .. .......... .. ... ..................... .. .. .. .......... ... .. ..................... .. .. ..575

132 Run/Stop, Debug Bit Interaction SWDBG (Bit 5), Run/Stop (Bit 0)

Operation578

133 USB EHCI PCI Register Address Map (USB EHCI—D29:F7, D26:F7) .......................... .....585

134 Enhanced Host Controller Capability Registers............................................................603

135 Enhanced Host Controller Operational Register Address Map.........................................607

136 Debug Port Register Address Map .............................................................................620

137 SMBus Controller PCI Register Address Map (SMBUS—D31:F3).....................................625

138 SMBus I/O and Memory Mapped I/O Register Address Map ..........................................631

139 Intel® High Definition Audio PCI Register Address Map

(Intel® High Definition Audio D27:F0) .......................................................................643

140 Intel® High Definition Audio PCI Register Address Map

(Intel® High Definition Audio D27:F0) .......................................................................666

141 PCI Express* Configuration Registers Address Map

(PCI Express—D28:F0/F1/F2/F3/F4/F5).....................................................................697

142 Memory-Mapped Registers.......................................................................................741

143 Serial Peripheral Interface (SPI) Register Address Map

(SPI Memory Mappe d Conf igur ation Registers) .... .. .. ............. .. ............. .. ............. ........747

Intel® ICH8 Family Datasheet 39

144 Gigabit LAN SPI Flash Program Register Address Map

(GbE LAN Memory Mapped Configuration Registers).................................................... 776

145 Thermal Sensor Register Address Map (D31:F6)......................................................... 789

146 Ballout by Signal Name (Desktop Only)..................................................................... 804

147 Ballout by Signal Name (Mobile Only) ....................................................................... 812

148 Intel® ICH8 Absolute Maximum Ratings .................................................................... 819

149 DC Current Characteristics (Desktop Only) ................................................................ 820

150 DC Current Characteristics (Mobile Only)................................................................... 821

151 DC Characteristic Inpu t Signal Association................................................................. 822

152 DC Input Characteristics ......................................................................................... 823

153 DC Characteristic Output Signal Association............................................................... 826

154 DC Output Characteristics ....................................................................................... 828

155 Other DC Characteristics......................................................................................... 830

156 Clock Timings........................................................................................................ 832

157 PCI Interface Timing............................................................................................... 834

158 IDE PIO Mode Timings (Mobile Only)......................................................................... 835

159 IDE Multiword DMA Timings (Mobile Only)................................................................. 836

160 Ultra ATA Timing (Mode 0, Mode 1, Mode 2) (Mobile Only).......................................... 836

161 Ultra ATA Timing (Mode 3, Mode 4, Mode 5) (Mobile Only)......................................... 839

162 Universal Serial Bus Timing ...................... ...... ......................................................... 841

163 SATA Interface Timings........................................................................................... 842

164 SMBus Timi ng......... .. ... .......... .. ........... .. .......... .. ... .......... .. ........... .. .. ........... .. .......... 842

166 LPC Timing............................................................................................................ 843

167 Miscellaneous Timings ............................................................................................ 843

165 Intel® High Definition Audio Timing ... .. .. .. .. .. .. ........................................................... 843

168 SPI Timings (20 MHz)............................................................................................. 844

169 SPI Timings (33 MHz)............................................................................................. 844

170 SST Timings (Desktop Only)................................................................................... 845

171 PECI Timings (Desktop Only)................................................................................... 845

172 Power Sequencing and Reset Signal Timings.............................................................. 846

173 Power Management Timings.................................................................................... 848

40 Intel® ICH8 Family Datasheet

Revision History

§ §

Revision Description Date

-001 • Initial release. June 2006

-002 • Added 82801HDH ICH8 Digital Home (ICH8DH) and 82801HDO ICH8 Digital Office

(ICH8DO) July 2006

-003

•Added Intel

® 82801HBM ICH8 Mobile (ICH8M) and Intel® 82801HEM ICH8 Mobile

Enhanced (ICH8M-E)

• Added Documentation Changes, Specification Changes, and Specification Clarifications

from Specification Update, Rev -008.

May 2007

-004 • Added additional data for IRQ14 and IRQ15. May 2014

Intel® ICH8 Family Datasheet 41

Intel® ICH8 Features

Direct Media Interface

—10 Gb/s each direction, full duplex

—Transparent to software

PCI Express*

—6 PCI Express root ports

—Supports PCI Express 1.1

—Ports 1-4 can be statically

configured as four x1 or one x4

—Support for full 2.5 Gb/s bandwidth

in each direction per x1 lane

—Module based Hot-Plug supported

(e.g., ExpressCard*)

PCI Bus Interface

—Supports PCI Rev 2.3 Specification

at 33 MHz

—Four available PCI REQ/GNT pairs

—Support for 64-bit addressing on

PCI using DAC protocol

Integrated Serial ATA Host Controller

—NEW: Up to six SATA ports (Mobile

has 3 ports)

—NEW: External SATA support

(Desktop Only)

—Data transfer rates up to 3.0 Gb/s

(300 MB/s).

—Integrated AHCI controller

Intel® Matrix Storage Technology

(ICH8R, ICH8DH, ICH8DO, ICH8M-E

only)

—Configures the ICH8 SA TA controller

as a RAID controller supporting

RAID 0/1/5/10 in the ICH8R,

ICH8DH, ICH8DO, and supporting

Raid 0/1 in the ICH8M-E

Integrated IDE Controller (Mobile

only)

—Independent timing of up to two

drives

—Ultra ATA/1 00/66/33, BMIDE and

PIO modes

—Tri-state modes to enable swap bay

NEW:Intel® Active Management

Technology with System Defense

(ICH8DO and ICH8M-E only)

Intel® High Definition Audio Interface

—PCI Express endpoint

—Independent Bus Master logic for

eight general purpose streams: four

input and four output

—Support four external Codecs

—Supports variable length stream

slots

—Supports multichannel, 32-bit

sample depth, 192 kHz sample rate

output

—Provides mic array support

—Allows for non-48 kHz sampling

output

—Support for ACPI Device States

—Low Voltage Mode

—Docking Support (Mobile only)

NEW : Intel® Quiet System Technology

(Desktop Only)

—Four TACH signals and three PWM

signals

NEW: Simple Serial Transport (SST)

Bus and Platform Environmental

Control Interface (PECI) (Desktop

Only)

USB 2.0

—NEW: up to five UHCI Host

Controllers, supporting ten external

ports

—NEW: up to two EHCI Host

Controllers that supports ten ports

—NEW: Includes up to two USB 2.0

High-speed Debug Ports

—Supports wake-up from sleeping

states S1–S5

—Supports legacy Keyboard/Mouse

software

NEW: Integrated Gigabit LAN

Controller

—Integrated ASF Management

Controller

—NEW: Network security with System

Defense

—Supports IEEE 802.3

—LAN Connect Interface (LCI) and

new Gigabit LAN Connect Interface

(GLCI)

—10/100/1000 Mb/s Ethernet

Support

42 Intel® ICH8 Family Datasheet

Note: Not all features are available on all ICH8 components. See Section 1.2 for

more details.

Power Management Logic

—Supports ACPI 3.0

—ACPI-defined power states (C1, S1,

S3–S5 for Desktop and C1–C4, S1,

S3–S5 for Mobile)

—ACPI Power Management Timer

—(Mobile Only) Support for “Intel

SpeedStep® Technology” processor

power control and “Deeper Sleep”

power state

—PCI CLKRUN# (Mobile only) and

PME# support

—SMI# generation

—All registers readable/restorable for

proper resume from 0 V suspend

states

External Glue Integration

—Integrated Pull-up, Pull-down and

Series Termination resistors on IDE

(Mobile only), processor interface

—Integrated Pull-down and Series

resistors on USB

SMBus

—NEW: faster speed, up to 100 kbps

—Flexible SMBus/SMLINK

architecture to optimize for ASF

—Provides independent

manageability bus through SMLink

interface

—Supports SMBus 2.0 Specification

—Host interface allows processor to

communicate via SMBus

—Slave interface allows an internal or

external Microcontroller to access

system resources

—Compatible with most two-wire

components that are also I2C

compatible

High Precision Event Tim ers

—Advanced operating system

interrupt scheduling

Timers Based on 82C54

—System timer, Refresh request,

Speaker tone output

Rea l-Tim e Clock

—256-byte battery-backed CMOS

RAM

—Integrated oscillator components

—Lower Power DC/DC Converter

implementation

System T C O Reduction Circuits

—Timers to generate SMI# and R eset

upon detection of system hang

—Timers to detect improper

processor reset

—Integrated processor frequency

strap logic

—Supports ability to disable external

devices

Enhanced DMA Controller

—Two cascaded 8237 DMA controllers

—Supports LPC DMA

Interrupt Controller

—Supports up to eight PCI interrupt

pins

—Supports PCI 2.3 M essage Signaled

Interrupts

—Two cascaded 82C59 with 15

interrupts

—Integrated I/O APIC capability with

24 interrupts

—Supports Processor System Bus

interrupt delivery

1.05 V operation with 1.5 V and 3.3 V

I/O

—5 V tolerant buffers on IDE (Mobile

only), PCI, USB, and selected

Legacy signals

1.05 V Core Voltage

NEW: Five Integrated Voltage

Regulators for different power rails

Firmware Hub I/F supports BIOS

Memory size up to 8 MB

Serial Peripheral Interface (SPI)

—NEW: supports up to two SPI

devices

—NEW: supports 20 MHz and 33 MHz

SPI devices

Low Pin Count (LPC) I/F

—Supports two Master/DMA devices.

—Support for Security Device

(Trusted Platform Module)

connected to LPC.

GPIO

—TTL, Open-Drain, Inversion

Package

—31x31 mm 652 mBGA (Desktop

Only)

—31x31 mm 676 mBGA (Mobile

Only)

Intel® ICH8 Family Datasheet 43

§ §§

Desktop Configuration

Mobile Configuration

SPI BIOS

SPI Flash

Intel® Gigabit

Ethernet Phy

Intel®

ICH8

USB 2.0

(Supports 10 USB ports

Dual EHCI Controller)

System Management

(TCO)

GPIO

SMBus 2.0/I2C

Power Management

PCI Bus

...

Clock Generators

Intel® High Definition

Audio Codec(s)

Firmware Hub

Other ASICs

(Optional)

LPC I/F

Super I/O

SATA (6 ports)

PCI Express* x1

DMI

(To (G)MCH)

TPM

(Optional)

LCI

GLCI

Intel®

ICH8M

USB 2.0

(Supports 10 US B ports

Dual EHCI Controllers)

System M anagem ent

(TCO)

IDE

GPIO

SMBus 2.0/I2C

Po wer M anagem ent

PCI Bus

Clo ck Ge n e ra tors

Cardbus

C o n troller (&

attached slots)

DMI

(T o (G )MC H)

Intel® GbE Phy

Inte l® H ig h D e finition

Audio Codec(s)

Flash BIO S

Other ASICs

(Optional)

L PC I/F

Super I/O

SATA (3 ports)

Docking

Bridge

PC I E xpress x1

TPM

(Optional)

GLCI

LCI

SPI Flash

44 Intel® ICH8 Family Datasheet

Intel® ICH8 Family Datasheet 45

Introduction

1 Introduction

This document is intended for Original Equipment Manufacturers and BIOS vendors

creating Intel® I/O Controller Hub 8 (ICH8) Family based products. This document is

the datasheet for the following:

•Intel

® 82801HB ICH8 (ICH8)

•Intel

® 82801HR ICH8 RAID (ICH8R)

•Intel

® 82801HDH ICH8 Digital Home (ICH8DH)

•Intel

® 82801HDO ICH8 Digital Office (ICH8DO)

•Intel

® 82801HBM ICH8 Mobile (ICH8M)

•Intel

® 82801HEM ICH8 Mobile Enhanced (ICH8M-E)

Section 1.2 provides high-level feature differ ences for the ICH8 Family components.

Note: Throughout this datasheet, I CH8 is used as a general ICH8 term and refers to the

82801HB ICH8 and 82801HR ICH8R 82801HDH ICH8DH, 82801HDO ICH8DO,

82801HBM ICH8M, and 82801HEM ICH8M-E components, unless specifically noted

otherwise.

Note: Throughout this datasheet, the term “Desktop” refers to an y implementation, be it in a

desktop, server, workstation, etc., unless specifically noted otherwise.

Note: Throughout this datasheet, the term “Desktop Only” refers to information that is for the

82801HB ICH8, 82801HR ICH8R, 828 01HDH ICH8DH, and 82801HDO ICH8D O unless

specifically noted otherwise. The term “Digital Home Only“ refers to information that is

for the 82801HDH ICH8DH, unless specifically noted otherwise. The term “Digital Office

Only“ refers to information that is for the 82801HDO ICH8DO, unless specifically noted

otherwise. The term “Mobile Only” refers to information that is for both the 82801HBM

ICH8M and 82801HEM ICH8M-E, unless noted otherwise.

This datasheet is intended for Original Equipment Manufacturers and BIOS vendors

creating Intel® ICH8 family-based products. This manual assumes a working

knowledge of the vocabulary and principles of PCI Express*, USB, IDE (Mobile Only),

AHCI, SATA, Intel® High Definition Audio (Intel® HD Audio), SMBus, PCI, ACPI and

LPC. Although some details of these features are described within this manual, refer to

the individual industry specifications listed in Table 1 for the complete details.

Table 1. Industry Specifications

Specification Location

Intel® I/O Controller Hub 8 (ICH8) Family Specification

Update http://www.intel.com/design/

chipsets/specupdt/313057.htm

PCI Express* Base Specification, Revision 1.1 http://www.pcisig.com/specifications

Low Pin Count Inte rface Specification, Revision 1.1

(LPC) http://developer.intel.com/design/

chipsets/industry/lpc.htm

System Management Bus S p ecification, Version 2.0

(SMBus) http://www.smbus.org/specs/

PCI Local Bus Specification, Revision 2.3 (PCI) http://www.pcisig.com/specificati o ns

PCI Mobile Design Guide, Revision 1.1 http://www.pcisig.com/specifications

PCI Power Management Specification, Revision 1.1 http://www.pcisig.com/specificatio ns

Introduction

46 Intel® ICH8 Family Datasheet

Chapter 1. Introduction

Chapter 1 introduces the ICH8 and provides information on manual organization and

gives a general overview of the ICH8.

Chapter 2. Signal Description

Chapter 2 provides a block diagram of the ICH8 and a detailed description of each

signal. Signals are arranged according to interface and details are provided as to the

drive characteristics (Input/Output, Open Drain, etc.) of all signals.

Chapter 3. Intel® ICH8 Pin States

Chapter 3 provides a complete list of signals, their associated power well, their logic

level in each suspend state, and their logic level before and after reset.

Chapter 4. Intel® ICH8 and System Clock Domains

Chapter 4 provides a list of each clock domain associated with the ICH8 in an ICH8

based system.

Chapter 5. Functional Description

Chapter 5 provides a detailed description of the functions in the ICH8. All PCI buses,

devices and functions in this manual are abbreviated using the following nomenclature;

Bus:Device:Function. This manual abbreviates buses as B0 and B1, devices as D8,

D27, D28, D29, D30 and D31 and functions as F0, F1, F2, F3, F4, F5, F6 and F7. For

example Device 31 Function 0 is abbreviated as D31:F0, Bus 1 Device 8 Function 0 is

abbreviated as B1:D8:F0. Generally, the bus number will not be used, and can be

considered to be Bus 0. Note that the ICH8’s external PCI bus is typically Bus 1, but

may be assigned a different number depending upon system configuration.

Chapter 6. Register and Memory Mappings

Chapter 6 provides an overview of the registers, fixed I/O ra nges, variable I/O ranges

and memory ranges decoded by the ICH8.

Chapter 7. Chipset Configuration Registers

Chapter 7 provides a detailed description of all registers and base functionality that is

related to chipset configuration and not a specific interface (such as LPC, PCI, or PCI

Express). It contains the root complex register block, which describes the behavior of

the upstream internal link.

Universal Ser ial Bus Specificatio n (USB), Revision 2.0 http://www.usb.org/developers/docs

Advanced Configuration and Power Interface, Version

2.0 (ACPI) http://www.acpi.info/spec.htm

Universal Hos t Controller Interface, Revision 1.1 (UHCI) http://developer.intel.com/design/

USB/UHCI11D.htm

Enhanced Host Controller Interface Specification for

Universal Ser ial Bus, Revision 1. 0 ( EHCI) http://developer.intel.com/

technology/usb/ehcispec.htm

Serial ATA Specification, Revision 2.5 http://www.serialata.org/

specifications.asp

Alert Standard Format Specification, Version 1.03 http://www.dmtf.org/standards/asf

IEEE 802.3 Fast Ethernet http://standards.ieee.org/

getieee802/

AT Attachment - 6 with Packet Interfac e (ATA/ATAPI - 6) http://T13.org (T13 1410D)

IA-PC HP ET (High Precisio n Event Time rs) Specifi cation,

Revision 0.98a http://www.intel.com/

hardwaredesign/hpetspec.htm

Table 1. Industry Specifications

Specification Location

Intel® ICH8 Family Datasheet 47

Introduction

Chapter 8. Integrated LAN Controller Registers

Chapter 8 provides a detailed description of all registers that reside in the ICH8’s

integrated LAN controller. The integrated LAN Controller resides at Device 25, Function

0 (D25:F0).

Chapter 9. LPC Bridge Registers

Chapter 9 provides a detailed description of all registers that reside in the LPC bridge.

This bridge resides at Device 31, Function 0 (D31:F0). This function contains registers

for many different units within the ICH8 including DMA, Timers, Interrupts, Processor

Interface, GPIO, Power Management, System Management and RTC.

Chapter 10. PCI-to-PCI Bridge Registers

Chapter 10 provides a detailed description of all registers that reside in the PCI-to-PCI

bridge. This bridge resides at Device 30, Function 0 (D30:F0).

Chapter 11. IDE Controller Registers (Mobile Only)

Chapter 11 provides a detailed description of all registers that reside in the IDE

controller. This controller resides at Device 31, Function 1 (D31:F1).

Chapter 11. SATA Controller Registers

Chapter 12 provides a detailed description of all registers that reside in the SATA

controller #1. This controller resides at Device 31, Function 2 (D31:F2).

Chapter 12. SATA Controller Registers

Chapter 13 provides a detailed description of all registers that reside in the SATA

controller #2. This controller resides at Device 31, Function 5 (D31:F5).

Chapter 13. UHCI Controller Registers

Chapter 14 provides a detailed description of all registers that reside in the five UHCI

host controllers. These controllers reside at Device 29, Functions 0, 1, 2, and 3

(D29:F0/F1/F2/F3) and Device 26, Function 1 (D26:F1)

Chapter 14. EHCI Controller Registers

Chapter 15 provides a detailed description of all registers that reside in the EHCI host

controllers. This controller resides at Device 29, Function 7 (D29:F7) and Device 26,

Function 7 (D26:F7)

Chapter 15. SMBus Controller Registers

Chapter 16 provides a detailed description of all registers that reside in the SMBus

controller. This controller resides at Device 31, Function 3 (D31:F3).

Chapter 16. Intel® High Definition Audio Controller Registers

Chapter 17 provides a detailed description of all registers that reside in the Intel High

Definition Audio controller. This controller resides at Device 27, Function 0 (D27:F0).

Chapter 17. PCI Express* Port Controller Registers

Chapter 18 provides a detailed description of all registers that reside in the PCI Express

controller. This controller resides at Device 28, Functions 0 to 5(D30:F0-F5).

Chapter 18. High Precision Event Timers Registers

Chapter 19 provides a detailed description of all registers that reside in the multimedia

timer memory mapped register space.

Chapter 19. Serial Peripheral Interface Registers

Chapter 20 provides a detailed description of all registers that reside in the SPI

memory mapped register space.

Chapter 20. Thermal Sensors

Chapter 21 provides a detailed description of all registers that reside in the thermal

sensors PCI configuration space. The registers reside at Device 31, Function 6

(D31:F6).

Introduction

48 Intel® ICH8 Family Datasheet

Chapter 21. Ballout Definition

Chapter 22 provides a table of each signal and its ball assignment in the 652-mBGA

package.

Chapter 22. Electrical Characteristics

Chapter 23 provides all AC and DC characteristics including detailed timing diagrams.

Chapter 24. Package Information

Chapter 24 provides drawings of the physical dimensions and characteristics of the

652-mBGA package.

Appendix A. Index

This volume ends with indexes of registers and register bits.

1.1 Overview

The ICH8 provides extensive I/O support. Functions and capabilities include:

•PCI Express* Base Specification, Revision 1.1 support

•PCI Local Bus Specification, Revision 2.3 support for 33 MHz PCI operations

(supports up to four Req/Gnt pairs).

• ACPI Power Management Logic Support

• Enhanced DMA controller, interrupt controller, and timer functions

• Integrated Serial ATA host controllers with independent DMA operation on up to six

ports (Desktop only) or three ports (Mobile only) and AHCI support.

• Integrated IDE controller supports Ultra ATA100/66/33 (Mobile only)

• USB host interface with support for up to ten USB ports; five UHCI host controllers;

two EHCI high-speed USB 2.0 Host controllers

• Integrated 10/100/1000 GbE MAC with System Defense

•System Management Bus (SMBus) Specification, Version 2.0 with additional

support for I2C devices)

•Supports Intel High Definition Audio

•Supports Intel

® Matrix Stor age Technology (ICH8, ICH8DH, ICH8DO, and ICH8M-E

only)

•Supports Intel

® Active Management Technology (ICH8DO and ICH8M-E only)

• Low Pin Count (LPC) interface

• Firmware Hub (FWH) interface support

• Serial Peripheral Interface (SPI) support

•Intel

® Quiet System Technology (Desktop only)

The Intel ICH8 incorporates a variety of PCI devices and functions, as shown in Table 2.

They are divided into seven logical devices. The first device is the DMI-To-PCI bridge

(Device 30). The second device (Device 31) contains most of the standard PCI

functions that have existed in legacy PCI-to- ISA bridges (South Bridges). The third and

fourth devices (Device 29 and Device 26) are the USB host controller devices. The fifth

device (Device 28) is PCI Express device. The sixth device (Device 27) is the Intel HD

Audio controller device, and the seventh device (Device 25) is the GbE controller

device.

Intel® ICH8 Family Datasheet 49

Introduction

NOTES:

1. The PCI-to-LPC bridge contains registers that control LPC, Po wer Management, System

Management, GPIO, Processor Interface, RTC, Interrupts, Timers, and DMA.

The following sub-sections provide an overview of ICH8 capabilities.

Direct Media Interface (DMI)

Direct Media Interface (DMI) is the chip-to-chip connection between the Memory

Controller Hub / Graphics Memory Controller Hub ((G)MCH) and I/O Controller Hub 8

(ICH8). This high-speed interface integrates advanced priority-based servicing allowing

for concurrent traffic and true isochronous transfer capabilities. Base functionality is

completely software-transparent, permitting current and legacy software to operate

normally.

PCI Express* Interface

The ICH8 provides up to 6 PCI Express Root Ports, supporting the PCI Express Base

Specification, Revision 1.1. Each Root Port supports 2.5 Gb/s bandwidth in each

direction (5 Gb/s concurrent). PCI Express Root Ports 1–4 can be statically configured

as four x1 P orts or ganged together to form one x4 port. Ports 5 and 6 can only be used

as two x1 ports. On Mobile platforms, PCI Express Ports 1–4 can also be configured as

one x2 port (using ports 1 and 2) with ports 3 and 4 configured as x1 ports.

Table 2. PCI Devices and Functions

Bus:Device:Function Function Description

Bus 0:Device 30:Function 0 PCI-to-PCI Bridge

Bus 0:Device 31:Function 0 LPC Controller1

Bus 0:Device 31:Function 1 IDE Controller (Mobile only)

Bus 0:Device 31:Function 2 SATA Controller 1

Bus 0:Device 31:Function 5 SATA Controller 2

Bus 0:Device 31:Function 6 Thermal Subsystem

Bus 0:Device 31:Function 3 SMBus Controller

Bus 0:Device 29:Function 0 USB FS/LS UHCI Controller 1

Bus 0:Device 29:Function 1 USB FS/LS UHCI Controller 2

Bus 0:Device 29:Function 2 USB FS/LS UHCI Controller 3

Bus 0:Device 29:Function 7 USB HS EHCI Controller 1

Bus 0:Device 26:Function 0 USB FS/LS UHCI Controller 4

Bus 0:Device 26:Function 1 USB FS/LS UHCI Controller 5

Bus 0:Device 26:Fucntion 7 USB HS EHCI Controller 2

Bus 0:Device 28:Function 0 PCI Express* Port 1

Bus 0:Device 28:Function 1 PCI Express Port 2

Bus 0:Device 28:Function 2 PCI Express Port 3

Bus 0:Device 28:Function 3 PCI Express Port 4

Bus 0:Device 28:Function 4 PCI Express Port 5

Bus 0:Device 28:Function 5 PCI Express Port 6

Bus 0:Device 27:Function 0 Intel® High Definition Audio Controller

Bus 0:Device 25:Function 0 GbE Controller

Introduction

50 Intel® ICH8 Family Datasheet

Note: The integrated GbE controllers data lines for 1000 Mb/s speed are multiplexed with PCI

Express* Root P ort 6 and, therefore, unavailable if a Gigabit Ethernet PHY is connected.

The use of a 10/100 Mb/s PHY does not consume PCI Express Root Port 6 and,

therefore, the port is available to be used as a x1 port.

Serial ATA (SATA) Controller

The ICH8 has integrated SATA host controllers that supports independent DMA

operation on up to six ports (desktop only) or three ports (mobile only) and supports

data transfer rates of up to 3.0 Gb/s (300 MB/s). The SATA controller contains two

modes of operation – a legacy mode using I/O space, and an AHCI mode using memory

space. SATA and PATA (Mobile only) can also be used in a combined function mode

(where the SATA function is used with PATA). In this combined function mode, AHCI

mode is not used. Software that uses legacy mode will not have AHCI capabilities.

The ICH8 supports the Serial ATA Specification, Revision 2.5. The ICH8 also supports

several optional sections of the Serial ATA II: Extensions to Serial ATA 1.0

Specification, Revision 1.0 (AHCI support is required for some elements).

Note: SATA Ports 2 and 3 are not on the ICH8 Base product. See Section 1.2 for details on

product feature availability.

AHCI

The ICH8 provides hardware support for Advanced Host Controller Interface (AHCI), a

new programming interface for SATA host controllers. Platforms supporting AHCI may

take advantage of performance features such as no master/slave designation for S ATA

devices—each device is treated as a master—and hardware-assisted native command

queuing. AHCI also provides usability enhancements such as Hot-Plug. AHCI requires

appropriate software support (e.g., an AHCI driver) and for some features, hardware

support in the SATA device or additional platform hardware.

Intel Matrix Storage Technology (Intel® ICH8R, ICH8DH, ICH8DO, and

ICH8M-E Only)

The ICH8 provides support for Intel Matrix Storage Technology, providing both AHCI

(see above for details on AHCI) and integr ated RAID functionality. The industry-leading

RAID capability provides high-performance RAID 0, 1, 5, and 10 functionality on up to

6 SATA ports of ICH8. Matrix RAID support is provided to allow multiple RAID levels to

be combined on a single set of hard drives, such as RAID 0 and RAID 1 on two disks.

Other RAID features include hot spare support, SMART alerting, and RAID 0 auto

replace. Software components include an Option ROM for pre-boot configuration and

boot functionality, a Microsoft Windows compatible driver, and a user interface for

configuration and management of the RAID capability of ICH8. Note that ICH8M-E

supports only RAID 0 and RAID 1.

PCI Interface

The ICH8 PCI interface provides a 33 MHz, Revision 2.3 implementation. The ICH8

integrates a PCI arbiter that supports up to four external PCI bus masters in addition to

the internal ICH8 requests. This allows for combinations of up to four PCI down devices

and PCI slots.

Intel® ICH8 Family Datasheet 51

Introduction

IDE Interface (Bus Master Capability and Synchronous DMA Mode) (Mobile

Only)

The fast IDE interface supports up to two IDE devices providing an interface for IDE

hard disks and ATAPI devices. Each IDE device can have independent timings. The IDE

interface supports PIO IDE transfers up to 16 MB/sec and Ultra ATA transfers up

100 MB/sec. It does not consume any legacy DMA resources. The IDE interface

integrates 16x32-bit buffers for optimal transfers.

The ICH8’s IDE system contains a single, independent IDE signal channel that can be

electrically isolated. There are integrated series resistors on the data and control lines

(see Section 5.17 for details). See Section 1.2 for details on component feature

availability.

Low Pin Count (LPC) Interface

The ICH8 implements an LPC Interface as described in the LPC 1.1 Specification. The

Low Pin Count (LPC) bridge function of the ICH8 resides in PCI Device 31:Function 0. In

addition to the LPC bridge interface function, D31:F0 contains other functional units

including DMA, interrupt controllers, timers, power management, system management,

GPIO, and RTC.

Serial Peripheral Interface (SPI)

The ICH8 implements an SPI Interface as an alternative interface for the BIOS flash

device. An SPI flash device can be used as a replacement for the FWH, and is required

to support Intel Active Management Technology (ICH8DO and ICH8M-E only) and the

integrated Fan Speed Control (Intel® Quiet System Technology) (Desktop only). The

ICH8 supports up to two SPI flash devices with speeds up to 33 MHz using two chip

select pins.

Compatibility Modules (DMA Controller, Timer/Counters, Interrupt

Controller)

The DMA controller incorporates the logic of two 82C37 DMA controllers, with seven

independently programmable channels. Channels 0–3 are hardwired to 8-bit, count-by -

byte transfers, and channels 5–7 are hardwired to 16-bit, count-by -word transfers. Any

two of the seven DMA channels can be programmed to support fast Type-F transfers.

The ICH8 supports LPC DMA, which is similar to ISA DMA, through the ICH8’s DMA

controller. LPC DMA is handled through the use of the LDRQ# lines from peripherals

and special encoding on LAD[3:0] from the host. Single, Demand, Verify, and

Increment m odes are supported on the LPC in terface. Channels 0–3 are 8-bit channels.

Channels 5–7 are 16-bit channels. Channel 4 is reserved as a generic bus master

request.

The timer/counter block contains three counters that are equivalent in function to those

found in one 82C54 programmable interval timer. These three counters are combined

to provide the system timer function, and speaker tone. The 14.31818 MHz oscillator

input provides the clock source for these three counters.

The ICH8 provides an ISA-Compatible Programmable Interrupt Controller (PIC) that

incorporates the functionality of two, 82C59 interrupt controllers. The two interrupt

controllers are cascaded so that 14 external and two internal interrupts are possible. In

addition, the ICH8 supports a serial interrupt scheme.

All of the registers in these modules can be read and restored. This is required to save

and restore system state after power has been removed and restored to the platform.

Introduction

52 Intel® ICH8 Family Datasheet

Advanced Programmable Interrupt Controller (APIC)

In addition to the standard ISA compatible Programmable Interrupt controller (PIC)

described in the previous section, the ICH8 incorporates the Advanced Programmable

Interrupt Controller (APIC).

Universal Serial Bus (USB) Controllers

The ICH8 contains up to two Enhanced Host Controller Interface (EHCI) host controllers

that support USB high-speed signaling. High-speed USB 2.0 allows data transfers up to

480 Mb/s which is 40 times faster than full-speed USB. The ICH8 also contains up to

five Universal Host Controller Interface (UHCI) controllers that support USB full-speed

and low-speed signaling.

The ICH8 supports up to ten USB 2.0 ports. All ten ports are high-speed, full-speed,

and low-speed capable. ICH8’s port-routing logic determines whether a USB port is

controlled by one of the UHCI or EHCI controllers. See Section 5.18 and Section 5.19

for details.

Gigabit Ethernet Controller

The Gigabit Ethernet Controller provides a system interface via a PCI function. The

controller provides a full memory-mapped or IO mapped interface along with a 64 bit

address master support for systems using more than 4 GB of physical memory and

DMA (Direct Memory Addressing) mechanisms for high performance data transfers. Its

bus master capabilities enable the component to process high-level commands and

perform multiple operations; this lowers processor utilization by off-loading

communication tasks from the processor. Two large configurable transmit and receive

FIFOs (up to 16 KB each) help prevent data underruns and overruns while waiting for

bus accesses. This enables the integrated LAN controller to transmit data with

minimum interframe spacing (IFS).

The LAN controller can operate at multiple speeds (10/100/1000 Mb/s) and in either

full duplex or half duplex mode. In full duplex mode the LAN controller adheres with the

IEEE 802.3x Flow Control Specification. Half duplex performance is enhanced by a

proprietary collision reduction mechanism. See Section 5.3 for details.

RTC

The ICH8 contains a Motorola MC146818A-compatible real-time clock with 256 bytes of

battery-backed RAM. The real-time clock performs two key functions: keeping track of

the time of day and storing system data, even when the system is powered down. The

RTC op erates on a 32.768 KHz crystal and a 3 V battery.

The R TC also supports two lockable memory r anges. By setting bits in the configur ation

space, two 8-byte ranges can be locked to read and write accesses. This prevents

unauthorized reading of passwords or other system security information.

The RTC also supports a date alarm that allows for scheduling a wake up event up to

30 days in advance, rather than just 24 hours in advance.

GPIO

Various general purpose inputs and outputs are provided for custom system design.

The number of inputs and outputs varies depending on ICH8 configuration.

Intel® ICH8 Family Datasheet 53

Introduction

Enhanced Power Management

The ICH8’s power management functions include enhanced clock control and various

low-power (suspend) states (e.g. , Suspend-to-RAM and Suspend-to-Disk). A hardware-

based thermal management circuit permits software-independent entrance to low-

power states. The IC H8 contains full support for the Advanced Configuration and Power

Interface (ACPI) Specification, Revisi on 2.0.

Intel® Quick Resume Technology (QRT) (Intel® ICH8DH Only)

ICH8DH implements Intel Quick Resume Technology (QRT) to give the PC a Consumer

Electronics device-like feel. Intel QRT provides the capability to design a PC with a

single power button that reliably and instantly (user's perception) turns the PC On and

Off. When the system is On and the user presses the power button, the display

instantly goes dark, sound is muted, and there is no response to keyboard/mouse

commands (except for keyboard power button). When the system is Off and the user

presses the power button, picture and sound quickly return, and the keyboard/mouse

return to normal functionality, allowing user input.

Intel® Active Management Technology (Intel® AMT) (Intel® ICH8DO

and ICH8M-E Only)

Intel Active Management Technology is the next generation of client manageability via

the wired network. Intel AMT is a set of adv anced manageability features dev eloped as

a direct result of IT customer feedback gained through Intel market research. With the

new implementation of System Defense in ICH8, the advanced manageability feature

set of Intel AMT is further enhanced.

Manageability

In addition to Intel AMT the ICH8 integrates several functions designed to manage the

system and lower the total cost of ownership (TCO) of the system. These system

management functions are designed to report errors, diagnose the system, and recover

from system lockups without the aid of an external microcontroller.

•TCO Timer. The ICH8’s integrated progr ammable TCO timer is used to detect

system locks. The first expiration of the timer generates an SMI# that the system

can use to recover from a softw are lock. The second expir ation of the timer causes

a system reset to recover from a hardware lock.

•Processor Present Indicator. The ICH8 looks for the processor to fetch the first

instruction after reset. If the processor does not fetch the first instruction, the ICH8

will reboot the system.

•ECC Error Reporting. When detecting an ECC error, the host controller has the

ability to send one of several messages to the ICH8. The host controller can

instruct the ICH8 to generate either an SMI#, NMI, SERR#, or TCO interrupt.

•Function Disable. The ICH8 provides the ability to disable the following integrated

functions: IDE, LAN, USB, LPC, Intel HD Audio, SATA, or SMBus. Once disabled,

these functions no longer decode I/O, memory, or PCI configuration space. Also, no

interrupts or power management events are gener ated from the disabled functions.

•Intruder Detect. The ICH8 provides an input signal (INTRUDER#) that can be

attached to a switch that is activated by the system case being opened. The ICH8

can be programmed to generate an SMI# or TCO interrupt due to an active

INTRUDER# signal.

Note: ASF functionality with the integr ated ICH8 ASF controller requires a correctly

configured system, including an appropriate (G)MCH with ME, ME Firmware,

system BIOS support, and appropriate Platform LAN Connect Device.

Introduction

54 Intel® ICH8 Family Datasheet

System Management Bus (SMBus 2.0)

The ICH8 contains an SMBus Host interface that allows the processor to communicate

with SMBus slaves. This interface is compatible with most I2C devices. Special I2C

commands are implemented.

The ICH8’s SMBus host controller provides a mechanism for the processor to initiate

communications with SMBus peripherals (slaves). Also, the ICH8 supports slave

functionality, including the Host Notify protocol. Hence, t he host con troller supports

eight command protocols of the SMBus interface (see System Management Bus

(SMBus) Specification, Version 2.0): Quick Command, Send Byte, Receiv e Byte, Write

Byte/Word, Read Byte/Word, Process Call, Block Read/Write, and Host Notify.

ICH8’s SMBus also implements hardware-based Packet Error Checking for data

robustness and the Address Resolution Protocol (ARP) to dynamically provide address

to all SMBus devices.

Intel® High Definition Audio Controller

The Intel® High Definition Audio Specification defines a digital interface that can be

used to attach different types of codecs, such as audio and modem codecs. The ICH8

Intel HD Audio controller supports up to 4 codecs. The link can operate at either 3.3 V

or 1.5 V.

With the support of multi-channel audio stream, 32-bit sample depth, and sample rate

up to 192 kHz, the Intel HD Audio controller pro vides audio quality that can deliver CE

levels of audio experience. On the input side, the ICH8 adds support for an array of

microphones.

Intel® Quiet System Technology (Desktop Only)

The ICH8 integrates four fan speed sensors (four TACH signals) and 3 fan speed

controllers (three Pulse Width Modulator (PWM) signals), which enables monitoring and

controlling up to four fans on the system. With the new implementation of the single-

wire Simple Serial Transport (SST) bus and Platform Environmental Control Interface

(PECI), the ICH8 provides an easy way to connect to SST-based thermal sensors and

access the processor thermal data. In addition, coupled with the new sophisticated

Intel® Quiet System Technology algorithms, the ICH8 integrated fan speed control

provides effective thermal and acoustic management for the platform.

Note: Intel® Quiet System Technology functionality requires a correctly configured system,

including an appropriate (G)MCH with ME, ME Firmware, and system BIOS support.

Intel® ICH8 Family Datasheet 55

Introduction

1.2 Intel® ICH8 Family High-Level Component

Differences

NOTES:

1. Table above shows feature differences between ICH8 family components. If a feature is not

listed in the table it is considered a Base feature that is included in all family components.

2. Product feature capability can be read in D31:F0, Offset E4h.

3. SATA Ports 2 and 3 are not available in the Desktop ICH8 Base component.

NOTES:

1. Table above shows feature differences between ICH8 family components. If a feature is not

listed in the table it is considered a Base feature that is included in all family components.

2. Product feature capability can be read in D31:F0:Offset E4h.

§ §

Table 3. Intel® ICH8 Desktop/Server Family

Product Name Short Name SATA Ports (#) Intel® Matrix Storage

Technology

ICH8 Base ICH8 4 No

ICH8 RAID ICH8R 6 Yes

ICH8 Digital

Home ICH8DH 6 Yes

ICH8 Digital

Office ICH8DO 6 Yes

Table 4. Intel® ICH8 Mobile Family

Product Name Short

Name SATA Ports

(#)

Intel® Matrix

Storage Technology

RAID 0/1 Support

Intel® Active

Management

Technology

ICH8M Base ICH8M 3 No No

ICH8M

Enhanced ICH8M-E 3 Yes Yes

Introduction

56 Intel® ICH8 Family Datasheet

Intel® ICH8 Family Datasheet 57

Signal Description

2 Signal Description

This chapter provides a detailed description of each signal. The signals are arranged in

functional groups according to their associated interface.

The “#” symbol at the end of the signal name indicates that the active, or asserted

state occurs when the signal is at a low voltage level. When “#” is not present, the

signal is asserted when at the high voltage level.

The following notations are used to describe the signal type:

IInput Pin

O Output Pin

OD O Open Drain Output Pin.

I/OD Bi-directional Input/Open Drain Output Pin.

I/O Bi-directional Input / Output Pin.

OC Open Collector Output Pin.

Signal Description

58 Intel® ICH8 Family Datasheet

Figure 1. Intel® ICH8 Interface Signals Block Diagram (Desktop)

THRM#

THRMTRIP#

SYS_RESET#

RSMRST#

MCH_SYNC#

SLP_S3#

SLP_S4#

SLP_S5#

SLP_M#

S4_STATE#/GPIO26

PWROK

CLPWROK

PWRBTN#

RI#

WAKE#

SUS_STAT# / LPCPD#

SUSCLK

LAN_RST#

VRMPWRGD

PLTRST#

CK_PWRGD

AD[31:0]

C/BE[3:0]#

DEVSEL#

FRAME#

IRDY#

TRDY#

STOP#

PAR

PERR#

REQ0#

R EQ1# / GPIO 50

R EQ2# / GPIO 52

R EQ3# / GPIO 54

GNT0#

G NT1# / GPIO5 1

G NT2# / GPIO5 3

G NT3# / GPIO5 5

SERR#

PME#

PCICLK

PCIRST#

PLOCK#

PCI

Interface

GLAN_CLK

GLAN_TXp/PET6p; GLAN_TXn/PET6n

GLAN_RXp/PER6p; GLAN_RXn/PER6n

GLAN_COMPO

GLAN_COMPI

GbE

Controller

Power

Mgnt.

Interrupt

Interface

A20M#

CPUSLP#

FERR#

IGNNE#

INIT#

INIT3_3V#

INTR

NMI

SMI#

STPCLK#

RCIN#

A20GATE

CPUPWRGD / GPIO49

Processor

Interface

USB

SERIRQ

PIRQ[D:A]#

P IR Q[H:E ]# / G P IO[5:2]

USB [9:0]P; US B[9:0]N

O C 0 # ; O C[9:8]#

OC1#/GPIO40; OC2#/GPIO41

OC3#/GPIO42; OC4#/GPIO43

OC5#/GPIO29; OC6#/GPIO30

OC7#/GPIO31

USBRBIAS

USBRBIAS#

RTCX1

RTCX2

CLK14

CLK48

SATA_CLKP, SATA_CLKN

DMI_CLKP, DMI_CLKN

RTC

Clocks

Misc.

Signals

INTVRMEN

SPKR

RTCRST#

TP0,TP6

TP[2:1]

TP[3:5]

LAN100_SLP

General

Purpose

I/O

GPIO[43,33,32,25,20,18,16,

15,13,12,8]

Fan Sp eed

Control

PWM[2:0]

TACH0/GPIO17; TACH1/GPIO1

TACH2/GPIO6; TACH3/GPIO7

SST

PECI

INTRUDER#

SMLINK[1:0]

LINKALERT#

CLGPIO0/GPIO24;CLGPIO1/GPIO10

CLGPIO2/GPIO14;WOL_EN/GPIO9

DMI[3:0 ]T XP, DMI[3:0 ]T XN

DMI[3:0 ]RXP , DMI[3:0 ] RXN

DMI_ZCOMP

DMI_IRCOMP

Direct

Media

Interface

LPC

Interface

SMBus

Interface

HDA_RST#

HDA_SYNC

HDA_BIT_CLK

HDA_SDOUT

HDA_SDIN[3:0]

Intel®

High

Definition

Audio

Firmware

Hub

System

Mgnt.

FW H [3:0] / LAD [3:0]

FWH 4 / LFRA ME #

LAD[3:0] / FWH[3:0]

LFRAME # / FW H 4

LDRQ0#

LDRQ 1# / GPIO23

SMBDATA

SMBCLK

SMBALERT# / GPIO11

GLAN_CLK

LAN_RXD[2:0]

LAN_TXD[2:0]

LAN_RSTSYNC

Platform

LAN

Connect

SATA[5:0]TXP, SATA[5:0]TXN

SATA[5:0]RXP, SATA[5:0]RXN

SATARBIAS

SATARBIAS#

SATALED#

SATACLKREQ# / GPIO35

SATA0GP /GPIO21

SATA1GP /GPIO19

SATA2GP /GPIO36

SATA3GP /GPIO37

SATA4GP

SATA5GP

SCLOCK/GPIO22

SLOAD/GPIO38

SDATAOUT0/GPIO39

SDATAOUT1/GPIO48

Serial ATA

Interface

PCI

Express*

Interface

PETp[5:1], PETn[5:1]

PER p[5:1], PERn[5:1]

GLAN _TXp/PET6p; GLAN_TX n/PET6n

GLAN _R X p/PER6p; GL AN _RX n/PE R6n

SPI

SPI_CS[0]#

SPI_CS[1]#

SPI_MISO

SPI_MOSI

SPI_CLK

QR T _ S T A T E [1:0 ] / GPIO[28:27 ]

Intel® Quick

Resume

Technology

CL_CLK ; CL_D A TA

CL_VREF

CL_RST#

C ontroller

Link

Intel® ICH8 Family Datasheet 59

Signal Description

Figure 2. I ntel® ICH8 Interface Signals Block Diagram (Mobile)

THRM#

THRMTRIP#

SYS_RESET#

RSMRST#

MCH_SYNC#

SLP_S3#

SLP_S4#

SLP_S5#

SLP_M#

S4_STATE#/GPIO26

PWROK

CLPWROK

PWRBTN#

RI#

WAKE#

SUS_STAT# / LPCPD#

SUSCLK

LAN_RST#

VRMPWRGD

PLTRST#

CK_PWRGD

BMBUSY#/GPIO0

CLKRUN#

STP_PCI#

STP_CPU#

BATLOW#

DPRSLPVR/GPIO16

DPRSTP#

AD[31:0]

C/BE[3:0]#

DEVSEL#

FRAME#

IRDY#

TRDY#

STOP#

PAR

PERR#

REQ0#

REQ1# / GPIO50

REQ2# / GPIO52

REQ3# / GPIO54

GNT0#

GNT1# / GPIO51

GNT2# / GPIO53

GNT3# / GPIO55

SERR#

PME#

PCICLK

PCIRST#

PLOCK#

PCI

Interface

GLAN_CLK

GLAN _TXp/PET6p; GLAN_TXn /PET6n

GLAN_RXp/PER6p; GLAN_RXn/PER6n

GLAN_COMPO

GLAN_COMPI

GLAN_DOCK#/GPIO13

GbE

Controller

Power

Mgnt.

Inter ru p t

Interface

A20M#

FERR#

IGNNE#

INIT#

INTR

NMI

SMI#

STPCLK#

RCIN#

A20GATE

CPUPWRGD / GPIO49

DPSLP#

Processor

Interface

USB

SERIRQ

PIRQ[D:A]#

PIR Q[H:E ]# / G P IO[5: 2 ]

IDEIRQ

USB[9:0]P; USB[9:0]N

OC0#; O C[9:8 ] #

O C 1#/GP IO4 0 ; OC 2#/GP I O 41

O C 3#/GP IO4 2 ; OC 4#/GP I O 43

O C 5#/GP IO2 9 ; OC 6#/GP I O 30

OC7#/GPIO31

USBRBIAS

USBRBIAS#

RTCX1

RTCX2

CLK14

CLK48

SATA_CLKP, SATA_CLKN

DMI_CLKP, DMI_CLKN

RTC

Clocks

Misc.

Signals

INTVRMEN

SPKR

RTCRST#

TP3, TP7, TP8

LAN100_SLP

General

Purpose

I/O

GPIO[43,37,20,18,17,12,8,7,6,1]

IDE

Interface

INTRUDER#

SMLINK[1:0]

LINKALERT#/CL_RST1#

MEM_LED/GPIO24;ALERT#/GPIO10

NETDETECT/GPIO14;WOL_EN/GPIO9

DMI[3:0]TXP, DMI[3:0 ]TXN

DMI[3:0]RXP, DMI[3:0]RXN

DMI_ZCOMP

DMI_IRCOMP

Direct

Media

Interface

LPC

Interface

SMBus

Interface

HDA_RST#

HDA_SYNC

HDA_BIT_CLK

HDA_SDOUT

HDA_SDIN[3:0]

HDA_DOCK_EN#/GPIO33

HDA_DOC_RST#/GPIO34

Intel®

High

Definition

Audio

Firmw are

Hub

System

Mgnt.

FW H[3:0] / LAD[3:0]

FWH4 / LFRAME#

LAD[3:0] / FWH[3:0]

LFRAM E # / FW H 4

LDRQ0#

LDRQ1# / GPIO23

SMBDATA

SMBCLK

SMBA LERT # / GPIO11

GLAN_CLK

LAN_RXD[2:0]

LAN_TXD[2:0]

LAN_RSTSYNC

Platform

LAN

Connect

SATA[2:0]TXP, SATA[2:0]TXN

SATA[2:0]RXP, SATA[2:0]RXN

SATARBIAS

SATARBIAS#

SATALED#

SATACLKREQ# / GPIO35

SATA0GP /GPIO21

SATA1GP /GPIO19

SATA2GP /GPIO36

SCLOCK/GPIO22

SLOAD/GPIO38

SDATAOUT0/GPIO39

SDATAOUT1/GPIO48

Serial ATA

Interface

PCI

Express*

Interface

PETp[5:1], P ETn[5:1]

PERp [5 :1], PER n[5 :1]

GLAN_TXp/PET6p; GLAN_TXn/PET6n

GLAN _RXp /PER 6p; GLA N_R Xn /PER 6n

SPI

SPI_CS[0]#

SPI_CS[1]#

SPI_MISO

SPI_MOSI

SPI_CLK

QRT_ S TA T E[1 :0 ] / GPIO[2 8:27 ]

Intel®

Quick

Resume

Technology

CL _CLK[1 :0] ; C L_D A TA [ 1 : 0]

CL_VREF[1:0]

CL_RST#

Controller

Link

DCS1#

DCS3#

DA[2:0]

DD[15:0]

DDREQ

DDACK#

DIOR# (DWSTB / RDMARDY#)

DIOW# (DSTOP)

IORDY (DRSTB / WDMARDY#)

Signal Description

60 Intel® ICH8 Family Datasheet

2.1 Direct Media Interface (DMI) to Host Controller

2.2 PCI Express*

Table 5. Direct Media Interface Signals

Name Type Description

DMI0TXP, DMI0TXN ODirect Media Interface Differential Transmit Pair 0

DMI0RXP, DMI0RXN IDirect Media Interface Differential Receive Pair 0

DMI1TXP, DMI1TXN ODirect Media Interface Differential Transmit Pair 1

DMI1RXP, DMI1RXN IDirect Media Interface Differential Receive Pair 1

DMI2TXP, DMI2TXN ODirect Media Interface Differential Transmit Pair 2

DMI2RXP, DMI2RXN IDirect Media Interface Differential Receive Pair 2

DMI3TXP, DMI3TXN ODirect Media Interface Differential Transmit Pair 3

DMI3RXP, DMI3RXN IDirect Media Interface Differential Receive Pair 3

DMI_ZCOMP IImpedance Compensation Input: This signal determines

DMI input impedance.

DMI_IRCOMP OImpedance/Current Compensation Output: This signal

determines DMI output impedance and bias current.

Table 6. PCI Express* Signals

Name Type Description

PETp1, PETn1 OPCI Express* Differential Transmit Pair 1

PERp1, PERn1 IPCI Express Differential Receive P a ir 1

PETp2, PETn2 OPCI Express Differential Transmit Pair 2

PERp2, PERn2 IPCI Express Differential Receive P a ir 2

PETp3, PETn3 OPCI Express Differential Transmit Pair 3

PERp3, PERn3 IPCI Express Differential Receive P a ir 3

PETp4, PETn4 OPCI Express Differential Transmit Pair 4

PERp4, PERn4 IPCI Express Differential Receive P a ir 4

PETp5, PETn5 OPCI Express Differential Transmit Pair 5

PERp5, PERn5 IPCI Express Differential Receive P a ir 5

PETp6/GLAN_TXp,

PETn6/GLAN_TXn OPCI Express Differential Transmit Pair 6: The differential

pair functions as th e GbE LAN t ransmit pair when the integrated

GbE controller is enabled.

PERp6/GLAN_RXp,

PERn6/GLAN_RXn IPCI Express Differential Receive Pair 6: The differential pair

functions as the GbE LA N receive pair when the integrated GbE

controller is enabled.

Intel® ICH8 Family Datasheet 61

Signal Description

2.3 LAN Connect Interface

2.4 Gigabit LAN Connect Interface

Table 7. LAN Connect Interface Signals

Name Type Description

GLAN_CLK I

GbE Input Clock: This clock is driv en by LAN Conne ct De vice. The

frequency will vary depending on link speed.

NOTE: The clock is shared between LAN Connect Interface and

Gigabit LAN Connect Interface.

LAN_RXD[2:0] I

Received Data : The Platform LAN Connect component uses these

signals to transfer data and control information to the integrated

LAN control ler. These signals have integrated weak pull-up

resistors.

LAN_TXD[2:0] OTransmit Data: The integrated LAN controller uses these sign als to

transfer data and control information to the Platform LAN Connect

device.

LAN_RSTSYNC OLAN Reset/Sync: The LAN Connect component’s Reset and Sync

signals are multiplexed onto this pin.

Table 8. Gigabit LAN Connect Interface Signals

Name Type Description

GLAN_CLK I

GbE Input Clock: Clock driven by LAN Connect Device. The

frequency will vary depending on link speed.

NOTE: The clock is shared between LAN Connect Interface and

Gigabit LAN Connect Interface.

GLAN_TXp/PET6p;

GLAN_TXn/PET6n OGigabit LAN Differential Transmit Pair: These s ignals can,

instead, be used as PCI Express port 6 differential transmit pair

GLAN_RXp/PER6p;

GLAN_RXn/PER6n IGigabit LAN Differential Receive Pair: These signals can,

instead, be used as PCI Express port 6 differential receive pair.

GLAN_COMPO OImpedance Compensation Output pad: Determines Gigabit

LAN Connect Interface output impedance and bias current.

GLAN_COMPI IImpedance Compensation Input pad: Determines Gigabit

LAN Connect Interface input impedance.

GLAN_DOCK#

(Mobile Only)/

GPIO12 I

GbE Dock/Undock Indication: This signal Indicates if the

platform is in docked or undocked position. The platform should

drive this pin low or high depending on its docked or undocked

state. This signal is configured via soft straps as described in

Section 20.2.5.1.

This signal may instead be used as a GPIO.

Signal Description

62 Intel® ICH8 Family Datasheet

2.5 Firmware Hub Interface

ENERGY_DETECT

(Mobile Only) /

GPIO13 I

Energy Detect (Mo bile Only): This input detect signal indicates

that power to the LAN Connected Device must be restored. This

signal connects to the output of an external link detect circuit and

is required to implement the Intel® Auto Detect Battery Saver

feature for LAN Connect Device Full Power Down savings.

This signal may instead be used as a GPIO.

LAN_RSTSYNC O

LAN Reset/Sync: This is the reset/sync signal from the GbE

LAN interface to the physical device. The LAN Connect

component’s Reset and Sync signals are multiplexed onto this

pin.

NOTE: The signal is shared between LAN Connect Interface and

Gigabit LAN Connect Interface.

Table 9. Firmware Hub Interfac e Signals

Name Type Description

FWH[3:0] /

LAD[3:0] I/O Firmware Hub Signals. These signals are multiplexed with the LPC

address signals.

FWH4 /

LFRAME# OFirmware Hub Signals. This signal is multiplexed with the LPC LFRAME#

signal.

Table 8. Gigabit LAN Connect Interface Signals

Name Type Description

Intel® ICH8 Family Datasheet 63

Signal Description

2.6 PCI Interface

Table 10. PCI Interface Signals (Sheet 1 of 3)

Name Type Description

AD[31:0] I/O

PCI Address/Data: AD[31: 0] is a multiplexed address and data

bus. During the first clock of a transaction, AD[31:0] contain a

physical address (32 bits). During subsequent clocks, AD[31:0]

contain data. The Intel® ICH8 will drive all 0s on AD[31:0] during

the address phase of all PCI Special Cycles.

C/BE[3:0]# I/O

Bus Command and Byte Enables: The command and byte enable

signals are multiplexed on the same PCI pins. During the address

phase of a transaction,

C/BE[3:0]# define the bus command. During the data phase C/

BE[3:0]# define the By te Enables.

All command encodi ngs not shown ar e reserved. The ICH8 does not

decode reserved values, and therefore will not respond if a PCI

master generates a cycle usin g one of the reserved values.

DEVSEL# I/O

Device Select: The ICH8 asserts DEVSEL# to claim a PCI

transaction. As an output, the ICH8 asserts DEVSEL# when a PCI

master peripheral attempts an access to an internal ICH8 address

or an address destined DMI (main memory or graphics). As an

input, DEVSEL# indicates the response to an ICH8-initiated

transaction on the PCI bus. D EVSEL# is tri-stated fr om the leading

edge of PLTRST#. DEVSEL# remains tri-stated by the ICH8 until

driven by a target device.

FRAME# I/O

Cycle Frame: The current initiator drives FRAME# to indicate the

beginning and duration of a PCI transaction. While the initiator

asserts FRAME#, data transfers continue. When the initiator

negates FRAME#, the transaction is in the final data phase.

FRAME# is an input to the ICH8 when the ICH8 is the target, and

FRAME# is an output from the ICH8 when the ICH8 is the initiator.

FRAME# remains tri-stated by the ICH8 until driven by an initiator.

C/BE[3:0]# Command Type

0000b Interrupt Ack nowledge

0001b Special Cycle

0010b I/O Read

0011b I/O Write

0110b Memory Read

0111b Memory Write

1010b Configuration Read

1011b Configuration Write

1100b Memory Read Multiple

1110b Memory Read Line

1111b Memory Write and Invalidate

Signal Description

64 Intel® ICH8 Family Datasheet

IRDY# I/O

Initiator Ready: IRDY# indic ates the ICH8's ability, as an initiator,

to complete the current data phase of the transaction. It is used in

conjunction with TRDY#. A data phase is completed on any clock

both IRDY# and TRDY# are sampled asserted. During a write,

IRDY# indicates the ICH8 has valid data present on AD[31:0].

During a read, it indicates the ICH8 is prepared to latch data.

IRDY# is an input to the ICH8 when the ICH8 is the target and an

output from the ICH8 when the ICH8 is an initiator. IRDY# remains

tri-stated by the ICH8 until driven by an initiator.

TRDY# I/O

Target Ready: TRDY# indicates the ICH8's ability as a target to

complete the current data phase of the transaction. TRDY# is used

in conjunction with IRDY#. A data phase is completed when both

TRDY# and IRDY# are sampled asserted. During a read, TRDY#

indicates that the ICH8, as a target, has placed valid data on

AD[31:0]. During a write, TRDY# indicates the ICH8, as a target is

prepared to latch data. TRDY# is an input to the ICH8 when the

ICH8 is the initiator and an output from the ICH8 when the ICH8 is

a target. TRDY# is tri-stated from the leading edge of PLTRS T#.

TRDY# remains tri-stated by the ICH8 until driven by a target.

STOP# I/O

Stop: ST OP# indicates that th e ICH8, as a target, is requesting th e

initiator to stop the current tr ansaction. ST OP# causes the ICH8, as

an initiator, to stop the current transaction. STOP# is an output

when the ICH8 is a target and an input when the ICH8 is an

initiator.

PAR I/O

Calculated/Checked Parity: PAR uses “even” parity calculated on

36 bits, AD[31:0] plus C/BE[3:0]#. “Even” parity means that the

ICH8 counts t h e nu mbe r of on e within the 36 bits pl u s PAR and the

sum is always even. The ICH8 always calculates PAR on 36 bits

regardless of the valid byte enables. The ICH8 generates PAR for

address and data phases and only assures PAR to be valid one PCI

clock after the corresponding address or data phase. The ICH8

drives and tri-states PAR identically to the AD[31:0] lines except

that the ICH8 delays PAR by exactly one PCI clock. PAR is an output

during the address phase (delayed one clock) for all ICH8 initiated

transactions. PAR is an output during the data phase (delayed one

clock) when the ICH8 is the initiator of a PCI write transaction, and

when it is the target of a read transaction. ICH8 checks parity when

it is the target of a PCI write transaction. If a parity error is

detected, the ICH8 will set the appropriate internal status bits, and

has the option to generate an NMI# or SMI#.

PERR# I/O

Parity Error: An external PCI device drives PERR# when it rece ives

data that has a parity error. The ICH8 drives PERR# when it detects

a parity error. The ICH8 can either gener ate an NMI# or S MI# upon

detecting a parity error (either detected internally or reported via

the PERR# signal).

REQ0#

REQ1#/ GPIO50

REQ2#/ GPIO52

REQ3#/GPIO54

IPCI Requests: The I CH8 supports up t o 4 masters on the PCI bus.

REQ[3:1]# pins can instead be used as GPIO.

Table 10. PCI Interface Signals (Sheet 2 of 3)

Name Type Description

Intel® ICH8 Family Datasheet 65

Signal Description

GNT0#

GNT1#/ GPIO51

GNT2#/ GPIO53

GNT3#/GPIO55

PCI Grants: The ICH8 supports up to 4 masters on the PCI bus.

GNT[3:1]# pins can instead be used as GPIO.

Pull-up resistors are not required on these signals. If pull-ups are

used, they should be tied to the Vcc3_3 power rail.

NOTE: GNT[3:0]# are sampled as a functional strap. See

Section 2.26 for details.

PCICLK I

PCI Clock: This is a 33 MHz clock. PCICLK provides timing for all

transactions on the PCI Bus.

NOTE: (Mobile Only) This clock does not stop based on STP_PCI#

signal. PCI Clock only stops based on SLP_S3#.

PCIRST# O

PCI Reset: This is the Secondary PCI B us reset signal. It is a

logical OR of the primary interface PLTRST# signal and the state of

the Secondary Bus Reset bit of th e Bridge Control register

(D30:F0:3Eh, bit 6).

PLOCK# I/O

PCI Lock: This signal indicates an exclusive bus operation and may

require multiple transactions to complete. ICH8 asserts PLOCK#

when it performs non-exclusive transactions on the PCI bus.

PLOCK# is ignored when PCI masters are granted the bus in

desktop configurations.

NOTE: In mobile configuration, devices on the PCI bus ( other than

the ICH8) are not permitted to assert the PLOCK# signal.

SERR# I/OD System Error: SERR# can be pulsed active by any PCI device that

detects a system error condition. Upon sampling SERR# active, the

ICH8 has the ability to generate an NMI, SMI#, or interrupt.

PME# I/OD

PCI Power Management Event: PCI peripherals drive PME# to

wake the system from low-power states S1–S5. PME# assertion can

also be enabled to generate an SCI from the S0 state. In some

cases the ICH8 may drive PME# active due to an internal wake

event. The ICH8 will not drive PME# high, but it will be pulled up to

VccSus3_3 by an internal pull-up resistor.

Table 10. PCI Interface Signals (Sheet 3 of 3)

Name Type Description

Signal Description

66 Intel® ICH8 Family Datasheet

2.7 Serial ATA Interface

Table 11. Serial ATA Interface Signals (Sheet 1 of 3)

Name Type Description

SATA0TXP

SATA0TXN O

Serial ATA Differential Transmit Pairs: These are outbound

high-speed differential signals to Port 0.

In compatible mode, SATA Port 0 is the primary master of SATA

Controller 1.

SATA0RXP

SATA0RXN I

Serial ATA 0 Differential Receive Pair: These are inbound high-

speed differential signals from Port 0.

In compatible mode, SATA Port 0 is the primary master of SATA

Controller 1.

SATA1TXP

SATA1TXN O

Serial ATA 1 Differential Transmit Pair: These are outbound

high-speed differential signals to Port 1.

In compatible mode, SATA Port 1 is the secondary master of SATA

Controller 1.

SATA1RXP

SATA1RXN I

Serial ATA 1 Differential Receive Pair: These are inbound high-

speed differential signals from Port 1.

In compatible mode, SATA Port 1 is the secondary master of SATA

Controller 1

SATA2TXP

SATA2TXN O

Serial ATA 2 Differential Transmit Pair: These are outbound

high-speed differential signals to Port 2.

In compatible mode, SATA Port 2 is the primary slave of SATA

Controller 1.

NOTE: This port is not functional in the Desktop ICH8 Base

component.

SATA2RXP

SATA2RXN I

Serial ATA 2 Differential Receive Pair: These are inbound high-

speed differential signals from Port 2.

In compatible mode, SATA Port 2 is the primary slave of SATA

Controller 1.

NOTE: This port is not functional in the Desktop ICH8 Base

component.

SATA3TXP

SATA3TXN

(Desktop Only) O

Serial ATA 3 Differential Transmit Pair: These are outbound

high-speed differential signals to Port 3

In compatible mode, SATA Port 3 is the secondary slave of SATA

Controller 1.

NOTE: This port is not functional in the Desktop ICH8 Base

component.

SATA3RXP

SATA3RXN

(Desktop Only) I

Serial ATA 3 Differential Receive Pair: These are inbound high-

speed differential signals from Port 3

In compatible mode, SATA Port 3 is the secondary slave of SATA

Controller 1.

NOTE: This port is not functional in the Desktop ICH8 Base

component.

SATA4TXP

SATA4TXN

(Desktop Only) O

Serial ATA 4 Differential Transmit Pair: These are outbound

high-speed differential signals to Port 4.

In compatible mode, SATA Port 4 is the primary master of SATA

Controller 2

Intel® ICH8 Family Datasheet 67

Signal Description

SATA4RXP

SATA4RXN

(Desktop Only) I

Serial ATA 4 Differential Receive Pair: These are inbound high-

speed differential signals from Port 4.

In compatible mode, SATA Port 4 is the primary master of SATA

Controller 2

SATA5TXP

SATA5TXN

(Desktop Only) O

Serial ATA 5 Differential Transmit Pair: These are outbound

high-speed differential signals to Port 5.

In compatible mode, SATA Port 5 is the secondary master of SATA

Controller 2

SATA5RXP

SATA5RXN

(Desktop Only) I

Serial ATA 5 Differential Receive Pair: These are inbound high-

speed differential signals from Port 5.

In compatible mode, SATA Port 5 is the secondary master of SATA

Controller 2

SATARBIAS OSerial ATA Resistor Bias: These are analog connection points for

an external resistor to ground.

SATARBIAS# ISerial ATA Resistor Bias Complement: These are analog

connection points for an external resistor to ground.

SATA0GP /

GPIO21 I

Serial ATA 0 General Purpose: This is an input pin which can be

configured as an interlock switch corresponding to SATA Port 0.

When used as an interlock switch status indication, this signal

should be drive to ‘0’ to indicate that the switch is closed and to ‘1’

to indicate that the switch is open.

If interlock switches are not required, this pin can be configured as

GPIO21.

SATA1GP /

GPIO19 I

Serial ATA 1 General Purpose: Same function as SATA0GP,

except for SATA Port 1.

If interlock switches are not required, this pin can be configured as

GPIO19.

SATA2GP

(ICH8R Only) /

GPIO36 I

Serial ATA 2 General Purpose: Same function as SATA0GP,

except for SATA Port 2.

If interlock switches are not required, this pin can be configured as

GPIO36.

NOTE: This signal can only be used as GPIO36 in the Desktop ICH8

Base component.

SATA3GP

(Desktop Only) /

GPIO37 I

Serial ATA 3 General Purpose: Same function as SATA0GP,

except for SATA Port 3.

If interlock switches are not required, this pin can be configured as

GPIO37.

NOTE: This signal can only be used as GPIO37 in the Desktop ICH8

Base component.

SATA4GP

(Desktop Only) ISerial ATA 4 General Purpose: Same function as SATA0GP,

except for SATA Port 4.

SATA5GP

(Desktop Only) ISerial ATA 5 General Purpose: Same function as SATA0GP,

except for SATA Port 5.

Table 11. Serial ATA Interface Signals (She et 2 of 3)

Name Type Description

Signal Description

68 Intel® ICH8 Family Datasheet

2.8 IDE Interface (Mobile Only)

SATALED# OC

Serial ATA LED: This is an open-collect or output pin driven during

SATA command activity. It is t o be connected to external circuitry

that can provide the current to drive a platform LED. When active,

the LED is on. When tri-stated, the LED is off. An external pull-up

resistor to Vcc3_3 is required.

Note: This is sampled as a functional strap. See Strapping section

for details.

SATACLKREQ#

/GPIO35

(Native)

I/O (GP)

Serial ATA Clock Request: This is an open-drain output pin when

configured as SATACLKREQ#. It is to connect to the system clock

chip. When active, request for SATA Clock running is asserted.

When tri-stated, it tells the clock chip that SATA clock can be

stopped. An external pull-up resistor is required.

SCLOCK/

GPIO22

(Native)/

I/O (GP)

SGPIO Reference Clock: The SAT A c ontroller uses risi ng edges of

this clock to transmit serial data, and the target uses the falling

edge of this clock to latch data.

If SGPIO interface is not used, this signal can be used as a GPIO.

SLOAD/GPIO38 OD

(Native)/

I/O (GP)

SGPIO Load: The controller drives a 1 at the rising edge of

SCLOCK to indicate either the start or end of a bit stream. A 4-bit

vendor specific pattern will be transmitted right after the signal

assertion.

If SGPIO interface is not used, this signal can be used as a GPIO.

SDATAOUT0/

GPIO39

SDATAOUT1/

GPIO48

(Native)/

I/O (GP)

SGPIO Dataout: Driven by the controller to indicate the drive

status in the following sequence: drive 0, 1, 2, n, 0, 1, 2, n, 2...

If SGPIO interface is not used, the signals can be used as GPIO.

Table 12. IDE Interface Signals (Mobile Only)

Name Typ

eDescription

DCS1# O IDE Device Chip Selects for 100 Range: For ATA command register

block. This output signal is connected to the corresponding signal on the

IDE connector.

DCS3# O IDE Device Chip Selec t for 300 Range: For A TA control register block.

This output signal is connected to the corresponding signal on the IDE

connector.

DA[2:0] O

IDE Device Address: These output signals are connected to the

corresponding signals on the ID E connector. They are used to indicate

which byte in either the ATA command block or control block is being

addressed.

DD[15:0] I/O IDE Device Data: These signals directly drive the corresponding signals

on the IDE connector. There is a weak internal pull-down resistor on DD7.

DDREQ I

IDE Device DMA Request: This input signal is directly driven from the

DRQ signal on the IDE connector. It is asserted by the IDE device to

request a data transfer, and used in conjunction with the PCI bus master

IDE function and are not associated with any A T compatible DMA channel.

There is a weak internal pull-down resistor on this signal.

Table 11. Serial ATA Interface Signals (Sheet 3 of 3)

Name Type Description

Intel® ICH8 Family Datasheet 69

Signal Description

2.9 LPC Interface

DDACK# O

IDE Device DMA Acknow le dge : This signal directly drives the DAK#

signal on the IDE connector. DDACK# is asserted by the Intel® ICH8 to

indicate to IDE DMA slave devices that a given data transfer cycle

(assertion of DIOR# or DIOW#) is a DMA data transfer cycle. This signal

is used in conjunction with the PCI bus mast er IDE function and are not

associated with any AT-compatible DMA channel.

DIOR# /

(DWSTB /

RDMARDY#) O

Disk I/O Read (PIO and Non-Ultra DMA): This is the command to the

IDE device that it may driv e data onto the DD lines. Data is latched by the

ICH8 on the deassertion edge of DIOR#. The IDE device is selected either

by the AT A register file chip selects (DCS1# or DCS3#) and the DA lines,

or the IDE DMA acknowledge (DDAK#).

Disk W rite Strobe (Ultr a DMA Writes to Disk): This is the data write strobe

for writes to disk. When writing to disk, ICH8 drives valid data on rising

and falling edges of DWSTB.

Disk DMA Ready (Ultra DMA Reads from Disk): This is the DMA ready for

reads from disk. When reading from disk, ICH8 deasserts RDMARDY# to

pause burst data transfers.

DIOW# /

(DSTOP) O

Disk I/O Write (PIO and Non-Ultra DMA): This is the command to

the IDE device that it may latch data from the DD lines. Data is latched

by the IDE device on the deassertion edge of DIOW#. The IDE device is

selected either by the ATA register file ch ip selects (DCS1# or DC S3#)

and the DA lines, or the IDE DMA acknowledge (DDAK#).

Disk Stop (Ultra DMA): ICH8 asserts this signal to terminate a burst.

IORDY /

(DRSTB /

WDMARDY#) I

I/O Channel Ready (PIO): This signal will keep the strobe active

(DIOR# on reads, DIOW# on writes) longer than the minimum width. It

adds wait-states to PIO transfers.

Disk Read Strobe (Ultra DMA Reads from Disk): When reading from disk,

ICH8 latches data on rising and falling edges of this signal from the disk.

Disk DMA Ready (Ultra DMA Writes to Disk): When writing to disk, this is

de-asserted by the disk to pause burst data transfers.

Table 13. LPC Interface Signals

Name Type Description

LAD[3:0] /

FWH[3:0] I/O LPC Multiplexed Command, Address, Data: For LAD[3:0], internal

pull-ups are provided.

LFRAME# /

FWH4 OLPC Frame: LFRAME# indicates the start of an LPC cycle, or an abort.

LDRQ0#

LDRQ1# /

GPIO23 I

LPC Serial DMA/Master Request Inputs: LDRQ[1:0]# are used to

request DMA or bus master acc ess. The se signals are t ypical ly connecte d

to external Super I/O device. An internal pull-up resistor is provided on

these signals.

LDRQ1# may optionally be used as GPIO.

Table 12. IDE Interface Signals (Mob ile Only)

Name Typ

eDescription

Signal Description

70 Intel® ICH8 Family Datasheet

2.10 Interrupt Interface

Table 14. Interrupt Signals

Name Type Description

SERIRQ I/O Serial Interrupt Request: This pin implements the serial interrupt

protocol.

PIRQ[D:A]# I/OD

PCI Interrupt Requests: In non-APIC mode the PIRQx# signals can

be routed to interrupts 3, 4, 5, 6, 7, 9, 10, 11, 12, 14 or 15 as

described in the Interrupt Steering section. Each PIRQx# line has a

separate Route Control register.

In APIC mode, these signals are connected to the internal I/O APIC in

the following fashion: PIRQA# is connected to IRQ16, PIRQB# to

IRQ17, PIRQC# to IRQ18, and PIRQD# to IRQ19. This frees the legacy

interrupts.

PIRQ[H:E]# /

GPIO[5:2] I/OD

PCI Interrupt Requests: In non-APIC mode the PIRQx# signals can

be routed to interrupts 3, 4, 5, 6, 7, 9, 10, 11, 12, 14 or 15 as

described in the Interrupt Steering section. Each PIRQx# line has a

separate Route Control register.

In APIC mode, these signals are connected to the internal I/O APIC in

the following fashion: PIRQE# is connected to IRQ20, PIRQF# to

IRQ21, PIRQG# to IRQ22, and PIRQH# to IRQ23. This frees the legacy

interrupts. If not needed for interrupts, these signals can be used as

GPIO.

IDEIRQ

(Mobile Only) IIDE Interrupt Request: This interrupt input is connected to the IDE

drive.

Intel® ICH8 Family Datasheet 71

Signal Description

2.11 USB Interface

Table 15. USB Interface Signals

Name Type Description

USBP0P,

USBP0N,

USBP1P,

USBP1N

I/O

Universal Serial Bus Port [1 :0 ] Differential : These differential

pairs are used to transmit Data/Address/Command signals for ports

0 and 1. These ports can be routed to UHCI controller #1 or the

EHCI controller #1.

NOTE: No external resistors are required on these signals. The

Intel® ICH8 integrates 15 kΩ pull-downs and provides an

output driver impedance of 45 Ω which requires no external

series resistor

USBP2P,

USBP2N,

USBP3P,

USBP3N

I/O

Universal Serial Bus Port [3 :2 ] Differential : These differential

pairs are used to t ransmit data/address/command signals for ports

2 and 3. These ports can be routed to UHCI controller #2 or the

EHCI controller #1.

NOTE: No external resistors are required on these signals. The

ICH8 integrates 15 kΩ pull-downs and provides an output

driver impedance of 45 Ω which requires no external series

resistor

USBP4P,

USBP4N,

USBP5P,

USBP5N

I/O

Universal Serial Bus Port [5 :4 ] Differential : These differential

pairs are used to transmit Data/Address/Command signals for ports

4 and 5. These ports can be routed to UHCI controller #3 or the

EHCI controller #1.

NOTE: No external resistors are required on these signals. The

ICH8 integrates 15 kΩ pull-downs and provides an output

driver impedance of 45 Ω which requires no external series

resistor

USBP6P,

USBP6N,

USBP7P,

USBP7N

I/O

Universal Serial Bus Port [7 :6 ] Differential: These differentia l

pairs are used to transmit Data/Address/Command signals for ports

6 and 7. These ports can be routed to UHCI controller #4 or the

EHCI controller #2.

NOTE: No external resistors are required on these signals. The

ICH8 integrates 15 kW pull-downs and provides an output

driver impedance of 45 W which requires no external series

resistor

USBP8P,

USBP8N,

USBP9P,

USBP9N

I/O

Universal Serial Bus Port [9 :8 ] Differential: These differentia l

pairs are used to transmit Data/Address/Command signals for ports

8 and 9. These ports can be routed to UHCI controller #5 or the

EHCI controller #2.

NOTE: No external resistors are required on these signals. The

ICH8 integrates 15 kW pull-downs and provides an output

driver impedance of 45 W which requires no external series

resistor

Signal Description

72 Intel® ICH8 Family Datasheet

2.12 Power Management Interface

OC0#

OC1# /GPIO40

OC2# /GPIO41

OC3# /GPIO42

OC4# /GPIO43

OC5# /GPIO29

OC6# /GPIO30

OC7# /GPIO31

OC[9:8]#

Overcurrent Indicators: These signals set corresponding bits in

the USB controllers to indic ate that an overcurrent condition has

occurred.

OC[7:1]# may optionally be used as GPIOs.

NOTE: OC[9:0]# are not 5 V tolerant.

USBRBIAS OUSB Resistor Bias: Analog connection point for an external

resistor. Used to set transmit currents and internal load resistors.

USBRBIAS# IUSB Resistor Bias Complement: Analog connection point for an

external resistor. Used to set transmit currents and internal load

resistors.

Table 16. Power Management Interface Signals (Sheet 1 of 4)

Name Type Description

PLTRST# O

Platform Reset: The Intel® ICH8 ass erts PLTRST# to reset devices on

the platform (e.g., SIO, FWH, LAN, (G)MCH, TPM, etc.). The ICH8

asserts PLTRST# during power-up and when S/W initiates a hard reset

sequence through the Reset Control register (I/O Register CF9h). The

ICH8 drives PLTRST# inactive a minimum of 1 ms after both PWROK

and VRMPWRGD are driven high. The ICH8 drives PLTRST# active a

minimum of 1 ms when initiated through the Reset Control register (I/

O Register CF9h).

NOTE: PLTRST# is in the VccSus3_3 well.

THRM# IThermal Alarm: Active low signal generated by external hardware to

generate an SMI# or SCI.

THRMTRIP# I

Thermal Trip: When low , thi s signal indicates that a therm al trip from

the processor occurred, and the ICH8 will immediately transition to a

S5 state. The ICH8 will not wait for the processor stop grant cycle since

the processor has overheated.

SLP_S3# OS3 Sl eep Control: SLP_S3# is for power plane control. This signal

shuts off power to all non- critical systems when in S3 (Suspend To

RAM), S4 (Suspend to Disk), or S5 (Soft Off) states.

Table 15. USB Interface Signal s

Name Type Description

Intel® ICH8 Family Datasheet 73

Signal Description

SLP_S4# O

S4 Sleep Control: SLP_S4# is for power plane control. This signal

shuts power to all non-critical systems whe n in the S4 (Suspend to

Disk) or S5 (Soft Off) state.

NOTE: This pin must be used to control the DRAM power in order to

use the ICH8’s DRAM power-cycling feature. Refer to

Chapter 5.13.11.2 for details

NOTE: In a system with Intel AMT support, this signal should be used

to control the DRAM power. In M1 state (where the host

platform is in S3-S5 states and the manageability sub-system

is running) the signal is forced high along with SLP_M# in order

to properly maintain power to the DIMM used for manageability

sub-system.

SLP_S5# OS5 Sleep Control: SLP_S5# is for power plane control. This signal is

used to shut power off to all non-critical systems when in the S5 (Soft

Off) states.

SLP_M# OManageability Sleep State Control: This signal is used to control

power planes to the Intel AMT sub-system. IF no ME firmware is

present, SLP_M# will have the same timings as SLP_S3#.

S4_STATE#/

GPIO26 O

S4 State Indication: This signals asserts low when the host platform

is in S4 or S5 state. In platforms where the manageability engine is

forcing the SLP_S4# high along with SLP_M#, this signal can be used

by other devices on the board to know when the host pl atform is bel ow

the S3 state.

PWROK I

Power OK: When asserted, PWROK is an indication to the ICH8 that

all power rails have been stable for 99 ms and that PCICLK has been

stable for 1 ms. PWROK can be driven asynchronously. When PWROK is

negated, the ICH8 asserts PLTRST#.

NOTE: PWROK must deassert for a minimum of three RTC clock

periods in order for the ICH8 to fully reset the power and

properly generate the PLTRST# output.

CLPWROK I

Controller Link Power OK: When asserted, this signal indicates that

power to the Controller Link subsystem ((G)MCH, ICH8, etc.) is stable

and tells the ICH8 to deassert CL_RST# to the (G)MCH.

NOTES:

1. CLPWROK must not assert before RSMRST# deasserts

2. CLPWROK must not assert after PWROK asserts

PWRBTN# I

Power Button : The Power Button will cause SMI# or SCI to indicate a

system request to go to a sleep state. If the system is already in a

sleep state, this signal will cause a wake event. If PWRB TN# is pres sed

for more than 4 seconds, this will cause an unconditional transition

(power button ov erride) to the S5 s tate. Ov erride wi ll occur e ven if the

system is in the S1-S4 states. This signal has an internal pull-up

resistor and has an internal 16 ms de-bounce on the input.

RI# IRing Indicate: This signal is an input from a modem. It can be

enabled as a wake event, and this is preserved across power failures.

Table 16. Power Management Interface Signals (Sheet 2 of 4)

Name Type Description

Signal Description

74 Intel® ICH8 Family Datasheet

SYS_RESET# I

System Reset: This pin forces an internal reset after being

debounced. The ICH8 will reset immediately if the SMBus is idle;

otherwise, it will wait up to 25 ms ± 2 ms for the SMBus to idle before

forcing a reset on the system.

RSMRST# I

Resume Well Reset: This signal is used for resetting the resume

power plane logic. This signal must be asserted for at least 10 ms after

the suspend power wells are valid. When deasserted, this signal is an

indication that the suspend power wells are stable.

LAN_RST# I

LAN Reset: When asserted, the internal LAN controller is in reset. This

signal must be asserted until the LAN power wells (VccLAN3_3 and

VccLAN1_05) and VccCL3_3 power well are valid. When deasserted,

this signal is an indication that the LAN power wells are stable.

NOTES:

1. LAN_RST# m ust not deassert before RSMRST# deasserts

2. LAN_RST# mus t not deassert after PWROK asserts.

3. If integrated LAN is no t used LAN_RST# can be tied to Vss.

WAKE# IPCI Express* Wake Event: Sideband wake signal on PCI Express

asserted by components requesting wake up.

MCH_SYNC# IMCH SYNC: This input is internally ANDed with the PWROK input. This

signal is connect to the ICH_SYNC# output of (G)M CH.

SUS_STAT# /

LPCPD# O

Suspend Status: This signal is asserted by the ICH8 to indicate that

the system will be entering a low power state soon. Thi s can be

monitored by devices with memory that need to switch from normal

refresh to suspend refresh mode. It can also be used by other

peripherals as an indication that they should isolate their outputs that

may be going to powered-off planes. This signal is called LPCPD# on

the LPC interface.

SUSCLK OSuspend Clock: This clock is an output of the RTC gener ator circuit to

use by other chips for refresh clock.

VRMPWRGD I

VRM Power Goo d : This signal should be connected to be the

processor’ s VRM Power Good signifying the VRM is stable. This signal is

internally ANDed with the PWROK input.

This signal is in the resume well.

CK_PWRGD OClock Generator Power Good: indicates to the clock gener ator when

the main power w ell is valid. This signal is asserted high when both

SLP_S3# and VRMPWRGD are high.

BMBUSY#

(Mobile On ly) /

GPIO0

(Desktop Only)

Bus Master Busy: To support the C3 state. Indication that a bus

master device is busy. When this signal is asserted, the BM_STS bit will

be set. If this signal goes active in a C3 state, it is treated as a break

event.

NOTE: This signal is internally synchronized using the PCICLK and a

two-stage synchronizer. It does not need to meet any particular

setup or hold time.

NOTE: In desktop configurations, this signal is a GPIO.

CLKRUN#

(Mobile Only)/

GPIO32

(Desktop Only)

I/O PCI Clock Run: This signal is used to support PCI CLKRUN protocol. It

connects to per ipherals that need to reque st clock restart or preventi on

of clock stopping.

Table 16. Power Management Interface Signals (Sheet 3 of 4)

Name Type Description

Intel® ICH8 Family Datasheet 75

Signal Description

2.13 Processor Interface

STP_PCI#

(Mobile Only) /

GPIO15

(Desktop Only)

Stop PCI Clock: This signal is an output to the external clock

generator for it to turn off the PCI clock. It is used to support PCI

CLKRUN# protocol. This pin i s also used to communicate the host clock

frequency select for ME operation.

If this functionality is not needed, this signal can be configured as a

GPIO.

STP_CPU#

(Mobile Only) /

GPIO25

(Desktop Only)

Stop CPU Clock: This signal is an output to the external clock

generator for it to turn off the processor clock. It is used to support the

C3 state. This pin is also used to communicate the host clock frequency

select for ME operation.

If this functionality is not needed, this signal can be configured as a

GPIO.

BATLOW#

(Mobile Only) /

TP0

(Desktop Only)

Battery Low: This signal is an input from battery to indicate that

there is insufficient power to boot the system. Assertion will prevent

wake from S3–S5 state. This signal can also be enabled to cause an

SMI# when asserted.

DPRSLPVR

(Mobile Only) /

GPIO16

(Desktop Only)

Deeper Sleep - Voltage Regulator: This signal is used to lower the

voltage of VRM during the C4 state. When the signal is high, the

voltage regulator outputs the lower “Deeper Sleep” voltage. When low

(default), the voltage regulator outputs the higher “Normal” voltage.

DPRSTP#

(Mobile Only) /

TP1

(Desktop Only)

ODeeper Stop: This is a copy of the DPRSLPVR and it is active low.

Table 17. Processor Interface Signals (Sheet 1 of 2)

Name Type Description

A20M# OMask A20: A20M# will go active based on either setting the

appropriate bit in the Port 92h register, or based on the A20GATE

input being active.

CPUSLP#

(Desktop Only) O

CPU Sleep: This signal puts the processor into a state that saves

substantia l power compared to Stop-Grant state. However, during

that time, no sno ops occ u r. The Intel® ICH8 can optionally assert the

CPUSLP# signal when going to the S1 state.

FERR# I

Numeric Coprocessor Error: This signal is tied to the coprocessor

error signal on the processor. FERR# is only used if the ICH8

coprocessor error reporting function is enabled in the OIC.CEN

FERR# is asserted, the ICH8 generates an internal IRQ13 to its

interrupt controller unit. It is also used to gate the IGNN E# signal to

ensure that IGNNE# is not asserted to the processor unless FERR# is

active. FERR# requires an external weak pull-up to ensure a high

level when the coprocessor error function is disabled.

NOTE: FERR# can be used in some states for notification by the

processor of pending interrupt events. This functionality is

independent of the OIC register bit se tt in g.

Table 16. Power Management Interface Signals (Sheet 4 of 4)

Name Type Description

Signal Description

76 Intel® ICH8 Family Datasheet

IGNNE# O

Ignore Numeric Error: This signal is connected to the ignore error

pin on the processor. IGNNE# is only used if the ICH8 coprocesso r

error reporting function is enabled in the OIC.CEN register (Chipset

Configuration Registers:Offset 31FFh: bit 1). If FERR# is active,

indicating a coprocessor error, a write to the Coprocessor Error

IGNNE# remains asserted until FERR# is negated. If FERR# is not

asserted when the Coprocessor Error register is written, the IGNNE#

signal is not asserted.

INIT# OInitialization: INIT# is asserted by the ICH8 for 16 PCI clocks to

reset the processor. ICH8 can be configured to support processor Built

In Self Test (BIST).

INIT3_3V#

(Desktop Only) OInitialization 3.3 V: This is the identical 3.3 V copy of INIT#

intended for Firmware Hub.

INTR OCPU Interrupt: INTR is asserted by the ICH8 to signal the processor

that an interrupt request is pending and needs to be serviced. It is an

asynchronous output and normally driven low.

NMI O

Non-Maskable Interrupt: NMI is used to force a non-Maskable

interrupt to the processor. The ICH8 can generate an NMI when either

SERR# is asserted or IOCHK# goes active via the SERIRQ# stream.

The processor detects an NMI when it detects a rising edge on NMI.

NMI is reset by setting the corresponding NMI source enable/disable

bit in the NMI Status and Control register (I/O Register 61h).

SMI# OSystem Management Interrupt: SMI# is an active low output

synchronous to PCICLK. It is asserted by the ICH8 in response to one

of many enabled hardware or software events.

STPCLK# O

Stop Clock Request: STPCLK# is an active low output synchronous

to PCICLK. It is asserted by the ICH8 in response to one of many

hardware or software events. When the processor samples STPCLK#

asserted, it responds by stopping its internal clock.

RCIN# I

Keyboard Controller Reset CPU: The keyboard controller can

generate INIT# to the processor. This saves the external OR gate with

the ICH8’s other sources of INIT#. When the ICH8 detects the

assertion of this signal, INIT# is generated for

16 PCI clocks.

NOTE: The ICH8 will ignore RCIN# assertion during transitions to the

S1, S3, S4, and S5 states.

A20GATE IA20 Gate: A20GATE is from the keyboard controller. The sign al acts

as an alternative method to force the A20M# signal active. It saves

the external OR gate needed with various other chipsets.

CPUPWRGD /

GPIO49 O

CPU Power Good: This signal should be connected to the processor’ s

PWRGOOD input to indicate whe n the processor power is v alid. This is

an output signal that represents a logical AND of the ICH8’s PWROK

and VRMPWRGD signals.

This signal may optionally be configured as a GPIO.

DPSLP#

(Mobile Only) /

TP2 (Desktop

Only)

Deeper Sleep: DPSLP# is asserted by the ICH8 to the processor.

When the signal is low, the processor enters the deep sleep state by

gating off the processor Core Clock inside the processor. When the

signal is high (default), the processor is not in th e deep sleep state.

Table 17. Processor Interface Signals (Sheet 2 of 2)

Name Type Description

Intel® ICH8 Family Datasheet 77

Signal Description

2.14 SMBus Interface

2.15 System Management Interface

Table 18. SM Bus Interface Signals

Name Type Description

SMBDATA I/OD SMBus Data: External pull-up resistor is required.

SMBCLK I/OD SMBus Clock: External pull-up resistor is required.

SMBALERT# /

GPIO11 ISMBus Alert: This signal is used to wake the system or generate

SMI#. If not used for SMBALERT#, it can be used as a GPIO.

Table 19. System Management Interface Signals (Sheet 1 of 2)

Name Type Description

INTRUDER# IIntruder Detect: This signal can be set to disable system if box

detected open. This signal’s status is readable , so it can be used like

a GPIO if the Intruder Dete ction is not needed.

SMLINK[1:0] I/OD

System Management Link: SMBus link to optional external

system management ASIC or LAN controller. External pull-ups are

required. Note that SMLINK0 corresponds to an SMBus Clock signal,

and SMLINK1 corresponds to an SMBus Data signal.

LINKALERT# /

CL_RST1# I/OD

SMLink Alert: Output of the integrated LAN and input to either the

integrated ASF or an external management controller in order for

the LAN’s SMLINK slave to be serviced.

When used as LINKLERT#, an external pull-up resistor is required.

CLGPIO0

(MEM_LED)/

GPIO24 I/O

Controller Link General Purpose I /O 0: Provides DRAM-powered

LED control. Allows for the blinking of an LED circuit to indicate

memory activity.

This signal can instead be used as GPIO.

SusPwrAck/

ALERT#

(Mobile On ly)/

GPIO10

I/O

SusPwrAck/ALERT# (Mobile Only) / GPIO10: The primary use

of this pin is for SusPwrAck communication from the Management

Engine (ME) to the plat form Embedded Controller (EC). ALERT#

functionality is provided for backup to facilitate SMBus ME-to-EC and

EC-to-ME communication and is not used in the current

implementation.

SusPwrAck signal is an output signal used by the ME in conjunction

with SLP_M# to indicate to the EC that it acknowledges any

Suspend well power down decision by the EC. When the ME asserts

this signal high and SLP_M# is low, this indicates to the EC it is safe

to power off the Suspend well. Likewise, when the ME de-asserts

this signal low and the Suspend well is powered, this indicates to the

EC that the ME requires th e Suspend well to remain powered.

(Active High, Level).

This signal can instead be used as a GPIO. This signal is used as

GPIO10 in desktop systems.

Signal Description

78 Intel® ICH8 Family Datasheet

2.16 Real Time Clock Interface

AC_PRESENT

(Mobile Only)/

GPIO14 I/O

AC_PRESENT (Mobile Only) / GPIO14: AC_Present is an anput

signal from the platform Embedded Controller (EC) to the

Management Engine (ME). The AC_Present signal is used by the EC

to indicate to the ME the current power source of the system. When

the signal is high, this indicates to the ME that the system is

connected to an external AC sources. When the signal is low, this

indicates to the ME that the system is connected to a DC (battery)

source. The ME uses this information in conjunction with the current

system power state to determine what ME power state to run in

(M0, M1, or MOff). (Active High, Level).

This signal can instead be used as a GPIO. This signal is used as

GPIO14 in desktop systems.

WOL_EN /

GPIO9 O

Wake On LAN Power Enable: In an Intel® AMT or integrated ASF

enabled system, this output signal is driven high by the ICH8 to

control the LAN subsystem power (VccLAN3_3, VccCL3_3, LAN PHY

Power, and SPI device) to support Wake on LAN (WOL) when the

Intel® Manageability Engine is powered off. This functionality is

configured and controlled by the Manageability Engine prior to

entering the powered off state.

NOTES:

1. This signal should be OR’d with the SLP_M# signal on the

motherboard to determine when to power the LAN

subsystem.

2. To support WOL out of a G3 state, the WOL_EN pin needs to

be pulled high by an external resistor until the Manageability

Engine is initialized.

If Intel AMT or integrated ASF are disabled on a board that is

configured for WOL_EN support, BIOS must use GPIO9 to control

power to the LAN subsystem when entering S3–S5.

In platforms that do not support Intel AMT or integrated ASF, this

signal is used as GPIO9.

Table 20. Real Time Clock Interface

Name Type Description

RTCX1 Special Crystal Input 1: This signal is connected to the 32.768 kHz crystal. If

no external crystal is used, then RT CX1 can be driv en with the desired

clock rate .

RTCX2 Special Crystal Input 2: This signal is connected to the 32.768 kHz crystal. If

no external crystal i s used, then RTCX2 should be left floating.

Table 19. System Management Interface Signals (Sheet 2 of 2)

Name Type Description

Intel® ICH8 Family Datasheet 79

Signal Description

2.17 Other Clocks

2.18 Miscellaneous Signals

Table 21. Other Clocks

Name Type Description

CLK14 IOscillator Clock: This clock is used for 8254 timers. It runs at

14.31818 MHz. This clock is permitted to stop during S3 (or lower)

states.

CLK48 I48 MHz Clock: This clock is used to run the USB controller. It runs at

48.000 MHz. This clock is permitted to stop during S3 (or lower) states.

SATA_CLKP

SATA_CLKN I100 MHz Differential Clock: These signals are used to run the SATA

controller at 100 MHz. This clock is permitted to stop during S3/S4/S5

states.

DMI_CLKP,

DMI_CLKN I100 MHz Differential Clock: These signals are used to run the Direct

Media Interface. Runs at 100 MHz.

Table 22. Miscellaneous Signals (Sheet 1 of 2)

Name Type Description

INTVRMEN IInternal Voltage Regulator Enable: This signal enables the

internal VccSus1_05, VccSus1_5 and VccCL1_5 regulators. This

signal must be pulled-up to VccRTC.

LAN100_SLP IInternal Voltage Regulator Enable: This signal enables the

internal voltage regulators powering VccLAN1_05 and VccCL1_05.

This signal must be pulled-up to VccRTC.

SPKR O

Speaker: The SPKR signal is the output of counter 2 and is

internally “ANDed” with Port 61h bit 1 to provide Speaker Data

Enable. This signal drives an external speaker driver device, which

in turn drives the system speaker. Upon PLTRST#, its output state

is 0.

NOTE: SPKR is sampled at the rising edge of PWROK as a

functional strap. See Section 2.26.1 for more details. There

is a weak integrated pull-down resistor on SPKR pin.

RTCRST# I

RTC Reset: When asserted, this signal resets register bits in the

RTC well.

NOTES:

1. Unless CMOS is being cleared (only to be done in the G3

power state), the RTCRST# input must always be high

when all other RTC power planes are on.

2. In the case where the RTC battery is dead or missing on

the platform, the RTCRST# pin must rise before the

RSMRST# pin.

TP0

(Desktop Only) /

BATLOW#

(Mobile On ly)

ITest Point 0: This signal must have an external pull-up to

VccSus3_3.

Signal Description

80 Intel® ICH8 Family Datasheet

2.19 Intel® High Definition Audio Link

TP1

(Desktop Only) /

DPRSTP#

(Mobile Only)

OTest Point 1: Route signal to a test point.

TP2

(Desktop Only) /

DPSLP#

(Mobile Only)

OTest Point 2: Route signal to a test point.

TP3 I/O Test Point 3: Route signal to a test point.

TP4

(Desktop Only) /

CL_DATA1

(Mobile Only)

I/O Test Point 4: Route signal to a test point.

TP5

(Desktop Only) /

CL_CLK1

(Mobile Only)

I/O Test Point 5: Route signal to a test point.

TP6

(Desktop Only) /

CL_VREF1

(Mobile Only)

I/O Test Point 6: Route signal to a test point.

TP7

(Mobile Only) I/O Test Point 7: Route signal to a test point.

TP8

(Mobile Only) I/O Test Point 8: Route signal to a test point.

Table 23. Intel® High Definition Audio Link Signals (Sheet 1 of 2)

Name Type Description

HDA_RST# OIntel® High Definition Audio Reset: This signal is a master

hardware reset to external codec(s).

HDA_SYNC O

Intel High Definitio n Audio Sync: This signal is a 48 kHz fixed

rate sample sync to the codec(s). Also used to encode the stream

number.

NOTE: HDA_SYNC is sampled at the rising edge of PWROK as a

functional strap. See Section 2.26.1 for more details. There

is a weak integrated pull-down resistor on the HDA_SYNC

pin.

HDA_BIT_CLK O

Intel High Definition Audio Bit Clock Output: 24.000 MHz

serial data clock generated by the Intel High Definition Au dio

controller (the Intel® ICH8). This signal has a weak internal pull-

down resistor.

Table 22. Miscellaneous Signals (Sheet 2 of 2)

Name Type Description

Intel® ICH8 Family Datasheet 81

Signal Description

NOTES:

1. Some signals have integrated pull-ups or pull-downs. Consult table in Section 3.1 for

details.

2.20 Serial Peripheral Interface (SPI)

HDA_SDOUT O

Intel High Definition Audio Serial Da ta Out: This signal is the

serial TDM data output to the codec(s). This serial output is

double-pumped for a bit rate of 48 Mb/s for Intel High Definition

Audio.

NOTE: HDA_SDOUT is sampled at the rising edge of PWROK as a

functional strap. See Section 2.26.1 for more details. There

is a weak integrated pull-down resistor on the HDA_SDOUT

pin.

HDA_SDIN[3:0] I

Intel High Definition Audio Serial D a ta I n [3:0 ] : These

signals are serial TDM data inputs from the codecs. The serial input

is single-pumped for a bit rate of 24 Mb/s for Intel® High Definition

Audio. These signals have integrated pull-down resistors, which

are always enabled.

HDA_DOCK_EN#

(Mobile Only) /

GPIO33 I/O

High Definition Audio Dock Enable: This signal controls the

external Intel HD Audio docking isolation logic. This is an active

low signal. When deasserted the external docking switch is in

isolate mode. Wh en asserted the external docking switch

electrically connects the Intel HD Audio dock signals to the

corresponding Intel® ICH8 signals.

This signal is shared with GPIO33. This signal defaults to GPIO33

mode after PLTRST# reset and will be in the high state after

PLTRST# reset. BIOS is responsible for configuring GPIO33 to

HDA_DOCK_EN# mode.

HDA_DOCK_RST#

(Mobile Only) /

GPIO34 I/O

High Definition Audio Dock Reset: This signal is a dedicated

HDA_RST# signal for the codec(s) in the docking station. A side

from operating independently from the normal HDA_RST# signal,

it otherwise works similarly to the HDA_RST# signal.

This signal is shared with GPIO34. This signal defaults to GPIO34

mode after PLTRST# reset and will be in the low state after

PLTRST# reset. BIOS is responsible for configuring GPIO34 to

HDA_DOCK_RST# mode.

Table 23. Intel® High Definition Audio Link Signals (Sheet 2 of 2)

Name Type Description

Table 24. Serial Peripheral Interface (SPI) Signals

Name Type Description

SPI_CS0# OSPI Chip Select 0: Used as the SPI bus request signals.

SPI_CS1# I/O SPI Chip Select 1: Used as the SPI bus request signals. This signa l

is also used as Boot BIOS destination selection strap with GNT0#.

SPI_MISO ISPI Master IN Slave OUT: Data input pin for ICH8.

SPI_MOSI OSPI Master OUT Slave IN: Data output pin for ICH8.

SPI_CLK OSPI Clock: SPI clock signal, during idle the bus owner will drive the

clock signal low. 17.86 MHz and 31.25 MHz.

Signal Description

82 Intel® ICH8 Family Datasheet

2.21 Intel® Quick Resume Technology (Intel® ICH8DH

Only)

2.22 Controller Link

Table 25. Intel® Quick Resume Technology Signals

Name Type Description

QRT_STATE[1:0]

/ GPIO[28:27] I/O

Intel Quick Resume Technology State: Intel Quick Resume

Technology status signals that may optionally be used to drive

front chassis indicators. See Section 5.26.3 for details.

When Intel Quick Resume Technology is enabled, the signals will

function as QR T_ST A TE[ 1:0] only. Otherwise, the signals are used

as GPIOs.

Table 26. Controller Link Signals

Name Type Description

CL_CLK0 I/O Controller Link Clock 0: This signal is a bi-directional clock that

connects to the (G)MCH.

CL_DATA0 I/O Controller Link Data 0: This signal is a bi-directional data signal

that connects to the (G)MCH.

CL_VREF0 I Controller Link Reference Voltage 0: This signal ia an external

reference voltage for Controller Link 0.

CL_RST0# O North Controller Link reset that connects to the (G)MCH.

CL_RST1# /

LINKALERT# OD/O Controller Link Reset: South Controller link reset that connects

to a device supporting Intel Active Managment Technology.

When used as CL_RST1#, no external pullup or pulldown should be used.

CL_CLK1

(Mobile Only)/

TP5

(Desktop Only)

I/O Controller Link Clock 1: This signal is a bi-directional clock that

connects to a device supporting Intel® Active Management

Technology

CL_DATA1

(Mobile Only)

TP4

(Desktop Only)

I/O Controller Link Data 1: This is a bi-directional data signal that

connects to a device supporting Intel® Active Management

Technology.

CL_VREF1

(Mobile Only)

TP6

(Desktop Only)

IController Link Reference Voltage: This signal is an external

reference voltage for Controller Link 1.

Intel® ICH8 Family Datasheet 83

Signal Description

2.23 Intel® Quiet System Technology (Desktop Only)

2.24 General Purpose I/O Signals

Table 27. Intel® Quiet System Technology Signals

Name Type Description

PWM[2:0] OD

Fan Pulse Width Modulation Outputs: This is a Pulse Width

Modulated duty cycle output signal that is used Intel Quiet

System Technology.

When controlling a 3-wire fan, this signal controls a power

transistor that, in turn, controls power to the fan. When

controlling a 4-wire fan, this signal is connected to the “Control”

signal on the fan. The polarity of this signal is programmable.

The output default is lo w. These signals are 5 V tolerant.

TACH0/GPIO17

TACH1/GPIO1

TACH2/GPIO6

TACH3/GPIO7

Fan Tachometer Inputs: These are Tachometer pulse input

signals that are used to measure fan speed. The signals are

connected to the “Sense” signal on the fan.

Can instead be used as a GPIO signal.

SST I/O Simple Serial Transport: Single-wire, serial bus. Connect to

SST compliant devices such as SST thermal sensors or voltage

sensors.

PECI I/O Platform Environmental Control Interface: Single-wir e,

serial bus. This signal connects to the corresponding pin of the

processor for accessing proc essor digital thermometer.

Table 28. General Purpose I/O Signals (Sheet 1 of 3)

Name Type Tolerance Power

Well Default Description

GPIO55 I/O 3.3 V Core Native Multiplexed with GNT3#

GPIO54 I/O 5.5 V Core Native Multiplexed with REQ3#

(Note 5)

GPIO53 I/O 3.3 V Core Native Multiplexed with GNT2#

GPIO52 I/O 5.5 V Core Native Multiplexed with REQ2#

(Note 5)

GPIO51 I/O 3.3 V Core Native Multiplexed with GNT1#

GPIO50 I/O 5.5 V Core Native Multiplexed with REQ1#

(Note 5)

GPIO49 I/O V_CPU_IO V_CPU_IO Native Multiplexed with CPUPWRGD

(Note 4)

GPIO48 I/O 3.3 V Core GPI Multiplexed with SDATAOUT1

GPIO[47:44] N/A N/A N/A N/A Not implemented.

GPIO[43:40] I/O 3.3 V Resume Native Multiplexed with OC[4:1]#

(Note 5)

GPIO39 I/O 3.3V Core GPI Multiplexed with SDATAOUT0

GPIO38 I/O 3.3 V Core GPI Multiplexed with SLOAD

Signal Description

84 Intel® ICH8 Family Datasheet

GPIO37 I/O 3.3 V Core GPI Mobile: Unmultiplexed.

Desktop: Multiplexed with

SATA3GP.

GPIO36 I/O 3.3 V Core GPI Multiplexed with SATA2GP.

GPIO35 I/O 3.3 V Core GPO Multiplexed with SATACLKREQ#.

GPIO34 I/O 3.3 V Core GPO Mobile: Multiplexed with

HDA_DOCK_RST#.

Desktop: Unmultiplexed.

GPIO33 I/O 3.3 V Core GPO Mobile: Multiplexed with

HDA_DOCK_EN#.

Desktop: Unmultiplexed.

GPIO32

(Desktop Only) I/O 3.3 V Core GPO

Mobile: this GPIO is not

implemented and is used instead

as CLKRUN#.

Desktop: Unmultiplexed.

GPIO31 I/O 3.3 V Resume Native Multiplexed with OC7 #

(Note 5)

GPIO30 I/O 3.3 V Resume Native Multiplexed with OC6 #

(Note 5)

GPIO29 I/O 3.3 V Resume Native Multiplexed with OC5 #

(Note 5)

GPIO28 I/O 3.3 V Resume GPO Digital Home: Multiplexed with

QRT_STATE1

ICH8 Base: Unmultiplexed.

GPIO27 I/O 3.3 V Resume GPO Digital Home: Multiplexed with

QRT_STATE0

ICH8 Base: Unmultiplexed.

GPIO26 I/O 3.3 V Resume Native Multiplexed with S4_STATE#

GPIO25

(Desktop Only) I/O 3.3 V Resume Native

Mobile: this GPIO is not

implemented and is used instead

as STP_CPU#

Desktop: Default as STP_CPU#

(Note 3)

GPIO24 I/O 3.3 V Resume GPO

Mobile: Multiplexed with

MEM_LED

Desktop: Multiplexed with

CLGPIO0.

Not cleared by CF9h reset event.

GPIO23 I/O 3.3 V Core Native Multiplexed with LDRQ 1#

(Note 5)

GPIO22 I /O 3.3 V Core GPI Multiplexed with SCLOCK

GPIO21 I/O 3.3 V Core GPI Multiplexed with SATA0GP.

GPIO20 I/O 3.3 V Core GPO Unmultiplexed

GPIO19 I/O 3.3 V Core GPI Multiplexed with SATA1GP

GPIO18 I/O 3.3 V Core GPO Unmultiplexed

GPIO17 I/O 3.3 V Core GPI Multiplexed with TACH0

Table 28. General Purpose I/O Signals (Sheet 2 of 3)

Name Type Tolerance Power

Well Default Description

Intel® ICH8 Family Datasheet 85

Signal Description

NOTES:

1. GPI[15:0] can be configured to cause a SMI# or SCI. Note that a GPI can be routed to

either an SMI# or an SCI, but not both.

2. Some GPIOs exist in the VccSus3_3 power plane. Care must be taken to make sure GPIO

signals are not driven high into powered-down planes. Some ICH8 GPIOs may be

connected to pins on devices that exist in the core well. If these GPIOs are outputs, there

is a danger that a loss of core power (PWROK low) or a Power Button Override event will

result in the Intel ICH8 driving a pin to a logic 1 to another device that is powered down.

3. The functionality that is multiplexed with the GPIO may not be used in desktop

configuration.

4. This GPIO is not capable of actively driving high. This GPIO is tristated as an output and an

external pull-up is needed to pull the signal high).

GPIO16 I/O 3.3 V Core

Native

(Mobile) /

GPO

(Desktop)

Mobile: Natively used as

DPRSLPVR.

Desktop: Unmultiplexed.

GPIO15

(Desktop Only) I/O 3.3 V Resume Native

Mobile: GPIO is not implemented

and is used instead as

STP_PCI#.

Desktop: default as STP_PCI#

(Note 3)

GPIO14 I/O 3.3 V Resume GPI Mobile: Multipl exed with

AC_PRESENT

Desktop: Unmultiplexed

GPIO13 I/O 3.3V Resume

Native

(Mobile) /

GPI

(Desktop)

Mobile: Natively used as

ENERGY_DETECT

Desktop: Unmultiplexed

GPIO12 I/O 3.3 V Resume

Native

(Mobile) /

GPI

(Desktop)

Mobile: Natively used as

GLAN_DOCK#

Desktop: Unmultiplexed.

GPIO11 I/O 3.3 V Resume Native Multiplexed with SMBALERT#

(Note 5)

GPIO10 I/O 3.3 V Resume GPI Mobile: Multipl exed with

SusPwrAck/ALERT#

Desktop: Unmultiplexed

GPIO9 I/O 3.3 V Resume GPI Refer to Table 19 for signal

description.

GPIO8 I/O 3.3 V Resume GPI Unmultiplexed

GPIO[7:6] I/O 3.3 V C ore GPI Mobile: Unmultiplexed

Desktop: Multiplexed with

TACH[3:2]

GPIO[5:2] I/OD 5 V Core GPI Multiplexed with PIRQ[H :E]#

GPIO1 I/O 3.3 V Core GPI Multiplexed with TACH1

GPIO0 I/O 3.3 V Core GPI Mobile: Multipl exed with

BM_BUSY#

Desktop: Unmultiplexed

Table 28. General Purpose I/O Signals (Sheet 3 of 3)

Name Type Tolerance Power

Well Default Description

Signal Description

86 Intel® ICH8 Family Datasheet

5. When the multiplexed GPIO is used as GPIO functionality, care should be taken to ensure

the signal is stable in its inactive state of the native functionality, immediately after reset

until it is initialized to GPIO functionality.

2.25 Power and Ground

Table 29. Power and Ground Signals (Sheet 1 of 2)

Name Description

Vcc3_3 3.3 V supply for core well I/O buffers. This power may be shut off in S3, S4, S5

or G3 states.

Vcc1_05 1.05 V supply for core well logic. This power may be shut off in S3, S4, S5 or

G3 states.

Vcc1_5_A 1.5 V supply for Logic and I/O. This power may be shut off in S3, S4, S5 or G3

states.

Vcc1_5_B 1.5 V supply for Logic and I/O. This power may be shut off in S3, S4, S5 or G3

states.

Vcc_DMI Power supply for DMI. 1.25V or 1.5V depending on (G)MCH’s DMI voltage.

V5REF Reference for 5 V tolerance on core well inputs. This power may be shut off in

S3, S4, S5 or G3 states.

VccSus3_3

3.3 V supply for resume well I/O buffers. This power is not expected to be shut

off unless the system is unplugged in desktop configurations or the main

battery is removed or completely drained and AC power is not available in

mobile configurations.

VccSus1_5

1.5V supply for the resume well I/O. This power is not expected to be shut off

unless the system is unplugged in desktop configurations.

This voltage is generated internally (see Section 2.26.1 for strapping option).

and these pins can be left as NC unless decoupli ng is required.

VccSus1_05

1.05 V supply for resume well logic. This power is not expected to be shut off

unless the system is unplugged in desktop configurations or the main battery is

removed or completely drained and AC power is not available in mobile

configurations.

This voltage is generated internally (see Section 2.26.1 for strapping option).

and these pins can be left as NC unless decoupli ng is required.

V5REF_Sus

Reference for 5 V tolerance on resume well inputs. This power is not expected

to be shut off unless the system is unplugged in desktop configurations or the

main battery is remove d or completely dr ained and AC power is not available in

mobile configurations.

VccGLAN1_5 1.5V supply for integrated Gigabit LAN I/O buffers. This power can be turned

off if the integrated Gigabit LAN is not used. If the integrated Gigabit LAN is

used, the power is off in S3, S4, S5.

VccGLAN3_3 3.3V supply for integrated Gigabit LAN logic and I/O. This power can be turned

off if the integrated Gigabit LAN is not used. If the integrated Gigabit LAN is

used, the power is off in S3, S4, S5.

VccCL1_05

1.05V supply for Controller Link. This vo ltage may be generated internal ly (see

Section 2.26.1 for str apping option). This pin must be connected to an external

1.05 V power supply when the integrated VRM is disabled. This pin can be left

as NC if the internal VRM is used unless decoupling is required.

Intel® ICH8 Family Datasheet 87

Signal Description

VccCL1_5

1.5V supply for Controller Link. This plane must be on in S0 and other times

Controller Link is used.

This voltage is generated internally (see Section 2.26.1 for strapping option).

and these pins can be left as NC unless decoupling is required.

VccCL3_3

3.3V supply for Controller Link. This is a separ ate power plane that may or may

not be powered in S3–S5 states. This plane must be on in S0 and other times

Controller Link is used.

NOTE: VccCL3_3 must always be powered when VccLAN3_3 is powered.

VccLAN3_3

3.3 V supply for LAN Connect interface buffers. This is a separate power plane

that may or may not be powered in S3–S5 states.

NOTE: VccLAN3_3 must always be powered when VccCL3_3 or Vcc3_3 is

powered.

VccLAN1_05

1.05 V supply for LAN controller logic. This is a separate power plane that may

or may not be powered in S3–S5 states.

This voltage is generated internally (see Section 2.26.1 for strapping option).

and these pins can be left as NC unless decoupling is required..

VccSusHDA

Suspend supply for Intel High Defini tion Audio. This pin can be either 1.5 or 3.3

V. This power is not expected to be shut off unless the system is unplugged in

desktop configurations or the main b a ttery is removed or completely drained

and AC power is not available in mobile configurations.

VccHDA Core supply for Intel High Definition Audio. This pin can be either 1.5 or 3.3 V.

This power may be shut off in S3, S4, S5 or G3 states.

VccRTC

3.3 V (can drop to 2.0 V min. in G3 state) supply for the RTC well. This power

is not expected to be shut off unless the RTC battery is removed or completely

drained.

Note: Implementations should not attempt to clear CMOS by using a jumper to

pull VccRT C low. Clearing CMOS in an Intel® ICH8-based platform can be done

by using a jumper on RTCRST# or GPI.

VccUSBPLL 1.5 V supply for core well logic. This signal is used for the USB PLL. This power

may be shut off in S3, S4, S5 or G3 states. Must be powered even if USB not

used.

VccDMIPLL 1.5 V supply for core well logic. This signal is used for the DMI PLL. This power

may be shut off in S3, S4, S5 or G3 states.

VccSATAPLL 1.5 V supply for core well logic. This signal is used for the SATA PLL. This power

may be shut off in S3, S4, S5 or G3 states. Must be powered even if SATA is

not used.

VccGLANPLL 1.5V supply for core will logic. This signal is used for the integrated Gigabit LAN

PLL. This power is shut off in S3, S4, S5 and G3 states.

V_CPU_IO Powered by the same supply as the processor I/O voltage. This supply is used

to drive the processor interface signals listed in Table 17.

Vss Grounds.

VSS_NTSC

(Mobile On ly)

Not critical to function; ball s are for improved package Reliability . These signals

are connected to GND on the chipset package, and can be connected to GND or

left as NC on the platform (can be left as test points).

NOTE: There is no functional impact if these signals are grou nded.

Table 29. Power and Ground Signals (Sheet 2 of 2)

Name Description

Signal Description

88 Intel® ICH8 Family Datasheet

2.26 Pin Straps

2.26.1 Functional Straps

The following signals are used for static configuration. They are sampled at the rising

edge of PWROK to select configurations (ex cept as noted), and then revert later to their

normal usage. To invoke the associated mode, the signal should be driv en at least four

PCI clocks prior to the time it is sampled.

Intel® ICH8 has implemented a new feature called Soft Straps. Soft Straps are used to

configure specific functions within the ICH8 and (G)MCH very early in the boot process

before BIOS or software intervention. When Descriptor Mode is enabled, the ICH8 will

read Soft Strap data out of the SPI device prior to the de- assertion of reset to both the

Manageability Engine and the Host system. Refer to Section 5.23.1.1 for information on

Descriptor Mode and Section 20.2.5 for more information on Soft Straps and their

settings

Table 30. Functional Strap Definitions (Sheet 1 of 2)

Signal Usage When

Sampled Comment

HDA_SDOUT XOR Chain Entrance / PCI

Express* Port Config 1,

bit 1 (Port 1–4)

Rising Edge of

PWROK

Allows entrance to XOR Chain testing when TP3

pulled low at rising edge of PWROK.

When TP3 not pulled low at rising edge of

PWROK, sets bit 1 of RPC.PC (Chipset

Configuration Registers:Offset 224h).This signal

has a weak internal pull-down.

HDA_SYNC PCI Express Port Config

1, bit 0 (Port 1–4) Rising Edge of

PWROK

This signal has a weak internal pull-down.

Sets bit 0 of RPC.PC (Chipset Configuration

Registers:Offset 224h)

GNT2# PCI Express Port Config

2, bit 0 (Port 5–6) Rising Edge of

PWROK

This signal has a weak internal pull-up.

Sets bit 2 of RPC.PC2 (Chipset Configuration

Registers:Offset 0224h) when sampled low.

GPIO20 Reserved Rising Edge of

PWROK

This signal has a weak internal pull-down.

NOTE: This signal should not be pulled high

GNT1#/GPIO51 ESI Strap (Server Only) Rising edge of

PWROK

Tying this strap low configures DMI for ESI-

compatible operation. This signal has a weak

internal pu ll-up.

NOTE: ESI compatible mode is for server

platforms only. This signal should not be

pulled low for desktopand mobile.

GNT3# Top-Block Swap Override Rising Edge of

PWROK

The signal has a weak internal pull-up. If the

signal is sampled low, this indicates that the

system is strapped to the “top-block swap” mode

(Intel® ICH8 inverts A16 for all cycles targeting

BIOS space). The status of this strap is readable

via the Top Swap bit (Chipset Configuration

Registers:Offset 3414h:bit 0). Note that

software will not be able to clear the Top-Swap

bit until the system is rebooted without GNT3#

being pulled down.

Intel® ICH8 Family Datasheet 89

Signal Description

NOTE:

1. See Section 3.1for full details on pull-up/pull-down resistors.

2. When strapped, the SPI_CS1# pin is required to be held at the strapped value for the

minimum of 200 ns with respect to the rising edge of either the CLP WROK pin or the

LAN_RST# pin, whichever rises first. Note that the hold time is also required to meet the

minimum of 101 ms after the RSMRST# pin is deasserted in the case both ICH8 ME well

and AUX well are connected to the Resume Well power.

GNT0#,

SPI_CS1# Boot BIOS Destination

Selection

Rising Edge of

PWROK

(Note 1)

This field determines the destination of accesses

to the BIOS memory range. Signals have weak

internal pull-ups. Also controllable via Boot BIOS

Destination bit (Chipset Configuration

Registers:Offset 3410h:bit 11:10).

(GNT0# is MSB)

01 = SPI

10 = PCI

11 = LPC

NOTE: Booting to PCI is intended for debug/

testing only. Boot BIOS Destination

Select to LPC/PCI by functional strap or

via Boot BIOS Destination Bit will not

affect SPI accesses initiated by ME or

Integrated GbE LAN.

INTVRMEN Integrated VccSus1_05,

VccSus1_5, and

VccCL1_5 VRM Enable Always Enables integrated VccSus1_05, VccSus1_5 and

VccCL1_5 VRMs. Pin must be pulled-up to

VccRTC.

LAN100_SLP Integrated VccLAN1_05

and VccCL1_05 VRM

Enable Always Enables integrated VccLAN1_05 and VccCL1_05

VRMs. Pin must be pulled-up to VccRTC.

SATALED# PCI Express Lane

Reversal (Lanes 1–4) Rising Edge of

PWROK

Signal has weak internal pull-up.

Sets bit 27 of MPC.LR (Device 28: Function 0:

Offset D8)

SPKR No Reboot Rising Edge of

PWROK

The signal has a weak internal pull-down. If the

signal is sampled high, this indicates that the

system is strapped to the “No Reboot” mode

(ICH8 will disable the TCO Timer system reboot

feature). The status of this strap is readable via

the NO REBOOT bit (Chipset Configuration

Registers:Offset 3410h:bit 5).

TP3 XOR Chain Entrance Rising Edge of

PWROK

See Chapter 29 for functionality information.

This signal has a weak internal pull-up.

NOTE: This signal should not be pulled low

unless using XOR Chain testing.

GPIO33 /

HDA_DOCK_EN# Flash Descriptor Security

Override Strap Rising Edge of

PWROK

This signal has a weak internal pull-up. If

sampled low, the Flash Descri ptor Security will

be overridden. If high, the security measures

defined in the Flash Descriptor will be in effect.

NOTE: This should only be used in

manufacturing environments.

Table 30. Functional Strap Definition s (Sheet 2 of 2)

Signal Usage When

Sampled Comment

Signal Description

90 Intel® ICH8 Family Datasheet

2.26.2 External RTC Circuitry

To reduce RTC well power consumption, the ICH8 implements an internal oscillator

circuit that is sensitive to step voltage changes in VccRTC. Figure 3 shows an example

schematic recommended to ensure correct operation of the ICH8 RTC.

NOTE: C1 and C2 depend on crystal load.

§ §

Figure 3. Example External RTC Circuit

32.768 kHz

Xtal

1 µF

(20% toleranc e) C2

15 pF

(5% tolerance)

VCCRTC

RTCX2

RTCX1

Vbatt

1 µF

(20% tolerance)

1 KΩ

VccSus3_3

15 pF

(5% tolerance )

10 MΩ

–

RTCRST#

20 KΩ

Schottky

Diodes

Intel® ICH8 Family Datasheet 91

Intel® ICH8 Pin State s

3 Intel® ICH8 Pin States

3.1 Integrated Pull-Ups and Pull-Downs

NOTES:

1. Simulation data shows that these resistor values can range from 10 kΩ to 40 kΩ.

2. Simulation data shows that these resistor values can range from 9 kΩ to 50 kΩ.

3. Simulation data shows that these resistor values can range from 15 kΩ to 35 kΩ.

4. Simulation data shows that these resistor values can range from 7.5kΩ to 16 kΩ.

5. Simulation data shows that these resistor values can range from 14.25 kΩ to 24.8 kΩ.

6. Simulation data shows that these resistor values can range from 10 kΩ to 30 kΩ.

7. The pull-up or pull-down on this signal is only enabled at boot/reset for strapping function.

8. Simulation data shows that these resistor values can range from 10 kΩ to 20 kΩ. The

internal pull-up is only enabled during PLTRST# assertion.

9. The pull-down on this signal is only enabled when in S3.

10. Simulation data shows that these resistor values can range from 5.7 kΩ to 28.3 kΩ.

11. The integrated resistors are disabled after PLTRST# de-assertion.

Table 31. Integrated Pull- Up and Pull-Down Resistors

Signal Resistor Ty Nominal Val Notes

DD[7] Pull-down 15 kΩ10

DDREQ Pull-down 15 kΩ10

HDA_BIT_CLK Pull-Down 20 kΩ1,9

HDA_RST# None N/A

HDA_SDIN[3:0] Pull-down 20 kΩ2

HDA_SDOUT Pull-down 20 kΩ3

HDA_SYNC Pull-down 20 kΩ2

GNT[3:0] Pull-up 20 kΩ3, 7

GPIO[20] Pull-down 20 kΩ3

GPIO33 Pull-up 20 kΩ3

GPIO 48 Pull-Up 20 kΩ3, 11

GPIO[18, 19, 21, 32, 35, 37] Pull-Down 20 kΩ3, 11

LAD[3:0]# / FHW[3:0]# Pull-up 20 kΩ3

LAN_RXD[2:0] Pull-up 10 kΩ4

LDRQ[0] Pull-up 20 kΩ3

LDRQ[1] / GPIO 23 Pull-up 20 kΩ3

PME# Pull-up 20 kΩ3

PWRBTN# Pull-up 20 kΩ3

SATALED# Pull-up 15 kΩ8

SPI_CS1# Pull-up 20 kΩ3

SPI_MISO Pull-up 20 kΩ3

TACH[3:0] Pull-up 20 kΩ3

SPKR Pull-down 20 kΩ2

TP3 Pull-up 20 kΩ6

USB[9:0] [P,N] Pull-down 15 kΩ5

Intel® ICH8 Pin State s

92 Intel® ICH8 Family Datasheet

3.2 IDE Integrated Series Termination Resistors

(Mobile Only)

Table 32 shows the ICH8M IDE signals that have integrated series termination

resistors.

NOTE: Simulation data i ndicates that the inte grated series termination resistors are a nominal

33 Ω but can range from 21 Ω to 75 Ω.

3.3 Output and I/O Signals Planes and States

Table 33 and Table 34 shows the power plane associated with the output and I/O

signals, as well as the state at various times. Within the table, the following terms are

used:

“High-Z” Tri-state. ICH8 not driving the signal high or low.

“High” ICH8 is driving the signal to a logic 1.

“Low” ICH8 is driving the signal to a logic 0.

“Defined” Driven to a level that is defined by the function or external pull-

up/pull-down resistor (will be high or low).

“Undefined” ICH8 is driving the signal, but the value is indeterminate.

“Driven” Will be high or low, will be allowed to change.

“Running” Clock is toggling or signal is transitioning because function not

stopping.

“Off” The power plane is off; ICH8 is not driving when configured as

an output or sampling when configured as an input.

“Input” ICH8 is sampling and signal state determined by external driver.

Note that the signal levels are the same in S4 and S5, except as noted.

ICH8 suspend well signal states are indeterminate and undefined and may glitch prior

to RSMRST# deassertion. This does not apply to LAN_RST#, SLP_S3#, SLP_S4#,

SLP_S5# and SLP_M#. These signals are determinate and de fined prior to RSMRST#

deassertion.

ICH8 core well signal states are indeterminate and undefined and may glitch prior to

PWROK assertion. This does not apply to FERR# and THRMTRIP#. These signals are

determinate and defined prior to PWROK assertion.

Table 32. IDE Series Termination Resistors

Signal Integrated Series Termination Resistor Value

DD[15:0], DIOW#, DIOR#, DREQ ,

DDACK#, IORDY, DA[2:0], DCS1#,

DCS3#, IDEIRQ approximately 33 Ω (See Note )

Intel® ICH8 Family Datasheet 93

Intel® ICH8 Pin State s

Table 33. Power Plane and States for Output and I/O Signals for Desktop Configurations

(Sheet 1 of 5)

Signal Name Power

Plane During

Reset4Immediately

after Reset4S1 S3 S4/S5

PCI Express*

PETp[6:1],

PETn[6:1] Core High High8Defined Off Off

DMI

DMI[3:0]TXP,

DMI[3:0]TXN Core High High8Defined Off Off

PCI Bus

AD[31:0] Core Low Undefined Defined Off Off

C/BE[3:0]# Core Low Undefined Defined Off Off

DEVSEL# Core High-Z High-Z High-Z Off Off

FRAME# Core High-Z High-Z High-Z Off Off

GNT0#, GNT[3:1]#/

GPIO[55, 53, 51] Core High-Z with

Internal

Pull-up High High Off Off

IRDY#, TRDY# Core High-Z High-Z High-Z Off Off

PAR Core Low Undefined Defined Off Off

PCIRST# Suspend Low High High Low Low

PERR# Core High-Z High-Z High-Z Off Off

PLOCK# Core High-Z High-Z High-Z Off Off

STOP# Core High-Z High-Z High-Z Off Off

LPC Interface

LAD[3:0] /

FWH[3:0] Core High High High Off Off

LFRAME# / FWH[4] Core High High High Off Off

Platform LAN Connect Interface

LAN_RSTSYNC LAN High Low Defined Off Off

LAN_TXD[2:0] LAN Low Low Defined Off Off

Gigabit LAN Connect Interface

GLAN_TXp,

GLAN_TXn GLAN High High Defined Off Off

SATA Interface

SATA[5:0]TXP,

SATA[5:0]TXN Core High-Z High-Z Defined Off Off

SATALED# Core High-Z High-Z Defined Off Off

SATARBIAS Core High-Z High-Z High-Z Off Off

Intel® ICH8 Pin State s

94 Intel® ICH8 Family Datasheet

SATA5GP

SATA4GP

SATA3GP / GPIO37

SATA2GP / GPIO36

SATA1GP / GPIO19

SATA0GP / GPIO21

Core Input Input Driven Off Off

SATACLKREQ# /

GPIO35 Core Low Low Defined Off Off

SCLOCK/GPIO22 Core Input Input Defined Off Off

SLOAD/GPIO38 Core Input Input Defined Off Off

SDATAOUT[1:0]/

GPIO[48,39] Core Input Input Defined Off Off

Interrupts

PIRQ[A:D]#,

PIRQ[H:E]# /

GPIO[5:2] Core High-Z High-Z High-Z Off Off

SERIRQ Core High-Z High-Z High-Z Off Off

Table 33. Power Plane and States for Output and I/O Signals for Desktop Configurations

(Sheet 2 of 5)

Signal Name Power

Plane During

Reset4Immediately

after Reset4S1 S3 S4/S5

Intel® ICH8 Family Datasheet 95

Intel® ICH8 Pin State s

USB Interface

USBP[9:0][P,N] Suspend Low Low Low Low Low

USBRBIAS Suspend High-Z High-Z Defined Defined Defined

Power Management

PLTRST# Suspend Low High High Low Low

SLP_M9Suspend Low High High Driven Driven

SLP_S3# Suspend Low High High Low Low

SLP_S4# Suspend Low High High High Low

SLP_S5# Suspend Low High High High Low7

SUS_STAT# Suspend Low High High Low Low

SUSCLK Suspend Low Running

CK_PWRGD Suspend Low High Low High High

Processor Interface

A20M# CPU

Dependant

A20GATE

Signal

See Note 1 High Off Off

CPUPWRGD /

GPIO49 CPU Defined High High Off Off

CPUSLP# CPU High High Defined Off Off

IGNNE# CPU High See Note 1 High Off Off

INIT# CPU High High High Off Off

INIT3_3V# Core High High High Off Off

INTR CPU See Note 5 See Note 5 Low Off Off

NMI CPU See Note 5 See Note 5 Low Off Off

SMI# CPU High High High Off Off

STPCLK# CPU High High Low Off Off

SMBus Interface

SMBCLK, SMBDATA Suspend High-Z High-Z Defined Defined Defined

System Management Interface

CLGPIO0 Suspend High-Z High-Z Defined Defined Defined

WOL_EN Suspend High-Z High-Z Defined Defined Defined

SMLINK[1:0] Suspend High-Z High-Z Defined Defined Defined

LINKALERT# Suspend High-Z High-Z Defined Defined Defined

Table 33. Power Plane and States for Output and I/O Signals for Desktop Configurations

(Sheet 3 of 5)

Signal Name Power

Plane During

Reset4Immediately

after Reset4S1 S3 S4/S5

Intel® ICH8 Pin State s

96 Intel® ICH8 Family Datasheet

Miscellaneous Signals

SPKR Core High-Z with

Internal

Pull-down Low Defined Off Off

Intel®High Definition Audio Interface

HDA_RST# HDA

Suspend Low Low8Running Low Low

HDA_SDOUT HDA High-Z with

Internal

Pull-down Running Low Off Off

HDA_SYNC HDA High-Z with

Internal

Pull-down Running Low Off Off

HDA_BIT_CLK HDA High-Z with

Internal

Pull-down Low Low Off Off

Unmultiplexed GPIO Signals

GPIO0 Core Input Input Driven Off Off

GPIO10 Suspend High-Z High-Z Defined Defined Defined

GPIO[13, 12, 8] Suspend Input Input Driven Driven Driven

GPIO14 Suspend High-Z High-Z Defined Defined Defined

GPIO15 Suspend High High Defined Defined Defined

GPIO16 Core Low Low Defined Off Off

GPIO18 Core High See Note 2 Defined Off Off

GPIO20 Core High High Defined Off Off

GPIO25 Core High High Defined Off Off

GPIO[33:32] Core High High Defined Off Off

GPIO34 Core Low Low Defined Off Off

SPI Interface

SPI_CS[1:0]# Controller

Link High High High Off Off

SPI_MOSI Controller

Link High High High Off Off

SPI_CLK Controller

Link Low Low Low Off Off

Intel®Quick Resume Technology Interface (Intel®ICH8DH Only)

QRT_STATE[1:0] /

GPIO[28:27] Suspend Low Low Defined Defined Defined

Table 33. Power Plane and States for Output and I/O Signals for Desktop Configurations

(Sheet 4 of 5)

Signal Name Power

Plane During

Reset4Immediately

after Reset4S1 S3 S4/S5

Intel® ICH8 Family Datasheet 97

Intel® ICH8 Pin State s

NOTES:

1. ICH8 drives these signals High after the processor Reset

2. GPIO[18] will toggle at a frequency of approximately 1 Hz when the ICH8 comes out of

reset

3. CPUPWRGD represents a logical AND of the ICH8’s VRMPWRGD and PWROK signals, and

thus will be driven low by ICH8 when either VRMPWR GD or PWROK are inactive. During

boot, or during a hard reset with power cycling, CPUPWRGD will be expected to transition

from low to Hig h-Z.

4. The states of Core and processor signals are evaluated at the times During PLTRST# and

Immediately after PLTRST#. The states of the LAN and GLAN signals are evaluated at the

times During LAN_RST# and Immediately after LA N_RST#. The states of the Controll er

Link signals are taken at the times Duri ng CL _RST# and Immediately after CL_RST#. The

states of the Suspend signals are evaluated at the times During RSMRST# and

Immediately after RSMRST#. The states of the HDA signals are evaluated at the times

During HDA_RST# and Immediately after HDA_RST#.

5. ICH8 drives these signals Low before PWROK rising and Low after the processor Reset.

6. SLP_S5# signals will be high in the S4 state.

7. Low until Intel High Definition Audio Controller Reset bit set (D27:F0:Offset

HDBAR+08h:bit 0), at which time HDA_RST# will be High and HDA_BIT_CLK will be

Running.

8. PETp/n[6:1] high until port is enabled by software.

9. The SLP_M# state will be determined by Intel® AMT policies.

Controller Link

CL_CLK Controller

Link Low Low Low Off Off

CL_DATA0 Controller

Link Low Low Low Off Off

CL_RST# Suspend Low High High High High

Intel®Quiet System Technology (Desktop Only)

PWM[2:0] Core Low Low Defined Off Off

SST Controller

Link Low Low Defined Off Off

PECI CPU Low Low Defined Off Off

Table 33. Power Plane and States for Output and I/O Signals for Desktop Configurations

(Sheet 5 of 5)

Signal Name Power

Plane During

Reset4Immediately

after Reset4S1 S3 S4/S5

Intel® ICH8 Pin State s

98 Intel® ICH8 Family Datasheet

Table 34. Power Plane and States for Output and I/O Signals for Mobile Configurations

(Sheet 1 of 4)

Signal Name Power

Plane During

Reset4Immediately

after Reset4C3/C4 S1 S3 S4/S5

PCI Express*

PETp[6:1], PET n[6:1] Co re High High9Defined Defined Off Off

DMI

DMI[3:0]TXP,

DMI[3:0]TXN Core High High9Defined Defined Off Off

PCI Bus

AD[31:0] Core Low Undefined Defined Defined Off Off

C/BE[3:0]# Core Low Undefined Defined Defined Off Off

CLKRUN# Core Low Low Defined Off Off

DEVSEL# Core High-Z High-Z High-Z High-Z Off Off

FRAME# Core High-Z High-Z High-Z High-Z Off Off

GNT0#, GNT[3:1]#/

GPIO[55, 53, 51] Core High with

Internal Pull-

ups High High High Off Off

IRDY#, TRDY# Core High-Z High-Z High-Z High-Z Off Off

PAR Core Low Undefined Defined Defined Off Off

PCIRST# Suspend Low High High High Low Low

PERR# Core High-Z High-Z High-Z High-Z Off Off

PLOCK# Core High-Z High-Z High-Z High-Z Off Off

STOP# Core High-Z High-Z High-Z High-Z Off Off

LPC Interface

LAD[3:0] / FWH[3:0] Core High High High High Off Off

LFRAME# / FWH[4] Core High High High High Off Off

Platform LAN Connect Interface

LAN_RSTSYNC LAN High Low Defined Defined Off Off

LAN_TXD[2:0] LAN Low Low Defined Defined Off Off

Gigabit LAN Connect Interface

GLAN_TXp,

GLAN_TXn GLAN High High Defined Defined Off Off

IDE Interface

DA[2:0] Core Undefined Undefined Undefined Undefined Off Off

DCS1#, DCS3# Core High High High High Off Off

DD[15:8], DD[6:0] Core High-Z High-Z Defined High-Z Off Off

DD[7] Core Low Low Defined Low Off Off

DDACK# Core High High High High Off Off

DIOR#, DIOW# Core High High High High Off Off

Intel® ICH8 Family Datasheet 99

Intel® ICH8 Pin State s

SATA Interface

SATA[2:0]TXP,

SATA[2:0]TXN Core High-Z High-Z Defined Defined Off Off

SATALED# Core High-Z High-Z Defined Defined Off Off

SATARBIAS Core High-Z High-Z Defined Defined Off Off

SATA2GP / GPIO36

SATA1GP / GPIO19

SATA0GP / GPIO21 Core Input Input Driven Driven Off Off

SATACLKREQ# /

GPIO35 Core Low Low Defined Defined Off Off

Interrupts

PIRQ[A:D]#,

PIRQ[H:E]# /

GPIO[5:2] Core High-Z High-Z Defined High-Z Off Off

SERIRQ Core High-Z High-Z Running High-Z Off Off

USB Interface

USB[9:0][P,N] Suspend Low Low Low Low Low Low

USBRBIAS Suspend High-Z High-Z Defined Defined Defined Defined

Power Management

PLTRST# Suspend Low High High High Low Low

SLP_M# Suspend Low High High High Driven Driven

SLP_S3# Suspend Low High High High Low Low

SLP_S4# Suspend Low High High High High Low

SLP_S5# Suspend Low High High High High Low8

STP_CPU# Core High High Defined High Off Off

STP_PCI# Core High High Defined High Off Off

SUS_STAT# Suspend Low High High High Low Low

DPRSLPVR Core Low Low Low/

High4High Off Off

DPRSTP# Core High High Low/

High4High Off Off

SUSCLK Suspend Low Running

CK_PWRGD Suspend Low High Low Low High High

Processor Interface

A20M# CPU Dependant

on A20GA TE

Signal See Note 1 Defined High Off Off

CPUPWRGD / GPIO 49 CPU See Note 3 High Hi g h High Off Off

IGNNE# CPU High See Note 1 High High Off Off

INIT# CPU High High High High Off Off

Table 34. Power Plane and States for Output and I/O Signals for Mobile Configurations

(Sheet 2 of 4)

Signal Name Power

Plane During

Reset4Immediately

after Reset4C3/C4 S1 S3 S4/S5

Intel® ICH8 Pin State s

100 Intel® ICH8 Family Datasheet

INTR CPU See Note 6 See Note 6 Defined Low Off Off

NMI CPU See Note 6 See Note 6 Defined Low Off Off

SMI# CPU High High Defined High Off Off

STPCLK# CPU High High Low Low Off Off

DPSLP# CPU High High High/Low High Off Off

SMBus Interface

SMBCLK, SMBDATA Suspend High-Z High-Z Defined Defined Defined Defined

System Management Interface

CLGPIO0/GPIO24 Suspend High-Z High-Z Defined Defined Defined Defined

ALERT#/GPIO10 Suspend High-Z High-Z Defined Defined Defined Defined

NETDETECT/GPIO14 Suspend High-Z High-Z Defined Defined Defined Defined

WOL_EN/GPIO9 Suspend High-Z High-Z Defined Defined Defined Defined

SMLINK[1:0] Suspend High-Z High-Z Defined Defined Defined Defined

LINKALERT# Suspend High-Z High-Z Defined Defined Defined Defined

Miscellaneous Signals

SPKR Core High-Z with

Internal Pull-

down Low Defined Defined Off Off

Intel® High Definition Audio Interface

HDA_RST# HDA

Suspend Low Low8High TBD Low Low

HDA_SDOUT HDA High-Z with

Internal Pull-

down Running Running Low Off Off

HDA_SYNC HDA High-Z with

Internal Pull-

down Running Running Low Off Off

HDA_BIT_CLK HDA High-Z with

Internal Pull-

down Low8Running Low Off Off

HDA_DOCK_RST# /

GPIO34 HDA

Suspend Low Low9Defined Defined Off Off

HDA_DOCK_EN# /

GPIO33 HDA High High Defined Defined Off Off

Unmultiplexed GPIO Signals

GPIO[12, 8] Suspend Input Input Driven Driven Driven Driven

GPIO18 Core High See Note 2 Driven Driven Off Off

GPIO20 Core High High Defined Defined Off Off

Table 34. Power Plane and States for Output and I/O Signals for Mobile Configurations

(Sheet 3 of 4)

Signal Name Power

Plane During

Reset4Immediately

after Reset4C3/C4 S1 S3 S4/S5

Intel® ICH8 Family Datasheet 101

Intel® ICH8 Pin State s

NOTES:

1. ICH8 drives these signals High after the CPU Reset

2. GPIO[18] will toggle at a frequency of approximately 1 Hz when the ICH8 comes out of

reset

3. CPUPWRGD represents a logical AND of the ICH8’s VRMPWRGD and PWROK signals, and

thus will be driven low by ICH8 when either VRMPWR GD or PWROK are inactive. During

boot, or during a hard reset with power cycling, CPUPWRGD will be expected to transition

from low to Hig h-Z.

4. The states of Core and processor signals are evaluated at the times During PLTRST# and

Immediately after PLTRST#. The states of the LAN and GLAN signals are evaluated at the

times During LAN_RST# and Immediately after LA N_RST#. The states of the Controll er

Link signals are evaluated at the times During CL_RST# and Immediately after CL_RST#.

The states of the Suspend signals are evaluated at the times During RSMRST# and

Immediately after RSMRST#. The states of the HDA signals are evaluated at the times

During HDA_RST# and Immediately after HDA_RST#.

5. ICH8 drives these signals Low before PWROK rising and Low after the processor Reset.

6. SLP_S5# signals will be high in the S4 state.

7. Low until Intel High Definition Audio Controller Reset bit set (D27:F0:Offset

HDBAR+08h:bit 0), at which time HDA_RST# will be High and HDA_BIT_CLK will be

Running.

8. PETp/n[6:1] high until port is enabled by software.

9. The SLP_M# state wil l be determined by AMT policies

SPI Interface

SPI_CS[1:0]# Controller

Link High High High High Off Off

SPI_MOSI Controller

Link High High High High Off Off

SPI_CLK Controller

Link Low Low Low Low Off Off

Controller Link

CL_CLK 0

CL_DATA 0 Controller

Link Low Low Low Low Off Off

CL_CLK 1

CL_DATA 1 Suspend Low Low Low Low Off Off

CL_RST# Suspend Low High High High High High

Table 34. Power Plane and States for Output and I/O Signals for Mobile Configurations

(Sheet 4 of 4)

Signal Name Power

Plane During

Reset4Immediately

after Reset4C3/C4 S1 S3 S4/S5

Intel® ICH8 Pin State s

102 Intel® ICH8 Family Datasheet

3.4 Power Planes for Input Signals

Table 35 and Table 36 shows the power plane associated with each input signal, as well

as what device drives the signal at various times. Valid states include:

High

Low

Static: Will be high or low, but will not change

Driven: Will be high or low, and is allowed to change

Running: For input clocks

Table 35. Power Plane for Input Signals for Desktop Configurations (Sheet 1 of 3)

Signal Name Power Well Driver During Reset S1 S3 S4/S5

DMI

DMI_CLKP, DMI_CLKN Core Clock Generator Running Off Off

DMI[3:0]RXP,

DMI[3:0]RXN Core (G)MCH Driven Off Off

PCI Express*

PERp[6:1], PERn[6:1] Core PCI Express* Device Driven Of f Off

PCI Bus

REQ0#,

REQ1# / GPIO501, 3

REQ2# / GPIO521, 3

REQ3# / GPIO541, 3

Core External Pull up Driven Off Off

PCICLK Core Clock Generator Running Off Off

PME# Suspend Internal Pull-up Driven Driven Driven

SERR# Core PCI Bus Peripherals High Off Off

LPC Interface

LDRQ0# Core LPC Devices High Off Off

LDRQ1# / GPIO232Core LPC Devices High Off Off

Platform LAN Connect Interface

GLAN_CLK Suspend LAN Connect Component Driven Driven Driven

LAN_RXD[2:0] Suspend LAN Connect Com p onent Driven Driven Driven

Gigabit LAN Connect Interface

GLAN_RXp

GLAN_RXn Suspend Gigabit Lan Connect

Component Driven Driven Driven

SATA Interface

SATA_CLKP, SATA_CLKN Core Clock Ge nerator Running Off Off

SATA[3:0]RXP,

SATA[3:0]RXN Core SATA Drive Driven Off Off

SATARBIAS# Core External Pull-down Driven Off Off

SATA[5:4]GP

SATA[3:0]GP /

GPIO[37,36,19]1Core External Device or

External Pull-up/Pu ll-down Driven Off Off

USB Interface

Intel® ICH8 Family Datasheet 103

Intel® ICH8 Pin State s

OC0#, OC[7:1]# /

GPIO[31, 30, 29, 43,

42,41, 40], OC[9:8]# Suspend External Pull-ups Driv e n Driven Driven

USBRBIAS# Suspend External Pull-down Driven Driven Driven

Power Management

CLPWROK Suspend External Circuit Driven Driven Driven

LAN_RST# Suspend External Circuit High High High

MCH_SYNC# Core (G)MCH Driven Off Off

PWRBTN# Suspend Internal Pull-up Driven Driven Driven

PWROK RTC System Power Supply Driven Off Off

RI# Suspend Serial Port Buffer Driven Driven Driven

RSMRST# Suspend External RC Circuit High High High

SYS_RESET# Suspend External Circuit Driven Driven Driven

THRM# Core Thermal Sensor Driven Off O ff

THRMTRIP# Core Therma l Sensor Driven Off Off

VRMPWRGD Suspend Processor Voltage

Regulator High Low Low

WAKE# Suspend External Pull-up Driven Driven Driven

Processor Interface

A20GATE Core External Microcontroller Static Off Off

FERR# Core Processor Static Off Off

RCIN# Core External Microcontroller High Off Off

SMBus Interface

SMBALERT# / GPIO111Suspend External Pull-up Driven Driven Driven

System Management Interface

INTRUDER# RTC External Switch Driven High High

Miscellaneous Signals

INTVRMEN RTC External Pull-up High High Hig h

LAN100_SLP RTC External Pull-up High High High

RTCRST# RTC External RC Circuit High High High

TP[0] Suspend External Pull-up High Hig h High

TP[3] Suspend Internal Pull-up High High High

Intel®High Definition Audio Interface

HDA_SDIN[3:0] Suspend Intel® High Definition

Audio Codec Low Low Low

Table 35. Power Plane for Input Signals for Desktop Configurations (Sheet 2 of 3)

Signal Name Power Well Driver During Reset S1 S3 S4/S5

Intel® ICH8 Pin State s

104 Intel® ICH8 Family Datasheet

NOTES:

1. These signals can be configured as outputs in GPIO mode.

2. The state of the DPRSLPVR and DPRSTP# signals in C4 are high if Deeper Sleep is enabled

or low if it is disabled.

3. GPIO50, GPIO52, GPIO54 need to be glitch free immediately after Reset to when they are

being initialized to GPIO. Multiplexed GPIO signals defaulting to a native function must be

glitch free i mmediately after Reset until the time they ar e initialized as GPIO.

SPI Interface

SPI_MISO Suspend Internal Pull-up Driven Driven Driven

Fan Speed Control

TACH[3:0]/

GPIO[7,6,1,17]1Core External Pull-up Driven Off Off

Clocks

CLK14 Core Clock Generator Running Off Off

CLK48 Core Clock Generator Running Off Off

Table 35. Power Plane for Input Signals for Desktop Configurations (Sheet 3 of 3)

Signal Name Power Well Driver During Reset S1 S3 S4/S5

Table 36. Power Plane for Input Signals for Mobile Configurations (Sheet 1 of 3)

Signal Name Power

Well Driver During Reset C3/C4 S1 S3 S4/S5

DMI

DMI_CLKP

DMI_CLKN Core Clock Generator Running Running Off Off

DMI[3:0]RXP,

DMI[3:0]RXN Core (G)MCH Driven Driven Off Off

PCI Express

PERp[6:1], PERn[6:1] Core PCI Express* Device Driven Driven Off Off

PCI Bus

PCICLK Core Clock Generator Running Running Off Off

PME# Suspend Internal Pull-up Driven Driven Driven Driven

REQ0#,

REQ1/GPIO501, 3

REQ2/GPIO521, 3

REQ3/GPIO531, 3

Core External Pull up Driven Driven Off Off

SERR# Core PCI Bus Peripherals Driven High Off Off

LPC Interface

LDRQ0# Core LPC Dev ic es Dri ven High Off Off

LDRQ1# / GPIO231Core LPC Devices Driven High Off Off

Platform LAN Connect Interface

GLAN_CLK Suspend LAN Connect

Component Driven Driven Driven Driven

Intel® ICH8 Family Datasheet 105

Intel® ICH8 Pin State s

LAN_RXD[2:0] Suspend LAN Connect

Component Driven Driven Driven Driven

Gigabit LAN Connect Interface

GLAN_RXp

GLAN_RXn Suspend Gigabit Lan Connect

Component Driven Driven Driven Driven

SATA Interface

SATA_CLKP, SATA_CLKN Core Clock Generator Running Running Off Off

SATA[2:0]RXP,

SATA[2:0]RXN Core S AT A Drive Driven Driven Off Off

SATARBIAS# Core External Pull-Down Driven Driven Off Off

SATA[5:4]GP

SATA[3:0]GP /

GPIO[37, 36, 19]1Core External Device or

External Pull-up/Pull-

down Driven Driven Off Off

IDE Interface

DDREQ Core IDE Device Driven Static Off Off

IDEIRQ Core IDE Driven Static Off Off

IORDY Core IDE Device Static Static Off Off

USB Interface

OC0#, OC[7:1]# /

GPIO[31, 30, 29, 43,

42,41, 40], OC[9:8]# Suspend External Pull-ups Driven Driven Driven Driven

USBRBIAS# Suspend External Pull-down Driven Driven Driven Driven

Power Management

BMBUSY# /GPIO01Core Graphics Component

[(G)MCH] Driven High Off Off

CLPWROK Suspend External Circuit Driven Driven Driven Driven

LAN_RST# Suspend Power Supply High High Static Static

MCH_SYNC# Core (G)MCH Driven Driven Off Off

PWRBTN# Suspend Internal Pull-up Driven Driven Driven Driven

PWROK RTC System Power Supply Driven Driven Off Off

RI# Suspend Serial Port Buffer Driven Driven Driven Driven

RSMRST# Suspend External RC Circuit High High High High

SYS_RESET# Suspend External Circuit Driven Driven Driven Driven

THRM# Co re Thermal Sensor Dr iven Dr iven Off Off

THRMTRIP# Core Thermal Sensor Driven Driven Off Off

VRMPWRGD Suspend Processor Voltage

Regulator Driven Driven Low Low

WAKE# Suspend External Pull-up Driven Driven Driven Driven

Table 36. Power Plane for Input Signals for Mobile Configurations (Sheet 2 of 3)

Signal Name Power

Well Driver During Reset C3/C4 S1 S3 S4/S5

Intel® ICH8 Pin State s

106 Intel® ICH8 Family Datasheet

NOTE:

1. These signals can be configured as outputs in GPIO mode.

2. The state of the DPRSLPVR and DPRSTP# signals in C4 are high if Deeper Sleep is enabled

or low if it is disabled.

3. GPIO50, GPIO52, GPIO54 need to be glitch free immediately after Reset to when they are

being initialized to GPIO. Multiplexed GPIO signals defaulting to a native function must be

glitch free i mmediately after Reset until the time they ar e initialized as GPIO.

§ §

Processor Interface

A20GATE Core External

Microcontroller Static Static Off Off

FERR# Core Processor Static Static Off Off

RCIN# Core External

Microcontroller High High Off Off

SMBus Interface

SMBALERT# / GPIO111Suspend External P ull-up Driven Driven Driven Driven

System Management Interface

INTRUDER# RTC External Switch Driven Driven High High

Miscellaneous Signals

BATLOW# Suspend Power Supply High High High High

INTVRMEN RTC External Pull-up High High High High

LAN100_SLP RTC External Pull-up High Driven High High

RTCRST# RTC External RC Circuit High High High High

TP[3] Suspend Internal Pull-up High High High High

Intel® High Definition Audio Interface

HDA_SDIN[3:0] Suspend Intel® High Definition

Audio Codec Driven Low Low Low

SPI Interface

SPI_MISO Suspend InternalPull-up Driven Driven Driven Driven

Clocks

CLK14 Core Clock Generator Running Running Off Off

CLK48 Core Clock Generator Running Running Off Off

Table 36. Power Plane for Input Signals for Mobile Configurations (Sheet 3 of 3)

Signal Name Power

Well Driver During Reset C3/C4 S1 S3 S4/S5

Intel® ICH8 Family Datasheet 107

Intel® ICH8 and System Clock Domains

4 Intel® ICH8 and System Clock

Domains

Table 37 shows the system clock domains. Figure 4 and Figure 5 shows the assumed

connection of the various system components, including the clock generator in both

desktop and mobile systems. For complete details of the system clocking solution, refer

to the system’s clock generator component specification.

Table 37. Intel® ICH8 and System Clock Domains

Clock

Domain Frequency Source Usage

ICH8

SATA_CLKP,

SATA_CLKN 100 MHz Main Clock

Generator Differential clock pair used for SATA.

ICH8

DMI_CLKP,

DMI_CLKN 100 MHz Main Clock

Generator Differential clock pair used for DMI.

ICH8

PCICLK 33 MHz Main Clock

Generator

Free-running PCI Clock to Intel® ICH8. This

clock remains on during S0 and S1 (in desktop)

state, and is expected to be shut off during S3

or below in desktop configurations or S1 or

below in mobile configurations.

System PCI 33 MHz Main Clock

Generator

PCI Bus, LPC Inte rface . The s e cl ocks only go to

external PCI and LPC devices. These clocks will

stop based on CLKRUN# (and STP_PCI#) in

mobile configurations.

ICH8

CLK48 48.000 MHz Main Clock

Generator

Super I/O, USB controllers. This clock is

expected to be shut off during S3 or below in

desktop configurat ions or S1 or below in mobi le

configurations.

ICH8

CLK14 14.31818 MHz Main Clock

Generator

Used for ACPI timer and Multimedia Timers .

This clock is expected to be shut off during S3

or below in desktop configurations or S1 or

below in mobile configurations.

GLAN_CLK 5 t o 62.5 MHz LAN Connect

Component

Generated by the LAN Connect component. This

clock is expected to be shut off during S3 or

below in desktop configurations or S1 or below

in mobile configurations.

SPI_CLK 17.86 MHz/

31.25 MHz ICH8

Generated by the ICH8. This clock is expected

to be shut off during S3 or below in desktop

configurations or S1 or below in mobile

configurations.

Intel® ICH8 and System Clock Domains

108 Intel® ICH8 Family Datasheet

§ §

Figure 4. Desktop Conceptual System Clock Diagram

Figure 5. Mobile Conceptual Clock Diagram

Intel

ICH8

PCI Clocks

(33 MHz)

Clock

Gen. 14.31818 MHz

48.000 MHz

32 kHz

XTAL SUSCLK # (32 kH z)

LAN Connect

62.5 MHz

HD Audio Codec(s)

33 MHz

14.31818 MHz

100 MHz

Diff. Pair 1 to 6

Differential

Clock Fan

Out Device

SATA 100 MHz Diff. Pair

DMI 100 MHz Diff. Pair

PCI Express

100

MHz

Diff. Pair s

24 MHz

48.000 MHz

Intel

ICH8-M

32 kHz

XTAL

SUSCLK# (32 kHz)

14.31818 MHz

STP_CPU#

STP_PCI#

PCI Clocks

(33 MHz)

Clock

Gen. 14.31818 MHz

48 MHz

LAN Connect

100 MH z Diff. Pair

SATA 100 M H z D iff. Pa ir

D M I 1 0 0 MHz D iff. P air PCI Express

100

M Hz

D iff. Pa irs

HD Audio Codec(s)

24 MHz

62.5 MHz

48.000 MHz

33 M Hz

1 to 6

Diffe re ntia l

Clock Fan

Out Device

Intel® ICH8 Family Datasheet 109

Functional Description

5 Functional Description

This chapter describes the functions and interfaces of the ICH8 family.

5.1 PCI-to-PCI Bridge (D30:F0)

The PCI-to-PCI bridge resides in PCI Device 30, Function 0 on bus #0. This portion of

the ICH8 implements the buffering and control logic between PCI and Direct Media

Interface (DMI). The arbitration for the PCI bus is handled by this PCI device. The PCI

decoder in this device must decode the ranges for the DMI. All register contents are

lost when core well power is removed.

Direct Media Interface (DMI) is the chip-to-chip connection between the Memory

Controller Hub / Graphics and Memory Controller Hub ((G)MCH) and I/O Controller Hub

8 (ICH8). This high-speed interface integrates advanced priority-based servicing

allowing for concurrent traffic and true isochronous transfer capabilities. Base

functionality is completely software transparen t permitting current and legacy software

to operate normally.

In order to provide for true isochronous transfers and configurable Quality of Service

(QoS) transactions, the ICH8 supports two virtual channels on DMI: VC0 and VC1.

These two channels provide a fixed arbitr ation scheme where VC1 is alwa ys the highest

priority. VC0 is the default conduit of traffic for DMI and is always enabled. VC1 must be

specifically enabled and configured at both ends of the DMI link (i.e ., the ICH8 and

(G)MCH).

Configuration registers for DMI, virtual channel support, and DMI active state power

management (ASPM) are in the RCRB space in the Chipset Config Registers

(Section 7).

5.1.1 PCI Bus Interface

The ICH8 PCI interface supports PCI Local Bus Specification, Revision 2.3, at 33 MHz.

The ICH8 integrates a PCI arbiter that supports up to four external PCI bus masters in

addition to the internal ICH8 requests.

5.1.2 PCI Bridge As an Initiator

The bridge initiates cycles on the PCI bus when granted by the PCI arbiter. The bridge

generates the following cycle types:

Table 38. PCI Bridge Initiator Cycle Types

Command C/BE# Notes

I/O Read/Write 2h/3h Non-posted

Memory Read/Write 6h/7h Writes are posted

Configuration Read/Write Ah/Bh Non-posted

Special Cycles 1h Posted

Functional Description

110 Intel® ICH8 Family Datasheet

5.1.2.1 M emory Reads and Writes

The bridge bursts memory writes on PCI that are received as a single pack et from DMI.

I/O Reads and Writes

The bridge generates single DW I/O read and write cycles. When the cycle completes

on PCI bus, the bridge generates a corresponding completion on DMI. If the cycle is

retried, the cycle is kept in the down bound queue and may be passed by a postable

cycle.

5.1.2.2 C onfiguration Reads and Writes

The bridge generates single DW configuration read and write cycles. When the cycle

completes on PCI bus, the bridge generates a corresponding completion. If the cycle is

retried, the cycle is kept in the down bound queue and may be passed by a postable

cycle.

5.1.2.3 Locked Cycles

The bridge propagates locks from DMI per the PCI Local Bus Specification. The PCI

bridge implements bus lock, which means the arbiter will not grant to an y agent except

DMI while locked.

If a locked read results in a target or master abort, the lock is not established (as per

the PCI Local Bus Specification). Agents north of the ICH8 must not forward a

subsequent locked read to the bridge if they see the first one finish with a failed

completion.

5.1.2.4 T arget / Master Aborts

When a cycle initiated by the bridge is master/target aborted, the bridge will not re-

attempt the same cycle. Fo r multiple DW cycles, the bridge increments the address and

attempts the next DW of the transaction. For all non-postable cycles, a target abort

response packet is returned for each DW that w as master or target aborted on PCI. The

bridge drops posted writes that abort.

5.1.2.5 Seconda ry Master Latency Timer

The bridge implem ents a Master Late nc y Time r vi a the SLT register which, upon

expiration, causes the de-assertion of FRAME# at the next v alid clock edge when there

is another active request to use the PCI bus.

5.1.2.6 Dual Address Cycle (DAC)

The bridge will issue full 64-bit dual address cycles for device memory-mapped

registers above 4 GB.

Intel® ICH8 Family Datasheet 111

Functional Description

5.1.2.7 Memory and I/O Decode to PCI

The PCI bridge in the ICH8 is a subtractive decode agent, which follows the following

rules when forwarding a cycle from DMI to the PCI interface:

• The PCI bridge will positively decode any memory/IO address within its window

registers, assuming PCICMD.MSE (D30:F0:Offset 04h:bit 1) is set for memory

windows and PCICMD.IOSE (D30:F0:Offset 04h:bit 0) is set for IO windows.

• The PCI bridge will subtractively decode any 64-bit memory address not claimed

by another agent, assuming PCICMD.MSE (D30:F0:Offset 04h:bit 1) is set.

• The PCI bridge will subtractively decode any 16-bit I/O address not claimed by

another agent assuming PCICMD.IOSE (D30:F0:Offset 04h:bit 0) set

• If BCTRL.IE (D 30:F0:Offset 3Eh:bit 2) is set, the PCI bridge will not positively

forward from primary to secondary called out ranges in the IO window per PCI

Local Bus Specification (I/O transactions addressing the last 768 bytes in each,

1-KB block: offsets 100h to 3FFh). The PCI bridge will still take them subtractively

assuming the above rules.

• If BCTRL.VGA E (D30:F0:Offset 3Eh:bit 3) is set, the PCI bridge will positively

forward from primary to secondary I/O and memory ranges as called out in the PCI

Bridge Specification, assuming the above rules are met.

5.1.3 Parity Error Detection and Generation

PCI parity errors can be detected and reported. The following behavioral rules apply:

• When a parity error is detected on PCI, the bridge sets the SECSTS.DPE

(D30:F0:Off set 1Eh:bit 15).

• If the bridge is a master and BCTRL.PERE (D30:F0:Offset 3Eh:bit 0) and one of the

parity errors defined below is detected on PCI, then the bridge will set SECSTS.DPD

(D30:F0:Offset 1Eh:bit 8) and will also generate an internal SERR#.

— During a write cycle, the PERR# signal is active, or

— A data parity error is detected while performing a read cycle

• If an address or command parity error is detected on PCI and PCICMD.SEE

(D30:F0:Offset 04h:bit 8), BCTRL.PERE, and BCTRL.SEE (D30:F0:Offset 3Eh:bit 1)

are all set, the bridge will set the PSTS.SSE (D30:F0:Offset 06h:bit 14) and

generate an internal SERR#.

• If the PSTS.SSE is set because of an address parity error and the PCICMD.SEE is

set, the bridge will generate an internal SERR#

• When bad parity is detected from DMI, bad parity will be driven on all data the

bridge.

• When an address parity error is detected on PCI, the PCI bridge will never claim the

cycle. This is a slight deviation from the PCI bridge spec, which says that a cycle

should be claimed if BCTRL.PERE is not set. However, DMI does not have a concept

of address parity error, so claiming the cycle could result in the rest of the system

seeing a bad transaction as a good transaction.

5.1.4 PCIRST#

The PCIRST# pin is generated under two conditions:

•PLTRST# active

• BCTRL.SBR (D30:F0:Offset 3Eh:bit 6) set to 1

The PCIRST# pin is in the resume well. PCIRST# should be tied to PCI bus agents, but

not other agents in the system.

Functional Description

112 Intel® ICH8 Family Datasheet

5.1.5 Peer Cycles

The PCI bridge may be the initiator of peer cycles. Peer cy cles include memory, IO, and

configuration cycle types. Peer cycles are only allowed through VC0, and are enabled

with the following bits:

• BPC.PDE (D30:F0:Offset 4Ch:bit 2) – Me mory and I/O cycles

• BPC.CDE (D30:F0:Offset 4Ch:bit 1) – Configuration cycles

When enabled for peer for one of the above cycle types, the PCI bridge will perform a

peer decode to see if a peer agent can receive the cycle. When not enabled, memory

cycles (posted and/or non-posted) are sent to DMI, and I/O and/or configuration cycles

are not claimed.

Configuration cycles hav e special considerations. Under the PCI Local Bus Specification,

these cycles are not allowed to be forwarded upstream through a bridge. However, to

enable things such as manageability, BPC.CDE can be set. When set, type 1 cycles are

allowed into the part. The address format of the type 1 cycle is slightly different from a

standard PCI configuration cy cle to allow addressing of extended PCI space. The format

is as follows:

Note: The ICH8’ s IDE (Mobile only) and USB controllers cannot perform peer-to-peer traffic.

5.1.6 PCI-to-PCI Bridge Model

From a software perspective, the ICH8 contains a PCI-to-PCI bridge. This bridge

connects DMI to the PCI bus. By using the PCI-to-PCI bridge software model, the ICH8

can have its decode ranges programmed by existing plug-and-play software such that

PCI ranges do not conflict with graphics aperture ranges in the Host controller.

5.1.7 IDSEL to Device Number Mapping

When addressing devices on the external PCI bus (with the PCI slots), the ICH8 asserts

one address signal as an IDSEL. When accessing device 0, the ICH8 asserts AD16.

When accessing Device 1, the ICH8 asserts AD17. This mapping continues all the way

up to device 15 where the ICH8 asserts AD31. Note that the ICH8’s internal functions

(Intel High Definition Audio, IDE (Mobile only), USB, SATA and PCI Bridge) are

enumerated like they are off of a separate PCI bus (DMI) from the external PCI bus.

Table 39. Type 1 Address Format

Bits Definition

31:27 Reserved (same as the PCI Local Bus Specification)

26:24 Extended Confi guration Addres s – allows addressing of up to 4K. These bits are

combined with bits 7:2 to get the full register.

23:16 Bus Number (same as the PCI Local Bus Specification)

15:11 Device Number (same as the PCI Local Bus Specification)

10:8 Function Number (same as the PCI Local Bus Specification)

7:2 Register (same as the PCI Local Bus Specification)

0 Must be 1 to indicate a type 1 cycle. Type 0 cycles are not decoded.

Intel® ICH8 Family Datasheet 113

Functional Description

5.1.8 Standard PCI Bus Configuration Mechanism

The PCI Bus defines a slot based “configuration space” that allows each device to

contain up to eight functions with each function containing up to 256, 8-bit

configuration registers. The PCI Local Bus Specification, Revision 2.3 defines two bus

cycles to access the PCI configuration space: Configuration Read and Configuration

Write. Memory and I/O spaces are supported directly by the processor. Configuration

space is supported by a mapping mechanism implemented within the ICH8. The PCI

Local Bus Specification, Revision 2.3 defines two mechanisms to access configuration

space, Mechanism 1 and Mechanism 2. The ICH8 only supports Mechanism 1.

Warning: Configuration writes to intern al devices, w hen the devices are disabled, are invalid and

may cause undefined results.

5.2 PCI Express* Root Ports (D28:F0,F1,F2,F3,F4,F5)

There are six root ports available in ICH8. These all reside in device 28, and take

function 0 – 5. Port 1 is function 0, port 2 is function 1, port 3 is function 2, port 4 is

function 3, port 5 is function 4, and port 6 is function 5.

5.2.1 Interrupt Generation

The root port generates interrupts on behalf of Hot-Plug and power management

events, w hen enable d. T hese i nterrup ts can ei ther be pin based, or can be MSIs, when

enabled.

When an interrupt is generated via the legacy pin, the pin is internally routed to the

ICH8 interrupt controllers. The pin that is driven is based upon the setting of the

chipset configuration registers. Specifically, the chipset configuration registers used are

the D28IP (Base address + 310Ch) and D28IR (Base address + 3146h) register s.

Table 40 summarizes interrupt behavior for MSI and wire-modes. In the table “bits”

refers to the Hot-Plug and PME interrupt bits.

Table 40. MSI vs. PCI IRQ Actions

Interrupt Register Wire-Mode

Action MSI Action

All bits 0 Wire inactive No action

One or more bits set to 1 Wire active Send

message

One or more bits set to 1, new bit gets set to 1 Wire active Send

message

One or more bits set to 1, soft wa re clears some (bu t not all )

bits Wire active Send

message

One or more bits set to 1, software clears all bits Wire inactive No action

Software clears one or more bits, and one or more bits are

set on the same clock Wire active Send

message

Functional Description

114 Intel® ICH8 Family Datasheet

5.2.2 Power Management

5.2.2.1 S3/S4/S5 Support

Software initiates the tran sitio n to S3/S4/S5 by performing an IO write to the Power

Management Control register in the ICH8. After the IO write completion has been

returned to the processor, each root port will send a PME_Turn_Off TLP (Transaction

Layer Packet) message on its downstream link. The device attached to the link will

eventually respond with a PME_TO_Ack TLP message followed by sending a

PM_Enter_L23 DLLP (Data Link Layer Packet) request to enter the L2/L3 Ready state.

When all of the ICH8 root ports links are in the L2/L3 Ready state, the ICH8 power

management control logic will proceed with the entry into S3/S4/S5.

Prior to entering S3, software is requ ired to put each device into D3 HOT. When a device

is put into D3HOT it will initiate entry into a L1 link state by sending a PM_Enter_L1

DLLP. Thus under normal operating conditions when the root ports sends the

PME_Turn_Off message the link will be in state L1. However, when the root port is

instructed to send the PME_Turn_Off message, it will send it whether or not the link

was in L1. Endpoints attached to the ICH8 can make no assumptions about th e state of

the link prior to receiving a PME_Turn_Off message.

5.2.2.2 Resuming from Suspended State

The root port contains enough circuitry in the resume well to detect a wake event

through the WAKE# signal and to wake the system. When WAKE# is detected asserted,

an internal signal is sent to the power management controller of the ICH8 to cause the

system to wake up. This internal message is not logged in any register, nor is an

interrupt/GPE generated due to it.

5.2.2.3 Device Initiated PM_PME Message

When the system has returned to a working state from a previous low power state, a

device requesting service will send a PM_PME message continuously, until acknowledge

by the root port. The root port will take different actions depending upon whether this

is the first PM_PME has been received, or whether a previous message has been

received but not yet serviced by the operating system.

If this is the first message received (RSTS.PS - D28:F0/F1/F2/F3/F4/F5:Offset 60h:bit

16 is cleared), the root port will set RSTS.PS, and log the PME Requester ID into

RSTS.RID (D28:F0/F1/F2/F3/F4/F5:Offset 60h:bits 15:0). If an interrupt is enabled via

RCTL.PIE (D28:F0/F1/F2/F3/F4/F5:Offset 5Ch:bit 3), an interrupt will be generated.

This interrupt can be either a pin or an MSI if MSI is enabled via MC.MSIE (D28:F0/F1/

F2/F3/F4/F5:Offset 82h:bit 0). See Section 5.2.2.4 for SMI/SCI generation.

If this is a subsequent message receiv ed (RSTS.PS is already set), the root port will set

RSTS.PP (D28:F0/F1/F2/F3/F4/F5:Offset 60h:bit 17) and log the PME Requester ID

from the message in a hidden register. No other action will be taken.

When the first PME event is cleared by software clearing RSTS .PS, the root port will set

RSTS.PS, clear RSTS.PP, and move the requester ID from the hidden register into

RSTS.RID.

If RCTL.PIE is set, genera te an interrupt. If RCTL.PIE is not set, send o ver to the power

management controller so that a GPE can be set. If messages have been logged

(RSTS.PS is set), and RCTL.PIE is later written from a 0 to a 1, and interrupt must be

generated. This last condition handles the case where the message was received prior

to the operating system re-enabling interrupts after resuming from a low power state.

Intel® ICH8 Family Datasheet 115

Functional Description

5.2.2.4 SMI/SCI Generation

Interrupts for power management events are not supported on legacy operating

systems. To support power management on non-PCI Express aware oper ating systems,

PM events can be routed to generate SCI. To generate SCI, MPC.PMCE must be set.

When set, a power management event will cause SMSCS.PMCS (D28:F0/F1/F2/F3/F4/

F5:Offset DCh:bit 31) to be set.

Additionally, BIOS workarounds for power management can be supported by setting

MPC.PMME (D28:F0/F1/F2/F3/F4/F5:Offset D8h:bit 0). When this bit is set, power

management events will set SMSCS.PMMS (D28:F0/F1/F2/F3/F4/F5:Offset DCh:bit 0),

and SMI # will be generated. This bit will be set regardless of whether interrupts or SCI

is enabled. The SMI# may occur concurrently with an interrupt or SCI.

5.2.3 SERR# Generation

SERR# may be generated via two path s – through PCI mechanisms involving bits in the

PCI header, or through PCI Express mechanisms involving bits in the PCI Express

capability structure.

5.2.4 Hot-Plug

Each root port implements a Hot-Plug controller which performs the following:

• Messages to turn on / off / blink LEDs

• Presence and attention button detection

• Interrupt generation

The root port only allows Hot-Plug with modules (e.g., ExpressCard*). Edge-connector

based Hot-Plug is not supported.

5.2.4.1 Presence Detection

When a module is plugged in and power is supplied, the physical layer will detect the

presence of the device, and the root port sets SLSTS.PDS (D28:F0/F1/F2/F3/F4/

F5:Offset 5Ah:bit 6) and SLSTS.PDC (D28:F0/F1/F2/F3:Offset 6h:bit 3). If SLCTL.PDE

(D28:F0/F1/F2/F3F4/F5:Offset 58h:bit 3) and SLCTL.HPE (D28:F0/F1/F2/F3F4/

F5:Offset 58h:bit 5) are both set, the root port will also generate an interrupt.

When a module is removed (via the physical layer detection), the root port clears

SLSTS.PDS and sets SLSTS.PDC. If SLCTL.PDE and SLCTL.HPE are both set, the root

port will also generate an interrupt.

Figure 6. Generation of SERR# to Platform

PSTS.SSE

SERR#

PCICMD.SEE

Secondary Parity Error

Primary Parity Error

Secondary SERR#

Correctabl e S ERR#

Fatal SERR#

Non-Fatal SERR#

PCI

PCI Express

Functional Description

116 Intel® ICH8 Family Datasheet

5.2.4.2 Message Generation

When system software writes to SLCTL.AIC (D28:F0/F1/F2/F3F4/F5:Offset 58h:bits

7:6) or SLCTL.PIC (D28:F0/F1/F2/F3F4/F5:Offset 58h:bits 9:8), the root port will send

a message down the link to change the state of LEDs on the module.

Writes to these fields are non-postable cycles, and the resulting message is a postable

cycle. When receiving one of these writes, the root port performs the following:

• Changes the state in the register.

• Generates a completion into the upstream queue

• Formulates a message for the downstream port if the field is written to regardless

of if the field changed.

• Generates the message on the downstream port

• When the last message of a command is transmitted, sets SLSTS.CCE (D28:F0/F1/

F2/F3F4/F5:Offset 58h:bit 4) to indicate the command has completed. If

SLCTL.CCE and SLCTL.HPE (D28:F0/F1/F2/F3F4/F5:Offset 58h:bit 5) are set, the

root port generates an interrupt.

The command completed register (SLSTS.CC) applies only to commands issued by

software to control the Attention Indicator (SLCTL.AIC), Power Indicator (SLCTL.PIC),

or Power Controller (SLCTL.PCC). However, writes to other parts of the Slot Control

Hence, any write to the Slot Control Register is considered a command and if enabled,

will result in a command complete interrupt. The only exception to this rule is a write to

disable the command complete interrupt which will not result in a command complete

interrupt.

A single write to the Slot Control register is considered to be a single command, and

hence receives a single command complete, even if the write affects more than one

field in the Slot Control Register.

5.2.4.3 Attention Button Detection

When an attached device is ejected, an attention button could be pressed by the user.

This attention button press will result in a the PCI Express message

“Attention_Button_Pressed” from the device. Upon receiving this message, the root

port will set SLSTS.ABP (D28:F0/F1/F2/F3F4/F5:Offset 5Ah:bit 0).

If SLCTL.ABE (D28:F0/F1/F2/F3F4/F5:Offset 58h:bit 0) and SLCTL.HPE (D28:F0/F1/F2/

F3F4/F5:Offset 58h:bit 5) are set, the Hot-Plug controller will also generate an

interrupt. The interrupt is generated on an edge-event. For example, if SLSTS.ABP is

already set, a new interrupt will not be generated.

Intel® ICH8 Family Datasheet 117

Functional Description

5.2.4.4 SMI/SCI Generation

Interrupts for Hot-Plug events are not supported on legacy operating systems. To

support Hot -Plug on non-PCI Express aware oper ating systems, Hot-Plug ev ents can be

routed to generate SCI. To generate SCI, MPC.HPCE (D28:F0/F1/F2/F3F4/F5:Offset

D8h:bit 30) must be set. When set, enabled Hot-Plug events will cause SMSCS.HPCS

(D28:F0/F1/F2/F3F4/F5:Offset DCh:bit 30) to be set.

Additionally, BIOS workarounds for Hot-Plug can be supported by setting MPC.HPME

(D28:F0/F1/F2/F3F4/F5:Offset D8h:bit 1). When this bit is set, Hot-Plug events can

cause SMI status bits in SMSCS to be set. Supported Hot-Plug events and their

corresponding SMSCS bit are:

• Command Completed - SCSCS.HPCCM (D28:F0/F1/F2/F3/F4/F5:Offset DCh:bit 3)

• Presence Detect Changed - SMSCS.HPPDM (D28:F0/F1/F2/F3/F4/F5:Offset DCh:bit

• Attention Button Pressed - SMSCS.HP ABM (D28:F0/F1/F2/F3/F4/F5:Offset DCh:bit

• Link Active State Changed - SMSCS.HPLAS (D28:F0/F1/F2/F3/F4/F5:Offset DCh:bit

When any of these bits are set, SMI # will be generated. These bits are set regardless

of whether interrupts or SCI is enabled for Hot-Plug events. The SMI# may occur

concurrently with an interrupt or SCI.

Functional Description

118 Intel® ICH8 Family Datasheet

5.3 Gigabit Ethernet Controller (B0:D25:F0)

The ICH8 integrates a Gigabit Ethernet Controller. The integrated GbE controller is

compatible with Intel 10/100 PHY (Intel® 82562V Platform LAN Connect device) and

GbE PHY (Intel® 82566 Gigabit Platform LA N Connect device). Th e integrated GbE

controller provides two interfaces: LCI for 10/100 operation and GLCI for GbE

operation. The GLCI is shared with the ICH8’s PCI Express port 6 and can be enabled

via a soft strap that is stored in system SPI flash.

The ICH8 integrated GbE controller supports multi speed oper ation, 10/100/1000 Mb/s.

The integrated GbE can operate in full-duplex at all supported speed or half-duplex at

10/100 Mb/s, and adheres with the IEEE 802.3x Flow Control Specification.

The controller provides a system interface via a PCI function. A full memory-m apped or

I/O-mapped interface is provided to the software, along with DMA mechanisms for high

performance data transfer.

The following summarizes the ICH8 integrated GbE controller features:

• Configurable LED operation for customization of LED display.

• IPv4 and IPv6 Checksum Offload support (receive, transmit, and large send)

• 64-bit address master support for system using more than 4 GB of physical

memory.

• Configurable receive and transmit data FIFO, programmable in 1 KB increments.

• Intelligent interrupt generation to enhance driver performance

• Compliance with Advanced Configuration and Power Interface and PCI Power

Management standards

• ACPI register set and power down functionality supporti ng D0 & D3 states

• Full wake-up support (ACPI)

• Magic Packet wake-up enable with unique MAC address

• Fragmented UDP checksum off load for package reassembly

5.3.1 GbE PCI Bus Interface

The GbE controller has a PCI interface to the host processor and host memory. The

following sections detail the transaction on the bus.

5.3.1.1 Transaction Layer

The upper layer of the host architecture is the transaction layer. The transaction layer

connects to the device core using an implementation specific protocol. Through this

core-to-transaction-layer protocol, the application-specific parts of the device interact

with the subsystem and transmit and receive requests to or from the remote agent,

respectively.

5.3.1.2 Data Alignment

5.3.1.2.1 4K Boundary

PCI requests must never specify an Address/Length combination that causes a Memory

Space access to cross a 4K boundary. It is the HW responsibility to break requests into

4K-aligned requests (if needed). This does not pose any requirement on SW. However,

if SW allocates a buffer across a 4K boundary, HW will issue multiple requests for the

buffer. SW should consider aligning buffers to 4KB boundary in cases where it improves

performance.

The alignment to the 4K boundaries is done in the core. The Transaction layer will not

do any alignment according to these boundaries.

Intel® ICH8 Family Datasheet 119

Functional Description

5.3.1.2.2 64 Bytes

PCI requests are multiples of 64 bytes and aligned to make better use of memory

controller resources. W rites, however, can be on any boundary and can cross a 64 byte

alignment boundary

5.3.1.3 Configuration Request Retry Status

The LAN Controller might have a delay in initialization due to NVM read. If the NVM

configuration read operation is not completed and the device receives a Configuration

Re quest, the device will respond with a Configuration Request Retry Completion Status

to terminate th e Reques t, and thus effectivel y stall the Configuration R equest until such

time that the subsystem has completed local initialization and is ready to communicate

with the host.

5.3.2 Error Events and Error Reporting

5.3.2.1 Data Parity Error

The PCI Host bus does not provide parity protection, but it does forward parity errors

from bridges. The LAN Controller recognizes parity errors through the internal bus

interface and will set the Parity Error bit in PCI Configur ation space. If parity errors are

enabled in configuration space, a system error will be indicated on the PCI Host bus to

the chipset. The offending cycle with a parity error will be dropped and not processed

by the LAN Controller.

5.3.2.2 Completion with Unsuccessful Completion Status

A completion with unsuccessful completion status (any status other than "000") will be

dropped and not processed by the LAN Controller. Furthermore, the request that

corresponds to the unsuccessful completion will not be retried. When this unsuccessful

completion status is received, the System Error bit in the PCI Configuration space will

be set. If the system errors are enabled in configuration space, a system error will be

indicated on the PCI Host bus to the chipset.

5.3.3 Ethernet Interface

The integrated LAN controller provides a complete CSMA/CD function supporting IEEE

802.3 (10Mb/s), 802.3u (100Mb/s) implementations. It also supports the IEEE 802.3z

and 802.3ab (1000Mb/s) implementations. The device performs all of the functions

required for transmission, reception and collision handling called out in the standards.

The mode used to communicate between the LAN controller and the LAN connect

device supports 10/100/1000 Mbps operation, with both half- and full-duplex oper ation

at 10/100 Mbps, and full-duplex operation at 1000 Mbps

5.3.3.1 MAC/LAN Connect Interface

The integrated LAN controller and LAN Connect Device communicate through either the

platform LAN connect interface (LCI) or GbE LAN connect interface (GLCI). All

controller configuration is performed using device control registers mapped into system

memory or I/O space. The LAN Connect Device is configured via the LCI or GbE Lan

connect interface.

The integrated MAC supports various modes as summarized in Table 41.

Functional Description

120 Intel® ICH8 Family Datasheet

5.3.4 PCI Power Management

The LAN Controller supports the Advanced Configuration and Power Interface (ACPI)

specification as well as Advanced Power Management (APM). This allows the host to be

awoken (i.e. from Sx to S0) by network-related activity via an internal host wake

signal.

The LAN controller contains power management registers for PCI, and supports D0 and

D3 states. PCI transactions are only allowed in the D0 state, except for host accesses

to the LAN controller’s PCI configuration registers.

5.3.4.1 Wake-Up

The LAN Controller supports two types of wakeup mechanisms:

1) Advanced Power Management (APM) Wakeup

2) ACPI Power Management Wakeup

Both mechanisms use an internal WAKE# signal to wake the system up. This signal is

connected to the resume wake logic in the ICH8. The wake-up steps are as follows:

1) Host Wake Event occurs (note that packet is not delivered to host)

2) PME_STATUS bit is set

3) Internal WAKE# signal asserted by Host LAN function

4) System wakes from Sx state to S0 state

5) The Host LAN function is transitioned to D0

6) The Host clears the PME_STATUS bit

7) Internal WAKE# signal is deasserted by Host LAN function

5.3.4.1.1 Advanced Power Management Wakeup

"Advanced Power Management Wakeup", or "APM Wakeup", was previously known as

"Wake on LAN". It is a feature that has existed in the 10/100 Mbps NICs for several

generations. The basic premise is to receive a broadcast or unicast packet with an

explicit data pattern, and then to assert a signal to wake-up the system. In the earlier

generations, this was accomplished by using special signal that ran across a cable to a

defined connector on the motherboard. The NIC would assert the signal for

approximately 50ms to signal a wakeup. The LAN Controller uses (if configured to) an

in-band PM_PME message for this.

On power-up, the LAN Controller will read the APM Enable bits from the NVM PCI Init

Control Word into the APM Enable (APME) bits of the Wakeup Control Register (WUC).

These bits control enabling of APM Wakeup.

When APM Wakeup is enabled, the LAN Controller checks all incoming packets for

"Magic Packets".

Table 41. LAN Mode Support

Mode Interface Active Connections

Legacy 10/100 LCI 82562

Normal 10/100/1000 LCI, GLCI 82566

Intel® ICH8 Family Datasheet 121

Functional Description

Once the LAN Controller receives a matching magic packet, it will:

• Set the Magic Packet Received bit in the Wake Up Status Register (WUS).

• Set the PME_Status bit in the Power Management Control / Status Register

(PMCSR) and assert the internal WAKE# signal.

"APM Wakeup" is supported in all power states and only disabled if a subsequent NVM

read results in the APM Wake Up bit being cleared or the software explicitly writes a 0

to the APM Wake Up (APM) bit of the WUC register.

5.3.4.1.2 ACPI Power Management Wakeup

The LAN Controller supports ACPI P o wer Management based Wakeups. It can generate

system wake-up events from three sources:

• Reception of a "Magic Packet".

• Reception of a Network Wakeup Packet.

• Detection of a link change of state.

Activating ACPI Power Management Wakeup requires the following steps:

• The driver programs the Wake Up Filter Control Register (WUF C) to indicate the

packets it wishes to wake up and supplies the necessary data to the Ipv4 Address

Table (IP4A T) and the Flexible Filter Mask Table (FFMT), Flexible Filter Length Table

(FFLT), and the Flexible Filter Value Table (FFVT). It can also set the Link Status

Change Wake Up Enable (LNKC) bit in the Wake Up Filter Control Register (WUFC)

to cause wakeup when the link changes state.

• The OS (at configuration time) writes a 1 to the PME_En bit of the Power

Management Control / Status Register (PMCSR.8).

Normally, after enabling wakeup, the OS will write 11b to the lower two bits of the

PMCSR to put the LAN Controller into low-power mode.

Once Wakeup is enabled, the LAN Controller monitors incoming packets, first filtering

them according to its standard address filtering method, then filtering them with all of

the enabled wakeup filters. If a packet passes both the standard address filtering and

at least one of the enabled wakeup filters, the LAN Controller will:

• Set the PME_Status bit in the Power Management Control / Status Register

(PMCSR)

• If the PME_En bit in the Power Management Control / Status Register (PMCSR) is

set, assert the internal WAKE# signal.

• Set one or more of the "Received" bits in the Wake Up Status Register (WUS).

(More than one bit will be set if a packet matches more than one filter.)

If enabled, a link state change wakeup will cause similar results, setting PME_Status,

asserting the internal WAKE# signal and setting the Link Status Changed (LNKC) bit in

the Wake Up Status Register (WUS) when the link goes up or down.

The internal WAKE# signal will remain asserted until the OS either writes a 1 to the

PME_Status bit of the PMCSR register or writes a 0 to the PME_En bit.

After receiving a wakeup packet, the LAN Controller will igno re any subsequent wakeup

packets until the driver clears all of the "R eceived" bits in the Wake Up Status Register

(WUS). It will also ignore link change events until the driver clears the Link Status

Changed (LNKC) bit in the Wake Up Status Register (WUS).

Functional Description

122 Intel® ICH8 Family Datasheet

5.3.5 Configurable LEDs

The LAN Controller supports 3 controllable and configurable LEDs that are driven from

the LAN Connect Device. Each of the three LED outputs can be individually configured

to select the particular event, state, or activity, which will be indicated on that output.

In addition, each LED can be individually configured for output polarity as well as for

blinking versus non-blinking (steady-state) indication.

The configuration for LED outputs is specified via the LEDCTL register. Furthermore, the

hardware-default configuration for all the LED outpu ts, can be specified via NVM fields,

thereby supporting LED displays configurable to a particular OEM preference.

Each of the 3 LEDs may be configured to use one of a variety of sources for output

indication. The MODE bits control the LED source:

• LINK_100/1000 is asserted when link is established at either 100 or 1000 Mbps.

• LINK_10/1000 is asserted when link is established at either 10 or 1000 Mbps.

• LINK_UP is asserted when any speed link is established and maintained.

• ACTIVITY is asserted when link is established and packets are being tr ansmitted or

received.

• LINK/ACTIVITY is asserted when link is established AND there is NO transmit or

receive activity

• LINK_10 is asserted when a 10 Mbps link is established and maintained.

• LINK_100 is asserted whe n a 100 Mbps link is established and maintained.

• LINK_1000 is asserted when a 1000 Mbps link is established and maintained.

• FULL_DUPLEX is asserted when the link is configured for full duplex operation.

• COLLISION is asserted when a collision is observed.

• PAUSED is asserted when the device's transmitter is flow controlled.

• LED_ON is always asserted; LED_OFF is always de-asserted.

The IVRT bits allow the LED source to be inverted before being output or observed by

the blink-control logic. LED outputs are assumed to normally be connected to the

negative side (cathode) of an external LED.

The BLINK bits control whether the LED should be blinked while the LED source is

asserted, and the blinking frequency (either 200 ms on and 200 ms off or 83 ms on and

83 ms off). The blink control may be especially useful for ensuring that certain events,

such as ACTIVITY indication, cause LED transitions, which are sufficiently visible to a

human eye. The same blinking rate is shared by all LEDs.

5.3.6 Intel® Auto Connect Battery Saver (Mobile Only)

Intel® Auto Connect Battery Saver (ACBS) is a power saving feature that completely or

partially shuts down the Intel® 82566 Gigabit Platform LAN Connect (PLC) device. This

power saving mode, if enabled, is entered upon link loss due to LAN cable

disconnection in S0. The PLC device will automatically resume power and reestablish its

connection when link pulses from a link partner are detected in S0.

The Intel® ACBS feature is controlled by the LAN Driver. The SW driver is responsible

for the PLC transitioning into Intel ACBS mode and the ICH8M Gigabit LAN Controller

HW is responsible for detecting the presence of a link partner which indicates that the

Intel ACBS mode should be terminated.

Intel® ICH8 Family Datasheet 123

Functional Description

5.3.6.1 Partial and Full Power Down Options

Intel Auto Connect Battery Saver has two power saving implementations: partial or full

power down of the PLC device. Both options require an external discrete energy

detection circuit and the use of the ICH8M ENERGY_DETECT signal.

Partial Power Down: Upon link loss the LAN controller sends an in-band message to

power down the internal 1.8V and 1.0V voltage regulators of the PLC device.

Full Power Down: The LAN PHY Power Control feature can be used to signal to an

external power supply controller or a FET switch to power down all the externally

supplied voltage rails of the PLC device.

5.3.6.1.1 Energy Detect

Energy Detection is essential to Intel ACBS operation. Energy Detection uses an on-

board discrete circuit to indicate a link partner is connected to the LAN cable. When in

Intel ACBS mode and a link is reestablished the ENERGY_DETECT signal will indicate to

the ICH8M Gigabit LAN Controller (GPIO13 input) to exit Intel ACBS mode and restore

power to the PLC device using the LAN PHY power control feature. Refer to Mobile

Design Guides for further information on the Energy Detection circuit.

5.3.6.1.2 LAN PHY Power Control

The LAN PHY Po wer Control function controls the power supplies to the PLC device. The

LAN PHY Power Control function can be routed to a power supply controller or FET

switch using either the ICH8M GLAN_DOCK# or SPI_CS1# signals configured by the

appropriate soft straps described in Section 24.2.5. The polarity of the signal

associated with the LAN PHY P ower Control function can be configured in the NVM, refer

to the Intel® I/O Controller Hub 8 (ICH8) NVM Map and Programming Information

Application Note (AP-496) for details. The LAN PHY power control feature is required to

fully power down the PLC device. This feature is also used to restore power to the PLC

device when the ENERGY_DETECT signal is asserted and the PLC device is in Intel ACBS

mode.

A platform designer may choose to implement Intel ACBS without the LAN PHY Power

Control feature. In such a case, the PLC device will only be able to be partially powered

down when the internal voltage regulators are used.

5.3.6.2 Intel® ACBS Signal Configurations

Both partial and full power down implementations of Intel ACBS require the use of

GPIO13 of the ICH8M as the ENERGY_DETECT signal. There are no additional ICH8M

configuration requirements for partial power down functionality.

For full power down capability two configurations are available for implementation of

Intel ACBS:

1. The recommended implementation is to use the GLAN_DOCK# signal for LAN PHY

Power Control functionality.

2. If GLAN_DOCK# is a required signal, SPI_CS1# can be configured to support the

LAN PHY Power control feature.

Both configurations are set by the use of ICH8M soft straps located in the Flash

Descriptor Memory Mapped Configuration Registers. See Section 24.2.5.1. If both

GLAN_DOCK# and SPI_CS1# are required signals, only Intel ACBS with partial power

down functionality can be enabled.

Functional Description

124 Intel® ICH8 Family Datasheet

5.4 LPC Bridge (w/ System and Management

Functions) (D31:F0)

The LPC bridge function of the ICH8 resides in PCI Device 31:Function 0. In addition to

the LPC bridge function, D31 : F0 contains other functional units including DMA,

Interrupt controllers, Timers, Power Management, System Management, GPIO, and

RTC. In this chapter, registers and functions associated with other functional units

(power management, GPIO, USB , IDE (Mo bile only), etc.) are described in their

respective sections.

5.4.1 LPC Interface

The ICH8 implements an LPC interface as described in the Low Pin Coun t Interfa ce

Specification, Revision 1.1. The LPC interface to the ICH8 is shown in Figure 7. Note

that the ICH8 implements all of the signals that are shown as optional, but peripherals

are not required to do so.

Figure 7. LPC Interface Diagram

Intel® ICH8 Family Datasheet 125

Functional Description

5.4.1.1 LPC Cycle Types

The ICH8 implements all of the cycle types described in the Low Pin Count Interface

Specification, Revision 1.0. Table 42 shows the cycle types supported by the ICH8.

NOTES:

1. For memory cycles below 16 MB that do not target enabled firmware hub ranges, the ICH8

performs standard LPC memory cycles. It only attempts 8-bit transfers. For larger

transfers, the ICH8 performs multiple 8-bit transfers. If the cycle is not claimed by any

peripheral, it is subsequently aborted, and the ICH8 returns a value of all 1s to the

processor. This is done to maintain compatibility with ISA memory cycles where pull-up

resistors would keep the bu s high if no device responds.

2. Bus Master Read or Write cycles must be naturally aligned. For example, a 1-byte transfer

can be to any address. However, the 2-byte transfer must be word-aligned (i.e., with an

address where A0=0). A dword transfer must be dword-aligned (i.e., with an address

where A1 and A0 are both 0).

5.4.1.2 Start Field Definition

NOTE: All other encodings are RESERVED.

Table 42. LPC Cycle Types Supported

Cycle Type Comment

I/O Read 1 byte only. Intel® ICH8 breaks up 16- and 32-bit processor cycles into

multiple 8-bit transfers.

I/O Write 1 byte only. ICH8 breaks up 16- and 32-bit proc essor c ycles into mul tiple

8-bit transfers.

DMA Read Can be 1, or 2 bytes

DMA Write Can be 1, or 2 bytes

Bus Master Read Can be 1, 2, or 4 bytes. (See Note 2 below)

Bus Master Write Can be 1, 2, or 4 bytes. (See Note 2 below)

Table 43. Start Field Bit Definitions

Bits[3:0]

Encoding Definition

0000 Start of cycle for a generic target

0010 Grant for bus master 0

0011 Grant for bus master 1

1111 Stop/Abort: End of a cycle for a

target.

Functional Description

126 Intel® ICH8 Family Datasheet

5.4.1.3 Cycle Type / Direction (CYCTYPE + DIR)

The ICH8 always drives bit 0 of this field to 0. Peripherals running bus master cycles

must also drive bit 0 to 0. Table 44 shows the valid bit encodings.

5.4.1.4 Size

Bits[3:2] are reserved. The ICH8 always drives them to 00. Peripherals running bus

master cycles are also supposed to drive 00 for bits 3:2; however, the ICH8 ignores

those bits. Bits[1:0] are encoded as listed in Table 45.

Table 44. Cycle Type Bit Definitions

Bits[3:2] Bit1 Definition

00 0 I/O Read

00 1 I/O Write

10 0 DMA Read

10 1 DMA Write

11 x Reserved. If a peripheral performing a bus master cycle generates this

value, the Intel® ICH8 aborts the cy c le.

Table 45. Transfer Size Bit Definition

Bits[1:0] Size

00 8-bit transfer (1 byte)

01 16-bit transfer (2 bytes)

10 Reserved. The Intel® ICH8 never drives this combination. If a peripheral running

a bus master cycle drives this combination, the ICH8 may abort the transfer.

11 32-bit transfer (4 bytes)

Intel® ICH8 Family Datasheet 127

Functional Description

5.4.1.5 SYNC

Valid values for the SYNC field are shown in Table 46.

NOTES:

1. All other combinations are RESERVED.

2. If the LPC controll er re ceives any SYNC re turned from the device other than short (0101),

long wait (0110), or ready (0000) when running a FWH cycle, indeterminate results may

occur. A FWH device is not allowed to assert an Error SYNC.

5.4.1.6 SYNC Time-Out

There are several error cases that can occur on the LPC interface. The ICH8 responds

as defined in Section 4.2.1.9 of the Low Pin Count Interface Specification, Revision 1.1

to the stimuli described therein. There may be other peripheral failure conditions;

however, these are not handled by the ICH8.

5.4.1.7 SYNC Error Indication

The ICH8 responds as defined in Section 4.2.1.10 of the Low Pin Count Interface

Specification, Revision 1.1.

Upon recognizing the SYNC field indicating an error, the ICH8 treats this as an SERR by

reporting this into the Device 31 Error Reporting Logic.

5.4.1.8 LFRAME# Usage

The ICH8 follows the usage of LFRAME# as defined in the Low Pin Count Interface

Specification, Revision 1.1.

The ICH8 performs an abort for the following cases (possible failure cases):

• ICH8 starts a Memory, I/O, or DMA cycle, but no device drives a valid SYNC after

four consecutive clocks.

• ICH8 starts a Memory, I/O, or DMA cy cle, and the peripheral drives an inv alid SYNC

pattern.

• A peripheral drives an invalid address when performing bus master cycles.

• A peripheral drives an invalid value.

Table 46. SYNC Bit Definition

Bits[3:0] Indication

0000 Ready: SYNC achieved with no error. For DMA transfers, this also indicates DMA

request deassertion and no more transfers desired for that channel.

0101 Short Wait: Part indicating wait-states. For bus master cycles, the Intel® ICH8

does not use this encoding. Instead, the ICH8 uses the Long Wait encoding (see

next encoding below).

0110 Long Wait: Part indicating wait-states, and many wait-states will be added. This

encoding driven by the ICH8 for bus mast er cycles, rather than the Short Wait

(0101).

1001

Ready More (Used only by peripheral for DMA cy cl e): SYNC achieved with

no error and more DMA transfers desired to continue after this transfer. This

value is valid only on DMA transfers and is not allowed for any other type of

cycle.

1010

Error: Sync achieved with error. This is generally used to replace the SERR# or

IOCHK# signal on the PCI/ISA bus. It indicates that the data is to be tr ansferred,

but there is a serious error in this transfer. For DMA transfers, this not only

indicates an error, but also indicates DMA request deassertion and no more

transfers desired for that channel.

Functional Description

128 Intel® ICH8 Family Datasheet

5.4.1.9 I /O Cycles

For I/O cycles targeting registers specified in the ICH8’s decode ranges, the ICH8

performs I/O cycles as defined in the Low Pin Count Interface Specification, Revision

1.1. These are 8-bit transfers. If the processor attempts a 16-bit or 32-bit tr ansfer, the

ICH8 breaks the cycle up into multiple 8-bit transfers to consecutive I/O addresses.

Note: If the cycle is not claimed by any peripheral (and subsequently aborted), the ICH8

returns a value of all 1s (FFh) to the processor. This is to maintain compatibility with

ISA I/O cycles where pull-up resistors would keep the bus high if no device responds.

5.4.1.10 Bus Master Cycles

The ICH8 supports Bus Master cycles and requests (using LDRQ#) as defined in the

Low Pin Count Interface Specific ation, Revision 1.1. The ICH8 has two LDRQ# inputs,

and thus supports two separate bus master devices. It uses the associated ST ART fields

for Bus Master 0 (0010b) or Bus Master 1 (0011b).

Note: The ICH8 does not support LPC Bus Masters performing I/O cycles. LPC Bus Masters

should only perform memory read or memory write cycles.

5.4.1.11 LPC Power Management

CLKRUN# Protocol (Mobile Only)

The CLKRUN# protocol is same as the PCI Local Bus Specification. Stopping the PCI

clock stops the LPC clock.

LPCPD# Protocol

Same timings as for SUS_STAT#. Upon driving SUS_STAT# low, LPC peripherals drive

LDRQ# low or tri-state it. ICH8 shuts off the LD RQ# inpu t buffers. After driving

SUS_STAT# active, the ICH8 drives LFRAME# low, and tri-states (or drive low)

LAD[3:0].

Note: The Low Pin Count Interface Specification, Revision 1.1 defines the LPCPD# protocol

where there is at least 30 µs from LPCPD# assertion to LRST# assertion. This

specification explicitly states that this protocol only applies to entry/exit of low power

states which does not include asynchronous reset events. The ICH8 asserts both

SUS_ST A T# (connects to LPCPD#) and PLTRST# (connects to LRST#) at the same time

when the core logic is reset (via CF9h, PWROK, or SYS_RESET#, etc.). This is not

inconsistent with the LPC LPCPD# pr otocol.

5.4.1.12 Configuration and Intel® ICH8 Implications

LPC I/F Decoders

To allow the I/O cycles and memory mapped cycles to go to the LPC interface, the ICH8

includes several decoders. During configuration, the ICH8 must be programmed with

the same decode ranges as the peripheral. The decoders are programmed via the

Device 31:Function 0 configuration space.

Note: The ICH8 cannot accept PCI write cycles from PCI-to-PCI bridges or devices with

similar characteristics (specifically those with a “Retry Read” feature which is enabled)

to an LPC device if there is an outstanding LPC read cycle towards the same PCI device

or bridge. These cycles are not part of normal system operation, but may be

encountered as part of platform validation testing using custom test fixtures.

Intel® ICH8 Family Datasheet 129

Functional Description

Bus Master Device Mapping and START Fields

Bus Masters must have a un ique ST AR T field. In th e case of the ICH8 that supports two

LPC bus masters, it drives 0010 for the START field for grants to bus master #0

(requested via LDRQ0#) and 0011 for grants to bus master #1 (requested via

LDRQ1#.). Thus, no registers are needed to configure the START fields for a particular

bus master.

5.5 DMA Operation (D31:F0)

The ICH8 supports LPC DMA using the ICH8’s DMA controller. The DMA controller has

registers that are fixed in the lower 64 KB of I/O space. The DMA controller is

configured using registers in the PCI configuration space. These registers allow

configuration of the channels for use by LPC DMA.

The DMA circuitry incorporates the functionality of two 82C37 DMA controllers with

seven independently programmable channels (Figure 8). DMA controller 1 (DMA-1)

corresponds to DMA channels 0–3 and DMA controller 2 (DMA-2) corresponds to

channels 5–7. DMA channel 4 is used to cascade the two controllers and defaults to

cascade mode in the DMA Channel Mode (DCM) Re gister. Channel 4 is not available for

any other purpose. In addition to accepting requests from DMA slaves, the DMA

controller also responds to requests that software initiates. Software may initiate a

DMA service request by setting any bit in the DMA Channel Request Register to a 1.

Each DMA channel is hardwired to the compatible settings for DMA device size:

channels [3:0] are hardwired to 8-bit, count -by-bytes transfers, and channels [7:5] are

hardwired to 16-bit,

count-by-words (address shifted) transfers.

ICH8 provides 24-bit addressing in compliance with the ISA-Compatible specification.

Each channel includes a 16-bit ISA-Compatible Current Register which holds the 16

least-significant bits of the 24-bit address, an ISA-Compatible Page Register which

contains the eight next most significant bits of address.

The DMA controller also features refresh address generation, and auto-initialization

following a DMA termination.

5.5.1 Channel Priority

For priority resolution, the DMA consists of two logical channel groups: channels 0–3

and channels 4–7. Each group may be in either fixed or rotate mode, as determined by

the DMA Command Register.

DMA I/O slaves normally assert their DREQ line to arbitrate for DMA service. However,

a software request for DMA service can be presented through each channel's DMA

Request Register. A software request is subject to the same prioritization as any

hardware request. See the detailed register description for Request Register

programming information in Section 9.2.

Figure 8. Intel® ICH8 DMA Controller

Channel 0

Channel 1

Channel 2

Channel 3

Channel 4

Channel 5

Channel 6

Channel 7

DMA-1 DMA-2

Functional Description

130 Intel® ICH8 Family Datasheet

5.5.1.1 Fixed Priority

The initial fixed priority structure is as follows:

The fixed priority ordering is 0, 1, 2, 3, 5, 6, and 7. In this scheme, channel 0 has the

highest priority, and channel 7 has the lowest priority. Channels [3:0] of DMA-1 assume

the priority position of channel 4 in DMA -2, thus taking priority ov er channels 5, 6, and

5.5.1.2 Rotating Priority

Rotation allows for “fairness” in priority resolution. The priority chain rotates so that the

last channel serviced is assigned the lowest priority in the channel group (0–3, 5–7).

Channels 0–3 rotate as a group of 4. They are always placed between channel 5 and

channel 7 in the priority list.

Channel 5–7 rotate as part of a group of 4. That is, channels (5–7) form the first three

positions in the rotation, while channel group (0–3) com prises the fourth position in the

arbitration.

5.5.2 Address Compatibility Mode

When the DMA is operating, the addresses do not increment or decrement through the

High and Low P age Registers. Therefore, if a 24-bit address is 01FFFFh and increments,

the next address is 010000h, not 020000h. Similarly, if a 24-bit address is 020000h

and decrements, the next address is 02FFFFh, not 01FFFFh. However, when the DMA is

operating in 16-bit mode, the addresses still do not increment or decrement through

the High and Low Page Registers but the page boundary is now 128 K. Therefore, if a

24-bit address is 01FFFEh and increments, the next address is 000000h, not

0100000h. Similarly, if a 24-bit address is 020000h and decrements, the next address

is 03FFFEh, not 02FFFEh. This is compatible with the 82C37 and Page Register

implementation used in the PC-AT. This mode is set after CPURST is valid.

High priority Low priority

0, 1, 2, 3 5, 6, 7

Intel® ICH8 Family Datasheet 131

Functional Description

5.5.3 Summary of DMA Transfer Sizes

Table 47 lists each of the DMA device transfer sizes. The column labeled “Current Byte/

W ord Count R egister” indicates that the register contents represents either the number

of bytes to transfer or the number of 16-bit words to transfer. The column labeled

“Current Address Increment/Decrement” indicates the number added to or taken from

the Current Address register after each DMA transfer cycle. The DMA Channel Mode

decremented.

5.5.3.1 Address Shifting When Programmed for 16-Bit I/O Count by Words

The ICH8 maintains compatibility with the implementation of the DMA in the PC A T that

used the 82C37. The DMA shifts the addresses for transfers to/from a 16-bit device

count-by-words.

Note: The least significant bit of the Low Page Register is dropped in 16-bit shifted mode.

When programming the Current Address Register (when the DMA channel is in this

mode), the Current Address must be programmed to an even address with the address

value shifted right by one bit.

The address shifting is shown in Table 48.

NOTE: The least significant bit of the Page Register is dropped in 16-bit shifted mode.

5.5.4 Autoinitialize

By programming a bit in the DMA Channel Mode Register, a channel may be set up as

an autoinitialize channel. When a channel undergoes autoinitialization, the original

values of the Current Page, Current Address and Current Byte/Word Count Registers

are automatically restored from the Base Page, Address, and Byte/Word Count

Registers of that channel following TC. The Base Registers are loaded simultaneously

with the Current Registers by the microprocessor when the DMA channel is

programmed and remain unchanged throughout the DMA service. The mask bit is not

set when the channel is in autoinitialize. Following autoinitialize, the channel is ready to

perform another DMA service, without processor intervention, as soon as a v alid DRE Q

is detected.

Table 47. DMA Transfer Size

DMA Device Date Size And Word Count Current Byte/Word

Count Register

Current Address

Increment/

Decrement

8-Bit I/O, Count By Bytes Bytes 1

16-Bit I/O, Count By Words (Address

Shifted) Words 1

Table 48. Address Shifting in 16-Bit I/O DMA Transfers

Output

Address 8-Bit I/O Programmed

Address (Ch 0–3)

16-Bit I/O Programmed

Address (Ch 5–7)

(Shifted)

A[16:1]

A[23:17]

A[16:1]

A[23:17]

A[15:0]

A[23:17]

Functional Description

132 Intel® ICH8 Family Datasheet

5.5.5 Software Commands

There are three additional special software commands that the DMA controller can

execute. The three software commands are:

• Clear Byte Pointer Flip-Flop

•Master Clear

• Clear Mask Register

They do not depend on any specific bit pattern on the data bus.

5.6 LPC DMA

DMA on LPC is handled through the use of the LDRQ# lines from peripherals and

special encodings on LAD[3:0] from the host. Single, Demand, Verify, and Increment

modes are supported on the LPC interface. Channels 0–3 ar e 8 bi t ch annels. Channels

5–7 are 16-bit channels.

Channel 4 is reserved as a generic bus master request.

5.6.1 Asserting DMA Requests

Peripherals that need DMA service encode their requested channel number on the

LDRQ# signal. To simplify the protocol, each peripheral on the LPC I/F has its own

dedicated LDRQ# signal (they may not be shared between two separate peripherals).

The ICH8 has two LDRQ# inputs, allowing at least two devices to support DMA or bus

mastering.

LDRQ# is synchronous with LCLK (PCI clock). As shown in Figure 9, the peripheral uses

the following serial encoding sequence:

• Peripheral starts the sequence by asserting LDRQ# low (start bit). LDRQ# is high

during idle conditions.

• The next three bits contain the encoded DMA channel number (MSB first).

• The next bit (ACT) indicates whether the request for the indicated DMA channel is

active or inactive. The ACT bit is 1 (high) to indicate if it is active and 0 (low) if it is

inactive. The case where ACT is low is rare, and is only used to indicate that a

previous request for that channel is being abandoned.

• After the active/inactive indication, the LDRQ# signal must go high for at least 1

clock. After that one clock, LDRQ# signal can be brought low to the next encoding

sequence.

If another DMA channel also needs to request a transfer, another sequence can be sent

on LDRQ#. For example, if an encoded request is sent for channel 2, and then channel

3 needs a transfer before the cycle for channel 2 is run on the interface, the peripher al

can send the encoded request for channel 3. This allows multiple DMA agents behind an

I/O device to request use of the LPC interface, and the I/O device does not need to self-

arbitrate before sending the message.

Figure 9. DMA Request Assertion through LDRQ#

Start MSB LSB ACT Start

LCLK

LDRQ#

Intel® ICH8 Family Datasheet 133

Functional Description

5.6.2 Abandoning DMA Requests

DMA Requests can be deasserted in two fashions: on error conditions by sending an

LDRQ# message with the ‘ ACT’ bit set to 0, or normally through a SYNC field during the

DMA transfer. This section describes boundary conditions where the DMA request needs

to be removed prior to a data transfer.

There may be some special cases where the peripheral desires to abandon a DMA

transfer. The most likely case of this occurring is due to a floppy disk controller which

has overrun or underrun its FIFO, or software stopping a device prematurely.

In these cases, the peripheral wishes to stop further DMA activity. It may do so by

sending an LDRQ# message with the ACT bit as 0. However, since the DMA request w as

seen by the ICH8, there is no assurance that the cycle has not been granted and will

shortly run on LPC. Therefore, peripherals must take into account that a DMA cycle may

still occur. The peripheral can choose not to respond to this cycle, in which case the

host will abort it, or it can choose to complete the cy cle normally with any r andom data.

This method of DMA deassertion should be prevented whenever possible, to limit

boundary conditions both on the ICH8 and the peripheral.

5.6.3 Gener al Flow of DMA Transfers

Arbitration for DMA channels is performed through the 8237 within the host. Once the

host has won arbitration on behalf of a DMA channel assigned to LPC, it asserts

LFRAME# on the LPC I/F and begins the DMA transfer. The general flow for a basic DMA

transfer is as follows:

1. ICH8 starts transfer by asserting 0000b on LAD[3:0] with LFRAME# asserted.

2. ICH8 asserts ‘cycle type’ of DMA, direction based on DMA transfer direction.

3. ICH8 asserts channel number and, if applicable, terminal count.

4. ICH8 indicates the size of the transfer: 8 or 16 bits.

5. If a DMA read…

— The ICH8 drives the first 8 bits of data and turns the bus around.

— The peripheral acknowledges the data with a valid SYNC.

— If a 16-bit transfer, the process is repeated for the next 8 bits.

6. If a DMA write…

— The ICH8 turns the bus around and waits for data.

— The peripheral indicates data ready through SYNC and transfers the first byte.

— If a 16-bit transfer, the peripheral indicates data ready and transfers the next

byte.

7. The peripheral turns around the bus.

5.6.4 Terminal Count

Terminal count is communicated through LAD[3] on the same clock that DMA channel is

communicated on LAD[2:0]. This field is the CHANNEL field. Terminal count indicates

the last byte of transfer, based upon the size of the transfer.

For example, on an 8-bit tr ansfer size (SIZE field is 00b), if the TC bit is set, then this is

the last byte. On a 16-bit transfer (SIZE field is 01b), if the TC bit is set, then the

second byte is the last byte. The peripheral, therefore, must internalize the T C bit when

the CHANNEL field is communicated, and only signal TC when the last byte of that

transfer size has been transferred.

Functional Description

134 Intel® ICH8 Family Datasheet

5.6.5 Verify Mode

Ve rify mode is supported on the LPC interface. A verify transfer to the peripheral is

similar to a DMA write, where the peripheral is transferring data to main memory. The

indication from the host is the same as a DMA write, so the peripheral will be driving

data onto the LPC interface. However, the host will not transfer this data into main

memory.

5.6.6 DMA Request Deassertion

An end of transfer is communicated to the ICH8 through a special SYNC field

transmitted by the peripheral. An LPC device must not attempt to signal the end of a

transfer by deasserting LDREQ#. If a DMA transfer is several bytes (e.g., a transfer

from a demand mode device) the ICH8 needs to know when to deassert the DMA

request based on the data currently being transferred.

The DMA agent uses a SYNC encoding on each byte of data being transferred, which

indicates to the ICH8 whether this is the last byte of transfer or if more bytes are

requested. To indicate the last byte of transfer, the peripheral uses a SYNC value of

0000b (ready with no error), or 1010b

(ready with error). These encodings tell the ICH8 that this is the last piece of data

transferred on a DMA read (ICH8 to peripheral), or the byte that follows is the last

piece of data transferred on a DMA write (peripheral to ICH8).

When the ICH8 sees one of these two encodings, it ends the DMA transfer after this

byte and deasserts the DMA request to the 8237. Therefore, if the ICH8 indicated a 16-

bit transfer, the peripheral can end the transfer after one byte by indicating a SYNC

value of 0000b or 1010b. The ICH8 does not attempt to transfer the second byte, and

deasserts the DMA request internally.

If the peripheral indicates a 0000b or 1010b SYNC pattern on the last byte of the

indicated size, then the ICH8 only deasserts the DMA request to the 8237 since it does

not need to end the transfer.

If the peripheral wishes to keep the DMA request active, then it uses a SYNC value of

1001b (ready plus more data). This tells the 8237 that more data bytes are requested

after the current byte has been transferred, so the ICH8 keeps the DMA request activ e

to the 8237. Therefore, on an 8-bit transfer size, if the peripheral indicates a SYNC

value of 1001b to the ICH8, the data will be transferred and the DMA request will

remain active to the 8237. At a later time, the ICH8 will then come back with another

START–CYCTYPE–CHANNEL–SIZE etc. combination to initiate another transfer to the

peripheral.

The peripheral must not assume that the next START indication from the ICH8 is

another grant to the peripheral if it had indicated a SYNC value of 1001b. On a single

mode DMA device, the 8237 will re-arbitrate after every transfer. Only demand mode

DMA devices can be assured that they will receive the next START indication from the

ICH8.

Note: Indicating a 0000b or 1010b encoding on the SYNC field of an odd byte of a 16-bit

channel (first byte of a 16-bit transfer) is an error condition.

Note: The host stops the transfer on the LPC bus as indicated, fills the upper byte with

random data on DMA writes (peripher al to memory), and indicates to the 8237 that the

DMA transfer occurred, incrementing the 8237’s address and decrementing its byte

count.

Intel® ICH8 Family Datasheet 135

Functional Description

5.6.7 SYNC Field / LDRQ# Rules

Since DMA transfers on LPC are requested through an LDRQ# assertion message, and

are ended through a SYNC field during the DMA transfer, the peripheral must obey the

following rule when initiating back-to-back transfers from a DMA channel.

The peripheral must not assert another message for eight LCLKs after a deassertion is

indicated through the SYNC field. This is needed to allow the 8237, that typically runs

off a much slower internal clock, to see a message deasserted before it is re-asserted

so that it can arbitrate to the next agent.

Under default operation, the host only performs 8-bit transfers on 8-bit channels and

16-bit transfers on 16-bit channels.

The method by which this communication between host and peripher al through system

BIOS is performed is beyond the scope of this specification. Since the LPC host and LPC

peripheral are motherboard devices, no “plug-n-play” registry is required.

The peripheral must not assume that the host is able to perform transfer sizes that are

larger than the size allowed for the DMA channel, and be willing to accept a SIZE field

that is smaller than what it may currently have buffered.

To that end, it is recommended that future devices that may appear on the LPC bus,

that require higher bandwidth than 8-bit or 16-bit DMA allow, do so with a bus

mastering interface and not rely on the 8237.

5.7 8254 Timers (D31:F0)

The ICH8 contains three counters that have fixed uses. All registers and functions

associated with the 8254 timers are in the core well. The 8254 unit is clocked by a

14.31818 MHz clock.

Counter 0, System Timer

This counter functions as the system timer by controlling the state of IRQ0 and is

typically programmed for Mode 3 operation. The counter produces a square wave with

a period equal to the product of the counter period (838 ns) and the initial count value.

The counter loads the initial count value 1 counter period after software writes the

count value to the counter I/O address. The counter initially asserts IRQ0 and

decrements the count value by two each counter period. The counter negates IRQ0

when the count value reaches 0. It then reloads the initial count value and again

decrements the initial count value by two each counter period. The counter then

asserts IRQ0 when the count value reaches 0, reloads the initial count value, and

repeats the cycle, alternately asserting and negating IRQ0.

Counter 1, Refresh Req uest Signal

This counter provides the refresh request signal and is typically programmed for Mode

2 operation and only impacts the period of the REF_TOGGLE bit in Port 61. The initial

count value is loaded one counter period after being written to the counter I/O address.

The REF_TOGGLE bit will have a square wa ve behavior (alternate between 0 and 1) and

will toggle at a rate based on the value in the counter. Programming the counter to

anything other than Mode 2 will result in undefined behavior for the REF_TOGGLE bit.

Counter 2, Speaker Tone

This counter provides the speaker tone and is typically programmed for Mode 3

operation. The counter provides a speaker frequency equal to the counter clock

frequency (1.193 MHz) divided by the initial count value. The speaker must be enabled

by a write to port 061h (see NMI Status and Control ports).

Functional Description

136 Intel® ICH8 Family Datasheet

5.7.1 Timer Programming

The counter/timers are programmed in the following fashion:

1. Write a control word to select a counter.

2. Write an initial count for that counter.

3. Load the least and/or most significant bytes (as required by Control W ord bits 5, 4)

of the 16-bit counter.

4. R epeat with other counters.

Only two conventions need to be observed when programming the counters. First, for

each counter, the control word must be written before the initial count is written.

Second, the initial count must follow the count format specified in the control word

(least significant byte only, most significant byte only, or least significant byte and then

most significant byte).

A new initial count may be written to a counter at any time without affecting the

counter's programmed mode. Counting is af fected as described in the mode definitions.

The new count must follow the programmed count format.

If a counter is programmed to read/write two-byte counts, the following precaution

applies: A program must not tr ansfer control between writing the first and second byte

to another routine which also writes into that same counter. Otherwise, the counter will

be loaded with an incorrect count.

The Control Word Register at port 43h controls the operation of all three counters.

Several commands are available:

•Control Word Command. Specifies which counter to read or write, the operating

mode, and the count format (binary or BCD).

•Counter Latch Command. Latches the current count so that it can be read by the

system. The countdown process continues.

•Read Back Command. Reads the count value, programmed mode, the current

state of the OUT pins, and the state of the Null Count Flag of the selected counter.

Table 49 lists the six operating modes for the interval counters.

Intel® ICH8 Family Datasheet 137

Functional Description

5.7.2 Reading from the Interval Timer

It is often desirable to read the value of a counter without disturbing the count in

progress. There are three methods for reading the counters: a simple read operation,

counter Latch command, and the Read-Back command. Each is explained below.

With the simple read and counter latch command methods, the count must be read

according to the programmed format; specifically, if the counter is programmed for two

byte counts, two bytes must be read. The two bytes do not have to be read one right

after the other. Read, write, or programming operations for other counters may be

inserted between them.

5.7.2.1 Simple Read

The first method is to perform a simple read operation. The counter is selected through

port 40h (counter 0), 41h (counter 1), or 42h (counter 2).

Note: Performing a direct read from the counter does not return a determinate value,

because the counting process is asynchronous to read oper ations. However, in the case

of counter 2, the count can be stopped by writing to the GATE bit in port 61h.

5.7.2.2 Counter Latch Command

The Counter Latch command, written to port 43h, latches the count of a specific

counter at the time the command is received. This command is used to ensure that the

count read from the counter is accurate, particularly when reading a two-byte count.

The count value is then read from each counter’ s Count register as was programmed by

the Control register.

The count is held in the latch until it is read or the counter is reprogrammed. The count

is then unlatched. This allows reading the contents of the counters on the fly without

affecting counting in progress. Multiple Counter Latch Commands may be used to latch

more than one counter. Counter Latch commands do not affect the programmed mode

of the counter in any way.

Table 49. Counter Operating Modes

Mode Function Description

0 Out signal on end of count (=0) Output is 0. When count goes to 0, output goes to

1 and stays at 1 until counter is reprogrammed.

1 Hardware retriggerable one-shot Output is 0. When count goes to 0, output goes to

1 for one clock time.

2Rate generator (divide by n

counter) Output is 1. Output goes to 0 for one clock time,

then back to 1 and counter is reloaded.

3Square wave output

Output is 1. Output goes to 0 when counter rolls

over, and counter is reloaded. Output goes to 1

when counter rolls over, and counter is reloaded,

etc.

4 Software triggered strobe Output is 1. Output goes to 0 when count expires

for one clock time.

5 Hardware triggered strobe Output is 1. Output goes to 0 when count expires

for one clock time.

Functional Description

138 Intel® ICH8 Family Datasheet

If a Counter is latched and then, some time later, latched again before the count is

read, the second Counter Latch command is ignored. The count read is the count at the

time the first Counter Latch command was issued.

5.7.2.3 Read Back Command

The Read Back command, written to port 43h, latches the count value, programmed

mode, and current states of the OUT pin and Null Count flag of the selected counter or

counters. The value of the counter and its status may then be read by I/O access to the

counter address.

The Read Back command may be used to latch multiple counter outputs at one time.

This single command is functionally equiv alent to sever al counter latch commands, one

for each counter latched. Each counter's latched count is held until it is read or

reprogrammed. Once read, a counter is unlatched. The other counters remain latched

until they are read. If multiple count Read Back commands are issued to the same

counter without reading the count, all but the first are ignored.

The Read Back command may additionally be used to latch status information of

selected counters. The status of a counter is accessed by a read from that counter's I/

O port address. If multiple counter status latch operations are performed without

reading the status, all but the first are ignored.

Both count and status of the selected counters may be latched simultaneously. This is

functionally the same as issuing two consecutive, separate Read Back commands. If

multiple count and/or status Read Back commands are issued to the same counters

without any intervening reads, all but the first are ignored.

If both count and status of a counter are latched, the first read operation from that

counter returns the latched status, regardless of which was latched first. The next one

or two reads, depending on whether the counter is programmed for one or two type

counts, returns the latched count. Subsequent reads return unlatched count.

Intel® ICH8 Family Datasheet 139

Functional Description

5.8 8259 Interrupt Controllers (PIC) (D31:F0)

The ICH8 incorporates the functionality of two 8259 interrupt controllers that provide

system interrupts for the ISA compatible interrupts. These interrupts are: system

timer, keyboard controller, serial ports, parallel ports, floppy disk, IDE (Mobile only),

mouse, and DMA channels. In addition, this interrupt controller can support the PCI

based interrupts, by mapping the PCI interrupt onto the compatible ISA interrupt line.

Each 8259 core supports eight interrupts, numbered 0–7. Table 50 shows how the

cores are connected.

The ICH8 cascades the slave controller onto the master controller through master

controller interrupt input 2. This means there are only 15 possible interrup t s for the

ICH8 PIC.

Interrupts can individually be programmed to be edge or level, except for IRQ0, IRQ2,

IRQ8#, and IRQ13.

Note: Active-low interrupt sources (e.g., the PIRQ#s) are inverted inside the ICH8. In the

following descriptions of the 8259s, the interrupt levels are in reference to the signals

at the internal interface of the 8259s, after the required inversions have occurred.

Therefore, the term “high” indicates “active,” which means “low” on an originating

PIRQ#.

Table 50. Interrupt Controlle r C ore Connections

8259 8259

Input Typical Interrupt

Source Connected Pin / Function

Master

0 Inte r nal Internal Timer / Counter 0 output / HPET #0

1 Keyboard IRQ1 via SERIRQ

2 Internal Slave controller INTR output

3 Serial Port A IRQ3 via SERIRQ, PIRQ#

4 Serial Port B IRQ4 via SERIRQ, PIRQ#

5 Parallel Port / Generic IRQ5 via SERIRQ, PIRQ#

6 Floppy Disk IRQ6 via SERIRQ, PIRQ#

7 Parallel Port / Generic IRQ7 via SERIRQ, PIRQ#

0Internal Real Time

Clock Internal RTC / HPET #1

1 Gene ric IRQ9 via SERIRQ, SCI, TCO, or PIRQ#

2 G eneric IRQ10 via SERIRQ, SCI, TCO, or PIRQ#

Slave 3 Generic IRQ11 via SERIRQ, SCI, TCO, or PIRQ#

4 P S/2 Mouse IRQ12 via SERI RQ, SCI, TCO, or PIRQ#

5Internal State Machine output based on processor FERR#

assertion. May optionally be used for SCI or TCO

interrupt if FERR# not needed.

6SATA,

IDE cable

(Mobile Only)

SATA Primary (legacy mode), or SERIRQ, or

PIRQ#.

Mobile Only: IDEIRQ (legacy mode, non-combined

or combined mapped as primary).

7SATA,

IDE cable

(Mobile Only)

SATA Secondary (legacy mode), or SERIRQ, or

PIRQ#.

Mobile Only: ID EIRQ (legacy mode — combined,

mapped as secondary).

Functional Description

140 Intel® ICH8 Family Datasheet

5.8.1 Interrupt Handling

5.8.1.1 Generating Interrupts

The PIC interrupt sequence involves three bits, from the IRR, ISR, and IMR, for each

interrupt level. These bits are used to determine the interrupt vector returned, and

status of any other pending interrupts. Table 51 defines the IRR, ISR, and IMR.

5.8.1.2 Acknowledging Interrupts

The processor generates an interrupt acknowledge cycle that is translated by the host

bridge into a PCI Interrupt Acknowledge Cycle to the ICH8. The PIC translates this

command into two internal INT A# pulses expected by the 8259 cores. The PIC uses the

first internal INT A# pulse to freeze the state of the in terrupts for priority resolution. On

the second INTA# pulse, the master or slave sends the interrupt vector to the

processor with the acknowledged interrupt code. This code is based upon bits [7:3] of

the corresponding ICW2 register, combined with three bits representing the interrupt

within that controller.

Table 51. Interrupt Status Registers

Bit Description

IRR Interrupt Request Register. This bit is set on a low to high transition of the interrupt

line in edge mode, and by an active high level in level mode. This bit is set whether or

not the interrupt is masked. However, a masked interrupt will not generate INTR.

ISR Interrupt Service Register. This bit is set, and the corresponding IRR bit cleared,

when an interrupt acknowledge cycle is seen, and the vector returned is for that

interrupt.

IMR Interrupt Mask Register. This bit determines whether an interrupt is masked.

Masked interrupts will not generate INTR.

Table 52. Content of Interrupt Vector Byte

Master, Slave Interrupt Bits [7:3] Bits [2:0]

IRQ7,15

ICW2[7:3]

111

IRQ6,14 110

IRQ5,13 101

IRQ4,12 100

IRQ3,11 011

IRQ2,10 010

IRQ1,9 001

IRQ0,8 000

Intel® ICH8 Family Datasheet 141

Functional Description

5.8.1.3 Hardware/Software Interrupt Sequence

1. One or more of the Interrupt Request lines (IRQ) are raised high in edge mode, or

seen high in level mode, setting the corresponding IRR bit.

2. The PIC sends INTR active to the processor if an asserted interrupt is not masked.

3. The processor acknowledges the INTR and responds with an interrupt acknowledge

cycle. The cycle is translated into a PCI interru pt acknowledge cycle by the host

bridge. This command is broadcast over PCI by the ICH8.

4. Upon observing its own interrupt acknowledge cycle on PCI, the ICH8 converts it

into the two cycles that the internal 8259 pair can respond to. Each cycle appears

as an interrupt acknowledge pulse on the internal INTA# pin of the cascaded

interrupt controllers.

5. Upon receiving the first internally generated INTA# pulse, the highest priority ISR

bit is set and the corresponding IRR bit is reset. On the trailing edge of the first

pulse, a slave identification code is broadcast by the master to the slave on a

private, internal three bit wide bus. The slave controller uses these bits to

determine if it must respond with an interrupt vector during the second INTA#

pulse.

6. Upon receiving the second internally generated INTA# pulse, the PIC returns the

interrupt vector. If no interrupt request is present because the request was too

short in duration, the PIC returns vector 7 from the master controller.

7. This completes the interrupt cycle. In AEOI mode the ISR bit is reset at the end of

the second INTA# pulse. Otherwise, the ISR bit remains set until an appropriate

EOI command is issued at the end of the interrupt subroutine.

5.8.2 Initializati on Command Words (ICWx)

Before operation can begin, each 8259 must be initialized. In the ICH8, this is a four

byte sequence. The four initialization command words are referred to by their

acronyms: ICW1, ICW2, ICW3, and ICW4.

The base address for each 8259 initialization command word is a fixed location in the

I/O memory space: 20h for the master controller, and A0h for the slave controller.

5.8.2.1 ICW1

An I/O write to the master or sla ve contro ller base address with data bit 4 equ al to 1 is

interpreted as a write to ICW1. Upon sensing this write, the ICH8 PIC expects three

more byte writes to 21h for the master controller, or A1h for the slave controller, to

complete the ICW sequence.

A write to ICW1 starts the initialization sequence during which the following

automatically occur:

1. Following initialization, an interrupt request (IRQ) input must make a low-to-high

transition to generate an interrupt.

2. The Interrupt Mask Register is cleared.

3. IRQ7 input is assigned priority 7.

4. The slave mode address is set to 7.

5. Special mask mode is cleared and Status Read is set to IRR.

Functional Description

142 Intel® ICH8 Family Datasheet

5.8.2.2 ICW2

The second write in the sequence (ICW2) is programmed to provide bits [7:3] of the

interrupt vector that will be released during an interrupt acknowledge. A different base

is selected for each interrupt controller.

5.8.2.3 ICW3

The third write in the sequence (ICW3) has a different meaning for each controller.

• For the master controller, ICW3 is used to indicate which IRQ input line is used to

cascade the slave controller. Within the ICH8, IRQ2 is used. Therefore, bit 2 of

ICW3 on the master controller is set to a 1, and the other bits are set to 0s.

• For the slave controller, ICW3 is the slave identification code used during an

interrupt acknowledge cycle. On interrupt acknowledge cycles, the master

controller broadcasts a code to the slave controller if the cascaded interrupt won

arbitration on the master controller. The slave controller compares this

identification code to the value stored in its ICW3, and if it matches, the slave

controller assumes responsibility for broadcasting the interrupt vector.

5.8.2.4 ICW4

The final write in the sequence (ICW4) must be programmed for both controllers. At

the very least, bit 0 must be set to a 1 to indicate that the controllers are operating in

an Intel Architecture-based system.

5.8.3 Operation Command Words (OCW)

These command words reprogram the Interrupt controller to operate in various

interrupt modes.

• OCW1 masks and unmasks interrupt lines.

• OCW2 controls the rotation of interrupt priorities when in rotating priority mode,

and controls the EOI function.

• OCW3 is sets up ISR/IRR reads, enables/disables the special mask mode (SMM),

and enables/disables polled interrupt mode.

Intel® ICH8 Family Datasheet 143

Functional Description

5.8.4 Modes of Operation

5.8.4.1 Fully Nested Mode

In this mode, interrupt requests are ordered in priority from 0 through 7, with 0 being

the highest. When an interrupt is acknowledged, the highest priority request is

determined and its vector placed on the bus. Additionally, the ISR for the interrupt is

set. This ISR bit remains set until: the processor issues an EOI command immediately

before returning from the service routine; or if in AEOI mode, on the trailing edge of

the second INTA#. While the ISR bit is set, all further interrupts of the same or lower

priority are inhibited, while higher levels generate another interrupt. Interrupt priorities

can be changed in the rotating priority mode.

5.8.4.2 Special Fully-Nested Mode

This mode is used in the case of a system where cascading is used, and the priority has

to be conserved within each slave. In this case, the special fully-nested mode is

programmed to the master controller. This mode is similar to the fully-nested mode

with the following exceptions:

• When an interrupt request from a certain slave is in service, this slav e is not locked

out from the master's priority logic and further interr upt requests from higher

priority interrupts within the slave are recognized by the master and initiate

interrupts to the processor. In the normal-nested mode, a slave is masked out

when its request is in service.

• When exiting the Interrupt Service routine, software has to check whether the

interrupt serviced was the only one from that slave. This is done by sending a Non-

Specific EOI command to the slave and then reading its ISR. If it is 0, a non-

specific EOI can also be sent to the master.

5.8.4.3 Automatic Rotation Mode (Equal Priority Devices)

In some applications, there are a number of interrupting devices of equal priority.

Automatic rotation mode provides for a sequential 8-way rotation. In this mode, a

device receives the lowest priority after being serviced. In the worst case, a device

requesting an interrupt has to wait until each of seven other devices are serviced at

most once.

There are two ways to accomplish automatic rotation using OCW2; the Rotation on

Non-Specific EOI Command (R=1, SL=0, EOI=1) and the rotate in automatic EOI mode

which is set by (R=1, SL=0, EOI=0).

5.8.4.4 Specific Rotation Mode (Specific Priority)

Software can change interrupt priorities by programmin g the bo ttom priorit y. For

example, if IRQ5 is programmed as the bottom priority device, then IRQ6 is the highest

priority device. The Set Priority Command is issued in OCW2 to accomplish this, where:

R=1, SL=1, and LO–L2 is the binary priority level code of the bottom priority device.

In this mode, internal status is updated by software control during OCW2. However, it

is independent of the EOI command. Priority changes can be executed during an EOI

command by using the Rotate on Specific EOI Command in OCW2 (R=1, SL=1, EOI=1

and LO–L2=IRQ level to receive bottom priority.

Functional Description

144 Intel® ICH8 Family Datasheet

5.8.4.5 Poll Mode

Poll mode can be used to conserve space in the interrupt vector table. Multiple

interrupts that can be serviced by one inter rupt serv ice routine do not need separate

vectors if the service routine uses the poll command. Poll mode can also be used to

expand the number of interrupts. The polling interrupt service routine can call the

appropriate service routine, instead of providing the interrupt vectors in the vector

table. In this mode, the INTR output is not used and the microprocessor internal

Interrupt Enable flip-flop is reset, disabling its interrupt input. Service to devices is

achieved by software using a Poll command.

The Poll command is issued by setting P=1 in OCW3. The PIC treats its next I/O read as

an interrupt acknowledge, sets the appropriate ISR bit if there is a request, and reads

the priority level. Interrupts are frozen from the OCW3 write to the I/O read. The byte

returned during the I/O read contains a 1 in bit 7 if there is an interrupt, and the binary

code of the highest priority level in bits 2:0.

5.8.4.6 Cascade Mode

The PIC in the ICH8 has one master 8259 and one slave 8259 cascaded onto the

master through IRQ2. This configuration can handle up to 15 separate priority levels.

The master controls the slaves through a three bit internal bus. In the ICH8, when the

master drives 010b on this bus, the slave controller takes responsibility for returning

the interrupt vector. An EOI command must be issued twice: once for the master and

once for the slave.

5.8.4.7 Edge and Level Triggered Mode

In ISA systems this mode is programmed using bit 3 in ICW1, which sets level or edge

for the entire controller. In the ICH8, this bit is disabled and a new register for edge and

level triggered mode selection, per interrupt input, is included. This is the Edge/Level

control Registers ELCR1 and ELCR2.

If an ELCR bit is 0, an interrupt request will be recognized by a low-to-high transition

on the corresponding IRQ input. The IRQ input can remain high without generating

another interrupt. If an ELCR bit is 1, an interrupt request will be recognized by a high

level on the corresponding IRQ input and there is no need for an edge detection. The

interrupt request must be removed before the EOI command is issued to prevent a

second interrupt from occurring.

In both the edge and level triggered modes, the IRQ inputs must remain active until

after the falling edge of the first internal INTA#. If the IRQ input goes inactive before

this time, a default IRQ7 vector is returned.

5.8.4.8 End of Interrupt (EOI) Operations

An EOI can occur in one of two fashions: by a command word write issued to the PIC

before returning from a service routine, the EOI command; or automatically when AEOI

bit in ICW4 is set to 1.

5.8.4.9 Normal End of Interrupt

In normal EOI, software writes an EOI command before leaving the interrupt service

routine to mark the interrupt as completed. There are two forms of EOI commands:

Specific and Non-Specific. When a Non-Specific EOI command is issued, the PIC clears

the highest ISR bit of those that are set to 1. Non-Specific EOI is the normal mode of

operation of the PIC within the ICH8, as the interrupt being serviced currently is the

interrupt entered with the interrupt acknowledge. When the PIC is operated in modes

that preserve the fully nested structure, software can determine which ISR bit to clear

Intel® ICH8 Family Datasheet 145

Functional Description

by issuing a Specific EOI. An ISR bit that is masked is not cleared by a Non-Specific EOI

if the PIC is in the special mask mode. An EOI command must be issued for both the

master and slave controller.

5.8.4.10 Automatic End of Interrupt Mode

In this mode, the PIC automatically performs a Non-Specific EOI operation at the

trailing edge of the last interrupt acknowledge pulse. From a system standpoint, this

mode should be used only when a nested mu lti-level interrupt structure is not required

within a single PIC. The AEOI mode can only be used in the master controller and not

the slave controller.

5.8.5 Masking Interrupts

5.8.5.1 Masking on an Individual Interrupt Request

Each interrupt request can be masked individually by the Interrupt Mask Register

(IMR). This register is programmed through OCW1. Each bit in the IMR masks one

interrupt channel. Masking IRQ2 on the master controller masks all requests for service

from the slave controller.

5.8.5.2 Special Mask Mode

Some applications may require an interrupt service routine to dynamically alter the

system priority structure during its execution under softw are control. For example, the

routine may wish to inhibit lower priority requests for a portion of its execution but

enable some of them for another portion.

The special mask mode enables all interrupts not masked by a bit set in the Mask

issuing an EOI to clear the ISR bit, the interrupt controller inhibits all lower priority

requests. In the special mask mode, any interrupts may be selectively enabled by

loading the Mask Register with the appropriate pattern. The special mask mode is set

by OCW3 where: SSMM=1, SMM=1, and cleared where SSMM=1, SMM=0.

5.8.6 Steering PCI Interr upts

The ICH8 can be programmed to allow PIRQA#-PIRQH# to be internally routed to

interrupts 3–7, 9–12, 14, or 15. The assignment is programmable through the through

the PIRQx Route Control registers, located at 60–63h and 68–6Bh in Device

31:Function 0. One or more PIRQx# lines can be routed to the same IRQx input. If

interrupt steering is not required, the Route registers can be programmed to disable

steering.

The PIRQx# lines are defined as active low, level sensitive to allow multiple interrupts

on a PCI board to share a single line across the connector. When a PIRQx# is routed to

specified IRQ line, software must change the IRQ's corresponding ELCR bit to level

sensitive mode. The ICH8 internally in verts the PIRQx# line to send an active high level

to the PIC. When a PCI interrupt is routed onto the PIC, the selected IRQ can no longer

be used by an active high device (through SERIRQ). However, active low interrupts can

share their interrupt with PCI interrupts.

Internal sources of the PIRQs, including SCI and TCO interrupts, cause the external

PIRQ to be asserted. The ICH8 receives the PIRQ input, like all of the other external

sources, and routes it accordingly.

Functional Description

146 Intel® ICH8 Family Datasheet

5.9 Advanced Programmable Interrupt Controller

(APIC) (D31:F0)

In addition to the standard ISA-compatible PIC described in the previous chapter, the

ICH8 incorporates the APIC. While the standard interrupt controller is intended for use

in a uni-processor system, APIC can be used in either a uni-processor or multi-

processor system.

5.9.1 Interrupt Handling

The I/O APIC handles interrupts very differently than the 8259. Briefly, these

differences are:

•Method of Interrupt Transmission. The I/O APIC transmits interrupts through

memory writes on the normal datapath to the processor, and interrupts are handled

without the need for the processor to run an interrupt acknowledge cycle.

•Interrupt Priority. The priority of interrupts in the I/O APIC is independent of the

interrupt number. For example, interrupt 10 can be given a higher priority than

interrupt 3.

•More Interrupts. The I/O APIC in the ICH8 supports a total of 24 interrupts.

•Multiple Interrup t Contro llers. The I/O APIC architecture allows for multiple I/O

APIC devices in the system with their own interrupt vectors.

5.9.2 Interrupt Mapping

The I/O APIC within the ICH8 supports 24 APIC interrupts. Each interrupt has its own

unique vector assigned by software. The interrupt vectors are mapped as follows, and

match “Config 6” of the Multi-Processor Specification.

Table 53. APIC Inte rr up t Mapp in g (She et 1 of 2)

IRQ # Via

SERIRQ Direct

from Pin Via PCI

Message Internal Modules

0 No No No Cascade from 8259 #1

1Yes No Yes

2 No No No 8254 Counter 0, HPET #0 (legacy mode)

3Yes No Yes

4Yes No Yes

5Yes No Yes

6Yes No Yes

7Yes No Yes

8NoNoNoRTC, HPET #1 (legacy mode)

9 Yes No Yes Option for SCI, TCO

10 Yes No Yes Option for SCI, TCO

11 Yes No Yes HPET #2, Option for SCI, TCO

12 Yes No Yes

13 No No No FERR# logic

14 Yes Yes1Yes Mobile Only: IDEIRQ (legacy mode, non-

combined or combined mapped as primary),

SATA Primary (legacy mode)

Intel® ICH8 Family Datasheet 147

Functional Description

NOTES:

1. Mobile Only: IDEIRQ can only be driven directly from the pin when in legacy IDE mode.

2. When programming the polarity of internal interrupt sources on the APIC, interrupts 0

through 15 receive active-high internal interrupt sources, while interrupts 16 through 23

receive acti ve-low internal interrupt sources.

3. If IRQ 11 is used for HPET #2, software should ensure IRQ 11 is not shared with any other

devices to assure the proper operation of HPET #2. ICH8 hardware does not prevent

sharing of IRQ 11.

5.9.3 PCI / PCI Express* Message-Based Interrupts

When external devices through PCI / PCI Express wish to generate an interrupt, they

will send the message defined in the PCI Express* Base Specification, Revision 1.0a for

generating INT A# - INTD#. These will be translated internal assertions/de-assertions of

INTA# - INTD#.

5.9.4 Front Side Bus Interrupt Delivery

For processors that support Front Side Bus (FSB) interrupt delivery, the ICH8 requires

that the I/O APIC deliver interrupt messages to the processor in a parallel manner,

rather than using the I/O APIC serial scheme.

This is done by the ICH8 writing (via DMI) to a memory location that is snooped by the

processor(s). The processor(s) snoop the cycle to know which interrupt goes active.

The following sequence is used:

1. When the ICH8 detects an interrupt event (active edge for edge-triggered mode or

a change for level-triggered mode), it sets or resets the internal IRR bit associated

with that interrupt.

2. Internally, the ICH8 requests to use the bus in a way that automatically flushes

upstream buffers. This can be internally implemented similar to a DMA device

request.

3. The ICH8 then delivers the message by performing a write cycle to the appropriate

address with the appropriate data. The address and data formats are described

below in Section 5.9.4.4.

Note: FSB Interrupt Delivery compatibility with processor clock control depends on the

processor, not the ICH8.

15 Yes Yes Yes Mobile Only: IDEIRQ (legacy mode — combined,

mapped as secondary), SATA Secondary (legacy

mode)

16 PIRQA# PIRQA#

Yes Internal devices are routable; see Section 7.1.52

though Section 7.1.58.

17 PIRQB# PIRQB#

18 PIRQC# PIRQC#

19 PIRQD# PIRQD#

20 N/A PIRQE#

Yes Option for SCI, TCO, HPET #0,1,2. Other internal

devices are routable; see Section 7.1.52 through

Section 7.1.58.

21 N/A PIRQF#

22 N/A PIRQG#

23 N/A PIRQH#

Table 53. APIC Interrupt Mapping (Sheet 2 of 2)

IRQ # Via

SERIRQ Direct

from Pin Via PCI

Message Internal Modules

Functional Description

148 Intel® ICH8 Family Datasheet

5.9.4.1 Edge-Triggered Operation

In this case, the “Assert Message” is sent when there is an inactive-to-active edge on

the interrupt.

5.9.4.2 Level-Triggered Operation

In this case, the “Assert Message” is sent when there is an inactive-to-active edge on

the interrupt. If after the EOI the interrupt is still active, then another “ Assert Message”

is sent to indicate that the interrupt is still active.

5.9.4.3 Registers Associated with Front Side Bus Interrupt Delivery

Capabilities Indication: The capability to support Front Side Bus interrupt delivery is

indicated via ACPI configuration techniques. This involves the BIOS creating a data

structure that gets reported to the ACPI configuration software.

5.9.4.4 Interrupt Message Format

The ICH8 writes the message to PCI (and to the Host controller) as a 32-bit memory

write cycle. It uses the formats shown in Table 54 and Table 55 for the address and

data.

The local APIC (in the processor) has a delivery mode option to interpret Front Side Bus

messages as a SMI in which case the processor treats the incoming interrupt as a SMI

instead of as an interrupt. This does not mean that the ICH8 has any wa y to have a SMI

source from ICH8 power management logic cause the I/O APIC to send an SMI

message (there is no way to do this). The ICH8’s I/O APIC can only send interrupts due

to interrupts which do not include SMI, NMI or INIT. This means that in IA32/IA64

based platforms, Front Side Bus interrupt message format delivery modes 010

(SMI/PMI), 100 (NMI), and 101 (INIT) as indicated in this section, must not be used

and is not supported. Only the hardware pin connection is supported by ICH8.

Table 54. Interrupt Message Address Format

Bit Description

31:20 Will always be FEEh

19:12 Destination ID: T his is the same as bits 63:56 of the I /O Redirect ion Table entry for

the interrupt associated with this message.

11:4 Extended Destination ID: This is the same as bits 55:48 of the I/O Redirection

Table entry for the interrupt associated with this message.

Redirection Hint: This bit is used by the proc essor host bridge to allow the interrupt

message to be redirected.

0 = The message will be delivered to the agent (processor) listed in bits 19:12.

1 = The message will be delivered to an agent with a lower interrupt priority This can

be derived from bits 10:8 in the Data Field (see below).

The Redirection Hint bit will be a 1 if bits 10:8 in the delivery mode field associated

with corresponding interrupt are encoded as 001 (Lowest Priority). Otherwise, the

Redirection Hint bit will be 0

Destination Mode: This bit is used only the Redirection Hint bit is set to 1. If the

Redirection Hint bit and the Destination Mode bit are both set to 1, then the logical

destination mode is used, and the redirection is l imited on ly to t hose proc essors that

are part of the logical group as based on the logical ID.

1:0 Will always be 00.

Intel® ICH8 Family Datasheet 149

Functional Description

5.10 Serial Interrupt (D31:F0)

The ICH8 supports a serial IRQ scheme. This allows a single signal to be used to report

interrupt requests. The signal used to transmit this information is shared between the

host, the ICH8, and all peripherals that support serial interrupts. The signal line,

SERIRQ, is synchronous to PCI clock, and follows the sustained tri-state protocol that is

used by all PCI signals. This means that if a device has driven SERIRQ low, it will first

drive it high synchronous to PCI clock and release it the following PCI clock. The serial

IRQ protocol defines this sustained tri-state signaling in the following fashion:

•S – Sample Phase. Signal driven low

•R – Recovery Phase. Signal driven high

•T – Turn-around Phase. Signal released

The ICH8 supports a message for 21 serial interrupts. These represent the 15 ISA

interrupts (IRQ0–1, 2–15), the four PCI interrupts, and the control signals SMI# and

IOCHK#. The serial IRQ protocol does not support the additional APIC interrupts

(20–23).

Note: Mobile Only: When the IDE controller is enabled or the SAT A controller is configured for

legacy IDE mode, IRQ14 and IRQ15 are expected to behave as ISA legacy interrupts,

which cannot be shared (i.e., through the Serial Interrupt pin). If IRQ14 and IRQ15 are

shared with Serial Interrupt pin, then abnormal system behavior may occur. For

example, IRQ14/15 may not be detected by ICH8's interrupt controller.

Notes on IRQ14 and IRQ15

IRQ14 and IRQ15 are special interrupts, used by the PATA or SATA controllers.

When in a legacy or Native mode, IRQ14 and IRQ15 are not accepted from the serial

stream and instead come from these controllers.

Table 55. Interrupt Message Data Format

Bit Description

31:16 Will always be 0000h.

15 Trigger Mode: 1 = Level, 0 = Edge. Same as the corresponding bit in the I/O

Redirection Table for that interrupt.

14 Delivery Status: 1 = Assert, 0 = Deassert. Only Assert messages are sent. This bit is

always 1.

13:12 Will always be 00

11 Destination Mode: 1 = Logical. 0 = Physical. Same as the corresponding bit in the I/

O Redirection Table for that interrupt.

10:8

Delivery Mode: Same as the corresponding bits in the I/O Redirection Table for that

interrupt.

000 = Fixed 100 = NMI 010 = SMI/PMI 110 = Reserved

001 = Lowest Priority 101 = INIT 011 = Reserved 111 = ExtINT

7:0 Vector: Same as the corresponding bits in the I/O Redirection Table for that interrupt.

Functional Description

150 Intel® ICH8 Family Datasheet

5.10.1 Start Frame

The serial IRQ protocol has two modes of operation which affect the start frame. These

two modes are: Continuous, where the ICH8 is solely responsible for generating the

start frame; and Quiet, where a serial IRQ peripheral is responsible for beginning the

start frame.

The mode that must first be entered when enabling the serial IRQ protocol is

continuous mode. In this mode, the ICH8 asserts the start frame. This start fr ame is 4,

6, or 8 PCI clocks wide based upon the Serial IRQ Control Register, bits 1:0 at 64h in

Device 31:Function 0 configuration space. This is a polling mode.

When the serial IRQ stream enters quiet mode (signaled in the Stop Frame), the

SERIRQ line remains inactive and pulled up between the Stop and Start Frame until a

peripheral drives the SERIRQ signal low . The ICH8 senses the line low and continues to

drive it low for the remainder of the Start Frame. Since the first PCI clock of the start

frame was driven by the peripheral in this mode, the ICH8 drives the SERIRQ line low

for 1 PCI clock less than in continuous mode. This mode of oper ation allows for a quiet,

and therefore lower power, operation.

5.10.2 Data Frames

Once the Start frame has been initiated, all of the SERIRQ peripherals must start

counting frames based on the rising edge of SERIRQ. Each of the IRQ/DATA frames has

exactly 3 phases of 1 clock each:

•Sample Phase. During this phase, the SERIRQ device drives SERIRQ low if the

corresponding interrupt signal is low. If the corresponding interrupt is high, then

the SERIRQ devices tri-state the SERIRQ signal. The SERIRQ line remains high due

to pull-up resistors (there is no internal pull-up resistor on this signal, an external

pull-up resistor is required). A low level during the IRQ0–1 and IRQ2–15 frames

indicates that an active-high ISA interrupt is not being requested, but a low level

during the PCI INT[A:D], SMI#, and IOCHK# frame indicates that an active-low

interrupt is being requested.

•Recovery Phase. During this phase, the device drives the SERIRQ line high if in

the Sample Phase it was driven low. If it was not driven in the sample phase, it is

tri-stated in this phase.

•Turn-around Phase. The device tri-states the SERIRQ line

5.10.3 Stop Frame

After all data frames, a Stop Frame is driven by the ICH8. The SERIRQ signal is driven

low by the ICH8 for 2 or 3 PCI clocks. The number of clocks is determined by the

SERIRQ configuration register. The number of clocks determines the next mode:

Table 56. Stop Frame Explanation

Stop Frame Width Next Mode

2 PCI clocks Quiet Mode. Any SERIRQ device may initiate a Start Frame

3 PCI clocks Continuous Mode. Only the host (Intel® ICH8) may initiate a Start

Frame

Intel® ICH8 Family Datasheet 151

Functional Description

5.10.4 Specific Interrupts Not Supported via SERIRQ

There are three interrupts seen through the serial stream that are not supported by the

ICH8. These interrupts are generated internally, and are not sharable with other

devices within the system. These interrupts are:

• IRQ0. Heartbeat interrupt generated off of the internal 8254 counter 0.

• IRQ8#. RTC interrupt can only be generated internally.

• IRQ13. Floating point error interrupt generated off of the processor assertion of

FERR#.

The ICH8 ignores the state of these interrupts in the serial stream, and does not adjust

their level based on the level seen in the serial stream.

5.10.5 Data Frame Format

Table 57 shows the format of the data frames. F or the PCI interrupts (A–D), the output

from the ICH8 is AND’d with the PCI input signal. This way, the interrupt can be

signaled via both the PCI interrupt input signal and via the SERIRQ signal (they are

shared).

Table 57. Data Frame Format

Data

Frame # Interrupt Clocks Past

Start

Frame Comment

1IRQ0 2

Ignored. IRQ0 can only be generated via the internal

8524

2IRQ1 5

3 SMI# 8 Causes SMI# if low. Will set the SERIRQ_SMI_STS bit.

4IRQ3 11

5IRQ4 14

6IRQ5 17

7IRQ6 20

8IRQ7 23

9IRQ8 26Ignored. IRQ8# can only be generated internally.

10 IRQ9 29

11 IRQ10 32

12 IRQ11 35

13 IRQ12 38

14 IRQ13 41 Ignored. IRQ13 can only be generated from FERR#

15 IRQ14 44 Not attached to PATA (Mobile Only) or SATA logic

16 IRQ15 47 Not attached to PATA (Mobile Only) or SATA logic

17 IOCHCK# 5 0 Same as ISA IOCHCK# going active.

18 PCI INTA# 53 Drive PIRQA#

19 PCI INTB# 56 Drive PIRQB#

20 PCI INTC # 59 Drive PIRQC#

21 PCI INTD# 62 Drive PIRQD#

Functional Description

152 Intel® ICH8 Family Datasheet

5.11 Real Time Clock (D31:F0)

The Re al Time Clock (RT C) module provides a battery backed-up d ate and time keeping

device with two banks of static RAM with 128 bytes each, although the first bank has

114 bytes for general purpose usage. Three interrupt features are available: time of

day alarm with once a second to once a month range, periodic rates of 122 µs to 500

ms, and end of update cycle notification. Seconds, minutes, hours, days, day of week,

month, and year are counted. Daylight savings compensation is available. The hour is

represented in twelve or twenty -four hour format, and data can be represented in BCD

or binary format. The design is functionally compatible with the Motorola MS146818B.

The time keeping comes from a 32.768 kHz oscillating source, which is divided to

achieve an update every second. The lower 14 bytes on the lower RAM block has very

specific functions. The first ten are for time and date information. The next four (0Ah to

0Dh) are registers, which configure and report RTC functions.

The time and calendar data should match the data mode (BCD or binary) and hour

mode (12 or 24 hour) as selected in register B. It is up to the programmer to make

sure that data stored in these locations is within the reasonable values ranges and

represents a possible date and time. The exception to these ranges is to store a value

of C0–FFh in the Alarm bytes to indicate a don’t care situation. All Alarm conditions

must match to trigger an Alarm Flag, which could trigger an Alarm Interrupt if enabled.

The SET bit must be 1 while programming these locations to avoid clashes with an

update cycle. Access to time and date information is done through the RAM locations. If

a RAM read from the ten time and date bytes is attempted during an update cycle, the

value read do not necessarily represent the true contents of those locations. Any RAM

writes under the same conditions are ignored.

Note: The leap year determination for adding a 29th day to February does not take into

account the end-of-the-century exceptions. The logic simply assumes that all years

divisible by 4 are leap years. According to the Ro yal Observ atory Greenwich, y ears that

are divisible by 100 are typically not leap years. In every fourth century (years divisible

by 400, like 2000), the 100-year-exception is over-ridden and a leap-year occurs. Note

that the year 2100 will be the first time in which the current RT C implementation would

incorrectly calculate the leap-year.

The ICH8 does not implem ent month/year alarms.

5.11.1 Update Cycles

An update cycle occurs once a second, if the SET bit of register B is not asserted and

the divide chain is properly configured. During this procedure, the stored time and date

are incremented, overflow is checked, a matching alarm condition is checked, and the

time and date are rewritten to the RAM locations. The update cycle will start at least

488 µs after the UIP bit of register A is asserted, and the entire cycle does not take

more than 1984 µs to complete. The time and date RAM locations (0–9) are

disconnected from the external bus during this time.

To avoid update and data corruption conditions, external RAM access to these locations

can safely occur at two times. When a updated-ended interrupt is detected, almost 999

ms is available to read and write the valid time and date data. If the UIP bit of Register

A is detected to be low, there is at least 488 µs before the update cycle begins.

Warning: The overflow conditions for leap years and daylight savings adjustments are based on

more than one date or time item. To ensure proper operation wh en adjusting the time,

the new time and data values should be set at least two seconds before one of these

conditions (leap year, daylight savings time adjustments) occurs.

Intel® ICH8 Family Datasheet 153

Functional Description

5.11.2 Interrupts

The real-time clock interrupt is internally routed within the ICH8 both to the I/O APIC

and the 8259. It is mapped to interrupt vector 8. This interrupt does not leave the

ICH8, nor is it shared with any other interrupt. IRQ8# from the SERIRQ stream is

ignored. However, the High Performance Event Timers can also be mapped to IRQ8#;

in this case, the RTC interrupt is blocked.

5.11.3 Lockable RAM Ranges

The RTC’s battery-backed RAM supports two 8-byte ranges that can be locked via the

configuration space. If the locking bits are set, the corresponding r ange in the RAM will

not be readable or writable. A write cycle to those locations will have no effect. A read

cycle to those locations will not return the location’s actual value (resultant value is

undefined).

Once a range is locked, the range can be unlocked only by a hard reset, which will

invoke the BIOS and allow it to relock the RAM range.

5.11.4 Century Rollover

The ICH8 detects a rollover when the Year byte (RTC I/O space, index offset 09h)

transitions form 99 to 00. Upon detecting the rollover, the ICH8 sets the

NEWCENTURY_STS bit (TCOBASE + 04h, bit 7). If the system is in an S0 state, this

causes an SMI#. The SMI# handler can update registers in the RTC RAM that are

associated with century value. If the system is in a sleep state (S1–S5) when the

century rollover occurs, the ICH8 also sets the NEWCENTURY_STS bit, but no SMI# is

generated. When the system resumes from the sleep state, BIOS should check the

NEWCENTURY_STS bit and update the century value in the RTC RAM.

5.11.5 Clearing Battery-Backed RTC RAM

Clearing CMOS RAM in an ICH8-based platform can be done by using a jumper on

RTCRST# or GPI. Implementations should not attempt to clear CMOS by using a

jumper to pull VccRTC low.

Using RTCRST# to Clear CMOS

A jumper on RTCRST# can be used to clear CMOS values, as well as reset to default,

the state of those configuration bits that reside in the RTC power well. When the

RTCRST# is strapped to ground, the RTC_PWR_STS bit (D31:F0:A4h bit 2) will be set

and those configuration bits in the RTC power well will be set to their default state.

BIOS can monitor the state of this bit, and manually clear the RT C CMOS array once the

system is booted. The normal position would cause R T CRST# to be pulled up through a

weak pull-up resistor. Table 58 shows which bits are set to their default state when

R TCRST# is asserted. This RTCRST# jumper technique allows the jumper to be moved

and then replaced—all while the system is powered off. Then, once booted, the

RTC_PWR_STS can be detected in the set state.

Functional Description

154 Intel® ICH8 Family Datasheet

Table 58. Configuration Bits Reset by RTCRST# Assertion (Sheet 1 of 2)

Bit Name Register Location Bit(s) Default

State

Alarm Interrupt Enable

(AIE)

Regi ster B (Gener al

Configuration)

(RTC_REGB)

I/O space (RTC Index +

0Bh) 5X

Alarm Flag (AF) Register C (Flag

(RTC_REGC)

I/O space (RTC Index +

0Ch) 5X

SWSMI_RATE_SEL

General PM

Configuration 3

GEN_PMCON_3

D31:F0:A4h 7:6 0

SLP_S4# Minimum

Assertion Width

General PM

Configuration 3

GEN_PMCON_3

D31:F0:A4h 5:4 0

SLP_S4# Assertion

Stretch Enable

General PM

Configuration 3

GEN_PMCON_3

D31:F0:A4h 3 0

RTC Power Status

(RTC_PWR_STS)

General PM

Configuration 3

GEN_PMCON_3

D31:F0:A4h 2 0

Power Failure

(PWR_FLR)

General PM

Configuration 3

(GEN_PMCON_3)

D31:F0:A4h 1 0

AFTERG3_EN

General PM

Configuration 3

GEN_PMCON_3

D31:F0:A4h 0 0

Power Button Override

Status

(PRBTNOR_STS)

Power Management 1

Status Register

(PM1_STS) PMBase + 00h 11 0

RTC Event Enable

(RTC_EN)

Power Management 1

Enable Register

(PM1_EN) PMBase + 02h 10 0

Sleep Type (SLP_TYP) Power Management 1

Control (PM1_CNT) PMBase + 04h 12:10 0

PME_EN General Purpose

Event 0 Enables

BATLOW_EN General Purpose

Event 0 Enables

RI_EN General Purpose

Event 0 Enables

Intel® ICH8 Family Datasheet 155

Functional Description

Using a GPI to Clear CMOS

A jumper on a GPI can also be used to clear CMOS values. BIOS would detect the

setting of this GPI on system boot-up , and manually clear the CMOS arr a y.

Note: The GPI strap technique to clear CMOS requires multiple steps to implement. The

system is booted with the jumper in new position, then powered back down. The

jumper is replaced back to the normal position, then the system is rebooted again.

Warning: Clearing CMOS, using a jumper on VccRTC, must not be implemented.

5.12 Processor Interface (D31:F0)

The ICH8 interfaces to the processor with a variety of signals

• Standard Outputs to processor: A20M#, SMI#, NMI, INIT#, INTR, STPCLK#,

IGNNE#, CPUSLP#, CPUPWRGD

• Standard Input from processor: FERR#

• Intel SpeedSte p® technology output to processor: CPUPWRGOOD (In mobile

configurations)

Most ICH8 outputs to the processor use standard buffers. The ICH8 has separate

V_CPU_IO signals that are pulled up at the system level to the processor voltage, and

thus determines VOH for the outputs to the processor.

5.12.1 Processor Interface Signals

This section describes each of the signals that interface between the ICH8 and the

processor(s). Note that the behavior of some signals may vary during processor reset,

as the signals are used for frequency strapping.

5.12.1.1 A20M# (Mask A20)

The A20M# signal is active (low) when both of the following conditions are true:

• The ALT_A20_GATE bit (Bit 1 of PORT92 register) is a 0

• The A20GATE input signal is a 0

The A20GATE input signal is expected to be generated by the external microcontroller

(KBC).

NEWCENTURY_STS TCO1 Status Register

(TCO1_STS) TCOBas e + 04h 7 0

Intruder Dete ct

(INTRD_DET) TCO2 Status Register

(TCO2_STS) TCOBas e + 06h 0 0

Top Swap (TS) Backed Up Control

Registers:Offset 3414h 0X

PA T A Reset State (PRS)

(Mobile Only) Backed Up Control

Registers:Offset 3414h 11

Table 58. Configuration Bits Reset by RTCRST# Assertion (Sheet 2 of 2)

Bit Name Register Location Bit(s) Default

State

Functional Description

156 Intel® ICH8 Family Datasheet

5.12.1.2 INIT# (Initialization)

The INIT# signal is active (driven low) based on any one of sev eral events described in

Table 59. When any of these events occur, INIT# is driven low for 16 PCI clocks, then

driven high.

Note: The 16-clock counter for INIT# assertion halts while STPCLK# is active. Therefore, if

INIT# is supposed to go active while STPCLK# is asserted, it actually goes active after

STPCLK# goes inactiv e .

This section refers to INIT#, but applies to two signals: INIT# and INIT3_3V#

(Desktop Only), as INIT3_3V# (Desktop Only) is functionally identical to INIT#, but

signaling at 3.3 V.

Table 59. INIT# Going Active

Cause of INIT# Going Active Comment

Shutdown special cycle from processor observed

on ICH-GMCH interconnect (from GMCH). INIT# assertion based on value of

Shutdown Policy Select register (SPS)

PORT92 write, where INIT_NOW (bit 0) tr ansitions

from a 0 to a 1.

PORTCF9 write, where SYS_RS T (bit 1) was a 0

and RST_CPU (bit 2) transitions from 0 to 1.

RCIN# input signal goes low. RCIN# is expected

to be driven by the external microcontroller

(KBC).

0 to 1 transition on RCIN# must occur

before the Intel® ICH8 will arm INIT# to be

generated again.

NOTE: RCIN# signal is expected to be low

during S3, S4, and S5 states.

Transition on the RCIN# signal in

those states (or the transition to

those states ) may not necessarily

cause the INIT# signal to be

generated to the processor.

CPU BIST To enter BIST, software sets CPU_BIST_EN

bit and then does a full processor reset

using the CF9 register.

Intel® ICH8 Family Datasheet 157

Functional Description

5.12.1.3 FERR#/IGNNE# (Numeric Coprocessor Error/ Ignore Numeric Error)

The ICH8 supports the coprocessor error function with the FERR#/IGNNE# pins. The

function is enabled via the COPROC_ERR_EN bit (Chipset Config Registers:Offset

31FFh:bit 1). FERR# is tied directly to the Coprocessor Error signal of the processor. If

FERR# is driven active by the processor, IRQ13 goes active (internally). When it

detects a write to the COPROC_ERR register (I/O Register F0h), the ICH8 negates the

internal IRQ13 and drives IGNNE# active. IGNNE# remains active until FERR# is driv en

inactive. IGNNE# is never driven active unless FERR# is active.

If COPROC_ERR_EN is not set, the assertion of FERR# will not generate an internal

IRQ13, nor will the write to F0h generate IGNNE#.

5.12.1.4 NMI (Non-Maskable Interrupt)

Non-Maskable Interrupts (NMIs) can be generated by several sources, as described in

Table 60.

5.12.1.5 Stop Clock Request and CPU Sleep (STPCLK# and CPUSLP#)

The ICH8 power management logic controls these active-low signals. Refer to

Section 5.13 for more information on the functionality of these signals.

5.12.1.6 CPU Power Good (CPUPWRGOOD)

This signal is connected to the processor’s PWRGOOD input. This signal represents a

logical AND of the ICH8’s PWROK and VRMPWRGD signals.

Figure 10. Coprocessor Error Timing Diagram

FERR#

Internal IRQ13

I/O Write to F0h

IGNNE#

Table 60. NMI Sources

Cause of NMI Comment

SERR# goes active (either inter nally,

externally via SERR# signal, or via

message from (G)MCH)

Can instead be routed to generate an SCI, through

the NMI2SCI_EN bit (Device 31:Function 0, TCO

Base + 08h, bit 11).

IOCHK# goes active via SERIRQ# stream

(ISA system Error)

Can instead be routed to generate an SCI, through

the NMI2SCI_EN bit (Device 31:Function 0, TCO

Base + 08h, bit 11).

Functional Description

158 Intel® ICH8 Family Datasheet

5.12.1.7 Deeper Sleep (DPSLP#) (Mobile Only)

This active-low signal controls the internal gating of the processor’s core clock. This

signal asserts before and deasserts after the STP_CPU# signal to effectively stop the

processor’s clock (internally) in the states in which STP_CPU# can be used to stop the

processor’s clock externally.

5.12.2 Dual-Processor Issues (Desktop Only)

5.12.2.1 Signal Differences

In dual-processor designs, some of the processor signals are unused or used differently

than for uniprocessor designs.

5.12.2.2 Power Management

For multiple-processor (or Multiple-core) configurations in which more than one Stop

Grant cycle ma y be gener ated, the (G)MCH is expected to count Stop Gr ant cy cles and

only pass the last one through to the ICH8. This prevents the ICH8 from getting out o f

sync with the processor on multiple STPCLK# assertions.

Because the S1 state will have the STPCLK# signal active, the STPCLK# signal can be

connected to both processors. However, for ACPI implementations, the BIOS must

indicate that the ICH8 only supports the C1 state for dual-processor designs.

In going to the S1 state for desktop, multiple Stop-Grant cycles will be generated by

the processors. The Intel ICH8 also has the option to assert the processor’ s SLP# signal

(CPUSLP#). It is assumed that prior to setting the SLP_EN bit (which causes the

transition to the S1 state), the processors will not be executing code that is likely to

delay the Stop-Grant cycles.

In going to the S3, S4, or S5 states, the system will appear to pass through the S1

state; thus, STPCLK# and SLP# are also used. During the S3, S4, and S5 states, both

processors will lose power. Upon exit from those states, the processors will have their

power restored.

Table 61. DP Signal Differences

Signal Difference

A20M# / A20GATE Generally not used, but still supported by Intel® ICH8.

STPCLK# Used for S1 State as well as preparation for entry to S3–S5

Also allows for THERM# based throttling (not via ACPI control methods).

Should be connected to both processors.

FERR# / IGNNE# Generally not used, but still supported by ICH8.

Intel® ICH8 Family Datasheet 159

Functional Description

5.13 Power Management (D31:F0)

5.13.1 Features

• Support for Advanced Configuration and Power Interface, Version 2.0 (ACPI)

providing power and thermal management

— ACPI 24-Bit Timer

— Software initiated throttling of processor performance for Thermal and Power

Reduction

— Hardware Override to throttle processor performance if system too hot

—SCI and SMI# Generation

• PCI PME# signal for Wake Up from Low-Power states

• System Clock Control

— (Mobile Only) ACPI C2 state: Stop Grant (using STPCLK# signal) halts

processor’s instruction stream

— (Mobile Only) ACPI C3 State: Ability to halt processor clock (but not memory

clock)

— (Mobile Only) ACPI C4 State: Ability to lower processor voltage.

— (Mobile Only) CLKRUN# Protocol for PCI Clock Starting/Stopping

• System Sleep State Control

— ACPI S1 state: Stop Grant (using STPCLK# signal) halts processor’s instruction

stream (only STPCLK# active, and CPUSLP# optional)

— ACPI S3 state — Suspend to RAM (STR)

— ACPI S4 state — Suspend-to-Disk (STD)

— ACPI G2/S5 state — Soft Off (SOFF)

— Power Failure Detection and Recovery

• Manageability Engine Power Management Support

— New Wake events from the ME (enabled from all S-States including

Catastrophic S5 conditions)

• Streamlined Legacy Power Management for APM-Based Systems

Functional Description

160 Intel® ICH8 Family Datasheet

5.13.2 Intel® ICH8 and System Power States

Table 62 shows the power states defined for ICH8-based platforms. The state names

generally match the corresponding ACPI states.

Table 63 shows the transitions rules among the various states. Note that transitions

among the various states may appear to temporarily transition through intermediate

states. For example, in going from S0 to S1, it may appear to pass through the G0/S0/

C2 states. These intermediate transitions and states are not listed in the table.

Table 62. General Power States for Systems Using Intel® ICH8

State/

Substates Legacy Name / Description

G0/S0/C0

Full On: Processor operating. Individual devices may be shut down to save

power. The different processor operating levels are defined by Cx states, as

shown in Table 63. Within the C0 state, the Intel® ICH8 can throttle the

processor using the STPCLK# signal to reduce power consumption. The thrott ling

can be initiated by software or by the operating system or BIOS.

G0/S0/C1 Auto-Halt: Processor has executed an AutoHalt instruction and is not executing

code. The processor snoops the bus and maintains cache coherency.

G0/S0/C2

(Mobile

Only)

Stop-Grant: The STPCLK# signal goes active to the processor. The proce ssor

performs a Stop-Grant cycle, halts its instruction stream, and remains in that

state until the STPCLK# signal goes inactive. In the Stop-Grant state, the

processor snoops the bus and maintains cache coherency.

G0/S0/C3

(Mobile

Only)

Stop-Clock: The STPCLK# signal goes active to the processor. The processor

performs a Stop-Grant cycle, halts its instruction stream. ICH8 then asserts

DPSLP# followed by STP_CPU#, which forces the clock generator to stop the

processor clock. This is also used for Intel SpeedStep® technology support.

Accesses to memory (b y graphics, PCI, or inte rnal units) is not permitt ed while in

a C3 state.

G0/S0/C4

(Mobile

Only)

Stop-Clock with Lower Processor Voltage: This closely resembles the G0/

S0/C3 state. However, after the ICH8 has asserted STP_CPU#, it then lowers the

voltage to the processor. This reduces the leakage on the processor. Prior to

exiting the C4 state, the ICH8 increase s the voltage to the processor.

G1/S1

Stop-Grant: Similar to G0/S0/C2 state. ICH8 also has the option to assert the

CPUSLP# signal to further reduce processor power consumption.

NOTE: The behavior for this state is slightly different when supporting iA64

processors.

G1/S3 Suspend-To-RAM (STR): The system context is mai ntained in system DRAM,

but power is shut off to non-critical circuits. Memory is retained, and refreshes

continue. All clocks stop except RTC clock.

G1/S4 Suspend-To-Disk (S TD): The context of the system is maintained on the disk.

All power is then shut off to the system except for the logic required to resume.

G2/S5 Soft Off (SOFF): System context is not maintained. All power is shut off except

for the logic required to restart. A full boot is required when waking.

Mechanical OFF (MOFF): System context not maintained. All power is shut off

except for the RT C. No “W ake” events are possible, because the system does not

have any power. This state occurs if the user removes the batteries, turns off a

mechanical switch, or if the system power supply is at a level that is in sufficient

to power the “waking” logic. When system power returns, transition will depends

on the state just prior to the entry to G3 and the AFTERG3 bit in the

GEN_PMCON3 register (D31:F0, offset A4). Refer to Table 70 for more details.

Intel® ICH8 Family Datasheet 161

Functional Description

NOTES:

1. Some wake events can be preserved through power failure.

2. Transitions from t h e S1–S5 or G3 states to the S0 state are deferred until BATLOW# is

inactive in mobile configurations.

Table 63. State Transition Rules for Intel® ICH8

Present

State Transition Trigger Next State

G0/S0/C0

• Processor halt instruction

• Level 2 Read (Mobile Only)

• Level 3 Read (Mobile Only)

Level 4 Read (Mobile Only)

•SLP_EN bit set

• Power Button Override

• Mechanical Off/Power Failure

•G0/S0/C1

•G0/S0/C2

• G0/S0/C2, G0/S0/C3 or G0/S0/C4 -

depending on C4onC3_EN bit

(D31:F0:Offset A0h:bit 7) and

BM_STS_ZERO_EN bit (D31:F0:Offset

A9h:bit 2) (Mobile Only)

• G1/Sx or G2/S5 state

•G2/S5

•G3

G0/S0/C1

• Any Enabled Break Event

•STPCLK# goes active

• Power Button Override

• Power Failure

•G0/S0/C0

•G0/S0/C2

•G2/S5

•G3

G0/S0/C2

(Mobile

Only)

• Any Enabled Break Event

• Power Button Override

• Power Failure

• Previously in C3/C4 and bus masters

idle

•G0/S0/C0

•G2/S5

•G3

• C3 or C4 - depending on PDME bit (D31:F0:

Offset A9h: bit 4)

G0/S0/C3

(Mobile

Only)

• Any Enabled Break Event

• Any Bus Master Event

• Power Button Override

• Power Failure

• Previously in C4 and bus masters idle

•G0/S0/C0

• G0/S0/C2 - if PUME bit (D31:F0: Offset A9h:

bit 3) is set, else G0/S0/C0

•G2/S5

•G3

• C4 - depending on PDME bit (D31:F0: Offset

A9h: bit 4

G0/S0/C4

(Mobile

Only)

• Any Enabled Break Event

• Any Bus Master Event

• Power Button Override

• Power Failure

•G0/S0/C0

• G0/S0/C2 - if PUME bit (D31:F0: Offset A9h:

bit 3) is set, else G0/S0/C0

•G2/S5

•G3

G1/S1,

G1/S3, or

G1/S4

•Any Enabled Wake Event

• Power Button Override

• Power Failure

• G0/S0/C0 (See Note 2)

•G2/S5

•G3

G2/S5 •Any Enabled Wake Event

• Power Failure • G0/S0/C0 (See Note 2)

•G3

G3 • Power Returns • Optional to go to S0/C0 (reboot) or G2/S5

(stay off until power bu tton pressed or other

wake event). (See Note 1 and 2)

Functional Description

162 Intel® ICH8 Family Datasheet

5.13.3 System Power Planes

The system has several independent power planes, as described in Table 64. Note that

when a particular power plane is shut off, it should go to a 0 V level.

5.13.4 SMI#/SCI Generation

On any SMI# event taking place, ICH8 asserts SMI# to the processor, which causes it

to enter SMM space. SMI# remains active until the EOS bit is set. When the EOS bit is

set, SMI# goes inactive for a minimum of 4 PCICLK. If another SMI event occurs, SMI#

is driven active again.

The SCI is a level-mode interrupt that is typically handled by an ACPI-aware operating

system. In non-APIC systems (which is the default), the SCI IRQ is routed to one of the

8259 interrupts (IRQ 9, 10, or 11). The 8259 interrupt controller must be programmed

to level mode for that interrupt.

In systems using the APIC, the SCI can be routed to interrupts 9, 10, 11, 20, 21, 22, or

23. The interrupt polarity changes depending on whether it is on an interrupt shareable

with a PIRQ or not (see Section 9.1.3). The interrupt remains asserted until all SCI

sources are removed.

Table 65 shows which events can cause an SMI# and SCI. Note that some events can

be programmed to cause either an SMI# or SCI. The usage of the event for SCI

(instead of SMI#) is typically associated with an ACPI -based system. Each SMI# or SCI

source has a corresponding enable and status bit.

Table 64. System Power Plane

Plane Controlled

By Description

CPU SLP_S3#

signal

The SLP_S3# signal can be used to cut the power to the processor

completely. The DPRSLPVR support al lows lowering the process or’s

voltage during the C4 state.

MAIN SLP_S3#

signal

When SLP_S3# goes active, power can be shut off to any circuit

not required to wake the system from the S3 state. Since the S3

state requires that the memory context be preserved, power must

be retained to the main memory.

The processor, devices on the PCI bus, LPC I/F, and graphics will

typically be shut off when the Main power plane is shut, although

there may be small subsections powered.

MEMORY

SLP_S4#

signal

SLP_S5#

signal

When the SLP_S4# goes active, power can be shut off to any

circuit not required to wake the system from th e S4. Since the

memory context does not need to be preserved in the S4 st ate,

the power to the memory can also be shut down.

When SLP_S5# goes active, power can be shut to any circuit not

required to wake the system from the S5 state. Since the memory

context does not need to be preserved in the S5 state, the power

to the memory c an also be shut.

Link

Controller SLP_M#

This pin is asserted when the manageability platform goes to MOff .

Depending on the platform, this pin may be used to control the

(G)MCH, ICH8 controller link power planes, the clock chip power,

and the SPI flash power.

DEVICE[n] GPIO Individual subsystems may have their own power plane. For

example, GPIO signals may be used to control the power to disk

drives, audio amplifiers, or the display screen.

Intel® ICH8 Family Datasheet 163

Functional Description

Table 65. Causes of SMI# and SCI (Sheet 1 of 2)

Cause SCI SMI Additional Enables Where Reported

PME# Yes Yes PME_EN=1 PME_STS

PME_B0 (internal EHCI

controller) Yes Yes PME_B0_EN=1 PME_B0_STS

PCI Express* PME Messages Yes Yes PCI_EXP_EN=1

(Not enabled for SMI) PCI_EXP_STS

PCI Express Hot Plug Message Yes Yes HOT_PLUG_EN=1

(Not enabled for SMI) HOT_PLUG_STS

Power Button Press Yes Yes PWRBTN_EN=1 PWRBTN_STS

Power Button Ov erride (Note

7) Yes No None PRBTNOR_STS

RTC Alarm Yes Yes RTC_ EN= 1 RTC_STS

Ring Indicate Yes Yes RI_EN=1 RI_STS

USB#1 wakes Yes Yes USB1_EN=1 USB1_STS

USB#2 wakes Yes Yes USB2_EN=1 USB2_STS

USB#3 wakes Yes Yes USB3_EN=1 USB3_STS

USB#4 wakes Yes Yes USB4_EN=1 USB4_STS

USB#5 wakes Yes Yes USB5_EN=1 USB5_STS

THRM# pin active Yes Yes THRM_EN=1 THRM_STS

ACPI Timer overflow

(2.34 sec.) Yes Yes TMROF_EN=1 TMROF_STS

Any GPI Yes Yes

GPI[x]_Route=10

(SCI)

GPI[x]_Route=01

(SMI)

GPE0[x]_EN=1

GPI[x]_STS

GPE0_STS

TCO SCI Logic Yes No TCOSCI_EN=1 TCOSCI_STS

TCO SCI message from

(G)MCH Yes No none MCHSCI_STS

TCO SMI Logic No Yes TCO_EN =1 TCO_STS

TCO SMI — Year 2000 Rollo ver No Yes none NEWCENTURY_STS

TCO SMI — TCO TIMEROUT No Yes none TIMEOUT

TCO SMI — OS writes to

TCO_DAT_IN register No Yes none OS_TCO_SMI

TCO SMI — Message from

(G)MCH No Yes none MCHSMI_STS

TCO SMI — NMI occurred (and

NMIs mapped to SMI) No Yes NMI2SMI_EN=1 NMI2SMI_STS

TCO SMI — INTRUDER# signal

goes active No Yes INTRD_SEL=10 INTRD_DET

TCO SMI — Change of the

BIOSWP bit from 0 to 1 No Yes BLD=1 BIOSWR_STS

Functional Description

164 Intel® ICH8 Family Datasheet

NOTES:

1. SCI_EN must be 1 to enable SCI. SCI_EN must be 0 to enable SMI.

2. SCI can be routed to cause interrupt 9:11 or 20:23 (20:23 only available in APIC mode).

3. GBL_SMI_EN must be 1 to enable SMI.

4. EOS must be written to 1 to re-enable SMI for the next 1.

5. ICH8 must have SMI# fully enabled when ICH8 is also enabled to trap cycles. If SMI# is

not enabled in conjunction with the trap enabling, then hardware behavior is undefined.

6. Only GPI[15:0] may generate an SMI# or SCI.

7. When a power button override first occurs, the system will transition immediat ely to S5.

The SCI will only occur after the next wake to S0 if the residual status bit (PRBTNOR_STS)

is not cleared prior to setting SCI_EN.

TCO SMI — Write attempted

to BIOS No Yes BIOSWP=1 BIOSWR_STS

BIOS_RLS written to Yes No GBL_EN=1 GBL_STS

GBL_RLS written to No Yes BIOS_EN=1 BIOS_STS

Write to B2h register No Yes APMC_EN = 1 APM_STS

Periodic timer expires No Yes PERIODIC_EN=1 PERIODIC_STS

64 ms timer expires No Yes SWSMI_TMR_EN=1 SWSMI_TMR_STS

Enhanced USB Legacy

Support Event No Yes LEGACY_USB2_EN = 1 LEGACY_USB2_STS

Enhanced USB Intel Specific

Event No Yes INTEL_USB2_EN = 1 INTEL_USB2_STS

UHCI USB Legacy logic No Yes LEGACY_USB_EN=1 LEGACY_USB_STS

Serial IRQ SMI reported No Yes none SERIRQ_SMI_STS

Device monitors match

address in its range No Yes none DEVMON_STS,

DEVACT_STS

SMBus Host Control le r No Yes SMB_SMI_EN

Host Controller

Enabled

SMBus host status

reg.

SMBus Slave SMI message No Yes none SMBUS_SMI_STS

SMBus SMBALERT# signal

active No Yes none SMBUS_SMI_STS

SMBus Host Notify message

received No Yes HOST_NOTIFY_INTRE

NSMBUS_SMI_STS

HOST_NOTIFY_STS

(Mobile Only) BATLOW#

assertion Yes Yes BATLOW_EN=1. BATLOW_STS

Access microcontroller 62h/

66h No Yes MCSMI_EN MCSMI_STS

SLP_EN bit written to 1 No Yes SMI_ON_SLP_EN=1 SMI_ON_SLP_EN_STS

USB Pe r-Port Registe rs Write

Enable bit changes to 1. No Yes USB2_EN=1,

Write_Enable_SMI_En

able=1

USB2_STS, Write

Enable Status

Table 65. Causes of SMI# and SCI (Sheet 2 of 2)

Cause SCI SMI Additional Enables Where Reported

Intel® ICH8 Family Datasheet 165

Functional Description

5.13.4.1 PCI Express* SCI

PCI Express ports and the (G)MCH (via DMI) have the ability to cause PME using

messages. When a PME message is received, ICH8 will set the PCI_EXP_STS bit. If the

PCI_EXP_EN bit is also set, the ICH8 can cause an SCI via the GPE1_STS register.

5.13.4.2 PCI Express* Hot-Plug

PCI Express has a Hot-Plug mechanism and is capable of generating a SCI via the GPE1

generating a wake event.

5.13.5 Dynamic Processor Clock Control

The ICH8 has extensive control for dynamically starting and stopping system clocks.

The clock control is used for tr ansitions among the v arious S0/Cx states, and processor

throttling. Each dynamic clock control method is described in this section. The various

sleep states may also perform types of non-dynamic clock control.

The ICH8 supports the ACPI C0 and C1 states (in desktop) or C0, C1, C2, C3, and C4

(in mobile) states.

The Dynamic Processor Clock control is handled using the following signals:

• STPCLK#: Used to halt processor instruction stream.

• (Mobile Only) STP_CPU#: Used to stop processor’s clock

• (Mobile Only) CPUSLP#: Asserted prior to STP_CPU# (in stop grant mode)

• (Mobile Only) DPSLP#: Used to force Deeper Sleep for processor.

• (Mobile Only) DPRSLPVR: Used to lower voltage of VRM during C4 state.

• (Mobile Only) DPRSTP#: Used to alert the processor of C4 state. Also works in

conjunction with DPRSLPVR to communicate to the VRM whether a slow or fast

voltage ramp should be used.

The C1 state is entered based on the processor performing an auto halt instruction.

(Mobile Only) The C2 state is entered based on the processor reading the Level 2

snoops and the PUME bit (D31:F0: Offset A9h: bit 3) is set.

(Mobile Only) The C3 state is entered based on the processor reading the Level 3

This state can also be entered after a temporary return to C2 from a prior C3 or C4

state.

(Mobile Only) The C4 state is entered based on the processor reading the Level 4

This state can also be entered after a temporary return to C2 from a prior C4 state.

A C1 state in desktop or a C1, C2, C3 or C4 state in mobile ends due to a Break event.

Based on the break event, the ICH8 returns the system to C0 state.

(Mobile Only) Table 66 lists the possible break events from C2, C3, or C4. The break

events from C1 are indicated in the processor’s datasheet.

Functional Description

166 Intel® ICH8 Family Datasheet

5.13.5.1 Slow C4 Exit (Mobile Only)

To eliminate the audible noise caused by aggressive voltage ramps when exiting C4

states at a regular, periodic frequency, the ICH8 supports a method to slow down the

voltage ramp at the processor VR for certain break events. If enabled for this behavior,

the ICH8 treats IRQ0 and IRQ8 as “slow” break events since both of these can be the

system timer tick interrupt. Rather than carefully tracking the interrupt and timer

configuration information to track the one correct interrupt, it was deemed acceptable

to simplify the logic and slow the break exit sequence for both interrupts. Other break

event sources invoke the normal exit timings.

The ICH8 indicates that a slow voltage ramp is desired by deasserting DPRSTP# (high)

and leaving DPRSLPVR asserted (high). The normal voltage ramp r ate is communicated

by deasserting DPRSTP# (high) and deasserting DPRSLPVR (low).

The ICH8 waits an additional delay before starting the normal voltage ramp timer

during the C4 exit sequence. If a “fast” break event occurs during the additional, slow-

Exit time delay, the ICH8 quickly deasserts DPRSLPVR (low), thereby speeding up the

voltage ramp and reducing the delay to a value that is typically seen by the device in

the past. In the event that a fast break event and a slow break event occur together,

the fast flow is taken.

The ICH8 provides enable for Slow C4 Exit as well as a programmable delay time.

Table 66. Break Events (Mobile Only)

Event Breaks

from Comment

Any unmasked interrupt goes

active C2, C3, C4 IRQ[0:15] when using the 8259s, IRQ[0:23]

for I/O APIC. Since SCI is an interrupt, any SCI

will also be a break event.

Any internal event that cause an

NMI or SMI# C2, C3, C4 Many possible sources

Any internal event that cause

INIT# to go active C2, C3, C4 Could be indicated by the keyboard controller

via the RCIN inpu t signal.

Any bus master request

(internal, external or DMA, or

BMBUSY#) goes active an d

BM_RLD=1 (D31:F0: Offset

PMBASE+04h: bit 1)

C3, C4

Need to wake up processor so it can do snoops

NOTE: If the PUME bit (D31:F0: Offset A9h:

bit 3) is set, then bus master activity

will NOT be treated as a break event.

Instead, there will be a return only to

the C2 state.

Processor Pending Break Event

Indication C2, C3, C4 Only available if FERR# enabled for break event

indication (See FERR# Mux Enable in GCS,

Chipset Config Registers:Offset 3410h:bit 6)

Intel® ICH8 Family Datasheet 167

Functional Description

5.13.5.2 Transition Rules among S0/Cx and Throttling States

The following priority rules and assumptions apply among the various S0/Cx and

throttling states:

• Entry to any S0/Cx state is mutually exclusive with entry to any S1–S5 state. This

is because the processor can only perform one register access at a time and Sleep

states have higher priority than thermal throttling.

• When the SLP_EN bit is set (system going to a S1 - S5 sleep state), the THTL_EN

and FORCE_THTL bits can be internally treated as being disabled (no throttling

while going to sleep state).

• (Mobile Only) If the THTL_EN or FORCE_THTL bits are set, and a Level 2, Level 3,

or Level 4 read then occurs, the system should immediately go and stay in a C2,

C3, or C4 state until a break event occurs. A Level 2, Level 3, or Level 4 read has

higher priority than the software initiated throttling.

• (Mobile Only) After an exit from a C2, C3 or C4 state (due to a Break event), and if

the THTL_EN or FORCE_THTL bits are still set, the system will continue to throttle

STPCLK#. Depending on the time of break event, the first transition on STPCLK#

active can be delayed by up to one THRM period (1024 PCI clocks = 30.72 µs).

• The Host controller must post Stop-Grant cycles in such a way that the processor

gets an indication of the end of the special cycle prior to the ICH8 observing the

Stop-Grant cycle. This ensures that the STPCLK# signals stays active for a

sufficient period after the processor observes the response phase.

• (Mobile Only) If in the C1 state and the STPCLK# signal goes active, the processor

will generate a Stop-Grant cycle, and the system should go to the C2 state. When

STPCLK# goes inactive, it should return to the C1 state.

5.13.5.3 Deferred C3/C4 (Mobile Only)

Due to the new DMI protocol, if there is any bus master activity (other than true isoch),

then the C0 to C3 transition will pause at the C2 state. ICH8 will keep the processor in

a C2 state until:

• ICH8 sees no bus master activity.

• A break event occurs. In this case, the ICH8 will perform the C2 to C0 sequence.

Note that bus master traffic is not a break event in this case.

To take advantage of the Deferred C3/C4 mode, the BM_STS_ZERO_EN bit must be

set. This will cause the BM_STS bit to read as 0 even if some bus master activity is

present. If this is not done, then the software may avoid even attempting to go to the

C3 or C4 state if it sees the BM_STS bit as 1.

If the PUME bit (D31:F0: Offset A9h: bit 3) is 0, then the ICH8 will treat bus master

activity as a break event. When reaching the C2 state, if there is any bus master

activity, the ICH8 will return the processor to a C0 state.

5.13.5.4 POPUP (Auto C3/C4 to C2) (Mobile Only)

When the PUME bit (D31:F0: Offset A9h: bit 3) is set, the ICH8 enables a mode of

operation where standard (non-isoch) bus master activity will not be treated as a full

break event from the C3 or C4 states. Instead, these will be treated merely as bus

master events and return the platform to a C2 state, and thus allow snoops to be

performed.

After returning to the C2 state, the bus master cycles will be sent to the (G)MCH, even

if the ARB_DIS bit is set.

Functional Description

168 Intel® ICH8 Family Datasheet

5.13.5.5 POPDOWN (Auto C2 to C3/C4) (Mobile Only)

After returning to the C2 state from C3/C4, it the PDME bit (D31:F0: Offset A9h: bit 4)

is set, the platform can return to a C3 or C4 state (depending on where it was prior to

going back up to C2). This behaves similar to the Deferred C3/C4 transition, and will

keep the processor in a C2 state until:

• Bus masters are no longer active.

• A break event occurs. Note that bus master traffic is not a break ev ent in this case.

5.13.6 Dynamic PCI Clock Control (Mobile Only)

The PCI clock can be dynamically controlled independent of any other low-power state.

This control is accomplished using the CLKRUN# protocol as described in the PCI Mobile

Design Guide, and is transparent to software.

The Dynamic PCI Clock control is handled using the following signals:

• CLKRUN#: Used by PCI and LPC peripherals to request the system PCI clock to run

• STP_PCI#: Used to stop the system PCI clock

Note: The 33 MHz clock to the ICH8 is “free-running” and is not affected by the STP_PCI#

signal.

5.13.6.1 Conditions for Check i ng the PCI Clock

When there is a lack of PCI activity, the ICH8 has the capability to stop the PCI clocks

to conserve power. “PCI activity” is defined as any activity that would require the PCI

clock to be running.

Any of the following conditions will indicate that it is not okay to stop the PCI clock:

• Cycles on PCI or LPC

• Cycles of any internal device that would need to go on the PCI bus

•SERIRQ activity

Behavioral Description

• When there is a lack of activity (as defined above) for 29 PCI clocks, the ICH8

deasserts (drive high) CLKRUN# for 1 clock and then tri-states the signal.

5.13.6.2 Conditions for Maintaining the PCI Clock

PCI masters or LPC devices that wish to maintain the PCI clock running will observ e the

CLKRUN# signal deasserted, and then must re-assert if (drive it low) within 3 clocks.

• When the ICH8 has tri-stated the CLKRUN# signal after deasserting it, the ICH8

then checks to see if the signal has been re-asserted (externally).

• After observing the CLKRUN# signal asserted for 1 clock, the ICH8 again starts

asserting the signal.

• If an internal device needs the PCI bus, the ICH8 asserts the CLKRUN# signal.

5.13.6.3 Conditions for Stopping the PCI Clock

• If no device re-asserts CLKRUN# once it has been deasserted for at least 6 clocks,

the ICH8 stops the PCI clock by asserting the STP_PCI# signal to the clock

synthesizer.

Intel® ICH8 Family Datasheet 169

Functional Description

5.13.6.4 Conditions for Re-Starting the PCI Clock

• A peripheral asserts CLKRUN# to indicate that it needs the PCI clock re-started.

• When the ICH8 observes the CLKRUN# signal asserted for 1 (free running) clock,

the ICH8 deasserts the STP_PCI# signal to the clock synthesizer within 4 (free

running) clocks.

• Observing the CLKRUN# signal asserted externally for 1 (free running) clock, the

ICH8 again starts driving CLKRUN# asserted.

If an internal source requests the clock to be re-started, the ICH8 re-asserts CLKRUN#,

and simultaneously deasserts the STP_PCI# signal.

5.13.6.5 LPC Devices and CLKRUN#

If an LPC device (of any type) needs the 33 MHz PCI clock, such as for LPC DMA or LPC

serial interrupt, then it can assert CLKRUN#. Note that LPC devices running DMA or bus

master cycles will not need to assert CLKRUN#, since the ICH8 asserts it on their

behalf.

The LDRQ# inputs are ignored by the ICH8 when the PCI clock is stopped to the LPC

devices in order to avoid misinterpreting the request. The ICH8 assumes that only one

more rising PCI clock edge occurs at the LPC device after the assertion of STP_PCI#.

Upon deassertion of STP_PCI#, the ICH8 assumes that the LPC device receives its first

clock rising edge corresponding to the ICH8’s second PCI clock rising edge after the

deassertion.

5.13.7 Sleep States

5.13.7.1 Sleep State Overview

The ICH8 directly supports different sleep states (S1–S5), which are entered by setting

the SLP_EN bit, or due to a Power Button press. The entry to the Sleep states is based

on several assumptions:

• Entry to a Cx state is mutually exclusive with entry to a Sleep state. This is because

the processor can only perform one register access at a time. A request to Sleep

always has higher priority than throttling.

• Prior to setting the SLP_EN bit, the software turns off processor-controlled

throttling. Note that thermal throttling cannot be disabled, but setting the SLP_EN

bit disables thermal throttling (since S1–S5 sleep state has higher priority).

• The G3 state cannot be entered via any software mechanism. The G3 state

indicates a complete loss of power.

5.13.7.2 Initiating Sleep State

Sleep states (S1–S5) are initiated by:

• Masking interrupts, turning off all bus master enable bits, setting the desired type

in the SLP_TYP field, and then setting the SLP_EN bit. The hardw are then attempts

to gracefully put the system into the corresponding Sleep state.

• Pressing the PWRBTN# Signal for more than 4 seconds to cause a Power Button

Override event. In this case the transition to the S5 state is less graceful, since

there are no dependencies on obse rving Stop-Grant cycles from the processor or

on clocks other than the RTC clock

• Assertion of the THRMTRIP# signal will cause a transition to the S5 state. This can

occur when system is in S0 or S1 state.

Functional Description

170 Intel® ICH8 Family Datasheet

5.13.7.3 Exiting Sleep States

Sleep states (S1–S5) are exited based on Wake events. The Wake events forces the

system to a full on state (S0), although some non-critical subsystems might still be

shut off and have to be brought back manually. For exampl e, the hard disk may be shut

off during a sleep state, and have to be enabled via a GPIO pin before it can be used.

Upon exit from the ICH8-controlled Sleep states, the WAK_STS bit is set. The possible

causes of Wake Events (and their restrictions) are shown in Table 68.

Note: (Mobile Only) If the BATLOW# signal is asserted, ICH8 does not attempt to wake from

an S1–S5 state, even if the power button is pressed. This prevents the system from

waking when the battery power is insufficient to wake the system. Wake events that

occur while BATLOW# is asserted are latched by the ICH8, and the system wak es after

BATLOW# is deasserted.

Table 67. Sleep Types

Sleep

Type Comment

S1 Intel® ICH8 asserts the STPCLK# signal. It also has the option to assert CPUSLP#

signal. This lowers the processor’s power consumption. No snooping is possible in

this state.

S3 ICH8 asserts SLP_S3#. The SLP_S3# signal controls the power to non-critical

circuits. Power is only retained to devic e s ne e ded to wake fro m this sleeping state ,

as well as to the memory.

S4 ICH8 asserts SLP_S3# and SLP_S4#. The SLP_S4# signal shuts off the power to

the memory subsystem. Only devices needed to wake from this state should be

powered.

S5 Same power state as S4. ICH8 asserts SLP_S3#, SLP_S4# and SLP_S5#.

Table 68. Causes of Wake Events (Sheet 1 of 2)

Cause States Can

Wake From How Enabled

RTC Alarm S1–S5 (Note

1) Set RTC_EN bit in PM1_EN register

Power Button S1–S5 Always enabled as Wake event

GPI[0:15] S1–S5

(Note 1)

GPE0_EN register

NOTE: GPI’s that are in the core well are not capable of

waking the system from sleep states where the core

well is not powered.

Classic USB S1–S5 Set USB1_EN, USB 2_EN, USB3_EN, and USB4_EN bits in

GPE0_EN register

LAN S1–S5 Will use PME#. Wake enable set with LAN logic.

RI# S1–S5

(Note 1) Set RI_EN bit in GPE0_EN register

Intel® High

Definition Audio S1–S5 Event Sets PME_B0_STS bit; PM_B0_EN must be enabled.

Can not wake from S5 state if it was entered due to power

failure or power button override.

Primary PME# S1–S5

(Note 1) PME_B0_EN bit in GPE0_EN register

Secondary PME# S1–S5 Set PME_EN bit in GPE0_EN register.

Intel® ICH8 Family Datasheet 171

Functional Description

NOTES:

1. This is a wake event from S5 only if the sleep state was entered by setting the SLP_EN and

SLP_TYP bits via software, or if there is a power failure.

2. If in the S5 state due to a power button over ride or THRMTRIP#, the possible wake events

are due to Power Button, Hard Reset Without Cycling (See Command Type 3 in Table 93),

and Hard Reset System (See Command Type 4 in Table 93).

3. When the WAKE# pin is active and the P CI Express device is enabled to wake the sys te m,

the ICH8 will wake the platform.

It is important to understand that the various GPIs hav e different levels of functionality

when used as wake events. The GPIs that reside in the core power well can only

generate wake events from sleep states where the core well is powered. Also, only

certain GPIs are “ACPI Compliant,” meaning that their Status and Enable bits reside in

ACPI I/O space. Table 69 summarizes the use of GPIs as wake events.

The latency to exit the various Sleep states varies greatly and is heavily dependent on

power supply design, so much so that the exit latencies due to the ICH8 are

insignificant.

PCI_EXP_WAKE# S1–S5 PCI_EXP_WAKE bit (Note 3)

PCI_EXP PME

Message S1 Must use the PCI Express* WAKE# pin rather than messages

for wake from S3,S4, or S5.

SMBALERT# S1–S5 Always enabled as Wake event

SMBus Slave

Message S1–S5

Wake/SMI# command always enabled as a Wake event.

NOTE: SMBus Slave Message can wake the system from S1–

S5, as well as from S5 due to Power Button Override.

SMBus Host

Notify message

received S1–S5 HOST_NOTIFY_WKEN bit SMBus Slave Command register.

Reported in the SMB_WAK_STS bit in the GPEO_STS register.

Table 68. Causes of Wake Events (Sheet 2 of 2)

Cause States Can

Wake From How Enabled

Table 69. GPI Wake Events

GPI Power We ll Wake Fro m Not es

GPI[7:0] Core S1 ACPI

Compliant

GPI[15:8] Resume S1–S5 ACPI

Compliant

Functional Description

172 Intel® ICH8 Family Datasheet

5.13.7.4 PCI Express* WAKE# Signal and PME Event Message

PCI Express ports can wake the platform from any sleep state (S1, S3, S4, or S5) using

the WAKE# pin. WAKE# is treated as a wake event, but does not cause any bits to go

active in the GPE_STS register.

PCI Express ports and the (G)MCH (via DMI) have the ability to cause PME using

messages. When a PME message is received, ICH8 will set the PCI_EXP_STS bit.

5.13.7.5 Sx-G3-Sx, Handling Power Failures

Depending on when the power failure occurs and how the system is designed, different

transitions could occur due to a power failure.

The AFTER_G3 bit provides the ability to program whether or not the system should

boot once power returns after a power loss event. If the policy is to not boot, the

system remains in an S5 state (unless previously in S4). There are only three possible

events that will wake the system after a power failure.

1. PWRBTN#: PWRBTN# is always enabled as a wake event. When RSMRST# is low

(G3 state), the PWRBTN_STS bit is reset. When the ICH8 exits G3 after power

returns (RSMRST# goes high), the PWRBTN# signal is already high (because VCC-

standby goes high before RSMRST# goes high) and the PWRBTN_STS bit is 0.

2. RI#: RI# does not have an internal pull-up . Therefore, if this signal is enabled as a

wake event, it is important to keep this signal powered during the power loss

event. If this signal goes low (active), when power return s the RI_STS bit is set and

the system interprets that as a wake event.

3. RTC Alarm: The RT C_EN bit is in the R T C well and is preserved after a power loss.

Like PWRBTN_STS the RTC_STS bit is cleared when RSMRST# goes low.

The ICH8 monitors both PWROK and RSMRST# to detect for power failures. If PWROK

goes low, the PWROK_FLR bit is set. If RSMRST# goes low, PWR_FLR is set.

Note: Although PME_EN is in the RTC well, this signal cannot wake the system after a power

loss. PME_EN is cleared by RTCRST#, and PME_STS is cleared by RSMRST#.

Table 70. Transitions Due to Power Failure

State at Power Failure AFTERG3_EN bit Transition When Power Returns

S0, S1, S3 1

0S5

S4 1

0S4

S5 1

0S5

Intel® ICH8 Family Datasheet 173

Functional Description

5.13.8 Thermal Management

The ICH8 has mechanisms to assist with managing thermal problems in the system.

5.13.8.1 THRM# Signal

The THRM# signal is used as a status input for a thermal sensor. Based on the THRM#

signal going active, the ICH8 generates an SMI# or SCI (depending on SCI_EN).

If the THRM_POL bit is set low, when the THRM# signal goes low, the THRM_STS bit

will be set. This is an indicator that the thermal threshold has been exceeded. If the

THRM_EN bit is set, then when THRM_STS goes active, either an SMI# or SCI will be

generated (depending on the SCI_EN bit being set).

The power management software (BIOS or ACPI) can then take measures to start

reducing the temperature. Examples include shutting off unwanted subsystems, or

halting the processor.

By setting the THRM_POL bit to high, another SMI# or SCI can optionally be gener ated

when the THRM# signal goes back high. This allows the software (BIOS or ACPI) to

turn off the cooling methods.

Note: THRM# assertion does not cause a TCO event message in S3 or S4. The level of the

signal is not reported in the heartbeat message.

5.13.8.2 Software Initiated Passive Cooling

This mode is initiated by software setting the THTL_EN or FORCE_THTL bits.

Software sets the THTL_DTY or THRM_DTY bits to select throttle ratio and THTL_EN or

FORCE_THTL bit to enable the throttling.

Throttling results in STPCLK# active for a minimum time of 12.5% and a maximum of

87.5%. The period is 1024 PCI clocks. Thus, the STPCLK# signal can be active for as

little as 128 PCI clocks or as much as 896 PCI clocks. The actual slowdown (and

cooling) of the processor depends on the instruction stream, because the processor is

allowed to finish the current instruction. Furthermore, the ICH8 waits for the STOP-

GRANT cycle before starting the count of the time the STPCLK# signal is active.

5.13.8.3 THRM# Override Software Bit

The FORCE_THTL bit allows the BIOS to force passive cooling, independent of the ACPI

software (which uses the THTL_EN and THTL_DTY bits). If this bit is set, the ICH8

starts throttling using the ratio in the THRM_DTY field.

When this bit is cleared the ICH8 stops throttling, unless the THTL_EN bit is set

(indicating that ACPI software is attempting throttling).

If both the THTL_EN and FORCE_THTL bits are set, then the ICH8 should use the duty

cycle defined by the THRM_DTY field, not the THTL_DTY field.

5.13.8.4 Active Cooling

Active cooling involves fans. The GPIO signals from the ICH8 can be used to turn on/off

a fan.

Functional Description

174 Intel® ICH8 Family Datasheet

5.13.9 Event Input Signals and Their Usage

The ICH8 has various input signals that trigger specific events. This section describes

those signals and how they should be used.

5.13.9.1 PWRBTN# (Power Button)

The ICH8 PWRBTN# signal operates as a “Fixed Power Button” as described in the

Advanced Configuration and Power Interface, Version 2.0b. PWRBTN# signal has a 16

ms de-bounce on the input. The state transition descriptions are included in Table 71.

Note that the transitions start as soon as the PWRBTN# is pressed (but after the

debounce logic), and does not depend on when the Power Button is released.

Note: During the time that the SLP_S4# signal is stretched for the minimum assertion width

(if enabled), the Power Button is not a wake event. Refer to Power Button Override

Function section below for further detail.

Power Button Override Function

If PWRBTN# is observ ed active for at least four consecutive seconds, the state machine

should unconditionally transition to the G2/S5 state, regardless of present state

(S0–S4), even if PWROK is not active. In this case, the transition to the G2/S5 state

should not depend on any particular response from the processor (e.g., a Stop-Grant

cycle), nor any similar dependency from any other subsystem.

The PWRBTN# status is readable to check if the button is currently being pressed or

has been released. The status is taken after the de-bounce, and is readable via the

PWRBTN_LVL bit.

Note: The 4-second PWRBTN# assertion should only be used if a system lock-up has

occurred. The 4-second timer starts counting when the ICH8 is in a S0 state. If the

PWRBTN# signal is asserted and held active when the system is in a suspend state

(S1–S5), the assertion causes a wake event. Once the system has resumed to the S0

state, the 4-second timer starts.

Note: During the time that the SLP_S4# signal is stretched for the minimum assertion width

(if enabled by D31:F0:A4h bit 3), the Power Button is not a wake event. As a result, it

is conceivable that the user will press and continue to hold the P ower Button waiting for

the system to awak e. Since a 4-second press of the Power Button is already defined as

an Unconditional Power down, the power button timer will be forced to inactive while

the power-cycle timer is in progress. Once the power-cycle timer has expired, the

Table 71. Transitions Due to Power Button

Present

State Event Transition/Action Comment

S0/Cx PWRBTN# goes low

SMI# or SCI generated

(depending on SCI_EN,

PWRBTN_INIT_EN,

PWRBTN_EN and

GLB_SMI_EN)

Software typically initiates a

Sleep state

S1–S5 PWRBTN# goes low Wake Event. Transitions to

S0 state Standard wakeup

G3 PWRBTN# pressed None No effect since no power

Not latched nor detected

S0–S4 PWRBTN# held low

for at least 4

consecutive seconds

Unconditio nal transition to

S5 state

No dependence on processor

(e.g., Stop-Grant cycles) or

any other subsystem

Intel® ICH8 Family Datasheet 175

Functional Description

Power Button awakes the system. Once the minimum SLP_S4# power cycle expires,

the Power Button must be pressed for another 4 to 5 seconds to create the Override

condition to S5.

Sleep Button

The Advanced Configuration and Power Interface, Version 2.0b defines an optional

Sleep button. It differs from the power button in that it only is a request to go from S0

to S1–S4 (not S5). Also , in an S5 state, the P ower Button can wake the system, but the

Sleep Button cannot.

Although the ICH8 does not include a specific signal designated as a Sleep Button, one

of the GPIO signals can be used to create a “Control Method” Sleep Button. See the

Advanced Configuration and Power Interface, Version 2.0b for implementation details.

5.13.9.2 RI# (Ring Indicator)

The Ring Indicator can cause a wake event (if enabled) from the S1–S5 states.

Table 72 shows when the wake event is generated or ignored in different states. If in

the G0/S0/Cx states, the ICH8 generates an interrupt based on RI# active, and the

interrupt will be set up as a Break event.

Note: Filtering/Debounce on RI# will not be done in ICH8. Can be in modem or external.

5.13.9.3 PME# (PCI Power Management Event)

The PME# signal comes from a PCI device to request that the system be restarted. The

PME# signal can generate an SMI#, SCI, or optionally a W ake event. The event occurs

when the PME# signal goes from high to low. No event is caused when it goes from low

to high.

There is also an internal PME_B0 bit. This is separate from the external PME# signal

and can cause the same effect.

5.13.9.4 SYS_RESET# Signal

When the SYS_RESET# pin is detected as active after the 16 ms debounce logic, the

ICH8 attempts to perform a “graceful” reset, by waiting up to 25 ms for the SMBus to

go idle. If the SMBus is idle when the pin is detected active, the reset occurs

immediately; otherwise, the counter starts. If at an y point during the count the SMBus

goes idle the reset occurs. If , however, the counter expires and the SMBus is still active,

a reset is forced upon the system even though activity is still occurring.

Once the reset is asserted, it remains asserted for 5 to 6 ms regardless of whether the

SYSRESET# input r emains asserted or not. It cannot occur again until SYS_RESET#

has been detected inactive after the debounce logic, and the system is back to a full S0

state with PLTRST# inactive. Note that if bit 3 of the CF9h I/O register is set then

SYS_RESET# will result in a full power cycle reset.

Table 72. Transitions Due to RI# Signal

Present State Event RI_EN Event

S0 RI# Active X Ignored

S1–S5 RI# Active 0

1Ignored

Wake Event

Functional Description

176 Intel® ICH8 Family Datasheet

5.13.9.5 THRMTRIP# Signal

If THRMTRIP# goes active, the processor is indicating an overheat condition, and the

ICH8 immediately transitions to an S5 state. However, since the proce ssor has

overheated, it does not respond to the ICH8’s STPCLK# pin with a stop grant special

cycle. Therefore, the ICH8 does not wait for one. Immediately upon seeing THRMTRIP#

low , the ICH8 initiates a transition to the S5 state, d rive SLP _S3#, SLP_S 4#, SLP_S5#

low, and set the CTS bit. The transition looks like a power button override.

It is extremely important that when a THRMTRIP# ev ent occurs, the ICH8 power down

immediately without following the normal S0 -> S5 path. This path may be taken in

parallel, but ICH8 must immediately enter a power down state. It does this by driving

SLP_S3#, SLP_S4#, and SLP_S5# immediately after sampling THRMTRIP# active.

If the processor is running extremely hot and is heating up, it is possible (although very

unlikely) that components around it, such as the ICH8, are no longer executing cycles

properly. Therefore, if THRMTRIP# goes active, and the ICH8 is relying on state

machine logic to perform the power down, the state machine may not be working, and

the system will not power down.

The ICH8 follows this flow for THRMTRIP#.

1. At boot (PLTRST# low), THRMTRIP# ignored.

2. After power- up (PLTRST# high), if THRMTRIP# sampled active, SLP_S3#,

SLP_S4#, and SLP_S5# assert, and normal sequence of sleep machine starts.

3. Until sleep machine enters the S5 state, SLP_S3#, SLP_S4#, and SLP_S5# stay

active, even if THRMTRIP# is now inactive. This is the equivalent of “latching” the

thermal trip event.

4. If S5 state reached, go to step #1, otherwise stay here. If the ICH8 never reaches

S5, the ICH8 does not reboot until power is cycled.

During boot, THRMTRIP# is ignored until SLP_S3#, PWROK, VRMPWRGD/VGATE, and

PLTRST# are all ‘1’. During entry into a powered-down state (due to S3, S4, S5 entry,

power cycle reset, etc.) THRMTRIP# is ignored until either SLP_S3# = 0, or PWROK =

0, or VRMPWRGD/VGATE = 0.

Note: A thermal trip event will:

• Set the AFTERG3_EN bit

• Clear the PWRBTN_STS bit

• Clear all the GPE0_EN register bits

• Clear the SMB_WAK_STS bit only if SMB_SAK_STS was set due to SMBus slave

receiving message and not set due to SMBAlert

5.13.9.6 BMBUSY# (Mobile Only)

The BMBUSY# signal is an input from a graphics component to indicate if it is busy. If

prior to going to the C3 state, the BMBUSY# signal is active, then the BM_STS bit will

be set. If after going to the C3 state, the BMBUSY# signal goes back active, the ICH8

will treat this as if one of the PCI REQ# signals went active. This is treated as a break

event.

Intel® ICH8 Family Datasheet 177

Functional Description

5.13.10 ALT Access Mode

Before entering a low power state, several registers from powered down parts may

need to be saved. In the majority of cases, this is not an issue, as registers have read

and write paths. However, sever al of the ISA compatible registers are either read only

or write only. To get data out of write-only registers, and to restore data into read-only

registers, the ICH8 implements an ALT access mode.

If the ALT access mode is entered and exited after reading the registers of the ICH8

timer (8254), the timer starts counting faster (13.5 ms). The following steps listed

below can cause problems:

1. BIOS enters ALT access mode for reading the ICH8 timer related registers.

2. BIOS exits ALT access mode.

3. BIOS continues through the execution of other needed steps and passes control to

the operating system.

After getting control in step #3, if the operating system does not reprogram the system

timer again, the timer ticks may be happening faster than expected. F or example DOS

and its associated softw are assume that the system tim er is running at 54.6 ms and as

a result the time-outs in the software may be happening faster than expected.

Operating systems (e.g., Microsoft Windows* 98, Windows* 2000, and Windows NT*)

reprogram the system timer and therefore do not encounter this problem.

For some other loss (e.g., Microsoft MS-DOS*) the BIOS should restore the timer back

to 54.6 ms before passing control to the operating system. If the BIOS is entering ALT

access mode before entering the suspend state it is not necessary to restore the timer

contents after the exit from ALT access mode.

5.13.10.1 Write Only Registers with Read Paths in ALT Access Mode

The registers described in Table 73 have read paths in ALT access mode. The access

number field in the table indicates which register will be returned per access to that

port.

Functional Description

178 Intel® ICH8 Family Datasheet

Table 73. Write Only Registers with Read Paths in ALT Access Mode (Sheet 1 of 2)

Restore Data Restore Data

I/O

Addr # of

Rds Access Data I/O

Addr # of

Rds Access Data

00h 2 1DMA Chan 0 base address low

byte

40h 7

1Timer Counter 0 status, bits

[5:0]

2DMA Chan 0 base address high

byte 2Timer Counter 0 base count

low byte

01h 2 1DMA Chan 0 base count low

byte 3Timer Counter 0 base count

high byte

2DMA Chan 0 base count high

byte 4Timer Counter 1 base count

low byte

02h 2 1DMA Chan 1 base address low

byte 5Timer Counter 1 base count

high byte

2DMA Chan 1 base address high

byte 6Timer Counter 2 base count

low byte

03h 2 1DMA Chan 1 base count low

byte 7Timer Counter 2 base count

high byte

2DMA Chan 1 base count high

byte 41h 1 Timer Counter 1 status, bits

[5:0]

04h 2 1DMA Chan 2 base address low

byte 42h 1 Timer Counter 2 status, bits

[5:0]

2DMA Chan 2 base address high

byte 70h 1 Bit 7 = NMI Enable,

Bits [6:0] = RTC Address

05h 2 1DMA Chan 2 base count low

byte C4h 2 1DMA Chan 5 base address low

byte

2DMA Chan 2 base count high

byte 2DMA Chan 5 base address

high byte

06h 2 1DMA Chan 3 base address low

byte C6h 2 1DMA Chan 5 base count low

byte

2DMA Chan 3 base address high

byte 2DMA Chan 5 base count high

byte

07h 2 1DMA Chan 3 base count low

byte C8h 2 1DMA Chan 6 base address low

byte

2DMA Chan 3 base count high

byte 2DMA Chan 6 base address

high byte

Intel® ICH8 Family Datasheet 179

Functional Description

NOTES:

1. The OCW1 register must be read before entering ALT access mode.

2. Bits 5, 3, 1, and 0 return 0.

5.13.10.2 PIC Reserved Bits

Many bits within the PIC are reserved, and must ha ve certain values written in order for

the PIC to operate properly. Therefore, there is no need to return these values in ALT

access mode. When reading PIC registers from 20h and A0h, the reserved bits shall

return the values listed in Table 74.

08h 6

1 DMA Chan 0–3 Command2

CAh 2 1DMA Cha n 6 base count low

byte

2 DMA Chan 0–3 Request 2 DMA Chan 6 base count high

byte

3DMA Chan 0 Mode:

Bits(1:0) = 00 CCh 2 1DMA Chan 7 base address low

byte

4DMA Chan 1 Mode:

Bits(1:0) = 01 2DMA Chan 7 base address

high byte

5DMA Chan 2 Mode:

Bits(1:0) = 10 CEh 2 1DMA Chan 7 base c o unt low

byte

6DMA Chan 3 Mode: Bits(1 :0) =

11. 2DMA Chan 7 base count high

byte

20h 12

1 PIC ICW2 of Master controller

D0h 6

1 DMA Chan 4–7 Command2

2 PIC ICW3 of Master controller 2 DMA Cha n 4–7 Request

3 PIC ICW4 of Master controller 3 DMA Chan 4 Mode: Bits(1:0)

= 00

4PIC OCW1 of Master

controller14DMA Chan 5 Mode: Bits(1:0)

= 01

5 PIC OCW2 of Master controller 5 DMA Cha n 6 Mode: Bits(1:0)

= 10

6 PIC OCW3 of Master controller 6 DMA Cha n 7 Mode: Bits(1:0)

= 11.

7 PIC ICW2 of Slave controller

8 PIC ICW3 of Slave controller

9 PIC ICW4 of Slave controller

10 PIC OCW1 of Slave controller1

11 PIC OCW2 of Slave controller

12 PIC OCW3 of Slave controller

Table 73. Write Only Registers with Read Paths in ALT Access Mode (Sheet 2 of 2)

Restore Data Restore Data

I/O

Addr # of

Rds Access Data I/O

Addr # of

Rds Access Data

Functional Description

180 Intel® ICH8 Family Datasheet

5.13.10.3 Read Only Registers with Write Paths in ALT Access Mode

The registers described in Table 75 have write paths to them in ALT access mode.

Software restores these values after returning from a powered down state. These

registers must be handled special by software. When in normal mode, writing to the

base address/count register also writes to the current address/count register.

Therefore, the base address/count must be written first, then the part is put into ALT

access mode and the current address/count register is written.

5.13.11 System Power Supplies, Planes, and Signals

5.13.11.1 Power Plane Control with SLP_S3#, SLP_S4#, SLP_S5# and SLP_M#

The SLP_S3# output signal can be used to cut power to the system cor e supply, since it

only goes active for the STR state (typically mapped to ACPI S3). Power must be

maintained to the ICH8 resume well, and to any other circuits that need to generate

Wake signals from the STR state.

Cutting power to the core may be done via the power supply, or by external FETs to the

motherboard.

The SLP_S4# or SLP_S5# output signal can be used to cut power to the system core

supply, as well as power to the system memory, since the context of the system is

saved on the disk. Cutting power to the memory may be done via the power supply, or

by external FETs to the motherboard.

The SLP_S4# output signal is used to remove power to additional subsystems th at are

powered during SLP_S3#.

SLP_S5# output signal can be used to cut power to the system core supply, as well as

power to the system memory, since the context of the system is saved on the disk.

Cutting power to the memory may be done via the power supply, or by external FETs to

the motherboard.

SLP_M# output signal can be used to cut power to the Link Controller, Clock chip or SPI

flash on a platform that supports Intel AMT.

Table 74. PIC Reserved Bits Return Values

PIC Reserved Bits Value Returned

ICW2(2:0) 000

ICW4(7:5) 000

ICW4(3:2) 00

ICW4(0) 0

OCW2(4:3) 00

OCW3(7) 0

OCW3(5) Reflects bit 6

OCW3(4:3) 01

Table 75. Register Write Accesses in ALT Access Mode

I/O Address Register Write Value

08h DMA Status Register for channels 0–3.

D0h DMA St atus Register for channels 4–7.

Intel® ICH8 Family Datasheet 181

Functional Description

5.13.11.2 SLP_S4# and Suspend-To-RAM Sequencing

The system memory suspend voltage regulator is controlled by the Glue logic. The

SLP_S4# signal should be used to remove power to system memory rather than the

SLP_S5# signal. The SLP_S 4# logic in the ICH8 provides a mechanism to fully cycle

the power to the DRAM and/or detect if the power is not cycled for a minimum time.

Note: To utilize the minimum DRAM power-down feature that is enabled by the SLP_S4#

Assertion Stretch Enable bit (D31:F0:A4h bit 3), the DRAM power must be controlled

by the SLP_S4# signal.

5.13.11.3 PWROK Signal

The PWROK input should go active based on the core supply voltages becoming valid.

PWROK should go active no sooner than 100 ms after Vcc3_3 and Vcc1_5 have reached

their nominal values.

Note:

1. SYSRESET# is recommended for implementing the system reset button. This saves

external logic that is needed if the PWROK input is used. Additionally, it allows for

better handling of the SMBus and processor resets, and avo ids improp e rly

reporting power failures.

2. If the PWROK input is used to implement the system reset button, the ICH8 does

not provide any mechanism to limit the amount of time that the processor is held in

reset. The platform must externally assure that maximum reset assertion specs are

met.

3. If a design has an active-low reset button electrically AND’d with the PWROK signal

from the power supply and the processor’s v oltage regulator module the ICH8

PWROK_FLR bit will be set. The ICH8 treats this internally as if the RSMRST# signal

had gone active. However, it is not treated as a full power failure. If PWROK goes

inactive and then active (but RSMRST# stays high), then the ICH8 reboots

(regardless of the state of the AFTERG3 bit). If the RSMRST# signal also goes low

before PWROK goes high, then this is a full power failure, and the reboot policy is

controlled by the AFTERG3 bit.

4. PWROK and RSMRST# are sampled using the RTC clock. Therefore, low times that

are less than one RTC clock period may not be detected by the ICH8.

5. In the case of true PWROK failure, PWROK goes low first before the VRMPWRGD.

6. When PWROK goes inactive, a host power cycle and global reset will occur. A host

power cycle is the assertion of SLP_S3#, SLP_S4#, and SLP_S5#, and the

deassertion of these signals 3-5 seconds later. The ME remains powered throughout

this cycle.

5.13.11.4 CPUPWRGD Signal

This signal is connected to the processor’s VRM via the VRMPWRGD signal and is

internally AND’d with the PWROK signal that comes from the system power supply.

5.13.11.5 VRMPWRGD Signal

VRMPWRGD is an input from the regulator indicating that all of the outputs from the

regulator are on and within specification. VRMPWRGD may go active before or after the

PWROK from the main power supply. ICH8 has no dependency on the order in which

these two signals go active or inactive. However, platforms that use the VRMPWRGD

signal to start the clock chip PLLs assume that it does assert milliseconds before

PWROK in order to provide valid clocks in time for the PWROK rising.

Functional Description

182 Intel® ICH8 Family Datasheet

Note: When VRMPWRGD goes inactive, a host power cycle and global reset will occur.

5.13.11.6 BATLOW# (Battery Low) (Mobile Only)

The BATLOW# input can inhibit waking from S3, S4, and S5 states if there is not

sufficient power. It also causes an SMI# if the system is already in an S0 state.

5.13.11.7 Controlling Leakage and Power Consumption

during Low-Power States

To control leakage in the system, various signals tri-state or go low during some low-

power states.

General principles:

• All signals going to powered down planes (either internally or externally) must be

either tri-stated or driven low.

• Signals with pull-up resistors should not be low during low-power states. This is to

avoid the power consumed in the pull-up resistor.

• Buses should be halted (and held) in a known state to avoid a floating input

(perhaps to some other device). Floating inputs can cause extra power

consumption.

Based on the above principles, the follow in g meas ures are tak e n:

• During S3 (STR), all signals attached to powered down planes are tri-stated or

driven low.

5.13.12 Clock Generat ors

The clock generator is expected to provide the frequencies shown in Table 76.

Table 76. Intel® ICH8 Clock Inputs

Clock

Domain Frequency Source Usage

SATA_CLK 100 MHz

Differential Main Clock

Generator Used by SATA controller . Stopped in S3 ~ S5 based on

SLP_S3# assertion.

DMI_CLK 100 MHz

Differential Main Clock

Generator Used by DMI and PCI Express*. Stopped in S3 ~ S5

based on SLP_S3# assertion.

PCICLK 33 MHz Main Clock

Generator

Desktop: Free-running PCI Clock to ICH8. Stopped in

S3 ~ S5 based on SLP_S3# assertion.

Mobile: Free-running (not affected by STP_PCI# PCI

Clock to ICH8. This is not the system PCI clock. This

clock must keep r u nning in S0 while the system PCI

clock may stop based on CLKRUN# protocol. Stopped

in S3 ~ S5 based on SLP_S3# assertion.

CLK48 48.000 MHz Main Clock

Generator

Used by USB controllers and Int el® High Definition

Audio controller. Stopped in S3 ~ S5 based on

SLP_S3# assertion.

CLK14 14.318 MHz Main Clock

Generator Used by ACPI timers. Stopped in S3 ~ S5 based on

SLP_S3# assertion.

LAN_CLK 0.8 to

50 MHz LAN

Connect LAN Connect Interface. Control policy is determined

by the clock source.

Intel® ICH8 Family Datasheet 183

Functional Description

5.13.12.1 Clock Control Signals from Intel® ICH8 to Clock

Synthesizer (Mobile Only)

The clock generator is assumed to hav e direct connect from the following ICH8 signals:

• STP_CPU#: Stops processor clocks in C3 and C4 states

• STP_PCI#: Stops system PCI clocks (not the ICH8 free-running 33 MHz clock) due

to CLKRUN# protocol

• SLP_S3#: Expected to drive clock chip PWRDOWN (through inverter), to stop

clocks in S3 to S5.

5.13.13 Legacy Power Management Theory of Operation

Instead of relying on ACPI software, legacy power management uses BIOS and various

hardware mechanisms. The scheme relies on the concept of detecting when individual

subsystems are idle, detecting when the whole system is idle, and detecting when

accesses are attempted to idle subsystems.

However, the operating system is assumed to be at least APM enabled. Without APM

calls, there is no quick way to know when the system is idle between keystrokes. The

ICH8 does not support burst modes.

5.13.13.1 APM Power Management (Desktop Only)

The ICH8 has a timer that, when enabled by the 1MIN_EN bit in the SMI Control and

Enable register, generates an SMI# once per minute. The SMI handler can check for

system activity by reading the DEVA CT_STS register. If none of the system bits are set,

the SMI handler can increment a software counter. When the counter reaches a

sufficient number of consecutiv e minutes with no activity, the SMI handler can then pu t

the system into a lower power state.

If there is activity, various bits in the DEVACT_STS register will be set. Software clears

the bits by writing a 1 to the bit position.

The DEVACT_STS register allows for monitoring various internal devices, or Super I/O

devices (SP, PP, FDC) on LPC or PCI, keyboard controller accesses, or audio functions

on LPC or PCI. Other PCI activity can be monitored by checking the PCI interrupts.

5.13.13.2 Mobile APM Power Management (Mobile Only)

In mobile systems, there are additional requirements associated with device power

management. To handle this, the ICH8 has specific SMI# traps available. The following

algorithm is used:

1. The periodic SMI# timer checks if a device is idle for the require time. If so, it puts

the device into a low-power state and sets the associated SMI# trap.

2. When software (not the SMI# handler) attempts to access the device, a tr ap occurs

(the cycle does not really go to the device and an SMI# is generated).

3. The SMI# handler turns on the device and turns off the trap

The SMI# handler exits with an I/O restart. This allows the original software to

continue.

Functional Description

184 Intel® ICH8 Family Datasheet

5.14 System Management (D31:F0)

The ICH8 provides various functions to make a system easier to manage and to lower

the Total Cost of Ownership (TCO) of the system. In addition, ICH8 provides integr ated

ASF Management support. Features and functions can be augmented via external A/D

converters and GPIO, as well as an external microcontroller.

The following features and functions are supported by the ICH8:

• Processor present detection

— Detects if processor fails to fetch the first instruction after reset

• Various Error detection (such as ECC Errors) Indicated by host controller

— Can generate SMI#, SCI, SERR, NMI, or TCO interrupt

• Intruder Detect input

— Can generate TCO interrupt or SMI# when the system cover is removed

— INTRUDER# allowed to go active in any power state, including G3

• Detection of bad BIOS Flash (FWH or Flash on SPI) programming

— Detects if data on first read is FFh (indicates that BIOS flash is not

programmed)

• Ability to hide a PCI device

— Allows software to hide a PCI device in terms of configuration space through

the use of a device hide register (See Section 7.1.71)

Note: Voltage ID from the processor can be read via GPI signals.

Note: ASF functionality with the integrated ICH8 ASF controller requires a correctly

configured system, including an appropriate (G)MCH with ME, ME Firmware, system

BIOS support, and appropriate Platform LAN Connect Device.

5.14.1 Theory of Operation

The System Management functions are designed to allow the system to diagnose failing

subsystems. The intent of this logic is that some of the system management

functionality be provided without the aid of an external microcontroller.

5.14.1.1 Detecting a System Lockup

When the processor is reset, it is expected to fetch its first instruction. If the processor

fails to fetch the first instruction after reset, the TCO timer times out twice and the

ICH8 asserts PLTRST#.

5.14.1.2 Handling an Intruder

The ICH8 has an input signal, INTRUDER#, that can be attached to a switch that is

activated by the system’ s case being open. This input has a two R TC clock debounce. If

INTRUDER# goes active (after the debouncer), this will set the INTRD_DET bit in the

TCO_STS register. The INTRD_SEL bits in the TCO_CNT register can enable the ICH8 to

cause an SMI# or interrupt. The BIOS or interrupt handler can then cause a transition

to the S5 state by writing to the SLP_EN bit.

The software can also directly read the status of the INTRUDER# signal (high or low) by

clearing and then reading the INTRD_DET bit. This allows the signal to be used as a GPI

if the intruder function is not required.

Intel® ICH8 Family Datasheet 185

Functional Description

If the INTRUDER# signal goes inactive some point after the INTRD_DET bit is written

as a 1, then the INTRD_DET signal will go to a 0 when INTRUDER# input signal goes

inactive. Note that this is slightly different than a classic sticky bit, since most sticky

bits would remain active indefinitely when the signal goes active and would

immediately go inactive when a 1 is written to the bit.

Note: The INTRD_DET bit resides in the ICH8’s RTC well, and is set and cleared

synchronously with the RTC clock. Thus, when software attempts to clear INTRD_DET

(by writing a 1 to the bit location) there may be as much as two RTC clocks (about 65

µs) delay before the bit is actually cleared. Also, the INTRUDER# signal should be

asserted for a minimum of 1 ms to assure that the INTRD_DET bit will be set.

Note: If the INTRUDER# signal is still active when software attempts to clear the INTRD_DET

bit, the bit remains set and the SMI is generated again immediately. The SMI handler

can clear the INTRD_SEL bits to avoid further SMIs. Howev er, if the INTRUDER# signal

goes inactive and then active again, there will not be further SMIs, since the

INTRD_SEL bits would select that no SMI# be generated.

5.14.1.3 Detecting Improper Firmware Hub Programming

The ICH8 can detect the case where the BIOS flash is not programmed. This results in

the first instruction fetched to have a value of FFh. If this occurs, the ICH8 sets the

BAD_BIOS bit. The BIOS flash may reside in FWH or flash on the SPI bus.

5.14.2 TCO Modes

5.14.2.1 TCO Legacy/Compatible Mode

In TCO Legacy/Compatible mode the Intel Management Engine and Intel AMT logic and

SMBus controllers are disabled. To enable Legacy/Compatible TCO mode the T COMODE

bit 7 in the ICHSTRP0 register in the SPI device must be 0. See Section 20.2.5.1 for

details.

Note: SMBus and SMLink may be tied together externally, if a device has a single SMBus

interface and needs access to the TCO slave and be visible to the host SMBus controller.

Functional Description

186 Intel® ICH8 Family Datasheet

In TCO Legacy/Compatible mode the Intel ICH8/ICH8M can function directly with the

integrated Gigabit Ethernet controller or equivalent external LAN controller to report

messages to a network management console without the aid of the system processor.

This is crucial in cases where the processor is malfunctioning or cannot function due to

being in a low-power state. Table 78 includes a list of events that will report messages

to the network management console.

NOTE: The GPIO11/SMBALERT# pin will trigger an event message (when enabled by the

GPIO11_ALERT_DISABLE bit) regardless of whether it is configured as a GPI or not.

Table 77. TCO Legacy/Compatible Mode SMBus Configuration

Host SMBus

TCO Slave

Intel® ICH8

SPD

(Slave) uCtrl

Legacy

Sensors

(Master or

Slave with

ALERT)

ASF

Sensors

(Master or

Slave)

TCO Compatible Mode

SMBus

Intel® AMT

SMBus

Controller 1

Intel® AMT

SMBus

Controller 2

SMLink

Table 78. Event Transitions that Cause Messages

Event Assertion? Deassertion? Comments

INTRUDER# pin yes no Must be in “S1 or hung S0” state

THRM# pin yes yes

Must be in “S1 or hung S0” state. Note

that the THRM# pin is isolated when

the core power is off, thus preventing

this event in S3-S5.

Watchdog Timer

Expired yes no (NA) “S1 or hung S0” state entered

GPIO[11]/

SMBALERT# pin yes yes Must be in “S1 or hung S0” state

BATLOW# yes yes Must be in “S1 or hung S0” state

CPU_PWR_FLR yes no “S1 or hung S0” state entered

Intel® ICH8 Family Datasheet 187

Functional Description

5.14.2.2 Advanced TCO Mode

Intel ICH8/ICH8M supports two modes of Advanced TCO. Intel® Activ e Management

Technology mode and BMC mode. To enable Advance TCO mode (AMT or BMC mode)

the TCOMODE bit 7 in the ICHSTRP0 register in the SPI device must be 1. See

Section 20.2.5.1 for details.

Advanced TCO Intel® Active Management Technology mode

In this mode, Intel AMT SMBus Controller 1, Host SMBus and SMLink are connected

together internally. See Figure below . This mode is enabled when the BMCMODE bit 15

in the ICHSTRP0 register in the SPI device is 0. See Section 20.2.5.1 for details.

The Intel AMT SMBus Controller 2 can be connected to either the SMBus pins or the

SMLink pins by the MESM2SEL bit 23 in the ICHSTRP0 register in the SPI device. See

Section 20.2.5.1 for details. The default is to have the Intel AMT SMBus Controller 2

connected to SMLink. The AMT SMBus Controller 2 has no connection to LINKALERT#.

5.14.2.3 Advanced TCO BMC Mode

In this mode, the external microcontroller (BMC) is connected to both SMLink and

SMBus. The BMC communicates with Management Engine through AMT SMBus

connected to SMLink. The host and TCO sla ve communicated with BMC through SMBus.

See figure below. This mode is enabled when the BMCMODE bit 15 in the ICHSTRP0

Figure 11. Advanced TCO Intel® AMT Mode SMBus/SMLink Configur ation

AMT SMBus

Controller 1

Host SMBus

Intel® ICH8

SPD

(Slave) uCtrl

Legacy

Sensors

(Master or

Slave with

ALERT)

ASF

Sensors

(Master or

Slave)

Advanced TCO AMT Mode

AMT SMBus

Controller 2

SMBus

TCO Slave

Embedded

Controller

SMLink

Intel® AMT

SMBus

Controller 1

Host SMBus

SPD

(Slave) uCtrl

Legacy

Sensors

(Master or

Slave with

ALERT)

ASF

Sensors

(Master or

Slave)

Advanced TCO AMT Mode

Intel® AMT

SMBus

Controller 2

SMBus

TCO Slave

Embedded

Controller

SMLink

Functional Description

188 Intel® ICH8 Family Datasheet

Figure 12. Advanced TCO BMC Mode SMBu s/SMLink Configuration

Host SMBus

TCO Slave

Intel® ICH8

SPD

(Slave)

Legacy

Sensors

(Master or

Slave with

ALERT)

ASF

Sensors

(Master or

Slave)

Advanced TCO BMC Mode

Intel® AMT

SMBus

Controller 1

SMBus

BMC

SMLink

Intel® AMT

SMBus

Controller 2

Intel® ICH8 Family Datasheet 189

Functional Description

5.15 IDE Controller (D31:F1) (Mobile Only)

The ICH8 IDE controller features one set of interface signals that can be enabled, tri-

stated or driven low.

The IDE interfaces of the ICH8 can support several types of data transfers:

•Programmed I/O (PIO): Processor is in control of the data transfer.

•8237 style DMA: DMA protocol that resembles the DMA on the ISA bus, although

it does not use the 8237 in the ICH8. This protocol off loads the processor from

moving data. This allows higher transfer rate of up to 16 MB/s.

•Ultra ATA/33: DMA protocol that redefines signals on the IDE cable to allow both

host and target throttling of data and transfer rates of up to 33 MB/s.

•Ultra ATA/66: DMA protocol that redefines signals on the IDE cable to allow both

host and target throttling of data and transfer rates of up to 66 MB/s.

•Ultra ATA/10 0: DMA protocol that redefines signals on the IDE cable to allow both

host and target throttling of data and transfer rates of up to 100 MB/s.

5.15.1 PIO Transfers

The ICH8 IDE controller includes both compatible and fast timing modes. The fast

timing modes can be enabled only for the IDE data ports. All other transactions to the

IDE registers are run in single transaction mode with compatible timings.

Up to two IDE devices may be attached to the IDE connector (drive 0 and drive 1). The

IDE_TIMP and IDE_TIMS Registers permit different timing modes to be programmed

for drive 0 and drive 1 of the same connector.

The Ultra ATA/33/66/100 synchronous DMA timing modes can also be applied to each

drive by programming the IDE I/O Configuration register and the Synchronous DMA

Control and Timing registers. When a drive is enabled for synchronous DMA mode

operation, the DMA tr ansfers are executed with the synchronous DMA timings. The PIO

transfers are executed using compatible timings or fast timings if also enabled.

5.15.1.1 PIO IDE Timing Modes

IDE data port transaction latency consists of startup latency, cycle latency, and

shutdown latency. Startup latency is incurred when a PCI master cycle targeting the

IDE data port is decoded and the DA[2:0] and CSxx# lines are not set up. Startup

latency provides the setup time for the DA[2:0] and CSxx# lines prior to assertion of

the read and write strobes (DIOR# and DIOW#).

Cycle latency consists of the I/O command strobe assertion length and recovery time.

Recovery time is provided so that transactions may occur back-to-back on the IDE

interface (without incurring startup and shutdown latency) without violating minimum

cycle periods for the IDE interface. The command strobe assertion width for the

enhanced timing mode is selected by the IDE_TIM Register and may be set to 2, 3, 4,

or 5 PCI clocks. The recovery time is selected by the IDE_TIM R egister and may be set

to 1, 2, 3, or 4 PCI clocks.

If IORDY is asserted when the initial sample point is reached, no wait -states are added

to the command strobe assertion length. If IORDY is negated when the initial sample

point is reached, additional wait -states are added. Since the rising edge of IORDY must

be synchronized, at least two additional PCI clocks are added.

Functional Description

190 Intel® ICH8 Family Datasheet

Shutdown latency is incurred after outstanding scheduled IDE data port transactions

(either a non-empty write post buffer or an outstanding read prefetch cycles) have

completed and before other transactions can proceed. It provides hold time on the

DA[2:0] and CSxx# lines with respect to the read and write strobes (DIOR# and

DIOW#). Shutdown latency is two PCI clocks in duration.

The IDE timings for various transaction types are shown in Table 79.

5.15.1.2 IORDY Masking

The IORDY signal can be ignored and assumed asserted at the first IORDY Sample Point

(ISP) on a drive by drive basis via the IDETIM Register.

5.15.1.3 PIO 32-Bit IDE D ata Port Accesses

A 32-bit PCI transaction run to the IDE data address (01F0h primary) results in two

back-to-back 16-bit transactions to the IDE data port. The 32-bit data port feature is

enabled for all timings, not just enhanced timing. For compatible timings, a shutdown

and startup latency is incurred between the two, 16-bit halves of the IDE transaction.

This assures that the chip selects are deasserted for at least two PCI clocks between

the two cycles.

5.15.1.4 PIO IDE Data Port Prefetching and Posting

The ICH8 can be programmed via the IDETIM registers to allow data to be posted to

and prefetched from the IDE data ports.

Data prefetching is initiated when a data port read occurs. Th e read prefetch elimi nates

latency to the IDE data ports and allows them to be performed back-to-back for the

highest possible PIO data transfer rates. The first data port read of a sector is called the

demand read. Subsequent data port reads from the sector are called prefetch reads.

The demand read and all prefetch reads much be of the same size (16 or 32 bits) –

software must not mix 32-bit and 16-bit reads.

Data posting is performed for writes to the IDE data ports. The transaction is completed

on the PCI bus after the data is received by the ICH8. The ICH8 then runs the IDE cycle

to transfer the data to the drive. If the IC H8 write buffer is non-empty and an unrelated

(non-data or opposite channel) IDE transaction occurs, that transaction will be stalled

until all current data in the write buffer is transferred to the drive. Only 16-bit buffer

writes are supported.

Table 79. IDE Transaction Timings (PCI Clocks)

IDE Transaction Type Startup

Latency

IORDY

Sample

Point (ISP)

Recovery Time

(RCT) Shutdown

Latency

Non-Data Port Compatible 4 11 22 2

Data Port Compatible 3 6 14 2

Fast Timing Mode 2 2–5 1–4 2

Intel® ICH8 Family Datasheet 191

Functional Description

5.15.2 Bus Master Function

The ICH8 can act as a PCI Bus master on behalf of an IDE device. One PCI Bus master

channel is provided for the IDE connector. By performing the IDE data transfer as a PCI

Bus master, the ICH8 off-loads the processor and improves system performance in

multitasking environments. Both devices attached to the connector can be

programmed for bus master transfers, but only one device can be active at a time.

5.15.2.1 Physical Region Descriptor Format

The physical memory region to be transferred is described by a Physical Region

Descriptor (PRD). The PRDs are stored sequentially in a Descriptor Table in memory.

The data transfer proceeds until all regions described by the PRDs in the table have

been transferred.

Descriptor Tables must not cross a 64-KB boundary. Each PRD entry in the table is

8 bytes in length. The first 4 bytes specify the byte address of a physical memory

region. This memory region must be dword-aligned and must not cross a 64-KB

boundary. The next two bytes specify the size or transfer count of the region in bytes

(64-KB limit per region). A value of 0 in these two bytes indicates 64-KB (thus the

minimum transfer count is 1). If bit 7 (EO T ) of the last byte is a 1, it indicates that this

is the final PRD in the Descriptor table. Bus master operation terminates when the last

descriptor has been retired.

When the Bus Master IDE controller is reading data from the memory regions, bit 1 of

the Base Address is masked and byte enables are asserted for all read tr ansfers. When

writing data, bit 1 of the Base Address is not masked and if set, will cause the lower

Word byte enables to be deasserted for the first dword transfer. The write to PCI

typically consists of a 32-byte cache line. If valid data ends prior to end of the cache

line, the byte enables will be deasserted for invalid data.

The total sum of the byte counts in every PRD of the descriptor table must be equal to

or greater than the size of the disk transfer request. If greater than the disk transfer

request, the driver must terminate the bus master transaction (by setting bit 0 in the

Bus Master IDE Command Register to 0) when the drive issues an interrupt to signal

transfer completion.

Figure 13. Physical Region Descriptor Table Entry

EOT Reserved Byte Count [15:1]

Memory Region Physical Base Address [31:1]

Byte 3Byte 2Byte 1Byte 0

Memory

Region

Main Memory

Functional Description

192 Intel® ICH8 Family Datasheet

5.15.2.2 Bus Master IDE Timings

The timing modes used for Bus Master IDE transfers are identical to those for PIO

transfers. The DMA Timing Enable Only bits in IDE Timing register can be used to

program fast timing mode for DMA transactions only. This is useful for IDE devices

whose DMA transfer timings are faster than its PIO transfer timings. The IDE device

DMA request signal is sampled on the same PCI clock that DIOR# or DIOW# is

deasserted. If inactive, the DMA Acknowledge signal is deasserted on the next PCI

clock and no more transfers take place until DMA request is asserted again.

5.15.2.3 Interrupts

The ICH8 can generate interrupts based upon a signal coming from the PAT A device, or

due to the completion of a PRD with the ‘I’ bit set. The interrupt is edge triggered and

active high. The PATA host controller generates IDEIRQ.

When the ICH8 IDE controller is operating independently from the SATA controller

(D31:F2), IDEIRQ will generate IRQ14. When operating in conjunction with the SATA

controller (combined mode), IDE interrupts will still generate IDEIRQ, but this may in

turn generate either IRQ14 or IRQ15, depending upon the value of the MAP.MV

(D31:F2:90h:bits 1:0) register. When in combined mode and the SATA controller is

emulating the logical secondary channel (MAP.MV = 1h), the PATA channel will emulate

the logical primary channel and IDEIRQ will generate IRQ14. Conversely, if the SATA

controller in combined mode is emulating the logical primary channel (MAP.MV=2h),

IDEIRQ will generate IRQ15.

Note: IDE interrupts cannot be communicated through PCI devices or the serial IRQ stream.

5.15.2.4 Bus Master IDE Operation

To initiate a bus master transfer between memory and an IDE device, the following

steps are required:

1. Software prepares a PRD table in system memory. The PRD table must be dword-

aligned and must not cross a 64-KB boundary.

2. Software provides the starting address of the PRD Table by loading the PRD Table

Pointer Register. The direction of the data transfer is specified by setting the Read/

Write Control bit. The interrupt bit and Error bit in the Status register are cleared.

3. Software issues the appropriate DMA transfer command to the disk device.

4. The bus master function is engaged by software writing a 1 to the Start bit in the

Command Register. The first entry in the PRD table is fetched and loaded into two

registers which are not visible by software, the Current Base and Current Count

registers. These registers hold the current value of the address and byte count

loaded from the PRD table. The value in these registers is only va lid when there is

an active command to an IDE device.

5. Once the PRD is loaded internally, the IDE device will receive a DMA acknowledge.

6. The controller transfers data to/from memory responding to DMA requests from the

IDE device. The IDE device and the host controller may or may not throttle the

transfer sever al times. When the last data tr ansfer for a region has been completed

on the IDE interface, the next descriptor is fetched from the table. The descriptor

contents are loaded into the Current Base and Current Count registers.

7. At the end of the transfer, the IDE device signals an interrupt.

8. In response to the interrupt, software resets the Start/Stop bit in the command

determine if the transfer completed successfully.

Intel® ICH8 Family Datasheet 193

Functional Description

The last PRD in a table has the End of List (EOL) bit set. The PCI bus master data

transfers terminate when the physical region described by the last PRD in the table has

been completely transferred. The active bit in the Status Register is reset and the

DDRQ signal is masked.

The buffer is flushed (when in the write state) or invalidated (when in the read state)

when a terminal count condition exists; that is, the current region descriptor has the

EOL bit set and that region has been exhausted. The buffer is also flushed (write state)

or invalidated (read state) when the Interrupt bit in the Bus Master IDE Status register

is set. Software that reads the status register and finds the Error bit reset, and either

the Active bit reset or the Interrupt bit set, can be assured that all data destined for

system memory has been transferred and that data is valid in system memory.

Table 80 describes how to interpret the Interrupt and Active bits in the Status Register

after a DMA transfer has started.

5.15.2.5 Error Conditions

IDE devices are sector based mass storage devices. The drivers handle errors on a

sector basis; either a sector is transferred successfully or it is not. A sector is

512 bytes.

If the IDE device does not complete the transfer due to a hardware or software error,

the command will eventually be stopped by the driver setting Command Start bit to 0

when the driver times out the disk transaction. Information in the IDE device registers

help isolate the cause of the problem.

If the controller encounters an error while doing the bus master transfers it will stop

the transfer (i.e., reset the Active bit in the Command register) and set the Error bit in

the Bus Master IDE Status register. The controller does not generate an interru pt when

this happens. The device driver can use device specific information (PCI Configuration

Space Status register and IDE Drive Register) to determine what caused the error.

Whenever a requested transfer does not complete properly, information in the IDE

device registers (Sector Count) can be used to determine how much of the transfer was

completed and to construct a new PRD table to complete the requested operation. In

most cases the existing PRD table can be used to complete the operation.

Table 80. Interrupt/Active Bit Interaction Definition

Interrupt Active Description

DMA transfer is in progress. No interrupt has been generated by the IDE

device.

The IDE device generated an interrupt. The controller exhausted the

Physical Region Descriptors. This is the normal completion case where

the size of the physical memory regions was equal to the IDE device

transfer size.

The IDE device generated an interrupt. The controller has not reached

the end of the physical memory regions. This is a valid completion case

where the size of the physical memory regions was larger than the IDE

device transfer size.

This bit combination signals an error condition. If the Error bit in the

status register is set, then the controller has some problem transferring

data to/from memory. Specifics of the error have to be determined using

bus-specific information. If the Error bit is not set, then the PRDs

specified a smaller size than the IDE transfer size.

Functional Description

194 Intel® ICH8 Family Datasheet

5.15.3 Ultra ATA/100/66/33 Protocol

The ICH8 supports Ultra ATA/100/66/33 bus maste ring protocol, providing support for

a variety of transfer speeds with IDE devices. Ultra ATA/33 provides transfers up to

33 MB/s, Ultra ATA/66 provides transfers at up to 44 MB/s or 66 MB/s, and

Ultra ATA/100 can achieve read transfer rates up to 100 MB/s and write transfer rates

up to 88.9 MB/s.

The Ultra ATA/100/66/33 definition also incorporates a Cyclic Redundancy Checking

(CRC-16) error checking protocol.

5.15.3.1 Operation

Initial setup programming consists of enabling and performing the proper configuration

of the ICH8 and the IDE device for Ultra ATA/100/66/33 operation. For the ICH8, this

consists of enabling synchronous DMA mode and setting up appropriate Synchronous

DMA timings.

When ready to transfer data to or from an IDE device, the Bus Master IDE

programming model is followed. Once programmed, the drive and ICH8 control the

transfer of data via the Ultra ATA/100/66/33 protocol. The actual data transfer consists

of three phases, a start-up phase, a data transfer phase, and a burst termination

phase.

The IDE device begins the start-up phase by asserting DMARQ signal. When ready to

begin the transfer, the ICH8 asserts DMACK# signal. When DMACK# signal is asserted,

the host controller drives CS0# and CS1# inactive, DA0–DA2 low . F or write cycles, the

ICH8 deasserts STOP, waits for the IDE device to assert DMARD Y#, and then drives the

first data word and STROBE signal. For read cycles, the ICH8 tri-states the DD lines,

deasserts STOP, and asserts DMARDY#. The IDE device then sends the first data word

and STROBE.

The data transfer phase continues the burst tr ansfers with the data transmitter (ICH8 –

writes, IDE device – reads) providing data and toggling STROBE. Data is transferred

(latched by receiver) on each rising and falling edge of STROBE. The transmitter can

pause the burst by holding STROBE high or low, resuming the burst by again toggling

STROBE. The receiver can pause the burst by deasserting DMARDY# and resumes the

transfers by asserting DMARDY#. The ICH8 pauses a burst transaction to prevent an

internal line buffer over or under flow condition, resuming once the condition has

cleared. It may also pause a transaction if the current PRD byte count has expired,

resuming once it has fetched the next PRD.

The current burst can be terminated by either the transmitter or receiver. A burst

termination consists of a Stop Request, Stop Acknowledge and transfer of CRC data.

The ICH8 can stop a burst by asserting STOP, with the IDE device acknowledging by

deasserting DMARQ. The IDE device stops a burst by deasserting DMARQ and the ICH8

acknowledges by asserting STOP. The transmitter then drives the STROBE signal to a

high level. The ICH8 then drives the CRC value onto the DD lines and deassert

DMACK#. The IDE device latches the CRC value on rising edge of DMACK#. The ICH8

terminates a burst transfer if it needs to service the opposite IDE channel, if a

Programmed I/O (PIO) cycle is executed to the IDE channel currently running the

burst, or upon transferring the last data from the final PRD.

Intel® ICH8 Family Datasheet 195

Functional Description

5.15.4 Ultra ATA/33/66/100 Timing

The timings for Ultra A TA/33/66/100 modes are programmed via the S ynchronous DMA

Timing register and the IDE Configuration register. Different timings can be

programmed for each drive in the system. The Base Clock frequency for each drive is

selected in the IDE Configuration register. The Cycle Time (CT) and Ready to Pause

(RP) time (defined as multiples of the Base Clock) are progr ammed in the Sy nchronous

DMA Timing Register. The Cycle Time represents the minimum pulse width of the data

strobe (STROBE) signal. The R eady to P ause time represents the number of Base Clock

periods that the ICH8 waits from deassertion of DMARDY# to the assertion of STOP

when it desires to stop a burst read transaction.

Note: The internal Base Clock for Ultra ATA/100 (Mode 5) runs at 133 MHz, and the Cycle

Time (CT) must be set for three Base Clocks. The ICH8 thus toggles the write strobe

signal every 22.5 ns, transferring two bytes of data on each strobe edge. This means

that the ICH8 performs Mode 5 write transfers at a maximum rate of 88.9 MB/s. For

read transfers, the read strobe is driven by the AT A/100 device, and the ICH8 supports

reads at the maximum rate of 100 MB/s.

5.15.5 ATA Swap Bay

To support PATA swap bay, the ICH8 allows the IDE output signals to be tri-stated and

input buffers to be turned off . This should be done prior to the removal of the drive. The

output signals can also be driven low. This can be used to remove charge built up on

the signals. Configuration bits are included in the IDE I/O Co nfiguration register, offset

54h in the IDE PCI configuration space.

In a PATA swap bay operation, an IDE device is removed and a new one inserted while

the IDE interface is powered down and the rest of the system is in a fully powered-on

state (SO). During a PATA swap bay operation, if the oper ating system ex ecutes cycles

to the IDE interface after it has been powered down it will cause the ICH8 to hang the

system that is waiting for IORDY to be asserted from the drive.

To correct this issue, the following BIOS procedures are required for performing an IDE

swap:

1. Program IDE SIG_MODE (Configuration register at offset 54h) to 10b (drive low

mode).

2. Clear IORDY Sample Point Enable (bits 1 or 5 of IDE Timing reg.). This prevents the

ICH8 from waiting for IORDY assertion when the operating system accesses the

IDE device after the IDE drive powers down, and ensures that 0s are always be

returned for read cycles that occur during swap operation.

Warning: Software should not attempt to control the outputs (either tri-state or driving low),

while an IDE transfer is in progress. Unpredictable results could occur, including a

system lockup.

5.15.6 SMI Trapping

Device 31:Function 1: Offset C0h (see Section 12.1.56) contain control for generating

SMI# on accesses to the IDE I/O spaces. These bits map to the legacy ranges

(1F0–1F7h and 3F6h). Accesses to one of these ranges with the appropriate bit set

causes the cycle to not be forwarded to the IDE controller, and for an SMI# to be

generated. If an access to the Bus-Master IDE registers occurs while trapping is

enabled for the device being accessed, then the register is updated, an SMI# is

generated, and the device activity status bits (Device 31 : Func ti on 1:Of fs e t C4h) are

updated indicating that a trap occurred.

Functional Description

196 Intel® ICH8 Family Datasheet

5.16 SATA Host Controller (D31:F2, F5)

The SATA function in the ICH8 has three modes of operation to support different

operating system conditions. In the case of Native IDE enabled operating systems, the

ICH8 utilizes two controllers to enable all six ports of the bus. The first controller

(Device 31: Function 2) supports ports 0 -3 and the second controller

(Device 31: Function 5) supports ports 4 and 5. When using a legacy operating system,

only one controller (Device 31: Function 2) is available that supports ports 0 – 3. In

AHCI or RAID mode, only one controller (Device 31: Function 2) is utilized enabling all

six ports.

The MAP register, Section 13.1.29, provides the ability to share PCI functions. When

sharing is enabled, all decode of I/O is done through the SATA registers. Device 31,

Function 1 (IDE controller) is hidden by software writing to the Function Disable

The ICH8 SATA controllers feature six (desktop only) / three (mobile only) sets of

interface signals (ports) that can be independently enabled or disabled (they cannot be

tri-stated or driven low). Each interface is supported by an independent DMA controller.

The ICH8 SATA controllers interact with an attached mass storage device through a

The host software follows existing standards and conventions when accessing the

Note: SATA interface transfer rates are independent of UDMA mode settings. SATA interface

transfer rates will operate at the bus’s maximum speed, regardless of the UDMA mode

reported by the SATA device or the system BIOS.

Table 81. SATA Feature Support

Feature ICH8

(AHCI/

RAID Disabled)

ICH8

(AHCI/

RAID Enabled)

Native Command Queuing (NCQ) N/A Supported

Auto Activate for DMA N/A Supported

Hot Plug Support N/A Supported

Asynchronous Signal Recovery N/A Supported

3 Gb/s Transfer Rate Supported Supported

ATAPI Asynchronous Notification N/A Supported

Host Initiated Power Management N/A Supported

(Mobile Only)

Staggered Spin-Up Supported Supported

Command Completion Coalescing N/A N/A

Port Multiplier N/A N/A

External SATA N/A Supported

(Desktop Only)

Intel® ICH8 Family Datasheet 197

Functional Description

5.16.1 Theory of Operation

5.16.1.1 Standard ATA Emulation

The ICH8 contains a set of registers that shadow the contents of the legacy IDE

registers. The behavior of the Command and Control Block registers, PIO, and DMA

data transfers, resets, and interrupts are all emulated.

Note: The ICHn will assert INTR when the master device completes the EDD command

regardless of the command completion status of the slave device. If the master

completes EDD first, an INTR is generated and BSY will remain '1' until the slave

completes the command. If the slave completes EDD first, BSY will be '0' when the

master completes the EDD command and asserts INTR. Software must wait for busy to

clear (0) before completing an EDD command, as required by the ATA5 through ATA7

(T13) industry standards.

5.16.1.2 48-Bit LBA Operation

The SATA host controller supports 48-bit LBA through the host-to-device register FIS

when accesses are performed via writes to the task file. The SATA host controller will

ensure that the correct data is put into the correct byte of the host-to-device FIS.

Table 82. SATA Feature Support

Feature Description

Native Command Queuing

(NCQ) Allows the device to reorder commands for more efficient data

transfers

Auto Activate for DMA Collapses a DMA Setup then DMA Activate sequence into a DMA

Setup only

Hot Plug Support Allows for device detection without power being applied and

ability to conne ct and disconnect devices without prior

notification to the system

Asynchronous Signal

Recovery Provides a recovery from a loss of signal or establishing

communication after hot plug

3 Gb/s Transfer Rate Capable of data transfers up to 3Gb/s

ATAPI Asynchronous

Notification A mechanism for a device to send a notification to the host that

the device requires attention

Host Initiated Power

Management Capability for the host controller to request Partial and Slumber

interface power states

Staggered Spin-Up Enables the host the ability to spin up hard drives sequentially to

prevent power load problems on boot

Command Completion

Coalescing

Reduces interrupt and completion overhead by allowing a

specified number of commands to complete and then generating

an interrupt t o process the commands

Port Multiplier A mechanism for one active host connection to communicate

with multiple devices

External SATA Technology that allows for an outside the box connection of up to

2 meters (when using the cable defined in SATA-IO)

Functional Description

198 Intel® ICH8 Family Datasheet

There are special considerations when reading from the task file to support 48-bit LBA

operation. Software may need to read all 16-bits. Since the registers are only 8-bits

wide and act as a FIFO, a bit must be set in the device/control register, which is at

offset 3F6h for primary and 376h for secondary (or their native counterparts).

If software clears bit 7 of the control register before performing a read, the last item

written will be returned from the FIFO. If software sets bit 7 of the control register

before performing a read, the first item written will be returned from the FIFO.

5.16.2 SATA Swap Bay Support

Dynamic Hot-Plug (e.g., surprise removal) is not supported by the SATA host controller

without special support from AHCI and the proper board hardware. However, the ICH8

does provide for basic SATA swap bay support using the PSC register configur ation bits

and power management flows. A device can be powered down by software and the port

can then be disabled, allowing removal and insertion of a new device.

Note: This SATA swap bay operation requires board hardware (implementation specific),

BIOS, and operating system support.

5.16.3 Intel® Matrix Storage Technology Configuration (Intel®

ICH8R, ICH8DH, ICH8DO, and ICH8M-E Only)

The Intel® Matrix Storage Technology offers several diverse options for RAID

(redundant array of independent disks) to meet the needs of the end user. AHCI

support provides higher performance and alleviates disk bottlenecks by taking

advantage of the independent DMA engines that each SATA port offers in ICH8.

• RAID Level 0 performance scaling up to 4 drives, enabling higher throughput for

data intensive applications such as video editing.

• Data security is offered through RAID Level 1, which performs mirroring.

• RAID Level 10 provid es high levels of storage performance with data protection,

combining the fault-tolerance of RAID Level 1 with the performance of RAID Level

0. By striping RAID Level 1 segments, high I/O rates can be achieved on systems

that require both performance and fault-tolerance. RAID Level 10 requires 4 hard

drives, and provides the capacity of two drives.

• RAID Level 5 provides highly efficient storage while maintaining fault-tolerance on

3 or more drives. By striping parity, and rotating it across all disks, fault tolerance

of any single drive is achieved while only consuming 1 driv e worth of capacity. That

is, a 3 drive RAID 5 has the capacity of 2 drives, or a 4 drive RAID 5 has the

capacity of 3 drives. RAID 5 has high read transaction rates, with a medium write

rate. RAID 5 is well suited for applications that require high amounts of storage

while maintaining fault tolerance.

By using the ICH8’s built-in Intel Matrix Storage Technology, there is no loss of PCI

resources (request/grant pair) or add-in card slot.

Intel® Matrix Storage Technology functionality requires the following items:

1. ICH8 component enabled for Intel Matrix Storage Technology (see Section 1.2)

2. Intel® Matrix Storage Manager RAID Option ROM must be on the platform

3. Intel® Matrix Storage Manager drivers, most recent revision.

4. At least two SATA hard disk drives (minimum depends on RAID configuration).

Intel Matrix Storage Technology is not available in the following configurations:

1. The SATA controller in compatible mode.

Intel® ICH8 Family Datasheet 199

Functional Description

5.16.3.1 Intel® Matrix Storage Manager RAID Option ROM

The Intel Matrix Storage Manager RAID Option ROM is a standard PnP Option ROM that

is easily integrated into any System BIOS. When in place, it provides the following

three primary functions:

• Provides a text mode user interface that allows the user to manage the RAID

configuration on the system in a pre-oper ating system environment. Its feature set

is kept simple to keep size to a minimum, but allows the user to create & delete

RAID volumes and select recovery options when problems occur.

• Provides boot support when using a RAID volume as a boot disk. It does this by

providing Int13 services when a RAID volume needs to be accessed by DOS

applications (such as NTLDR) and by exporting the RAID volumes to the System

BIOS for selection in the boot order.

• At each boot up, provides the user with a status of the RAID volumes and the

option to enter the user interface by pressing CTRL-I.

5.16.4 Power Management Operation

Power management of the ICH8 SATA controller and ports will cover operations of the

host controller and the SATA wire.

5.16.4.1 Power State Mappings

The D0 PCI power management state for device is supported by the ICH8 SATA

controller.

SATA devices may also have multiple power states. From parallel ATA, three device

states are supported through ACPI. They are:

• D0 – Device is working and instantly available.

• D1 – device enters when it receives a ST ANDBY IMMEDIATE command. Exit latency

from this state is in seconds

• D3 – from the SATA device’s perspective, no different than a D1 state, in that it is

entered via the STANDBY IMMEDIATE command. However, an ACPI method is also

called which will reset the device and then cut its power.

Each of these device states are subsets of the host controller’s D0 state.

Finally, SA TA defines three PHY layer power states, which have no equiv alent mappings

to parallel ATA. They are:

• PHY READY – PHY logic and PLL are both on and active

• Partial – PHY logic is powered, but in a reduced state. Exit latency is no longer than

10 ns

• Slumber – PHY logic is powered, but in a reduced state. Exit latency can be up to

10 ms.

Since these states have much lower exit latency than the ACPI D1 and D3 states, the

SATA controller defines these states as sub-states of the device D0 state.

Functional Description

200 Intel® ICH8 Family Datasheet

5.16.4.2 Power State Transitions

5.16.4.2.1 Partial and Slumber State Entry/Exit

The partial and slumber states save interface power when the interface is idle. It would

be most analogous to PCI CLKRUN# (in power savings, not in mechanism), where the

interface can have power saved while no commands are pending. The SATA controller

defines PHY layer power management (as performed via primitives) as a driver

operation from the host side, and a device proprietary mechanism on the device side.

The SATA controller accepts device transition types, but does not issue any transitions

as a host. All received requests from a SATA device will be ACKed.

When an operation is performed to the SATA controller such that it needs to use the

SATA cable, the controller must check whether the link is in the Partial or Slumber

states, and if so, must issue a COM_WAKE to bring the link back online. Similarly, the

SATA device must perform the same action.

5.16.4.2.2 Device D1, D3 States

These states are entered after some period of time when software has determined that

no commands will be sent to this device for some time. The mechanism for putting a

device in these states does not involve any work on the host controller, other then

sending commands over the interface to the device. Th e command most likely to be

used in ATA/ATAPI is the “STANDBY IMMEDIATE” command.

5.16.4.2.3 Host Controller D3HOT State

After the interface and device have been put into a low power state, the SATA host

controller may be put into a low power state. This is performed via the PCI power

management registers in configuration space. There are two very important aspects to

note when using PCI power management.

1. When the power state is D3, only accesses to configur ation space are allowed. Any

attempt to access the memory or I/O spaces will result in master abort.

2. When the power state is D3, no interrupts may be generated, even if they are

enabled. If an interrupt status bit is pending when the controller transitions to D0,

an interrupt may be generated.

When the controller is put into D3, it is assumed that software has properly shut down

the device and disabled the ports. Therefore, there is no ne ed to sustai n an y values on

the port wires. The interface will be treated as if no device is present on the cable, and

power will be minimized.

When returning from a D3 state, an internal reset will not be performed.

Figure 14. SATA Power States

Intel® ICH SATA Controller = D0

Device = D3

Power

Resume Latency

Device = D0

PHY =

Ready

Device = D1

PHY =

Slumber

PHY =

Partial PHY =

Off (port

disabled)

PHY =

Slumber PHY =

Off (port

disabled)

PHY =

Slumber PHY =

Off (port

disabled)

Intel® ICH8 Family Datasheet 201

Functional Description

5.16.4.2.4 Non-AHCI Mode PME# Generation

When in non-AHCI mode (legacy mode) of operation, the SATA controller does not

generate PME#. This includes attach events (since the port must be disabled), or

interlock switch events (via the SATAGP pins).

5.16.4.3 SMI Trapping (APM)

Device 31:Function2:Offset C0h (see Section 12.1.56) contain control for generating SMI#

on accesses to the IDE I/O spaces. These bits map to the legacy ranges

(1F0–1F7h, 3F6h, 170–177h, and 376h). If the SA TA controller is in legacy mode and is

using these addresses, accesses to one of these ranges with the appropriate bit set

causes the cycle to not be forwarded to the SATA controller, and for an SMI# to be

generated. If an access to the Bus-Master IDE registers occurs while trapping is

enabled for the device being accessed, then the register is updated, an SMI# is

generated, and the device activity status bits (Section 12.1.56) are updated indicating

that a trap occurred.

5.16.5 SATA LED

The SATALED# output is driven whenever the BSY bit is set in any SATA port. The

SATALED# is an active-low open-collector output. When SATALED# is low, the LED

should be active. When SATALED# is high, the LED should be inactive.

5.16.6 AHCI Operation

The ICH8 provides hardware support for Advanced Host Controller Interface (AHCI), a

programming interface for SATA host controllers developed through a joint industry

effort. AHCI defines transactions between the SA T A controller and software and enables

advanced performance and usability with SATA. Platforms supporting AHCI may take

advantage of performance features such as no master/slave designation for SATA

devices—each device is treated as a master—and hardware assisted native command

queuing. AHCI also provides usability enhancements such as Hot-Plug. AHCI requires

appropriate software support (e.g., an AHCI driv er) and for some features, hardware

support in the SATA device or additional platform hardware.

The ICH8 supports all of the mandatory features of the Serial ATA Advanced Host

Controller Interface Specification, Revision 1.0 and many optional features, such as

hardware assisted native command queuing, aggressive power management, LED

indicator support, and Hot-Plug through the use of interlock switch support (additional

platform hardware and softw are may be required depending upon the implementation).

Note: For reliable device removal notification while in AHCI operation without the use of

interlock switches (surprise removal), interface power management should be disabled

for the associated port. See Section 7.3.1 of the AHCI Specification for more

information.

Functional Description

202 Intel® ICH8 Family Datasheet

5.16.7 Serial ATA Reference Clock Low Power Request

(SATACLKREQ#)

The 100 MHz Serial A T A R eference Clock (SA T ACLKP, SA T ACLKN) is implemented on the

system as a ground-terminated low-v oltage differential signal pair driven by the system

Clock Chip. When all the SATA links are in Slumber or disabled, the SATA Reference

Clock is not needed and may be stopped and tri-stated at the clock chip allowing

system-level power reductions.

The ICH8 uses the S ATACLKREQ# output signal to communicate with the system Clock

Chip to request either SATA clock running or to tell the system clock chip that it can

stop the SATA Reference Clock. ICH8 drives this signal low to request clock running,

and tristates the signal to indicate that the SATA Reference Clock may be stopped (the

ICH8 never drives the pin h igh). When the S ATACLKREQ# is tristated by the ICH8, the

clock chip may stop the SATA Reference Clock within 100 ns, anytime after 100 ns, or

not at all. If the SATA Reference Clock is not already running, it will start within 100 ns

after a SATACLKREQ# is driven low by the ICH8.

To enable SATA Reference Clock Low Power Request:

1. Configure GPIO35 to native function

2. Set SATA Clock Request Enable (SCRE) bit to ‘1’ (Dev 31:F2:Offset 94h:bit 28).

Note: The reset default for SATACLKREQ# is low to ensure that the SATA Reference Clock is

running after system reset.

5.16.8 SGPIO Signals

The SGPIO signals, in accordance to the SFF-8485 specification, support per-port LED

signaling. These signals are not related to SATALED#, which allows for simplified

indication of SATA command activity. The SGPIO group interfaces with an external

controller chip that fetches and serializes the data for driving across the SGPIO bus.

The output signals then control the LEDs.

5.16.9 External SATA (Intel® ICH8R, ICH8DH, and ICH8DO Only)

ICH8 supports external SATA. External SATA uses the SATA interface outside of the

system box. The usage model for this feature must comply with the Serial ATA II

Cables and Connectors Volume 2 Gold specification at www.sata-io.org. Intel validates

two configurations:

1. The "cable-up" solution involves an internal SATA cable that connects to the SATA

motherboard connector and spans to a back panel PCI bracket with an e-SATA

connector. A separate e-SATA cable is required to connect an e-SATA device.

2. The back-panel solution involves running a trace to the I/O back panel and

connecting a device via an external SATA connector on the board.

Note: Port multipliers are not supported on ICH8. There is no hot plugging of the OS host

device. Intel® Matrix Storage Technology must be present to support external SATA.

Intel® ICH8 Family Datasheet 203

Functional Description

5.17 High Precision Event Timers

This function provides a set of timers that can be used by the operating system. The

timers are defined such that in the future, the operating system ma y be able to assign

specific timers to used directly by specific applications. Each timer can be configured to

cause a separate interrupt.

ICH8 provides three timers. The three timers are implemented as a single counter each

with its own comparator and v alue register. This counter increases monotonically. Each

individual timer can generate an interrupt when the value in its value register matches

the value in the main counter.

The registers associated with these timers are mapped to a memory space (much like

the I/O APIC). However, it is not implemented as a standard PCI function. The BIOS

reports to the operating system the location of the register space. The hardware can

support an assignable decode space; however, the BIOS sets this space prior to

handing it over to the operating system (See Section 6.4). It is not expected that the

operating system will move the location of these timers once it is set by the BIOS.

5.17.1 Timer Accuracy

1. The timers are accurate over any 1 ms period to within 0.05% of the time specified

in the timer resolution fields.

2. Within any 100 microsecond period, the timer reports a time that is up to two ticks

too early or too late. Each tick is less than or equal to 100 ns, so this represents an

error of less than 0.2%.

3. The timer is monotonic. It does not return the same value on two consecutive

reads (unless the counter has rolled over and reached the same value).

The main counter is clocked by the 14.31818 MHz clock, synchronized into the

66.666 MHz domain. This results in a non-uniform duty cycle on the synchronized

clock, but does have the correct av erage period. The accur acy of the main counter is as

accurate as the 14.3818 MHz clock.

5.17.2 Interrupt Mapping

Mapping Option #1 (Legacy Replacement Option)

In this case, the Legacy Replacement Rout bit (LEG_RT_CNF) is set. This forces the

mapping found in Table 83.

Mapping Option #2 (Standard Option)

In this case, the Legacy Replacement Rout bit (LEG_RT_CNF) is 0. Each timer has its

own routing control. The supported interrupt values are IRQ 20, 21, 22, and 23.

Table 83. Legacy Replacement Routing

Timer 8259 Mapping APIC Mapping Comment

0IRQ0 IRQ2

In this case, the 8254 timer will

not cause any interrupts

1IRQ8 IRQ8

In this case, the R TC will not cause

any interrupts.

2 Per IRQ Routing Field. Per IRQ Routing Field

Functional Description

204 Intel® ICH8 Family Datasheet

5.17.3 Periodic vs. Non-Periodic Modes

Non-Periodic Mode

Timer 0 is configurable to 32 (default) or 64-bit mode, whereas Timers 1 and 2 only

support 32-bit mode (See Section 19.1.5).

All three timers support non-periodic mode.

Consult Section 2.3.9.2.1 of the IA-PC HPET Specification for a description of this

mode.

Periodic Mode

Timer 0 is the only timer that supports periodic mode. Consult Section 2.3.9.2.2 of the

IA-PC HPET Specification for a description of this mode.

The following usage model is expected:

1. Softw a re cl ears th e EN ABLE_CNF bit to pre v e n t an y i nterrupts

2. Software Clears the main counter by writing a value of 00h to it.

3. Softw a re sets the TI M ER 0 _ VAL_SET_CNF bit.

4. Software writes the new value in the TIMER0_COMPARATOR_VAL register

5. Softw a re s ets the EN AB LE_CNF bit to enable interrupts.

The Timer 0 Comparator Value register cannot be prog rammed reliably by a single 64-

bit write in a 32-bit environment except if only the periodic rate is being changed

during run-time. If the actual Timer 0 Comparator Value needs to be reinitialized, then

the following software solution will always work regardless of the environment:

1. Set TIMER0_VAL_SET_CNF bit

2. Set the lower 32 bits of the Timer0 Comparator Value register

3. Set TIMER0_VAL_SET_CNF bit

4. 4) Set the upper 32 bits of the Timer0 Comparator Value register

5.17.4 Enabling the Timers

The BIOS or operating system PnP code should route the interrupts. This includes the

Legacy Rout bit, Interrupt Rout bit (for each timer), interrupt type (to select the edge

or level type for each timer)

The Device Driver code should do the following for an available timer:

1. Set the Overall Enable bit (Offset 04h, bit 0).

2. Set the timer type field (selects one-shot or periodic).

3. Set the interrupt enable

4. Set the comparator value

Intel® ICH8 Family Datasheet 205

Functional Description

5.17.5 Interrupt Levels

Interrupts directed to the internal 8259s are active high. See Section 5.9 for

information regarding the polarity programming of the I/O APIC for detecting internal

interrupts.

If the interrupts are mapped to the I/O APIC and set for level-triggered mode, they can

be shared with PCI interrupts. This may be shared although it’s unlikely for the

operating system to attempt to do this.

If more than one timer is configured to share the same IRQ (using the

TIMERn_INT_ROUT_CNF fields), then the software must configure the timers to level-

triggered mode. Edge-triggered interrupts cannot be shared.

5.17.6 Handling Interrupts

If each timer has a unique interrupt and the timer has been configured for edge-

triggered mode, then there are no specific steps required. No read is required to

process the interrupt.

If a timer has been configured to level-triggered mode, then its interrupt must be

cleared by the software. This is done by reading the interrupt status register and

writing a 1 back to the bit position for the interrupt to be cleared.

Independent of the mode, software can read the value in the main counter to see how

time has passed between when the interrupt was generated and when it was first

serviced.

If Timer 0 is set up to generate a periodic interrupt, the softw are can check to see how

much time remains until the next interrupt by checking the timer value register.

5.17.7 Issues Related to 64-Bit Timers with 32-Bit Processors

A 32-bit timer can be read directly using processors that are capable of 32-bit or 64-bit

instructions. However, a 32-bit processor may not be able to directly read 64-bit timer.

A race condition comes up if a 32-bit processor reads the 64-bit register using two

separate 32-bit reads. The danger is that just after reading one half, the other half rolls

over and changes the first half.

If a 32-bit processor needs to access a 64-bit timer, it must first halt the timer before

reading both the upper and lower 32-bits of the timer. If a 32-bit processor does not

want to halt the timer, it can use the 64-bit timer as a 32-bit timer by setting the

TIMERn_32MODE_CNF bit. This causes the timer to behave as a 32-bit timer. The upper

32-bits are always 0.

Functional Description

206 Intel® ICH8 Family Datasheet

5.18 USB UHCI Host Controllers (D29:F0, F1, F2 and

D26:F0, F1)

The ICH8 contains five USB full/low-speed host controllers that support the standard

Universal Host Controller Interface (UHCI), Revision 1.1. Each UHCI Host Controller

(UHC) includes a root hub with two separate USB ports each, for a total of ten USB

ports.

• Overcurrent detection on all ten USB ports is supported. The overcurrent inputs are

not 5 V tolerant, and can be used as GPIs if not needed.

• The ICH8’s UHCI host controllers are arbitrated differently than standard PCI

devices to improve arbitration latency.

• The UHCI controllers use the Analog Front End (AFE) embedded cell that allows

support for USB full-speed signaling rates, instead of USB I/O buffers.

5.18.1 Data Structures in Main Memory

Section 3.1 - 3.3 of the Universal Host Controller Interface Specification, Revision 1.1

details the data structures used to communicate control, status, and data between

software and the ICH8.

5.18.2 Data Transfers to/from Main Memory

Section 3.4 of the Universal Host Controller Interface Specification, Revision 1.1

describes the details on how HCD and the ICH8 communicate via the Schedule data

structures.

5.18.3 Data Encoding and Bit Stuffing

The ICH8 USB employs NRZI data encoding (Non-Return to Zero Inverted) when

transmitting packets. Full details on this implementation are given in the Universal

Serial Bus Specification, Revision 2.0.

5.18.4 Bus Protocol

5.18.4.1 Bit Ordering

Bits are sent out onto the bus least significant bit (LSb) first, followed by next LSb,

through to the most significant bit (MSb) last.

5.18.4.2 SYNC Field

All packets begin with a synchronization (SYNC) field, which is a coded sequence that

generates a maximum edge transition density. The SYNC field appears on the bus as

IDLE followed by the binary string “KJKJKJKK,” in its NRZI encoding. It is used by the

input circuitry to align incoming data with the local clock and is defined to be 8 bits in

length. SYNC serves only as a sy nchronizat ion mechanism. Full details are given in the

Universal Serial Bus Specification, Revision 2.0, in Section 8.3.1. The last two bits in

the SYNC field are a marker that is used to identify the first bit of the PID. All

subsequent bits in the packet must be indexed from this point.

5.18.4.3 Packet Field Formats

All packets hav e distinct start and end of pack et delimiters. Full details are given in the

Universal Serial Bus Specification, Revision 2.0, in Section 8.3.1.

Intel® ICH8 Family Datasheet 207

Functional Description

5.18.4.4 Address Fields

Function endpoints are addressed using the function address field and the endpoint

field. Full details on this are given in the Universal Serial Bus Specification, Revision

2.0, in Section 8.3.2.

5.18.4.5 Frame Number Field

The frame number field is an 11-bit field that is incremented by the host on a per frame

basis. The fr ame number field rolls ov er upon reaching its maximum v alue of 7FFh, and

is sent only for SOF tokens at the start of each frame.

5.18.4.6 Data Field

The data field may range from 0 to 1023 bytes and must be an integral numbers of

bytes. Data bits within each byte are shifted out LSB first.

5.18.4.7 Cyclic Redundancy Check (CRC)

CRC is used to protect the all no n-PID fields in tok en and data pack ets. In this context,

these fields are considered to be protected fields. Full details on this are given in the

Universal Serial Bus Specification, Revision 2.0, in Section 8.3.5.

5.18.5 Packet Formats

The USB protocol calls out several packet types: token, data, and handshake packets.

Full details on this are given in the Universal Serial Bus Specification, Revision 2.0, in

section 8.4.

5.18.6 USB Interrupts

There are two general groups of USB interrupt sources, those resulting from execution

of transactions in the schedule, and those resulting from an ICH8 operation error. All

transaction-based sources can be masked by software through the ICH8’s Interrupt

Enable register. Additionally, individual transfer descriptors can be marked to generate

an interrupt on completion.

When the ICH8 driv es an inte rrupt for U SB , it internally drives the PIRQA# pin for USB

function #0 and USB function #3, PIRQD# pin for USB function #1, and the PIRQC#

pin for USB function #2, until all sources of the interrupt are cleared. In order to

accommodate some operating systems, the Interrupt Pin register must contain a

different value for each function of this new multi-function device.

5.18.6.1 Transaction-Based Interrupts

These interrupts are not signaled until after the status for the last complete transaction

in the frame has been written back to host memory. This assures that software can

safely process through (Frame List Current Index -1) when it is servicing an interrupt.

CRC Error / Time-Out

A CRC/Time-Out error occurs when a packet tr ansmitted from the ICH8 to a USB device

or a packet tr ansmitted from a USB device to the ICH8 generates a CRC error. The ICH8

is informed of this event by a time-out from the USB device or by the ICH8’s CRC

checker generating an error on reception of the packet. Additionally, a USB bus time-

out occurs when USB devices do not respond to a transaction phase within 19-bit times

of an EOP. Either of these conditions causes the C_ERR field of the TD to decrement.

Functional Description

208 Intel® ICH8 Family Datasheet

When the C_ERR field decrements to 0, the following occurs:

• The Active bit in the TD is cleared

• The Stalled bit in the TD is set

• The CRC/Time-out bit in the TD is set.

• At the end of the frame, the USB Error Interrupt bit is set in the HC status register.

If the CRC/Time out interrupt is enabled in the Interrupt Enable register, a hardware

interrupt will be signaled to the system.

Interrupt on Completion

Transfer Descriptors contain a bit that can be set to cause an interrupt on their

completion. The completion of the transaction associated with that block causes the

USB Interrupt bit in the HC Status Register to be set at the end of the frame in which

the transfer completed. When a TD is encountered with the IOC bit set to 1, the IOC bit

in the HC Status register is set to 1 at the end of the frame if the active bit in the TD is

set to 0 (even if it was set to 0 when initially read).

If the IOC Enable bit of Interrupt Enable register (bit 2 of I/O offset 04h) is set, a

hardware interrupt is signaled to the system. The USB Interrupt bit in the HC status

completion is because of errors, the USB Error bit in the HC status register is also set.

Short Packet Detect

A transfer set is a collection of data which requires more than one USB transaction to

completely move the data across the USB . An example might be a large print file which

requires numerous TDs in multiple frames to completely transfer the data. R eception of

a data packet that is less than the endpoint’s Max Packet size during Control, Bulk or

Interrupt transfers signals the completion of the transfer set, even if there are active

TDs remaining for this transfer set. Setting the SPD bit in a TD indicates to the HC to

set the USB Interrupt bit in the HC status register at the end of the frame in which this

event occurs. This feature streamlines the processing of input on these transfer types.

If the Short Packet Interrupt Enable bit in the Interrupt Enable register is set, a

hardware interrupt is signaled to the system at the end of the frame where the event

occurred.

Serial Bus Babble

When a device transmits on the USB for a time greater than its assigned Max Length, it

is said to be babbling. Since isochrony can be destroyed by a babbling device, this error

results in the Active bit in the TD being cleared to 0 and the Stalled and Babble bits

being set to 1. The C_ERR field is not decremented for a babble. The USB Error

Interrupt bit in the HC Status register is set to 1 at the end of the frame. A hardware

interrupt is signaled to the system.

If an EOF babble was caused by the ICH8 (due to incorrect schedule for instance), the

ICH8 forces a bit stuff error followed by an EOP and the start of the next frame.

Stalled

This event indicates that a device/endpoint returned a STALL handshake during a

transaction or that the transaction ended in an error condition. The TDs Stalled bit is

set and the Active bit is cleared. Reception of a STALL does not decrement the error

counter. A hardware interrupt is signaled to the system.

Intel® ICH8 Family Datasheet 209

Functional Description

Data Buffer Error

This event indicates that an overrun of incoming data or a under-run of outgoing data

has occurred for this tr ansaction. This would generally be cau sed by the ICH8 not being

able to access required data buffers in memory within necessary latency requirements.

Either of these conditions causes the C_ERR fie ld of the TD to be decremented.

When C_ERR decrements to 0, the Active bit in the TD is cleared, the Stalled bit is set,

the USB Error Interrupt bit in the HC Status register is set to 1 at the end of the fr am e

and a hardware interrupt is signaled to the system.

Bit Stuff Error

A bit stuff error results from the detection of a sequence of more that six 1s in a row

within the incoming data stream. This causes the C_ERR field of the TD to be

decremented. When the C_ERR field decrements to 0, the Activ e bit in the TD is cleared

to 0, the Stalled bit is set to 1, the USB Error Interrupt bit in the HC Status register is

set to 1 at the end of the frame and a hardware interrupt is signaled to the system.

5.18.6.2 Non-Transaction Based Interrupts

If an ICH8 process error or system error occur, the ICH8 halts and immediately issues a

hardware interrupt to the system.

Resume Received

This event indicates that the ICH8 receiv ed a RE SUME signal from a device on the USB

bus during a global suspend. If this interrupt is enabled in the Interrupt Enable register,

a hardware interrupt is signaled to the system allowing the USB to be brought out of

the suspend state and returned to normal operation.

ICH8 Process Error

The HC monitors certain critical fields during operation to ensure that it does not

process corrupted data structures. These include checking for a valid PID and verifying

that the MaxLength field is less than 1280. If it detects a condition that would indicate

that it is processing corrupted data structures, it immediately halts processing, sets the

HC Process Error bit in the HC Status register and signals a hardware interrupt to the

system.

This interrupt cannot be disabled through the Interrupt Enable register.

Host System Error

The ICH8 sets this bit to 1 when a Parity error, Master Abort, or Target Abort occur.

When this error occurs, the ICH8 clears the Run/Stop bit in the Command register to

prevent further execution of the scheduled TDs. This interrupt cannot be disabled

through the Interrupt Enable register.

Functional Description

210 Intel® ICH8 Family Datasheet

5.18.7 USB Power Management

The Host controller can be put into a suspended state and its power can be removed.

This requires that certain bits of information are retained in the resume power plane of

the ICH8 so that a device on a port may w ak e the system. Such a device ma y be a fax-

modem, which will wake up the machine to receive a fax or take a voice message. The

settings of the following bits in I/O space will be maintained when the ICH8 enters the

S3, S4, or S5 states.

When the ICH8 detects a resume event on any of its ports, it sets the corresponding

USB_STS bit in ACPI space. If USB is enabled as a wake/break event, the system

wakes up and an SCI generated.

5.18.8 USB Legacy Keyboard Operation

When a USB keyboard is plugged into the system, and a standard keyboard is not, the

system may not boot, and MS-DOS legacy softw are will not run, because the keyboard

will not be identified. The ICH8 implements a series of trapping operations which will

snoop accesses that go to the keyboard controller, and put the expected data from the

USB keyboard into the keyboard controller.

Note: The scheme described below assumes that the keyboard controller (8042 or

equivalent) is on the LPC bus.

This legacy operation is performed through SMM space. Figure 15 shows the Enable

and Status path. The latched SMI source (60R, 60W, 64R, 64W) is available in the

Status Register. Because the enable is after the latch, it is possible to check for other

events that didn't necessarily cause an SMI. It is the software's responsibility to

logically AND the value with the appropriate enable bits.

Note also that the SMI is generated before the PCI cycle completes (e.g. , before TRDY#

goes active) to ensure that the processor doesn't complete the cycle before the SMI is

observed. This method is used on MPIIX and has been validated.

The logic also needs to block the accesses to the 8042. If there is an external 8042,

then this is simply accomplished by not activating the 8042 CS. This is simply done by

logically ANDing the four enables (60R, 60W, 64R, 64W) with the 4 types of accesses to

determine if 8042CS should go active. An additional term is required for the “pass-

through” case.

The state table for the diagram is shown in Table 85.

Table 84. Bits Maintained in Low Power States

Command 00h 3 Enter Global Suspend Mode (EGSM)

Status 02h 2 Resume Detect

Port Status and

Control 10h & 12h

2 Port Enabled/Disabled

6 Resume Detect

8Low-speed Device Attached

12 Suspend

Intel® ICH8 Family Datasheet 211

Functional Description

Figure 15. USB Legacy Keyboard Flow Diagram

Table 85. USB Legacy Keyboard State Transitions

Current

State Action Data

Value Next

State Comment

IDLE 64h / Write D1h GateState1 Standard D1 command. Cycle passed

through to 8042. SMI# doesn't go active.

PSTATE (offset C0, bit 6) goes to 1.

IDLE 64h / Write Not D1h IDLE Bit 3 in Config Register determines if cycle

passed through to 8042 and if SMI#

generated.

IDLE 64h / Read N/A IDLE Bit 2 in Config Register determines if cycle

passed through to 8042 and if SMI#

generated.

IDLE 60h / Write Don't Care IDLE Bit 1 in Config Register determines if cycle

passed through to 8042 and if SMI#

generated.

IDLE 60h / Read N/A IDLE Bit 0 in Config Register determines if cycle

passed through to 8042 and if SMI#

generated.

GateState1 60h / Write XXh GateState2

Cycle passed through to 8042, even if trap

enabled in Bit 1 in Config R egister. No SMI#

generated. PSTATE remains 1. If data value

is not DFh or DDh then the 8042 m ay chose

to ignore it.

KBC Accesses

PCI Config

Read, Write

60 READ

Clear SMI_60_R

EN_SMI_ON_60R

Comb.

Decoder AND

Same for 60W, 64R, 64W

SMI

To Individual

"Caused By"

"Bits"

To PIRQD#

To "Caused By" Bit

AND

EN_PIRQD#

USB_IRQ

Clear USB_IRQ

EN_SMI_ON_IRQ

Functional Description

212 Intel® ICH8 Family Datasheet

GateState1 64h / Write D1h GateState1

Cycle passed through to 8042, even if trap

enabled via Bit 3 in Config Register. No SMI#

generated. PSTATE remains 1. Stay in

GateState1 because this is part of the

double-trigger sequence.

GateState1 64h / Write Not D1h ILDE

Bit 3 in Config space determines if cycle

passed through to 8042 and if SMI#

generated. PSTATE goes to 0. If Bit 7 in

Config Register is set, then SMI# should be

generated.

GateState1 60h / Read N/A IDLE

This is an invalid sequence. Bit 0 in Config

to 8042 and if SMI# generated. PST A TE goes

to 0. If Bit 7 in Config Register is set, then

SMI# should be generated.

GateState1 64h / Read N/A GateState1 Just stay in same state. Generate an SMI# if

enabled in Bit 2 of Config Register. PSTATE

remains 1.

GateState2 64 / Write FFh IDLE

Standard end of sequence. Cycle passed

through to 8042. PSTATE goes to 0. Bit 7 in

Config Space determines if SMI# should be

generated.

GateState2 64h / Write Not FFh IDLE

Improper end of sequence. Bit 3 in Config

to 8042 and if SMI# generated. PST A TE goes

to 0. If Bit 7 in Config Register is set, then

SMI# should be generated.

GateState2 64h / Read N/A GateState2 Just stay in same state. Generate an SMI# if

enabled in Bit 2 of Config Register. PSTATE

remains 1.

GateState2 60h / Write XXh IDLE

Improper end of sequence. Bit 1 in Config

to 8042 and if SMI# generated. PST A TE goes

to 0. If Bit 7 in Config Register is set, then

SMI# should be generated.

GateState2 60h / Read N/A IDLE

Improper end of sequence. Bit 0 in Config

to 8042 and if SMI# generated. PST A TE goes

to 0. If Bit 7 in Config Register is set, then

SMI# should be generated.

Table 85. USB Legacy Keyboard State Transitions

Current

State Action Data

Value Next

State Comment

Intel® ICH8 Family Datasheet 213

Functional Description

5.19 USB EHCI Host Controllers (D29:F7 and D26:F7)

The ICH8 contains two Enhanced Host Controller Interface (EHCI) host controllers

which support up to ten USB 2.0 high-speed root ports. USB 2.0 allows data transfers

up to 480 Mb/s using the same pins as the ten USB full-speed/low-speed ports. The

ICH8 contains port-routing logic that determines whether a USB port is controlled by

one of the UHCI controllers or by one of the EHCI controllers. US B 2.0 based Debug

Port is also implemented in the ICH8.

A summary of the key architectural differences between the USB UHCI host controllers

and the EHCI host controller are shown in Table 86.

5.19.1 EHC Initialization

The following descriptions step through the expected ICH8 Enhanced Host Controller

(EHC) initialization sequence in chronological order, beginning with a complete power

cycle in which the suspend well and core well have been off.

5.19.1.1 BIOS Initialization

BIOS performs a number of platform customization steps after the core well has

powered up. Contact your Intel Field Representative for additional ICH8 BIOS

information.

5.19.1.2 Driver Initialization

See Chapter 4 of the Enhanced Host Controller Interface Specification for Universal

Serial Bus, Revision 1.0.

Table 86. UHCI vs. EHCI

Parameter USB UHCI USB EHCI

Accessible by I/O space Memory Space

Memory Data Structure Single li nked list Separated in to Periodic and Asynchronous

lists

Differential Signal ing Voltage 3. 3 V 400 mV

Ports per Controller 2 6 (controller #1) and 4 (Controller #2)

Functional Description

214 Intel® ICH8 Family Datasheet

5.19.1.3 EHC Resets

In addition to the standard ICH8 hardware resets, portions of the EHC are reset by the

HCRESET bit and the tr ansition from th e D3 HOT device power management state to the

D0 state. The effects of each of these resets are listed in the following table.

If the detailed register descriptions give exceptions to these rules, those exceptions

override these rules. This summary is provid ed to help explain the reasons for the reset

policies.

5.19.2 Data Structures in Main Memory

See Section 3 and Appendix B of the Enhanced Host Controller Interface Specification

for Universal Serial Bus, Revision 1 .0 for details.

5.19.3 USB 2.0 Enhanced Host Controller DMA

The ICH8 USB 2.0 EHC implements three sources of USB packets. They are, in order of

priority on USB during each microframe:

1. The USB 2.0 Debug Port (see Section USB 2.0 Based Debug Port),

2. The Periodic DM A engine, and

3. The Async hronous DM A engine. The ICH8 al w ays performs any currently-pending

debug port transaction at the beginning of a microframe, followed by any pending

periodic traffic for the current microframe. If there is time left in the microframe,

then the EHC performs any pending asynchronous traffic until the end of the

microframe (EOF1). Note that the debug port traffic is only presented on one port

(Port #0), while the other ports are idle during this time.

5.19.4 Data Encoding and Bit Stuffing

See Chapter 8 of the Universal Serial Bus Specification, Revision 2.0.

5.19.5 Packet Formats

See Chapter 8 of the Universal Serial Bus Specification, Revision 2.0.

The ICH8 EHCI allows entrance to USB test modes, as defined in the USB 2.0

specification, including Test J, Test Pack et, etc. However note that the ICH8 Test Packet

test mode interpacket gap timing may not meet the USB 2.0 specification.

Reset Does Reset Does not Reset Comments

HCRESET bit set.

Memory space

registers except

Structural

Parameters (which is

written by BIOS).

Configuration

registers.

The HCRESET must only affect

registers that the EHCI driver

controls. PCI Configuration

space and BIOS-programmed

parameters can not be reset.

Software writes

the Device Power

State from D3HOT

(11b) to D0

(00b).

Core well registers

(except BIOS-

programmed

registers).

Suspend well

registers; BIOS-

programmed core

well registers.

The D3-to-D0 transition must

not cause wake information

(suspend well) to be lost. It also

must not clear BIOS-

programmed registers because

BIOS may not be invoked

following the D3-to-D0

transition.

Intel® ICH8 Family Datasheet 215

Functional Description

5.19.6 USB 2.0 Interrupts and Error Conditions

Section 4 of the Enhanced Host Controller Interface Specification for Universal Serial

Bus, Revision 1.0 goes into detail on the EHC interrupts and the error conditions that

cause them. All error conditions that the EHC detects can be reported through the EHCI

Interrupt status bits. Only ICH8-specific interrupt and error-reporting behavior is

documented in this section. The EHCI Interrupts Section must be read first, followed by

this section of the datasheet to fully comprehend the EHC interrupt and error-reporting

functionality.

• Based on the EHC’s Buffer sizes and buffer management policies, the Data Buffer

Error can never occur on the ICH8.

• Master Abort and Target Abort responses from hub interface on EHC-initiated read

packets will be treated as Fatal Host Errors. The EHC halts when these conditions

are encountered.

• The ICH8 may assert the interrupts which are based on the interrupt threshold as

soon as the status for the last complete transaction in the interrupt interval has

been posted in the internal write buffers. The requirement in the Enhanced Host

Controller Interface Specification for Universal Serial Bus, Revision 1.0 (that the

status is written to memory) is met internally, even though the write may not be

seen on DMI before the interrupt is asserted.

• Since the ICH8 supports the 1024-element Frame List size, the Frame List Rollover

interrupt occurs every 1024 milliseconds.

• The ICH8 delivers interrupts using PIRQH#.

• The ICH8 does not modify the CERR count on an Interrupt IN wh en the “Do

Complete-Split” execution criteria are not met.

• For complete-split transactions in the P eriodic list, the “Missed Microfr ame” bit does

not get set on a control-structure-fetch that fails the late-start test. If subsequent

accesses to that control structure do not fail the late-start test, then the “Missed

Microframe” bit will get set and written back.

5.19.6.1 Aborts on USB 2.0-Initiated Memory Reads

If a read initiated by the EHC is aborted, the EHC treats it as a fatal host error. The

following actions are taken when this occurs:

• The Host System Error status bit is set

• The DMA engines are halted after completing up to one more transaction on the

USB interface

• If enabled (by the Host System Error Enable), then an interrupt is generated

• If the status is Master Abort, then the Received Master Abort bit in configuration

space is set

• If the status is Target Abort, then the Received Target Abort bit in configuration

space is set

• If enabled (by the SERR Enable bit in the function’ s configuration space), then the

Signaled System Error bit in configuration bit is set.

Functional Description

216 Intel® ICH8 Family Datasheet

5.19.7 USB 2.0 Power Management

5.19.7.1 USB Pre-Fetch Pause Feature

The Pre-F etch Based Pause is a power management feature in USB (EHCI) host

controllers to ensure maximum C3/C4 CPU power state time with C2 popup. This

feature applies to the period schedule and works by allowing the DMA engine to identify

periods of idleness and prevents the DMA engine from accessing memory when the

periodic schedule is idle. Typically in the presence of periodic devices with multiple

millisecond poll periods, the periodic schedule will be idle for several frames between

polls.

The USB Pre-Fetch Based Pause feature is disabled by setting bit 4 of EHCI

Configuration Register Section 15.1.30.

5.19.7.2 Suspend Feature

The Enhanced Host Controller Interface (EHCI) For Universal Serial Bus Specification,

Section 4.3 describes the details of Port Suspend and Resume.

5.19.7.3 ACPI Device States

The USB 2.0 function only supports the D0 and D3 PCI Power Management states.

Notes regarding the ICH8 implementation of the Device States:

1. The EHC hardware does not inherently consume any more power when it is in the

D0 state than it does in the D3 state. However, software is required to suspend or

disable all ports prior to entering the D3 state such that the maximum power

consumption is reduced.

2. In the D0 state, all implemented EHC features are enabled.

3. In the D3 state, accesses to the EHC memory-mapped I/O range will master abort.

Note that, since the Debug Port uses the same memory range, the Debug Port is

only operational when the EHC is in the D0 state.

4. In the D3 state, the EHC interrupt must never assert for any reason. The internal

PME# signal is used to signal wake events, etc.

5. When the Device Power State field is written to D0 from D3, an internal reset is

generated. See section EHC Resets for general rules on the effects of this reset.

6. Attempts to write any other value into the Device Power State field other than 00b

(D0 state) and 11b (D3 state) will complete normally without changing the current

value in this field.

Intel® ICH8 Family Datasheet 217

Functional Description

5.19.7.4 ACPI System States

The EHC behavior as it relates to other power management states in the system is

summarized in the following list:

— The System is alwa ys in the S0 state when the EHC is in the D0 state. However,

when the EHC is in the D3 state, the system may be in any power management

state (including S0).

— When in D0, the Pause feature (See Section 5.19.7.1) enables dynamic

processor low-power states to be entered.

— The PLL in the EHC is disabled when entering the S3/S4/S5 states (core power

turns off).

— All core well logic is reset in the S3/S4/S5 states.

5.19.7.5 Mobile Considerations

The ICH8 USB 2.0 implementation does not behave differently in the mobile

configurations versus the desktop configurations. However, some features may be

especially useful for the mobile configurations.

• If a system (e.g., mobile) does not implement all ten USB 2.0 ports, the ICH8

provides mechanisms for changing the structur al parameters of the EHC and hiding

unused UHCI controllers. See the Intel® ICH8 BIOS Specification for information on

how BIOS should configure the ICH8.

• Mobile systems may want to minimize the conditions that will wake the system.

The ICH8 implements the “Wake Enable” bits in the Port Status and Control

registers, as specified in the EHCI spec, for this purpose.

• Mobile systems may want to cut suspend well power to some or all USB ports when

in a low-power state. The ICH8 implements the optional Port Wake Capability

R egister in the EHC Configuration Space for this platform-specific information to be

communicated to software.

5.19.8 Interaction with UHCI Host Controllers

The Enhanced Host controllers share its ports with UHCI Host controllers in the ICH8.

The UHC at D29:F0 shares ports 0 and 1; the UHC at D29:F1 shares ports 2 and 3; the

UHC at D29:F2 shares ports 4 and 5 with the EHC at D29:F7, while the UHC at D26:F0

shares ports 6 and 7, the UHC at D26:F1 shares ports 8 and 9 with EHC at D26:F7.

There is very little interaction between the Enhanced and the UHCI controllers other

than the multiplexing control which is provided as part of the EHC. Figure 16 shows the

USB Port Connections at a conceptual level.

5.19.8.1 Port-Routing Logic

Integrated into the EHC functionality is port-routing logic, which performs the muxing

between the UHCI and EHCI host controllers. The ICH8 conceptually implements this

logic as described in Section 4.2 of the Enhanced Host Controller Interface Specification

for Universal Serial Bus, Revision 1.0. If a device is connected that is not capable of

USB 2.0’s high-speed signaling protocol or if the EHCI softw are drivers are not present

as indicated by the Configured Flag, then the UHCI controller owns the port. Owning

the port means that the differential output is driven by the owner and the input stream

is only visible to the owner. The host controller that is not the owner of the port

internally sees a disconnected port.

Functional Description

218 Intel® ICH8 Family Datasheet

Note that the port-routing logic is the only block of logic within the ICH8 that observes

the physical (real) connect/disconnect information. The port status logic inside each of

the host controllers observes the electrical connect/disconnect information that is

generated by the port-routing logic.

Only the differential signal pairs are multiplexed/demultiplexed between the UHCI and

EHCI host controllers. The other USB functional signals are handled as follows:

• The Overcurrent inputs (OC[9:0]#) are directly routed to both controllers. An

overcurrent event is recorded in both controllers’ status registers.

The Port-Routing logic is implemented in the Suspend power well so that re-

enumeration and re-mapping of the USB ports is not required following entering and

exiting a system sleep state in which the core power is turned off.

The ICH8 also allows the USB Debug Port traffic to be routed in and out of Port #0.

When in this mode, the Enhanced Host controller is the owner of Port 0.

5.19.8.2 Device Connects

The Enhanced Host Controller Interface Specification for Universal Serial Bus, Revision

1.0 describes the details of handling Device Connects in Section 4.2. There are four

general scenarios that are summarized below.

1. Configure Flag = 0 and a full-speed/low -speed-only Device is connected

— In this case, the UHC is the owner of the port both before and after the connect

occurs. The EHC (except for the port-routing logic) never sees the connect

occur. The UHCI driver handles the connection and initialization process.

2. Configure Flag = 0 and a high-speed-capable Device is connected

— In this case, the UHC is the owner of the port both before and after the connect

occurs. The EHC (except for the port-routing logic) never sees the connect

occur. The UHCI driver handles the connection and initialization process. Since

the UHC does not perform the high-speed chirp handshake, the device operates

in compatible mode.

3. Configure Flag = 1 and a full-speed/low -speed-only Device is connected

— In this case, the EHC is the owner of the port before the connect occurs. The

EHCI driver handles the connection and performs the port reset. After the reset

process completes, the EHC hardware has cleared (not set) the Port Enable bit

in the EHC’ s PORTSC register. The EHCI driver then writes a 1 to the P ort Owner

Figure 16. Intel® ICH8-USB Port Connections

UHC

IUHC

Port

0Port

UHC

Port

2Port

3Port

4Port

5Port

6Port

7Port

8Port

UHCI 1 UHCI 4

UHCI 2

Port

Device 29 EHCI

UHCI 5

Port

2Port

3Port

4Port

5Port

6Port

7Port

8Port

Device 26 EHCI

UHCI 3

Intel® ICH8 Family Datasheet 219

Functional Description

bit in the same register, causing the UHC to see a connect event and the EHC to

see an “electrical” disconnect event. The UHCI driver and hardware handle the

connection and initialization process from that point on. The EHCI driver and

hardware handle the perceived disconnect.

4. Configure Flag = 1 and a high-speed-capable Device is connected

— In this case, the EHC is the owner of the port before, and remains the owner

after, the connect occurs. The EHCI driv er handles the connection and performs

the port reset. After the reset process completes, the EHC hardw are has set the

P ort Enable bit in the EHC’s POR TSC register. The port is functional at this point.

The UHC continues to see an unconnected port.

5.19.8.3 Device Disconnects

The Enhanced Host Controller Interface Specification for Universal Serial Bus, Revision

1.0 describes the details of handling Device Connects in Section 4.2. There are three

general scenarios that are summarized below.

1. Configure Flag = 0 and the device is disconnected

— In this case, the UHC is the owner of the port both before and after the

disconnect occurs. The EHC (except for the port-routing logic) never sees a

device attached. The UHCI driver handles disconnection process.

2. Configure Flag = 1 and a full-speed/low-speed-capable Device is disconnected

— In this case, the UHC is the owner of the port before the disconnect occurs. The

disconnect is reported by the UHC and serviced by the associated UHCI driver.

The port-routing logic in the EHC cluster forces the Port Owner bit to 0,

indicating that the EHC owns the unconnected port.

3. Configure Flag = 1 and a high-speed-capable Device is disconnected

— In this case, the EHC is the owner of the port before, and remains the owner

after, the disconnect occurs. The EHCI hardware and driver handle the

disconnection process. The UHC never sees a device attached.

5.19.8.4 Effect of Resets on Port-Routing Logic

As mentioned above, the Port Routing logic is implemented in the suspend power well

so that remuneration and re-mapping of the USB ports is not required following

entering and exiting a system sleep state in which the core power is turned off.

5.19.9 USB 2.0 Legacy Keyboard Operation

The ICH8 must support the possibility of a keyboard downstream from either a full-

speed/low-speed or a high-speed port. The description of the legacy k eyboard support

is unchanged from USB 1.1 (See Section 5.18.8).

The EHC provides the basic ability to generate SMIs on an interrupt event, along with

more sophisticated control of the generation of SMIs.

Reset Event Effect on Configure Flag Effect on Port Owner Bits

Suspend Well Reset cleared (0) set (1)

Core Well Reset no effect no effect

D3-to-D0 Reset no effect no effect

HCRESET cleared (0) set (1)

Functional Description

220 Intel® ICH8 Family Datasheet

5.19.10 USB 2.0 Based Debug Port

The ICH8 supports the elimination of the legacy COM ports by providing the ability for

new debugger software to interact with devices on a USB 2.0 port.

High-level restrictions and features are:

• Operational before USB 2.0 drivers are loaded.

• Functions even when the port is disabled.

• Works even though non-configured port is default-routed to the UHCI. Note that

the Debug Port can not be used to debug an issue that requires a full-speed/low-

speed device on Port #0 using the UHCI drivers.

• Allows normal system USB 2.0 traffic in a system that may only hav e one USB port.

• Debug Port device (DPD) must be high-speed capable and connect directly to Port

#0 on ICH8 systems (e.g., the DPD cannot be connected to Port #0 through a

hub).

• Debug Port FIFO always makes forward progress (a bad status on USB is simply

presented back to software).

• The Debug Port FIFO is only given one USB access per microframe.

The Debug port facilitates operating system and device driver debug. It allows the

software to communicate with an external console using a USB 2.0 connection.

Because the interface to this link does not go through the normal USB 2.0 stack, it

allows communication with the external console during cases where the operating

system is not loaded, the USB 2.0 software is broken, or where the USB 2.0 software is

being debugged. Specific features of this implementation of a debug port are:

• Only works with an external USB 2.0 debug device (console)

• Implemented for a specific port on the host controller

• Operational anytime the port is not suspended AND the host controller is in D0

power state.

• Capability is interrupted when port is driving USB RESET

5.19.10.1 Theory of Operation

There are two operational modes for the USB debug port:

1. Mode 1 is when the USB port is in a disabled state from the viewpoint of a standard

host controller driver. In Mode 1, the Debug Port controller is required to gen erate a

“keepalive” packets less than 2 ms apart to keep the attached debug device from

suspending. The keepalive packet should be a standalone 32-bit SYNC field.

2. Mode 2 is when the host controller is running (i.e., host controller’s Run/Stop# bit

is 1). In Mode 2, the normal transmission of SOF packets will keep the debug

device from suspending.

Behavioral Rules

1. In both modes 1 and 2, the Debug Port controller must check for software

requested debug transactions at least every 125 microseconds.

2. If the debug port is enabled by the debug driver, and the standard host controller

driver resets the USB port, USB debug transactions are held off for the duration of

the reset and until after the first SOF is sent.

3. If the standard host controller driver suspends the USB port, then USB debug

transactions are held off for the duration of the suspend/resume sequence and until

after the first SOF is sent.

4. The ENAB LE D_CNT bit in the debug register space is independent of the similar

port control bit in the associated Port Status and Control register.

Intel® ICH8 Family Datasheet 221

Functional Description

Table 87 shows the debug port behavior related to the state of bits in the debug

registers as well as bits in the associated Port Status and Control register.

Table 87. Debug Port Behavior

OWNER_CNT ENABLED_CT Port

Enable Run /

Stop Suspend Debug Port Behavior

0XXXX

Debug port is not being used.

Normal operation.

10XXX

Debug port is not being used.

Normal operation.

1100X

Debug port in Mode 1. SYNC

keepalives sent plus debug

traffic

1101X

Debug port in Mode 2. SOF

(and only SOF) is sent as

keepalive. Debug tr affic is also

sent. Note that no other

normal traffic is sent out this

port, because the port is not

enabled.

11100

Invalid. Host controller driver

should never put controller

into this state (enabled, not

running and not suspended).

11101

Port is suspended. No debug

traffic sent.

11110

Debug port in Mode 2. Debug

traffic is interspersed with

normal traffic.

11111

Port is suspended. No debug

traffic sent.

Functional Description

222 Intel® ICH8 Family Datasheet

5.19.10.1.1 OUT Transactions

An Out transaction sends data to the debug device. It can occur only when the

following are true:

• The debug port is enabled

• The debug software sets the GO_CNT bit

• The WRITE_READ#_CNT bit is set

The sequence of the transaction is:

1. Softw are s ets the app r op riate values in the following bits:

— USB_ADDRESS_CNF

—USB_ENDPOINT_CNF

— DATA_BUFFER[63:0]

— TOKEN_PID_CNT[7:0]

—SEND_PID_CNT[15:8]

—DATA_LEN_CNT

— WRITE_READ#_CNT (note: this will always be 1 for OUT transactions)

— GO_CNT (note: this will always be 1 to initiate the transaction)

2. The debug port controller sends a token packet consisting of:

—SYNC

— T OKEN_PID_C N T fie l d

— USB_ADDRESS_CNT field

— USB_ENDPOINT_CNT field

— 5-bit CRC field

3. After sending the token packet, the debug port controller sends a data packet

consisting of:

—SYNC

— SEND_PID_CNT field

— The number of data bytes indicated in DATA_LEN_CNT from the DATA_BUFFER

—16-bit CRC

NOTE: A DATA_LEN_CNT value of 0 is valid in which case no data bytes would be

included in the packet.

4. After sending the data packet, the controller waits for a handshake response from

the debug device.

• If a handshake is received, the debug port controller:

— a. Places the received PID in the RECEIVED_PID_STS field

— b. Resets the ERROR_GOOD#_STS bit

— c. Sets the DONE_STS bit

• If no handshake PID is received, the debug port controller:

— a. Sets the EXCEPTION_STS field to 001b

— b. Sets the ERROR_GOOD#_STS bit

— c. Sets the DONE_STS bit

Intel® ICH8 Family Datasheet 223

Functional Description

5.19.10.1.2 IN Transactions

An IN transaction receives data from the debug device. It can occur only when the

following are true:

• The debug port is enabled

• The debug software sets the GO_CNT bit

• The WRITE_READ#_CNT bit is reset

The sequence of the transaction is:

1. Software sets the appropriate values in the following bits:

—USB_ADDRESS_CNF

—USB_ENDPOINT_CNF

— TOKEN_PID_CNT[7:0]

—DATA_LEN_CNT

— WRITE_READ#_CNT (note: this will always be 0 for IN transactions)

— GO_CNT (note: this will always be 1 to initiate the transaction)

2. The debug port controller sends a token packet consisting of:

—SYNC

— TOKEN_PID_CNT field

— USB_ADDRESS_CNT field

—USB_ENDPOINT_CNT field

— 5-bit CRC field.

3. After sending the token packet, the debug port controller w aits for a response from

the debug device.

If a response is received:

— The received PID is placed into the RECEIVED_PID_STS field

— Any subsequent bytes are placed into the DATA_BUFFER

— The DATA_LEN_CNT field is updated to show the number of bytes that were

received after the PID.

4. If valid packet was receiv ed from the device that was one byte in length (indicating

it was a handshake packet), then the debug port controller:

— Resets the ERROR_GOOD#_STS bit

— Sets the DONE_STS bit

5. If valid packet w as received from the devi ce that was more than one byte in length

(indicating it was a data packet), then the debug port controller:

— Transmits an ACK handshake packet

— Resets the ERROR_GOOD#_STS bit

— Sets the DONE_STS bit

6. If no valid packet is received, then the debug port controller:

— Sets the EXCEPTION_STS field to 001b

— Sets the ERROR_GOOD#_STS bit

— Sets the DONE_STS bit.

Functional Description

224 Intel® ICH8 Family Datasheet

5.19.10.1.3 Debug Software

Enabling the Debug Port

There are two mutually exclusive conditions that debug software must address as part

of its startup processing:

• The EHCI has been initialized by system software

• The EHCI has not been initialized by system software

Debug software can determine the current ‘initialized’ state of the EHCI by examining

the Configure Flag in the EHCI USB 2.0 Command Register. If this flag is set, then

system software has initialized the EHCI. Otherwise the EHCI should not be considered

initialized. Debug software will initialize the debug port registers depending on the

state the EHCI. However, before this can be accomplished, debug software must

determine which root USB port is designated as the debug port.

Determining the Debug Port

Debug software can easily determine which USB root port has been designated as the

debug port by examining bits 20:23 of the EHCI Host Controller Structural Parameters

0000=port 0).

Debug Software Startup with Non-Initialized EHCI

Debug software can attempt to use the debug port if after setting the OWNER_CNT bit,

the Current Connect Status bit in the appropriate (See Determining the Debug Port)

PORTSC register is set. If the Current Connect Status bit is not set, then debug

software may choose to terminate or it may choose to wait until a device is connected.

If a device is connected to the port, then debug software must reset/enable the port.

Debug software does this by setting and then clearing the Port Reset bit the PORTSC

clearing the Port Reset bit. Due to possible delays, this bit may not change to 0

immediately; reset is complete when this bit reads as 0. Software must not continue

until this bit reads 0.

If a high-speed device is attached, the EHCI will automatically set the Port Enabled/

Disabled bit in the PORTSC register and the debug software can proceed. Debug

software should set the ENABLED_CNT bit in the Debug Port Control/Status register,

and then reset (clear) the P ort Enabled/Disabled bit in the PORTSC register (so that the

system host controller driver does not see an enabled port when it is first loaded).

Debug Software Startup with Initialized EHCI

Debug software can attempt to use the debug port if the Current Connect Status bit in

the appropriate (See Determining the Debug Port) PORTSC register is set. If the

Current Connect Status bit is not set, then debug software may choose to termin ate or

it may choose to wait until a device is connected.

If a device is connected, then debug software must set the OWNER_CNT bit and then

the ENABLED_CNT bit in the Debug Port Control/Status register.

Determining Debug Peripheral Presence

After enabling the debug port functionalit y, debug software can determine if a debug

peripheral is attached by attempting to send data to the debug peripheral. If all

attempts result in an error (Exception bits in the Debug Port Control/Status register

indicates a Transaction Error), then the attached device is not a debug peripheral. If the

debug port peripheral is not present, then debug software may choose to terminate or

it may choose to wait until a debug peripheral is connected.

Intel® ICH8 Family Datasheet 225

Functional Description

5.20 SMBus Controller (D31:F3)

The ICH8 provides an System Management Bus (SMBus) 2.0 host controller as well as

an SMBus Slave Interface. The host controller provides a mechanism for the processor

to initiate communications with SMBus peripher als (slaves). The ICH8 is also capable of

operating in a mode in which it can communicate with I2C compatible devices.

The ICH8 can perform SMBus messages with either packet error checking (PEC)

enabled or disabled. The actual PEC calculation and checking is performed in hardware

by the ICH8.

The Slave Interface allows an external master to read from or write to the ICH8. Write

cycles can be used to cause certain events or pass messages, and the read cycles can

be used to determine the state of various status bits. The ICH8’s internal host

controller cannot access the ICH8’s internal Slave Interface.

The ICH8 SMBus logic exists in Device 31:Function 3 configuration space, and consists

of a transmit data path, and host controller. The transmit data path provides the data

flow logic needed to implement the seven different SMBus command protocols and is

controlled by the host controller. The ICH8 SMBus controller logic is clocked by RTC

clock.

The SMBus Address Resolution Protocol (ARP) is supported by using the existing host

controller commands through software, except for the new Host Notify command

(which is actually a received message).

The programming model of the host controller is combined into two portions: a PCI

configuration portion, and a system I/O mapped portion. All static configuration, such

as the I/O base address, is done via the PCI configuration space. Real-time

programming of the Host interface is done in system I/O space.

The ICH8 SMBus host controller checks for parity errors as a target. If an error is

detected, the detected parity error bit in the PCI Status Register (Device 31:Function

3:Offset 06h:bit 15) is set. If bit 6 and bit 8 of the PCI Command Register (Device

31:Function 3:Offset 04h) are set, an SERR# is generated and the signaled SERR# bit

in the PCI Status Register (bit 14) is set.

Note that the ICH8 SMBus controller may stop responding if an SMBus device suddenly

stops transmitting in the middle of a packet. This could result in unexpected system

behavior, including a system hang.

5.20.1 Host Controller

The SMBus host controller is used to send commands to other SMBus slave devices.

Software sets up the host controller with an address, command, and, for writes, data

and optional PEC; and then tells the controller to start. When the controller has finished

transmitting data on writes, or receiving data on reads, it generates an SMI# or

interrupt, if enabled.

The host controller supports 8 command protocols of the SMBus interface (see System

Management Bus (SMBus) Specification, Version 2.0): Quick Command, Send Byte,

Receiv e Byte, W rite Byte/Word, Read Byte/Word, Process Call, Block R ead/Write, Block

Write–Block Read Process Call, and Host Notify.

The SMBus host controller requires that the various data and command fields be setup

for the type of command to be sent. When softw are sets the ST AR T bit, the SMBus Host

controller performs the requested transaction, and interrupts the processor (or

generates an SMI#) when the transaction is completed. Once a START command has

been issued, the values of the “active registers” (Host Control, Host Command,

Transmit Slave Address, Data 0, Data 1) should not be changed or read until the

Functional Description

226 Intel® ICH8 Family Datasheet

interrupt status bit (INTR) has been set (indicating the completion of the command).

Any register values needed for computation purposes should be saved prior to issuing

of a new command, as the SMBus host controller updates all registers while completing

the new command.

The ICH8 supports the System Management Bus (SMBus) Specification, Version 2.0.

Slave functionality, including the Host Notify protocol, is available on the SMBus pins.

The SMLink and SMBus signals should not be tied together externally.

Using the SMB host controller to send commands to the ICH8’s SMB slave port is not

supported.

5.20.1.1 Command Protocols

In all of the following commands, the Host Status Register (offset 00h) is used to

determine the progress of the command. While the command is in operation, the

HOST_BUSY bit is set. If the command completes successfully, the INTR bit will be set

in the Host Status Register. If the device does not respond with an acknowledge, and

the transaction times out, the DEV_ERR bit is set. If software sets the KILL bit in the

Host Control Register while the command is running, the transaction will stop and the

FAILED bit wi ll be set.

Quick Command

When programmed for a Quick Command, the Transmit Slave Address Register is sent.

The PEC byte is never appended to the Quick Protocol. Software should force the

PEC_EN bit to 0 when performing the Quick Command. Software must force the

I2C_EN bit to 0 when running this command. See Section 5.5.1 of the System

Management Bus (SMBus) Specification, Version 2.0 for the format of the protocol.

Send Byte / Receive Byte

For the Send Byte command, the Transmit Slave Address and Device Command

Registers are sent. F or the Receive Byte command, the Transmit Slave Address R egister

is sent. The data received is stored in the DATA0 register. Software must force the

I2C_EN bit to 0 when running this command.

The Receive Byte is similar to a Send Byte, the only difference is the direction of data

transfer. See Sections 5.5.2 and 5.5. 3 of the System Management Bus (SMBus)

Specification, Version 2. 0 for the format of the protocol.

Write Byte/Word

The first byte of a Write Byte/W ord access is the command code. The next 1 or 2 bytes

are the data to be written. When programmed for a Write Byte/Word command, the

Transmit Slave Address, Device Command, and Data0 Registers are sent. In addition,

the Data1 Register is sent on a W rite Word command. Software must force the I2C_EN

bit to 0 when running this command. See Section 5.5.4 of the System Management Bus

(SMBus) Specification, Version 2.0 for the format of the protocol.

Read Byte/Word

Reading data is slightly more complicated than writing data. First the ICH8 must write a

command to the slave device. Then it must follow that command with a repeated start

condition to denote a read from that device's address. The slave then returns 1 or 2

bytes of data. Software must force the I2C_EN bit to 0 when running this command.

Intel® ICH8 Family Datasheet 227

Functional Description

When programmed for the read byte/word command, the Transmit Slave Address and

Device Command Registers are sent. Data is received into the DAT A 0 on the read byte,

and the DAT0 and DATA1 registers on the read word. See Section 5.5. 5 of the System

Management Bus (SMBus) Specification, Version 2.0 for the format of the protocol.

Process Call

The process call is so named because a command sends data and w aits for the slav e to

return a value dependent on that data. The protocol is simply a Write W ord followed by

a Read Word, but without a second command or stop condition.

When programmed for the Process Call command, the ICH8 transmits the Transmit

Slave Address, Host Command, DATA0 and DATA1 registers. Data received from the

device is stored in the DATA0 and DATA1 registers. The Process Call command with

I2C_EN set and the PEC_EN bit set produces undefined results. Software must force

either I2C_EN or PEC_EN to 0 when running this command. See Section 5.5.6 of the

System Management Bus (SMBus) Specification, Version 2.0 for the format of the

protocol.

Note: For process call command, the value written into bit 0 of the Transmit Slave Address

Note: If the I2C_EN bit is set, the protocol sequence changes slightly: the Command Code

(bits 18:11 in the bit sequence) are not sent - as a result, the slave will not

acknowledge (bit 19 in the sequence).

Block Read/Wri te

The ICH8 contains a 32-byte buffer for read and write data which can be enabled by

setting bit 1 of the Auxiliary Control register at offset 0Dh in I/O space, as opposed to a

single byte of buffering. This 32-byte buffer is filled with write data before

transmission, and filled with read data on reception. In the ICH8, the interrupt is

generated only after a transmission or reception of 32 bytes, or when the entire byte

count has been transmitted/received.

The byte count field is transmitted but ignored by the ICH8 as software will end the

transfer after all bytes it cares about have been sent or received.

For a Block Write, software must either force the I2C_EN bit or both the PEC_EN and

AAC bits to 0 when running this command.

The block write begins with a slave address and a write condition. After the command

code the ICH8 issues a byte count describing how many more bytes will follow in the

message. If a slave had 20 bytes to send, the first byte would be the number 20 (14h),

followed by 20 bytes of data. The byte count may not be 0. A Block Read or Write is

allowed to transfer a maximum of 32 data bytes.

When programmed for a block write command, the Transmit Slave Address, Device

Command, and Data0 (count) registers are sent. Data is then sent from the Block Data

Byte register; the total data sent being the v alue stored in the Data0 R egister. On block

read commands, the first byte received is stored in the Data0 register, and the

remaining bytes are stored in the Block Data Byte register. See Section 5.5.7 of the

System Management Bus (SMBus) Specification, Version 2.0 for the format of the

protocol.

Note: For Block Write, if the I2C_EN bit is set, the format of the command changes slightly.

The ICH8 will still send the number of bytes (on writes) or receive the number of bytes

(on reads) indicated in the DAT A0 register. However, it will not send the contents of the

DATA0 register as part of the message. Also, the Block Write protocol sequence

Functional Description

228 Intel® ICH8 Family Datasheet

changes slightly: the Byte Count (bits 27:20 in the bit sequence) are not sent - as a

result, the slave will not acknowledge (bit 28 in the sequence).

I2C Read

This command allows the ICH8 to perform block reads to certain I2C devices, such as

serial E2PROMs. The SMBus Block Read supports the 7-bit addressing mode only.

However, this does not allow access to devices using the I2C “Combined Format” that

has data bytes after the address. Typically these data bytes correspond to an offset

(address) within the serial memory chips.

Note: This command is supported independent of the setting of the I2C_EN bit. The I2C Read

command with the PEC_EN bit set produces undefined results. Software must force

both the PEC_EN and AAC bit to 0 when running this command.

For I2C Read command, the value written into bit 0 of the Transmit Slave Address

The format that is used for the command is shown in Table 88.

The ICH8 will continue reading data from the peripheral until the NAK is received.

Table 88. I2C Block Read

Bit Description

1Start

8:2 Slave Address — 7 bits

9Write

10 Acknowledge from slave

18:11 Send DATA1 register

19 Acknowledge from slave

20 Repeated Start

27:21 Slave Address — 7 bits

28 Read

29 Acknowledge from slave

37:30 Data byte 1 from slave — 8 bits

38 Acknowledge

46:39 Data byte 2 from slave — 8 bits

47 Acknowledge

–Data bytes from slave /

Acknowledge

– Data byte N from slave — 8 bits

– NOT Acknowledge

–Stop

Intel® ICH8 Family Datasheet 229

Functional Description

Block Write–Block Read Process Call

The block write-block read process call is a two-part message. The call begins with a

slave address and a write condition. After the command code the host issues a write

byte count (M) that describes how many more bytes will be written in the first part of

the message. If a master has 6 bytes to send, the byte count field will have the value 6

(0000 0110b), followed by the 6 bytes of data. The write byte count (M) cannot be 0.

The second part of the message is a block of read data beginning with a repeated start

condition followed by the slave address and a Read bit. The next byte is the read byte

count (N), which may differ from the write byte count (M). The read byte count (N)

cannot be 0.

The combined data payload must not exceed 32 bytes. The byte length restrictions of

this process call are summarized as follows:

•M ≥ 1 byte

•N ≥ 1 byte

•M + N ≤ 32 bytes

The read byte count does not include the PEC byte. The PEC is computed on the total

message beginning with the first slave address and using the normal PEC

computational rules. It is highly recommended that a PEC byte be used with the Block

Write-Block Read Process Call. Software must do a read to the command register

(offset 2h) to reset the 32 byte buffer pointer prior to reading the block data register.

Note that there is no STOP condition before the repeated START condition, and that a

NACK signifies the end of the read transfer.

Note: E32B bit in the Auxiliary Control register must be set when using this protocol.

See Section 5.5.8 of the System Management Bus (SMBus) Specification, Version 2.0

for the format of the protocol.

5.20.2 Bus Arbitration

Several masters may attempt to get on the bus at the same time by driving the

SMBDATA line low to signal a start condition. The ICH8 continuously monitors the

SMBDATA line. When the ICH8 is attempting to drive the bus to a 1 by letting go of the

SMBDA TA line, and it samples SMBDA T A low , th en some other master is driving the bus

and the ICH8 will stop transferring data.

If the ICH8 sees that it has lost arbitration, the condition is called a collision. The ICH8

will set the BUS_ERR bit in the Host Status Register, and if enabled, generate an

interrupt or SMI#. The processor is responsible for restarting the transaction.

When the ICH8 is a SMBus master, it drives the clock. When the ICH8 is sending

address or command as an SMBus master, or data bytes as a master on writes, it driv es

data relative to the clock it is also driving. It will not start toggling the clock until the

start or stop condition meets proper setup and hold time. The ICH8 will also assure

minimum time between SMBus transactions as a master.

Note: The ICH8 supports the same arbitration protocol for both the SMBus and the System

Management (SMLINK) interfaces.

Functional Description

230 Intel® ICH8 Family Datasheet

5.20.3 Bus Timing

5.20.3.1 Clock Stretching

Some devices may not be able to handle their clock toggling at the rate that the ICH8

as an SMBus master would like. They have the capability of stretching the low time of

the clock. When the ICH8 attempts to release the clock (allowing the c lock to go high),

the clock will remain low for an extended period of time.

The ICH8 monitors the SMBus clock line after it releases the bus to determine whether

to enable the counter for the high time of the clock. While the bus is still low, the high

time counter must not be enabled. Similarly, the low period of the clock can be

stretched by a SMBus master if it is not ready to send or receive data.

5.20.3.2 Bus Time Out (Intel® ICH8 as SMBus Master)

If there is an error in the transaction, such that an SMBus device does not signal an

acknowledge, or holds the clock lower than the allowed time-out time, the transaction

will time out. The ICH8 will discard the cycle and set the DEV_ERR bit. The time out

minimum is 25 ms (800 RTC clocks). The time-out counter inside the ICH8 will start

after the last bit of data is transferred by the ICH8 and it is waiting for a response.

The 25 ms timeout counter will not count under the following conditions:

1. BYTE_DONE_STATUS bit (SMBus I/O Offset 00h, bit 7) is set

2. The SECOND_TO_STS bit (TCO I/O Offset 06h, bit 1) is not set (this indicates that

the system has not locked up).

5.20.4 Interrupts / SMI#

The ICH8 SMBus controller uses PIRQB# as its interrupt pin. However, the system can

alternatively be set up to generate SMI# instead of an interrupt, by setting the

SMBUS_SMI_EN bit (Device 31:Function 0:Offset 40h:bit 1).

Table 90 and Table 91 specify how the various enable bits in the SMBus function control

the generation of the interrupt, Host and Slave SMI, and Wake internal signals. The

rows in the tables are additive, which means that if more than one row is true for a

particular scenario then the Results for all of the activated rows will occur.

Intel® ICH8 Family Datasheet 231

Functional Description

Table 89. Enable for SMBALERT#

Event

INTREN (Host

Control I/O

02h, Bit 0)

SMB_SMI_EN (H ost

Configuration Register,

D31:F3:Offset 40h, Bit 1)

SMBALERT_DIS

(Slave Command

I/O Register,

Offset 11h, Bit 2)

Result

SMBALERT#

asserted low

(always reported

in Host Status

Re gister, Bit 5)

XX XWake generated

X1 0

Slave SMI#

generated

(SMBUS_SMI_STS)

10 0

Interrupt

generated

Table 90. Enables for SMBus Slave Wr ite and SMBus Host Events

Event INTREN (H os t

Control I/O Register,

Offset 02h, Bit 0)

SMB_SMI_EN (Host

Configuration Register,

D31:F3:Offset 40h, Bit1) Event

Slave Write to Wake/

SMI# Command XX

Wake generated when asleep.

Slave SMI# generated when

awake (SMBUS_SMI_STS).

Slave Write to

SMLINK_SLAVE_SMI

Command XX

Slave SMI# generated when in

the S0 state (SMBUS_SMI_STS)

Any combination of

Host Status Register

[4:1] asserted

0XNone

1 0 Interrupt generated

11Host SMI# generated

Table 91. Enables for the Host Notify Command

HOST_NOTIFY_INTREN

(Slave Control I/O

SMB_SMI_EN (H ost

Config Register,

D31:F3:Off40h, Bit 1)

HOST_NOTIFY_WKEN

(Slave Control I/O

0X0None

XX1Wake generated

1 0 X Interrupt generated

11X

Slave SMI# generated

(SMBUS_SMI_STS)

Functional Description

232 Intel® ICH8 Family Datasheet

5.20.5 SMBALERT#

SMBALERT# is multiplex ed with GPIO[11]. When enable and the signal is asserted, The

ICH8 can generate an interrupt, an SMI#, or a wake event from S1–S5.

5.20.6 SMBus CRC Generation and Checking

If the AAC bit is set in the Auxiliary Control register, the ICH8 automatically calculates

and drives CRC at the end of the transmitted packet for write cycles, and will check the

CRC for read cycles. It will not transmit the contents of the PEC register for CRC. The

PEC bit must not be set in the Host Control register if this bit is set, or unspecified

behavior will result.

If the read cycle results in a CRC error, the DEV_ERR bit and the CRCE bit in the

Auxiliary Status register at offset 0Ch will be set.

5.20.7 SMBus Slave Interface

The ICH8’ s SMBus Slave interface is accessed via the SMBus. The SMBus slave logic will

not generate or handle receiving the PEC byte and will only act as a Legacy Alerting

Protocol device. The slave interface allows the ICH8 to decode cycles, and allows an

external microcontroller to perform specific actions. Key features and capabilities

include:

• Supports decode of three types of messages: Byte Write, Byte Read, and Host

Notify.

• Receive Slave Address register: This is the address that the ICH8 decodes. A

default value is provided so that the slave interface can be used without the

processor having to program this register.

• Receive Slave Data register in the SMBus I/O space that includes the data written

by the external microcontroller.

• Registers that the external microcontroller can read to get the state of the ICH8.

• Status bits to indicate that the SMBus slave logic caused an interrupt or SMI# due

to the reception of a message that matched the slave address.

— Bit 0 of the Slave Status Register for the Host Notify command

— Bit 16 of the SMI Status Register (Section 9.8.3.15) for all others

Note: The external microcontroller should not attempt to access the Intel ICH8’s SMBu s slave

logic until either:

— 800 milliseconds after both: RTCRST## is high and RSMRST# is high, OR

— the PLTRST# de-asserts

— The 800 ms case is based on the scenario where the RTC Battery is dead or

missing such that the RTC Power Well comes up simultaneously with Suspend

Well. In this case, the RTC clock may take a while to stabilize. The ICH8 uses

the RTC clock to extend the internal RSMRST# by ~100 ms. Therefore, if the

clock is slow to toggle, this time could be extended. 800 ms is assumed to be

sufficient guardband for this.

If a master leaves the clock and data bits of the SMBus interface at 1 for 50 µs or more

in the middle of a cycle, the ICH8 slave logic's behavior is undefined. This is interpreted

as an unexpected idle and should be avoided when performing management activities

to the slave logic.

Note: When an external microcontroller accesses the SMBus Slave Interface over the SMBus

a translation in the address is needed to accommodate the least significant bit used for

read/write control. For example, if the ICH8 slave address (RCV_SLVA) is left at 44h

(default), the external micro controller would use an address of 88h/89h (write/read).

Intel® ICH8 Family Datasheet 233

Functional Description

5.20.7.1 Format of Slave Write Cycle

The external master performs Byte Write commands to the ICH8 SMBus Slave I/F. The

“Command” field (bits 11:18) indicate which register is being accessed. The Data field

(bits 20:27) indicate the value that should be written to that register.

Note: If the ICH8 is sent a ‘Hard Reset Without Cyclin g’ command on SMBus while the system

is in S4 or S5, the reset command and any other write commands accepted by the

ICH8 SMBus will not be executed until the next wake event. SMBus write commands

that are accepted by the ICH8 are not lost, but completion occurs after the next system

wake event. This also applies to any SMBus wake commands accepted after a ‘Hard

Reset Without Cycling’ command, such that the SMBus wake command will not cause

the system to wake. Any SMBus read that is accepted by the ICH8 will complete

normally. Intel® Active Management Technology is not impacted as Intel AMT does not

use the Hard Re set Without Cycling command while the system is in S4 or S5.

Table 92 has the values associated with the registers.

NOTE: The external microcontroller is responsible to make sure that it does not update the

contents of the data byte registers until they have been read by the system processor. The

ICH8 overwrites the old value with any new value received. A race condition is possible

where the new value is being written to the register just at the time it is being read. ICH8

will not attempt to cover this race condition

(i.e., unpredictable resu lts in this case).

Table 92. Slave Write Registers

0Command Register. See Table 93 below for valid values written to this register.

1–3 Reserved

4 Data Message Byte 0

5 Data Message Byte 1

6–7 Reserved

8 Reserved

9–FFh Reserved

Functional Description

234 Intel® ICH8 Family Datasheet

Table 93. Command Types

Command

Type Description

0Reserved

WAKE/SMI#. This command wakes the system if it is not already awake. If

system is already awake, an SMI# is generated.

NOTE: The SMB_WAK_STS bit will be set by this command, even if the system is

already awake. The SMI handler should then clear this bit.

2Unconditional Powerdown. This command sets the PWRBTNOR_STS bit, and

has the same effect as the Powerbutton Override occurring.

3HARD RESET WITHOUT CYCLING: This command causes a hard reset of the

system (does not include cycling of the power supply). This is equivalent to a write

to the CF9h register with bits 2:1 set to 1, but bit 3 set to 0.

4HARD RESET SYSTEM. This command causes a hard reset of the system

(including cycling of the power supply). This is equivalent to a write to the CF9h

Disable the TCO Messages. This command will disable the Intel® ICH8 from

sending Heartbeat and Event me ssages (as described in Section 5.15). Once this

command has been executed, Heartbeat and Event message reporting can only be

re-enabled by assertion and deassertion of the RSMRST# signal.

6WD RELOAD: Reload watchdog timer.

7Reserved

SMLINK_SLV_SMI. When ICH8 detects this command type while in the S0 state,

it sets the SMLINK_SLV_SMI_STS bit (see Section 9.9.5). This command shoul d

only be used if the system is in an S0 state. If the message is received during S1–

S5 states, the ICH8 acknowledges it, but the SMLINK_SLV_SMI_STS bit does not

get set.

NOTE: It is possible that the system transitions out of the S0 st ate at the same

time that the SMLINK_SLV_SMI command is received. In this case, the

SMLINK_SLV_SMI_STS bit may get set but not serviced before the system

goes to sleep. Once the system returns to S0, the SMI associated with this

bit would then be generated. Software must be able to handle this scenario.

9–FFh Reserved

Intel® ICH8 Family Datasheet 235

Functional Description

5.20.7.2 Format of Read Command

The external master performs Byte Read commands to the ICH8 SMBus Slave I/F. The

“Command” field (bits 18:11) indicate which register is being accessed. The Data field

(bits 30:37) contain the value that should be read from that register.

Table 94. Slave Read Cycle Format

Bit Description Driven by: Comment:

1 Start External Microcontroller

2–8 Slave Address - 7 bits External Microcontroller Must match value in Receive Slave

Address register.

9 Write External Microcontroller Always 0

10 ACK Intel ICH8

11–18 Command code – 8 bits External Microcontroller Indicates which register is being

accessed. See Table 95 below for

list of implemented registers.

19 ACK Intel ICH8

20 Repeated Start External Microcontroller

21–27 Slave Address - 7 bits External Microcontroller Must match value in Receive Slave

Address register

28 Read External Microcontroller Always 1

29 ACK Intel ICH8

30–37 Data Byte Intel ICH8 Value depends on register being

accessed. Table 95 belo w for list of

implemented registers.

38 NOT ACK External Microcontroller

39 Stop External Microcontroller

Table 95. Data Values for Slave Read Registers (Sheet 1 of 2)

07:0

Reserv ed for capabilities indication. Should always return 0 0h. Future chips

may return another value to indicate different capabilities.

12:0

System Power State

000 = S0 001 = S1 010 = Reserved 011 = S3

100 = S4 101 = S5 110 = Reserved 111 = Reserved

7:3 Reserved

23:0 Reserved

7:4 Reserved

35:0

Watchdog Timer current value. Note that Wa tchdog Timer has 10 bits,

but this fiel d is only 6 bits. If the current value is greater than 3Fh, ICH8

will always report 3Fh in this field.

7:6 Reserved

1 = The Intruder Detect (INTRD_DET) bit is set. This indicates that the

system cover has probably been opened.

11 = BTI Temperature Event occurred. This bit will be set if the Intel

ICH8’s THRM# input signal is active.

Functional Description

236 Intel® ICH8 Family Datasheet

5.20.7.2.1 Behavioral Notes

According to SMBus protocol, Read and Write messages always begin with a Start bit –

Address– Write bit sequence. When the ICH8 detects that the address matches the

value in the Receive Slave Address register, it will assume that the protocol is always

followed and ignore the Write bit (bit 9) and signal an Acknowledge during bit 10. In

other words, if a Start – Address–R ead occurs (which is inv alid for SMBus Read or W rite

protocol), and the address matches the ICH8’s Slave Address, the ICH8 will still grab

the cycle.

2 DOA CPU Status. This bit will be 1 to indicate th at the processor is dead

31 = SECOND_TO_STS bit set. This bit will be set after the second time -out

(SECOND_TO_STS bit) of the Watchdog Timer occurs.

6:4 Reserved. Will always be 0, but software should ignore.

Reflects the value of the GPI[11]/SMBALERT# pin (and is dependent upon

the value of the GPI_INV[11] bit. If the GPI_INV[11] bit is 1, then the value

in this bit equals the level of the GPI[11]/SMBALERT# pin (high = 1,

low = 0).

If the GPI_INV[11] bit is 0, then the value of this bit will equal the inverse

of the level of the GPI[11]/SMBALERT# pin (high = 0, low = 1).

5 0

FWH bad bit. This bit will be 1 to indicate that th e FWH read returned FFh,

which indicates that it is probably blank .

1Battery Low Status. ‘1’ if the BATLOW# pin is a ‘0’.

2CPU Power Failure Status: ‘1’ if the CPUPWR_FLR bit in the

GEN_PMCON_2 register is set.

INIT# due to receiving Shutdown message: This event i s visible from

the recept ion of t he sh utd own messag e un ti l a platform reset is done if the

Shutdown Policy Select bit (SPS) is configured to drive INIT#. When the

SPS bit is configured to generate PLTRST# based on shutdown, this register

bit will always return 0.

Events on signal will not create a event message

5POWER_OK_BAD: Indicates the failure core power well ramp during boot/

resume. This bit will be active if the SLP_S3# pin is de-asserted and

PWROK pin is not asserted.

6Thermal Trip: This bit will shadow the state of CPU Thermal Trip status bit

(CTS) (16.2.1.2, GEN_PMCON_2, bit 3). Events on signal will not create a

event message

Reserved: Default value is “X”

NOTE: Software should not expect a consistent value when this bit is read

through SMBUS/SMLINK

67:0

Contents o f the Message 1 regist er. See Section 9.9.8 for the description of

this register.

77:0

Contents o f the Message 2 regist er. See Section 9.9.8 for the description of

this register.

87:0

Contents of the WDST A TUS register. See Section 9.9.9 for the description of

this register.

9 – FFh 7:0 Reserved

Table 95. Data Values for Slave Read Registers (Sheet 2 of 2)

Intel® ICH8 Family Datasheet 237

Functional Description

Also according to SMBus protocol, a Read cycle contains a Repeated Start–Address–

Re ad sequence beginning at bit 20. Once again, if the Address matches the ICH8’s

Receive Slave Address, it will assume that the protocol is followed, ignore bit 28, and

proceed with the Slave Read cycle.

Note: An external microcontroller must not attempt to access the ICH8’s SMBus Slave logic

until at least 1 second after both RTCRST# and RSMRST# are deasserted (high).

5.20.7.3 Format of Host Notify Command

The ICH8 tracks and responds to the standard Host Notify command as specified in the

System Management Bus (SMBus) Specification, Version 2.0. The host address for this

command is fixed to 0001000b. If the ICH8 already has data for a previously-received

host notify command which has not been serviced yet by the host software (as

indicated by the HOST_NOTIFY_STS bit), then it will NACK following the host address

byte of the protocol. This allows the host to communicate non-acceptance to the

master and retain the host notify address and data values for the previous cycle until

host software completely services the interrupt.

Note: Host software must always clear the HOST_NOTIFY _STS bit after completing any

necessary reads of the address and data registers.

Table 96 shows the Host Notify format.

Table 96. Host Notify Format

Bit Desc r iption Driven By Comment

1Start External

Master

8:2 SMB Host Address — 7

bits External

Master Always 0001_000

9Write External

Master Always 0

10 ACK (or NACK) Intel® ICH8 ICH8 NACKs if HOST_NOTIFY_STS is 1

17:11 Device Address – 7 bits External

Master

Indicates the address of the master;

loaded into the Notify Device Address

18 Unused — Always 0 External

Master 7-bit-only address; this bit is inserted to

complete the byte

19 ACK ICH8

27:20 Data Byte Low — 8 bits External

Master Loaded into the Notify Data Low Byte

28 ACK ICH8

36:29 Data Byte High — 8 bits External

Master Loaded into the Notify Data High Byte

37 ACK ICH8

38 Stop External

Master

Functional Description

238 Intel® ICH8 Family Datasheet

5.21 Intel® High Definition Audio Overview

The ICH8’s controller communicates with the external codec(s) over the Intel High

Definition Audio serial link. The controller consists of a set of DMA engines that are

used to move samples of digitally encoded data between system memory and an

external codec(s). The ICH8 implements four output DMA engines and 4 input DMA

engines. The output DMA engines move digital data from system memory to a D-A

converter in a codec. ICH8 implements a single Serial Data Output signal

(HDA_SDOUT) that is connected to all external codecs. The input DMA engines move

digital data from the A-D converter in the codec to system memory. The ICH8

implements four Serial Digital Input signals (HDA_SDI[3:0]) supporting up to four

codecs.

Audio software renders outbound and processes inbound data to/from buffers in

system memory. The location of individual buffers is described by a Buffer Descriptor

List (BDL) that is fetched and processed by the controller. The data in the buffers is

arranged in a predefined format. The output DMA engines fetch the digital data from

memory and reformat it based on the programmed sample rate, bit/sample and

number of channels. The data from the output DMA engines is then combined and

serially sent to the external codecs over the Intel High Definition Audio link. The input

DMA engines receive data from the codecs ov er the Intel High Definition Audio link and

format the data based on the programmable attributes for that stream. The data is

then written to memory in the predefined format for software to process. Each DMA

engine moves one stream of data. A single codec can accept or generate multiple

streams of data, one for each A-D or D-A converter in the codec. Multiple codecs can

accept the same output stream processed by a single DMA engine.

Codec commands and responses are also transported to and from the codecs via DMA

engines.

5.21.1 Intel® High Definition Audio Docking (Mobile Only)

5.21.1.1 Dock Sequence

Note that this sequence is followed when the system is running and a docking event

occurs.

1. Since the ICH8 supports docking, the Docking Supported (DCKSTS. DS) bit defaults

to a 1. POST BIOS and ACPI BIOS software uses this bit to determine if the HD

Audio controller supports docking. BIOS may write a 0 to this RWO bit during POST

to effectively turn off the docking feature.

2. After reset in the undocked quiescent state, the Dock Attach (DCKCTL.DA) bit and

the Dock Mate (DCKSTS.DM) bit are both de- asserted. The HDA_DOCK_EN# signal

is de-asserted and HDA_DOCK_RST# is asserted. BCLK, SYNC and SDO signals

may or may no be running at the point in time that the docking event occurs.

3. The physical docking event is signaled to ACPI BIOS software via ACPI control

methods. This is normally done through a GPIO signal on the ICH8 and is outside

the scope of this section of the specification.

4. ACPI BIOS software first checks that the docking is supported via DCKSTS.DS=1

and that the DCKSTS.DM=0 and then initiates the docking sequence by writing a 1

to the DCKCTL.DA bit.

5. The HD Audio controller then asserts the HDA_DOCK_EN# signal so that the BCLK

signal begins toggling to the dock codec. HDA_DOCK_EN# shall be asserted

synchronously to BCLK and timed such that BCLK is low, SYNC is low, and SDO is

low. Pull-down resistors on these signals in the docking station discharge the

signals low so that when the state of the signal on both sides of the switch is the

same when the switch is turned on. This reduces the potential for charge coupling

Intel® ICH8 Family Datasheet 239

Functional Description

glitches on these signals. Note that in the ICH8 the first 8 bits of the Command field

are “reserved” and always driven to 0s. This creates a predictable point in time to

always assert HDA_DOCK_EN#. Note that the HD Audio link reset exit specification

that requires that SYNC and SDO be driven low during BCLK startup is not assured.

Note also that the SDO and BCLK signals may not be low while HDA_DOCK_RST#

is asserted which also violates the spec.

6. After the controller asserts HDA_DOCK_EN# it waits for a minimum of 2400 BCLKs

(100 us) and then de-asserts HDA_DOCK_RST#. This is done in such a way to

meet the HD Audio link reset exit specification. HDA_DOCK_RST# de-assertion

should be synchronous to BCLK and timed such that there are least 4 full BCLKS

from the de-assertion of HDA_DOCK_RST# to the first frame SYNC assertion.

7. The Connect/Turnaround/Address Frame hardware initialization sequence will now

occur on the dock codecs' SDI signals. A dock codec is detected when SDI is high

on the last BCLK cycle of the Frame Sync of a Connect Frame. The appropriate

bit(s) in the State Change Status (STATESTS) register will be set. The Turnaround

and Address Frame initialization sequence then occurs on the dock codecs' SDI(s).

8. After this hardware initialization sequence is complete (approximately 32 frames),

the controller hardware sets the DCKST S.DM bit to 1 indicating that the dock is now

mated. ACPI BIOS polls the DCKSTS.DM bit and when it detects it is set to 1,

conveys this to the OS through a plug-N-play IRP. This eventually invokes the HD

Audio Bus Driver, which then begins it's codec discovery, enumeration, and

configuration process.

9. Alternatively to step #8, the HD Audio Bus Driver may choose to enable an

interrupt by setting the WAKEEN bits for SDINs that didn't originally have codecs

attached to them. When a corresponding STA TESTS bit gets set an interrupt will be

generated. In this case the HD Audio Bus Driver is called directly by this interrupt

instead of being notified by the plug-N-play IRP.

10.HD Audio Bus Driver software “discovers” the dock codecs by comparing the bits

now set in the STATESTS register with the bits that were set prior to the docking

event.

5.21.1.2 Exiting D3/CRST# when Docked

1. In D3/CRST#, CRST# is asserted by the HD Audio Bus Driver. CRST# asserted

resets the dock state machines, but does not reset the DCKCTL.DA bit. Because the

dock state machines are reset, the dock is electrically isolated (HDA_DOCK_EN#

de-asserted) and DOCK_RST# is asserted.

2. The Bus Driver clears the STATESTS bits, then de-asserts CRST#, waits

approximately 7ms, then checks the STATESTS bits to see which codecs are

present.

3. When CRST# is de-asserted, the dock state machine detects that DCKCTL.DA is

still set and the controller hardware sequences through steps to electrically connect

the dock by asserting HDA_DOCK_EN# and then eventually de-asserts

DOCK_RST#. This completes within the 7 ms mentioned in step 2).

4. The Bus Driver enumerates the codecs present as indicated via the STATES TS bits.

5. Note that this process did not require BIOS or ACPI BIOS to set the DCKCTL.DA bit.

Functional Description

240 Intel® ICH8 Family Datasheet

5.21.1.3 Cold Boot/Resume from S3 When Docked

1. When booting and resuming from S3, PLTRST# switches from asserted to de-

asserted. This clears the DCKCTL.DA bit and the dock state machines. Because the

dock state machines are reset, the dock is electrically isolated (HDA_DOCK_EN#

de-asserted) and DOCK_RST# is asserted.

2. POST BIOS detects that the dock is attached and sets the DCKCTL.DA bit to 1. Note

that at this point CRST# is still asserted so the dock state machine will remain in

it's reset state.

3. The Bus Driver clears the STATESTS bits, then de-asserts CRST#, waits

approximately 7ms, then checks the STATESTS bits to see which codecs are

present.

4. When CRST# is de-asserted, the dock state machine detects that DCKCTL.DA is

still set and the controller hardware sequences through steps to electrically connect

the dock by asserting HDA_DOCK_EN# and then eventually de-asserts

DOCK_RST#. This completes within the 7ms mentioned in step 3).

5. The Bus Driv er enumerates the code cs prese nt as i nd icate d via the STATESTS bits .

5.21.1.4 Undock Sequence

There are two possible undocking scenarios. The first is the one that is initiated by the

user that invokes software and gracefully shuts down the dock codecs before they are

undocked. The second is referred to as the “surprise undock” where the user undocks

while the dock codec is running. Both of these situations appear the same to the

controller as it is not cognizant of the “surprise removal”. But both sequences will be

discussed here.

5.21.1.4.1 Normal Undock

1. In the docked quiescent state, the Dock Attach (DCKCTL.DA) bit and the Dock Mate

(DCKSTS.DM) bit are both asserted. The HDA_DOCK_EN# signal is asserted and

HDA_DOCK_RST# is de-asserted.

2. The user initiates an undock event through the GUI interface or by pushing a

button. This mechanism is outside the scope of this section of the document. Either

way ACPI BIOS software will be invoked to manage the undock process.

3. ACPI BIOS will call the HD Audio Bus Driver software in order to halt the stream to

the dock codec(s) prior to electrical undocking. If the HD Audio Bus Driver is not

capable of halting the stream to the docked codec, ACPI BIOS will initiate the

hardware undocking sequence as described in the n ext step while the dock stream

is still running. From this standpoint, the result is similar to the “surprise undock”

scenario where an audio glitch may occur to the docked codec(s) during the undock

process.

4. The ACPI BIOS initiates the hardware undocking sequence by writing a 0 to the

DCKCTL.DA bit.

5. The HD Audio controller asserts HDA_DOCK_RST#. HDA_DOCK_RST# assertion

shall be synchronous to BCLK. There are no other timing requirements for

HDA_DOCK_RST# assertion. Note that the HD Audio link reset specification

requirement that the last Frame sync be skipped will not be met.

6. A minimum of 4 BCLKs after HDA_DOCK_RST# the controller will de-assert

HDA_DOCK_EN# to isolate the dock codec signals from the ICH8 HD Audio link

signals. HDA_DOCK_EN# is de-asserted synchronously to BCLK and timed such

that BCLK, SYNC, and SDO are low.

7. After this hardware undocking sequence is com plete, the controller hardware clears

the DCKSTS.DM bit to 0 indicating that the dock is now un-mated. ACPI BIOS

software polls DCKSTS.DM and when it sees DM set, conveys to the end user that

physical undocking can proceed. The controller is now ready for a subsequent

docking event.

Intel® ICH8 Family Datasheet 241

Functional Description

5.21.1.4.2 Surprise Undock

1. In the surprise undock case the user undocks before software has had the

opportunity to gracefully halt the stream to the dock codec and initiate the

hardware undock sequence.

2. A signal on the docking connector is connected to the switch that isolates the dock

codec signals from the ICH8 HD Audio link signals (DOCK_DET# in the conceptual

diagram). When the undock event begins to occur the switch will be put into isolate

mode.

3. The undock event is communicated to the ACPI BIOS via ACPI control methods that

are outside the scope of this section of the document.

4. ACPI BIOS software writes a 0 to the DCKCTL.DA bit. ACPI BIOS then calls the HD

Audio Bus Driver via plug-N-play IRP. The Bus Driver then posthumously cleans up

the dock codec stream.

5. The HD Audio controller hardware is oblivious to the fact that a surprise undock

occurred. The flow from this point on is identical to the normal undocking sequence

described in section 0 starting at step 3). It finishes with the hardware clearing the

DCKSTS.DM bit set to 0 indicating that the dock is now un-mated. The controller is

now ready for a subsequent docking event.

5.21.1.5 Interaction Between Dock/Undock and Power Management States

When exiting from S3, PLTRST# will be asserted. The POST BIOS is responsible for

initiating the docking sequence if the dock is already attached when PLTRST# is de-

asserted. POST BIOS writes a 1 to the DCKCTL.DA bit prior to the HD Audio driver de-

asserting CRTS# and detecting and enumerating the codecs attached to the

HDA_DOCK_RST# signal. The HD Audio controller does not directly monitor a hardw are

signal indicating that a dock is attached. Therefore a method outside the scope of this

document must be used to cause the POST BIOS to initiate the docking sequence.

When exiting from D3, CRST# will be asserted. When CRST# bit is “0” (asserted), the

DCKCTL.DA bit is not cleared. Th e dock state machine will be reset such that

HDA_DOCK_EN# will be de-asserted, HDA_DOCK_RST# will be asserted and the

DCKSTS.DM bit will be cleared to reflect this state. When the CRST# bit is de-asserted,

the dock state machine will detect that DCKCTL.DA is set to “1” and will begin

sequencing through the dock process. Note that this does not require any software

intervention.

5.21.1.6 Relationship between HDA_DOCK_RST# and HDA_RST#

HDA_RST# will be asserted when a PLTRST# occurs or when the CRST# bit is 0. As

long as HDA_RST# is asserted, the DOCK_RST# signal will also be asserted.

When PLTRST# is asserted, the DCKCTL.DA and DCKSTS.DM bits will be get cleared to

their default state (0's), and the dock state machine will be reset such that

HDA_DOCK_EN# will be de-asserted, and HDA_DOCK_RST# will be asserted. After any

PLTRST#, POST BIOS software is responsible for detecting that a dock is attached and

then writing a “1” to the DCKCTL.DA bit prior to the HD Audio Bus Driver de-asserting

CRST#.

When CRST# bit is “0” (asserted), the DCKCTL.DA bit is not cleared. The dock state

machine will be reset such that HDA_DOCK_EN# will be de-asserted,

HDA_DOCK_RST# will be asserted and the DCKSTS.DM bit will be cleared to reflect this

state. When the CRST# bit is de-asserted, the dock state machine will detect that

DCKCTL.DA is set to “1” and will begin sequencing through the dock process. Note that

this does not require any software intervention.

Functional Description

242 Intel® ICH8 Family Datasheet

5.22 Intel® Active Management Technology (Intel®

AMT) (Intel® ICH8DO and ICH8M-E Only))

Intel Active Management Technology is a set of advanced manageability features

developed as a direct result of IT customer feedback gained through Intel market

research. Reducing the Total Cost of Ownership (TCO) through improved asset tracking,

remote manageability, and fewer desk-side visits were identified as key IT priorities.

Intel AMT extends the capabilities of existing management solutions by making the

asset information, remote diagnostics, recovery and contain capabilities always

available, or Out of Band (OOB), even when the system is in a low-power “off” state or

the OS is hung.

Another technology feature of Intel Active Technology is System Defense. System

Defense is a Intel AMT feature that is used to stop the propagation of worms and

viruses. Programmable packet filters in the integrated LAN Controller are used to

accomplish this. These filters inspect all incoming and all outgoing packets and decide

whether to block or pass the packets as configured. There is no indication to the host

that a packet has been blocked or accepted.

The logic can be used to accept or block reception to host or transmission to network

paths. Additionally, counter logic can be used to count the number or filter matches for

a given filter. This feature allows for statistical sampling of connections as well as rate

limiting of connections.

5.22.1 Intel® AMT Features

• E-Asset Tag

• OOB HW and SW Inventory Logs

• OOB Alerts

•IDE Redirect

• Serial over LAN for Remote Control

• Remote Diagnostics Execution

•OS Lock-Up Alert

•OS Repair

• Remote BIOS Recovery and Update

5.22.2 Intel® AMT Requirements

Intel AMT is a platform-level solution that utilizes multiple system components

including:

• Intel AMT-Ready ICH8 component

• Intel Gigabit Ethernet PHY (Intel® 82566 Gigabit Platform LAN Connect device)

with Intel® Active Management Technology for remote access

• SPI flash memory with 4 KB sector erase that meets requirements set in

Section 5.23.2.2 (16 Mb minimum for Intel AMT 2.0 (Desktop only) and 32-Mb

minimum for Intel AMT 2.5 (Mobile only) to store asset information, management

software code, and logs

• BIOS to provide asset detection and POST diagnostics (BIOS and Intel AMT can

optionally share same flash memory device)

• Familiar ISV software packages to take advantage of Intel AMT’s platform

management capabilities

Intel® ICH8 Family Datasheet 243

Functional Description

5.23 Serial Peripheral Interface (SPI)

The Serial Peripheral Interface (SPI) is a 4-pin interface that provides a potentially

lower-cost alternative for system flash versus the Firmware Hub on the LPC bus.

The 4-pin SPI interface consists of clock (CLK), master data out (Master Out Slave In

(MOSI)), master data in (Master In Slave Out (MISO)) and an active low chip select

(CS#).

The ICH8 supports two SPI flash devices using two separ ate Chip Select pins. Each SPI

flash device can be up to 16 MBytes. The ICH8 SPI interface supports 20 MHz and 33

MHz SPI devices.

Communication on the SPI bus is done with a Master – Slave protocol. The Slave is

connected to the ICH8 and is impl emented as a tri-state bus.

Note: When SPI is selected by the Boot BIOS Destination Strap and a SPI device is detected

by the ICH8, LPC based BIOS flash is disabled.

5.23.1 SPI Supported Feature Overview

SPI Flash on the ICH8 has two operational modes, descriptor and non-descriptor. Non-

descriptor mode is similar to flash functionality of Intel® ICH7. In this mode, SPI Flash

can only be used for BIOS. Direct read and writes are not supported. BIOS has read/

write access only through register accesses. Through those register accesses BIOS can

read and write to the entire flash without security checking. There is also no support

for the integrated GbE, Manageability Engine, chipset soft straps, as well multiple SPI

Flash components.

Descriptor Mode enables many new features of the chipset

• Integrated GbE and Host CPU for GbE Software

• Intel Active Management Technology (ICH8DO and ICH8M-E Only)

•Intel

® Quiet System Technology (Desktop Only)

• Supports two SPI Flash components using two separate chip select pins

• Hardware enforced security restricting master accesses to different regions

• Chipset Soft Strap region provides the ability to use Flash NVM as an alternative to

hardware pull-up/pull-down resistors for both ICH and MCH

• Supports the SPI Fast Read instruction and frequencies of 33 MHz

• Uses standardized Flash Instruction Set

In Descriptor Mode the Flash is divided into four separate regions:

Only three masters can access the four regions: Host CPU running BIOS code,

Integrated GbE and Host CPU running GbE Software, and ME. The Flash Descriptor is

requires one 4KB Block/Sector. The Integrated GbE needs two 4KB Blocks/Sectors.

BIOS and the Manageability Engine (ME) are the other two regions. The only required

region is Region 0, the Flash Descriptor. Region 0 must be located in the first sector of

component 0 (offset 0).

Region Content

0 Flash Descriptor

1BIOS

2ME

3GbE

Functional Description

244 Intel® ICH8 Family Datasheet

5.23.1.1 Flash Descriptor

The maximum size of the Flash Descriptor is one 4KB block. The information stored in

the Flash Descriptor can only be written during the manufacturing process as its read/

write permissions must be set to Read only when the computer leaves the

manufacturing floor. The Flash Descriptor is broken up into six sections:

The Flash signature as mentioned before is what selects Descriptor Mode as well as

verifying if the flash is programmed and functioning. The data at the bottom of the

flash (offset 0) must be 0FF0A55Ah in order to be in Descriptor mode. The Descriptor

map has pointers to the other six descriptor sections as well as the size of each. The

component section has information about the SPI flash in the system. It has number of

components, density of each, inv alid instructions (such as chip er ase), and frequ encies

for read, fast read and write/erase instructions. The Region section points to the three

other regions as well as the size of each region. The master region contains the security

settings for the flash, granting read/write permissions for each region and identifying

each master. The MCH and ICH chipset soft strap sections contain MCH and ICH

configurable par ameters. The R eserv ed for Chipset Future uses region between the to p

of the MCH strap section and the bottom of the VSCC Table is reserved for future uses

or growth of the existing sections by the chipset. The Descriptor Upper Map is 256B

below the 4KB boundary of the descriptor. This determines the length and base address

of the VSCC Table. The VSCC Table holds the JEDEC ID and the VSCC information of all

the SPI Flash supported by that NVM image. The JEDEC and VSCC information is

necessary to allow devices that meet the compatibility requirements in

Section 5.23.2.2 to work with Intel® AMT, ASF, and/or Intel® Quiet Technology. 256B

is reserved at the top of the Flash Descriptor for use by OEM.

Figure 17. Flash Descriptor

Component

Descriptor

MAP

Signature

Region

Master

ICH S o ft

Straps

MCH Soft

Straps

4KB 256B O EM

Section

Re se rv ed fo r

Ch i p s e t futu re

uses

Descriptor

Upper MA P

VSCC Table

Intel® ICH8 Family Datasheet 245

Functional Description

5.23.1.2 Flash Access

There are two types of flash accesses:

Direct Access:

• Masters are allowed to do direct read only of their primary region

— GbE region can only be directly accessed by the GbE controller. GbE software

must use Program Registers to access the GbE region.

• Master's Host or ME virtual read address is converted into the SPI Flash Linear

Address (FLA) using the Flash Descriptor Region Base/Limit registers

Program Register Access:

• Program Register Accesses are not allowed to cross a 4KB boundary and can not

issue a command that might extend across two componen ts

• Software programs the FLA corresponding to the region desired

— Software must read the devices Pri mary R egion Base/Limit address to create a

FLA.

5.23.1.3 Program Register Software Sequencing

• Supported in Descriptor and Non-Descriptor Mode

• Software has full control over the SPI op codes and transactions

— Same behavior as ICH7

— Additional registers such as SPI Cycle Frequency and Fast Read have been

added in ICH8

• Primary use of software sequencing is wh en using non-standard instructions and as

a backup to hardware sequencing.

5.23.1.4 Direct Access Security

• "Requester ID of the device must match that of the primary Requester ID in the

Master Section

• "Calculated Flash Linear Address must fall between primary region base/limit

• "Direct Write not allowed

• "Direct Read Cache contents are reset to 0's on a read from a different master

— Supports the same cache flush mechanism in ICH7 which includes Program

5.23.1.5 Register Access Security

• Only primary region masters can access the registers

Note: Processor running GbE software can access GbE registers

• Masters are only allowed to read or write those regions they have read/write

permission

• Using the Flash Region Access Permissions, one master can give another master

read/write permissions to their area

• Using the five Protected Range registers, each master can add separate read/write

protection above that granted in the Flash Descriptor for their own accesses

— Example: BIOS may want to protect different regions of BIOS from being

erased

— Ranges can extend across region boundaries

Functional Description

246 Intel® ICH8 Family Datasheet

5.23.2 SPI Device Compatibility Requirements

A variety of SPI flash devices exist in the market. In order for a SPI device to be

compatible with the ICH8 it must meet the minimum requirements detailed in the

following sections.

5.23.2.1 Device Requirements for System BIOS Storage Only

A serial flash device must meet the following minimum requirements when used

explicitly for system BIOS storage.

• Erase size capability of at least one of the following: 64 Kbytes, 4 Kbytes, or 256

bytes.

— If two serial flash devices will be used, they must have the same erase size

capabilities and opcodes.

• Required command set and associated opcodes (Refer to Section 5.23.3.1).

• JEDEC ID Device identification command (Refer to Section 5.23.3.3).

• Device must support multiple writes to a page without requiring a preceding erase

cycle (Refer to Section 5.23.3.4)

• Serial flash device must ignore the upper address bits such that an address of

FFFFFFh simply aliases to the top of the flash memory.

• SPI Compatible Mode 0 support (clock phase is 0 and data is latched on the rising

edge of the clock).

• If the device receives a command that is not supported, the device must complete

the cycle gracefully without any impact on the flash content.

• An erase command (page, sector, block, chip, etc.) must set to 1 (FFh) all bits

inside the designated area (page, sector, block, chip, etc.).

• Minimum density of 4 Mbit (Platform dependent based on size of BIOS).

5.23.2.2 Device Requirements for Intel® AMT, ASF and AFSC Firmware

ICH8 has added the capability that a single SPI flash device can be used to store

system BIOS, Intel

AMT Firmware and GbE EEPROM information. This unified flash configur ation for system

BIOS

and Intel AMT firmware must meet the following minimum requirements to be

compatible with the ICH8:

The following are requirements that are in common with System BIOS only

configuration as listed in Section 5.23.2.1:

Intel® ICH8 Family Datasheet 247

Functional Description

The following is a list of additional requirements specific to configurations 2 and 3:

• 4 Kbytes erase size must be supported.

• Flash device must power up in an unlocked state (no write protection) or use the

write status register to disable write protection. If the write status register must be

unprotected, it must use the enable write status register command 50h or write

enable 06h. Opcode 01h must then be used to write 00h into the write status

write status register, then 06h and 50h must be ignored.

• Byte write must be supported.

— The flexibility to perform a write between 1 byte to 256 bytes is recommended

• A serial flash device that requires the Write Enable command must automatically

clear the Write Enable Latch at the end of Data Program instructions.

• Status Register bit 0 must be set to 1 when a write or erase is in progress and

cleared to 0 when a write or erase is NOT in progress.

• Minimum density of AFSC + BIOS is 8 Mb

• Minimum density of ASF + BIOS is 8 Mb

• Minimum density of Intel® AMT 2.0 (Desktop Only)+BIOS+GbE is 16 Mb;

Minimum density of Intel AMT 2.5 (Mobile Only) + BIOS +GbE is 32 Mb.

5.23.2.3 Device Requirements for GbE

A serial flash device that will be used for both system BIOS and GbE on the same

device must meet the minimum compatibility requirements detailed in Section 5.23.2.1

5.23.3 Serial Flash Command Set

5.23.3.1 Required Command Set for Interoperability

The following table contains a list of commands and the associated opcodes that a SPI-

based serial flash device must support in order to be interoperable with the Intel Serial

Peripheral Interface.

Table 97. Required Commands and Opcodes

Commands OPCODE Notes

Write Status 01h If command is supported, 01h must be the opcode.

Program Data 02h Write Data / Program Data

Read Data 03h

Write Disable 04h

Read Status 05h

Writ e Enable 06h If command is supported, 06h must be the opcode.

Fast Read 0Bh

Enable Write

Status 50h If Write status register must be unlocked it must use thi s

opcode or Write Enable.

Erase Programmab

le Size and opcode programmed in the VSSC Register

JEDEC ID 9Fh Refer to Section 5.23.3.3

Functional Description

248 Intel® ICH8 Family Datasheet

5.23.3.2 Recommended Command Set and Opcodes

The following table lists recommended opcodes for serial flash commands. Using a

command specified below, with the associated opcode, will allow software developers

to streamline their code and will aid in minimizing latencies.

5.23.3.3 JEDEC Device Identification

Since each serial flash device may have unique capabilities and commands, the JEDEC

ID is the necessary mechanism for identifying the device so the uniqueness of the

device can be comprehended by the controller (master). The JEDEC ID uses the opcode

9Fh and a specified implementation and usage model. This JEDEC Standard

Manufacturer and Device ID read method is defined in Standard JESD21-C, PRN03-NV1

and is available on the JEDEC website: www.je dec.org.

5.23.3.4 Multiple Page Write Usage Model

The system BIOS and Intel® Active Management Technology firmware usage models

require that the serial flash device support multiple writes (minimum of 512 writes) to

a page (256 bytes) without requiring a preceding erase command. BIOS commonly

uses capabilities such as counters that are typically implemented by using byte writes

to ‘increment’ the bits within a page that have been designated as the counter. The

Intel AMT firmware usage model requires the capability for multiple data updates within

any given page. These data updates occur via byte writes without executing a

preceding erase to the given page. Both the BIOS and Intel AMT firmware multiple

page write usage models apply to sequential and non-sequential data writes.

Note: This usage model requirement is based on any given bit only being written once from a

‘1’ to a ‘0’ without requiring the preceding erase. An erase would be required to change

bits back to the ‘1’ state.

Table 98. Recommended Command and Opcode Associations

Commands OPCODE Notes

Full Chip Erase C7h

Intel® ICH8 Family Datasheet 249

Functional Description

5.24 Intel® Quiet System Technology (Desktop Only)

The ICH8 implements three PWM and 4 TACH signals for fan speed control.

Note: Intel® Quiet System Technology functionality requires a correctly configured system,

including an appropriate (G)MCH with ME, ME Firmware, and system BIOS support.

5.24.1 PWM Outputs

This signal is driven as open-drain. An external pull-up resistor is integrated into the

fan to provide the rising edge of the PWM output signal. The PWM output is driven low

during reset, which represents 0% duty cycle to the fans. After reset de-assertion, the

PWM output will continue to be driven low until one of the following occurs:

• The internal PWM control register is programmed to a non-zero value by the AFSC

firmware

• The watchdog timer expires (enabled and set at 4 seconds by default).

• The polarity of the signal is inverted by the Intel Quiet System Technology firmware

Note that if a PWM output will be programmed to inverted polarity for a particular fan,

then the low voltage driven during reset represents 100% duty cycle to the fan.

5.24.2 TACH Inputs

This signal is driven as an open-collector or open-drain output from the fan. An

external pull-up is expected to be implemented on the motherboard to provide the

rising edge of the TACH input. This signal has analog hysteresis and digital filtering due

to the potentially slow rise and fall times. This signal has a weak internal pull-up

resistor to keep the input buffer from floating if the TACH input is not connected to a

fan.

5.25 Thermal Sensors

ICH8 integrates two thermal sensors that monitor the temperature within its die. The

thermal sensors are used for Intel Quiet System Technology. The AFSC firmware can

internally access the temperature measured by the sensors and use the data as a

factor to determine how to control the fans.

The ICH8 thermal sensors also provide the capability to protect the ICH8 under a

catastrophic thermal situation. When the sensors are enabled and correctly

programmed by the system BIOS, the ICH8 will shut down the system when the ICH8

thermal limit is reached. Refer to the Thermal Memory Mapped Configuration R egisters

(Section 20.2) for more information on the catastrophic settings.

Functional Description

250 Intel® ICH8 Family Datasheet

5.26 Intel® Quick Resume Technology (Intel® ICH8DH

Only)

ICH8DH implements the following Intel Quick Resume Technology features:

• Visual Off

• Consumer Electronics (CE) like On/Off

5.26.1 5.26.1 Visual Off

Intel Quick Resume Technology provides a new functional state called Visual Off. In

Visual Off the PC appears to be Off but is actually active and able to run program tasks.

The Visual Off state is transparent to the user. It is entered by simply pressing the

power button when the system is On. This turns off the display, sound, front panel

lights and HID devices (e.g. keyboard and mouse) but the PC stays activ e. P erceptually

to the user, the system appears Off in this state. Pressing the power button again will

turn back On the perceptual components that were “muted” in Visual Off.

From the Visual Off state, the system's power management can place the PC in a low

power suspend state (S3) using existing mechanisms. Again, this is transparent to the

end user.

5.26.2 5.26.2 CE-like On/Off

Intel Quick Resume Technology redefines the PC's power button behavior to switch

between user perceived On and Off states like a consumer electronics (CE) device. For

example when a television is turned off there is no shutdown procedure. The viewer

simply turns it Off. Likewise when a modern television is turned On it returns to the

same channel, volume level, color balance, etc. as when it was turned Off. Intel Quick

Resume Technology gives the PC this similar functionality. A simple press of the power

button turns it On or Off. There is no user visible lengthy boot up or shutdown process

as the Visual Off state is used. Therefore, there is no need to exit running applications.

Just as televisions may have multiple power buttons (e.g. on the TV and on a remote

control) so may the PC (e.g. a power button on the system unit and another on the

keyboard). However all power buttons behave the same - On/Off. The PC will not turn

On (wake up) when any key is pressed or the mouse moved just as pressing the

volume button or TV channel button does not cause the TV to turn On. Only a power

button press turns it On and Off.

5.26.3 Intel® Quick Resume Technology Signals

To provide the end user notification of the system power state, it is recommended that

the front panel LED be used to indicate Visual Off in the same way that the front panel

LED is used to indicate the S3 system state. For example, if in the S3 state the front

panel LED is solid amber, also set the front panel LED to be solid amber upon entrance

into Visual Off.

To provide for platform implementation flexibility, the ICH8 implements two Intel Quick

Resume Technology signals which are multiplexed with GPIOs: QRT_STATE0/GPIO27

and QRT_STA TE1/GPIO28. The QR T_STATE[1:0] pins may be used to control LED(s) to

provide end-user notification of the current system state or may be used as GPIO pins

(independently or combined). See section 14 for further details on controlling these

signals.

Intel® ICH8 Family Datasheet 251

Functional Description

5.26.4 Power Button Sequence

When Intel Quick Resume Technology is enabled and the user presses the PWRBTN# to

indicate a desire to put the system into the Visual Off state, the following sequence is

assumed:

1. User presses the Power Button, which causes the PWRBTN# signal to go low.

2. Intel Quick Resume Technology logic sets the EL_PB_STS bit. If the

PWRBTN_INT_EN bit is set, the ICH8 does NOT set the PWRBTN_STS bit at this

point.

3. Intel Quick Resume Technology logic causes an SMI or SCI (depending on the

SMI_OPTION_CNT bit.)

4. If the Intel Quick Resume Technology logic was set to cause an SMI, the SMI

handler executes and then sets the SCI_NOW_CNT bit.

5. The Intel Quick Resume Technology SCI handler executes.

6. The Intel Quick Resume Technology SCI handler needs to cause the PWRBTN_STS

bit to be set, it can do so by setting the PWRBTN_EVENT bit.

Note: When PWRBTN_STS is set, the ICH8 causes an SCI and the normal OS handler for

PWRBTN_STS is called.

5.27 Feature Capability Mechanism

A new set of registers have been added into ICH8 LPC Interface (Device 31, Function 0,

offset E0h – EBh) that allows the system software or BIOS to easily determine the

features supported by ICH8. These registers can be accessed through LPC PCI

configuration space, thus allowing for convenient single point access mechanism for

chipset feature detection.

This set of registers consists of:

Capability ID (FDCAP)

Capability Length (FDLEN)

Capability Version and Vendor-Specific Capability ID (FDVER)

Feature Vector (FVECT)

Functional Description

252 Intel® ICH8 Family Datasheet

5.28 Serial POST Codes Over GPIO

ICH8 adds the extended capability allowing system software to serialize POST or other

messages on GPIO. This capability negates the requirement for dedicated diagnostic

LEDs on the platform. Additionally, based on the newer BTX form factors, the PCI bus

as a target for POST codes is increasingly difficult to support as the total number of PCI

devices supported are decreasing.

5.28.1 Theory of operation

For the ICH8, generation POST code serialization logic will be shared with GPIO. These

GPIO will likely be shared with LED control offered by the Super I/O (SIO) component.

The anticipated usage model is that either the ICH8 or the SIO can drive a pin low to

turn off an LED. In the case of the power LED, the SIO would normally leave its

corresponding pin in a high-Z state to allow the LED to turn on. In this state, the ICH8

can blink the LED by driving its corresponding pin low and subsequently tri-stating the

buffer.

An external optical sensing device can detect the on/off state of the LED . By externally

post-processing the information from the optical device, the serial bit stream can be

recovered. The hardware will supply a ‘sync’ byte before the actual data transmission

to allow external detection of the transmit frequency. The frequency of transmission

should be limited to 1 transition ev ery 1usec to ensure the detector can reliably sample

the on/off state of the LED. To allow flexibility in pull-up resistor values for power

optimization, the frequency of the transmission is programmable via the DRS field in

the GP_SB_CMDSTS register (See Section 9.10.7).

The serial bit stream is Manchester encoded. This choice of transmission ensures that a

transition will be seen on every clock. The 1 or 0 data is based on the transmission

happening during the high or low phase of the clock.

A simplified hardware/software register interface provides control and status

information to track the activity of this block. Software enabling the serial blink

capability should implement an algorithm referenced below to send the serialized

message on the enabled GPIO.

1. Read the Go/Busy status bit in the GP_SB_CMDSTS register and verify it is cleared.

This will ensure that the GPIO is idled and a previously requested message is still

not in progress.

2. Write the data to serialize into the GP_SB_DATA register.

3. Write the DLS and DRS values into the GP_SB_CMDSTS register and set the Go bit.

This may be accomplished using a single write.

By providing a generic capability that can be used both in the main and the suspend

power planes, maximum flexibility can be achieved. A key point to make is that the

ICH8 will not unintentionally drive the LED control pin low unless a serialization is in

progress. System board connections using this serialization capability are required to

use the same power plane controlling the LED as the ICH8 GPIO pin. Otherwise, the

ICH8 GPIO may float low during the message and prevent the LED from being

controlled from the SIO. The hardw are will only be serializing messages when the core

power well is powered and the processor is operational.

Care should be taken to prevent the ICH8 from driving an active ‘1’ on a pin sharing the

serial LED capability. Since the SIO could be driving the line to 0, having the ICH8 drive

a 1 would create a high current path. A recommendation to avoid this condition

involves choosing a GPIO defaulting to an input. The GP_SER_BLINK register (See

Intel® ICH8 Family Datasheet 253

Functional Description

Section 9.10.7) should be set first before changing the direction of the pin to an output.

This sequence ensures the open-drain capability of the buffer is properly configured

before enabling the pin as an output.

5.28.2 Serial Message Format

To serialize the data onto the GPIO, an initial state of hi-Z is assumed. The SIO is

required to have its LED control pin in a high-Z state as well to allow ICH8 to blink the

LED.

The three components of the serial message include the sync, data, and idle fields. The

sync field is 7 bits of ‘1’ data followed by 1 bit of ‘0’ data. Starting from the hi-Z state

(LED on) provides external hardware a known initial condition and a known pattern. In

case one or more of the leading 1 sync bits are lost, the 1’s followed by 0 provide a

clear indication of ‘end of sync’. This pattern will be used to ‘lock’ external sampling

logic to the encoded clock.

The data field is shifted out with the highest byte first (MSB). Within each byte, the

most significant bit is shifted first (MSb).

The idle field is enforced by the hardware and is at least 2 bit times long. The hardware

will not clear the Busy and Go bits until this idle time is met. Supporting the idle time in

hardware prevents time-based counting in BIOS as the hardware is immediately ready

for the next serial code when the Go bit is cleared. Note that the idle state is

represented as a high-Z condition on the pin. If the last transmitted bit is a ‘1’,

returning to the idle state will result in a final 0-1 transition on the output Manchester

data. Two full bit times of idle correspond to a count of 4 time intervals (the width of

the time interval is controlled by the DRS field).

The waveform below shows a 1-byte serial write with a data byte of 5Ah. The internal

clock and bit position are for reference purposes only. The Manchester D is the

resultant data generated and serialized onto the GPIO. Since the buffer is operating in

open-drain mode the transitions are from hi-Z to 0 and back.

§ §

I nt ernal Clo c k

M anchest e r D

8-bit sync field

(1111_1110)

Bit 7 0123456

5A data byte 2 clk

idle

Functional Description

254 Intel® ICH8 Family Datasheet

Intel® ICH8 Family Datasheet 255

6 Register and Memory Mapping

The ICH8 contains registers that are located in the processor’s I/O space and memory

space and sets of PCI configuration registers that are located in PCI configuration

space. This chapter describes the ICH8 I/O and memory maps at the register-set lev el.

bit descriptions are provided in the following chapters. The following notations and

definitions are used in the register/instruction description chapters.

RO Read Only . In some cases, If a register is read only , writes to this

separate registers are located at the same location where a read

accesses one of the registers and a write accesses the other

WO Write Only. In some cases, If a register is write only, reads to

this register location have no effect. However, in other cases,

two separate registers are located at the same location where a

read accesses one of the registers and a write accesses the

other register. See the I/O and memory map tables for details.

R/W Read/Write. A register with this attribute can be read and

written.

R/WC Read/Write Clear. A register bit with this attribute can be read

and written. However, a write of 1 clears (sets to 0) the

corresponding bit and a write of 0 has no effect.

R/WO Read/Write-Once. A register bit with this attribute can be

written only once after power up. After the first write, the bit

becomes read only.

R/WLO R ead/W rite, Lock-Once. A register bit with this attribute can be

written to the non-locked value multiple times, but to the locked

value only once. After the locked v alue has been written, the bit

becomes read only.

Default When ICH8 is reset, it sets its registers to predetermined default

states. The default state represents the minimum functionality

feature set required to successfully bring up the system. Hence,

it does not represent the optimal system configur ation. It is the

responsibility of the system initialization software to determine

configuration, operating parameters, and optional system

features that are applicable, and to program the ICH8 registers

accordingly.

Bold Register bits that are highlighted in bold text indicate that the

bit is implemented in the ICH8. Register bits that are not

implemented or are hardwired will remain in plain text.

6.1 PCI Devices and Functions

The Intel ICH8 incorporates a variety of PCI devices and functions, as shown in

Table 99. They are divided into seven logical devices. The first is the DMI-To-PCI bridge

(Device 30). The second device (Device 31) contains most of the standard PCI

functions that always existed in the PCI-to-ISA bridges (South Bridges), such as the

Intel PIIX4 or Intel PIIX6. The third and fourth (Device 29 and Device 26) are the USB

256 Intel® ICH8 Family Datasheet

(and USB2) host controller devices. The fifth (Device 28) is PCI Express device. The

sixth (Device 27) is HD Audio controller device, and the seventh (Device 25) is the GbE

controller device.

If for some reason, the particular system platform does not want to support any one of

the Device Functions, with the exception of D30:F0, they can individually be disabled.

The integrated LAN controller will be disabled if no Platform LAN Connect component is

detected (See Chapter 5.3). When a function is disabled, it does not appear at all to the

software. A disabled function will not respond to any register reads or writes, insuring

that these devices appear hidden to software.

NOTES:

1. The PCI-to-LPC bridge contains registers that control LPC, Power Management, System

Management, GPIO, Processor Interface, RTC, Interrupts, Timers, and DMA

2. When USB ports 9, 10 and EHCI controller #2 are disabled, the UHCI host controller #4

will be mapped to D29:F3. Otherwise, it will be mapped to D26:F0.

Table 99. PCI Devices and Functions

Bus:Device:F unction Function Descriptio n

Bus 0:Device 30:Function 0 PCI-to-PCI Bridge

Bus 0:Device 31:Function 0 LPC Cont roller1

Bus 0:Device 31:Function 1 IDE Controller

Bus 0:Device 31:Functi on 2 SATA Controlle r #1

Bus 0:Device 31:Function 3 SMBus Controller

Bus 0:Device 31:Func tion 5 SATA Controller #2

Bus 0:Device 31:Function 6 Thermal Subsystem

Bus 0:Device 29:Function 0 USB UHCI Controller #1

Bus 0:Device 29:Function 1 USB UHCI Controller #2

Bus 0:Device 29:Function 2 USB UHCI Controller #3

Bus 0:Device 29:Function 3 USB UHCI Controller #42

Bus 0:Device 26:Function 0 USB1.1 UHCI Controller #42

Bus 0:Device 26:Function 1 USB1.1 UHCI Controller #5

Bus 0:Device 29:Function 7 USB 2.0 EHCI Controller #1

Bus 0:Device 26:Fucntion 7 USB2 EHCI Controller #2

Bus 0:Device 28:Function 0 PCI Express* Port 1

Bus 0:Device 28:Function 1 PCI Express Port 2

Bus 0:Device 28:Function 2 PCI Express Port 3

Bus 0:Device 28:Function 3 PCI Express Port 4

Bus 0:Device 28:Function 4 PCI Express Port 5

Bus 0:Device 28:Function 5 PCI Express Port 6

Bus 0:Device 27:Function 0 Intel® High Definition Audio Controller

Bus 0:Device 25:Func tion 0 GbE Controller

Intel® ICH8 Family Datasheet 257

6.2 PCI Configuration Map

Each PCI function on the ICH8 has a set of PCI configuration registers. The register

address map tables for these register sets are included at the beginning of the chapter

for the particular function.

Configuration Space registers are accessed through configuration cy cles on the PCI bus

by the Host bridge using configuration mechanism #1 detailed in the PCI Local Bus

Specification, Revision 2.3.

Some of the PCI registers contain reserved bits. Software must deal correctly with

fields that are reserved. On reads, software must use appropriate masks to extr act the

defined bits and not rely on reserved bits being any particular value. On writes,

software must ensure that the values of reserved bit position s are pres e rved. That is,

the values of reserv ed bit positions mu st first be read, merged with the new values for

other bit positions and then written back. Note the software does not need to perform

read, merge, write operation for the configuration address register.

In addition to reserved bits with in a register, the configuration space contains reserved

locations. Software should not write to reserved PCI configuration locations in the

device-specific region (above address offset 3Fh).

6.3 I/O Map

The I/O map is divided into Fixed and Variable address ranges. Fixed r anges cannot be

moved, but in some cases can be disabled. Variable ranges can be moved and can also

be disabled.

6.3.1 Fixed I/O Address Ranges

Table 100 shows the Fixed I/O decode ranges from the processor perspective. Note

that for each I/O range, there may be separate behavior for reads and writes. DMI

(Direct Media Interface) cycles that go to target ranges that are marked as “Reserved”

will not be decoded by the ICH8, and will be passed to PCI unless the Subtractive

Decode Policy bit is set (D31:F0:Offset 42h, bit 0). If a PCI master targets one of the

fixed I/O target ranges, it will be positively decoded by the ICH8 in medium speed.

Refer to Table 100 for a complete list of all fixed I/O registers. Address ranges that are

not listed or marked “Reserved” are not decoded by the ICH8 (unless assigned to one

of the variable ranges).

258 Intel® ICH8 Family Datasheet

Table 100. Fixed I/O Ranges Decoded by Intel® ICH8 (Sheet 1 of 2)

I/O

Address Read Target Write Target Internal Unit

00h–08h DMA Controller DMA Controller DMA

09h–0Eh RESERVED DMA Controller DMA

0Fh DMA Controller DMA Controller DMA

10h–18h DMA Controller DMA Controller DMA

19h–1Eh RESERVED DMA Controller DMA

1Fh DMA Controller DMA Controller DMA

20h–21h Interrupt Controller Interrupt Controller Interrupt

24h–25h Interrupt Controller Interrupt Controller Interrupt

28h–29h Interrupt Controller Interrupt Controller Interrupt

2Ch–2Dh Interrupt Controller Interrupt Controller Interrupt

2E–2F LPC SIO LPC SIO Forwarded to LPC

30h–31h Interrupt Controller Interrupt Controller Interrupt

34h–35h Interrupt Controller Interrupt Controller Interrupt

38h–39h Interrupt Controller Interrupt Controller Interrupt

3Ch–3Dh Interrupt Controller Interrupt Controller Interrupt

40h–42h Timer/Counter Timer/Counter P IT (82 54)

43h RESERVED Timer/Counter PIT

4E–4F LPC SIO LPC SIO Forwarded to LPC

50h–52h Timer/Counter Timer/Counter PIT

53h RESERVED Timer/Counter PIT

60h Microcontroller Microcontroller Forwarded to LPC

61h NMI Controller NMI Controller Processor I/F

62h Microcontroller Microcontroller Forwarded to LPC

64h Microcontroller Microcontroller Forwarded to LPC

66h Microcontroller Microcontroller Forwarded to LPC

70h RESERVED NMI and RTC Controller RTC

71h RTC Controller RTC Controller RTC

72h RTC Controller NMI and RTC Controller RTC

73h RTC Controller RTC Controller RTC

74h RTC Controller NMI and RTC Controller RTC

75h RTC Controller RTC Controller RTC

76h RTC Controller NMI and RTC Controller RTC

77h RTC Controller RTC Controller RTC

80h DMA Controller, or LPC, or

PCI DMA Controller and LPC or

PCI DMA

81h–83h DMA Controller DMA Controller DMA

84h–86h DMA Controller DMA Controller and LPC or

PCI DMA

87h DMA Controller DMA Controller DMA

Intel® ICH8 Family Datasheet 259

NOTES:

1. A read to this address will subtractively go to PCI, where it will master abort.

2. Mobile Only: Only if IDE I/O space is enabled (D31:F1:40 bit 15) and the IDE controller is

in legacy mode. Otherwise, the target is PCI.

88h DMA Controller DMA Controller and LPC or

PCI DMA

89h–8Bh DMA Controller DMA Controller DMA

8Ch–8Eh DMA Controller DM A Controller and LPC or

PCI DMA

08Fh DMA Controller DMA Controller DMA

90h–91h DMA Controller DMA Controller DMA

92h Reset Generator Reset Generator Processor I/F

93h–9Fh DMA Controller DMA Controller DMA

A0h–A1h Interrupt Controller Interrupt Controller Interrupt

A4h–A5h Interrupt Controller Interrupt Controller Interrupt

A8h–A9h Interrupt Controller Interrupt Controller Interrupt

ACh–ADh Interrupt Controller Interrupt Controller Interrupt

B0h–B1h Interrupt Controller Interrupt Controller Interrupt

B2h–B3h Power Management Power Management Power

Management

B4h–B5h Interrupt Controller Interrupt Controller Interrupt

B8h–B9h Interrupt Controller Interrupt Controller Interrupt

BCh–BDh Interrupt Controller Interrupt Controller Interrupt

C0h–D1h DMA Controller DMA Controller DMA

D2h–DDh RESERVED DMA Controller DMA

DEh–DFh D MA Controller DMA Controller DMA

F0h PCI and Master Abort1FERR#/IGNNE# / Interrupt

Controller Processor I/F

170h–177h IDE Controller (Mob ile only),

SATA Controller, or PCI IDE Controller (Mobile only),

SATA Controller, or PCI

Forw arded to IDE

(Mobile only) or

SATA

1F0h–1F7h IDE Controller (Mobile o nly),

SATA Controller, or PCI2 IDE Controller (Mobile only),

SATA Controller, or PCI

Forw arded to IDE

(Mobile only) or

SATA

376h IDE Controller (Mobile only),

SATA Controller, or PCI IDE Controller (Mobile only),

SATA Controller, or PCI

Forw arded to IDE

(Mobile only) or

SATA

3F6h IDE Cont roller (Mobil e only),

SATA Controller, or PCI 2 IDE Controller (Mobile only),

SATA Controller, or PCI

Forw arded to IDE

(Mobile only) or

SATA

4D0h–4D1h Interrupt Controller Interrupt Controller Interrupt

CF9h Reset Generator Reset Generator Processor I/F

Table 100. Fixed I/O Ranges Decoded by Intel® ICH8 (Sheet 2 of 2)

I/O

Address Read Target W rit e Target Internal Unit

260 Intel® ICH8 Family Datasheet

6.3.2 Variable I/O Decode Ranges

Table 101 shows the Variable I/O Decode Ranges. They are set using Base Address

Registers (BARs) or other configuration bits in the various PCI configuration spaces.

The PNP software (PCI or ACPI) can use their configuration mechanisms to set and

adjust these values.

Warning: The Variable I/O Ranges should not be set to conflict with the Fixed I/O Ranges.

Unpredictable results if the configuration software allows conflicts to occur. The ICH8

does not perform any checks for conflicts.

NOTE:

1. Decode range size determined by D31:F0:ADh:bits 5:4.

Table 101. Variable I/O Decode Ranges

Range Name Mappable Size

(Bytes) Target

ACPI Anywhere in 64 KB I/O Space 64 Power

Management

IDE Bus Master

(Mobile only) Anywhere in 64 KB I/O Space 16 IDE Unit

Native IDE Command

(Mobile only) Anywhere in 64 KB I/O Space 8 IDE Unit

Native IDE Control

(Mobile only) Anywhere in 64 KB I/O Space 4 IDE Unit

USB UHCI Controller #1 Anywhere in 64 KB I/O Space 32 USB Unit 1

USB UHCI Controller #2 Anywhere in 64 KB I/O Space 32 USB Unit 2

USB UHCI Controller #3 Anywhere in 64 KB I/O Space 32 USB Unit 3

USB UHCI Controller #4 Anywhere in 64 KB I/O Space 32 USB Unit 4

USB UHCI Controller #5 Anywhere in 64 KB I/O Space 32 USB Unit 5

SMBus Anywhere in 64 KB I/O Space 32 SMB Unit

TCO 96 Bytes above ACPI Base 32 TCO Unit

GPIO Anywhere in 64 KB I/O Space 64 GPIO Unit

Parallel Port 3 Ranges in 64 KB I/O Space 8 LPC Peripheral

Serial Port 1 8 Ranges in 64 KB I/O Space 8 LPC Peripheral

Serial Port 2 8 Ranges in 64 KB I/O Space 8 LPC Peripheral

Floppy Disk Controller 2 Ranges in 64 KB I/O Space 8 LPC Peripheral

LAN Anywhere in 64 KB I/O Space 32 LAN Unit

LPC Generic 1 Anywhere in 64 KB I/O Space 4 to 256 LPC Peripheral

LPC Generic 2 Anywhere in 64 KB I/O Space 4 to 256 LPC Peripheral

LPC Generic 3 Anywhere in 64 KB I/O Space 4 to 256 LPC Peripheral

LPC Generic 4 Anywhere in 64 KB I/O Space 4 to 256 LPC Peripheral

I/O Trapping Ranges Anywhere in 64 KB I/O Space 1 to 256 Trap on

Backbone

Intel® ICH8 Family Datasheet 261

6.4 Memory Map

Table 102 shows (from the processor perspective) the memory ranges that the ICH8

decodes. Cycles that arrive from DMI that are not directed to any of the internal

memory targets that decode directly from DMI will be driven out on PCI unless the

Subtractive Decode Policy bit is set (D31:F0:Offset 42h, bit 0).

PCI cycles generated by external PCI masters will be positively decoded unless they fall

in the PCI-to-PCI bridge memory forwarding ranges (those addresses are reserved for

PCI peer-to-peer traffic). If the cycle is not in the internal LAN controller’s r ange, it will

be forwarded up to DMI. Software must not attempt locks to the ICH8’s memory-

mapped I/O ranges for EHCI and HPET. If attempted, the lock is not honored which

means potential deadlock conditions may occur.

Table 102. Memory Decode Ranges from Processor Pe rspective (Sheet 1 of 2)

Memory Range Target Dependency/Comments

0000 0000h–000D FFFFh

0010 0000h–TOM

(Top of Memory) Main Memory TOM registers in Host controller

000E 0000h–000E FFFFh Firmware Hub Bit 6 in Firmware Hub Decode Enable

000F 0000h–000F FFFFh Firmware Hub Bit 7 in Firmware Hub Decode Enable

FEC0 x000h–FEC0 x040h IO(x) APIC inside ICH8 X is controlled via APIC Range Select

(ASEL) field and APIC Enable (AEN) bit

FEC1 0000h–FEC1 7FFF PCI Express* Port 1 PCI Express* Root Port 1 I/OxAPIC

Enable (PAE) set

FEC1 8000h–FEC1 8FFFh PCI Express* Port 2 PCI Express* Root Port 2 I/OxAPIC

Enable (PAE) set

FEC2 0000h–FEC2 7FFFh PCI Express* Port 3 PCI Express* Root Port 3 I/OxAPIC

Enable (PAE) set

FEC2 8000h–FEC2 8FFFh PCI Express* Port 4 PCI Express* Root Port 4 I/OxAPIC

Enable (PAE) set

FEC3 0000h–FEC3 7FFFh PCI Express* Port 5 PCI Express* Root Port 5 I/OxAPIC

Enable (PAE) set

FEC3 8000h–FEC3 8FFFh PCI Express* Port 6 PCI Express* Root Port 6 I/OxAPIC

Enable (PAE) set

FED4 0000h–FED4 BFFFh TPM on LPC

FFC0 0000h–FFC7 FFFFh

FF80 0000h–FF87 FFFFh Firmware Hub (or PCI)2Bit 8 in Firmware Hub Decode Enable

FFC8 0000h–FFCF FFFFh

FF88 0000h–FF8F FFFFh Firmware Hub (or PCI)2Bit 9 in Firmware Hub Decode Enable

FFD0 0000h–FFD7 FFFFh

FF90 0000h–FF97 FFFFh Firmware Hub (or PCI)2Bit 10 in Firmware Hub Decode Enable

FFD8 0000h–FFDF FFFFh

FF98 0000h–FF9F FFFFh Firmware Hub (or PCI)2Bit 11 in Firmware Hub Decode Enable

FFE0 000h–FFE7 FFFFh

FFA0 0000h–FFA7 FFFFh Firmware Hub (or PCI)2Bit 12 in Firmware Hub Decode Enable

262 Intel® ICH8 Family Datasheet

NOTES:

1. Software must not attempt locks to memory mapped I/O ranges for USB EHCI or High

Precision Event Timers. If attempted, the lock is not honored, which means potential

deadlock conditions may occur.

2. PCI is the tar get when the Boot BIOS Destination selection bi t is low (Chipset Conf ig

Registers:Offset 3401:bit 3). When PCI selected, the Firmware Hub Decode Enable bits

have no effect.

FFE8 0000h–FFEF FFFFh

FFA8 0000h–FFAF FFFFh Firmware Hub (or PCI)3Bit 13 in Firmware Hub Decode Enable

FFF0 0000h–FFF7 FFFFh

FFB0 0000h–FFB7 FFFFh Firmware Hub (or PCI)2Bit 14 in Firmware Hub Decode Enable

FFF8 0000h–FFFF FFFFh

FFB8 0000h–FFBF FFFFh Firmware Hub (or PCI)2

Always enabled.

The top two, 64 KB blocks of this range

can be swapped, as described in

Section 7.4.1.

FF70 0000h–FF7F FFFFh

FF30 0000h–FF3F FFFFh Firmware Hub (or PCI)2Bit 3 in Firmware Hub Decode Enable

FF60 0000h–FF6F FFFFh

FF20 0000h–FF2F FFFFh Firmware Hub (or PCI)2Bit 2 in Firmware Hub Decode Enable

FF50 0000h–FF5F FFFFh

FF10 0000h–FF1F FFFFh Firmware Hub (or PCI)2Bit 1 in Firmware Hub Decode Enable

FF40 0000h–FF4F FFFFh

FF00 0000h–FF0F FFFFh Firmware Hub (or PCI)2Bit 0 in Firmware Hub Decode Enable

128 KB anywhere in 4-

GB range Integrated LAN

Controller Enable via BAR in Device 25:Function 0

(Integrated LAN Controller)

1 KB anywhere in 4-GB

range USB EHCI Controller #11Enable via standard PCI mechanism

(Device 29, Function 7)

1 KB anywhere in 4-GB

range USB EHCI Controller #21Enable via standard PCI mechanism

(Device 26, Function 7)

512 B anywhere in 64-bit

addressing space Intel® High Definition

Audio Host Controller Enable via standard PCI mechanism

(Device 27, Function 0)

FED0 X000h–FED0 X3FFh High Precision Event

Timers 1

BIOS determines the “fixed” location

which is one of four, 1-KB ranges where X

(in the first column) is 0h, 1h, 2h, or 3h.

All other PCI None

Table 102. Memory Decode Ranges from Processor Perspective (Sheet 2 of 2)

Memory Range Target Dependency/Comments

Intel® ICH8 Family Datasheet 263

6.4.1 Boot-Block Update Scheme

The ICH8 supports a “top-block swap” mode that has the ICH8 swap the top block in

the Firmware Hu b (the boot block) with another location. This allows for safe update of

the Boot Block (even if a power failure occurs). When the “TOP_SWAP” Enable bit is

set, the ICH8 will invert A16 for cycles targeting Firmware Hub space. When this bit is

0, the ICH8 will not invert A16. This bit is automatically set to 0 by RTCRST#, but not

by PLTRST#.

The scheme is based on the concept that the top block is reserved as the “boot” block,

and the block immediately below the top block is reserved for doing boot-block

updates.

The algorithm is:

1. Software copies the top block to the block immediately below the top

2. Software checks that the copied block is correct. This could be done by performing

a checksum calculation.

3. Software sets the TOP_SWAP bit. This will invert A16 for cycles going to the

Firmware Hub. processor access to FFFF_0000h through FFFF_FFFFh will be

directed to FFFE_0000h through FFFE_FFFFh in the Fi rmware Hub, and processor

accesses to FFFE_0000h through FFFE_FFFF will be directed to FFFF_0000h

through FFFF_FFFFh.

4. Software erases the top block

5. Software writes the new top block

6. Software checks the new top block

7. Software clears the TOP_SWAP bit

8. Software sets the Top_Swap Lock-Down bit

If a power failure occurs at any point after step 3, the system will be able to boot from

the copy of the boot block that is stored in the block below the top. This is because the

TOP_SWAP bit is backed in the RTC well.

Note: The top-block swap mode may be forced by an external strapping option (See

Section 2.26.1). When top-block swap mode is forced in this manner, the TOP_SWAP

bit cannot be cleared by software. A re-boot with the str ap remov e d will be required to

exit a forced top-block swap mode.

Note: Top-block swap mode only affects accesses to the Firmware Hub space, not feature

space.

Note: The top-block swap mode has no effect on accesses below FFFE_0000h.

§ §

264 Intel® ICH8 Family Datasheet

Intel® ICH8 Family Datasheet 265

Chipset Configuration Registers

7 Chipset Configuration Registers

This section describes all registers and base functionality that is related to chipset

configuration and not a specific interface (such as LPC, PCI, or PCI Express*). It

contains the root complex register block, which describes the behavior of the upstream

internal link.

This block is mapped into memory space, using register RCBA of the PCI -to-LPC bridge.

Accesses in this space must be limited to 32-(DW) bit quantities. Burst accesses are

not allowed.

7.1 Chipset Configuration Registers (Memory Space)

Note: Address locations that are not shown should be treated as Reserved (see Section 6.2

for details).

Table 103. Chipset Configuration Register Memory Map (Memory Space) (Sheet 1 of 3)

Offset Mnemonic Register Name Default Type

0000–0003h VCH Virtual Channel Capability Header 10010002h RO

0004–0007h VCAP1 Virtual Channel Capability #1 00000801h RO

0008–000Bh VCAP2 Virtual Channel Capability #2 00000001h RO

000C–000Dh PVC Port VC Control 0000h R/W, RO

000E–000Fh PVS Port VC Status 0000h RO

0010–0013h V0CAP VC 0 Resource Capability 00000001h RO

0014–0017h V0CTL VC 0 Resource Control 800000FFh R/W, RO

001A–001Bh V0STS VC 0 Resource Status 0000h RO

001C–001Fh V1CAP VC 1 Resource Capability 30008010h R/WO, RO

0020–0023h V1CTL VC 1 Resource Control 00000000h R/W, RO

0026–0027h V1STS VC 1 Resource Status 0000h RO

0030–006Fh PAT Port Arbitration Table

0088–008Bh CIR1 Chipset Initialization Register 1 00000000h R/WO, RO

0100–0103h RCTCL Root Complex T opology Capability

List 1A010005h RO

0104–0107h ESD Element Self Description 00000602h R/WO, RO

0110–0113h ULD Upstream Link Descriptor 00000001h R/WO, RO

0118–011Fh ULBA Upstream Link Base Address 00000000000000

00h R/WO

0120–0123h RP1D Root Port 1 Descriptor 01xx0002h R/WO, RO

0128–012Fh RP1BA Root Port 1 Base Address 00000000000E00

00h RO

0130–0133h RP2D Root Port 2 Descriptor 02xx0002h R/WO, RO

0138–013Fh RP2BA Root Port 2 Base Address 00000000000E10

00h RO

Chipset Configuration Registers

266 Intel® ICH8 Family Datasheet

0140–0143h RP3D Root Port 3 Descriptor 03xx0002h R/WO, RO

0148–014Fh RP3BA Root Port 3 Base Address 00000000000E20

00h RO

0150–0153h RP4D Root Port 4 Descriptor 04xx0002h R/WO, RO

0158–015Fh RP4BA Root Port 4 Base Address 00000000000E30

00h RO

0160–0163h HDD Intel® High Definition Audio

Descriptor 15xx0002h R/WO, RO

0168–016Fh HDBA Intel High Defini tion Audio Base

Address 00000000000D80

00h RO

0170–0173h RP5D Root Port 5 Descriptor 05xx0002h R/WO, RO

0178–017Fh RP5A Root Port 5 Base Address 00000000000E40

00h RO

0180–0183h RP6D Root Port 6 Descriptor 06xx0002h R/WO, RO

0188–018Fh RP6BA Root Port 6 Base Address 00000000000E50

00h RO

01A0–01A3h ILCL Internal Link Capability List 00010006h RO

01A4–01A7h LCAP Link Capabilities 00012441h RO, R/WO

01A8–01A9h LCTL Link Control 0000h R/W

01AA–01ABh LSTS Link Status 0041h RO

01FC–01FDh CIR3 Chipset Initialization Register 3 0000h R/W, RO

0200–0201h CIR4 Chipset Initialization Register 4 0000h R/W, RO

0220–0223h B CR Backbone Configuration Register 00000000 R/W

0224–0227h RPC Root Port Configuration 0000000xh R/W, RO

0234–0237h DMIC DMI Control Register 00000000h R/W, RO

0238–023Bh RPFN Root Port Function Number for

PCI Express Root Po rts 00543210h R/WO, RO

1D40–1D47h CIR5 Chipset Initialization Register 5 00000000000000

00h R/W, R/

1E00–1E03h TRSR Trap Status Register 00000000h R/WC, RO

1E10–1E17h TRCR Trapped Cycle Register 00000000000000

00h RO

1E18–1E1Fh TWDR Trapped Write Data Register 00000000000000

00h RO

1E80–1E87h IOTR0 I/O Trap Register 0 00000000000000

00h R/W, RO

1E88–1E8Fh IOTR1 I/O Trap Register 1 00000000000000

00h R/W, RO

1E90–1E97h IOTR2 I/O Trap Register 2 00000000000000

00h R/W, RO

1E98–1E9Fh IOTR3 I/O Trap Register 3 00000000000000

00h R/W, RO

Table 103. Chipset Configuration Register Memory Map (Memory Space) (Sheet 2 of 3)

Offset Mnemonic Register Name Default Type

Intel® ICH8 Family Datasheet 267

Chipset Configuration Registers

2010–2013h DMC DMI Miscellaneous Control

2024–2027h CIR6 Chipset Initialization Register 6

(Mobile On ly) 0B2030XXh R/W, RO

2034–2037h CIR7 Chipset Initialization Register 7 B2B477CCh R/W

3000–3001h TCTL TCO Control 00h R/W

3100–3103h D31IP Device 31 Interrupt Pin 03243210h R/W, RO

3104–3107h D30IP Device 30 Interrupt Pin 00000000h R/W, RO

3108–310Bh D29IP Device 29 Interrupt Pin 10004321h R/W

310C–310Fh D28IP Device 28 Interrupt Pin 00004321h R/W

3110–3113h D27IP Device 27 Interrupt Pin 00000001h R/W

3114–3117h D26IP Device 26 Interrupt Pin 30000021h R/W, RO

3118–3121h D25IP Device 25 Interrupt Pin 00000001h R/W, RO

3140–3141h D31IR Device 31 Interrupt Route 3210h R/W

3144–3145h D29IR Device 29 Interrupt Route 3210h R/W

3146–3147h D28IR Device 28 Interrupt Route 3210h R/W

3148–3149h D27IR Device 27 Interrupt Route 3210h R/W

314C–314Dh D26IR Device 26 Interrupt Route 3210h R/W

3150–3151h D25IR Device 25 Interrupt Route 3210h R/W

31FF–31FFh OIC Other Interrupt Control 00h R/W

3400–3403h RC RTC Configuration 00000000h R/W,

R/WLO

3404–3407h HPTC High Precision Timer

Configuration 00000000h R/W

3410–3413h GCS General Control and Status 0000000xh R/W,

R/WLO

3414–3414h BUC Backed Up Control

0000001xb

(Mobile)

0000000xb

(Desktop)

R/W

3418–341Bh FD Function Disable See bit description R/W, RO

341C–341Fh CG Clock Gating (Mobile Only) 00000000h R/W, RO

3420h FDSW Function Disable SUS Well 00h R/W, RO

3430h CIR8 Chipset Initialization Register 8 00h R/W, RO

350Ch-350Fh CIR9 Chipset Initialization Register 9 00000000h R/W, RO

Table 103. Chipset Configuration Register Memory Map (Memory Space) (Sheet 3 of 3)

Offset Mnemonic Register Name Default Type

Chipset Configuration Registers

268 Intel® ICH8 Family Datasheet

7.1.1 VCH—Virtual Channel Capability Header Register

Offset Address: 0000–0003h Attribute: RO

Default Value: 10010002h Size: 32-bit

7.1.2 VCAP1—Virtual Channel Capability #1 Register

Offset Address: 0004–0007h Attribute: RO

Default Value: 00000000h Size: 32-bit

7.1.3 VCAP2—Virtual Channel Capability #2 Register

Offset Address: 0008–000Bh Attribute: RO

Default Value: 00000001h Size: 32-bit

Bit Description

31:20 Next Capability Offset (NCO) — RO. Indicates the next item in the list.

19:16 Capability Version (CV) — RO. Indicates support as a version 1 capability structure.

15:0 Capability ID (CID) — RO. Indicates this is the Virtual Channel capability item.

Bit Description

31:12 Reserved

11:10 Port Arbitration Table Entry Size (PATS) — RO. Indicate s the size of the port

arbitration table is 4 bits (to allow up to 8 ports).

9:8 Reference Clock (RC) — RO. Fixed at 100 ns.

7 Reserved

6:4 Low Priority Extended VC Count (LPEVC) — RO. Indicates that there are no additional

VCs of low priority with extended capabilities.

3 Reserved

2:0 Extended VC Count (EVC) — RO. Indicates that there is one additional VC (VC1) that

exists with extended capabilities.

Bit Description

31:24 VC Arbitration Table Offset (ATO) — RO. Indicates that no table is present for VC

arbitration since it is fixed.

23:8 Reserved

7:0 VC Arbitration Capability (AC) — RO. Indicates that the VC arbitration is fixed in the

root complex.

Intel® ICH8 Family Datasheet 269

Chipset Configuration Registers

7.1.4 PVC—Port Virtual Channel Control Register

Offset Address: 000C–000Dh Attribute: R/W, RO

Default Value: 0000h Size: 16-bit

7.1.5 PVS—Port Virtual Channel Status Register

Offset Address: 000E–000Fh Attribute: RO

Default Value: 0000h Size: 16-bit

7.1.6 V0CAP—Virtual Channel 0 Resource Capability Register

Offset Address: 0010–0013h Attribute: RO

Default Value: 00000001h Size: 32-bit

Bit Description

15:04 Reserved

3:1 VC Arbitration Select (AS) — RO. Indicates which VC should be programmed in the

VC arbitration table. The root complex takes no action on the setting of this field

since there is no arbitration table.

0Load VC Arbitration Table (LAT) — RO. Indicates that the table programmed should

be loaded into the VC arbitration table. This bit is defined as read/write with always

returning 0 on reads.

Bit Description

15:01 Reserved

0VC Arbitration Table St atus (VAS) — RO. Indicates the c o herency status of the VC

Arbitration table when it is being updated. This field is always 0 in the root complex

since there is no V C arbitration table.

Bit Description

31:24 Port Arbitr ation Table Offset (A T) — RO. This VC implements no port arbi tration table

since the arbitration is fixed.

23 Reserved

22:16 Maximum Time Slot s (MTS) — RO. This VC implements fixed arbitration, and

therefore this field is not used.

15 Reject Snoop Transactions (RTS) — RO. This VC must be able to take snoopable

transactions.

14 Advanced Packet Switching (APS) — RO. This VC is capable of all transactions, not

just advanced packet switching transactions.

13:8 Reserved

7:0 Port Arbitration Capability (PAC) — RO. Indicates that this VC uses fixed port

arbitration.

Chipset Configuration Registers

270 Intel® ICH8 Family Datasheet

7.1.7 V0CTL—Virtual Channel 0 Resource Control Register

Offset Address: 0014–0017h Attribute: R/W, RO

Default Value: 800000FFh Size: 32-bit

7.1.8 V0STS—Virtual Channel 0 Resource Status Register

Offset Address: 001A–001Bh Attribute: RO

Default Value: 0000h Size: 16-bit

Bit Description

31 Virtual Channel Enable (EN) — RO. Always set to 1. VC0 is always enabled and

cannot be disabled.

30:27 Reserved

26:24 Virtual Channel Identifier (ID) — RO. Indicates the ID to use for this virtual channel.

23:20 Reserved

19:17 Port Arbitr ation Select (PAS) — R/W. Indicates which port table is being

programmed. The root complex takes no action on this setting since the arbitration is

fixed and there is no arbitration table.

16 Load Port Arbitration Table (LAT) — RO. The root complex does n o t implement an

arbitration table for this virtual channel.

15:8 Reserved

7:1 Transaction Class / Virtual Channel Map (TVM) — R/W. Indicates which

transaction classes are mapped to this virtual channel. When a bit is set, this

transaction class is mapped to the virtual channel.

0 Reserved

Bit Description

15:02 Reserved

1VC Negotiation Pending (NP ) — RO. When set, indicates the virtual channel is still

being negotiated with ingress ports.

0Port Arbitration Tables Status (ATS) — RO. There is no port arbitration table for this

VC, so this bit is reserved at 0.

Intel® ICH8 Family Datasheet 271

Chipset Configuration Registers

7.1.9 V1CAP—Virtual Channel 1 Resource Capability Register

Offset Address: 001C–001Fh Attribute: R/WO, RO

Default Value: 30008010h Size: 32-bit

7.1.10 V1CTL—Virtual Channel 1 Resource Control Register

Offset Address: 0020–0023h Attribute: R/W, RO

Default Value: 00000000h Size: 32-bit

Bit Description

31:24 Port Arbitration Table Offset (AT) — RO. Indicates the location of the port arbitration

table in the root complex. A value of 3h indicates the table is at offset 30h.

23 Reserved

22:16 Maximum Time Slots (MTS) — R/WO. This value is updated by platform BIOS

based upon the determination of the number of time slots available in the platform.

15 Reject Snoop Transactions (RTS) — RO. All snoopable transactions on VC1 are

rejected. This VC is for isochronous transfers only.

14 Advanced Packet Switching (APS) — RO. This VC is capable of all transactions, not

just advanced packet switching transactions.

13:8 Reserved

7:0 Port Arbitration Capability (PAC) — RO. Indicates the port arbitration capability is

time-based WRR of 128 phases.

Bit Description

31 Virtual Channel Enable (EN) — R/W. Enables the VC when set. Disables the VC

when cleared.

30:27 Reserved

26:24 Virtual Channel Identifier (ID) — R/W. Indicates the ID to use for this virtual

channel.

23:20 Reserved

19:17 Port Arbitration Select (PAS) — R/W. Indicates which port table is being

programmed. The only permissible value of this field is 4h for the time-based WRR

entries.

16 Load Port Arbitration Table (LAT) — RO/W. When set, the port arbitration table

loaded based upon the PAS field in this register. This bit always returns 0 when read.

15:8 Reserved

7:1 Transaction Class / Virtual Channel Map (TVM) — R/W. Indicates which

transaction classes are mapped to this virtua l channel. When a bit is set, this

transaction class is mapped to the virtual channel.

0 Reserved

Chipset Configuration Registers

272 Intel® ICH8 Family Datasheet

7.1.11 V1STS—Virtual Channel 1 Resource Status Register

Offset Address: 0026–0027h Attribute: RO

Default Value: 0000h Size: 16-bit

7.1.12 PAT—Port Arbitration Table

Offset Address: 0030–006Fh Attribute:

Default Value: Size: 64-Byte

This is a 64-byte register that contains the arbitration table to be loaded into the port

arbitration table. Every 4-bits contains an entry for one of the downstream PCI-Express

ports or a 0h to indicate idle. The ports are mapped as follows:

• Port 1: Value used is 1h.

• Port 2: Value used is 2h.

• Port 3: Value used is 3h

• Port 4: Value used is 4h

• Port 5: Value used is 5h

• Port 6: Value used is 6h

•Intel

® High Definition Audio: Value used is Fh

This table is copied to an internal structure used during port arbitration when

V1CTL.PAS is set to 04h, and V1CTL.LAT is set to 1.

7.1.13 CIR1—Chipset Initialization Register 1

Offset Address: 0088–008Bh Attribute: R/WO, RO

Default Value: 00000000h Size: 32-bit

Bit Description

15:02 Reserved

1VC Negotiation Pending (NP ) — RO. When set, indicates the virtual channel is still

being negotiated with ingress ports.

Port Arbitration Tables Status (ATS) — RO. Indicates the coherency status of the

port arbitration table. This bit is set when LAT (offset 000Ch:bit 0) is written with

value 1 and P AS (offset 0014h:bi ts19:17) has value of 4h. This bit is cleared after the

table has been updated.

Bit Description

31:21 Reserved

20 CIR1 Field 3 — R/WO. BIOS must set this bit.

19:16 Reserved

15 CIR1 Field 2 — R/WO. BIOS must set this bit.

14:13 Reserved

12 CIR1 Field 1— R/WO. BIOS must set this bit.

11:0 Reserved

Intel® ICH8 Family Datasheet 273

Chipset Configuration Registers

7.1.14 RCTCL—Root Complex Topology Capabilities List Register

Offset Address: 0100–0103h Attribute: RO

Default Value: 1A010005h Size: 3 2-bit

7.1.15 ESD—Element Self Description Register

Offset Address: 0104–0107h Attribute: R/WO, RO

Default Value: 00000602h Size: 32-bit

7.1.16 ULD—Upstream Link Descriptor Register

Offset Address: 0110–0113h Attribute: R/WO, RO

Default Value: 00000001h Size: 32-bit

Bit Description

31:20 Next Capability (NEXT) — RO. Indicates the next item in the list.

19:16 Capability Version (CV) — RO. Indicates the version of the capabi lity structure.

15:0 Capability ID (CID) — RO . Indicates this is a PCI Express* link capability section of an

RCRB.

Bit Description

31:24 Port Number (PN) — RO. A value of 0 to indicate the egress port for the Intel® ICH.

23:16 Component ID (CID) — R/WO. This field indicates the component ID assigned to

this element by software. This is written once by platform BIOS and is locked until a

platform reset.

15:8 Number of Link Entries (NLE) — RO. This field indicates that one link entry

(corresponding to DMI), 6 root port entries (for the downstream ports), and the

Intel® High Definition Audio device are described by this RCRB.

7:4 Reserved

3:0 Element Type (ET) — RO. This field indic ates that the el ement t ype is a root complex

internal link.

Bit Description

31:24 Target Port Number (PN) — R/WO. This field is programmed by platform BIOS to

match the port n umber of the (G)MCH RCRB that is attached to this RCRB.

23:16 Target Component ID (TCID) — R/WO . This field is programmed b y platform BIOS

to match the component ID of the (G)MCH RCRB that is attached to this RCRB.

15:2 Reserved

1Link Type (LT) — RO. This field indicates that the link points to the (G)MCH RCRB.

0Link Valid (LV) — RO. This field indicates that the link entry is valid.

Chipset Configuration Registers

274 Intel® ICH8 Family Datasheet

7.1.17 ULBA—Upstream Link Base Address Register

Offset Address: 0118–011Fh Attribute: R/WO

Default Value: 0000000000000000h Size: 64-bit

7.1.18 RP1D—Root Port 1 Descriptor Register

Offset Address: 0120–0123h Attribute: R/WO, RO

Default Value: 01xx0002h Size: 32-bit

7.1.19 RP1BA—Root Port 1 Base Address Register

Offset Address: 0128–012Fh Attribute: RO

Default Value: 00000000000E0000h Size: 64-bit

Bit Description

63:32 Base Address Upper (BAU) — R/WO. This field is progr ammed by platform BIOS to

match the upper 32 -bits of base address of the (G)MCH RCRB th at is attached to t his

RCRB.

31:0 Base Address Lower (BAL) — R/WO. This field is programmed by platform BIOS to

match the lower 32-bit s of base address of the (G)MCH RCRB that is att ached to this

RCRB.

Bit Description

31:24 Target Port Number (PN) — RO. Indicates the target port number is 1h (root port

#1).

23:16 Target Component ID (TCID) — R/WO. This field returns the v alue of the ESD.CID

(offset 0104h, bits 23:16) fie ld progr ammed by platfo rm BIOS, since the root port is

in the same compone nt as the RCRB.

15:2 Reserved

1 Link Type (LT) — RO. Indicates that the link points to a root port.

0Link Valid (LV) — RO. When FD.PE1D (offset 3418h, bit 16) is set, this link is not

valid (returns 0). When FD.PE1D is cleared, this link is valid (returns 1).

Bit Description

63:32 Reserved

31:28 Reserved

27:20 Bus Number (BN) — RO. Indicates the root port is on bus #0.

19:15 Device Number (DN) — RO. Indicates the root port is on device #28.

14:12 Function Number (FN) — RO. Indicates the root port is on function #0.

11:0 Reserved

Intel® ICH8 Family Datasheet 275

Chipset Configuration Registers

7.1.20 RP2D—Root Port 2 Descriptor Register

Offset Address: 0130–0133h Attribute: R/WO, RO

Default Value: 02xx0002h Size: 32-bit

7.1.21 RP2BA—Root Port 2 Base Address Register

Offset Address: 0138–013Fh Attribute: RO

Default Value: 00000000000E1000h Size: 64-bit

7.1.22 RP3D—Root Port 3 Descriptor Register

Offset Address: 0140–0143h Attribute: R/WO, RO

Default Value: 03xx0002h Size: 32-bit

Bit Description

31:24 Target Port Number (PN) — RO. Indicates the target port number is 2h (root port

#2).

23:16 Target Compo nent ID (TCID ) — R/WO. This field returns the value of the ESD .CID

(offset 0104h, bi ts 23 :16 ) field progr amm ed by platform BIOS, since the root port is

in the same component as the RCRB.

15:2 Reserved

1 Link Type (LT) — RO. Indicates that the link points to a root port.

Link Valid (LV) — RO. When RPC.PC (offset 0224h, bits 1:0) is ‘01’, ‘10’, or ‘11’, or

FD.P E2D (offset 3418h, bit 17) i s set, the link for this root port is not val id (return 0).

When RPC.PC is ‘00’ and FD .PE2D is cleared, the link for this root port is v alid (return

1).

Bit Description

63:32 Reserved

31:28 Reserved

27:20 Bus Number (BN) — RO. Indicates the root port is on bus #0.

19:15 Device Number (DN) — RO. Indicates the root port is on device #28.

14:12 Function Number (FN) — RO. Indicates the root port is on function #1.

11:0 Reserved

Bit Description

31:24 Target Port Number (PN) — RO. Indicates the target port number is 3h (root port

#3).

23:16 Target Compo nent ID (TCID ) — R/WO. This field returns the value of the ESD .CID

(offset 0104h, bi ts 23 :16 ) field progr amm ed by platform BIOS, since the root port is

in the same component as the RCRB.

15:2 Reserved

1 Link Type (LT) — RO. Indicates that the link points to a root port.

Link Valid (LV) — RO. When RPC.PC (offset 0224h, bits 1:0) is ‘11’, or FD.PE3D

(offset 3418h, bit 18) is set, the link for this root port is not valid (return 0). When

RPC.PC is ‘00’, ‘01’, or “10’, and FD.PE3D is cleared, the link for this root port is valid

(return 1).

Chipset Configuration Registers

276 Intel® ICH8 Family Datasheet

7.1.23 RP3BA—Root Port 3 Base Address Register

Offset Address: 0148–014Fh Attribute: RO

Default Value: 00000000000E2000h Size: 64-bit

7.1.24 RP4D—Root Port 4 Descriptor Register

Offset Address: 0150–0153h Attribute: R/WO, RO

Default Value: 04xx0002h Size: 32-bit

7.1.25 RP4BA—Root Port 4 Base Address Register

Offset Address: 0158–015Fh Attribute: RO

Default Value: 00000000000E3000h Size: 64-bit

Bit Description

63:32 Reserved

31:28 Reserved

27:20 Bus Number (BN) — RO. Indicates the root port is on bus #0.

19:15 Device Number (DN) — RO. Indicates the root port is on device #28.

14:12 Function Number (FN) — RO. Indicates the root port is on function #2.

11:0 Reserved

Bit Description

31:24 Target Port Number (PN) — RO. Indicates the target port number is 4h (root port

#4).

23:16 Target Component ID (TCID) — R/WO. This field returns the v alue of the ESD.CID

(offset 0104h, bits 23:16) fie ld progr ammed by platfo rm BIOS, since the root port is

in the same compone nt as the RCRB.

15:2 Reserved

1 Link Type (LT) — RO. Indicates that the link points to a root port.

Link Valid (LV) — RO. When RPC.PC (offset 0224h, bits 1:0) is ‘10’ or ‘11’, or

FD. PE4D (offset 3418h, bit 19) is set, the link for this root port is no t valid (return 0).

When RPC.PC is ‘00’ or ‘01’ and FD.PE4D is cleared, the link for this root port is v ali d

(return 1).

Bit Description

63:32 Reserved

31:28 Reserved

27:20 Bus Number (BN) — RO. Indicates the root port is on bus #0.

19:15 Device Number (DN) — RO. Indicates the root port is on device #28.

14:12 Function Number (FN) — RO. Indicates the root port is on function #3.

11:0 Reserved

Intel® ICH8 Family Datasheet 277

Chipset Configuration Registers

7.1.26 HDD—Intel® High Definition Audio Descriptor Register

Offset Address: 0160–0163h Attribute: R/WO, RO

Default Value: 15xx0002h Size: 32-bit

7.1.27 HDBA—Intel® High Definition Audio Base Address Register

Offset Address: 0168–016Fh Attribute: RO

Default Value: 00000000000D8000h Size: 64-bit

7.1.28 RP5D—Root Port 5 Descriptor Register

Offset Address: 0170–0173h Attribute: R/WO, RO

Default Value: 05xx0002h Size: 32-bit

Bit Description

31:24 Target P ort Number (PN) — RO . Indicates the target port number is 15h (Intel® High

Definition Audio).

23:16 Target Compo nent ID (TCID ) — R/WO. This field returns the value of the ESD .CID

(offset 0104h, bi ts 23 :16 ) field progr amm ed by platform BIOS, since the root port is

in the same component as the RCRB.

15:2 Reserved

1 Link Type (LT) — RO. Indicates that the link points to a root port.

0Link Valid (LV) — RO. When FD.ZD (offset 3418h, bit 4) is set, the link to Intel High

Definition Audio is not valid (return 0). When FD.ZD is cleared, the link to Intel High

Definition Audio is valid (return 1).

Bit Description

63:32 Reserved

31:28 Reserved

27:20 Bus Number (BN) — RO. Indicates the root port is on bus #0.

19:15 Device Number (DN) — RO. Indicates the root port is on device #27.

14:12 Function Number (FN) — RO. Indicates the root port is on function #0.

11:0 Reserved

Bit Description

31:24 Target Port Number (PN) — RO. Indicates the target port number is 5h (root port

#5).

23:16 Target Compo nent ID (TCID ) — R/WO. This field returns the value of the ESD .CID

(offset 0104h, bi ts 23 :16 ) field progr amm ed by platform BIOS, since the root port is

in the same component as the RCRB.

15:2 Reserved

1 Link Type (LT) — RO. Indicates that the link points to a root port.

0Link Valid (LV) — RO. When FD.PE5D (offset 3418h, bit 20) is set, the link for this

root port is not valid (return 0). When FD.PE5D is cleared, the link for this root port is

valid (return 1).

Chipset Configuration Registers

278 Intel® ICH8 Family Datasheet

7.1.29 RP5BA—Root Port 5 Base Address Register

Offset Address: 0178–017Fh Attribute: RO

Default Value: 00000000000E4000h Size: 64-bit

7.1.30 RP6D—Root Port 6 Descriptor Register

Offset Address: 0180–0183h Attribute: R/WO, RO

Default Value: 06xx0002h Size: 32-bit

7.1.31 RP6BA—Root Port 6 Base Address Register

Offset Address: 0188–018Fh Attribute: RO

Default Value: 00000000000E5000h Size: 64-bit

Bit Description

63:32 Reserved

31:28 Reserved

27:20 Bus Number (BN) — RO. Indicates the root port is on bus #0.

19:15 Device Number (DN) — RO. Indicates the root port is on device #28.

14:12 Function Number (FN) — RO. Indicates the root port is on function #4.

11:0 Reserved

Bit Description

31:24 Target Port Number (PN) — RO. Indicates the target port number is 6h (root port

#6).

23:16 Target Component ID (TCID) — R/WO. This field returns the v alue of the ESD.CID

(offset 0104h, bits 23:16) fie ld progr ammed by platfo rm BIOS, since the root port is

in the same compone nt as the RCRB.

15:2 Reserved

1 Link Type (LT) — RO. Indicates that the link points to a root port.

0Link Valid (LV) — RO. When RPC.PC2 (offset 0224h, bits 1:0) is ‘01’ or FD.PE6D

(offset 3418h, bit 21) is set, the link for this root port is not valid (return 0). When

RPC.PC is ‘00’ and FD.PE6D is cleared, the link for this root port is valid (return 1).

Bit Description

63:32 Reserved

31:28 Reserved

27:20 Bus Number (BN) — RO. Indicates the root port is on bus 0.

19:15 Device Number (DN) — RO. Indicates the root port is on device 28.

14:12 Function Number (FN) — RO. Indicates the root port is on function 5.

11:0 Reserved

Intel® ICH8 Family Datasheet 279

Chipset Configuration Registers

7.1.32 ILCL—Internal Link Capabilities List Register

Offset Address: 01A0–01A3h Attribute: RO

Default Value: 00010006h Size: 32-bit

7.1.33 LCAP—Link Capabilities Register

Offset Address: 01A4–01A7h Attribute: RO/ R/WO

Default Value: 00012441h Size: 32-bit

Bit Description

31:20 Next Capability Offset (NEXT) — RO. Indicates this is the last item in the list.

19:16 Capability Version (CV) — RO. Indicates the version of the capabi lity structure.

15:0 Capability ID (CID) — RO. Indicates this is capability for DMI.

Bit Description

31:18 Reserved

17:15 L1 Exit Latency (EL1) — L1 not supported on DMI.

14:12 L0s Exit Latency (EL0) — R/WO . This field indicates that exit latency is 128 ns to less

than 256 ns.

11:10

(Desktop

Only) Reserved

11:10

(Mobile

Only)

Active State Link PM Support (APMS) — R/WO. Indicates that L0s is supported on

DMI.

9:4 Maximum Link Width (MLW) — Indicates the maximum link width is 4 ports.

3:0 Maximum Link Speed (MLS) — Indicates the link speed is 2.5 Gb/s.

Chipset Configuration Registers

280 Intel® ICH8 Family Datasheet

7.1.34 LCTL—Link Control Register

Offset Address: 01A8–01A9h Attribute: R/W

Default Value: 0000h Size: 16-bit

7.1.35 LSTS—Link Status Register

Offset Address: 01AA–01ABh Attribute: RO

Default Value: 0041h Size: 16-bit

7.1.36 CIR2 — Chipset Initialization Register 2

Offset Address: 01F4–01F7h Attribute: R/W

Default Value: 00000000h Size: 32-bit

Bit Description

15:8 Reserved

7Extended Synch (ES) — R/W. When set, forces extended transmission of FTS

ordered sets when exiting L0s prior to entering L0.

6:2 Reserved

1:0

(Desktop

Only) Reserved

1:0

(Mobile

Only)

Active State Link PM Control (APMC) — R/W. Indicates whether DMI should

enter L0s.

00 = Disabled

01 = L0s entry enable d

10 = Reserved

11 = Reserved

Bit Description

15:10 Reserved

9:4 Negotiated Link Width (NLW) — RO. Negotiated link width is x4 (000100b).

ICH8M may also indicate x2 (000010b), depending on (G)MCH configuration.

3:0 Link Speed (LS) — RO. Link is 2.5 G b /s.

Bit Description

31:0 CIR2 Field 1 — R/W. BIOS shall program to 86000040h

Intel® ICH8 Family Datasheet 281

Chipset Configuration Registers

7.1.37 CIR3 — Chipset Initialization Register 3

Offset Address: 01FC–01FDh Attribute: R/W, RO

Default Value: 0000h Size: 16-bit

7.1.38 CIR4 — Chipset Initialization Register 4

Offset Address: 0200–0201h Attribute: R/W, RO

Default Value: 0000h Size: 16-bit

7.1.39 BCR — Backbone Configuration Register

Offset Address: 0220–0223h Attribute: R/W

Default Value: 00000000h Size: 32-bit

Bit Description

15:11 Reserved

10:8 CIR3 Field 3 — R/W. BIOS must program this field to 110b.

7:4 Reserved

3CIR3 Field 2 — R/W. BIOS must set this bit.

2 Reserved

1:0 CIR3 Field 1 — R/W. BIOS must program this field to 11b.

Bit Description

15:14 Reserved

13:8 CIR4 Field 2 — R/W. BIOS must program this field to 10 0000b

7:6 Reserved

5:0 CIR4 Field 1 — R/W. BIOS must program this field to 00 1000b.

Bit Description

31:7 Reserved

6BCR Field 2 — R/W. BIOS must set this bit.

5:3 Reserved

2:0 BCR Field 1 — R/W. BIOS program this field to 101b

Chipset Configuration Registers

282 Intel® ICH8 Family Datasheet

7.1.40 RPC—Root Port Configuration Register

Offset Address: 0224–0227h Attribute: R/W, RO

Default Value: 0000000yh (y = 00xxb) Size: 32-bit

7.1.41 DMIC—DMI Control Register

Offset Address: 0234–0237h Attribute: R/W, RO

Default Value: 00000000h Size: 32-bit

Bit Description

31:8 Reserved

High Priority Port Enable (HPE ) — R/W.

0 = The high priority path is not enabled.

1 = The port selected by the HPP field in this register is enabled for high priority. It

will be arbitrated above all other VC0 (including integrated VC0) devices.

6:4

High Priority Port (HPP) — R/W. This controls which port is enabled for high

priority when the HPE bit in this register is set.

111 = Reserved

110 = Reserved

101 = Port 6

100 = Port 5

101 = Port 4

010 = Port 3

001 = Port 2

000 = Port 1

3 Reserved

Port Configuration2 (PC2) — RO. This contr ols how the PCI bridges are organized

in various modes of operation for Ports 5 and 6.

1 = Reserved

0 = 2 x1s, Port 5 (x1), Port 6 (x1)

This bit is in the resume well and is only reset by RSMRST#.

1:0

Port Configuration (PC) — RO. This field controls how the PCI bridges are

organized in v a rious mo des of ope r ation for P or ts 1–4. For the following mappings, if

a port is not shown, it is considered a x1 port with no connection.

These bits represent the strap values of HDA_SDOUT (bit 1) and HDA_SYNC (bit 0)

when TP[3] is not pulled low at the rising edge of PWROK.

11 = 1 x4, Port 1 (x4)

10 = Reserved

01 = 1 x2 & 2 x1s, Port 1 (x2), Port 3 (x1), Port 4 (x1)

00 = 4 x1s, Port 1 (x1), Port 2 (x1), Port 3 (x1), Port 4 (x1)

These bits live in the resume well and are only reset by RSMRST#.

Bit Description

31:2 Reserved

1:0 DMI Clock Gate Enable (DMICGEN) — R/W. BIOS must program this field to 00b

(desktop) or 11b (mobile only)

Intel® ICH8 Family Datasheet 283

Chipset Configuration Registers

7.1.42 RPFN—Root Port Function Number for PCI Express* Root

Ports

Offset Address: 0238–1E03h Attribute: R/WO, RO

Default Value: 00543210h Size: 32-bit

For the PCI Express root ports, the assignment of a function number to a root port is

not fixed. BIOS may re-assign the function numbers on a port by port basis. This

capability will allow BIOS to disable/hide any root port and have still have functions 0

thru N-1 where N is the total number of enabled root ports.

Port numbers will remain fixed to a physical root port.

The existing root port Function Disable registers operate on physical ports (not

functions).

Port Configuration (1x4, 4x1, etc.) is not affected by the logical function number

assignment and is associated with physical ports.

Bit Description

31:23 Reserved

22:20 Root Port 6 Function Number (RP6FN) — R/WO. These bits set the function

number for PCI Express Root Port 6. This root port function number must be a

unique value from the other root port function numbers

19 Reserved

18:16 Root Port 5 Function Number (RP5FN) — R/WO. These bits set the function

number for PCI Express Root Port 5. This root port function number must be a

unique value from the other root port function numbers

15 Reserved

14:12 Root Port 4 Function Number (RP4FN) — R/WO. These bits set the function

number for PCI Express Root Port 4. This root port function number must be a

unique value from the other root port function numbers

11 Reserved

10:8 Root Port 3 Function Number (RP3FN) — R/WO. These bits set the function

number for PCI Express Root Port 3. This root port function number must be a

unique value from the other root port function numbers

7 Reserved

6:4 Root Port 2 Function Number (RP2FN) — R/WO. These bits set the function

number for PCI Express Root Port 2. This root port function number must be a

unique value from the other root port function numbers

3 Reserved

2:0 Root Port 1 Function Number (RP1FN) — R/WO. These bits set the function

number for PCI Express Root Port 1. This root port function number must be a

unique value from the other root port function numbers

Chipset Configuration Registers

284 Intel® ICH8 Family Datasheet

7.1.43 CIR5—Chipset Initialization Register 5

Offset Address: 1D40h–1D47h Attrib ute: R/W, R/WL

Default Value: 0000000000000000h Size: 64-bit

7.1.44 TRSR—Trap Status Register

Offset Address: 1E00–1E03h Attribute: R/WC, RO

Default Value: 00000000h Size: 32-bit

7.1.45 TRCR—Trapped Cycle Register

Offset Address: 1E10–1E17h Attribute: RO

Default Value: 0000000000000000h Size: 64-bit

This register saves information about th e I/O Cycle that was tr apped and generated the

SMI# for software to read.

Bit Description

63:1 Reserved

0CIR5 Field 1 — R/W. BIOS must program this field to 1b

Bit Description

31:4 Reserved

3:0

Cycle Trap SMI# Status (CTSS ) — R/WC. These bits are set by hardware when the

corresponding Cycle Trap register is enabled and a matching cycle is received (and

trapped). These bits are OR’ed together to create a single status bit in the Power

Management register space.

Note that the SMI# and trapping must be enabled in order to set these bits.

These bits are set before the completion is generated for the trapped cycle, thereby

assuring that th e processor can enter the SMI# handler when the instruction

completes. Each status bit is cleared by writing a 1 to the corresponding bit location

in this register.

Bit Description

63:25 Reserved

24 Read/Write# (RWI) — RO.

0 = Trapped cycle was a write cycle.

1 = Trapped cycle was a read cycle.

23:20 Reserved

19:16 Active-high Byte Enables (AHBE) — RO. This is the dword-aligned byte enables

associated with the trapped cycle. A 1 in any bit location indicates that the

corresponding byte is enabled in the cycle.

15:2 Trapped I/O Address (TIOA) — RO. This is the dword-aligned address of the

trapped cycle.

1:0 Reserved

Intel® ICH8 Family Datasheet 285

Chipset Configuration Registers

7.1.46 TWDR—Trapped Write Data Register

Offset Address: 1E18–1E1Fh Attribute: RO

Default Value: 0000000000000000h Size: 64-bit

This register saves the data from I/O write cycles that are trapped for software to read.

7.1.47 IOTRn — I/O Trap Register (0–3)

Offset Address: 1E80–1E87h Register 0 Attribute: R/W, RO

1E88–1E8Fh Register 1

1E90–1E97h Register 2

1E98–1E9Fh Register 3

Default Value: 0000000000000000h Size: 64-bit

These registers are used to specify the set of I/O cycles to be trapped and to enable

this functionality.

Bit Description

63:32 Reserved

31:0 Trapped I/O Data (TIOD) — RO. Dword of I/O write data. This field is undefined

after trapping a read cycle.

Bit Description

63:50 Reserved

49 Read/Write Mask (RWM) — R/W.

0 = The cycle must match the type specified in bit 48.

1 = Trapping logic will operate on both read and write cycles.

Read/Write# (RWIO) — R/W.

0 = Write

1 = Read

NOTE: The value in this field does not matter if bit 49 is set.

47:40 Reserved

39:36 Byte Enable Mask (BEM) — R/W. A 1 in any bit position indicates that any value in

the corresponding byte enable bit in a received cycle will be treated as a match. The

corresponding bit in the Byte Enables field, below, is ignored.

35:32 Byte Enables (TBE) — R/W. Active-high dword-aligned byte enables.

31:24 Reserved

23:18

Address[7:2] Mask (ADMA) — R/W. A 1 in any bit position indicates that any value

in the corresponding address bit in a received cycle will be treated as a match. The

corresponding bit in the Address field, below, is ignored. The mask is only provided

for the lower 6 bits of the dword address, allowing for traps on address ranges up to

256 bytes in size.

17:16 Reserved

15:2 I/O Address[15:2] (IOAD ) — R/W. dword-aligned address

1 Reserved

0Trap and SMI# Enable (TRSE) — R/W.

0 = Trapping and SMI# logic disabled.

1 = The trapping logic specified in this register is enabled.

Chipset Configuration Registers

286 Intel® ICH8 Family Datasheet

7.1.48 DMC—DMI Miscellaneous Control Register (Mobile Only)

Offset Address: 2010–2013h Attribute: R/W

Default Value: NA Size: 32-bit

7.1.49 CIR6—Chipset Initialization Register 6 (Mobile Only)

Offset Address: 2024–2027h Attribute: R/W, RO

Default Value: 0B2030xxh Size: 32-bit

7.1.50 CIR7—Chipset Initialization Register 7

Offset Address: 2034–2037h Attribute: R/W

Default Value: B2B477CCh Size: 32-bit

Bit Description

31:2 Reserved

DMI Misc. Control Field 1 — R/W. BIOS shall always program this field as per the

BIOS Specification.

0 = Disable DMI Power Savings.

1 = Enable DM I Power Savin gs.

0 Reserved

Bit Description

31:24 Reserved

23:21 CIR6 Field 2 — R/W. (Mobile Only) BIOS must program this field to 011b.

20:8 Reserved

7CIR6 Field 1 — R/W. BIOS must clear this bit.

6:0 Reserved

Bit Description

31:20 Reserved

19:16 CIR7 Field 1 — R/W. BIOS must program this field to 0101b.

15:0 Reserved

Intel® ICH8 Family Datasheet 287

Chipset Configuration Registers

7.1.51 TCTL—TCO Configuration Register

Offset Address: 3000–3000h Attribute: R/W

Default Value: 00h Size: 8-bit

Bit Description

7TCO IRQ Enable (IE) — R/W.

0 = TCO IRQ is disabled.

1 = TCO IRQ is enabled, as selected by the TCO_IRQ_SEL field.

6:3 Reserved

2:0

TCO IRQ Select (IS) — R/W. Specifies on which IRQ the T CO wil l inte rnall y appear.

If not using the APIC, the TCO interrupt must be routed to IRQ9-11, and that

interrupt is not sharable with the SERIRQ stream, but is shareable with other PCI

interrupts. If using the APIC, the TCO interrupt can also be mapped to IRQ20-23, and

can be shared with other interrupt.

000 = IRQ 9

001 = IRQ 10

010 = IRQ 11

011 = Reserved

100 = IRQ 20 (only if APIC enabled)

101 = IRQ 21 (only if APIC enabled)

110 = IRQ 22 (only if APIC enabled)

111 = IRQ 23 (only if APIC enabled)

When setting the these bits, the IE bit should be cleared to prevent glitching.

When the interrupt is mapped to APIC interrupts 9, 10 or 11, the APIC should be

programmed for active-high reception. When the interrupt is mapped to APIC

interrupts 20 through 23, the APIC should be programmed for active-low reception.

Chipset Configuration Registers

288 Intel® ICH8 Family Datasheet

7.1.52 D31IP—Device 31 Interrupt Pin Register

Offset Address: 3100–3103h Attribute: R/W, RO

Default Value: 03243210h Size: 32-bit

Bit Description

31:16 Reserved

27:24

Thermal Throttle Pin (TTIP) — R/W. This field indicates which pin the Thermal

Throttle controller drives as its interrupt.

0h = No interrupt

1h = INTA#

2h = INTB# (Default)

3h = INTC#

4h = INTD#

5h–Fh = Reserved

23:20

SATA Pin 2 (SIP2) — R/W. This field indicates which pin the SATA controller 2

drives as its interrupt.

0h = No interrupt.

1h = INTA#

2h = INTB# (Default)

3h = INTC#

4h = INTD#

5h–Fh = Reserved

19:16 Reserved

15:12

SM Bus Pin (SMIP) — R/W. This field indicates which pin the SMBus controller

drives as its interrupt.

0h = No interrupt

1h = INTA#

2h = INTB# (Default)

3h = INTC#

4h = INTD#

5h–Fh = Reserved

11:8

SATA Pin (SIP) — R/W. This field indicates which pin the SATA controller drives as

its interrupt.

0h = No interrupt

1h = INTA#

2h = INTB# (Default)

3h = INTC#

4h = INTD#

5h–Fh = Reserved

7:4

PATA Pin (SMI P) — R/W. This field indicates which pin the PAT A controller drives as

its interrupt.

0h = No interrupt

1h = INTA# (Default)

2h = INTB#

3h = INTC#

4h = INTD#

5h–Fh = Reserved

3:0 LPC Bridge Pin (PIP) — RO. Currently, the LPC bridge does not generate an interrupt,

so this field is read-only and 0.

Intel® ICH8 Family Datasheet 289

Chipset Configuration Registers

7.1.53 D30IP—Device 30 Interrupt Pin Regi ster

Offset Address: 3104–3107h Attribute: R/W, RO

Default Value: 00000000h Size: 32-bit

7.1.54 D29IP—Device 29 Interrupt Pin Regi ster

Offset Address: 3108–310Bh Attribute: R/W

Default Value: 10004321h Size: 32-bit

Bit Description

31:4 Reserved

3:0 PCI Bridge Pin (LIP) — RO. Currently, the PCI bridge does not generate an interrupt,

so this field is read-only and 0.

Bit Description

31:28

EHCI Pin (EIP) — R/W. Th is field indicate s which pin the EHCI controller drives as

its interrupt.

0h = No interrupt

1h = INTA# (Default)

2h = INTB#

3h = INTC#

4h = INTD#

5h–7h = Reserved

27:12 Reserved

11:8

UHCI #2 Pin (U2P) — R/W. This field indicates which pin the UHCI controller #2

(ports 4 and 5) drives as its interrupt.

0h = No interrupt

1h = INTA#

2h = INTB#

3h = INTC# (Default)

4h = INTD#

5h–7h = Reserved

7:4

UHCI #1 Pin (U1P) — R/W. This field indicates which pin the UHCI controller #1

(ports 2 and 3) drives as its interrupt.

0h = No interrupt

1h = INTA#

2h = INTB# (Default)

3h = INTC#

4h = INTD#

5h–7h = Reserved

3:0

UHCI #0 Pin (U0P) — R/W. This field indicates which pin the UHCI controller #0

(ports 0 and 1) drives as its interrupt.

0h = No interrupt

1h = INTA# (Default)

2h = INTB#

3h = INTC#

4h = INTD#

5h–7h = Reserved

Chipset Configuration Registers

290 Intel® ICH8 Family Datasheet

7.1.55 D28IP—Device 28 Interrupt Pin Register

Offset Address: 310C–310Fh Attribute: R/W

Default Value: 00214321h Size: 32-bit

Bit Description

31:16 Reserved

23:20

PCI Express* #6 Pi n (P 6IP) — R/W. This field indicates which pin the PCI

Express* port #6 drives as its interrupt.

0h = No interrupt

1h = INTA#

2h = INTB# (Default)

3h = INTC#

4h = INTD#

5h–7h = Reserved

19:16

PCI Express #5 Pin (P5 I P ) — R/W. This field indicates which pin the PCI Express

port #5 drives as its interrupt.

0h = No interrupt

1h = INTA# (Default)

2h = INTB#

3h = INTC#

4h = INTD#

5h–7h = Reserved

15:12

PCI Express #4 Pin ( P4IP) — R/W. This field indicates which pi n th e PC I Ex pr ess*

port #4 drives as its interrupt.

0h = No interrupt

1h = INTA#

2h = INTB#

3h = INTC#

4h = INTD# (Default)

5h–7h = Reserved

11:8

PCI Express #3 Pin (P3 I P ) — R/W. This field indicates which pin the PCI Express

port #3 drives as its interrupt.

0h = No interrupt

1h = INTA#

2h = INTB#

3h = INTC# (Default)

4h = INTD#

5h–7h = Reserved

7:4

PCI Express #2 Pin (P2 I P ) — R/W. This field indicates which pin the PCI Express

port #2 drives as its interrupt.

0h = No interrupt

1h = INTA#

2h = INTB# (Default)

3h = INTC#

4h = INTD#

5h–7h = Reserved

3:0

PCI Express #1 Pin (P1 I P ) — R/W. This field indicates which pin the PCI Express

port #1 drives as its interrupt.

0h = No interrupt

1h = INTA# (Default)

2h = INTB#

3h = INTC#

4h = INTD#

5h–7h = Reserved

Intel® ICH8 Family Datasheet 291

Chipset Configuration Registers

7.1.56 D27IP—Device 27 Interrupt Pin Regi ster

Offset Address: 3110–3113h Attribute: R/W

Default Value: 00000001h Size: 32-bit

7.1.57 D26IP—Device 26 Interrupt Pin Regi ster

Offset Address: 3114–3117h Attribute: R/W, RO

Default Value: 30000021h Size: 32-bit

Bit Description

31:4 Reserved

3:0

Intel® High Definition Audio Pin (ZIP) — R/W. This field indicates which pin the

Intel High Definition Audio controller drives as its interrupt.

0h = No interrupt

1h = INTA# (Default)

2h = INTB#

3h = INTC#

4h = INTD#

5h–Fh = Reserved

Bit Description

31:28

EHCI #2 Pin (E2IP): This field indicates which pin the EH CI cont roller #2 driv es as

its interrupt:

0h = No Interrupt

1h = INTA#

2h = INTB#

3h = INTC# (Default)

4h = INTD#

5h–Fh = Reserved

27:8 Reserved

7:4

UHCI #5 Pin (U5P): This field applies to UHCI controller #5 (ports 8 & 9)

0h = No Interrupt

1h = INTA#

2h = INTB# (Default)

3h = INTC#

4h = INTD#

5h–Fh = Reserved

3:0

UHCI #4 Pin (U4P): This field applies to UHCI controller #4 (ports 6 and 7)

0h = No Interrupt

1h = INTA# (Default)

2h = INTB#

3h = INTC#

4h = INTD#

5h–Fh = Reserved

Chipset Configuration Registers

292 Intel® ICH8 Family Datasheet

7.1.58 D25IP—Device 25 Interrupt Pin Register

Offset Address: 3118–3121h Attribute: RO, R/W

Default Value: 00000001h Size: 32-bit

7.1.59 D31IR—Device 31 Int errupt Route Register

Offset Address: 3140–3141h Attribute: R/W

Default Value: 3210h Size: 16-bit

Bit Description

31:4 Reserved

3:0

IGBE LAN Pin (LIP): This field indicates which pin the internal GbE LAN controller

drives as its interrupt

0h = No Interrupt

1h = INTA# (Default)

2h = INTB#

3h = INTC#

4h = INTD#

5h–Fh = Reserved

Bit Description

15 Reserved

14:12

Interrupt D Pin Route (IDR) — R/W. This field indicates which physical pin on the

Intel® ICH8 is connected to the INTD# pin reported for device 31 functions.

0h = PIRQA#

1h = PIRQB#

2h = PIRQC#

3h = PIRQD# (Default)

4h = PIRQE#

5h = PIRQF#

6h = PIRQG#

7h = PIRQH#

11 Reserved

10:8

Interrupt C Pin Route (ICR) — R/W. This field indicates which physical pin on the

ICH8 is connected to the INTC# pin reported for device 31 functions.

0h = PIRQA#

1h = PIRQB#

2h = PIRQC# (Default)

3h = PIRQD#

4h = PIRQE#

5h = PIRQF#

6h = PIRQG#

7h = PIRQH#

7:4 Reserved

NetDetect Enable (ND E )— R/W. This register is in the R TC well instead of the SUS

well to maintain state if the SUS well power is removed in S4.

0 = Disabled

1 = GPIO14 input signal is multiplexed onto the South MLink MLCLK pin as a

NetDetect Request signal to the wireless LAN component.

Intel® ICH8 Family Datasheet 293

Chipset Configuration Registers

7.1.60 D30IR—Device 30 Interrupt Route Register

Offset Address: 3142–3143h Attribute: RO

Default Value: 0000h Size: 16-bit

7.1.61 D29IR—Device 29 Interrupt Route Register

Offset Address: 3144–3145h Attribute: R/W

Default Value: 3210h Size: 16-bit

2:0

Interrupt A Pin Route (IAR) — R/W. This field indicates which physical pin on the

ICH8 is connected to the INTA# pin reported for device 31 functions.

0h = PIRQA# (Default)

1h = PIRQB#

2h = PIRQC#

3h = PIRQD#

4h = PIRQE#

5h = PIRQF#

6h = PIRQG#

7h = PIRQH#

Bit Description

15:0 Reserved. No interrupts generated from Device 30

Bit Description

15 Reserved

14:12

Interrupt D Pin Route (IDR) — R/W. This field indicates which physical pin on the

Intel® ICH8 is connected to the INTD# pin reported for device 29 functions.

0h = PIRQA#

1h = PIRQB#

2h = PIRQC#

3h = PIRQD# (Default)

4h = PIRQE#

5h = PIRQF#

6h = PIRQG#

7h = PIRQH#

11 Reserved

10:8

Interrupt C Pin Route (ICR) — R/W. This field indicate s which physical pin on the

ICH8 is connected to the INTC# pin reported for device 29 functions.

0h = PIRQA#

1h = PIRQB#

2h = PIRQC# (Default)

3h = PIRQD#

4h = PIRQE#

5h = PIRQF#

6h = PIRQG#

7h = PIRQH#

Chipset Configuration Registers

294 Intel® ICH8 Family Datasheet

7 Reserved

6:4

Interrupt B Pin Route (IBR) — R/W. This field indicates which physical pin on the

ICH8 is connected to the INTB# pin reported for device 29 functions.

0h = PIRQA#

1h = PIRQB# (Default)

2h = PIRQC#

3h = PIRQD#

4h = PIRQE#

5h = PIRQF#

6h = PIRQG#

7h = PIRQH#

3 Reserved

2:0

Interrupt A Pin Route (IAR) — R/W. This field indicates whic h phys ical pin on the

ICH8 is connected to the INTA# pin reported for device 29 functions.

0h = PIRQA# (Default)

1h = PIRQB#

2h = PIRQC#

3h = PIRQD#

4h = PIRQE#

5h = PIRQF#

6h = PIRQG#

7h = PIRQH#

Bit Description

Intel® ICH8 Family Datasheet 295

Chipset Configuration Registers

7.1.62 D28IR—Device 28 Interrupt Route Register

Offset Address: 3146–3147h Attribute: R/W

Default Value: 3210h Size: 16-bit

Bit Description

15 Reserved

14:12

Interrupt D Pin Route (IDR) — R/W. This field indicates which physical pin on the

Intel® ICH8 is connected to the INTD# pin reported for device 28 functions.

0h = PIRQA#

1h = PIRQB#

2h = PIRQC#

3h = PIRQD# (Default)

4h = PIRQE#

5h = PIRQF#

6h = PIRQG#

7h = PIRQH#

11 Reserved

10:8

Interrupt C Pin Route (ICR) — R/W. This field indicate s which physical pin on the

ICH8 is connected to the INTC# pin reported for device 28 functions.

0h = PIRQA#

1h = PIRQB#

2h = PIRQC# (Default)

3h = PIRQD#

4h = PIRQE#

5h = PIRQF#

6h = PIRQG#

7h = PIRQH#

7 Reserved

6:4

Interrupt B Pin Route (IBR) — R/W. This field indicates which physical pin on the

ICH8 is connected to the INTB# pin reported for device 28 functions.

0h = PIRQA#

1h = PIRQB# (Default)

2h = PIRQC#

3h = PIRQD#

4h = PIRQE#

5h = PIRQF#

6h = PIRQG#

7h = PIRQH#

3 Reserved

2:0

Interrupt A Pin Route (IAR) — R/W. This field indicates which physical pin on the

ICH8 is connected to the INTA# pin reported for device 28 functions.

0h = PIRQA# (Default)

1h = PIRQB#

2h = PIRQC#

3h = PIRQD#

4h = PIRQE#

5h = PIRQF#

6h = PIRQG#

7h = PIRQH#

Chipset Configuration Registers

296 Intel® ICH8 Family Datasheet

7.1.63 D27IR—Device 27 Int errupt Route Register

Offset Address: 3148–3149h Attribute: R/W

Default Value: 3210h Size: 16-bit

Bit Description

15 Reserved

14:12

Interrupt D Pin Route (IDR) — R/W. This field indicates which physical pin on the

Intel® ICH8 is connected to the INTD# pin reported for device 27 functions.

0h = PIRQA#

1h = PIRQB#

2h = PIRQC#

3h = PIRQD# (Default)

4h = PIRQE#

5h = PIRQF#

6h = PIRQG#

7h = PIRQH#

11 Reserved

10:8

Interrupt C Pin Route (ICR) — R/W. This field indicates which physical pin on the

ICH8 is connected to the INTC# pin reported for device 27 functions.

0h = PIRQA#

1h = PIRQB#

2h = PIRQC# (Default)

3h = PIRQD#

4h = PIRQE#

5h = PIRQF#

6h = PIRQG#

7h = PIRQH#

7 Reserved

6:4

Interrupt B Pin Route (IBR) — R/W. This field indicates which physical pin on the

ICH8 is connected to the INTB# pin reported for device 27 functions.

0h = PIRQA#

1h = PIRQB# (Default)

2h = PIRQC#

3h = PIRQD#

4h = PIRQE#

5h = PIRQF#

6h = PIRQG#

7h = PIRQH#

3 Reserved

2:0

Interrupt A Pin Route (IAR) — R/W. This field indicates whic h phys ical pin on the

ICH8 is connected to the INTA# pin reported for device 27 functions.

0h = PIRQA# (Default)

1h = PIRQB#

2h = PIRQC#

3h = PIRQD#

4h = PIRQE#

5h = PIRQF#

6h = PIRQG#

7h = PIRQH#

Intel® ICH8 Family Datasheet 297

Chipset Configuration Registers

7.1.64 D26IR—Device 26 Interrupt Route Register

Offset Address: 314C–314Dh Attribute: R/W

Default Value: 3210h Size: 16-bit

Bit Description

15 Reserved

14:12

Interrupt D Pin Route (IDR): This field indicates which physical pin on the ICH8 is

connected to the INTD# pin reported for device 26 functions:

0h = PIRQA#

1h = PIRQB#

2h = PIRQC#

3h = PIRQD# (Default)

4h = PIRQE#

5h = PIRQF#

6h = PIRQG#

7h = PIRQH#

11 Reserved

10:8

Interrupt C Pin Route (ICR) — R/W. This field indicate s which physical pin on the

ICH8 is connected to the INTC# pin reported for device 26 functions.

0h = PIRQA#

1h = PIRQB#

2h = PIRQC# (Default)

3h = PIRQD#

4h = PIRQE#

5h = PIRQF#

6h = PIRQG#

7h = PIRQH#

7 Reserved

6:4

Interrupt B Pin Route (IBR) — R/W. This field indicates which physical pin on the

ICH8 is connected to the INTB# pin reported for device 26 functions.

0h = PIRQA#

1h = PIRQB# (Default)

2h = PIRQC#

3h = PIRQD#

4h = PIRQE#

5h = PIRQF#

6h = PIRQG#

7h = PIRQH#

3 Reserved

2:0

Interrupt A Pin Route (IAR) — R/W. This field indicates which physical pin on the

ICH8 is connected to the INTA# pin reported for device 26 functions.

0h = PIRQA# (Default)

1h = PIRQB#

2h = PIRQC#

3h = PIRQD#

4h = PIRQE#

5h = PIRQF#

6h = PIRQG#

7h = PIRQH#

Chipset Configuration Registers

298 Intel® ICH8 Family Datasheet

7.1.65 D25IR—Device 25 Int errupt Route Register

Offset Address: 3150–3151h Attribute: R/W

Default Value: 3210h Size: 16-bit

Bit Description

15 Reserved

14:12

Interrupt D Pin Route (IDR): This field indicates which physical pin on the ICH8 is

connected to the INTD# pin reported for device 25 functions:

0h = PIRQA#

1h = PIRQB#

2h = PIRQC#

3h = PIRQD# (Default)

4h = PIRQE#

5h = PIRQF#

6h = PIRQG#

7h = PIRQH#

11 Reserved

10:8

Interrupt C Pin Route (ICR) — R/W. This field indicates which physical pin on the

ICH8 is connected to the INTC# pin reported for device 25 functions.

0h = PIRQA#

1h = PIRQB#

2h = PIRQC# (Default)

3h = PIRQD#

4h = PIRQE#

5h = PIRQF#

6h = PIRQG#

7h = PIRQH#

7 Reserved

6:4

Interrupt B Pin Route (IBR) — R/W. This field indicates which physical pin on the

ICH8 is connected to the INTB# pin reported for device 25 functions.

0h = PIRQA#

1h = PIRQB# (Default)

2h = PIRQC#

3h = PIRQD#

4h = PIRQE#

5h = PIRQF#

6h = PIRQG#

7h = PIRQH#

3 Reserved

2:0

Interrupt A Pin Route (IAR) — R/W. This field indicates whic h phys ical pin on the

ICH8 is connected to the INTA# pin reported for device 25 functions.

0h = PIRQA# (Default)

1h = PIRQB#

2h = PIRQC#

3h = PIRQD#

4h = PIRQE#

5h = PIRQF#

6h = PIRQG#

7h = PIRQH#

Intel® ICH8 Family Datasheet 299

Chipset Configuration Registers

7.1.66 OIC—Other Interrupt Contr ol Register

Offset Address: 31FF–3 1FFh Attribute: R/W

Default Value: 00h Size: 8-bit

7.1.67 RC—RTC Configuration Register

Offset Address: 3400–3403h Attribute: R/W, R/WLO

Default Value: 00000000h Size: 32-bit

Bit Description

7:4

APIC Range Select (ASEL): These bits define address bits 15:12 for the IOxAPIC

range. The default value of 0h enables compatibility with prior ICH8 products as an

initial value. This value must not be changed unless the IOxAPIC Enable bit is

cleared.

3:2 Reserved

Coprocessor Error Enable (CEN) — R/W.

0 = FERR# will not generate IRQ13 nor IGNNE#.

1 = If FERR# is low , the Int el® ICH8 generates IRQ13 internally and holds it until an

I/O port F0h write. It will also drive IGNNE# active.

APIC Enable (AEN) — R/W.

0 = The internal IOxAPIC is disabled.

1 = Enables the internal IOxAPIC and its address decode.

NOTE: Software should read this register after modifying APIC Enable bit prior to

access to the IOxAPIC address range.

Bit Description

31:5 Reserved

Upper 128 Byte Lock (UL) — R/WLO.

0 = Bytes not locked.

1 = Bytes 38h-3Fh in the upper 128-byte bank of R T C RAM are lock ed and cannot be

accessed. Writes will be dropped and reads will not return any assured data. Bit

reset on system reset.

Lower 128 Byte Lock (LL) — R/WLO.

0 = Bytes not locked.

1 = Bytes 38h-3Fh in the lower 128-byte ba nk of RTC RAM are locked and cannot be

accessed. Writes will be dropped and reads will not return any assured data. Bit

reset on system reset.

2Upper 128 Byte Enable (UE) — R/W.

0 = Bytes locked.

1 = The upper 128-byte bank of RTC RAM can be accessed.

1:0 Reserved

Chipset Configuration Registers

300 Intel® ICH8 Family Datasheet

7.1.68 HPTC—High Precision Timer Configuration Register

Offset Address: 3404–3407h Attribute: R/W

Default Value: 00000000h Size: 32-bit

Bit Description

31:8 Reserved

Address Enable (AE) — R/W.

0 = Address disabled.

1 = The Intel® ICH8 will decode the High Precision Timer memory address range

selected by bits 1:0 below.

6:2 Reserved

1:0

Address Select (AS) — R/W. This 2-bit field sele cts 1 of 4 possible memory address

ranges for the High Precision Timer functionality. The encodings are:

00 = FED0_0000h - FED0_03FFh

01 = FED0_1000h - FED0_13FFh

10 = FED0_2000h - FED0_23FFh

11 = FED0_3000h - FED0_33FFh

Intel® ICH8 Family Datasheet 301

Chipset Configuration Registers

7.1.69 GCS—General Control and Status Register

Offset Address: 3410–3413h Attribute: R/W, R/WLO

Default Value: 00000yy0h (yy = xx0000x0b) Size: 32-bit

Bit Description

31:12 Reserved

11:10

Boot BIOS Strap s (BBS): This field determines the destination of accesses to the

BIOS memory r ange. The default v alues for these bits repres ent the strap v alues of

GNT0# (bit 11) and SPI_CS1# (bit 10) at the rising edge of PWROK.

When PCI is selected, the top 16MB of memory below 4GB (FF00_0000h to

FFFF_FFFFh) is accepted by the primary side of the PCI P2P bridge and forwarded

to the PCI bus. This allows systems with corrupted or unprogrammed flash to boot

from a PCI device. The PCI-to-PCI bridge Memory Space Enable bit does not need

to be set (nor any o ther bits) in order for th ese cycl es to go to PCI. Note that BIOS

decode range bits and the other BIOS protection bits have no effect when PCI is

selected.

When SPI or LPC is selected, the range that is decoded is further qualified by other

configuration bits described in the respective sections.

The value in this field can be overwritten by software as long as the BIOS Interface

Lock-Down (bit 0) is not set.

NOTE: Boot BIOS Destination Select to LPC/PCI by functional strap or via Boot

BIOS Destination Bit will not affect SPI accesses initiated by ME or

Integrated GbE LAN.

Server Error Reporting Mode (SERM) — R/W.

0 = The Intel® ICH8 is the final t arget of all errors. The (G)MCH sends a messages

to the ICH8 for the purpose of generating NMI.

1 = The (G)MCH is th e fin al target of all errors from PCI Express* and DMI. In this

mode, if the ICH8 detects a fatal, non-fatal, or correctable error on DMI or its

downstream ports, it s ends a message t o th e (G) MCH. If the ICH8 rece iv es an

ERR_* message from the downstream port, it sends that message to the

(G)MCH.

8 Reserved

(Mobile

only)

Mobile IDE Configuration Lock Down (MICLD) — R/WLO.

0 = Disabled.

1 = BUC.PRS (offset 3414h, bit 1) is locked and cannot be written until a system

reset occurs. This prevents rogue software from changing the default state of

the PATA pins during boot after BIOS configures them. This bit is write once,

and is cleared by system reset and when returning from the S3/S4/ S 5 state s.

7:6

(Desktop

only) Reserved

(Mobile

only)

FERR# MUX Enable (FME) — R/W. This bit enables FERR# to be a processor

break event indication. See Chapter 5.13.5 for a functional description.

0 = Disabled.

1 = The ICH8 examines FERR# during a C2, C3, or C4 state as a break event.

Bits 11:10 Description

0xb SPI

10b PCI

11b LPC

Chipset Configuration Registers

302 Intel® ICH8 Family Datasheet

No Reboot (NR) — R/W. This bit is set when the “No Reboot” strap (SPKR pin on

ICH8) is sampled high on PWROK. This bit may be set or cleared by software if the

strap is sampled low but may not override the strap when it indicates “No Reboot”.

0 = System will reboot upon the second timeout of the TCO timer.

1 = The TCO timer will count down and generate the SMI# on the first timeout, but

will not reboot on the second timeout.

Alternate Access Mode Enable (AME) — R/W.

0 = Disabled.

1 = Alternate access read only registers can be written, and write only registers

can be read. Before entering a low power state, several registers from

powered down parts may need to be sav ed. In the majority of cases, this is not

an issue, as registers have read and write paths. However, several of the ISA

compatible registers are either read only or write only. To get data out of write-

only registers, and to restore data into read-only registers, the ICH8

implements an alternate access mode. For a list of these registe r s see

Section 5.13.10.

Shutdown Policy Select (SPS) — R/W. When cleared (default), the ICH8 will

drive INIT# in response to the shutdown Vendor Defined Message (VDM). When

set to 1, ICH8 will treat the shutdown VDM similar to receiving a CF9h I/O write

with data value o6h, and will drive PLTRST# active.

Reserved Page Route (RPR) — R/W. Determines where to send the reserved

page registers. These addresses are sent to PCI or LPC for the purpose of

generating POST codes. The I/O addresses modified by this field are: 80h, 84h,

85h, 86h, 88h, 8Ch, 8Dh, and 8Eh.

0 = Writes will be forwarded to LPC, shadowed within the ICH, and reads will be

returned from the internal shadow

1 = Writes will be forwarded to PCI, shadowed within the ICH, and reads will be

returned from the internal shadow.

Note, if some writes are done to LPC/PCI to these I/O ranges, and then this bit is

flipped, such that writes will now go to the other interface, the reads will not return

what was last written. Shadowing is performed on each interface.

The aliases for these registers, at 90h, 94h, 95h, 96h, 98h, 9Ch, 9Dh, and 9Eh, are

always decoded to LPC.

1Reserved

BIOS Interface Lock-Down (BILD) — R/WLO.

0 = Disabled.

1 = Prevents BUC.TS (offset 3414, bit 0) and GCS.BBS (offset 3410h, bits 11:10)

from being changed. This bit can only be written from 0 to 1 once.

Bit Description

Intel® ICH8 Family Datasheet 303

Chipset Configuration Registers

7.1.70 BUC—Backed Up Control Regi ster

Offset Address: 3414–3414h Attribute: R/W

Default Value: 0000000xb (Desktop) Size : 8-bit

0000001xb (Mobile)

All bits in this register are in the RTC well and only cleared by RTCRST#.

7.1.71 FD—Function Disable Register

Offset Address: 3418–341Bh Attribute: R/W, RO

Default Value: See bit description Size: 32-bit

The UHCI functions must be disabled from highest function number to lowest within

each PCI device (Device 29 or Device 26). For example, if only two UHCIs are wanted

on Device 29, software must disable UHCI #3 (UD3 bit set). When disabling UHCIs, the

EHCI Structural Parameters Registers must be updated with coherent information in

“Number of Companion Controllers” and “N_Ports” fields.

When disabling a function, only the configuration space is disabled. Software must

ensure that all functionality within a controller that is not desired (such as memory

spaces, I/O spaces, and DMA engines) is disabled prior to disabling the function.

When a function is disabled, software must not attempt to re-enable it. A disabled

function can only be re-enabled by a platform reset.

Bit Description

7:3 Reserved

CPU BIST Enable (CBE) — R/W. This bit is in the resume well and is reset by

RSMRST#, but not PLTRST# nor CF9h writes.

0 = Disabled.

1 = The INIT# signals will be driven active when CPURST# is active. INIT# and

INIT3_3V# will go inactive with the same timings as the other processor

interface signals (hold time after CPURST# inactive).

(Mobile

only)

PATA Reset State (PRS) — R/W.

0 = Disabled.

1 = The reset state of the PATA pins will be driven/tri-state.

(Desktop

only) Reserved

Top Swap (TS) — R/W.

0 = Intel® ICH8 will not invert A16.

1 = ICH8 will invert A16 for cycles going to the BIOS space (but not the feature

space) in the FWH.

If ICH8 is strapped for Top-Swap (GNT3# is low at rising edge of PWROK), then this

bit cannot be cleared by software. The strap jumper should be removed and the

system rebooted.

Chipset Configuration Registers

304 Intel® ICH8 Family Datasheet

Bit Description

31:26 Reserved

25 Serial ATA Disable 2 (SAD2) — R/W. Default is 0 .

0 = The SATA controller #2 (D31:F5) is enabled.

1 = The SATA controller #2 (D31:F5) is disabled.

24 Thermal Throttle Disable (TTD) — R/W. Default is 0.

0 = Thermal Throttle is enabled.

1 = Thermal Throttle is disabled.

23:22 Reserved

PCI Express* 6 Disable (PE6D) — R/W. Default is 0. When disabled, the link for

this port is put into the “link down” state.

0 = PCI Express* port #6 is enabled.

1 = PCI Express port #6 is disabled.

PCI Express 5 Disable (PE5D) — R/W. Default is 0. When disabled, the link for this

port is put into the link down state.

0 = PCI Express port #5 is enabled.

1 = PCI Express port #5 is disabled.

PCI Express 4 Disable (PE4D) — R/W. Default is 0. When disabled, the link for this

port is put into the “link down” state.

0 = PCI Express* port #4 is enabled.

1 = PCI Express port #4 is disabled.

PCI Express 3 Disable (PE3D) — R/W. Default is 0. When disabled, the link for this

port is put into the link down state.

0 = PCI Express port #3 is enabled.

1 = PCI Express port #3 is disabled.

PCI Express 2 Disable (PE2D) — R/W. Default is 0. When disabled, the link for this

port is put into the link down state.

0 = PCI Express port #2 is enabled.

1 = PCI Express port #2 is disabled.

PCI Express 1 Disable (PE1D) — R/W. Default is 0. When disabled, the link for this

port is put into the link down state.

0 = PCI Express port #1 is enabled.

1 = PCI Express port #1 is disabled.

15 EHCI #1 Disable (EHCI1 D) — R/W. Default is 0.

0 = The EHCI #1 is enabled.

1 = The EHCI #1 is disabled.

LPC Bridge Disable (LBD) — R/W. Default is 0.

0 = The LPC bridge is enabled.

1 = The LPC bridge is disabled. Unlike the other disables in this register, the following

additional spaces will no longer be decoded by the LPC bridge:

• · Memory cycles below 16 MB (1000000h)

• · I/O cycles below 64 KB (10000h)

• · The Internal I/OxAPIC at FEC0_0000 to FECF_FFFF

Memory cy cles in the LPC BIOS r ange below 4 GB will still be decoded when this bit is

set, but the aliases at the top of 1 MB (the E and F segment) no longer will be

decoded.

Intel® ICH8 Family Datasheet 305

Chipset Configuration Registers

EHCI #2 Disable (EHCI2D) — R/W. Default is 0.

0 = The EHCI #2 is enabled.

1 = The EHCI #2 is disabled.

NOTE: When this bit is set, the UHCI #5 function is not available and the UHCI #4

must be disabled by setting bit 11 in this register.

USB1 #5 Disable (U5D) — R/W. Default is 0

0 = The UHCI #5 is enabled.

1 = The UHCI #5 is disabled.

NOTE: When the EHCI #2 Device Disable (EHCI2D) is set, thi s bit is a don’ t care

UHCI #4 Disable (U4D) — R/W. Default is 0.

0 = The 4th UHCI (ports 6 and 7) is enabled.

1 = The 4th UHCI (ports 6 and 7) is disabled.

NOTE: UHCI #4 must be disabled when EHCI #2 is disabled with bit 13 in this

10 UHCI #3 Disable (U3D) — R/W. Default is 0.

0 = The 3rd UHCI (ports 4 and 5) is enabled.

1 = The 3rd UHCI (ports 4 and 5) is disabled.

9UHCI #2 Disable (U2D) — R/W. Default is 0.

0 = The 2nd UHCI (ports 2 and 3) is enabled.

1 = The 2nd UHCI (ports 2 and 3) is disabled.

8UHCI #1 Disable (U1D) — R/W. Default is 0.

0 = The 1st UHCI (ports 0 and 1) is enabled.

1 = The 1st UHCI (ports 0 and 1) is disabled.

7:5 Reserved

Intel® High Definiti on Audio Disable (ZD) — R/W. Defaul t is 0.

0 = The Intel High Definition Audio controller is enabled.

1 = The Intel High Definition Audio controller is disabled and its PCI configuration

space is not accessible.

SM Bus Disable (SD) — R/W. Default is 0.

0 = The SM Bus controller is enabled.

1 = The SM Bus controller is disabled. In ICH5 and previous, this also disabled the

I/O space. In ICH8, it only disables the configuration space.

2Serial ATA Disable 1 (SAD1) — R/W. Default is 0.

0 = The SATA controller #1 (D31:F2) is enabled.

1 = The SATA controller #1 (D31:F2) is disabled.

1 Reserved

0 BIOS must set this bit to 0b

Bit Description

Chipset Configuration Registers

306 Intel® ICH8 Family Datasheet

7.1.72 CG—Clock Gating (Mobile Only)

Offset Address: 341C–341Fh Attribute: R/W, RO

Default Value: 00000000h Size: 32-bit

Bit Description

31 Legacy (LPC) Dynami c Clock Gate En a b le — R/W.

0 = Legacy Dynamic Clock Gating is Disabled

1 = Legacy Dynamic Clock Gating is Enabled

PATA Dynamic Clock Gate Enable — R/W.

0 = PATA Dynamic Clock Gating is Disabled

1 = PATA Dynamic Clock Gating is Enabled

29:28

USB UHCI Dynamic Clock Gate Enable — R/W.

0 = USB UHCI Dynamic Clock Gating is Disabled

1 = USB UHCI Dynamic Clock Gating is Enabled

0 = Reserved

1 = Reserved

27 Reserved

26 SATA Port 2 Dynamic Clock Gate Enable — R/W.

0 = SATA Port 2 Dynamic Clock Gating is Disabled

1 = SATA Port 2 Dynamic Clock Gating is Enabled

25 SATA Port 1 Dynamic Clock Gate Enable — R/W.

0 = SATA Port 1 Dynamic Clock Gating is Disabled

1 = SATA Port 1 Dynamic Clock Gating is Enabled

24 SATA Port 0 Dynamic Clock Gate Enable — R/W.

0 = SATA Port 0 Dynamic Clock Gating is Disabled

1 = SATA Port 0 Dynamic Clock Gating is Enabled

LAN Static Clock Gating Enable (LANSCGE) — R/W.

0 = LAN Static clock gating is disabled

1 = LAN Static clock gating is enabled when the LAN Disable bit is set in th e Function

Disable SUS Well register.

22 High Definition Audio Dynamic Clock Gate Enable — R/W.

0 = High Definition Audio Dynamic Clock Gating is Disabled

1 = High Definition Audio Dynamic Clock Gating is Enabled

21 High Definition Audio Static Clock Gate Enable — R/W.

0 = High Definition Audio Static Clock Gating is Disabled

1 = High Definition Audio Static Clock Gating is Enabled

20 USB EHCI Static Clock Gate Enable — R/W.

0 = USB EHCI Static Clock Gating is Disabled

1 = USB EHCI Static Clock Gating is Enabled

19 USB EHCI Dynamic Clock Gate Enable — R/W.

0 = USB EHCI Dynamic Clock Gating is Disabled

1 = USB EHCI Dynamic Clock Gating is Enabled

18:17 Reserved

16 PCI Dynamic Gat e En able — R/W.

0 = PCI Dynamic Gating is Disabled

1 = PCI Dynamic Gating is Enabled

Intel® ICH8 Family Datasheet 307

Chipset Configuration Registers

7.1.73 FDSW—Function Disable SUS Well

Offset Address: 3420h Attribute: R/W, RO

Default Value: 0000h Size: 8-bit

15 IDE C3 HV IO Biasing Disable (IC3HVBD) — R/W.

0 = IDE HV IO Biasing is always on

1 = IDE HV IO Biasing is disabled on selected pins when in C3.

14:5 Reserved

4PCI Express* RX Clock Gating Enable (PRXCGEN) — R/W.

0 = AFE Rx clock gating is disabled

1 = AFE Rx clock gating is enabled whenever all PCIe ports Rx are in squelch

3DMI and PCI Express* RX Dynamic Clock Gate Enable — R/W.

0 = DMI and PCI Express root port RX Dynamic Clock Gating is Disabled

1 = DMI and PCI Express root port RX Dynamic Clock Gating is Enabled

2PCI Express TX Dynamic Clock Gate Enable — R/W.

0 = PCI Express root port TX Dynamic Clock Gating is Disabled

1 = PCI Express root port TX Dynamic Clock Gating is Enabled

1DMI TX Dynamic Clock Gate Enable — R/W.

0 = DMI TX Dynamic Clock Gating is Disabled

1 = DMI TX Dynamic Clock Gating is Enabled

0PCI Express Root Port Static Clock Gate Enable — R/W.

0 = PCI Express root port Static Clock Gating is Disabled

1 = PCI Express root port Static Clock Gating is Enabled

Bit Description

Function Disable SUS Well Lockdown (FDSWL)— R/WL

0 = FDSW registers are not locked down

1 = FDSW registers are locked down

NOTE: This bit must be set when Intel® Active Management Technology is enabled

(ICH8DO and ICH8M-E Only).

6:1 Reserved

LAN Disable — R/WL

0 = LAN is enabled

1 = LAN is Disabled.

If the Function Disa ble SUS Well Lockdown bit is set, this register is locked.

Chipset Configuration Registers

308 Intel® ICH8 Family Datasheet

7.1.74 CIR8—Chipset Initialization Register 8

Offset Address: 3430h Attribute: R/W, RO

Default Value: 00h Size: 8-bit

7.1.75 CIR9—Chipset Initialization Register 9

Offset Address: 350Ch–350Fh Attribute: R/W, RO

Default Value: 00000000h Size: 32-bit

§ §

Bit Description

7:2 Reserved

1:0 CIR8 Field 1 — R/W. BIOS must program this field to 11b.

Bit Description

31:28 Reserved

27:26 CIR9 Field 1 — R/W. BIOS must program this field to 10b.

25:0 Reserved

Intel® ICH8 Family Datasheet 309

Gigabit LAN Configuration Registers

8 Gigabit LAN Configuration

Registers

8.1 Gigabit LAN Configuration Registers

(Gigabit LAN — D25:F0)

Note: Register address locations that are not shown in Table 143 and should be treated as

Reserved.

Table 104. Gigabit LAN Configuration Registers Address Map

(Gigabit LAN —D25:F0) (Sheet 1 of 2)

Offset Mnemonic Register Name Function 0

Default Type

00h–01h VID Vendor Identification 8086h RO

02h–03h DID Device Identification See register

description RO

04h–05h PCICMD PCI Command 0000h R/W, RO

06h–07h PCISTS PCI Status 0010h R/WC, RO

08h RID Revision Identification See register

description RO

09h–0Bh CC Class Code 020000 RO

0Ch CLS Cache Line Size 00h R/W

0Dh PLT Primary Latency Timer 00h RO

0Eh HEADTYP Header Type 00h RO

10h–13h MBARA Memory Base Address A 00000000h R/W, RO

14h–17h MBARB Memory Base Address B 00000000h R/W, RO

18h–1Bh MBARC Memory Base Address C 00000000h R/W, RO

2Ch–2Dh SID Subsystem ID See register

description. RO

2Eh–2Fh SVID Subsystem Vendor ID See register

description RO

30h–33h ERBA Expansion ROM Base Address See register

description RO

34h CAPP Capabilities List Pointer C8h RO

3Ch–3Dh INTR Interrupt Information See register

description. R/W, RO

3Eh MLMG Maximum Latency/Minimum

Grant 00h RO

C8h–C9h CLIST1 Capabilities List 1 D001h RO

CAh–CBh PMC PCI Power Management Capability See register

description RO

CCh–CDh PMCS PCI Power Management Control

and Status See register

description R/WC, R/W,

Gigabit LAN Configuration Registers

310 Intel® ICH8 Family Datasheet

8.1.1 VID—Vendor Identification Register

(Gigabit LAN—D25:F0)

Address Offset: 00h–01h Attribute: RO

Default Value: 8086h Size: 16 bits

8.1.2 DID—Device Identification Register

(Gigabit LAN—D25:F0)

Address Offset: 02h–03h Attribute: RO

Default Value: See bit description Size: 16 bits

CFh DR Data Register See register

description RO

D0h–D1h CLIST2 Capabilit ies List 2 0005h RO

D2h–D3h MCTL Message Control 0080h R/W, RO

D4h–D7h MADDL Message Address Low See register

description R/W

D8h–DBh MADDH Message A ddress High See register

description R/W

DCh–DDh MDAT Message Data See register

description R/W

Table 104. Gigabit LAN Configuration Registers Address Map

(Gigabit LAN —D25:F0) (Sheet 2 of 2)

Offset Mnemonic Register Name Function 0

Default Type

Bit Description

15:0 Vendor ID — RO. This is a 16-bit value assigned to Intel. The field may be auto-loaded

from the NVM at address 0Eh during init time depending on the "Load Vendor/Device

ID" bit field in NVM word 0Ah with a default value of 8086h.

Bit Description

15:0 Device ID — RO. This is a 16-bit value assigne d to the Intel® ICH8 Gigabit LAN

controller. The field may be auto-loaded from the NVM word 0Dh during initialization

time depending on the "Load Vendor/Device ID" bit field in NVM word 0Ah.

Intel® ICH8 Family Datasheet 311

Gigabit LAN Configuration Registers

8.1.3 PCICMD—PCI Command Register

(Gigabit LAN—D25:F0)

Address Offset: 04h–05h Attribute: R/W, RO

Default Value: 0000h Size: 16 bits

Bit Description

15:11 Reserved

Interrupt Disable — R/W. This disables pin-based INTx# interrupts on enabled Hot-

Plug and power management events. This bit has no effect on MSI operation.

0 = Internal INTx# messages are generated if there is an interrupt for Hot-Plug or

power management and MSI is not enabled.

1 = Internal INTx# messages will not be generated.

This bit does not affect interrupt forwarding from devices connected to the root port.

Assert_INTx and Deassert_INTx messages will still be forwarded to the internal

interrupt c ontrollers if this bit is set.

9Fast Back to Back Enable (FB E) — RO. Hardwired to ‘0’.

SERR# Enable (SEE) — R/W.

0 = Disable

1 = Enables the Gb LAN controller to generate an SERR# message when PSTS.SSE is

set.

7Wait Cycle Co ntrol (WCC) — RO. Hardwired to ‘0’.

Parity Error Response (PER) — R/W.

0 = Disable.

1 = Indicates that the device is capable of reporting parity errors as a master on the

backbone.

5Palette Snoop Enable (PSE) — RO. Hardwired to ‘0’.

4Postable Memory Write Enable (PMWE) — RO. Hardwired to ‘0’.

3Special Cycle Enable (SCE) — RO. Hardwired to ‘0’.

Bus Master Enable (BME) — R/W.

0 = Disable. All cycles from the device are maste r aborted

1 = Enable. Allows the root port to forward cycles onto the backbone from a Gigabit

LAN* device.

Memory Space Enable (MSE) — R/W.

0 = Disable. Memory cycles wi thin the range specified by the memory base and limit

registers are master aborte d on the backbone.

1 = Enable. Allows memory cycles within the range specified by the memory base and

limit registers can be forwarded to the Gigabit LAN device.

I/O Space Enable (IOSE) — R/W. This bit controls acc ess to the I/O space regi ster s.

0 = Disable. I/O cycles within the range specified by the I/O base and limit registers

are master aborted on the backbone.

1 = Enable. Allows I/O cycles within the range specified by the I/O base and limit

registers can be forwarded to the Gigabit LAN devi ce.

Gigabit LAN Configuration Registers

312 Intel® ICH8 Family Datasheet

8.1.4 PCISTS—PCI Status Register

(Gigabit LAN—D25:F0)

Address Offset: 06h–07h Attribute: R/WC, RO

Default Value: 0010h Size: 16 bits

Bit Description

Detected Parity Error (DPE) — R/WC.

0 = No parity error detected.

1 = Set when the Gb LAN controller receives a command or data from the backbone

with a parity error. This is set even if PCIMD.PER (D25:F0, bit 6) is not se t.

14 Signaled System Error (SSE) — R/WC.

0 = No system error signaled.

1 = Set when the Gb LAN controller signals a system error to the internal SERR# logic.

Received Master Abort (RMA) — R/WC.

0 = Root port has not received a completion with unsupported request status from the

backbone.

1 = Set when the Gb LAN controller receive s a com ple tion with unsupported request

status from the backbone.

Received Target Abort (RTA) — R/WC.

0 = Root port has not received a completion with completer abort from the backbone.

1 = Set when the Gb LAN controller receives a completion with completer abort from

the backbone.

Signaled Target Abort (STA) — R/WC .

0 = No target abort received.

1 = Set whenever the Gb LAN controller forwards a target abort received from the

downstream device onto the backbone.

10:9 DEVSEL# Timing Status (DEV_STS) — RO. Hardwired to ‘0’.

Master Data Parity Error Detected (DPED) — R/WC.

0 = No data parity error received.

1 = Set when the Gb LAN Controller receives a completion with a data parity error on

the backbone and PCIMD.PER (D25:F0, bit 6) is set.

7 Fast Back to Back Capable (FB2BC) — RO. Hardwired to ‘0’.

6Reserved

5 66 MHz Capable — RO. Hardwired to ‘0’.

4 Capabilities List — RO. Hardwired to ‘1’. Indicates the presence of a capabilities list.

Interrupt Stat us — RO. Indi cat es s tat us of Hot-Plug and power ma nage men t in terrup ts

on the root port that result in INTx# message generation.

0 = Interrupt is deasserted.

1 = Interrupt is asserted.

This bit is not set if MSI is enabled. If MSI is not enabled, this bit is set regardless of the

state of PCICMD.Interrupt Disable bit (D25:F0:04h:bit 10).

2:0 Reserved

Intel® ICH8 Family Datasheet 313

Gigabit LAN Configuration Registers

8.1.5 RID—Revision Identification Register

(Gigabit LAN—D25:F0)

Offset Address: 08h Attribute: RO

Default Value: See bit description Size: 8 bits

8.1.6 CC—Class Code Register

(Gigabit LAN—D25:F0)

Address Offset: 09h–0Bh Attribute: RO

Default Value: 020000h Size: 24 bits

8.1.7 CLS—Cache Line Size Register

(Gigabit LAN—D25:F0)

Address Offset: 0Ch Attribute: R/W

Default Value: 00h Size: 8 bits

8.1.8 PLT—Primary Latency Timer Register

(Gigabit LAN—D25:F0)

Address Offset: 0Dh Attribute: RO

Default Value: 00h Size: 8 bits

8.1.9 HT—Header Type Register

(Gigabit LAN—D25:F0)

Address Offset: 0Eh Attribute: RO

Default Value: 00h Size: 8 bits

Bit Description

7:0 R evision ID — RO. Refer to the Intel® I/O Controller Hub 8 (ICH8) Fami ly Specification

Update for the value of the Revision ID Register.

Bit Description

23:0 Class Code— RO. This field indicates the device as an Ethernet Adapter.

020000h = Ethernet Adapter.

Bit Description

7:0 Cache Line Size — R/W . This field is implemented by PCI devices as a readwrite field for

legacy compatibility purposes but has no impact on any device functionality.

Bit Description

7:0 Latency Timer (LT) — RO. Hardwired to 0.

Bit Description

7:0 Header Type (HT) — RO.

00h = Indicates this is a single function device.

Gigabit LAN Configuration Registers

314 Intel® ICH8 Family Datasheet

8.1.10 MBARA—Memory Base Address Register A

(Gigabit LAN—D25:F0)

Address Offset: 10h–13h Attribute: R/W, RO

Default Value: 00000000h Size: 32 bits

The internal CSR registers and memories are accessed as direct memory mapped

offsets from the base address register. SW may only access whole DWord at a time.

8.1.11 MBARB—Memory Base Address Register B

(Gigabit LAN—D25:F0)

Address Offset: 14h–17h Attribute: R/W, RO

Default Value: 00000001h Size: 32 bits

The internal registers that are used to access the LAN Space in the External FLASH

device. Accessed to these registers are direct memory mapped offsets from the base

address register. SW may only access a DWord at a time.

Bit Description

31:15 Base Address (BA) — R/W. Software programs this field with the base address of

this region.

14:4 Memory Size (MSIZE) — R/W. Memory size is 32 KB.

3Prefetchable Memory (PM) — RO. The Gb LAN controller does not implement

prefetchable memory.

2:1 Memory Type (MT) — RO. Set to 00b indicating a 32 bit BAR.

0 Memory / IO Space (MIOS) — RO. Set to ‘0’ indicating a Memory Space BAR.

Bit Description

31:12 Base Address (BA) — R/W. Software programs this field with the base address of

this region.

11:4 Memory Size (MSIZE) — R/W. Memory size is 4K Bytes.

3Prefetchable Memory (PM) — RO. The Gb LAN controller does not implement

prefetchable memory.

2:1 Memory Type (MT) — RO. Set to 00b indicating a 32 bit BAR.

0 Memory / IO Space (MIOS) — RO. Set to ‘0’ indicating a Memory Space BAR.

Intel® ICH8 Family Datasheet 315

Gigabit LAN Configuration Registers

8.1.12 MBARC—Memory Base Address Register C

(Gigabit LAN—D25:F0)

Address Offset: 18h–1Bh Attribute: R/W, RO

Default Value: 00000000h Size: 32 bits

Internal registers, and memories, can be accessed using I/O operations. There are two

4B registers in the IO mapping win dow: Addr Reg and Data R eg. SW ma y only access a

Dword at a time.

8.1.13 SID—Subsystem ID Register

(Gigabit LAN—D25:F0)

Address Offset: 2Ch–2Dh Attribute: RO

Default Value: See bit description Size: 16 bits

8.1.14 SVID—Subsystem Vendor ID Register

(Gigabit LAN—D25:F0)

Address Offset: 2Eh–2Fh Attribute: RO

Default Value: See bit description Size: 16 bits

Bit Description

31:5 Base Address (BA) — R/W. Software programs this field with the base address of

this region.

4:1 I/O Size (IOSIZE) — RO. I/O space size is 32 Bytes.

0 Memory / IO Space (MIOS) — RO. Set to ‘1’ indicating an IO Space BAR.

Bit Description

15:0

Subsystem ID (SID) — RO. This value may be loaded automatically from the NVM

W ord 0Ch upon power up depending on the "Load Subsystem ID" bit field in NVM word

0Ah. A value of 8086h is default for this field upon power up if the NVM does not

respond or is not programmed. All functions are initialized to the same value.

Bit Description

15:0

Subsystem Vendor ID (SVID) — RO. This value may be loade d automaticall y from the

NVM W ord 0Bh upon power up or reset depending on the "Load Subsystem ID" bit field

in NVM word 0Ah with a default value of 0000h. This v alue is loadable from NVM word

location 0Bh.

Gigabit LAN Configuration Registers

316 Intel® ICH8 Family Datasheet

8.1.15 ERBA—Expansion ROM Base Address Register

(Gigabit LAN—D25:F0)

Address Offset: 30h–33h Attribute: RO

Default Value: See bit description Size: 32 bits

8.1.16 CAPP—Capabilities List Pointer Register

(Gigabit LAN—D25:F0)

Address Offset: 34h Attribute: R0

Default Value: C8h Size: 8 bits

8.1.17 INTR—Interrupt Information Register

(Gigabit LAN—D25:F0)

Address Offset: 3Ch–3Dh Attribute: R/W, RO

Default Value: 0100h Size: 16 bits

8.1.18 MLMG—Maximum Latency/Minimum Grant Register

(Gigabit LAN—D25:F0)

Address Offset: 3Eh Attribute: RO

Default Value: 00h Size: 8 bits

Bit Description

31:0 Expansion ROM Base Address (ERBA) — RO. This register is used to define the address

and size information for boot-time access to the optional FLASH memory. If no Flash

memory exists this register reports 00000000h.

Bit Description

7:0 Capabilities Pointer (PTR) — RO. This field indicates that the pointer for the first

entry in the capabilities list is at C8h in configuration space.

Bit Description

15:8 Interrupt Pin (I PIN) — RO. This field indicates the interrupt pin driven by the Gb LAN

controller.

01h = The Gb LAN controller implements legacy inte rrupts on INTA.

7:0 Interrupt Line (ILINE) — R/W. Default = 00h. Software written value to indicate

which interrupt line (vector) the interrupt is connected to. No hardware action is taken

on this register.

Bit Description

7:0 Maximum Latency/Minimum Grant (MLMG ) — RO. Not used. Hardwired to 00h.

Intel® ICH8 Family Datasheet 317

Gigabit LAN Configuration Registers

8.1.19 CLIST 1—Capabilities List Register 1

(Gigabit LAN—D25:F0)

Address Offset: C8h–C9h Attribute: RO

Default Value: D001h Size: 16 bits

8.1.20 PMC—PCI Power Management Capabilities Register

(Gigabit LAN—D25:F0)

Address Offset: CAh–CBh Attribute: RO

Default Value: See bit descriptions Size: 16 bits

Bit Description

15:8 Next Capability (NEXT) — RO. Value of D0h indicates the location of the next pointer.

7:0 Capability ID (CID) — RO. Indicates the linked list item is a PCI Power Management

Bit Description

15:11

PME_Support (PMES) — RO. This five-bit field indicates the power states in which the

function may assert PME#. It depend on PM Ena and AUX-PWR bits in word 0Ah in the

NVM:

Condition Functionality Value

PM Ena=0 No PME at all states 00000b

PM Ena & AUX-PWR=0 PME at D0 and D3hot 01001b

PM Ena & AUX-PWR=1 PME at D0, D3hot and D3cold 11001b.

10 D2_Support (D2S) — RO. The D2 state is not supported.

9 D1_Support (D1S) — RO The D1 state is not supported.

8:6 Aux_Current (AC) — RO. Required current defined in the Data Register.

5Device Specific Initialization (DSI) — RO. Set to 1. The Gb LAN Controller requires its

device driver to be executed following transition to the D0 un-initialized state.

4 Reserved

3 PME Clock (PMEC) — RO. Hardwired to ‘0’.

2:0 Version (VS) — RO. Hardwired to 010b to indicate support for Revision 1.1 of the PCI

Power Management Specification.

Gigabit LAN Configuration Registers

318 Intel® ICH8 Family Datasheet

8.1.21 PMCS—PCI Power Management Control and Status

Address Offset: CCh–CDh Attribute: R/WC, R/W, RO

Default Value: See bit description Size: 16 bits

8.1.22 DR—Data Regist er

(Gigabit LAN—D25:F0)

Address Offset: CFh Attribute: RO

Default Value: See bit description Size: 8 bits

Bit Description

15 PME Status (PMES) — R/WC. This bit is set to 1 when the function detects a wake-up

event independent of the state of the PMEE bit. Writing a 1 will clear this bit.

14:13

Data Scale (DSC) — R/W. This field indicates th e scaling factor to be used when

interpreting the value of the Data register.

For the GbE LAN and co mmon func tions t his fi eld equal s 01b (indicati ng 0.1 wat t units)

if the PM is enabled in the NVM, and the Data_Select field is set to 0, 3, 4, 7, (or 8 for

Function 0). Else it equals 00b.

For th e manage abil it y functions, th is fi el d equals 10b (indicat ing 0. 01 watt units) if t he

PM is enabled in the NVM, and the Data_Select field is set to 0, 3, 4, 7; otherwise, it

equals 00b.

12:9

Data Select (DSL) — R/W. This four-bit field is used to select which data is to be

reported through the Data register (offset CFh) and Data_Scale field. These bits are

writeable only when the Power Management is enabled via NVM.

0h = D0 Power Consumption

3h = D3 Power Consumption

4h = D0 Power Dissipation

7h = D3 Power Dissipation

8h = Common Power

All other values are reserved.

8PME Enable (PMEE) — R/W. If Power Management is enabled in the NVM, writing a 1

to this register will enable Wakeup. If Power Management is disabled in the NVM,

writing a 1 to this bit has no affect, and will not set the bit to 1.

7:2 Reserved - Returns a value of ‘000000’.

1:0

Power State (PS) — R/W. This field is used both to determine the current power state

of the Gb LAN Controller and to set a new power state. The values are:

00 = D0 state (default)

01 = Ignored

10 = Ignored

11 = D3 state (Power Management must be enables in the NV M or this cycle will be

ignored).

Bit Description

7:0

Report ed Dat a (RD) — RO. This register i s used to report power consumption and heat

dissipation. This register is controlled by the Data_Select field in the PMCS (Offset CCh,

bits 12:9), and the power scale is reported in the Data_Scale field in the PMCS (Offset

CCh, bits 14:13). The data of this field is loaded from the NVM if PM is enabled in the

NVM or with a default value of 0x00 otherwise.

Intel® ICH8 Family Datasheet 319

Gigabit LAN Configuration Registers

8.1.23 CLIST 2—Capabilities List Register 2

(Gigabit LAN—D25:F0)

Address Offset: D0h–D1h Attribute: RO

Default Value: 0005h Size: 16 bits

8.1.24 MCTL—Message Control Register

(Gigabit LAN—D25:F0)

Address Offset: D2h–D3h Attribute: R/W, RO

Default Value: 0080h Size: 16 bits

8.1.25 MADDL—Message Address Low Register

(Gigabit LAN—D25:F0)

Address Offset: D4h–D7h Attribute: R/W

Default Value: See bit description Size: 32 bits

Bit Description

15:8 Next Capability (NEXT) — RO. Value of 00h indicates the end of the li st.

7:0 Capability ID (CID) — RO. Indicates the linked list item is a Message Signaled

Interrupt Register.

Bit Description

15:8 Reserved

764-bit Capable (CID) — RO. Set to 1 to indicate that the Gb LAN Controller is capable of

generating 64-bit message addresses.

6:4 Multiple Message Enable (MME) — RO. Returns 000b to in dicate that the Gb LAN

controller only supports a single message.

3:1 Multiple Message Capable (MMC) — RO. The Gb LAN controller does not support

multiple messages.

MSI Enable (MSIE) — R/W.

0 = MSI generation is disabled.

1 = The Gb LAN controller will generate MSI for interrupt assertion instead of INTx

signaling.

Bit Description

31:0 Message Address Low (MADDL) — R/W. This field is written by the system to

indicate the lower 32 bits of the address to use for the MSI memory write transaction.

The lower two bits will always return 0 regardless of the write operation.

Gigabit LAN Configuration Registers

320 Intel® ICH8 Family Datasheet

8.1.26 MADDH—Message Address High Register

(Gigabit LAN—D25:F0)

Address Offset: D8h–DBh Attribute: R/W

Default Value: See bit description Size: 32 bits

8.1.27 MDAT—Message Data Register

(Gigabit LAN—D25:F0)

Address Offset: DCh–DDh Attribute: R/W

Default Value: See bit description Size: 16 bits

Bit Description

31:0 Message Address High (MADDH) — R/W. This field is written by the syst em to

indicate the upper 32 bits of the address to use for the MSI memory write transaction.

Bit Description

31:0 Message Data (MDAT) — R/W. This fiel d is written by the system to indicate the

lower 16 bits of the data written in the MSI memory write DWord transaction. The

upper 16 bits of the transaction are written as 0000h.

Intel® ICH8 Family Datasheet 321

Gigabit LAN Configuration Registers

8.2 GBAR0—Gigabit LAN Base Address Register 0

Registers

8.2.1 LDCR1—LAN Device Control Regi ster 1

(Gigabit LAN Memory Mapped Base Address Register)

Address Offset: GBAR0 + 00h Attribute: R/W, RO

Default Value: 00100201h Size: 32 bits

8.2.2 LDCR2—LAN Device Control Regi ster 2

(Gigabit LAN Memory Mapped Base Address Register)

Address Offset: GBAR0 + 18h Attribute: R/W, RO

Default Value: 001000000h Size: 3 2 bits

8.2.3 LDR1—LAN Device Initialization Register 1

(Gigabit LAN Memory Mapped Base Address Register)

Address Offset: GBAR0 + 20h Attribute: R/W, RO

Default Value: 1000xxxxh Size: 32 bits

Bit Description

31:25 Reserved

PLCD Power Do wn (PLCDPD ) — R/W. When the bit is cleared to '0', the PLCD power

down setting is controlled by the internal logic of the LAN controller. When set to '1' and

the LDCR.LPPDE is set as well, the LAN controller sets the external PLCD to power down

mode.

Further, if the LAN PHY Power Control functionality is implemented, the LAN controller

disconnects the LCD power supply (mobile only - see Section 5.3.6).

23:0 Reserved

Bit Description

31:21 Reserved

20 LAN PHY Power Down Enable (LPPDE) — R/W. When set, enables the PHY to enter

a low-power state when the LAN controller is at the Moff / D3 no WoL.

This bit is loaded from word 13h in the NVM

19:0 Reserved

Bit Description

31:0 LDR1 Field 1 — R/W.

Gigabit LAN Configuration Registers

322 Intel® ICH8 Family Datasheet

8.2.4 EXTCNF_CTRL—Extended Configuration Control Register

(Gigabit LAN Memory Mapped Base A ddress Register)

Address Offset: GBAR0 + F00h Attribute: R/W, RO

Default Value: 000000002h Size: 32 bits

8.2.5 LDR2—LAN Device Initialization Register 2

(Gigabit LAN Memory Mapped Base A ddress Register)

Address Offset: GBAR0 + 3004h Attribute: R/W

Default Value: B2B47CCh Size: 32 bits

§ §

Bit Description

31:6 Reserved

5SW Semaphore Flag (SWFLAG) — R/W. This bit is set by the device driver to gain

access permission to shared CSR registers with the firmware and hardware

4:0 Reserved

Bit Description

31:10 Reserved

19:16 LDR2 Field 1 — R/W. BIOS must program this field to 0101b.

15:0 Reserved

Intel® ICH8 Family Datasheet 323

LPC Interface Bridge Registers (D31:F0)

9 LPC Interface Bridge Registers

(D31:F0)

The LPC bridge function of the ICH8 resides in PCI Device 31:Function 0. This function

contains many other functional units, such as DMA and Interrupt controllers, Timers,

Power Management, System Management, GPIO, RTC, and LPC Configuration

Registers.

R egisters and functions associated with other functional units (EHCI, UHCI, IDE (Mobile

only), etc.) are described in their respective sections.

9.1 PCI Configuration Registers (LPC I/F—D31:F0)

Note: Address locations that are not shown should be treated as Reserved.

Table 105. LPC Interface PCI Register Address Map (LPC I/F—D31:F0) (Sheet 1 of 2)

Offset Mnemonic Register Name Default Type

00h–01h VID Vendor Identification 8086h RO

02h–03h DID Device Identification See register

description RO

04h–05h PCICMD PCI Command 0007h R/W, RO

06h–07h PCISTS PCI Status 0200h R/WC, RO

08h RID Revision Identification See register

description RO

09h PI Programming Interface 00h RO

0Ah SCC Sub Class Code 01h RO

0Bh BCC Base Class Code 06h RO

0Dh PLT Primary Latency Timer 00h RO

0Eh HEADTYP Header Type 80h RO

2Ch–2Fh SS Sub System Identifiers 00000000h R/WO

40h–43h PMBASE ACPI Base Address 00000001h R/W, RO

44h ACPI_CNTL ACPI Control 00h R/W

48h–4Bh GPIOBASE GPIO Base Address 00000001h R/W, RO

4C GC GPIO Control 00h R/W

60h–63h PIRQ[n]_ROUT PIRQ[A–D] Routing Control 80h R/W

64h SIRQ_CNTL Serial IRQ Control 10h R/W, RO

68h–6Bh PIRQ[n]_ROUT PIRQ[E–H] Routing Control 80h R/W

80h LPC_I/O_DEC I/O Decode Ranges 0000h R/W

82h–83h LPC_EN LPC I/F Enables 0000h R/W

84h–87h GEN1_DEC LPC I/F Generic Decode Range 1 00000000h R/W

88h–8Bh GEN2_DEC LPC I/F Generic Decode Range 2 00000000h R/W

8Ch–8Eh GEN3_DEC LPC I/F Generic Decode Range 3 00000000h R/W

LPC Interface Bridge Registers (D31:F 0)

324 Intel® ICH8 Family Datasheet

9.1.1 VID—Vendor Identification Register (LPC I/F—D31:F0)

Offset Address: 00h–01h Attribute: RO

Default Value: 8086h Size: 16-bit

Lockable: No Power Well: Core

9.1.2 DID—Device Identification Register (LPC I/F—D31:F0)

Offset Address: 02h–03h Attribute: RO

Default Value: See bit description Size: 16-bit

Lockable: No Power Well: Core

90h–93h GEN4_DEC LPC I/F Generic Decode Range 4 00000000h R/W

A0h–CFh Power Management (See

Section 9.8.1)

D0h–D3h FWH_SEL1 Firmware Hub Select 1 00112233h R/W, RO

D4h–D5h FWH_SEL2 Firmware Hub Select 2 4567h R/W

D8h–D9h FWH_DEC_EN1 Firmware Hub Decode Enable 1 FFCFh R/W, RO

DCh BIOS_CNTL BIOS Control 00h R/WLO, R/W

E0h–E1h FDCAP Feature Detection Capability ID 0000h RO

E2h FDLEN Feature Detection Capability

Length 0Ch RO

E3h F DVER Feature Detection Version 10h RO

E4h-EBh FDVCT Feature Vector See

Description RO

F0h–F3h RCBA Root Complex Base Address 00000000h R/W

Table 105. LPC Interface PCI Register Address Map (LPC I/F—D31:F0) (Sheet 2 of 2)

Offset Mnemonic Register Name Default Type

Bit Description

15:0 Vendor ID — RO. This is a 16-bit value assigned to Intel. Intel VID = 8086h

Bit Description

15:0 Device ID — RO. Thi s is a 16-bit value assigned to the Intel ® ICH8 LPC bridge. Refer

to the Intel ICH8 Family Specification Update for the value of the Device ID Register.

Intel® ICH8 Family Datasheet 325

LPC Interface Bridge Registers (D31:F0)

9.1.3 PCICMD—PCI COMMAND Register (LPC I/F—D31:F0)

Offset Address: 04h–05h Attribute: R/W, RO

Default Value: 0007h Size: 16-bit

Lockable: No Power Well: Core

9.1.4 PCISTS—PCI Status Register (LPC I/F—D31:F0)

Offset Address: 06–07h Attribute: RO, R/WC

Default Value: 0210h Size: 16-bit

Lockable: Noh Power We ll: Core

Note: For the writable bits, software must write a 1 to clear bits that are set. Writing a 0 to

the bit has no effect.

Bit Description

15:10 Reserved

9 Fast Back to Back Enable (FBE) — RO. Hardwired to 0.

8SERR# Enable (SERR_EN) — R/W. The LPC bridge generates SERR# if this bit is set.

7 Wait Cycle Control (WCC) — RO. Hardwired to 0.

Parity Error Response Enable (PERE) — R/W.

0 = No action i s taken when detecting a parity error.

1 = Enables the ICH8 LPC bridge to respond to parity errors detected on backbone

interface.

5 VGA Palette Snoop (VPS) — RO. Hardwired to 0.

4 Memory Write and Invalidate Enable (MWIE) — RO. Hardwired to 0.

3 Special Cycle Enable (SCE) — RO. Hardwired to 0.

2 Bus Master Enable (BME) — RO. Bus Masters cannot be disa bled.

1 Memory Space Enable (MSE) — RO. Memory space cannot be disabled on LPC.

0 I/O Space Enable (IOSE) — RO. I/O space cannot be disabled on LPC.

Bit Description

Detected Parity Error (DPE) — R/WC. Set when the LPC bridge detects a parity

error on the internal backbone. Set even if th e PCICMD.P ERE bit (D31:F0:04 , bit 6) is

0 = Parity Error Not detected.

1 = Parity Error detected.

14 Signaled System Error (SSE)— R/WC. Set when the LPC bridge signals a system

error to the internal SERR# logic.

Master Abort Status (RM A) — R/WC.

0 = Unsupported request status not received.

1 = The bridge received a completion with unsupported request status from the

backbone.

12 Received Target Abort (RTA) — R/WC.

0 = Completion abort not received.

1 = Completion with completion abort received from the backbone.

LPC Interface Bridge Registers (D31:F 0)

326 Intel® ICH8 Family Datasheet

9.1.5 RID—Revision Identification Register (LPC I/F—D31:F0)

Offset Address: 08h Attribute: RO

Default Value: See bit description Size: 8 bits

9.1.6 PI—Programming Interface Register (LPC I/F—D31:F0)

Offset Address: 09h Attribute: RO

Default Value: 00h Size: 8 bits

Signaled Target Abort (STA) — R/WC.

0 = Target abort Not generated on the backbone.

1 = LPC bridge generated a completion packet with target abort status on the

backbone.

10:9 DEVSEL# Timing Status (DEV_STS) — RO.

01 = Medium Timing.

Data Parity Error Detected (DPED) — R/WC.

0 = All conditions listed below Not met.

1 = Set when all three of the following conditions are met:

• LPC bridge receives a completion packet from the backbone from a previous request,

• Parity error has been detected (D31:F0:06, bit 15)

• PCICMD.PERE bit (D31:F0:04, bit 6) is set.

7Fast Back to Back Capable (FBC): Reserved – bit has no meaning on the internal

backbone.

6 Reserved.

566 MHz Capable (66MHZ_CAP) — Reserved – bit has no meaning on internal

backbone.

4 Capabilities List (CLI ST) — RO. Capability list exists on the LPC bridge.

3 Interrupt Status (IS) — RO. The LPC bridge does not generate interrupts.

2:0 Reserved.

Bit Description

7:0 Revision ID (RID) — RO. Refer to the Intel® I/O Controller Hub 8 (ICH8) Family

Specification Update for the value of the Revision ID Register

Bit Description

7:0 Programming Interface — RO.

Intel® ICH8 Family Datasheet 327

LPC Interface Bridge Registers (D31:F0)

9.1.7 SCC—Sub Class Code Register (LPC I/F—D31:F0)

Offset Address: 0Ah Attribute: RO

Default Value: 01h Size: 8 bits

9.1.8 BCC—Base Cl ass Co de Register (LPC I/F—D31:F0)

Offset Address: 0Bh Attribute: RO

Default Value: 06h Size: 8 bits

9.1.9 PLT—Primary Latency Ti me r Register (LPC I/F—D31:F0)

Offset Address: 0Dh Attribute: RO

Default Value: 00h Size: 8 bits

9.1.10 HEADTYP—Header Type Register (LPC I/F—D31:F0)

Offset Address: 0Eh Attribute: RO

Default Value: 80h Size: 8 bits

Bit Description

7:0 Sub Class Code — RO. 8-bit value that indicates the category of bridge for the LPC

bridge.

01h = PCI-to-ISA bridge.

Bit Description

7:0 Base Class Code — RO. 8-bit value that indicates the type of device for the LPC

bridge.

06h = Bridge device.

Bit Description

7:3 Master Latency Count (MLC) — Reserved.

2:0 Reserved.

Bit Description

7 Multi-Function D evice — RO. This bit is 1 to indicate a multi-function device.

6:0 Header Type — RO. This 7-bit field identifies the header layout of the configuration

space.

LPC Interface Bridge Registers (D31:F 0)

328 Intel® ICH8 Family Datasheet

9.1.11 SS—Sub System Identifiers Register (LPC I/F—D31:F0)

Offset Address: 2Ch–2Fh Attribute: R/WO

Default Value: 00000000h Size: 32 bits

This register is initialized to logic 0 by the assertion of PLTRST#. This register can be

written only once after PLTRST# de-assertion.

9.1.12 PMBASE—ACPI Base Address Register (LPC I/F—D31:F0)

Offset Address: 40h–43h Attribute: R/W, RO

Default Value: 00000001h Size: 32 bit

Lockable: No Usage: ACPI, Legacy

Power Well: Core

Sets base address for ACPI I/O registers, GPIO registers and TCO I/O registers. These

registers can be mapped anywhere in the 64-K I/O space on 128-byte boundaries.

Bit Description

31:16 Subsystem ID (SSID) — R/WO This is written b y BIOS . No hardw are actio n tak en on

this value.

15:0 Subsystem Vendor ID (SSVID) — R/WO This is written by BIOS. No hardware act ion

taken on this value.

Bit Description

31:16 Reserved

15:7 Base Address — R/W. This field provides 128 bytes of I/O space for ACPI, GPIO, and

TCO logic. This is placed on a 128-byte boundary.

6:1 Reserved

0 Resource Type Indicator (RTE) — RO. Hardwired to 1 to indicate I/O space.

Intel® ICH8 Family Datasheet 329

LPC Interface Bridge Registers (D31:F0)

9.1.13 ACPI_CNTL—ACPI Control Register (LPC I/F — D31:F0)

Offset Address: 44h Attribute: R/W

Default Value: 00h Size: 8 bit

Lockable: No Usage: ACPI, Legacy

Power Well: Core

9.1.14 GPIOBASE—GPIO Base Address Register (LPC I/F —

D31:F0)

Offset Address: 48h–4Bh Attribute: R/W, RO

Default Value: 00000001h Size: 32 bit

Bit Description

ACPI Enable (ACPI_EN) — R/W.

0 = Disable.

1 = Decode of the I/O range pointed to by the ACPI base register is enabled, and the

ACPI power management function is enabled. Note that the APM power

management ranges (B2/B3h) are always enabled and are not affected by this bit.

6:3 Reserved

2:0

SCI IRQ Select (SCI_IRQ_SEL) — R/W. This field specifies on which IRQ the SCI will

internally appear. If not using the APIC, the SCI must be routed to IRQ9–11, and that

interrupt is not sharable with the SERIRQ stream, but is shareable with other PCI

interrupts. If using the APIC, the SCI ca n also be mapped to IRQ20–23, and can be

shared with other interrupts.

NOTE: When the interrupt is mapped to APIC interrupts 9, 10 or 11, the APIC should be

programmed for active-high reception. When the interrupt is mapped to APIC

interrupts 20 through 23, the APIC should be programmed for active-low

reception.

Bits SCI Map

000b IRQ9

001b IRQ10

010b IRQ11

011b Reserved

100b IRQ20 (Only available if APIC enabled)

101b IRQ21 (Only available if APIC enabled)

110b IRQ22 (Only available if APIC enabled)

111b IRQ23 (Only available if APIC enabled)

Bit Description

31:16 Reserved. Always 0.

15:6 Base Address (BA) — R/W. Provides the 64 bytes of I/O space for GPIO.

5:1 Reserved. Always 0.

0 RO. Hardwired to 1 to indicate I/O space.

LPC Interface Bridge Registers (D31:F 0)

330 Intel® ICH8 Family Datasheet

9.1.15 GC—GPIO Control Register (LPC I/F — D31:F0)

Offset Address: 4Ch Attribute: R/W

Default Value: 00h Size: 8 bit

9.1.16 PIRQ[n]_ROUT—PIRQ[A,B,C,D] Routing Control Register

(LPC I/F—D31:F0)

Offset Address: PIRQA – 60h, PIRQB – 61h, Attribute: R/W

PIRQC – 62h, PIRQD – 63h

Default Value: 80h Size: 8 bit

Lockable: No Power Well: Core

Bit Description

7:5 Reserved.

GPIO Enable (EN) — R/W. This bit enables/disables decode of the I/O range pointed

to by the GPIO Base Address register (D31:F0:48h) and enables the GPIO function.

0 = Disable.

1 = Enable.

3:0 Reserved.

Bit Description

Interrupt Routing Enable (IRQEN) — R/W.

0 = The corresponding PIRQ is routed to one of the ISA-compatible interrupts

specified in bits[3:0].

1 = The PIRQ is not routed to the 8259.

NOTE: BIOS must program this bit to 0 during POST for any of the PIRQs that are

being used. The value of this bit may subsequently be changed by the OS

when setting up for I/O APIC interrupt delivery mode.

6:4 Reserved

3:0

IRQ Routing — R/W. (ISA compatible.)

Value IRQ Value IRQ

0000b Reserved 1000b Reserved

0001b Reserved 1001b IRQ9

0010b Reserved 1010b IRQ10

0011b IRQ3 1011b IRQ11

0100b IRQ4 1100b IRQ12

0101b IRQ5 1101b Reserved

0110b IRQ6 1110b IRQ14

0111b IRQ7 1111b IRQ15

Intel® ICH8 Family Datasheet 331

LPC Interface Bridge Registers (D31:F0)

9.1.17 SIRQ_CNTL—Serial IRQ Control Register

(LPC I/F—D31:F0)

Offset Address: 64h Attribute: R/W, RO

Default Value: 10h Size: 8 bit

Lockable: No Power Well: Core

Bit Description

7Serial IRQ Enable (SIRQEN) — R/W.

0 = The buffer is input only and internally SERIRQ will be a 1.

1 = Serial IRQs will be recognized. The SERIRQ pin will be configured as SERIRQ.

Serial IRQ Mode Select (SIRQMD) — R/W.

0 = The serial IRQ machine will be in quiet mode.

1 = The serial IRQ machine will be in continuous mode.

NOTE: F or sys tems u sing Q uiet Mode, thi s bit s hould be set to 1 (Con tin uous Mo de) for

at least one frame after coming out of reset before switching back to Quiet

Mode. Failure to do so will result in the ICH8 not recognizing SERIRQ interrupts.

5:2 Serial IRQ Frame Size (SIRQSZ) — RO. Fixed field that indicates the size of the

SERIRQ frame as 21 frames.

1:0

Start Frame Pulse Width (SFPW) — R/W. This is the number of PCI clocks that the

SERIRQ pin will be driven low by the serial IRQ machine to signal a start frame. In

continuous mode, the ICH8 will drive the start fr ame for the number of cloc ks specifie d.

In quiet mode, the ICH8 will drive the start frame for the number of clocks specified

minus one, as the first clock was driven by the peripheral.

00 = 4 clocks

01 = 6 clocks

10 = 8 clocks

11 = Reserved

LPC Interface Bridge Registers (D31:F 0)

332 Intel® ICH8 Family Datasheet

9.1.18 PIRQ[n]_ROUT—PIRQ[E,F,G,H] Routing Control Register

(LPC I/F—D31:F0)

Offset Address: PIRQE – 68h, PIRQF – 69h, Attribute: R/W

PIRQG – 6Ah, PIRQH – 6Bh

Default Value: 80h Size: 8 bit

Lockable: No Power Well: Core

Bit Description

Interrupt Routing Enable (IRQEN) — R/W.

0 = The corresponding PIRQ is routed to one of the ISA-compatible interrupts specified

in bits[3:0].

1 = The PIRQ is not routed to the 8259.

NOTE: BIOS must program this bit to 0 during POST for any of the PIRQs that are

being used. The value of this bit may subsequently be changed by the OS when

setting up for I/O APIC interrupt delivery mode.

6:4 Reserved

3:0

IRQ Routing — R/W. (ISA compatible.)

Value IRQ Value IRQ

0000b Reserved 1000b Reserved

0001b Reserved 1001b IRQ9

0010b Reserved 1010b IRQ10

0011b IRQ3 1011b IRQ11

0100b IRQ4 1100b IRQ12

0101b IRQ5 1101b Reserved

0110b IRQ6 1110b IRQ14

0111b IRQ7 1111b IRQ15

Intel® ICH8 Family Datasheet 333

LPC Interface Bridge Registers (D31:F0)

9.1.19 LPC_I/O_DEC—I/O Decode Ranges Register

(LPC I/F—D31:F0)

Offset Address: 80h Attribute: R/W

Default Value: 0000h Size: 16 bit

Bit Description

15:13 Reserved

12 FDD Decode Range — R/W. Determines which range to decode for the FDD Port

0 = 3F0h – 3F5h, 3F7h (Primary)

1 = 370h – 375h, 377h (Secondary)

11:10 Reserved

9:8

LPT Decode Range — R/W. This field determines which range to decode for the LPT

Port.

00 = 378h – 37Fh and 778h – 77Fh

01 = 278h – 27Fh (port 279h is read only) and 678h – 67Fh

10 = 3BCh –3BEh and 7BCh – 7BEh

11 = Reserved

7Reserved

6:4

COMB Decode Rang e — R/W. This field determines which range to decode for the

COMB Port.

000 = 3F8h – 3FFh (COM1)

001 = 2F8h – 2FFh (COM2)

010 = 220h – 227h

011 = 228h – 22Fh

100 = 238h – 23Fh

101 = 2E8h – 2EFh (COM4)

110 = 338h – 33Fh

111 = 3E8h – 3EFh (COM3)

3Reserved

2:0

COMA Decode Range — R/W. This field determines which range to decode for the

COMA Port.

000 = 3F8h – 3FFh (COM1)

001 = 2F8h – 2FFh (COM2)

010 = 220h – 227h

011 = 228h – 22Fh

100 = 238h – 23Fh

101 = 2E8h – 2EFh (COM4)

110 = 338h – 33Fh

111 = 3E8h – 3EFh (COM3)

LPC Interface Bridge Registers (D31:F 0)

334 Intel® ICH8 Family Datasheet

9.1.20 LPC_EN—LPC I/F Enables Register (LPC I/F—D31:F0)

Offset Address: 82h – 83h Attribute: R/W

Default Value: 0000h Size: 16 bit

Power Well: Core

Bit Description

15:14 Reserved

CNF2_LPC_EN — R/W. Microcontroller Enable # 2.

0 = Disable.

1 = Enables the decoding of the I/O locations 4Eh and 4Fh to the LPC interface. This

range is used for a microcontroller.

CNF1_LPC_EN — R/W. Super I/O Enable.

0 = Disable.

1 = Enables the decoding of the I/O locations 2Eh and 2Fh to the LPC interface. This

range is used for Super I/O devices.

MC_LPC_EN — R/W. Microcontroller Enable # 1.

0 = Disable.

1 = Enables the decoding of the I/O locations 62h and 66h to the LPC interface. This

range is used for a microcontroller.

KBC_LPC_EN — R/W. Keyboard Enable.

0 = Disable.

1 = Enables the decoding of the I/O locations 60h and 64h to the LPC interface. This

range is used for a microcontroller.

GAMEH_LPC_EN — R/W. High Gameport Enable

0 = Disable.

1 = Enables the decoding of the I/O locations 208h to 20Fh to the LPC interface. This

range is used for a gameport.

GAMEL_LPC_EN — R/W. Low Gameport Enable

0 = Disable.

1 = Enables the decoding of the I/O locations 200h to 207h to the LPC interface. This

range is used for a gameport.

7:4 Reserved

FDD_LPC_EN — R/W. Floppy Drive Enable

0 = Disable.

1 = Enables the decoding of the FDD ra nge to the LPC inte rface. This r ange is selected

in the LPC_FDD/LPT Decode Range Register (D31:F0:80h, bit 12).

LPT_LPC_EN — R/W. Parallel Port Enable

0 = Disable.

1 = Enables the decoding of the LPTrange to the LPC interf ace. This range is select ed in

the LPC_FDD/LPT Decode Range Register (D31:F0:80h, bit 9:8).

COMB_LPC_EN — R/W. Com Port B Enable

0 = Disable.

1 = Enables the decoding of the COMB range to the LPC interface. This range is

selected in the LPC_COM Decode Range Register (D31:F0:80h, bit s 6:4) .

COMA_LPC_EN — R/W. Com Port A Enable

0 = Disable.

1 = Enables the decoding of the COMA range to the LPC interface. This range is

selected in the LPC_COM Decode Range Register (D31:F0:80h, bit s 3:2) .

Intel® ICH8 Family Datasheet 335

LPC Interface Bridge Registers (D31:F0)

9.1.21 GEN1_DEC—LPC I/F Generic Decode Range 1 Register

(LPC I/F—D31:F0)

Offset Address: 84h – 87h Attribute: R/W

Default Value: 00000000h Size: 32 bit

Power Well: Core

9.1.22 GEN2_DEC—LPC I/F Generic Decode Range 2Register

(LPC I/F—D31:F0)

Offset Address: 88h – 8Bh Attribute: R/W

Default Value: 00000000h Size: 32 bit

Power Well: Core

Bit Description

31:24 Reserved

23:18

Generic I/O Decode Range Address[7:2] Mask: A ‘1’ in any bit position indicates

that any value in the corresponding address bit in a received cycle will be treated as a

match. The corresponding bit in the Address field, below, is ignored. The mask is only

provided for the lower 6 bits of the DWord address, allowing for decoding blocks up to

256 bytes in size.

17:16 Reserved

15:2 Generic I/O Decode Range 1 Base Address (GEN1_BASE) — R/W. This address is

aligned on a 128-byte boundary, and must have address lines 31:16 as 0.

NOTE: The ICH8 Does not provide decode down to the word or byte level

1Reserved

0Generic Decode Range 1 Enable (GEN1_EN) — R/W.

0 = Disable.

1 = Enable the GEN1 I/O range to be forwarded to the LPC I/F

Bit Description

31:24 Reserved

23:18

Generic I/O Decode Range Address[7:2] Mask: A ‘1’ in any bit position indicates

that any value in the corresponding address bit in a received cycle will be treated as a

match. The corresponding bit in the Address field, below, is ignored. The mask is only

provided for the lower 6 bits of the DWord address, allowing for decoding blocks up to

256 bytes in size.

17:16 Reserved

15:2 Generic I/O Decode Range 2Base Address (GEN1_BASE) — R/W.

NOTE: The ICH8 Does not provide decode down to the word or byte level

1Reserved

0Generic Decode Range 2Enable (GEN2_EN) — R/W.

0 = Disable.

1 = Enable the GEN2 I/O range to be forwarded to the LPC I/F

LPC Interface Bridge Registers (D31:F 0)

336 Intel® ICH8 Family Datasheet

9.1.23 GEN3_DEC—LPC I/F Generic Decode Range 3Register

(LPC I/F—D31:F0)

Offset Address: 8Ch – 8Eh Attribute: R/W

Default Value: 00000000h Size: 32 bit

Power Well: Core

9.1.24 GEN4_DEC—LPC I/F Generic Decode Range 4Register

(LPC I/F—D31:F0)

Offset Address: 90h – 93h Attribute: R/W

Default Value: 00000000h Size: 32 bit

Power Well: Core

Bit Description

31:24 Reserved

23:18

Generic I/O Decode Range Address[7:2] Mask: A ‘1’ in any bit position indicates

that any value in the corresponding address bit in a received cycle will be treated as a

match. The corresponding bit in the Address field, below, is ignored. The mask is only

provided for the lower 6 bits of the DWord address, allowing for decoding blocks up to

256 bytes in size.

17:16 Reserved

15:2 Generic I/O Decode Range 3Base Ad dress (GEN3_BASE) — R/W.

NOTE: The ICH8 Does not provide decode down to the word or byte level

1 Reserved

0Generic Decode Range 3Enable (GEN3_EN) — R/W.

0 = Disable.

1 = Enable the GEN3 I/O range to be forwarded to the LPC I/F

Bit Description

31:24 Reserved

23:18

Generic I/O Decode Range Address[7:2] Mask: A 1 in any bit position indicates

that any value in the corresponding address bit in a received cycle will be treated as a

match. The corresponding bit in the Address field, below, is ignored. The mask is only

provided for the lower 6 bits of the DWord address, allowing for decoding blocks up to

256 bytes in size.

17:16 Reserved

15:2 Generic I/O Decode Range 4Base Ad dress (GEN4_BASE) — R/W.

NOTE: The ICH8 Does not provide decode down to the word or byte level

1 Reserved

0Generic Decode Range 4Enable (GEN4_EN) — R/W.

0 = Disable.

1 = Enable the GEN4 I/O range to be forwarded to the LPC I/F

Intel® ICH8 Family Datasheet 337

LPC Interface Bridge Registers (D31:F0)

9.1.25 FWH_SEL1—Firmware Hub Select 1 Register

(LPC I/F—D31:F0)

Offset Address: D0h–D3h Attribute: R/W, RO

Default Value: 00112233h Size: 32 bits

Bit Description

31:28

FWH_F8_IDSEL — RO . IDSEL for two 512-KB Firm w are Hub me mory ra nges and one

128-KB memory range. This field is fixed at 0000. The IDSEL programmed in this field

addresses the following memory ranges:

FFF8 0000h – FFFF FFFFh

FFB8 0000h – FFBF FFFFh

000E 0000h – 000F FFFFh

27:24

FWH_F0_IDSEL — R/W. IDSEL for two 512-KB Firmware Hub memory ranges. The

IDSEL programmed in this field addresse s th e fo llo win g memory ranges:

FFF0 0000h – FFF7 FFFFh

FFB0 0000h – FFB7 FFFFh

23:20

FWH_E8_IDSEL — R/W. IDSEL for two 512-KB Firmware Hub memory ranges. The

IDSEL programmed in this field addresse s th e fo llo win g memory ranges:

FFE8 0000h – FFEF FFFFh

FFA8 0000h – FFAF FFFFh

19:16

FWH_E0_IDSEL — R/W. IDSEL for two 512-KB Firmware Hub memory ranges. The

IDSEL programmed in this field addresse s th e fo llo win g memory ranges:

FFE0 0000h – FFE7 FFFFh

FFA0 0000h – FFA7 FFFFh

15:12

FWH_D8_IDSEL — R/W. IDSEL for two 512-KB Firmware Hub memory ranges. The

IDSEL programmed in this field addresse s th e fo llo win g memory ranges:

FFD8 0000h – FFDF FFFFh

FF98 0000h – FF9F FFFFh

11:8

FWH_D0_IDSEL — R/W. IDSEL for two 512-KB Firmware Hub memory ranges. The

IDSEL programmed in this field addresse s th e fo llo win g memory ranges:

FFD0 0000h – FFD7 FFFFh

FF90 0000h – FF97 FFFFh

7:4

FWH_C8_IDSEL — R/W. IDSEL for two 512-KB Firmware Hub memory ranges. The

IDSEL programmed in this field addresse s th e fo llo win g memory ranges:

FFC8 0000h – FFCF FFFFh

FF88 0000h – FF8F FFFFh

3:0

FWH_C0_IDSEL — R/W. IDSEL for two 512-KB Firmware Hub memory ranges. The

IDSEL programmed in this field addresse s th e fo llo win g memory ranges:

FFC0 0000h – FFC7 FFFFh

FF80 0000h – FF87 FFFFh

LPC Interface Bridge Registers (D31:F 0)

338 Intel® ICH8 Family Datasheet

9.1.26 FWH_SEL2—Firmware Hub Select 2 Register

(LPC I/F—D31:F0)

Offset Address: D4h–D5h Attribute: R/W

Default Value: 4567h Size: 16 bits

9.1.27 FWH_DEC_EN1—Firmware Hub Decode Enable Re gister

(LPC I/F—D31:F0)

Offset Address: D8h–D9h Attribute: R/W, RO

Default Value: FFCFh Size: 16 bits

Bit Description

15:12

FWH_70_IDSEL — R/W. IDSEL for two, 1-M Firmware Hub memory ranges.

The IDSEL programmed in this field addresses the following memory ranges:

FF70 0000h – FF7F FFFFh

FF30 0000h – FF3F FFFFh

11:8

FWH_60_IDSEL — R/W. IDSEL for two, 1-M Firmware Hub memory ranges.

The IDSEL programmed in this field addresses the following memory ranges:

FF60 0000h – FF6F FFFFh

FF20 0000h – FF2F FFFFh

7:4

FWH_50_IDSEL — R/W. IDSEL for two, 1-M Firmware Hub memory ranges.

The IDSEL programmed in this field addresses the following memory ranges:

FF50 0000h – FF5F FFFFh

FF10 0000h – FF1F FFFFh

3:0

FWH_40_IDSEL — R/W. IDSEL for two, 1-M Firmware Hub memory ranges.

The IDSEL programmed in this field addresses the following memory ranges:

FF40 0000h – FF4F FFFFh

FF00 0000h – FF0F FFFFh

Bit Description

FWH_F8_EN — RO. This bit enables decoding two 512-KB Firmware Hub memory

ranges, and one 128-KB memory range.

0 = Disable

1 = Enable the following ranges for the Firmware Hub

FFF80000h – FFFFFFFFh

FFB80000h – FFBFFFFFh

FWH_F0_EN — R/W. This bit enables decoding two 512-KB Firmware Hub memory

ranges.

0 = Disable.

1 = Enable the following ranges for the Firmware Hub:

FFF00000h – FFF7FFFFh

FFB00000h – FFB7FFFFh

FWH_E8_EN — R/W. This bit enables decoding two 512-KB Firmware Hub memory

ranges.

0 = Disable.

1 = Enable the following ranges for the Firmware Hub:

FFE80000h – FFEFFFFh

FFA80000h – FFAFFFFFh

Intel® ICH8 Family Datasheet 339

LPC Interface Bridge Registers (D31:F0)

FWH_E0_EN — R/W. This bit enables decoding two 512-KB Firmware Hub memory

ranges.

0 = Disable.

1 = Enable the following ranges for the Firmware Hub:

FFE00000h – FFE7FFFFh

FFA00000h – FFA7FFFFh

FWH_D8_EN — R/W. This bit enables decoding two 512-KB Firmware Hub memory

ranges.

0 = Disable.

1 = Enable the following ranges for the Firmware Hub

FFD80000h – FFDFFFFFh

FF980000h – FF9FFFFFh

FWH_D0_EN — R/W. This bit enables decoding two 512-KB Firmware Hub memory

ranges.

0 = Disable.

1 = Enable the following ranges for the Firmware Hub

FFD00000h – FFD7FFFFh

FF900000h – FF97FFFFh

FWH_C8_EN — R/W. This bit enables decoding two 512-KB Firmware Hub memory

ranges.

0 = Disable.

1 = Enable the following ranges for the Firmware Hub

FFC80000h – FFCFFFFFh

FF880000h – FF8FFFFFh

FWH_C0_EN — R/W. This bit enables decoding two 512-KB Firmware Hub memory

ranges.

0 = Disable.

1 = Enable the following ranges for the Firmware Hub

FFC00000h – FFC7FFFFh

FF800000h – FF87FFFFh

FWH_Legacy_F_EN — R/W. This enables the decoding of the legacy 128-K range at

F0000h – FFFFFh.

0 = Disable.

1 = Enable the following legacy ranges for the Firmware Hub

F0000h – FFFFFh

FWH_Legacy_E_EN — R/W. This enables the decoding of the legacy 128-K range at

E0000h – EFFFFh.

0 = Disable.

1 = Enable the following legacy ranges for the Firmware Hub

E0000h – EFFFFh

5:4 Reserved

FWH_70_EN — R/W. Enables decoding two 1-M Firmware Hub memory ranges.

0 = Disable.

1 = Enable the following ranges for the Firmware Hub

FF70 0000h – FF7F FFFFh

FF30 0000h – FF3F FFFFh

Bit Description

LPC Interface Bridge Registers (D31:F 0)

340 Intel® ICH8 Family Datasheet

Note: This register effects the BIOS decode regardless of whether the BIOS is resident on LPC

or SPI. The concept of Feature Space does not apply to SPI-based flash. The ICH8

simply decodes these ranges as memory accesses when enabled for the SPI flash

interface.

FWH_60_EN — R/W. Enables decoding two 1-M Firmware Hub memory ranges.

0 = Disable.

1 = Enable the following ranges for the Firmware Hub

FF60 0000h – FF6F FFFFh

FF20 0000h – FF2F FFFFh

FWH_50_EN — R/W. Enables decoding two 1-M Firmware Hub memory ranges.

0 = Disable.

1 = Enable the following ranges for the Firmware Hub

FF50 0000h – FF5F FFFFh

FF10 0000h – FF1F FFFFh

FWH_40_EN — R/W. Enables decoding two 1-M Firmware Hub memory ranges.

0 = Disable.

1 = Enable the following ranges for the Firmware Hub

FF40 0000h – FF4F FFFFh

FF00 0000h – FF0F FFFFh

Bit Description

Intel® ICH8 Family Datasheet 341

LPC Interface Bridge Registers (D31:F0)

9.1.28 BIOS_CNTL—BIOS Control Register

(LPC I/F—D31:F0)

Offset Address: DCh Attribute: R/WLO, R/W, RO

Default Value: 00h Size: 8 bit

Lockable: No Power Well: Core

9.1.29 FDCAP—Feature Detection Capability ID

(LPC I/F—D31:F0)

Offset Address: E0h-E1h Attribute: RO

Default Value: 0000h Size: 16 bit

Power Well: Core

Bit Description

7:5 Reserved

4Top Swap Status (TSS)— RO: Th is bit pro vide s a read-only path to view the st ate of

the Top Swap bit that is at offset 3414h, bit 0.

3:2

SPI Read Configuration (SRC)— R/W : This 2-bit field c ontrols two poli cies related to

BIOS reads on the SPI interface:

Bit 3- Prefetch Enable

Bit 2- Cache Disable

Settings are summarized below:

BIOS Lock Enable (BLE) — R/WLO.

0 = Setting the BI OSWE will not cause SMIs.

1 = Enables setting the BIOSWE bit to cause SMIs. Once set, this bit can onl y be

cleared by a PLTRST#

BIOS Write Enable (BIOSWE) — R/W.

0 = Only read cycles result in Firmware Hub I/F cycles.

1 = Access to the BIOS space is enabled for both read and write cycles. When this bit is

written from a 0 to a 1 and BIOS Lock Enable (BLE) is also set, an SMI# is

generated. This ensures that only SMI code can update BIOS.

Bits 3:2 Description

00b No prefetching, but caching enabled. 64B demand reads load

the read buffer cache with “valid” data, allowing repeated code

fetches to the same line to complete quickly

01b No prefetching and no caching. One-to-one correspondence of

host BIOS reads to SPI cycles. This value can be used to invalidate

the cache.

10b Prefetching and Caching enabled. This mode is used for long

sequences o f short reads to consecut ive addres ses (i.e., shadowing).

11b Reserved. This is an inv a li d configuration , caching must be

enabled when prefetching is enabled.

Bit Description

15:8 Next Item Pointer (NEXT): Configuration offset of the next Capability Item. 00h

indicates the last item in the Capability List.

7:0 Capability ID: Indicates a Vendor Specific Capability

LPC Interface Bridge Registers (D31:F 0)

342 Intel® ICH8 Family Datasheet

9.1.30 FDLEN—Feature Detection Capability Length

(LPC I/F—D31:F0)

Offset Address: E2h Attribute: RO

Default Value: 0Ch Size: 8 bit

Power Well: Core

9.1.31 FDVER—Feature Detection Version

(LPC I/F—D31:F0)

Offset Address: E3h Attribute: RO

Default Value: 10h Size: 8 bit

Power Well: Core

9.1.32 FDVCT—Feature Vector

(LPC I/F—D31:F0)

Offset Address: E4h-EBh Attribute: RO

Default Value: See Description Size: 64 bit

Power Well: Core

Bit Description

7:0 Capability Length: Indicates the length of this Vendor Specific capability , as required by

PCI Spec.

Bit Description

7:4 Vendor-Specific Capability ID: A value of 1h in this 4-bit field identifies this Capability

as Feature Detection Type. This field allows software to differentiate the Feature

Detection Capability from other Vendor-Specific capabilities

3:0 Capability Version: This field indicates the version of the Feature Detection capability

Bit Description

63:40 Reserved

(ICH8DH

Only)

Quick Resume Technology Capability— RO:

0 = Capable

1 = Disabled

(ICH8

Base,

ICH8R,

ICH8DO,

Mobile

Only)

Reserved

38:19 Reserved

18 SATA RAID 5 Capability— RO:

0 = Capable

1 = Disabled

17:10 Reserved

Intel® ICH8 Family Datasheet 343

LPC Interface Bridge Registers (D31:F0)

9.1.33 RCBA—Root Complex Base Address Register

(LPC I/F—D31:F0)

Offset Address: F0h Attribute: R/W

Default Value: 00000000h Size: 32 bit

(Mobile

Only)

Mobile Features Capability— RO:

0 = Disabled

1 = Capable

(Desktop

Only) Reserved

8 Reserved

7PCI Express* 6 x1 Capability— RO:

0 = Capable

1 = Disabled – 4 PCI Express x1 Ports available

6 Reserved

5SATA RAID 0/1/10 Capability— RO:

0 = Capable

1 = Disabled

4 Reserved

3SATA AHCI Capability— RO:

0 = Capable

1 = Disabled

2:0 Reserved

Bit Description

31:14 Base Address (BA) — R/W. Base Address for the root complex register block decode

range. This address is aligned on a 16-KB boundary.

13:1 Reserved

0Enable (EN) — R/W. When set, enables the range specified in BA to be claimed as the

Root Complex Register Block.

LPC Interface Bridge Registers (D31:F 0)

344 Intel® ICH8 Family Datasheet

9.2 DMA I/O Registers (LPC I/F—D31:F0)

Table 106. DMA Registers (Sheet 1 of 2)

Port Alias Register Name Default Type

00h 10h Channel 0 DMA Base & Current Address Undefined R/W

01h 11h Channel 0 DMA Base & Current Count Undefined R/W

02h 12h Channel 1 DMA Base & Current Address Undefined R/W

03h 13h Channel 1 DMA Base & Current Count Undefined R/W

04h 14h Channel 2 DMA Base & Current Address Undefined R/W

05h 15h Channel 2 DMA Base & Current Count Undefined R/W

06h 16h Channel 3 DMA Base & Current Address Undefined R/W

07h 17h Channel 3 DMA Base & Current Count Undefined R/W

08h 18h Channel 0–3 DMA Command Undefined WO

Channel 0–3 DMA Status Undefined RO

0Ah 1Ah Channel 0–3 DMA Write Single Mask 000001XXb WO

0Bh 1Bh Channel 0–3 DMA Channel Mode 000000XXb WO

0Ch 1Ch Channel 0–3 DMA Clear Byte Pointer Undefined WO

0Dh 1Dh Channel 0–3 DMA Master Clear Undefined WO

0Eh 1Eh Channel 0–3 DMA Clear Mask Undefined WO

0Fh 1Fh Channel 0–3 DMA Write All Mask 0Fh R/W

80h 90h Reserved Page Undefined R/W

81h 91h Channel 2 DMA Memory Low Page Undefined R/W

82h — Channel 3 DMA Memory Low Page Undefined R/W

83h 93h Channel 1 DMA Memory Low Page Undefined R/W

84h–86h 94h–96h Reserve d Pages Undefined R/W

87h 97h Channel 0 DMA Memory Low Page Undefined R/W

88h 98h Reserved Page Undefined R/W

89h 99h Channel 6 DMA Memory Low Page Undefined R/W

8Ah 9Ah Channel 7 DMA Memory Low Page Undefined R/W

8Bh 9Bh Channel 5 DMA Memory Low Page Undefined R/W

8Ch–8Eh 9Ch–9Eh Re served Page Undefined R/W

8Fh 9Fh Refresh Low Page Undefined R/W

C0h C1h Channel 4 DMA Base & Current Address Undefined R/W

C2h C3h Channel 4 DMA Base & Current Count Undefined R/W

C4h C5h Channel 5 DMA Base & Current Address Undefined R/W

C6h C7h Channel 5 DMA Base & Current Count Undefined R/W

C8h C9h Channel 6 DMA Base & Current Address Undefined R/W

CAh CBh Channel 6 DMA Base & Current Count Undefined R/W

CCh CDh Channel 7 DMA Base & Current Address Undefined R/W

Intel® ICH8 Family Datasheet 345

LPC Interface Bridge Registers (D31:F0)

9.2.1 DMABASE_CA—DMA Base and Current Address

Registers (LPC I/F—D31:F0)

I/O Address: Ch. #0 = 00h; Ch. #1 = 02h Attribute: R/W

Ch. #2 = 04h; Ch. #3 = 06h Size: 16 bit (per channel),

Ch. #5 = C4h Ch. #6 = C8h but accessed in two 8-bit

Ch. #7 = CCh; quantities

Default Value: Undef

Lockable: No Power Well: Core

CEh CFh Channel 7 DMA Base & Current Count Undefined R/W

D0h D1h Channel 4–7 DMA Command Undefined WO

Channel 4–7 DMA Status Undefined RO

D4h D5h

Channel 4–7 DMA Write Single Mask 000001XXb WO

D6h D7h Channel 4–7 DMA Channel Mode 000000XXb WO

D8h D9h Channel 4–7 DMA Clear Byte Pointer Undefined WO

DAh DBh Channel 4–7 DMA Master Clear Undefined WO

DCh DDh Channel 4–7 DMA Clear Mask Undefined WO

DEh DFh Channel 4–7 DMA Write All Mask 0Fh R/W

Table 106. DMA Registers (Sheet 2 of 2)

Port Alias Register Name Default Type

Bit Description

15:0

Base and Current Address — R/W. This register determines the address for the

transfers to be performed. The address specified points to two separate registers. On

writes, the value is stored in the Base Address register and copied to the Current

Address register. On reads, the value is returned from the Current Address register.

The address i ncrements/decrement s in the Current Address re gister after each tr ansfer,

depending on the mode of the transfer. If the channel is in auto-initialize mode, the

Current Address register will be reloaded from the Base Address register after a

terminal count is generated.

For transfers to/from a 16-bit slave (channel’s 5-7), the address is shifted left one bit

location. Bit 15 will be shifted into Bit 16 .

The register is accessed in 8 bit quantities. The byte is pointed to by the current byte

pointer flip/flop. Before accessing an address register, the byte po inter flip/f lop should

be cleared to ensure that the low byte is accessed first

LPC Interface Bridge Registers (D31:F 0)

346 Intel® ICH8 Family Datasheet

9.2.2 DMABASE_CC—DMA Base and Current Count Registers

(LPC I/F—D31:F0)

I/O Address: Ch. #0 = 01h; Ch. #1 = 03h Attribute: R/W

Ch. #2 = 05h; Ch. #3 = 07h Size: 16-bit (per channel),

Ch. #5 = C6h; Ch. #6 = CAh but accessed in two 8-bit

Ch. #7 = CEh; quantities

Default Value: Undefined

Lockable: No Power Well: Core

9.2.3 DMAMEM_LP—DMA Memory Low Page Registers

(LPC I/F—D31:F0)

I/O Address: Ch. #0 = 87h; Ch. #1 = 83h

Ch. #2 = 81h; Ch. #3 = 82h

Ch. #5 = 8Bh; Ch. #6 = 89h

Ch. #7 = 8Ah; Attribute: R/W

Default Value: Undefined Size: 8-bit

Lockable: No Power Well: Core

Bit Description

15:0

Base and Current Count — R/W. This register determines the number of transfers to

be performed. The address specified points to two separate registers. On writes, the

value is store d in the Base Count register and copied to the Current Count register. On

reads, the value is returned from the Current Count register.

The actual number of transfers is one more than the n umber programmed in the Base

Count Register (i.e., programming a count of 4h results in 5 transfers). The count is

decrements in the Current Count register after each transfer. When the value in the

initialize mode, the Current Count register will be reloaded from the Base Count

For transfers to/from an 8-bit slave (channels 0–3), the c ount register indica tes the

number of bytes to be transferred. For transfers to/from a 16-bit slave (channels 5–7),

the count regist er indicates the number of words to be transferred.

The register is accessed in 8 bit quantities. The byte is pointed to by the current byte

pointer flip/flop. Before accessing a count register, the byte pointer flip/flop should be

cleared to ensure that the low byte is accessed first.

Bit Description

7:0

DMA Low Page (ISA Address bits [23:16]) — R/W. This register works in conjunction

with the DMA controller's Current Address Register to define the complete 24-bit

address for the DMA channel. Thi s register remain s static throughou t the DMA trans fer.

Bit 16 of this register is ignored when in 16 bit I/O count by words mode as it is

replaced by the bit 15 shifted out from the current address register.

Intel® ICH8 Family Datasheet 347

LPC Interface Bridge Registers (D31:F0)

9.2.4 DMACMD—DMA Command Register (LPC I/F—D31:F0)

I/O Address: Ch. #0–3 = 08h;

Ch. #4–7 = D0h Attribute: WO

Default Value: Undefined Size: 8-bit

Lockable: No Power Well: Core

9.2.5 DMASTA—DMA Status Register (LPC I/F—D31:F0)

I/O Address: Ch. #0–3 = 08h;

Ch. #4–7 = D0h Attribute: RO

Default Value: Undefined Size: 8-bit

Lockable: No Power Well: Core

Bit Description

7:5 Reserved. Must be 0.

DMA Group Arbitration Priority — WO. Each channel group is individually assigned

either fixed or rotating arbitration priority. At part reset, each group is initialized in

fixed priority.

0 = Fixed priority to the channel group

1 = Rotating priority to the group.

3 Reserved. Must be 0.

DMA Channel Group Enable — WO. Both channel groups are enabled following part

reset.

0 = Enable the DMA channel group.

1 = Disable. Disabling channel group 4–7 also disables channel group 0–3, which is

cascaded through channel 4.

1:0 Reserved. Must be 0.

Bit Description

7:4

Channel Request Status — RO. When a valid DMA request is pending for a channel,

the corresponding bit is set to 1. When a DMA request is not pending for a particular

channel, the corresponding bit is set to 0. The source of the DREQ may be hardware or

a software request. Note that channel 4 is the cascade channel, so the request status of

channel 4 is a lo gical OR of the r equest status for channels 0 through 3.

4 = Channel 0

5 = Channel 1 (5)

6 = Channel 2 (6)

7 = Channel 3 (7)

3:0

Channel Terminal Count Status — RO. When a channel reaches terminal count (TC),

its status bit is set to 1. If TC has not been reached, the status bit is set to 0. Channel 4

is programmed for cascade, so the TC bit response for channel 4 is irrelevant:

0 = Channel 0

1 = Channel 1 (5)

2 = Channel 2 (6)

3 = Channel 3 (7)

LPC Interface Bridge Registers (D31:F 0)

348 Intel® ICH8 Family Datasheet

9.2.6 DMA_WRSMSK—DMA Write Single Mask Register

(LPC I/F—D31:F0)

I/O Address: Ch. #0–3 = 0Ah;

Ch. #4–7 = D4h Attribute: WO

Default Value: 0000 01xx Size: 8-bit

Lockable: No Power Well: Core

Bit Description

7:3 Reserved. Must be 0.

Channel Mask Select — WO.

0 = Enable DREQ for the selected channel. The channel is selected through bits [1:0].

Therefore, only one channel can be masked / unmasked at a time.

1 = Disable DREQ for the selected channel.

1:0

DMA Channel Select — WO. These bits select the DMA Channel Mode Register to

program.

00 = Channel 0 (4)

01 = Channel 1 (5)

10 = Channel 2 (6)

11 = Channel 3 (7)

Intel® ICH8 Family Datasheet 349

LPC Interface Bridge Registers (D31:F0)

9.2.7 DMACH_MODE—DMA Channel Mode Register

(LPC I/F—D31:F0)

I/O Address: Ch. #0–3 = 0Bh;

Ch. #4–7 = D6h Attribute: WO

Default Value: 0000 00xx Size: 8-bit

Lockable: No Power Well: Core

Bit Description

7:6

DMA Transfer Mode — WO. Each DMA channel can be programmed in one of four

different modes:

00 = Demand mode

01 = Single mode

10 = Reserved

11 = Cascade mode

Address Increment/Decrement Select — WO. This bit controls address increment/

decrement during DMA t ransfers.

0 = Address incremen t. (default after part reset or Master Clear)

1 = Address decrement.

Autoinitialize Enable — WO.

0 = Autoinitialize feature is disabled and DMA transfers terminate on a terminal count.

A part reset or Master Clear disables autoinitialization.

1 = DMA restores the Base Address and Count registers to the current registers

following a terminal count (TC).

3:2

DMA Transfer Type — WO. These bits represent the di rection of the DMA transfer.

When the channel is progr ammed for cascade mode , (bits[7 :6] = 11) the tr ans fer type

is irrelevant.

00 = Verify – No I/O or memory strobes generated

01 = Write – Data transferred from the I/O devices to memory

10 = Read – Data transferred from memory to the I/O device

11 = Invalid

1:0

DMA Channel Select — WO. These bits select the DMA Channel Mode Register that

will be written by bits [7:2].

00 = Channel 0 (4)

01 = Channel 1 (5)

10 = Channel 2 (6)

11 = Channel 3 (7)

LPC Interface Bridge Registers (D31:F 0)

350 Intel® ICH8 Family Datasheet

9.2.8 DMA Clear Byte Pointer Register (LPC I/F—D31:F0)

I/O Address: Ch. #0–3 = 0Ch;

Ch. #4–7 = D8h Attribute: WO

Default Value: xxxx xxxx Size: 8-bit

Lockable: No Power Well: Core

9.2.9 DMA Master Clear Register (LPC I/F—D31:F0)

I/O Address: Ch. #0–3 = 0Dh;

Ch. #4–7 = DAh Attribute: WO

Default Value: xxxx xxxx Size: 8-bit

Bit Description

7:0

Clear Byte Pointer — WO. No specific pattern. Command enabled with a write to the

I/O port address. Writing to this re gister i nitiali z es the byte pointer flip/ flop to a known

state. It clears the internal latch used to address the upper or lower byte of the 16-bit

Address and Word Count Registers. The latch is also cleared by part reset and by the

Master Clear command. Thi s command precedes the first access to a 16-bit DMA

controller register. The first access to a 16-bit register will then access the significant

byte, and the second access automatically accesses the most significant byte.

Bit Description

7:0 Master Clea r — WO. No specific pattern. Enabled with a write to the port. This has the

same effect as the hardware Reset. The Command, Status, Request, and Byte Pointer

flip/flop registers are cleared and the Mask Register is set.

Intel® ICH8 Family Datasheet 351

LPC Interface Bridge Registers (D31:F0)

9.2.10 DMA_CLMSK—DMA Clear Mask Register (LPC I/F—D31:F0)

I/O Address: Ch. #0–3 = 0Eh;

Ch. #4–7 = DCh Attribute: WO

Default Value: xxxx xxxx Size: 8-bit

Lockable: No Power Well: Core

9.2.11 DMA_WRMSK—DMA Write All Mask Register

(LPC I/F—D31:F0)

I/O Address: Ch. #0–3 = 0Fh;

Ch. #4–7 = DEh Attribute: R/W

Default Value: 0000 1111 Size: 8-bit

Lockable: No Power Well: Core

Bit Description

7:0 Clear Mask Register — WO. No specific pattern. Command enabled with a write to the

port.

Bit Description

7:4 Reserved. Must be 0.

3:0

Channel Mask Bits — R/W. This register permits all four channels to be

simultaneously enabled/disabled instead of enabli ng/disabling each channel

individually, as is the case with the Mask Register – Write Single Mask Bit. In addition,

this register has a read path to allow the status of the channel mask bits to be read. A

channel's mask bit is automatically set to 1 when the Current Byte/Word Count R egister

reaches terminal count (unless the channel is in auto-initialization mode).

Setting the bit(s) to a 1 disables the corresponding DREQ(s). Setting the bit(s) to a 0

enables the corresponding DREQ(s). Bits [3:0] are set to 1 upon part reset or Master

Clear. When read, bits [3:0] indicate the DMA channel [3:0] ([7:4]) mask status.

Bit 0 = Channel 0 (4) 1 = Masked, 0 = Not Masked

Bit 1 = Channel 1 (5) 1 = Masked, 0 = Not Masked

Bit 2 = Channel 2 (6) 1 = Masked, 0 = Not Masked

Bit 3 = Channel 3 (7) 1 = Masked, 0 = Not Masked

NOTE: Disabling channel 4 als o disables channels 0–3 due to the cascade of channel’s

0 – 3 through channel 4.

LPC Interface Bridge Registers (D31:F 0)

352 Intel® ICH8 Family Datasheet

9.3 Timer I/O Registers (LPC I/F—D31:F0)

Port Aliases Register Name Default Value Type

40h 50h Counter 0 Interval Time Status Byte

Format 0XXXXXXXb RO

Counter 0 Counter Access Port Undefined R/W

41h 51h Counter 1 Interval Time Status Byte

Format 0XXXXXXXb RO

Counter 1 Counter Access Port Undefined R/W

42h 52h Counter 2 Interval Time Status Byte

Format 0XXXXXXXb RO

Counter 2 Counter Access Port Undefined R/W

43h 53h

Timer Control Word Undefined WO

Timer Control Word Register XXXXXXX0b WO

Counter Latch Command X0h WO

Intel® ICH8 Family Datasheet 353

LPC Interface Bridge Registers (D31:F0)

9.3.1 TCW—Timer Control Word Register (LPC I/F—D31:F0)

I/O Address: 43h Attribute: WO

Default Value: All bits undefined Size: 8 bits

This register is programmed prior to any counter being accessed to specify counter

modes. Following component reset, the control words for each register are undefined

and each counter output is 0. Each timer must be programmed to bring it into a known

state.

There are two special commands that can be issued to the counters through this

commands are chosen, several bits within this register are redefined. These register

formats are described in the following sub-sections:

RDBK_CMD—Read Back Command (LPC I/F—D31:F0)

The Read Back Command is used to determine the count value, programmed mode,

and current states of the OUT pin and Null count flag of the selected counter or

counters. Status and/or count may be latched in an y or all o f the counters by selecting

the counter during the register write. The count and status remain latched until read,

and further latch commands are ignored until the count is read. Both count and status

of the selected counters may be latched simultaneously by setting both bit 5 and bit 4

Bit Description

7:6

Counter Select — WO. The Counter Selection bits select the counter the co ntrol word

acts upon as shown below. The Read Back Command is selected when bits[7:6] are

both 1.

00 = Counter 0 select

01 = Counter 1 select

10 = Counter 2 select

11 = Read Back Command

5:4

Read/Write Select — WO. These bits are the read/write control bits. The actual

counter programming is done through the counter port (40h for counter 0, 41h for

counter 1, and 42h for counter 2).

00 = Counter Latch Co mmand

01 = Read/Write Least Significant Byte (LSB)

10 = Read/Write Most Significant Byte (MSB)

11 = Read/Write LSB then MSB

3:1

Counter Mode Selection — WO. These bits select one of six possible modes of

operation for the selected counter.

0Binary/BCD Countdown Select — WO.

0 = Binary countdown is used. The largest possible binary count is 216

1 = Binary coded decimal (BCD) count is used. The largest possible BCD count is 104

Bit Value Mode

000b Mode 0 Out signal on end of count (=0)

001b Mode 1 Hardware retriggerable one-shot

x10b Mode 2 Rate generator (divide by n counter)

x11b Mode 3 Square wave output

100b Mode 4 Software triggered strobe

101b Mode 5 Hardware triggered strobe

LPC Interface Bridge Registers (D31:F 0)

354 Intel® ICH8 Family Datasheet

to 0. If both are latched, the first read operation from that counter returns the latched

status. The next one or two reads, depending on whether the counter is programmed

for one or two byte counts, returns the latched count. Subsequent reads return an

unlatched count.

LTCH_CMD—Counter Latch Command (LPC I/F—D31:F0)

The Counter Latch Command latches the current cou nt v alue. This command is used to

ensure that the count read from the counter is accurate. The count value is then read

from each counter's count register through the Counter Ports Access Ports Register

(40h for counter 0, 41h for counter 1, and 42h for counter 2). The count must be read

according to the programmed format, i.e., if the counter is programmed for two byte

counts, two bytes must be read. The two bytes do not have to be read one right after

the other (read, write, or programming operations for other counters may be inserted

between the reads). If a counter is latched once and then latched again before the

count is read, the second Counter Latch Command is ignored.

Bit Description

7:6 Read Back Command. Must be 11 to select the Read Back Command

5Latch Count of Selected Counters.

0 = Current count value of the selected counters will be latched

1 = Current count will not be latched

4Latch Status of Selected Counters.

0 = Status of the selected counters will be latched

1 = Status will not be latched

3Counter 2 Select.

1 = Counter 2 count and/or status will be latched

2Counter 1 Select.

1 = Counter 1 count and/or status will be latched

1Counter 0 Select.

1 = Counter 0 count and/or status will be latched.

0 Reserved. Must be 0.

Bit Description

7:6

Counter Selection. These bits sele ct the counter for latching. If “11” is written, then

the write is interpreted as a read back command.

00 = Counter 0

01 = Counter 1

10 = Counter 2

5:4 Counter Latch Command.

00 = Selects the Counter Latch Command.

3:0 Reserved. Must be 0.

Intel® ICH8 Family Datasheet 355

LPC Interface Bridge Registers (D31:F0)

9.3.2 SBYTE_FMT—Interval Timer Status Byte Format Register

(LPC I/F—D31:F0)

I/O Address: Counter 0 = 40h,

Counter 1 = 41h, Attribute: RO

Counter 2 = 42h Size: 8 bits per counter

Default Value: Bits[6:0] undefined, Bit 7=0

Each counter's status byte can be read following a Re ad Back Command. If latch status

is chosen (bit 4=0, Read Back Command) as a read back option for a given counter, the

next read from the counter's Counter Access Ports Register (40h for counter 0, 41h for

counter 1, and 42h for counter 2) returns the status byte. The status byte returns the

following:

Bit Description

7Counter OUT Pin State — RO.

0 = OUT pin of the counter is also a 0

1 = OUT pin of the counter is also a 1

Count Register Status — RO. This bit indicates when the last count written to the

Count Register (CR) has been loaded into the counting element (CE). The exact time

this happens depends on the counter mode, but unti l the count is lo aded into the

counting elemen t (CE), the count value will be incorrect.

0 = Count has been transferred from CR to CE and is available for reading.

1 = Null Count. Count has not been transferred from CR to CE and is not yet available

for reading.

5:4

Read/Write Selection Status — RO. These reflect the read/write selection made

through bits[5:4] of the control register. The binary codes returned during the status

read match the co des used to program the counter read/write selection.

00 = Counter Latch Co mmand

01 = Read/Write Least Significant Byte (LSB)

10 = Read/Write Most Significant Byte (MSB)

11 = Read/Write LSB then MSB

3:1

Mode Selection Status — RO. These bits return the counter mode programming. The

binary code returned matches the code used to program the counter mode, as listed

under the bit function above.

000 = Mode 0 — Out signal on end of count (=0)

001 = Mode 1 — Hardware retriggerable one-shot

x10 = Mode 2 — Rate generator (divide by n counter)

x11 = Mode 3 — Square wave output

100 = Mode 4 — Software triggered strobe

101 = Mode 5 — Hardware triggered strobe

0Countdown Type Status — RO. This bit reflects the current countdown type.

0 = Binary countdown

1 = Binary Coded Decimal (BCD) countdown.

LPC Interface Bridge Registers (D31:F 0)

356 Intel® ICH8 Family Datasheet

9.3.3 Counter Access Ports Register (LPC I/F—D31:F0)

I/O Address: Counter 0 – 40h,

Counter 1 – 41h, Attribute: R/W

Counter 2 – 42h

Default Value: All bits undefined Size: 8 bit

9.4 8259 Interrupt Controller (PIC) Registers

(LPC I/F—D31:F0)

9.4.1 Interrupt Controller I/O MAP (LPC I/F—D31:F0)

The interrupt controller registers are located at 20h and 21h for the master controller

(IRQ 0–7), and at A0h and A1h for the slave controller (IRQ 8–13). These registers

have multiple functions, depending upon the data written to them. Table 107 shows the

different register possibilities for each address.

Note: Refer to note addressing active-low interrupt sources in 8259 Interrupt Controllers

section (Chapter 5.8).

Bit Description

7:0

Counter Port — R/W. Each counter port address is used to program the 16-bit Count

defined with the Interval Counter Control Register at port 43h. The counter port is also

used to read the current count from the Count Register, and return the status of the

counter programming following a Read Back Command.

Table 107. PIC Registers (LPC I/F—D31:F0)

Port Aliases Register Name Default

Value Type

20h 24h, 28h,

2Ch, 30h,

34h, 38h, 3Ch

Master PIC ICW1 Init. Cmd Word 1 Undefined WO

Master PIC OCW2 Op Ctrl Word 2 001XXXXXb WO

Master PIC OCW3 Op Ctrl Word 3 X01XXX10b WO

21h

25h, 29h,

2Dh, 31h,

35h, 39h,

3Dh

Master PIC ICW2 Init. Cmd Word 2 Undefined WO

Master PIC ICW3 Init. Cmd Word 3 Undefined WO

Master PIC ICW4 Init. Cmd Word 4 01h WO

Master PIC OCW1 Op Ctrl Word 1 00h R/W

A0h

A4h, A8h,

ACh, B0h,

B4h, B8h,

BCh

Slave PIC ICW1 Init. Cmd Word 1 Undefined WO

Slave PIC OCW2 Op Ctrl Word 2 001XXXXXb WO

Slave PIC OCW3 Op Ctrl Word 3 X01XXX10b WO

A1h

A5h, A9h,

ADh, B1h,

B5h, B9h,

BDh

Slave PIC ICW2 Init. Cmd Word 2 Undefined WO

Slave PIC ICW3 Init. Cmd Word 3 Undefined WO

Slave PIC ICW4 Init. Cmd Word 4 01h WO

Slave PIC OCW1 Op Ctrl Word 1 00h R/W

4D0h – Master PIC Edge/Level Triggered 00h R/W

4D1h – Slave PIC Edge/Level Triggered 00h R/W

Intel® ICH8 Family Datasheet 357

LPC Interface Bridge Registers (D31:F0)

9.4.2 ICW1—Initialization Command Word 1 Register

(LPC I/F—D31:F0)

Offset Address: Master Controller – 20h Attribute: WO

Slave Controller

– A0h Size: 8 bit /controller

Default Value: All bits undefined

A write to Initialization Command Word 1 starts the interrupt controller initialization

sequence, during which the following occurs:

1. The Interrupt Mask register is cleared.

2. IRQ7 input is assigned priority 7.

3. The slave mode address is set to 7.

4. Special mask mode is cleared and Status Read is set to IRR.

Once this write occurs, the controller expects writes to ICW2, ICW3, and ICW4 to

complete the initialization sequence.

Bit Description

7:5 ICW/OCW Select — WO. These bits are MCS-85 specific, and not needed.

000 = Should be programmed to “000”

4ICW/OCW Select — WO.

1 = This bit must be a 1 to select ICW1 and enable the ICW2, ICW3, and ICW4

sequence.

3Edge/Level Bank Select (LTIM) — WO. Disabled. Replaced by the edge/level

triggered control registers (ELCR, D31:F0:4D0h, D31:F0:4D1h).

2ADI — WO.

0 = Ignored for the ICH8. Should be programmed to 0.

1Single or Cascade (SNGL) — WO.

0 = Must be programmed to a 0 to indicate two controllers operating in cascade mode.

0ICW4 Write Required (IC4) — WO.

1 = This bit must be programmed to a 1 to indicate that ICW4 needs t o be

programmed.

LPC Interface Bridge Registers (D31:F 0)

358 Intel® ICH8 Family Datasheet

9.4.3 ICW2—Initialization Command Word 2 Register

(LPC I/F—D31:F0)

Offset Address: Master Controller – 21h Attribute: WO

Slave Controller

– A1h Size: 8 bit /controller

Default Value: All bits undefined

ICW2 is used to initialize the interrupt controller with the five most significant bits of

the interrupt vector address. The value programmed for bits[7:3] is used by the

processor to define the base address in the interrupt vector table for the interrupt

routines associated with each IRQ on the controller. Typical ISA ICW2 values are 08h

for the master controller and 70h for the slave controller.

9.4.4 ICW3—Master Controller Initialization Command

Word 3 Register (LPC I/F—D31:F0)

Offset Address: 21h Attribute: WO

Default Value: All bits undefined Size: 8 bits

Bit Description

7:3 Interrupt Vector Base Address — WO. Bits [7:3] define the base address in the

interrupt vector table for the interrupt routines associated wit h each interrupt request

level input.

2:0

Interrupt Request Level — WO. When writing ICW2, these bits should all be 0.

During an interrupt acknowledge c ycle, these bits are programmed by the interrupt

controller with the interrupt to be serviced. This is combined with bits [7:3] to form the

interrupt vector driven onto the data bus during the second INTA# cycle. Th e c ode i s a

three bit binary code:

Code Master Interrupt Slave Interrupt

000b IRQ0 IRQ8

001b IRQ1 IRQ9

010b IRQ2 IRQ10

011b IRQ3 IRQ11

100b IRQ4 IRQ12

101b IRQ5 IRQ13

110b IRQ6 IRQ14

111b IRQ7 IRQ15

Bit Description

7:3 0 = These bits must be programmed to 0.

Cascaded Interrupt Controller IRQ Connectio n — WO. This bit indicates that the

slave controller is cascaded on IRQ2. When IRQ8#–IRQ15 is asserted, it goes through

the slave controller’s priority resolver. The slave controller’s INTR output onto IRQ2.

IRQ2 then goes through the master controller’s priority solver. If it wins, the INTR

signal is asserted to the processor, and the returning interrupt acknowledge returns the

interrupt vector for the slave controller.

1 = This bit must always be programmed to a 1.

1:0 0 = These bits must be programmed to 0.

Intel® ICH8 Family Datasheet 359

LPC Interface Bridge Registers (D31:F0)

9.4.5 ICW3—Slave Controller Initialization Command

Word 3 Register (LPC I/F—D31:F0)

Offset Address: A1h Attribute: WO

Default Value: All bits undefined Size: 8 bits

9.4.6 ICW4—Initialization Command Word 4 Register

(LPC I/F—D31:F0)

Offset Address: Master Controller – 021h Attribute: WO

Slave Controller

– 0A1h Si ze: 8 bits

Default Value: 01h

Bit Description

7:3 0 = These bits must be programmed to 0.

2:0

Slave Identific ation Code — WO. These bits are compared against the slave

identification code broadcast by the master controller from the trail ing edge of the first

internal INT A# pulse to the trailing edge of the second internal INT A# pulse. These bits

must be programmed to 02h to match the code broadcast by the master controller.

When 02h is broadcast by the master controller during the INTA# sequence, the slave

controller assum es responsibility for broadcasting the interrupt vector.

Bit Description

7:5 0 = These bits must be programmed to 0.

4Special Fully Nested Mode (SFNM) — WO.

0 = Should normally be disabled by writing a 0 to this bit.

1 = Special fully nested mode is programmed.

3Buffered Mode (BUF) — WO.

0 = Must be programmed to 0 for the ICH8. This is non-buffered mode.

2Master/Slave in Buffered Mode — WO. Not used.

0 = Should always be programmed to 0.

1Automatic End of Interrupt (AEOI) — WO.

0 = This bit should normally be programmed to 0. This is the normal end of interrupt.

1 = Automatic End of Interrupt (AEOI) mode is programmed.

0Microprocessor Mode — WO.

1 = Must be programmed to 1 to indicate that the controller is operating in an Intel

Architecture-bas ed system.

LPC Interface Bridge Registers (D31:F 0)

360 Intel® ICH8 Family Datasheet

9.4.7 OCW1—Operational Control Word 1 (Interrupt Mask)

Offset Address: Master Controller – 021h Attribute: R/W

Slave Controller

– 0A1h Size: 8 bits

Default Value: 00h

9.4.8 OCW2—Operational Control Word 2 Register

(LPC I/F—D31:F0)

Offset Address: Master Controller – 020h Attribute: WO

Slave Controller

– 0A0h Size: 8 bits

Default Value: Bit[4:0]=undefined, Bit[7:5]=001

Following a part reset or ICW initialization, the controller enters the fully nested mode

of operation. Non-specific EOI without rotation is the default. Both rotation mode and

specific EOI mode are disabled following initialization.

Bit Description

7:0

Interrupt Request Mask — R/W. When a 1 is written to any bit in this register, the

corresponding IRQ line is masked. When a 0 is written to any bit in this register, the

corresponding IRQ mask bit is cleared, and interrupt requests will again be accepted by

the controller. Masking IRQ2 on the ma ster controller will also mask the interrupt

requests from the slave controller.

Bit Description

7:5

Rotate and EOI Codes (R, SL, EOI) — WO. These three bits control the Rotate and

End of Interrupt modes and combinations of the two.

000 = Rotate in Auto EOI Mode (Cle ar)

001 = Non-specific EOI command

010 = No Operation

011 = *Specific EOI Command

100 = Rotate in Auto EOI Mode (Set)

101 = Rotate on Non-Specific EOI Comman d

110 = *Set Priority Command

111 = *Rotate on Specific EOI Command

*L0 – L2 Are Used

4:3 OCW2 Select — WO. When selecting OCW2, bits 4:3 = “00”

2:0

Interrupt Level Select (L2, L1, L0) — WO. L2, L1, and L0 determine the interrupt

level acted u pon when the SL bit is active. A simple binary co de, outlined below , select s

the channel for the com mand to act upon. When the SL bit is inactiv e, these bits do not

have a defined function; programming L2, L1 and L0 to 0 is sufficient in this case.

Code Interrupt Level Code Interrupt Level

000b IRQ0/8 000b IRQ4/12

001b IRQ1/9 001b IRQ5/13

010b IRQ2/10 010b IRQ6/14

011b IRQ3/11 011b IRQ7/15

Intel® ICH8 Family Datasheet 361

LPC Interface Bridge Registers (D31:F0)

9.4.9 OCW3—Operational Control Word 3 Register

(LPC I/F—D31:F0)

Offset Address: Master Controller – 020h Attribute: WO

Slave Controller

– 0A0h Si ze: 8 bits

Default Value: Bit[6,0]=0, Bit[7,4:2]=undefined,

Bit[5,1]=1

Bit Description

7 Reserved. Must be 0.

Special Mask Mode (SMM) — WO.

1 = The Special Mask Mode can be used by an interrupt service rout in e to dyna mi ca l ly

alter the system priority structure while the routine is executing, through selective

enabling/disabling of the other channel's mask bits. Bit 5, the ESMM bit, must be

set for this bit to have any meaning.

5Enable Special Mask Mo de (E SMM) — WO.

0 = Disable. The SMM bit becomes a “don't care”.

1 = Enable the SMM bit to set or reset the Special Mask M ode .

4:3 OCW3 Select — WO. When selecting OCW3, bits 4:3 = 01

Poll Mode Command — WO.

0 = Disable. Poll Command is not issued.

1 = Enable. The next I/O read to the interrupt controller is treated as an interrupt

acknowledge cycle. An encoded byte is driven onto the data bus, representing the

highest priority level requesting service.

1:0

affect the register read selection. When bit 1=1, bit 0 selects the register status

returned following an OCW3 read. If bit 0=0, the IRR will be read. If bit 0=1, the ISR

will be read. Following ICW initialization, the default OCW3 port address read will be

“read IRR”. To retain the current selection (read ISR or read IRR), always write a 0 to

bit 1 when programming this register. The selected register can be read repeatedly

without reprogramming OCW3. To select a new status register, OCW3 must be

reprogrammed prior to attempting the read.

00 = No Action

01 = No Action

10 = Read IRQ Register

11 = Read IS Regist er

LPC Interface Bridge Registers (D31:F 0)

362 Intel® ICH8 Family Datasheet

9.4.10 ELCR1—Master Controller Edge/Level Triggered Register

(LPC I/F—D31:F0)

Offset Address: 4D0h Attribute: R/W

Default Value: 00h Size: 8 bits

In edge mode, (bit[x] = 0), the interrupt is recognized by a low to high transition. In

level mode (bit[x] = 1), the interrupt is recognized by a high level. The cascade

channel, IRQ2, the heart beat timer (IRQ0), and the keyboard controller (IRQ1),

cannot be put into level mode.

Bit Description

7IRQ7 ECL — R/W.

0 = Edge.

1 = Level.

6IRQ6 ECL — R/W.

0 = Edge.

1 = Level.

5IRQ5 ECL — R/W.

0 = Edge.

1 = Level.

4IRQ4 ECL — R/W.

0 = Edge.

1 = Level.

3IRQ3 ECL — R/W.

0 = Edge.

1 = Level.

2:0 Reserved. Must be 0.

Intel® ICH8 Family Datasheet 363

LPC Interface Bridge Registers (D31:F0)

9.4.11 ELCR2—Slave Controller Edge/Level Triggered Register

(LPC I/F—D31:F0)

Offset Address: 4D1h Attribute: R/W

Default Value: 00h Size: 8 bits

In edge mode, (bit[x] = 0), the interrupt is recognized by a low to high transition. In

level mode (bit[x] = 1), the interrupt is recognized by a high level. The real time clock,

IRQ8#, and the floating point error interrupt, IRQ13, cannot be programmed for level

mode.

Bit Description

7IRQ15 ECL — R/W.

0 = Edge

1 = Level

6IRQ14 ECL — R/W.

0 = Edge

1 = Level

5 Reserved. Must be 0.

4IRQ12 ECL — R/W.

0 = Edge

1 = Level

3IRQ11 ECL — R/W.

0 = Edge

1 = Level

2IRQ10 ECL — R/W.

0 = Edge

1 = Level

1IRQ9 ECL — R/W.

0 = Edge

1 = Level

0 Reserved. Must be 0.

LPC Interface Bridge Registers (D31:F 0)

364 Intel® ICH8 Family Datasheet

9.5 Advanced Programmable Interrupt Controller

(APIC)(D31:F0)

9.5.1 APIC Register Map (LPC I/F—D31:F0)

The APIC is accessed via an indirect addressing scheme. Two registers are visible by

software for manipulation of most of the APIC registers. These registers are mapped

into memory space. The address bits 15:12 of the address range are programmable

through bit 7:4 of OIC register (Chipset Configuration Register, offset 31 FFh.) The

registers are shown in Table 108.

Table 109 lists the registers which can be accessed within the APIC via the Index

For example, software should never access byte 2 from the Data register before

accessing bytes 0 and 1. The hardware will not attempt to recover from a bad

programming model in this case.

9.5.2 IND—Index Register (LPC I/F—D31:F0)

Memory Address FEC0_0000h Attribute: R/W

Default Value: 00h Size: 8 bits

The Index Register will select which APIC indirect register to be manipulated by

software. The selector values for the indirect registers are listed in Table 109. Software

will program this register to select the desired APIC internal register

Table 108. APIC Direct Registers (LPC I/F—D31:F0)

Address Mnemonic Register Name Size Type

FEC0_0000h IND Index 8 bits R/W

FEC0_0010h DAT Data 32 bits R/W

FECO_0040h EOIR EOI 32 bits WO

Table 109. APIC Indirect Registers (LPC I/F—D31:F0)

Index Mnemonic Register Name Size Type

00 ID Identification 32 bits R/W

01 VER Version 32 bits RO

02–0F — Reserved — RO

10–11 REDIR_TBL0 Redirection Table 0 64 bits R/W, RO

12–13 REDIR_TBL1 Redirection Table 1 64 bits R/W, RO

... ... ... ... ...

3E–3F REDIR_TBL23 Redirection Table 23 64 bits R/W, RO

40–FF — Reserved — RO

Bit Description

7:0 APIC Index — R/W. This is an 8-bit pointer into the I/O APIC register table.

Intel® ICH8 Family Datasheet 365

LPC Interface Bridge Registers (D31:F0)

9.5.3 DAT—Data Register (LPC I/F—D31:F0)

Memory Address FEC0_0010h Attribute: R/W

Default Value: 00000000h Size: 32 bits

This is a 32-bit register specifying the data to be read or written to the register pointed

to by the Index register. This register can only be accessed in dword quantities.

9.5.4 EOIR—EOI Register (LPC I/F—D31:F0)

Memory Address FEC0h_00 40h Attribute: WO

Default Value: N/A Size: 32 bits

The EOI register is present to provide a mechanism to maintain the level triggered

semantics for level-triggered interrupts issued on the parallel bus.

When a write is issued to this register, the I/O APIC will check the lower 8 bits written

to this register, and compare it with the vector field for each entry in the I/O

Redirection Ta ble. When a match is found, the Remote_IRR bit (Index Offset 10h,

bit 14) for that I/O Redirection Entry will be cleared.

Note: If multiple I/O Redirection entries, for any reason, assign the same vector for more

than one interrupt input, each of those entries will have the Remote_IRR bit reset to 0.

The interrupt which was prematurely reset will not be lost because if its input remained

active when the Remote_IRR bit is cleared, the interrupt will be reissued and serviced

at a later time. Note: Only bits 7:0 are actually used. Bits 31:8 are ignored by the

ICH8.

Note: To provide for future expansion, the processor should always write a value of 0 to

bits 31:8.

Bit Description

7:0 APIC Data — R/W. This is a 32-bit register for the data to be read or written to the

APIC indirect register (Figure 109) pointed to by the Index register (Memory Address

FEC0_0000h).

Bit Description

31:8 R eserved. To provide for future expansion, the processor should alwa ys write a value of

0 to Bits 31:8.

7:0

Redirection Entry Clear — WO. When a write is issued to this register, the I/O APIC

will check this field, and compare it with the vector field for each entry in the I/O

Redirection Table. When a match is found, the Remote_IRR bit for that I/O Re direction

Entry will be cleared.

LPC Interface Bridge Registers (D31:F 0)

366 Intel® ICH8 Family Datasheet

9.5.5 ID—Identification Register (LPC I/F—D31:F0)

Index Offset: 00h Attribute: R/W

Default Value: 00000000h Size: 32 bits

The APIC ID serves as a physical name of the APIC. The APIC bus arbitration ID for th e

APIC is derived from its I/O APIC ID. This register is reset to 0 on power-up reset.

9.5.6 VER—Version Register (LPC I/F—D31:F0)

Index Offset: 01h Attribute: RO

Default Value: 00170020h Size: 32 bits

Each I/O APIC contains a hardwired Version Register that identifies different

implementation of APIC and their ve rsions. The maximum redirection entry information

also is in this register, to let software know how many interrupt are supported by this

APIC.

Bit Description

31:28 Reserved

27:24 APIC ID — R/W. Software must program this value before using the APIC.

23:16 Reserved

15 Scratchpad Bit.

14:0 Reserved

Bit Description

31:24 Reserved

23:16

Maximum Redirection Entries — RO. This is the entry number (0 bein g the lowest

entry) of the highest entry in the redirection table. It is equal to the number of

interrupt input pins minus one and is in the range 0 through 239. In the ICH8 this field

is hardwired to 17h to indicate 24 interrupts.

15 PRQ — RO. Indicate that the IOx A PIC do es not implement th e Pin Assertion Register.

14:8 Reserved

7:0 Version — RO. This is a versio n number that identifies the implementati on version.

Intel® ICH8 Family Datasheet 367

LPC Interface Bridge Registers (D31:F0)

9.5.7 REDIR_TBL—Redirection Table (LPC I/F—D31:F0)

Index Offset: 10h–11h (vector 0) through Attribute: R/W, RO

3E–3Fh (vector 23)

Default Value: Bit 16 = 1,. Size: 64 bits each, (accessed as

All other bits undefined two 32 bit quantities)

The Redirection Ta ble has a dedicated entry for each interrupt input pin. The

information in the Redirection Ta ble is used to translate the interrupt manifestation on

the corresponding interrupt pin into an APIC message.

The APIC will respond to an edge triggered interrupt as long as the interrupt is held

until after the acknowledge cycle has begun. Once the interrupt is detected, a delivery

status bit internally to the I/O APIC is set. The state machine will step ahead and wait

for an acknowledgment from the APIC unit that the interrupt message was sent. Only

then will the I/O APIC be able to recognize a new edge on that interrupt pin. That new

edge will only result in a new invocation of the handler if its acceptance by the

destination APIC causes the Interrupt Request Register bit to go from 0 to 1.

(In other words, if the interrupt was not already pending at the destination.)

Bit Description

63:56

Destination — R/W. If bit 11 of this entry is 0 (Physical), then bits 59:56 specifies an

APIC ID. In this case, bits 63:59 should be programmed by software to 0.

If bit 11 of this entry is 1 (Logical), then bits 63:56 specify the logical destination

address of a set of processors.

55:48 Extended Destination ID (EDID) — RO. These bits are sent to a local APIC only

when in Processor System Bus mode. They become bits 11:4 of the address.

47:17 Reserved

Mask — R/W.

0 = Not masked: An edge or level on this interrupt pin results in the delivery of the

interrupt to the destination.

1 = Masked: Interrupts are not delivered nor held pending. Setting this bit after the

interrupt is accepted by a local APIC has no effect on that interrupt. This behavior

is identical to the device withdrawing the interrupt before it is posted to the

processor. It is software's responsibility to deal with the case where the mask bit is

set after the interrupt message has been accepted by a local APIC unit but before

the interrupt is dispensed to the processor.

Trigger Mode — R/W. This field indicates the type of signal on the interrupt pin that

triggers an interrupt.

0 = Edge triggered.

1 = Level triggered.

Remote IRR — R/W. This bit is used for level triggered interrupts; its meaning is

undefined for edge triggered interrupts.

0 = Reset when an EOI message is received from a local APIC.

1 = Set when Local APIC/s accept the level interrupt sent by the I/O APIC.

Interrupt Input Pin Polarity — R/W. This bit specifies the polarity of each interrupt

signal connected to the interrupt pins.

0 = Active high.

1 = Active low.

Delivery Status — RO. This field contains the current status of the delivery of this

interrupt. Writes to this bit have no effect.

0 = Idle. No activity for this interrupt.

1 = Pending. Interrupt has been injected, but delivery is no t complete.

LPC Interface Bridge Registers (D31:F 0)

368 Intel® ICH8 Family Datasheet

NOTE: Delivery Mode encoding:

000 = Fixed. Deliver the signal on the INTR signal of all processor cores listed in the destination.

Trigger Mode can be edge or level.

001 = Lowest Priority. Deliver the signal on the INTR signal of the processor core that is executing

at the lowest priority among all the processors listed in the specified desti nation. Trigger

Mode can be edge or level.

010 = SMI (System Management Interrupt). Requires the interrupt to be programmed as edge

triggered. The vector information is ignored but must be programmed to all 0’s for future

compatibility: not supported

011 = Reserved

100 = NMI. Deliver the signal on the NMI signal of all processor cores listed in the destination.

Ve ctor information is ignored. NMI is treated as an edge triggered interrupt even if it is

programmed as level triggered. For proper operation this redirection table entry must be

programmed to edge triggered. The NMI delivery mode does not set the RIRR bit. If the

redirection table is incorrectly set to level, the loop count will continue countin g through

the redirection table addresses. Once the count for the NMI pin is reached again, the

interrupt will be sent again: not supported

101 = INIT. Deliver the signal to all processor cores listed in the destination by asserting the INIT

signal. All addressed local APICs wi ll assum e their INIT state. INIT is alw a ys treated as an

edge triggered interrupt even if programmed as level triggered. For proper operation this

redirection table entry must be programmed to edge triggered. The INIT delivery mode

does not set the RIRR bit. If the redirection table is incorrectly set to level, the loop count

will continue counting through the redirection table addresses. Once the count for t he INIT

pin is reached again, the interrupt will be sent again: not supported

110 = Reserved

111 = ExtINT. Deliver the signal to the INTR signal of all processor cores listed in the destination

as an interrupt that originated in an externally connected 8259A compatible interrupt

controller. The INTA cycle that corresponds to this ExtINT delivery will be routed to the

external controller that is expected to supply the vector. Requires the interrupt to be

programmed as edge triggered.

Destination Mode — R/W. This field determines the interpretation of the Destination

field.

0 = Physical. Destination APIC ID is identified by bits 59:56.

1 = Logical. Destinations are identified by matching bit 63:56 with the Logical

Destination in the Destination Format Register and Logical Destination Register in

each Local APIC.

10:8

Delivery Mode — R/W. This field specifies how the APICs listed in the destination field

should act upon reception of this signal. Certain Delivery Mode s will only operate as

intended when used in c on j unction with a specific trigger mode. These encodings are

listed in the no te below:

7:0 Vector — R/W. This field contains the interrupt vector for this interrupt. Values range

between 10h and FEh.

Bit Description

Intel® ICH8 Family Datasheet 369

LPC Interface Bridge Registers (D31:F0)

9.6 Real Time Clock Registers (LPC I/F—D31:F0)

9.6.1 I/O Register Address Map (LPC I/F—D31:F0)

The RTC internal registers and RAM are organized as two banks of 128 bytes each,

called the standard and extended banks. The first 14 bytes of the standard bank

contain the R TC time and date information along with four registers, A –D, that are used

for configuration of the RTC. The extended bank contains a full 128 bytes of battery

backed SRAM, and will be accessible even when the RTC module is disabled (via the

RTC configuration register). Registers A–D do not physically exist in the RAM.

All data movement between the host processor and the real-time clock is done through

registers mapped to the standard I/O space. Th e register map appears in Table 110.

NOTES:

1. I/O locations 70h and 71h are the standard legacy location for the real-time clock.

The map for this bank is shown in Table 111. Locations 72h and 73h are for

accessing the extended RAM. The extended RAM bank is also accessed using an

indexed scheme. I/O address 72h is used as the address pointer and I/O address

73h is used as the data register. Index addresses above 127h are not valid. If the

extended RAM is not needed, it may be disabled.

2. Software must preserve the value of bit 7 at I/O addresses 70h and 74h. When

writing to this address, software must first read the v alue, and then write the same

value for bit 7 during the sequential address write. Note that port 70h is not

directly readable. The only way to read this register is through Alt Access mode.

Although R TC Index bits 6:0 are readable fr om port 74h, bit 7 will alwa ys return 0.

If the NMI# enable is not changed during normal operation, software can

alternatively read this bit once and then retain the value for all subsequent writes

to port 70h.

Table 110. RTC I/O Registers (LPC I/F—D31 :F0)

I/O

Locations If U128E bit = 0 Function

70h and 74h Also alias to 72h and 76h Real-Time Clock (Standard RAM) Index Register

71h and 75h Also alias to 73h and 77h Real-Time Clock (Standard RAM) Target Register

72h and 76h Extended RAM Index Register (if enabled)

73h and 77h Extended RAM Target Register (if enabled)

LPC Interface Bridge Registers (D31:F 0)

370 Intel® ICH8 Family Datasheet

9.6.2 Indexed Registers (LPC I/F—D31:F0)

The RTC contains two sets of indexed registers that are accessed using the two

separate Index and Target registers (70/7 1h or 72/73h), as shown in Table 111.

Table 111. RTC (Standard) RAM Bank (LPC I/F—D31:F0)

Index Name

00h Seconds

01h Seconds Alarm

02h Minutes

03h Minutes Alarm

04h Hours

05h Hours Alarm

06h Day of Week

07h Day of Month

08h Month

09h Year

0Ah Register A

0Bh Register B

0Ch Register C

0Dh Register D

0Eh–7Fh 114 Bytes of User RAM

Intel® ICH8 Family Datasheet 371

LPC Interface Bridge Registers (D31:F0)

9.6.2.1 RTC_REGA—Register A (LPC I/F—D31:F0)

RTC Index: 0 A Attribute: R/W

Default Value: Undefined Size: 8-bit

Lockable: No Power Well: RTC

This register is used for general configuration of the R TC fu nctions. None of the bits are

affected by RSMRST# or any other ICH8 reset signal.

Bit Description

Update In Progress (UIP) — R/W. This bit may be monitored as a status flag.

0 = The update cycle will not start for at least 488 µs. The time, calendar, and alarm

information in RAM is always available when the UIP bit is 0.

1 = The update is soon to occur or is in progress.

6:4

Division Chain Sele ct (DV[2:0]) — R/W. These three bits control the divider chain.

The division chain itself is reset by RSMRST# to all 0’s and it can also be cleared to 0’s

by firmware thru programming of DV. The periodic event (setting of RTCIS.PF and the

associated interrupt) can be based on the time as measured from RSMRST#

deassertion until a divider reset (DV=’11x’ to ‘010’) is performed by firmware.

DV2 corresponds to bit 6.

010 = Normal Operation

11X = Divider Reset

101 = Bypass 15 stages (test mode only)

100 = Bypass 10 stages (test mode only)

011 = Bypass 5 stages (test mode only)

001 = Invalid

000 = Invalid

3:0

Rate Select (RS[3:0]) — R/W. Selects one of 13 taps of the 15 stage divider chain.

The selected tap can generate a periodic interrupt if the PIE bit is set in Register B.

Otherwise this tap will set the PF flag of Register C. If the periodic interrupt is not to be

used, these bits should all be set to 0. RS3 corresponds to bit 3.

0000 = Interrupt never toggles

0001 = 3.90625 ms

0010 = 7.8125 ms

0011 = 122.070 µs

0100 = 244.141 µs

0101 = 488.281 µs

0110 = 976.5625 µs

0111 = 1.953125 ms

1000 = 3.90625 ms

1001 = 7.8125 ms

1010 = 15.625 ms

1011 = 31.25 ms

1100 = 62.5 ms

1101 = 125 ms

1110 = 250 ms

1111= 500 ms

LPC Interface Bridge Registers (D31:F 0)

372 Intel® ICH8 Family Datasheet

9.6.2.2 RT C_REGB—Register B (General Configuration)

(LPC I/F—D31:F0)

RTC Index: 0Bh Attribute: R/W

Default Value: U0U00UUU (U: Undefined) Size: 8-bit

Lockable: No Power Well: RTC

Bit Description

Update Cycle Inhibit (SET) — R/W. Enables/Inhibits the update cycles. This bit is not

affected by RSMRST# nor any other reset signal.

0 = Update cycle occurs normally once each second.

1 = A current update cycle will abort and subsequent update cycles will not occur until

SET is returned to 0. When set is one, the BIOS may initialize time and calendar

bytes safely.

NOTE: This bit should be set then cleared early in BIOS POST after each powerup

directly after coin-cell battery insertion.

Periodic Interrupt Enable (P IE) — R/W. This bit is cleared by RSMRST#, but not on

any other reset.

0 = Disable.

1 = Enable. Allows an interru pt to occur with a time base set with the RS bits of re gister

Alarm Interrupt Enable (AIE) — R/W . This bit is cleared by R TCRST#, but not on any

other reset.

0 = Disable.

1 = Enable. Allows an interrupt to occur when the AF is set by an alarm match from the

update cycle. An alarm can occur once a se cond, one an hour, once a day, or one a

month.

Update-Ended Interrupt Enable (UIE) — R/W. This bit is cleared by RSMRST#, but

not on any other reset.

0 = Disable.

1 = Enable. Allows an interrupt to occur when the update cycle ends.

3Square Wave Enable (SQWE) — R/W. This bit serves no function in the ICH8. It is

left in this register bank to provide compatibility with the Motorola 146818B. The ICH8

has no SQW pin. This bit is cleared by RSMRST#, but not on any other reset.

Data Mode (DM) — R/W. This bit specifies either binary or BCD data representation.

This bit is not affected by RSMRST# nor any other reset signal.

0 = BCD

1 = Binary

Hour Format (HOURFORM) — R/W. This bit indic ates the hour byte format. This bit is

not affected by RSMRST# nor any other reset signal.

0 = Twelve-hour mode. In twelve-hour mode, the seventh bit represents AM as 0 and

PM as one.

1 = Twenty-four hour mode.

Daylight Savings Enable (DSE) — R/W. This bit triggers two special hour updates per

year. The days for the hour adjustment are those specified in United States federal law

as of 1987, which is different than previous years. This bit is not affected by RSMRST#

nor any other reset signal.

0 = Daylight Savings Time updates do not occur.

1 = a) Update on the first Sunday in April, where time increments from 1:59:59 AM to

3:00:00 AM.

b) Update on the last Sunday in October when the time first reaches 1:59:59 AM, it

is changed to 1:00:00 AM. The time must increment normally for at least two

update cycles (seconds) previous to these conditions for the time change to occur

properly.

Intel® ICH8 Family Datasheet 373

LPC Interface Bridge Registers (D31:F0)

9.6.2.3 RTC_REGC— Register C (Flag Register)

(LPC I/F—D31:F0)

RTC Index: 0Ch Attribute: RO

Default Value: 00U00000 (U: Undefined) Size: 8-bit

Lockable: No Power Well: RTC

Writes to Register C have no effect.

9.6.2.4 RTC_REGD—Register D (Flag Register)

(LPC I/F—D31:F0)

RTC Index: 0Dh Attribute: R/W

Default Value: 10UUUUUU (U: Undefined) Size: 8-bit

Lockable: No Power Well: RTC

Bit Description

7 Interrupt Request Flag (IRQF) — RO . IRQF = (PF * PIE) + (AF * AIE) + (UF *UFE).

This bit also cau ses the R T C Interrupt to be asserted. This bit is cleared upon RSMRST#

or a read of Register C.

Periodic Interrupt Flag (PF) — RO. This bit is cleared upon RSMRST# or a read of

0 = If no taps are specified via the RS bits in Register A, this flag will not be set.

1 = Periodic interrupt Flag will be 1 when the tap specified by the RS bits of register A is

5Alarm Flag (AF) — RO.

0 = This bit is cleared upon RTCRST# or a read of Register C.

1 = Alarm Flag will be set after all Alarm values match the current time.

4Update-Ended Flag (UF) — RO.

0 = The bit is cleared upon RSMRST# or a read of Register C.

1 = Set immediately following an update cycle for each second.

3:0 Reserved. Will always report 0.

Bit Description

Valid RAM and Time Bit (VRT) — R/W.

0 = This bit should always be written as a 0 for write cycle, howev er it will return a 1 for

read cycles.

1 = This bit is hardwired to 1 in the RTC power well.

6 Reserved. This bit always returns a 0 and should be set to 0 for write cycles.

5:0

Date Alarm — R/W. These bits store the date of month alarm value. If set to 000000b,

then a don’ t care state is assumed. The host must configure the date alarm for these

bits to do anything, yet they can be written at any time. If the date alarm is not

enabled, these bits will return 0’s to mimic the functionality of the Motorola 146818B.

These bits are not affected by any reset assertion.

LPC Interface Bridge Registers (D31:F 0)

374 Intel® ICH8 Family Datasheet

9.7 Processor Interface Registers (LPC I/F—D31:F0)

Table 112 is the register address map for the processor interface registers.

9.7.1 NMI_SC—NMI Status and Control Register

(LPC I/F—D31:F0)

I/O Address: 61h Attribute: R/W, RO

Default Value: 00h Size: 8-bit

Lockable: No Power Well: Core

Table 112. Processor Interface PCI Register Address Map (LPC I/F—D31:F0)

Offset Mnemonic Register Name Default Type

61h NMI_SC NMI Status and Control 00h R/W, RO

70h NMI_EN NMI Enable 80h R/W (special)

92h PORT92 Fast A20 and Init 00h R/W

F0h COPROC_ERR Coprocessor Error 00h WO

CF9h RST_CNT Reset Control 00h R/W

Bit Description

SERR# NMI Source Status (SERR#_NMI_STS) — RO.

1 = Bit is set if a PCI agent detected a system error and pulses the PCI SER R# line and

if bit 2 (PCI_SERR_EN) is cleared. This interrupt source is enabled by setting bit 2

to 0. To reset the interrupt, set bit 2 to 1 and then set it to 0. When writing to port

61h, this bit must be 0.

NOTE: This bit is set by any of the ICH8 internal sources of SERR; this includes SERR

assertions forwarded from the secondary PCI bus, errors on a PCI Express*

port, or other internal functions that generate SERR#.

IOCHK# NMI Source Status (IOCHK_NMI_STS) — RO.

1 = Bit is set if an LPC agent (via SERIRQ) asserted IOCHK# and if bit 3

(IOCHK_NMI_EN) is cleared. This interrupt source is enabled by setting bit 3 to 0.

To reset the interrupt, set bit 3 to 1 and then set it to 0. When writing to port 61h,

this bit must be a 0.

Timer Counter 2 OUT Status (TMR2_OUT_STS) — RO. This bit reflects the current

state of the 8254 co unter 2 output. Cou nter 2 must be programmed following any PCI

reset for this bit to have a determinate value. When writing to port 61h, this bit must

be a 0.

4Refresh Cycle Togg le (REF_TOGGLE) — RO. This signal toggles from either 0 to 1 or

1 to 0 at a rate that is equivalent to when refresh cycles would occur. When writing to

port 61h, this bit must be a 0.

3IOCHK# NMI Enable (IOCHK_NMI_EN) — R/W.

0 = Enabled.

1 = Disabled and cleared.

2PCI SERR# Enable (PCI_SERR_EN) — R/W.

0 = SERR# NMIs are enabled.

1 = SERR# NMIs are disabled and cleared.

Intel® ICH8 Family Datasheet 375

LPC Interface Bridge Registers (D31:F0)

9.7.2 NMI_EN—NMI Enable (and Real Time Clock Index)

I/O Address: 70h Attribute: R/W (special)

Default Value: 80h Size: 8-bit

Lockable: No Power Well: Core

Note: The R TC Index field is write-only for normal operation. This field can only be read in Alt -

Access Mode. Note, however, that this register is aliased to Port 74h (documented in),

and all bits are readable at that address.

9.7.3 PORT92—Fast A20 and Init Register (LPC I/F—D31:F0)

I/O Address: 92h Attribute: R/W

Default Value: 00h Size: 8-bit

Lockable: No Power Well: Core

1Speaker Data Enab le (SPKR_DAT_EN) — R/W.

0 = SPKR ou tput is a 0.

1 = SPKR output is equivalent to the Counter 2 OUT signal value.

0Timer Counter 2 Enable (TIM_CNT2_EN) — R/W.

0 = Disable

1 = Enable

Bit Description

Bits Description

7NMI Enable (NMI_EN) — R/W (special).

0 = Enable NMI sources.

1 = Disable All NMI so urces.

6:0 Real Time Clock Index Address (RTC_INDX) — R/W (special). This data goes to

the RTC to select which register or CMOS RAM address is being accessed.

Bit Description

7:2 Reserved

Alternate A20 Gate (ALT_A20_GATE) — R/W. This bit is Or’d with t he A20GATE

input signal to generate A20M# to the processor.

0 = A20M# signal can potentially go active.

1 = This bit is set when INIT# goes active.

0INIT_NOW — R/W. When this bit trans itions from a 0 to a 1, the ICH8 will forc e INIT#

active for 16 PCI clocks.

LPC Interface Bridge Registers (D31:F 0)

376 Intel® ICH8 Family Datasheet

9.7.4 COPROC_ERR—Coprocessor Error Register

(LPC I/F—D31:F0)

I/O Address: F0h Attribute: WO

Default Value: 00h Size: 8-bits

Lockable: No Power Well: Core

9.7.5 RST_CNT—Reset Control Register (LPC I/F—D31:F0)

I/O Address: CF9h Attribute: R/W

Default Value: 00h Size: 8-bit

Lockable: No Power Well: Core

Bits Description

7:0

Coprocessor Error (COPR OC_ERR) — WO. Any value written to this register will

cause IGNNE# to go active, if FERR# had generated an internal IRQ13. For FERR# to

generate an internal IRQ13, the COPROC_ERR_EN bit (Chipset Configuration Register,

Offset 31FFh, bit 1) must be 1.

Bit Description

7:4 Reserved

Full Reset (FULL_RST) — R/W. This bit is used to determine the states o f SLP_S3#,

SLP_S4#, and SLP_S5# after a CF9 hard reset (SYS_RST =1 and RST_CPU is set to 1),

after PWROK going low (with RSMRST# high), or after two TCO timeouts.

0 = ICH8 will keep SLP_S3#, SLP_S4# and SLP_S5# high.

1 = ICH8 will drive SLP_S3#, SLP_S4# and SLP_S5# low for 3 – 5 seconds.

NOTE: When this bit is set, it also causes the full power cycle (SLP_S3/4/5# assertion)

in response to SYSRESET#, PWROK#, and Watchdog timer reset so urces.

2Reset CPU (RST_CPU) — R/W. When this bit transitions from a 0 to a 1, it initiates a

hard or soft reset, as determined by the SYS_RST bit (bit 1 of this register).

System Reset (SYS_RST) — R/W. This bit is used to determine a hard or soft reset to

the processor.

0 = When RST_CPU bit goes from 0 to 1, the ICH8 performs a soft reset by activating

INIT# for 16 PCI clocks.

1 = When RST_CPU bit goes from 0 to 1, the ICH8 performs a hard reset by activating

PLTRST# and SUS_STAT# active for about 5-6 milliseconds. In this case,

SLP_S#3, SLP_S4#, and SLP_S5# state (assertion or de-assertion) depends on

FULL_RST bit setting. The ICH8 main power well is reset when this bit is 1. It also

resets the resume well bits (except for those noted throughout the datasheet).

0 Reserved

Intel® ICH8 Family Datasheet 377

LPC Interface Bridge Registers (D31:F0)

9.8 Power Management Registers (PM—D31:F0)

The power management registers are distributed within the PCI Device 31: Function 0

space, as well as a separate I/O range. Each register is described below. Unless

otherwise indicate, bits are in the main (core) power well.

Bits not explicitly defined in each register are assumed to be reserved. When writin g to

a reserved bit, the value should always be 0. Software should not attempt to use the

value read from a reserved bit, as it may not be consistently 1 or 0.

9.8.1 Power Management PCI Configuration Registers

(PM—D31:F0)

Table 113 shows a small part of the configuration space for PCI Device 31: Function 0.

It includes only those registers dedicated for power management. Some of the

registers are only used for Legacy Power management schemes.

Table 113. Power Management PCI Register Address Map (PM—D31:F0)

Offset Mnemonic Register Name Default Type

A0h GEN_PMCON_1 General Power Management

Configuration 1 0000h R/W, RO,

R/WO

A2h GEN_PMCON_2 General Power Management

Configuration 2 00h R/W, R/

A4h GEN_PMCON_3 General Power Management

Configuration 3 00h R/W, R/

A9h Cx-STATE_CNF Cx State Configuration (Mobile Only). 00h R/W

AAh C4-TIMING_CNT C4 Timing Control (Mobile Only). 00h R/W

ABh BM_BREAK_EN BM_BREAK_EN (Mobile Only) 00h R/W

ACh PMIR Power Management Initialization 00h R/W

ADh MSC_FUN Miscellaneous Functionality 00h R/W

B0h QRT_STS Quick Resume Technology Stat us

B1h-B2h QRT_CNTL1 Quick Resume Technology Control 1

B3h QRT_CNTL2 Quick Resume Technology Control 2

B8–BBh GPI_ROUT GPI Route Control 0000000

0h R/W

LPC Interface Bridge Registers (D31:F 0)

378 Intel® ICH8 Family Datasheet

9.8.1.1 GEN_PMCON_1—General PM Configuration 1 Register

(PM—D31:F0)

Offset Address: A0h Attribute: R/W, RO, R/WO

Default Value: 0000h Size: 16-bit

Lockable: No Usage: ACPI, Legacy

Power Well: Core

Bit Description

15:13 Reserved

(Desktop

Only) Reserved

(Mobile

Only)

C4 Disable: This bit disables the C4 feature.

0 = Enables C4

1 = Disables C4

(Desktop) Reserved

(Mobile

Only)

C5_Enable: This bit enables the C5 and C6 features. When this bit is 0, the

platform does not enable the C5 and C6 features. When this bit is 1, the platform

enables C5/C6 features.

This bit also, along with GPIO_USE_SEL[0] bit, enables selection of BM_BUSY#/

PMSYNC# function on ICH pin as shown below:

When this bit i s 0:

• The R/W bits of the C5 Exit Timing Register become scratchpad with no effect on hardware

functions.

• I/O Reads to the LVL5 and LVL6 registers will be retired normally, but with no other action.

• All attempts to enter deeper C-States that require a transition through the C5 timing logic

will be ignored.

BIOS_PCI_EXP_EN — R/W. This bit acts as a global enable for the SCI associated

with the PCI Express* ports.

0 = The various PCI Express ports and (G)MCH cannot cause the PCI_EXP_STS bit

to go active.

1 = The various PCI Express ports and (G)MCH can cause the PCI_EXP_STS bit to

go active.

9PWRBTN_LVL — RO. This bit indicates the current state of the PWRBTN# signal.

0 = Low.

1 = High.

8 Reserved

(Desktop

Only) Reserved

(Mobile

Only)

Enter C4 When C3 Invoked (C4onC3_ EN) — R/W. If this bit is set, then when

software does a LVL3 read, the ICH8 transitions to the C4 state.

GPIO_USE_SEL[0] C5_Enable Result

1XGPIO

00BM_BUSY#

01PMSYNC#

Intel® ICH8 Family Datasheet 379

LPC Interface Bridge Registers (D31:F0)

6i64_EN. Software sets this bit to indi cate that the processor is an IA_64 pr ocessor,

not an IA_32 processor. This may be used in various state machines where there

are behavioral differences.

CPU SLP# Enable (CPUSLP_EN) — R/W.

0 = Disable.

1 = Enables the CPUSLP# signal to go active in the S1 state. This reduces the

processor power.

NOTE: CPUSLP# will go active during Intel SpeedStep® techn ology transitions and

on entry to C3 and C4 states even if this bit is not set.

SMI_LOCK — R/WO. When this bit is set, writes to the GLB_SMI_EN bit (PMBASE

+ 30h, bit 0) will have no effect. Once the SMI_LOCK bit is set, writes of 0 to

SMI_LOCK bit will have no effect (i.e., once set, this bit can only be cleared by

PLTRST#).

3:2

(Desktop

Only) Reserved

(Mobile

Only)

Intel SpeedStep Enable (SS_EN) — R/W.

0 = Intel SpeedStep technology logic is disabled and the SS_CNT register will not

be visible (reads to SS_CNT will return 00h and writes will have no effect).

1 = Intel SpeedStep technology logic is enabled.

(Mobile

Only)

PCI CLKRUN# Enable (CLKRUN_EN) — R/W.

0 = Disable. ICH8 drives the CLKRUN# signal low.

1 = Enable CLKRUN# logic to control the system PCI clock via the CLKRUN# and

STP_PCI# signals.

NOTE: when the SLP_EN# bit is set, the ICH8 drives the CLKRUN# signal low

regardless of the state of the CLKRUN_EN bit. This ensures that the PCI and

LPC clocks continue running during a transition to a sleep state.

1:0

Periodic SMI# Rate Select (PER_SMI_SEL) — R/W. Set by software to control the

rate at which periodic SMI# is generated.

00 = 64 seconds

01 = 32 seconds

10 = 16 seconds

11 = 8 seconds

Bit Description

LPC Interface Bridge Registers (D31:F 0)

380 Intel® ICH8 Family Datasheet

9.8.1.2 GEN_PMCON_2—General PM Configuration 2 Register

(PM—D31:F0)

Offset Address: A2h Attribute: R/W, R/WC

Default Value: 00h Size: 8-bit

Lockable: No Usage: ACPI, Legacy

Power Well: Resume

Bit Description

DRAM Initialization Bit — R/W. This bit does not effect hardware functionality in

any way. BIO S is expected to set this bit prior to starting t he DRAM initialization

sequence and to clear this bit after completing the DRAM initialization sequence.

BIOS can detect that a DRAM initialization sequence was interrupted by a reset by

reading this bit during the boot sequence .

• If the bit is 1, then the DRAM initialization was interrupted.

• This bit is reset by the assertion of the RSMRST# pin.

6:5

(Desktop

Only) Reserved

6:5

(Mobile

Only)

CPU PLL Lock Time (CPLT) — R/W. This field indicates the amount of time that the

processor needs to lock its PLLs. This is used wherever timing t250–t274 (see

Chapter 23) applies.

00 = min 30.7 µs (Default)

01 = min 61.4 µs

10 = min 122.8 µs

11 = min 245.6 µs

It is the responsibility of the BIOS to program the correct value in this field prior to

the first transition to C3 or C4 states (or performing Intel SpeedStep technology

transitions).

NOTE: The new DPSLP-TO-SLP bits (D31:FO:AAh, bits 1:0) act as an override to

these bits.

NOTE: These bits are not cleared by any type of reset except RSMRST# or a CF9

write

System Reset Status (SRS) — R/WC. Software clears this bit by writing a 1 to it.

0 = SYS_RESET# button Not pressed.

1 = ICH8 sets this bit when the SYS_RESET# button is pressed. BIOS is expected to

read this bit and clear it, if it is set.

NOTE: This bit is also reset by RSMRST# and CF9h resets.

CPU Thermal Trip Status (CTS) — R/WC.

0 = Software clears this bit by writing a 1 to it.

1 = This bit is se t when PLTRST# is inactive and THRMTRIP# goes active while the

system is in an S0 or S1 state.

NOTES:

1. This bit is also reset by RSMRST#, and CF9h resets. It is not reset by the

shutdown and reboot associated with the CPUTHRMTRIP# event.

2. The CF9h reset in the description refers to CF9h type core well reset which

includes SYS_RST#, PWROK/VRMPWRGD low, SMBus hard reset, TCO

Timeout. This type of reset will clear CTS bit.

Intel® ICH8 Family Datasheet 381

LPC Interface Bridge Registers (D31:F0)

NOTE: VRM PW ROK is sampled using the RTC clock. Therefore, low times that are less than one

RTC clock period may not be detected by the ICH8.

9.8.1.3 GEN_PMCON_3—General PM Configuration 3 Register

(PM—D31:F0)

Offset Address: A4h Attribute: R/W, R/WC

Default Value: 00h Size: 16-bit

Lockable: No Usage: ACPI, Legacy

Power Well: RTC

Minimum SLP_S4# Assertion Width Violation Status — R/WC.

0 = Software clears this bit by writing a 1 to it.

1 = Hardware sets this bit when the SLP_S4# assertion width is less than the time

programmed in the SLP_S4# Minimum Assertion Width field (D31:F0:Offset

A4h:bits 5:4). The ICH8 begins the timer when SLP_S4# is asserted during S4/

S5 entry, or when the RSMRST# input is deasserted during G3 exit. Note that

this bit is functional re gardless of the value in the SLP_S4# Assertion Stretch

Enable (D31:F0:Offset A4h:bit 3).

NOTE: This bit is reset by the asserti on of the RSMRST# pin, but can be set i n some

cases before the default value is readable.

CPU Power Failure (CP UP W R_ F L R) — R/W.

0 = Software (typically BIOS) clears this bit by writing a 0 to it.

1 = Indicates that the VRMPWRGD signal from the processor’s VRM went low while

the system was in an S0 or S1 state.

NOTE: VRM PW RGD is sampled using the RTC clock. Therefore, low times that are

less than one RTC clock period may not be detected by the Intel ICH8.

PWROK Failure (PWROK_FLR) — R/WC.

0 = Software clears this bit by writing a 1 to it, or when the system goes into a G3

state.

1 = This bit will be set any time PWROK goes low, when the system was in S0, or S1

state. The bit will b e cleared only by software by writing a 1 to this bit or when

the system goes to a G3 state.

NOTE: See Chapter 5.13.11.3 for more details about the PWROK pin functionality.

NOTE: In the case of true PWROK failure, PWROK will go low first before the

VRMPWRGD.

Bit Description

15:9 Reserved

S4_STATE# Pin Disable — R/W.

0 = The traditional SLP_S4# signal (without ME Overrides) is driven on the S4_STATE#

Pin.

1 = The S4_STATE# pin functionality is disabled and the pin can be used for other

functionality.

This bit is cleared by RTCRST#.

7:6

SWSMI_RATE_SEL — R/W. This field indicates when the SWSMI timer will time out.

Valid values are:

00 = 1.5 ms ± 0.6 ms

01 = 16 ms ± 4 ms

10 = 32 ms ± 4 ms

11 = 64 ms ± 4 ms

These bits are not cleared by any type of reset except RTCRST#.

LPC Interface Bridge Registers (D31:F 0)

382 Intel® ICH8 Family Datasheet

NOTE: RSMRST# is sampled using the RT C clock. Therefore, low times that are less than one RTC

clock period may not be detected by the ICH8.

5:4

SLP_S4# Minimum Assertion Width — R/W. This field indicates the minimum

assertion width of the SLP_S4# signal to assure that the DRAMs have been safely

power-cycled.

Valid values are:

11 = 1 to 2 seconds

10 = 2 to 3 seconds

01 = 3 to 4 seconds

00 = 4 to 5 seconds

This value is used in two ways:

1. If the SLP_S4# assertion width is ever shorter than this time, a status bit is set

for BIOS to read when S0 is entered.

2. If enabled by bit 3 in this register, the hardware will prevent the SLP_S4# signal

from deasserting within this minimum time period after asserting.

RTCRST# forces this field to the conservative default state (00b)

SLP_S4# Assertion Stretch Enable — R/W.

0 = The SLP_S4# minimum assertion time is 1 to 2 RTCCLK.

1 = The SLP_S4# signal minimally assert for the time specified in bits 5:4 of this

This bit is cleared by RTCRST#

2RTC Power Status (RTC_PWR_STS) — R/W. This bit is set when R TCRST# indicates

a weak or missing battery. Th e bit is not cleared by any type of reset. The bit will

remain set until the software clears it by writing a 0 back to this bit position.

Power Failu re (PWR_FLR) — R/WC. This bit is in th e RTC well, and is not cleared by

any type of reset except RTCRST#.

0 = Indicates that the trickle current has not failed since the last time the bit was

cleared. Software clears this bit by writing a 1 to it.

1 = Indicates that the trickle current (from the main battery or trickle supply) was

removed or failed.

NOTE: Clearing CMOS in an ICH-based platform can be done by using a jumper on

RTCRST# or GPI, or using SAFEMODE strap. Implementations s hould not

attempt to clear CMOS by using a jumper to pull VccRTC low.

AFTERG3_EN — R/W. This bit determines what state to go to when power is re-applied

after a power failure (G3 state). This bit is in the RTC well and is not cleared by any

type of reset except writes to CF9h or RTCRST#.

0 = System will return to S0 state (boot) after power is re-applied.

1 = System will ret urn to the S5 state (except if it was in S4, in which case it will return

to S4). In the S5 state, the only enabled wake event is the Power Button or any

enabled wake event that was preserved through the power failure.

NOTE: Bit will be set when THRMTRIP#-based shutdown occurs.

Bit Description

Intel® ICH8 Family Datasheet 383

LPC Interface Bridge Registers (D31:F0)

9.8.1.4 GEN_PMCON_LOCK—General Power Management Configuration Lock

Offset Address: A6h Attribute: R/W

Default Value: 00h Size: 8-bit

Lockable: No Usage: ACPI

Power Well: Core

This register is used to enable new C-state related modes.

Bit Description

(Mobile

Only)

Unlocked C-State Transition: This bit is set by hardware when a CPU power state

(C-State) transition deeper than C2 occurs and the C-STATE_CONFIG_LOCK bit is

not set. This bit is cleared by PLTRST# and is not writable by software.

6:2

(Mobile

Only)

7:2

(Desktop

Only)

Reserved

ACPI_BASE_LOCK: When set to 1, this bit locks down the ACPI Base Address

This bit becomes locked when a value of 1b is written to it. Writes of 0 to this bit are

always ignored. Once locked by writing 1, the only way to clear this bit is to perform

a platform reset.

(Mobile

Only)

C-STATE_CONFIG_LOCK: When set to 1, this bit locks down the C-State

configuration parameters. The following configuration bits become read-only when

this bit is set:

• GEYSERVILLE_EN (GEN_PMCON_1, bit 3)

• IA64_EN (GEN_PMCON_1, bit 6)

• C4_DISABLE (GEN_PMCON_1, bit 12)

• CPU_PLL_LOCK_TIME (GEN_PMCON_2, bits 6:5)

• The entire C4 Timing Control Register (C4_TIMING_CNT)

• The entire C5 Exit Timing Register (C5_EXIT_TIMING_CNT)

This bit becomes locked when a value of 1b is written to it. Writes of 0 to this bit are

always ignored. Once locked by writing 1, the only way to clear this bit is to perform

a platform reset.

(Desktop

Only) Reserved

LPC Interface Bridge Registers (D31:F 0)

384 Intel® ICH8 Family Datasheet

9.8.1.5 Cx-STATE_CNF—Cx State Configuration Register

(PM—D31:F0) (Mobile Only)

Offset Address: A9h Attribute: R/W

Default Value: 00h Size: 8-bit

Lockable: No Usage: ACPI, Legacy

Power Well: Core

This register is used to enable new C-state related modes.

Bit Description

7SCRATCHPAD (SP) — R/W.

6:5 Reserved

Popdown Mode Enable (PDME) — R/W. This bit is used in conjunction with the PUME

bit (D31:F0:A9h, bit 3). If PUME is 0, then this bit must also be 0.

0 = The ICH8 will not attempt to automatically return to a previous C3 or C4 state.

1 = When this bit is a 1 and Intel® ICH8 observes that there are no bus master

requests, it can return to a previous C3 or C4 state.

NOTE: This bit is separate from the PUME bit to cover cases where latency issues

permit POPUP but not PO PDOWN.

Popup Mode Enable (PUME) — R/W. When this bit is a 0, the ICH8 behaves like

ICH5, in that bus master traffic is a break event, and it will return from C3/C4 to C0

based on a break event. See Chapter 5.13.5 for additional details on this m ode.

0 = The ICH8 will treat Bus master traffic a break event, and will return from C3/C4 to

C0 based on a break event.

1 = When this bit is a 1 and ICH8 observes a bus master request, it will take the

system from a C3 or C4 state to a C2 state and auto enable bus masters. This will

let snoops and memory access occur.

Report Zero for BM_STS (BM_STS_ZERO_EN) — R/W.

0 = The ICH8 sets BM_STS (PMBASE + 00h, bit 4) if there is bus master activity from

PCI, PCI Express* and internal bus masters.

1 = When this bit is a 1, ICH8 will not set the BM_STS if t h ere is bus master activity

from PCI, PCI Express and internal bus masters.

NOTES:

1. If the BM_STS bit is already set when the BM_STS_ZERO_EN bit is set, the

BM_STS bit will remain set. Software will still need to clear the BM_STS bit.

2. It is expected that if the PUME bit (this registe r, bit 3) is set, the

BM_STS_ZERO_EN bit should also be set. Setting one without the other would

mainly be for debug or errata workaround.

3. BM_STS will be set by LPC DMA or LPC masters, even if BM_STS_ZERO_EN is

set.

1:0 Reserved

Intel® ICH8 Family Datasheet 385

LPC Interface Bridge Registers (D31:F0)

9.8.1.6 C4-TIMING_CNT—C4 Timing Control Register

(PM—D31:F0) (Mobile Only)

Offset Address: AAh Attribute: R/W

Default Value: 00h Size: 8-bit

Lockable: No Usage: ACPI, Legacy

Power Well: Core

This register is used to enable C-state related modes.

Bit Description

7 Reserved

6Slow-C4 Exit Enable —When 1, this bit enables the Slow-C4 Exit functionality.

5:4

Slow-C4 Exit Delay. This field selects the amount of time that the ICH8 waits from

deassertion of DPRSTP# until st arting the t266 timer when performing the Slow-C4

exit.

3:2

DPRSLPVR to STPCPU — R/W. This field sele cts the amount of time that the ICH8

waits for from the deassertion of DPRSLPVR to the deassertion of STP_CPU#. This

provides a programmable time for the processor’s voltage to stabilize when exiting

from a C4 state. Thus, thus changes the value for t266.

1:0

DPSLP-TO-SLP — R/W. This field selects the DPSLP# deassertion to CPU_SLP#

deassertion time (t270). Normally this value is determined by the

CPU_PLL_LOCK_TIME field in the GEN_PMCON_2 register. When this field is non-zero,

then the values in this regist er have higher priority. It is software’s responsibility to

program these fields in a consistent manner.

Bits Min Max Comment

00b 73 µs 76 µs Default. compatible with 01b setting of

t266

01b 67 µs 70 µs

10b 61 µs 64 µs compatible with 10b setting of t266

11b 46 µs 49 µs compatible with 11b setting of t266

Bits t266min t266max Comment

00b 95 µs 101 µs Default

01b 22 µs 28 µs Value used for “Fast” VRMs

10b 34 µs 40 µs Value used for “Fast” VRMs

11b Reserved

Bits t270

00b Use value is CPU_PLL_LOCK_TIME field (default is 30 µs)

01b 2 0 µs

10b 1 5 µs

11b 1 0 µs

LPC Interface Bridge Registers (D31:F 0)

386 Intel® ICH8 Family Datasheet

9.8.1.7 BM_BREAK_EN Register (PM—D31:F0) (Mobile Only)

Offset Address: ABh Attribute: R/W

Default Value: 00h Size: 8-bit

Lockable: No Usage: ACPI, Legacy

Power Well: Core

Bit Description

IDE_BREAK_EN — R/W.

0 = Parallel IDE or Serial ATA traffic will not act as a break event.

1 = Parallel IDE or Serial ATA traffic acts as a break event, even if the BM_STS-

ZERO_EN and POPUP_EN bits are set. Par allel IDE or Serial AT A master activity will

cause BM_STS to be set and will cause a break from C3/C4.

PCIE_BREAK_EN — R/W.

0 = PCI Express* traffic will not act as a break event.

1 = PCI Express traffic acts as a break event, even if the BM_STS-ZERO_EN and

POPUP_EN bits are set. PCI Express mast er activity will cause BM_STS to be set

and will cause a break from C3/C4.

PCI_BREAK_EN — R/W.

0 = PCI traffic will not act as a break event.

1 = PCI traffic acts as a break ev ent, even if th e BM_STS-Z ERO_EN and PO PUP_EN bits

are set. PCI master activity will cause BM_STS to be set and will cause a break

from C3/C4.

4:3 Reserved

EHCI_BREAK_EN — R/W.

0 = EHCI traffic will not act as a break event.

1 = EHCI traffic acts as a break event, even if the BM_STS-ZERO_EN and POPUP_EN

bits are set. EHCI master activity will cause BM_STS to be set and will cause a

break from C3/C4.

UHCI_BREAK_EN — R/W.

0 = UHCI traffic will not act as a break event.

1 = USB traffic from any of the internal UHCIs acts as a break event, even if the

BM_STS-ZERO_EN and POPUP_EN bits are set. UHCI master activity will cause

BM_STS to be set and will cause a break from C3/C4.

AZ_BREAK_EN — R/W.

0 = Intel® High Definition Audio traffic will not act as a break event.

1 = Intel High Definition Audio traffic acts as a break event, even if the BM_STS-

ZERO_EN and POPUP_EN bits are set.

Intel High Definition Audio master activity will cause BM_STS to be set and will

cause a break from C3/C4.

Intel® ICH8 Family Datasheet 387

LPC Interface Bridge Registers (D31:F0)

9.8.1.8 PMIR—Power Management Initialization Register

Offset Address: ACh Attribute: R/W, R/WL

Default Value: 00000000h Size: 32-bit

9.8.1.9 QRT_STS (PM—D31:F0): Quick Resume Technology Status Register

(Intel® ICH8DH Only)

Offset Address: B0h Attribute: R/W

Default Value: 00h Size: 8-bit

Lockable: No Usage: Quick Resume Technology

Power Well: Resume

Bit Description

31:21 Reserved

20 CF9h Global Reset (CF9GR) — R/W. When set, a CF9h write of 6h or Eh will cause a

Global Reset of both the Host and the ME partitions. If this bit is cleared, a CF9h write

of 6h or Eh will only re se t th e Host par tition.

19:0 Reserved

Bit Description

7:5 Reserved

QRT_SCI_NOW_STS— R/WC: This bit goes active when software writes a ‘1’ to

QRT_CNT1.SCI_NOW_CNT. It can be enabled to cause an SCI which will allow the QRT

software to transition the reaction to an QRT event from an SMI# handler to an SCI

handler. This bit remain s set until a 1 is written to this bit position.

Once a 1 is written to this bit position, the logic will “re-arm” to allow the bit to be set

on the next write of ‘1’ to SCI_NOW_CNT (Offset B1h:Bit 8).

QRT_PB_SCI_STS — R/WC: This bit goes active when the PWRBTN# pin goes from

high to low (post-debounce). It can be enabled to cause an SCI which will allow the

QRT softw are to see when the power button has been pressed. It is a separate bit from

PWRBTN_STS because the OS clears the PWRBTN_STS bit and does not provide any

indication to other (i.e. QRT) software.

The QRT software clears QRT_PB_SCI_STS by writing a 1 to this bit position.

2Reserved

QRT_PB_SMI_STS — R/WC: This bit goes active when the PWRBTN# pin goes from

high to low (post-debounce). It can be enabled to cause an SMI# which will allow the

QRT softw are to see when the power button has been pressed. It is a separate bit from

PWRBTN_STS because the OS clears the PWRBTN_STS bit and does not provide any

indication to other (i.e. QRT) software.

The QRT software clears QRT_PB_SMI_STS by writing a 1 to this bit position.

0 Reserved.

LPC Interface Bridge Registers (D31:F 0)

388 Intel® ICH8 Family Datasheet

9.8.1.10 QRT_CNT1 (PM—D31:F0): Q uick Resume Technology Control 1

Offset Address: B1h Attribute: R/W

Default Value: 0000h Size: 16-bit

Lockable: No U sage: Quick Resume Technology

Power Well: Resume

Bit Description

15:10 Reserved

9SMI_OPTION_CNT—R/W: When this bit is set to 1 the platform generates an SMI

when an QRT event occurs (r ather than generating a n SCI). The SMI han dler can cause

the SCI by setting the SCI_NOW_CNT.

8SCI_NOW_CNT—WO: When software writes a ‘1’ to this bit, it causes

QRT_SCI_NOW_STS (Offset B0:Bit 4) to assert (which can be enabled to cause an

SCI). This allows the SMI handler to cause the SCI.

PWRBTN_INT_EN—R/W: When this bit is set to 1, the QRT logic is enabled to

intercept the power button to cause the QRT SMI or SCI, and not immediately setting

the PWRBTN_STS bit. The QRT software will later set the PWRBTN_STS bit by setting

the PWRBTN_EVNT bit.

NOTE: This bit is effective only in S0.

PWRBTN_EVNT—WO: When this bit is set to 1 by software, the PWRBTN_STS bit is

set to 1. This allows software to communicate PWR_BTN event to OS.

NOTES:

1. Power Button override still possible

2. Software does not need to clear this bit, as it is treated as an event

5:4

QRT_STATE1_CNT[1:0]—R/W: These bits controls the QRT_STATE1 pin. The

QR T_STATE[1:0] pins can be used to control a multi color LED to indicate the platform

power states to user. If QRT_LED_OWN is 0 then these bits have no impact.

00 = Low

01 = High

10 = Blinking. Note that the blink rate is ~ 1 Hz

11 = Reserved. Software must not set this combination

3:2

QRT_STATE0_CNT[1:0]—R/W: These bits controls the QRT_STATE0 pin. The

QRT_STATE[1:0] pins can be used to control a multi-color LED to indicate the platform

power states to user. If QRT_LED_OWN is 0 then these bits have no impact.

00 = Low

01 = High

10 = Blinking. Note that the blink rate is ~ 1 Hz

11 = Reserved. Software must not set this combination

1QRT_LED_OWN—R/W: Software sets this bit to 1 to configure the multiplexed pins to

be QRT_STATE[1:0] rather than GPIO[28:27].

0 Reserved

Intel® ICH8 Family Datasheet 389

LPC Interface Bridge Registers (D31:F0)

9.8.1.11 QRT_CNT2 (PM—D31:F0): Quick Resume Technology Control 2

Offset Address: B3h Attribute: R/W

Default Value: 00h Size: 8-bit

Lockable: No Usage: Quick Resume Technology

Power Well: RTC

9.8.1.12 GPIO_ROUT—GPIO Routing Control Register

(PM—D31:F0)

Offset Address: B8h – BBh Attribute: R/W

Default Value: 00000000h Size: 32-bit

Lockable: No Power Well: Resume

Note: GPIOs that are not implemented will not have the corresponding bits implemented in

this register.

Bit Description

7:1 Reserved

QRT_EN—R/W: This bit enables Quick Resume Technology

0 = QRT Disabled

1 = QRT Enabled

When this bit is 0, the R/W bits of QRT Control Registers (QRT_CNT1, EL_CNT2)

scratchpad with no effect on hardware functions. Also, WO bits have no effect on

hardware functions.

BIOS software is expected to set this bit after booting. Default value for this bit is 0.

Bit Description

31:30 GPIO15 Route — R/W. See bits 1:0 for description.

Same pattern for GPIO14 through GPIO3

5:4 GPIO2 Route — R/W. See bits 1:0 for description.

3:2 GPIO1 Route — R/W. See bits 1:0 for description.

1:0

GPIO0 Route — R/W. GPIO[15:0] can be routed to cause an SMI or SCI when the

GPIO[n]_STS bit i s set. If the GPIO0 is not set to an input, this field has no effect.

If the system is in an S1–S5 state and if the G PE0_EN bit is also set, th en the GPIO can

cause a Wake event, even if the GPIO is NOT routed to cause an SMI# or SCI.

00 = No effect.

01 = SMI# (if corresponding ALT_GPI_SMI_EN bit is also set)

10 = SCI (if corresponding GPE0_EN bit is also set)

11 = Reserved

LPC Interface Bridge Registers (D31:F 0)

390 Intel® ICH8 Family Datasheet

9.8.2 APM I/O Decode

Table 114 shows the I/O registers associated with APM support. This register space is

enabled in the PCI Device 31: Function 0 space (APMDEC_EN), and cannot be moved

(fixed I/O location).

9.8.2.1 APM_CNT—Advanced Power Management Control Port

I/O Address: B2h Attribute: R/W

Default Value: 00h Size: 8-bit

Lockable: No Usage: Legacy Only

Power Well: Core

9.8.2.2 APM_STS—Advanced Power Management Status Port

I/O Address: B3h Attribute: R/W

Default Value: 00h Size: 8-bit

Lockable: No Usage: Legacy Only

Power Well: Core

Table 114. APM Register Map

Address Mnemonic Register Name Default Type

B2h APM_CNT Advanced Power Management Control Port 00h R/W

B3h APM_STS Advanced Power Management Status Port 00h R/W

Bit Description

7:0 Used to pass an APM command be tween the OS and the SMI handler. Writes to this

port not only store data in the APMC register, but also generates an SMI# when the

APMC_EN bit is set.

Bit Description

7:0 Used to pass data between t he OS and the SMI handler. Basically, this is a scratchpad

Intel® ICH8 Family Datasheet 391

LPC Interface Bridge Registers (D31:F0)

9.8.3 Power Management I/O Registers

Table 115 shows the registers associated with ACPI and Legacy power management

support. These registers are enabled in the PCI Device 31: Function 0 space

(PM_IO_EN), and can be moved to any I/O location (128-byte aligned). The registers

are defined to support the ACPI 2.0 specification, and use the same bit names.

Note: All reserved bits and registers will always return 0 when read, and will have no effect

when written.

Table 115. ACPI and Legacy I/O Register Map (Sheet 1 of 2)

PMBASE

+ Offset Mnemonic Register Name ACPI Pointer Default Type

00h–01h PM1_STS PM1 Status PM1a_EVT_BLK 0000h R/WC

02h–03h PM1_EN PM1 Enable PM1a_EVT_BLK+2 0000h R/W

04h–07h PM1_CNT PM1 Control PM1a_CNT_BLK 00000000h R/W, WO

08h–0Bh PM1_TMR PM1 Timer PMTMR_BLK xx000000h RO

0Ch–0Fh — Reserved — — —

10hh–13h PROC_CNT Processor Control P_BLK 00000000h R/W, RO, WO

14h LV2 Level 2 (Mobile Only) P_BLK+4 00h RO

15h–16h — Reserved (Desktop Only) — — —

15h LV3 Level 3 (Mobile Only) P_BLK+5 00h RO

16h LV4 Level 4 (Mobile Only) P_BLK+6 00h RO

17h–18h — Reserved (Desktop Only) — — —

17h LV5 Level 5 (Mobile Only) P_BLK+7 00h RO

18h LV6 Level 6 (Mobile Only) P_BLK+8 00h RO

19h — Reserved — — —

20h — Reserved (Desktop Only) — — —

20h PM2_CNT PM2 Control (Mobile On ly) PM2a_CN T_BLK 00h R/W

28h–2Bh GPE0_STS General Purpose Event 0

Status GPE0_BLK 00000000h R/WC

2Ch–2Fh GPE0_EN General Purpose Event 0

Enables GPE0_BLK+4 00000000h R/W

30h–33h SMI_EN SMI# Control and Enable — 00000000h R/W, WO,

R/W (special)

34h–37h SMI_STS SMI Status — 00000000h R/WC, RO

38h–39h ALT_GP_SMI_EN Alternate GPI SMI Enable — 0000h R/W

3Ah–3Bh ALT_GP_SMI_STS Alternate GPI SMI Status — 0000h R/WC

3Dh–41h — Reserved — — —

42h GPE_CNTL General Purpose Event

Control — 00h RO, R/W

43h — Reserved — — —

44h–45h DEVACT_STS Device Activity Status — 0000h R/WC

46h–4Fh — Reserved — — —

50h — Reserved (Desktop Only) — — —

50h SS_CNT Intel SpeedStep®

Technology Control

(Mobile On ly) 01h R/W (special)

51h–53h — Reserved — — —

LPC Interface Bridge Registers (D31:F 0)

392 Intel® ICH8 Family Datasheet

54h–5Bh — Reserved (Desktop Only) — — —

54h–57h C3_RES C3-Residency Register

(Mobile Only) — 00000000h RO, R/W

58h–5Bh C5_RES C5-Residency Register

(Mobile Only) — 00000000h RO, R/W

5Ch–5Fh — Reserved — — —

60h–7Fh — Reserved for TCO — — —

Table 115. ACPI and Legacy I/O Register Map (Sheet 2 of 2)

PMBASE

+ Offset Mnemonic Register Name ACPI Pointer Default Type

Intel® ICH8 Family Datasheet 393

LPC Interface Bridge Registers (D31:F0)

9.8.3.1 PM1_STS—Power Management 1 Stat us Register

I/O Address: PMBASE + 00h

(ACPI PM1a_EVT_BLK) Attribute: R/WC

Default Value: 0000h Size: 16-bit

Lockable: No Usage: ACPI or Legacy

Power Well: Bits 0–7: Core,

Bits 8–15: Resume,

except Bit 11 in RTC

If bit 10 or 8 in this register is set, and the corresponding _EN bit is set in the PM1_EN

already in an S0 state when the event occurs), the ICH8 will also generate an SCI if the

SCI_EN bit is set, or an SMI# if the SCI_EN bit is not set.

Note: Bit 5 does not cause an SMI# or a wake event. Bit 0 does not cause a wake event but

can cause an SMI# or SCI.

Bit Description

Wake Status (WAK_STS) — R/WC. This bit is not affected by hard resets caused

by a CF9 write, but is reset by RSMRST#.

0 = Software clears this bit by writing a 1 to it.

1 = Set by hardware when the system is in one of the sleep states (via the SLP_EN

bit) and an enabled wake event occurs. Upon setting this bit, the ICH8 will

transition the system to the ON state.

If the AFTERG3_EN bit is not set and a power failure (such as removed batteries)

occurs without the SLP_EN bit set, the system will return to an S0 state when powe r

returns, and the WAK_STS bit will not be set.

If the AFTERG3_EN bit is set and a power failure occurs without the SLP_EN bit

having been set, the system will go into an S5 state when power returns, and a

subsequent wake event will cause the WAK_STS bit to be set. Note that any

subsequent wake event would have to be caused by either a Power Button press, or

an enabled wake event that was preserved through the power failure (enable bit in

the RTC well).

PCI Express Wake Status (PCIEXPWAK_STS) — R/WC.

0 = Software clears this bit by writing a 1 to it. If the WAKE# pin is still active during

the write or the PME mes sage received indication h a s not been cleared in the

root port, then the bit will remain active (i.e. all inputs to this bit are level-

sensitive).

1 = This bit is set by hardware to indicate that the system woke due to a PCI

Express wakeup event. This wakeup event can be caused by the PCI Express

WAKE# pin being activ e or receipt of a PCI Express PME message at a root port.

This bit is set only when one of these events causes the system to transition

from a non-S0 system power state to the S0 system power state. This bit is set

independent of the s tate of the PCIEXP_WAKE_DIS bit.

Note: This bit does not itself cause a wake event or prevent entry to a sleeping

state. Th us i f the bit i s 1 an d the sy st em is put in to a sl eepin g s tate, the s ystem wil l

not automati cally wake.

13:12 Reserved

LPC Interface Bridge Registers (D31:F 0)

394 Intel® ICH8 Family Datasheet

Power Button Override Status (PRBTNOR_STS) — R/WC.

0 = Software clears this bit by writing a 1 to it.

1 = This bit is set an y time a P ower Button Override occurs (i.e., the power button is

pressed for at least 4 consecutive seconds), or due to the corresponding bit in

the SMBus slave message. The power button override causes an unconditional

transition to the S5 state, as well as sets the AFTERG# bit. The BIOS or SCI

handler clears this bit by writing a 1 to it. This bit is not affected by hard resets

via CF9h writes, and is not reset by RSMRST#. Thus, this bit is preserved

through power failures. Note that if this bit is still asserted when the global

SCI_EN is set then an SCI will be generated.

RTC Status (RTC_STS) — R/WC. This bit is not affected by hard resets caused by a

CF9 write, but is reset by RSMRST#.

0 = Software clears this bit by writing a 1 to it.

1 = Set by hardware when the RTC generates an alarm (assertion of the IRQ8#

signal). Additio nally if the R T C_EN bit (PM BASE + 02h, bit 10 ) is set, the s etting

of the RTC_STS bit will generate a wake event.

ME_STS: This bit is set when the ME generates a Non-Maskable wake event, and is

not affected by any other enable bit. When this bit is set, the Host Power

Management logic wakes to S0.

This bit is only set by hardware and can only be reset by writing a one to this bit

position. This bit is not affected by hard resets caused by a CF9 write, but is reset by

RSMRST#.

Power Button Status (PWRBTN__STS) — R/WC. This bit is not affected by hard

resets caused by a CF9 write.

0 = If the PWRBTN# signal is held low for more than 4 seconds, the hardware clears

the PWRBTN_STS bit, sets the PWRBTNOR_STS bit, and the system transitions

to the S5 state with only PWRBTN# enabled as a wake event.

This bit can be cleared by software by writing a one to the bit position.

1 = This bit is set by hardware when the PWRBT N# signal is asserted Low,

independent of any other enable bit.

In the S0 state, whil e PWRBTN_EN and PWRBT N_STS are both set, an SCI (or

SMI# if SCI_EN is not set) will be generated.

In any sleeping state S1–S5, while PWRBTN_EN (PMBASE + 02h, bit 8) and

PWRBTN_STS are both set, a wake event is generated.

NOTE: If the PWRBTN_STS bit is cleared by software while the PWRBTN# signal is

sell asserted, this will not cause the PWRBN_STS bit to be s et. The PWRBTN #

signal must go inactive and active again to set the PWRBTN_STS bit.

7:6 Reserved

Global Status (GBL _STS) — R/WC.

0 = The SCI handler should then clear this bit by writing a 1 to the bit location.

1 = Set when an SCI is generated due to BIOS wanting the attention of the SCI

handler. BIOS has a corresponding bit, BIOS_RLS, which will cause an SCI and

set this bit.

(Desktop

Only) Reserved

Bit Description

Intel® ICH8 Family Datasheet 395

LPC Interface Bridge Registers (D31:F0)

(Mobile

Only)

Bus Master Status (BM_STS) — R/WC. This bit will not cause a wake event, SCI

or SMI#.

0 = Software clears this bit by writing a 1 to it.

1 = Set by the ICH8 when a bus master requests access to main memory. Bus

master activit y is detected by any of th e PCI R equests being active, any internal

bus master request being active, the BMBUSY# signal being active, or REQ-C2

message received while in C3 or C4 state.

NOTES:

1. If the BM_STS_ZERO _EN bit is set, then this bit will generally report as a 0.

LPC DMA and bus master activity will always set the BM_STS bit, even if the

BM_STS_ZERO_EN bit is set.

3:1 Reserved

Timer Overflow Status (TMROF_STS) — R/WC.

0 = The SCI or SMI# handler clears this bit by writing a 1 to the bit location.

1 = This bit gets set any time bit 22 of the 24- b it timer goes high (bits are

numbered from 0 to 23). This will occur every 2.3435 seconds. When the

TMROF_EN bit (PMBA SE + 02h, bit 0) i s set, then the setting of th e TMROF_STS

bit will additionally generate an SCI or SMI# (depending on the SCI_EN).

Bit Description

LPC Interface Bridge Registers (D31:F 0)

396 Intel® ICH8 Family Datasheet

9.8.3.2 PM1 _EN—Power Management 1 Enable Register

I/O Address: PMBASE + 02h

(ACPI PM1a_EVT_BLK + 2) Attribute: R/W

Default Value: 0000h Size: 16-bit

Lockable: No Usage: ACPI or Legacy

Power Well: Bits 0–7: Core,

Bits 8–9, 11–15: Resume,

Bit 10: RTC

Bit Description

15 Reserved

PCI Express* Wake Disable(PCIEXPWAK_DIS) — R/W. Modification of this bit has

no impact on the value of the PCIEXP_WAKE_STS bit.

0 = Inputs to the PCIEXP_WAKE_STS bit in the PM1 Status register enabled to wake

the system.

1 = Inputs to the PCIEXP_WAKE_STS bit in the PM1 Status register disabled from

waking the system

13:11 Reserved

RTC Event Enable (RTC_EN) — R/W. This bit is in the RT C well to allow an RT C event

to wake after a power failure. This bit is not cleared by any reset other than RTCRST#

or a Power Button Override event.

0 = No SCI (or SMI#) or wake event is generated then RTC_STS (PMBASE + 00h, bit

10) goes active.

1 = An SCI (or SMI#) or wake event will occur when this bit is set and the RTC_STS bit

goes active.

9 Reserved.

Power Button Enable (PWR BTN_EN) — R/W. This bit is use d to enable the setting

of the PWRBTN_STS bit to generate a power management event (SMI#, SCI).

PWRBTN_EN has no effect on the PWRBTN_STS bit (PMBASE + 00h, bit 8) being set by

the assertion of the power button. The Power Button is always enable d a s a Wake

event.

0 = Disable.

1 = Enable.

7:6 Reserved.

Global Enable (GBL_EN) — R/W. When both the GBL_EN and the GBL_STS bit

(PMBASE + 00h, bit 5) are set, an SCI is raised.

0 = Disable.

1 = Enable SCI on GBL_STS going active.

4:1 Reserved.

Timer Overflow Interrupt Enable (TMROF_EN) — R/W. Works in conjunction with

the SCI_EN bit (PMBASE + 04h, bit 0) as described below:

TMROF_EN SCI_EN Effect when TMROF_STS is set

0 X No SMI# or SCI

10 SMI#

11 SCI

Intel® ICH8 Family Datasheet 397

LPC Interface Bridge Registers (D31:F0)

9.8.3.3 PM1_CNT—Power Management 1 C ontrol

I/O Address: PMBASE + 04h

(ACPI PM1a_CNT_BLK) Attribute: R/W, WO

Default Value: 00000000h Size: 32-bit

Lockable: No Usage: ACPI or Legacy

Power Well: Bits 0–7: Core,

Bits 8–12: RTC,

Bits 13–15: Resume

Bit Description

31:14 Reserved.

13 Sleep Enable (SLP_EN) — WO. Setting th is bit causes the system to seque nce into

the Sleep state defined by the SLP_TYP field.

12:10

Sleep Type (SLP_TYP) — R/W. This 3-bit field defines the type of Sleep the system

should enter when the SLP_EN bit is set to 1. These bits are only reset by RTCRST#.

9:3 Reserved.

Global Release (GBL_RLS) — WO.

0 = This bit always reads as 0.

1 = ACPI software writes a 1 to this bit to rai se an even t to the BIOS . BIOS softwa re

has a corresponding enable and status bits to control its ability to receive ACPI

events.

(Desktop

Only) Reserved

(Mobile

Only)

Bus Master Reload (BM_RLD) — R/W. This bit is treated as a scratchpad bit. This

bit is reset to 0 by PLTRST#

0 = Bus master requests will not cause a break from the C3 state.

1 = Enable Bus Master requests (internal, external or BMBUSY#) to cause a break

from the C3 state.

If software fails to set this bit before going to C3 state, ICH8 will still return to a

snoopable state from C3 or C4 states due to bus master activity.

SCI Enable (SCI_EN) — R/W. Selects the SCI interrupt or the SMI# interrupt for

various events includin g the bits in the PM1 _STS register (bit 10, 8, 0), and bits in

GPE0_STS.

0 = These events will generate an SMI#.

1 = These events will generate an SCI.

Code Mas ter Inter rupt

000b ON: Typically maps to S0 state.

001b Asserts STPCLK#. Puts processor in Stop-Grant state. Optional to

assert CPUSLP# to put processor in sleep state: Typically maps to S1

state.

010b Reserved

011b Reserved

100b Reserved

101b Suspend-To-RAM. Assert SLP_S3#: Typically maps to S3 state.

110b Suspend- To-Disk. Assert SLP_S3#, and SLP_S4#: Typically maps to S4

state.

111b Soft Off. Assert SLP_S3#, SLP_S4#, and SLP_S5#: Typically maps to

S5 state.

LPC Interface Bridge Registers (D31:F 0)

398 Intel® ICH8 Family Datasheet

9.8.3.4 PM1_TMR—Power Management 1 Ti mer Register

I/O Address: PMBASE + 08h

(ACPI PMTMR_BLK)Attribute: RO

Default Value: xx000000h Size: 32-bit

Lockable: No Usage: ACPI

Power Well: Core

9.8.3.5 PROC_CNT—Processor Control Register

I/O Address: PMBASE + 10h

(ACPI P_BLK) Attribute: R/W, RO, WO

Default Value: 00000000h Size: 32-bit

Lockable: No (bits 7:5 are write once)Usage: ACPI or Legacy

Power Well: Core

Bit Description

31:24 Reserved

23:0

Timer Value (TMR_VA L ) — RO. Returns the running count of the PM timer. This

counter runs off a 3.579545 MHz clock (14.31818 MHz divided by 4). It is reset to 0

during a PCI reset, and then co ntinues counting as long as the system is in the S0

state. After an S1 state, the counter will not be reset (it wi ll continue counting from the

last value in S0 state.

Anytime bit 22 of the timer goes HIGH to LOW (bits referenced from 0 to 23), the

TMROF_STS bit (PMBASE + 00h, bit 0) is set. The High-to-Low transition will occur

every 2.3435 seconds. If the TMROF_EN bit (PMBASE + 02h, bit 0) is set, an SCI

interrupt is also generated.

Bit Description

31:18 Reserved

Throttle Status (THTL_STS) — RO.

0 = No clock throttling is occurring (maximum processor performance).

1 = Indicates that the clo ck state machine is throttli ng the processor performance. Thi s

could be due to the THT_EN bit or the FORCE_THTL bit being set.

16:9 Reserved

Force Thermal Throttling (FORCE_THTL) — R/W. Software can set this bit to force

the thermal throttling function.

0 = No forced throttling.

1 = Throttling at the duty cycle specified in THRM_DTY starts immediately, and no

SMI# is generated.

Intel® ICH8 Family Datasheet 399

LPC Interface Bridge Registers (D31:F0)

7:5

THRM_DTY — WO. This write-once field determines the duty cycle of the throttling

when the FORCE_THTL bit is set. The duty cycle indicates the approximate percentage

of time the STPCLK# signal is asserted while in the throttle mo de. The STPCLK#

throttle period is 1024 PCICLKs. Note that the throttling only occurs if the system is in

the C0 state. For mobile components, if in the C2, C3, or C4 state, no throttling occurs.

Once the THRM_DTY field is written, any subsequent writes will have no effect until

PLTRST# goes active.

THTL_EN — R/W. When set and the system is in a C0 state, it enables a processor-

controlled STPCLK# throttling. The duty cycle is selected in the THTL_DTY field.

0 = Disable

1 = Enable

3:1

THTL_DTY — R/W. This field determines the duty cycle of the throttling when the

THTL_EN bit is set. The duty cycle indicates the approximate percentage of time the

STPCLK# signal is asserted (low) while in the throttle mode. The STPCLK# throttle

period is 1024 PCICLKs.

0 Reserved

Bit Description

THRM_DTY Throttle Mod e PCI Clocks

000b 50% (Default) 512

001b 87.5% 896

010b 75.0% 768

011b 62.5% 640

100b 50% 512

101b 37.5% 384

110b 25% 256

111b 12.5% 128

THTL_DTY Throttle Mode PCI Clocks

000b 50% (Default) 512

001b 87.5% 896

010b 75.0% 768

011b 62.5% 640

100b 50% 512

101b 37.5% 384

110b 25% 256

111b 12.5% 128

LPC Interface Bridge Registers (D31:F 0)

400 Intel® ICH8 Family Datasheet

9.8.3.6 LV2 — Level 2 Register (Mobile Only)

I/O Address: PMBASE + 14h

(ACPI P_BLK+4) Attribute: RO

Default Value: 00h Size: 8-bit

Lockable: No Usage: ACPI or Legacy

Power Well: Core

NOTE: This register should not be used by Intel® iA64 processors or systems with more than 1

logical processor, unless appropriate semaphoring software has been put in place to ensure

that all threads/processors are ready for the C2 state when the read to th is regis ter occ urs

9.8.3.7 LV3—Level 3 Register (Mobile Only)

I/O Address: PMBASE + 15h (ACPI P_BLK + 5)

Attribute: RO

Default Value: 00h Size: 8-bit

Lockable: No Usage: ACPI or Legacy

Power Well: Core

NOTE: If the C4onC3_EN bit is set, reads this register will initiate a LVL4 transition rather than a

LV L3 transition. In the event that software attempts to simultaneously read the LVL2 and

L VL3 registers (which is invalid), the ICH8 will ignore the L VL3 read, and only perform a C2

transition.

NOTE: This register should not be used by iA64 processors or systems with more than 1 logical

processor, unless appropriate semaphoring software has been put in place to ensure that

all threads/processors are ready for the C3 state when the read to this register occurs.

9.8.3.8 LV4—Level 4 Register (Mobile Only)

I/O Address: PMBASE + 16h (ACPI P_BLK + 6)

Attribute: RO

Default Value: 00h Size: 8-bit

Lockable: No Usage: ACPI or Legacy

Power Well: Core

NOTE: This register should not be used by iA64 processors or systems with more than 1 logical

processor, unless appropriate semaphoring software has been put in place to ensure that

all threads/processors are ready for the C4 state when the read to this register occurs.

Bit Description

7:0

Reads to this register return all 0s, writes to this register have no effect. Reads to this

cause the STPCLK# signal to go active, and stay active until a break event occurs.

Throttling (due either to THTL_EN or FORCE_THTL) will be ignored.

Bit Description

7:0 Reads to this register return all 0s, writes to this register have no effect. Reads to this

persists until a break event occurs.

Bit Description

7:0 Reads to this register return all 0s, writes to this register have no effect. Reads to this

persists until a break event occurs.

Intel® ICH8 Family Datasheet 401

LPC Interface Bridge Registers (D31:F0)

9.8.3.9 LV5—Level 5 Register (Mobile Only)

I/O Address: PMBASE + 17h (ACPI P_BLK + 7)

Attribute: RO

Default Value: 00h Size: 8-bit

Lockable: No Usage: ACPI or Legacy

Power Well: Core

NOTE: This register should not be used by IA-64 processors or systems with more than 1 logical processor,

unless appropriate semaphoring software has been put in place to ensure that all threads/processors

are ready for the C5 state when the read to this register occurs.

9.8.3.10 LV6—Level 6 Register (Mobile Only)

I/O Address: PMBASE + 18h (ACPI P_BLK + 8)

Attribute: RO

Default Value: 00h Size: 8-bit

Lockable: No Usage: ACPI or Legacy

Power Well: Core

NOTE: This register should not be used by IA-64 processors or systems with more than 1 logical

processor, unless appropriate semaphoring software has been put in place to ensure that

all threads/processors are ready for the C6 state when the read to this register occurs.

9.8.3.11 PM2_CNT—Power Management 2 Control (Mobile Only)

I/O Address: PMBASE + 20h

(ACPI PM2_BLK) Attribute: R/W

Default Value: 00h Size: 8-bit

Lockable: No Usage: ACPI

Power Well: Core

Bit Description

7:0 Reads to this register return all 0’s, writes to this registe r have no effect. Reads to this

persists until a break event occurs.

Bit Description

7:0 Reads to this register return all 0’s, writes to this registe r have no effect. Reads to this

persists until a break event occurs.

Bit Description

7:1 Reserved

Arbiter Disable (ARB_DIS) — R/W This bit is essentially just a scratchpad bit for

legacy software compatibility. Software typically sets this bit to 1 prior to ente ring a C3

or C4 state. When a transition to a C3 or C4 state occurs, ICH8 will automatically

prevent any internal or external non-Isoch bus masters from initiating any cycles up to

the (G)MCH. This blocking starts immediately upon the ICH8 sending the Go-C3

message to the (G)MCH. The blocking stops when the Ack-C2 message is received.

Note that this is not really blocking, in that messages (such as from PCI Express*) are

just queued and held pending.

LPC Interface Bridge Registers (D31:F 0)

402 Intel® ICH8 Family Datasheet

9.8.3.12 GPE0_STS—General Purpose Event 0 Status Register

I/O Address: PMBASE + 28h

(ACPI GPE0_BLK) Attribute: R/WC

Default Value: 00000000h Size: 32-bit

Lockable: No Usage: ACPI

Power Well: Resume

This register is symmetrical to the General Purpose Ev ent 0 Enab l e Register. Unless

indicated otherwise below, if the corresponding _EN bit is set, then when the _STS bit

get set, the ICH8 will generate a W ak e Event. Once back in an S0 state (or if already in

an S0 state when the event occurs), the ICH8 will also generate an SCI if the SCI_EN

bit is set, or an SMI# if the SCI_EN bit (PMBASE + 04h, bit 0) is not set. Bits 31:16 are

reset by a CF9h write; bits 15:0 are not. All are reset by RSMRST#.

Bit Description

31:16

GPIOn_STS — R/WC.

0 = Software clears this bit by writing a 1 to it.

1 = These bits are set any time the corresponding GPIO is set up as an input and

the corresponding GPIO signal is high (or low if the corresponding GP_INV bit

is set). If the corresponding enable bit is set in the GPE0_EN register, then

when the GPIO[n]_STS bit is set:

• If the system is in an S1–S5 state, the event will also wake the system.

• If the system is in an S0 state (or upon waking back to an S0 state), a SCI will be caused

depending on the GPIO_ROUT bits (D31:F0:B8h, bits 31:30) for the corresponding GPI.

NOTE: Mapping is as follows: bit 31 corresponds to GPIO[15]... and bit 16

corresponds to GPIO[0].

15 Reserved

USB4_STS — R/WC.

0 = Disable.

1 = Set by hardware and can be reset by writing a one to this bit position or a

resume well reset. This bit is set when USB UHCI controller #4 needs to cause

a wake. Additionally if the USB4_EN bit is set, the se tting of the USB4_ST S bit

will generate a wake event.

PME_B0_STS — R/WC. This bit will be set to 1 by the ICH8 when any internal

device with PCI Power Management capabilities on bus 0 asserts the equivalent of

the PME# signal . Addit ion all y, if the PME_B0_ EN bit is se t, and the system is in an

S0 state, then th e setting of the PME_B0_STS bit will generate an SCI (or SMI# if

SCI_EN is not set). If the PME_B0_STS bit is set, and the system is in an S1–S4

state (or S5 state due to SLP_TYP and SLP_EN), then the s etting of the

PME_B0_STS bit will generate a wake event, and an SCI (or SMI# if SCI_EN is not

set) will be generated. If the system is in an S5 state due to power button

override, then the PME_B0 _STS bit will not cause a wake event or SCI.

The default for this bit is 0. Writing a 1 to this bit position clears this bit.

Note: On ICH8, HD audio wake events are changed to be reported in this bit.

ME “maskable” wake events are also reported in this bit.

USB3_STS — R/WC.

0 = Disable.

1 = Set by hardware and can be reset by writing a one to this bit position or a

resume well reset. This bit is set when USB UHCI controller #3 needs to cause

a wake. Additionally if the USB3_EN bit is set, the se tting of the USB3_ST S bit

will generate a wake event.

Intel® ICH8 Family Datasheet 403

LPC Interface Bridge Registers (D31:F0)

PME_STS — R/WC.

0 = Software clears this bit by writing a 1 to it.

1 = Set by hardware when the PME# signal goes active. Additionally, if the

PME_EN bit is set, and the system is in an S0 state, then the setting of the

PME_STS bit will generate an SCI or SMI# (if SCI_EN is not set). If the

PME_EN bit is set, and the system is in an S1–S4 state (or S5 state due to

setting SLP_TYP and SLP _EN), then the setting of the PME_STS bit will

generate a wak e event, and an SCI will be generated. If the system is in an S5

state due to power button override or a power failure, then PME_STS will not

cause a wake event or SCI.

(ICH8

Base,

ICH8R,

ICH8DO

Only)

Reserved

(ICH8DH

Only)

QRT_SCI_STS — R/WC: In Desktop Mode, when Quick Resume Technology

feature is enabled, this bit will be set by hardware when the SCI_NOW_CNT or

QRT_PB_SCI_STS bit goes high. Software clears the bit by writing a 1 to the bit

position.

In Desktop Mode, when QRT feature is disabled, this bit will be treated as

Reserved.

(Mobile

Only)

BATLOW_STS — R/WC. Software clears this bit by writing a 1 to it.

0 = BATLOW# Not asserted

1 = Set by hardware when the BATLOW# signal is asserted.

PCI_EXP_STS — R/WC.

0 = Software clears this bit by writing a 1 to it.

1 = Set by hardware to indicate that:

• The PME event message was received on one or more of the PCI Express* ports

• An Assert PMEGPE message received from the (G)MCH via DMI

NOTES:

1. The PCI WAKE# pin has no impact on this bit.

2. If the PCI_EXP_STS bit went active due to an Assert PMEGPE message,

then a Deassert PMEGPE message must be received prior to the software

write in order for the bit to be cleared.

3. If the bit is not cleared and the corresponding PCI_EXP_EN bit is set, the

level-triggered SCI will remain active.

4. A race condition exists where the PCI Express device sends another PME

message because the PCI Express device was not serviced within the time

when it must resend the message. This may result in a spurious interrupt,

and this is comprehended and approved by the PCI Express* Specification,

Revision 1.0a. The window for this race condition is approximately 95-105

milliseconds.

8RI_STS — R/WC.

0 = Software clears this bit by writing a 1 to it.

1 = Set by hardware when the RI# input signal goes active.

Bit Description

LPC Interface Bridge Registers (D31:F 0)

404 Intel® ICH8 Family Datasheet

SMBus Wake Status (SMB_WAK_STS) — R/WC. The SMBus controller can

independently cause an SMI# or SCI, so this bit does not need to do so (unlike the

other bits in this register). Software clears this bit by writing a 1 to it.

0 = Wake event Not caused by the ICH8’s SMBus logic.

1 = Set by hardware to indicate that the wake event was caused by the ICH8’s

SMBus logic.This bit will be set by the WAKE/SMI# command type, even if the

system is already awake. The SMI handler should then clear this bit.

NOTES:

1. This bit is set by the SMBus slave command 01h (Wake/SMI#) even when

the system is in the S0 state. Therefore, to avoid an instant wake on

subsequent transitions to sleep states, software must clear this bit after

each reception of the Wake/SMI# command or just prior to entering the

sleep state.

2. If SMB_WAK_STS is set due to SMBus slave receiving a message, it will be

cleared by internal logic when a THRMTRIP# even t happens or a Power

Button Override event. However, THRMTRIP# or Power Button Override

event will not clear SMB_WAK_STS if it is set due to SMBALERT# signal

going active.

3. The SMBALER T_STS bit (D31:F 3:I/O Offset 00h:Bit 5) should be cleared by

software before the SMB_WAK_STS bit is cleared.

6TCOSCI_STS — R/WC. Software clears this bit by writing a 1 to it.

0 = TOC logic or thermal sensor logic did Not cause SCI.

1 = Set by hardware when the TCO logic or thermal sensor logic causes an SCI.

USB5_STS— R/WC. Software clears this bit by writing a 1 to it.

0 = USB UHCI controller 5 does NOT need to cause a wake.

1 = Set by hardware when USB UHCI controller 5 needs to cause a wake. Wake

event will be generated if the corresponding USB2_EN bit is set.

USB2_STS — R/WC. Software clears this bit by writing a 1 to it.

0 = USB UHCI controller 2 does Not need to cause a wake.

1 = Set by hardware when USB UHCI controller 2 needs to cause a wake. Wake

event will be generated if the corresponding USB2_EN bit is set.

USB1_STS — R/WC. Software clears this bit by writing a 1 to it.

0 = USB UHCI controller 1 does Not need to cause a wake.

1 = Set by hardware when USB UHCI controller 1 needs to cause a wake. Wake

event will be generated if the corresponding USB1_EN bit is set.

2SWGPE_STS — R/WC.

The SWGPE_CTRL bit (bit 1 of GPE_CTRL reg) acts as a level input to this bit.

HOT_PLUG_STS — R/WC.

0 = This bit is cleared by writing a 1 to this bit position.

1 = When a PCI Express* Hot-Plug event occurs. This will cause an SCI if the

HOT_PLUG_EN bit is set in the GEP0_EN register.

Thermal Interrupt Status (THRM_STS) — R/WC. Software clears this bit by

writing a 1 to it.

0 = THRM# signal Not driven active as defined by the THRM_POL bit

1 = Set by hardware anytime the THRM# signal is driven active as defined by the

THRM_POL bit. Additionally, if the THRM_EN bit is set, then the setting of the

THRM_STS bit will also generate a power management event (SCI or SMI#).

Bit Description

Intel® ICH8 Family Datasheet 405

LPC Interface Bridge Registers (D31:F0)

9.8.3.13 GPE0_EN—General Purpose Event 0 Enables Register

I/O Address: PMBASE + 2Ch

(ACPI GPE0_BLK + 4) Attribute: R/W

Default Value: 00000000h Size: 32-bit

Lockable: No Usage: ACPI

Power Well: Bits 0–7, 9, 12, 14–31 Resume,

Bits 8, 10–11, 13 RTC

This register is symmetrical to the General Purpose Event 0 Status R egister. All the bits

in this register should be cleared to 0 based on a Power Button Override or processor

Thermal Trip event. The resume well bits are all cleared by RSMRST#. Th e R TC s ell bits

are cleared by RTCRST#.

Bit Description

31:16

GPIn_EN — R/W. These bits enable the corresponding GPI[n]_STS bits being set to

cause a SCI, and/or wake event. These bits are cleared by RSMRST#.

NOTE: Mapping is as follows: bit 31 corresponds to GPIO15... and bit 16

corresponds to GPIO0.

15 Reserved

USB4_EN — R/W.

0 = Disable.

1 = Enable the se tting of the USB4_S TS bit to generate a wake event. The

USB4_STS bit is set anytime USB UHCI controller #4 signals a wake event.

Break events are handled via the USB interrupt.

PME_B0_EN — R/W.

0 = Disable

1 = Enables the setting of the PME_B0_STS bit to generate a wak e event and/or an

SCI or SMI#. PME_ B0_STS can be a wak e event from the S1– S4 states, or from

S5 (if entered via SLP_TYP and SLP_EN) or power failure, but not Power Button

Override. This bit defaults to 0.

NOTE: It is only cleared by Software or RTCRST#. It is not cleared by CF9h writes.

USB3_EN — R/W.

0 = Disable.

1 = Enable the se tting of the USB3_S TS bit to generate a wake event. The

USB3_STS bit is set anytime USB UHCI controller #3 signals a wake event.

Break events are handled via the USB interrupt.

PME_EN — R/W.

0 = Disable.

1 = Enables the setting of the PME_STS to generate a wake event and/or an SCI.

PME# can be a wake event from the S1 – S4 state or from S5 (if entered via

SLP_EN, but not power button override).

(Desktop

Only)

QRT_SCI_EN — R/W. In Desktop Mode this bit enables the QR T_SCI_STS si gnal to

cause an SCI (depending on the SCI_EN bit) when it is asserted

(Mobile

Only)

BATLOW_EN — R/W.

0 = Disable.

1 = Enables the BATLOW# signal to cause an SMI# or SCI (depending on the

SCI_EN bit) when it goes low. This bit does not prevent the BATLOW# signal

from inhibiting the wake event.

LPC Interface Bridge Registers (D31:F 0)

406 Intel® ICH8 Family Datasheet

PCI_EXP_EN — R/W.

0 = Disable SCI generation upon PCI_EXP_STS bit being set.

1 = Enables ICH8 to cause an SCI when PCI_EXP_STS bit is set. This is used to

allow the PCI Express* ports, including the link to the (G)MCH, to cause an SCI

due to wake/PME events.

RI_EN — R/W. The v alue of this bit will be maintained through a G3 state and is not

affected by a hard reset caused by a CF9h write.

0 = Disable.

1 = Enables the setting of the RI_STS to generate a wake event.

7 Reserved

6TCOSCI_EN — R/W.

0 = Disable.

1 = Enables the setting of the TCOSCI_STS to generate an SCI.

5USB5_EN — R/W.

0 = Disable.

1 = Enables the setting of the USB5_STS to generate a wake event.

4USB2_EN — R/W.

0 = Disable.

1 = Enables the setting of the USB2_STS to generate a wake event.

3USB1_EN — R/W.

0 = Disable.

1 = Enables the setting of the USB1_STS to generate a wake event.

SWGPE_EN— R/W. This bit allows software to co ntrol the assertion of SWGPE_STS

bit. This bit This bit, when set to 1, enable s the SW GPE function. If SWGP E_CTRL is

written to a 1, hardware will set SWGPE_STS (acts as a level input)

If SWGPE_STS, SWGPE_EN, and SCI_EN are all 1's, an SCI will be generated

If SWGPE_STS = 1, SWGPE_EN = 1, SCI_EN = 0, and GBL_SMI_EN = 1 then an

SMI# will be generated

HOT_PLUG_EN — R/W.

0 = Disables SCI ge neration upon the HOT_PLUG_STS bit being set.

1 = Enables the ICH8 to cause an SCI when the HOT_PLUG_STS bit is set. Thi s is

used to allow the PCI Express ports to cause an SCI due to hot-plug events.

THRM_EN — R/W.

0 = Disable.

1 = Active assertion of the THRM# signal (as defined by the THRM_POL bit) will set

the THRM_STS bit and generate a power management event (SCI or SMI).

Bit Description

Intel® ICH8 Family Datasheet 407

LPC Interface Bridge Registers (D31:F0)

9.8.3.14 SMI_EN—SMI Control and Enable Register

I/O Address: PMBASE + 30h Attribute: R/W, R/W (special), WO

Default Value: 00000000h Size: 32 bit

Lockable: No Usage: ACPI or Legacy

Power Well: Core

Note: This register is symmetrical to the SMI status register.

Bit Description

31:26 Reserved

25 EL_SMI_EN — R/W.

0 = Disable

1 = Software sets this bit to enable Energy Lake logic to cause SMI#

24:19 Reserved

18 INTEL_USB2_EN — R/W.

0 = Disable

1 = Enables Intel -Specific USB2 SMI logic to cause SMI#.

17 LEGACY_USB2_EN — R/W.

0 = Disable

1 = Enables legacy U S B2 logic to cause SMI#.

16:15 Reserved

PERIODIC_EN — R/W.

0 = Disable.

1 = Enables the ICH8 to generate an SMI# when the PERIODIC_S TS bit (PMBASE +

34h, bit 14) is set in the SMI_STS register (PMBASE + 34h).

TCO_EN — R/W.

0 = Disables TCO logic generating an SMI#. Note that if the NMI2SMI_EN bit is set,

SMIs that are caused by re-routed NMIs will not be gated by the TCO_EN bit. Even

if the TCO_EN bit is 0, NMIs will still be routed to cause SMIs.

1 = Enables the TCO logic to generate SMI#.

NOTE: This bit cannot be written once the TCO_LOCK bit is se t.

12 Reserved

MCSMI_ENMi cr ocontroller SM I Ena b le (MCSMI_EN) — R/W.

0 = Disable.

1 = Enables ICH8 to trap accesses to the microcontroller range (62h or 66h) and

generate an SMI#. Note that “trapped’ cycles will be claimed by the ICH8 on PCI,

but not forwarded to LPC.

10:8 Reserved

BIOS Release (BIOS_RLS) — WO.

0 = This bit will always return 0 on reads. Writes of 0 to this bit have no effect.

1 = Enables the generation of an SCI interrupt for ACPI software when a one is written

to this bit position by BIOS software.

NOTE: GBL_STS being set will cause an SCI, even if the SCI_EN bit is not set.

Software must take great care not to set the BIOS_RLS bit (which causes

GBL_STS to be set) if the SCI handler is not in place.

LPC Interface Bridge Registers (D31:F 0)

408 Intel® ICH8 Family Datasheet

Software SMI# Timer Enable (SWSMI_TMR_EN) — R/W.

0 = Disable. Clearing the SWSMI_TMR_EN bit before the timer expires will reset the

timer and the SMI# will not be generated.

1 = Starts Software SMI# Timer. When the SWSMI timer expires (the timeout period

depends upon the SWSMI_RATE_SEL bit setting), SWSMI_TMR_STS is set and an

SMI# is generated. SWSMI_TMR_EN stays set until cleared by software.

5APMC_EN — R/W.

0 = Disable. Writes to the APM_CNT register will not cause an SMI#.

1 = Enables writes to the APM_CNT register to cause an SMI#.

SLP_SMI_EN — R/W.

0 = Disables the generation of SMI# on SLP_EN. Note that this bit must be 0 before

the software attempts to transition the system into a sleep state by writin g a 1 to

the SLP_EN bit.

1 = A write of 1 to the SLP_EN bit (bit 13 in PM1_CNT register) will generate an SMI#,

and the system will not transition to the sleep state based on that write to the

SLP_EN bit.

3LEGACY_USB_EN — R/W.

0 = Disable.

1 = Enables legacy USB circuit to cause SMI#.

BIOS_EN — R/W.

0 = Disable.

1 = Enables the generation of SMI# when ACPI software writes a 1 to the GBL_RLS bit

(D31:F0:PMBase + 04h:bit 2). Note that if the BIOS_STS bit (D31:F0:PMBase +

34h:bit 2), which ge ts set when softw are writes 1 to GBL_RLS bit, is already a 1 at

the time that BIOS_EN beco mes 1, an SMI# will be generated when BIOS_EN gets

set.

End of SMI (EOS) — R/W (special). This bit controls the arbitration of the SMI signal

to the processor. This bit must be set for the ICH8 to assert SMI# low to the processor

after SMI# has been asserted previously.

0 = Once the ICH8 asserts SMI# low, the EOS bit is automatically cleared.

1 = When this bit is set to 1, SMI# signal will be deasserted fo r 4 PCI clocks before i ts

assertion. In the SMI handler, the processor should clear all pending SMIs (by

servicing them and then clearing their respectiv e status bits), se t the EOS bi t, and

exit SMM. This will allow the SMI arbiter to re- assert SMI upon detection of an SMI

event and the setting of a SMI status bit.

NOTE: ICH8 is able to generate 1s t SMI after reset e ven though EOS bit is not set.

Subsequent SMI require EOS bit is set.

GBL_SMI_EN — R/W.

0 = No SMI# will be generated by ICH8. This bit is reset by a PCI reset event.

1 = Enables the generation of SMI# in the system upon any enabled SMI event.

NOTE: When the SMI_LOCK bit is set, this bit cannot be changed.

Bit Description

Intel® ICH8 Family Datasheet 409

LPC Interface Bridge Registers (D31:F0)

9.8.3.15 SMI_STS—SMI Status Register

I/O Address: PMBASE + 34h Attribute: RO, R/WC

Default Value: 00000000h Size: 32-bit

Lockable: No Usage: ACPI or Legacy

Power Well: Core

Note: If the corresponding _EN bit is set when the _STS bit is set, the ICH8 will cause an

SMI# (except bits 8–10 and 12, which do not need enable bits since they are logic ORs

of other registers that have enable bits). The ICH8 uses the same GPE0_EN register

(I/O address: PMBase+2Ch) to enable/disable both SM I and ACPI SCI g eneral purpose

input events. ACPI OS assumes that it owns the entire GPE0_EN register per ACPI spec.

Problems arise when some of the general-purpose inputs are enabled as SMI by BIOS,

and some of the general purpose inputs are enabled for SCI. In this case ACPI OS turns

off the enabled bit for any GPIx inpu t sign als that are not indicated as SCI general-

purpose events at boot, and exit from sleeping states. BIOS should define a dummy

control method which prevents the ACPI OS from clearing the SMI GPE0_EN bits.

Bit Description

31:27 Reserved

26 SPI_STS — RO. This bit will be set if the SPI logic is generating an SMI#. This bit is

read only because the sticky status and enable bits associated with this function are

located in the SPI registers.

25 EL_SMI_STS — RO . This bit will be set if the Energy Lake logic is generating an SMI#.

Writing a 1 to this bit clears this bit to ‘0’.

24:22 Reserved

MONITOR_STS — RO. This bit will be set if the Trap/SMI logic has caused the SMI.

This will occur when the processor or a bus master accesses an assigned register (or a

sequence of accesses). See Section 7.1.44 through Section 7.1.47 for details on the

specific cause of the SMI.

20 PCI_EXP_SMI_STS — RO. PCI Express* SMI event occurred. This could be due to a

PCI Express PME event or Hot-Plug event.

19 Reserved

INTEL_USB2_STS — RO. This non-sticky read-only bit is a logical OR of each of the

SMI status bits in the Intel-Specific USB2 SMI Status Register ANDed with the

corresponding enable bits. This bit will not be active if the enable bits are not set.

Writes to this bit will have no effect.

All integrated USB2 Host Controllers are represented with this bit.

LEGACY_USB2_STS — RO. Thi s non- stic ky read- only bi t is a logi cal O R of e ach of the

SMI status bits in the USB2 Legacy Support Register ANDed with the corresponding

enable bits. This bit will not be active if the enable bits are not set. Writes to this bit will

have no effect.

All integrated USB2 Host Controllers are represented with this bit.

LPC Interface Bridge Registers (D31:F 0)

410 Intel® ICH8 Family Datasheet

SMBus SMI Status (SMBUS_SMI_ST S ) — R/WC. Software clears this bit by writing

a 1 to it.

0 = This bit is set from the 64 kHz clock domain used by the SMBus. Software must

wait at least 15.63 us after the initial assertion of this bit before clearing it.

1 = Indicates that the SMI# was caused by:

1. The SMBus Slave receiving a message that an SMI# should be caused, or

2. The SMBALERT# signal goes active and the SMB_SMI_EN bit is set and the

SMBALERT_DIS bit is cleared, or

3. The SMBus Slave receiving a Host Notify message and the

HOST_NOTIFY_INTREN and the SMB_SMI_EN bits are set, or

4. The ICH8 detecting the SMLINK_SLAVE_SMI command while in the S0 state.

SERIRQ_SMI_STS — RO.

0 = SMI# was not caused by the SERIRQ decoder.

1 = Indicates that the SMI# was caused by the SERIRQ decoder.

NOTE: This is not a sticky bit

PERIODIC_STS — R/WC. Software clears this bit by writing a 1 to it.

0 = Software clears this bit by writing a 1 to it.

1 = This bit is set at the rate determined by the PER_SMI_SEL bits. If the

PERIODIC_EN bit (PMBASE + 30h, bit 14) is also set, the ICH8 generates an SMI#.

TCO_STS — R/WC. Software clears this bit by writing a 1 to it.

0 = SMI# not caused by TCO logic.

1 = Indicates the SMI# was caused by the TCO logic. Note that this is not a wake

event.

Device Monitor Status (DEVMON_STS) — RO.

0 = SMI# not caused by Device Monitor.

1 = Set if bit 0 of the DEV ACT_STS registe r (PMBASE + 44h) is set. The bit is not sticky,

so writes to this bit will have no effect.

Microcontroller SMI# Status (MCSMI_STS) — R/WC. Software clears this bit by

writing a 1 to it.

0 = Indicates that there has been no access to the power management microcontroller

range (62h or 66h).

1 = Set if there has been an access to the power management microcontroller range

(62h or 66h) and the Microcontroller Decode Enable #1 bit in the LPC Bridge I/O

Enables configuration register is 1 (D31:F0:Offset 82h:bit 11). Note that this

implementation assumes that the Microcontroller is on LPC. If this bit is set, and

the MCSMI_EN bit is also set, the ICH8 will generate an SMI#.

GPE0_STS — RO. This bit is a logical OR of the bits in the ALT_GP_SMI_STS register

that are also set up to cause an SMI# (as indicated by the GPI_ROUT registers) and

have th e correspondin g bit set in the ALT_GP_SMI_EN register. Bits that are not route d

to cause an SMI# will have no effect on this bit.

0 = SMI# was not generated by a GPI assertion.

1 = SMI# was generated by a GPI assertion.

GPE0_STS — RO . This bit is a logical OR of the bits 14:10, 8:2, and 0 in the GPE0_STS

0 = SMI# was not generated by a GPE0 event.

1 = SMI# was generated by a GPE0 event.

PM1_STS_REG — RO. This is an ORs of the bits in the ACPI PM1 Status Register

(offset PMBASE+00h) that can cause an SMI#.

0 = SMI# was not generated by a PM1_STS event.

1 = SMI# was generated by a PM1_STS event.

Bit Description

Intel® ICH8 Family Datasheet 411

LPC Interface Bridge Registers (D31:F0)

9.8.3.16 ALT_GP_SMI_EN—Alternate GPI SMI Enable Register

I/O Address: PMBASE +38h Attribute: R/W

Default Value: 0000h Size: 16-bit

Lockable: No Usage: ACPI or Legacy

Power Well: Resume

7 Reserved

6SWSMI_TMR_STS — R/WC. Software clears this bit by writing a 1 to it.

0 = Software SMI# Timer has Not expired.

1 = Set by the hardware when the Software SMI# Timer expires.

APM_STS — R/WC. Software clears this bit by writing a 1 to it.

0 = No SMI# generated by write access to APM Control register with APMCH_EN bit set.

1 = SMI# was generated by a write access to the APM Control register with the

APMC_EN bit set.

SLP_SMI_STS — R/WC. Software clears this bit by writing a 1 to the bit location.

0 = No SMI# caused by write of 1 to SLP_EN bit when SLP_SMI_EN bit is also set.

1 = Indicates an SMI# was caused by a write of 1 to SLP_EN bit when SLP_SMI_EN bit

is also set.

LEGACY_USB_STS — RO. This bit is a logical OR of each of the SMI status bits in the

USB Legacy Keyboard/Mouse Control Registers ANDed with the corresponding enable

bits. This bit will not be active if the enable bits are not set.

0 = SMI# was not generated by USB Legacy event.

1 = SMI# was generated by USB Legacy event.

BIOS_STS — R/WC.

0 = No SMI# generated due to ACPI software requesting attention.

1 = This bit gets set by hardware when a 1 is written by software to the GBL_RLS bit

(D31:F0:PMBase + 04h:bit 2). When both the BIOS_EN bit (D31:F0:P MBase +

30h:bit 2) and the BIOS_STS bit are set, an SMI# will be generated. The

BIOS_STS bit is cleared when software writes a 1 to its bit position.

1:0 Reserved

Bit Description

15:0

Alternate GPI SMI Enable — R/W. These bits are used to enable the corresponding

GPIO to cause an SMI#. For these bits to have any effect, the following must be true.

• The corresponding bit in the ALT_GP_SMI_EN register is set.

• The corresponding GPI must be routed in the GPI_ROUT register to cause an SMI.

• The corresponding GPIO must be implemented.

NOTE: Mapping is as follows: bit 15 corresponds to GPIO15... bit 0 corresponds to

GPIO0.

LPC Interface Bridge Registers (D31:F 0)

412 Intel® ICH8 Family Datasheet

9.8.3.17 ALT_GP_SMI_STS—Alternate GPI SMI Status Register

I/O Address: PMBASE +3Ah Attribute: R/WC

Default Value: 0000h Size: 16-bit

Lockable: No Usage: ACPI or Legacy

Power Well: Resume

9.8.3.18 GPE_CNTL— General Purpose Control Register

I/O Address: PMBASE +42h Attribute: R/W

Default Value: 00h Size: 8-bit

Lockable: No Usage: ACPI or Legacy

Power Well: Resume

Bit Description

15:0

Alternate GPI SMI Status — R/WC. These bits report the status of the corres ponding

GPIOs.

0 = Inactive. Software clears this bit by writing a 1 to it.

1 = Active

These bits are sticky. If the following c onditions are true, then an SMI# will be

generated and the GPE0_STS bit set:

• The corresponding bit in the ALT_GPI_SMI_EN register (PMBASE + 38h) is set

• The corresponding GPIO must be routed in the GPI_ROUT register to cause an SMI.

• The corresponding GPIO must be implemented.

All bits are in the resume well. Default for these bits is dependent on the state of the

GPIO pins.

Bit Description

8:2 Reserved

SWGPE_CTRL— R/W. This bit allows software to control the assertion of SWGPE_STS

bit. This bit is used by hardware as the level input signal for the SWGPE_STS bit in the

GPE0_ST S register. When SWGPE_ CTRL is 1, SWGPE_STS will be set to 1, and writes to

SWGPE_STS with a value of 1 to

clear SWGPE_STS will result in SWGPE_STS being set back to 1 by hardware. When

SWGPE_CTRL is 0 , wr ites to SWGPE_STS with a value of 1 will clear SWGPE_STS to 0.

THRM#_POL — R/W. This bit controls the polarity of the THRM# pin needed to set the

THRM_STS bit.

0 = Low value on the THRM# signal will set the THRM_STS bit.

1 = HIGH value on the THRM# signal will set the THRM_STS bit.

Intel® ICH8 Family Datasheet 413

LPC Interface Bridge Registers (D31:F0)

9.8.3.19 DEVACT_STS — Device Activity Status Register

I/O Address: PMBASE +44h Attribute: R/WC

Default Value: 0000h Size: 16-bit

Lockable: No Usage: Legacy Only

Power Well: Core

Each bit indicates if an access has occurred to the corresponding device’ s trap range, or

for bits 6:9 if the corresponding PCI interrupt is active. This register is used in

conjunction with the P eriodic SMI# timer to detect any system activity for legacy power

management. The periodic SMI# timer indicates if it is the right time to read the

DEVACT_STS register (PMBASE + 44h).

Note: Software clears bits that are set in this register by writing a 1 to the bit position.

Bit Description

15:13 Reserved

KBC_ACT_STS — R/WC. KBC (60/64h).

0 = Indicates that there has been no access to this device’s I/O range.

1 = This device’s I/O r ange has been accessed. Clear this bit by writing a 1 to the bit

location.

11:10 Reserved

PIRQDH_ACT_STS — R/WC. PIRQ[D or H].

0 = The corresponding PCI interrupts have not been active.

1 = At least one of the corresponding PCI interrupts has been active. Clear this bit by

writing a 1 to the bit lo cation.

PIRQCG_ACT_STS — R/WC. PIRQ[C or G].

0 = The corresponding PCI interrupts have not been active.

1 = At least one of the corresponding PCI interrupts has been active. Clear this bit by

writing a 1 to the bit lo cation.

PIRQBF_ACT_STS — R/WC. PIRQ[B or F].

0 = The corresponding PCI interrupts have not been active.

1 = At least one of the corresponding PCI interrupts has been active. Clear this bit by

writing a 1 to the bit lo cation.

PIRQAE_ACT_STS — R/WC. PIRQ[A or E].

0 = The corresponding PCI interrupts have not been active.

1 = At least one of the corresponding PCI interrupts has been active. Clear this bit by

writing a 1 to the bit lo cation.

5:1 Reserved

Desktop

Only) Reserved

(Mobile

Only)

IDE_ACT_STS — R/WC . IDE Primary Drive 0 and Drive 1.

0 = Indicates that there has been no access to this device’s I/O range.

1 = This device’s I/O range has been accessed. The enable bit is in the ATC register

(D31:F1:Offset C0h). Clear this bit by writing a 1 to the bit locatio n.

LPC Interface Bridge Registers (D31:F 0)

414 Intel® ICH8 Family Datasheet

9.8.3.20 SS_CNT— Intel SpeedStep® Technology

Control Register (Mobile Only)

I/O Address: PMBASE +50h Attribute: R/W (special)

Default Value 01h Size: 8-bit

Lockable: No Usage: ACPI/Legacy

Power Well: Core

Note: Writes to this register will initiate an Intel SpeedStep technology transition that

involves a temporary transition to a C3-like state in which the STPCLK# signal will go

active. An Intel SpeedStep technology transition always occur on writes to the

SS_CNT register, even if the value written to SS_STATE is the same as the previous

value (after this “transition” the system would still be in the same Intel SpeedStep

technology state). If the SS_EN bit is 0, then writes to this register will have no effect

and reads will return 0.

9.8.3.21 C3_RES— C3 Residency Register (Mobile Only)

I/O Address: PMBASE +54h Attribute: R/W/RO

Default Value 00000000h Size: 32-bit

Lockable: No Usage: ACPI/Legacy

Power Well: Core

Software may only write this register during system initialization to set the state of the

C3_RESIDENCY_MODE bit. It must not be written while the timer is in use.

Bit Description

7:1 Reserved

SS_STATE (Intel SpeedStep® technology State) — R/W (Special). When this bit is

read, it returns the last value written to this register. By convention, this will be the

current Intel SpeedStep technology state. Writes to this register causes a change to the

Intel SpeedStep technology state indicated by the value written to th is bit. If the new

value for SS_STATE is the same as the previous value, then transition will still occur.

0 = High power state.

1 = Low power state

NOTE: This is only a convention because the transition is the same regardless of the

value written to this bit.

Bit Description

31:24 Reserved

23:0

C3_RESIDENCY — RO. The value in this field increments at the same rate as the Power

Management Timer. If the C3_RESEDENCY_MODE bit is clear, this field automatically

resets to 0 at the point when the L vl3 or Lvl4 read occurs. If the C3_RESIDENCY_MODE

bit is set, th e register does not reset when the L vl 3 or L vl4 read occurs. In either mode,

it increments while STP_CPU# is active (i.e., the processor is in a C3 or C4 state). This

field will roll over in the same way as the PM Timer, however the most significant bit is

NOT sticky.

Software is responsible for reading this field before performing the Lvl3/4 transition.

Software must also check for rollover if the maximum time in C3/C4 could be

exceeded.

NOTE: Hardware reset is the only reset of this counter field.

Intel® ICH8 Family Datasheet 415

LPC Interface Bridge Registers (D31:F0)

9.8.3.22 C5_RES— C5 Residency Register (Mobile Only)

I/O Address: PMBASE +58h Attribute: R/W/RO

Default Value 00000000h Size: 32-bit

Lockable: No Usage: ACPI/Legacy

Power Well: Core

Software may only write this register during system initialization to set the state of the

C5_RESIDENCY_MODE bit. It must not be written while the timer is in use.

Bit Description

31:24 Reserved

23:0

C5_RESIDENCY — RO. The value in this field increments at the same rate as the

Power Management Timer. If the C5_RESEDENCY_MODE bit is clear, this field

automatically resets to 0 at the point when the Lvl5 or Lvl6 read occurs. If the

C5_RESIDENCY_MODE bit is set, the register does not reset when the L vl5 or L vl6 read

occurs. In either mode, it increments while STP_CPU# is active (i.e. , the processor is in

C3/C4/C5/C6 state). This field will roll over in the same way as the PM Timer, however

the most sign ificant bit is NOT sticky.

Software is responsible for reading this field before performing the Lvl5/6 transition.

Software must also check for rollover if the maximum time in C5/C6 could be

exceeded.

NOTE: Hardware reset is the only reset of this counter field.

LPC Interface Bridge Registers (D31:F 0)

416 Intel® ICH8 Family Datasheet

9.9 System Management TCO Registers (D31:F0)

The TCO logic is accessed via registers mapped to the PCI configuration space (Device

31:Function 0) and the system I/O space. F or TCO PCI Configur ation registers, see LPC

Device 31:Function 0 PCI Configuration registers.

TCO Register I/O Map

The TCO I/O registers reside in a 32-byte range pointed to by a TCOBASE v alue, which

is, PMBASE + 60h in the PCI config space. The following table shows the mapping of

the registers within that 32-byte range. Each register is described in the following

sections.

9.9.1 TCO_RLD—TCO Timer Reload and Current Value Register

I/O Address: TCOBASE +00h Attribute: R/W

Default Value: 0000h Size: 16-bit

Lockable: No Power Well: Core

Table 116. TCO I/O Register Address Map

TCOBASE

+ Offset Mnemonic Register Name Default Type

00h–01h TCO_RLD TCO Timer Reload and Current

Value 0000h R/W

02h TCO_DAT_IN TCO Data In 00h R/W

03h TCO_DAT_OUT TCO Data Out 00h R/W

04h–05h TCO1_STS TCO1 Status 0000h R/WC, RO

06h–07h TCO2_STS TCO2 Status 0000h R/W, R/WC

08h–09h TCO1_CNT TCO1 Control 0000h

R/W,

R/W

(special), R/

0Ah–0Bh TCO2_CNT TCO2 Control 0008h R/W

0Ch–0Dh TCO_MESSAGE1,

TCO_MESSAGE2 TCO Message 1 and 2 00h R/W

0Eh TCO_WDCNT Watchdog Control 00h R/W

0Fh — Reserved — —

10h SW_IRQ_GEN Software IRQ Generation 03h R/W

11h — Reserved — —

12h–13h TCO_TMR TCO Timer Initial Value 0004h R/W

14h–1Fh — Reserved — —

Bit Description

15:10 Reserved

9:0 TCO Timer Value — R/W. Reading this register will return the current count of the TCO

timer. Writing any value to this register will reload the timer to preven t the timeout.

Intel® ICH8 Family Datasheet 417

LPC Interface Bridge Registers (D31:F0)

9.9.2 TCO_DAT_IN—TCO Data In Register

I/O Address: TCOBASE +02h Attribute: R/W

Default Value: 00h Size: 8-bit

Lockable: No Power Well: Core

9.9.3 TCO_DAT_OU T—TCO Data Out Register

I/O Address: TCOBASE +03h Attribute: R/W

Default Value: 00h Size: 8-bit

Lockable: No Power Well: Core

9.9.4 TCO1_STS—TCO1 Status Register

I/O Address: TCOBASE +04h Attribute: R/WC, RO

Default Value: 0000h Size: 16-bit

Lockable: No Power Well: Core

(Except bit 7, in RTC)

Bit Description

7:0 TCO Data In Value — R/W. This data register field is used for passing commands from

the OS to the SMI handler. Writes to th is register will cause an SMI and set the

SW_TCO_SMI bit in the TCO1_STS register (D31:F0:04h).

Bit Description

7:0

TCO Data Out Value — R/W. This data register field is used for passing commands

from the SMI handl er to the OS. W rites to this regis ter will set the T C O_INT_STS bit in

the TCO_STS register. It will also cause an interrupt, as selected by the TCO_INT_SEL

bits.

Bit Description

15:13 Reserved

DMISERR_STS — R/WC.

0 = Software clears this bit by writing a 1 to it.

1 = ICH8 received a DMI special cycle message via DMI indicating that it wants to

cause an SERR#. The software must read the (G)MCH to determine the reason for

the SERR#.

11 Reserved

DMISMI_STS — R/WC.

0 = Software clears this bit by writing a 1 to it.

1 = ICH8 received a DMI special cycle message via DMI indicating that it wants to

cause an SMI. The software must read the (G)MCH to determine the reason for the

SMI.

DMISCI_STS — R/WC.

0 = Software clears this bit by writing a 1 to it.

1 = ICH8 received a DMI special cycle message via DMI indicating that it wants to

cause an SCI. The software must read the (G)MCH to determine the reason for the

SCI.

LPC Interface Bridge Registers (D31:F 0)

418 Intel® ICH8 Family Datasheet

BIOSWR_STS — R/WC.

0 = Software clear s this bit by writing a 1 to it.

1 = ICH8 sets this bit and generates and SMI# to indic ate an inva lid attempt to write to

the BIOS. This occurs when either:

a) The BIOSWP bit is changed from 0 to 1 and the BLD bit is also set, or

b) any write is attempted to the BIOS and the BIOSWP bit is also set.

NOTE: On write cycles att empted to the 4 MB lo wer alias to the BIOS space, the

BIOSWR_STS will not be set.

NEWCENTURY_STS — R/WC. This bit is in the RTC well.

0 = Cleared by writing a 1 to the bit position or by RTCRST# going active.

1 = This bit is set whe n the Year byte (RTC I/O space, index offse t 09h) roll s o ve r from

99 to 00. Setting this bit will cause an SMI# (but not a wake event).

NOTE: The NEWCENTURY_STS bit is not valid when the R TC battery is first installed (or

when RTC power has not been maintained). Software can determine if RTC

power has not been maintained by checking the RTC_PWR_STS bit

(D31:F0:A4h, bit 2), or by other means (such as a checksum on RTC RAM). If

RTC power is determined to have not been maintained, BIOS should set the

time to a valid value and then clear the NEWCENTURY_STS bit.

The NEWCENTURY_S TS bit may take up to 3 RTC clocks for the bit to be cleared

after a 1 is written to the bit to clear it. After writing a 1 to this bit, software should

not exit the SMI handler un til verifying that the bit has actually been cleared. This

will ensure that the SMI is not re-entered.

6:4 Reserved

3TIMEOUT — R/WC.

0 = Software clear s this bit by writing a 1 to it.

1 = Set by ICH8 to indicate that the SMI was caused by the TCO timer reaching 0.

TCO_INT_STS — R/WC.

0 = Software clear s this bit by writing a 1 to it.

1 = SMI handler caused the interrupt by writing to the TCO_DAT_OUT register

(TCOBASE + 03h).

SW_TCO_SMI — R/WC.

0 = Software clear s this bit by writing a 1 to it.

1 = Software caused an SMI# by writing to the TCO_DAT_IN register (TCOBASE +

02h).

NMI2SMI_STS — RO.

0 = Cleared by clearing the associated NMI status bit.

1 = Set by the ICH8 when an SMI# occurs because an event occurred that would

otherwise have caused an NMI (because NMI2SMI_EN is set).

Bit Description

Intel® ICH8 Family Datasheet 419

LPC Interface Bridge Registers (D31:F0)

9.9.5 TCO2_STS—TCO2 Status Register

I/O Address: TCOBASE +06h Attribute: R/W, R/WC

Default Value: 0000h Size: 16-bit

Lockable: No Power Well: Resume

(Except Bit 0, in RTC)

Bit Description

15:6 Reserved

ME_WAKE_STS — R/WC. This bit is set when the ME gener ate s a Non-Maskable wak e

event, and is not affected by any other enable bit. When this bit is set, the Host Power

Management logic wakes to S0.

This bit is only set by hardware and can only be reset by writing a one to this bit

position. This bit is not affected by hard resets caused by a CF9 write, but is reset by

RSMRST.

SMLink Slave SMI Status (SMLINK_SLV_SMI_STS) — R/WC. Allow the software to

go directly into pre-determined sleep state. This av oids r ace conditions. Softw are clears

this bit by writing a 1 to it.

0 = The bit is reset by RSMRST#, but not due to the PCI Reset associated with exit

from S3–S5 states.

1 = ICH8 sets this bit to 1 when it receives the SMI message on the SMLink's Slave

Interface.

3 Reserved

BOOT_STS — R/WC.

0 = Cleared by ICH8 based on RSMRST# or by software writing a 1 to this bit. Note

that software should first clear the SECOND_T O_ST S bit before writing a 1 to clear

the BOOT_STS bit.

1 = Set to 1 when the SECOND_TO_STS bit goes from 0 to 1 and the processor has not

fetched the first instruction.

If rebooting due to a second TCO timer timeout, and if the BOOT_STS bit is set, the

ICH8 will reboot using t he ‘safe’ multiplier (1111). This allows the system to recover

from a processor frequency multiplier that is too high, and allows the BIOS to check the

BOOT_STS bit at boot. If the bit is set and the frequency multiplier is 1111, then the

BIOS knows that th e pro cessor has been programmed to an i nvalid multiplie r.

SECOND_TO_STS — R/WC.

0 = Software clears this bit by writing a 1 to it, or by a RSMRST#.

1 = ICH8 sets this bit to 1 to indicate that the TIMEOUT bit had been (or is currently)

set and a second timeout occurred before the TCO_RLD regi ster wa s written. If this

bit is set and the NO_REBOOT config bit is 0, then the ICH8 will reboot the system

after the second timeout. The reboot is done by asserting PLTRST#.

LPC Interface Bridge Registers (D31:F 0)

420 Intel® ICH8 Family Datasheet

9.9.6 TCO1_CNT—TCO1 Control Register

I/O Address: TCOBASE +08h Attribute: R/W, R/W (special), R/

Default Value: 0000h Size: 16-bit

Lockable: No Power Well: Core

Intruder Detect (INTRD_DET) — R/WC.

0 = Software clears this bit by writing a 1 to it, or by RTCRST# assertion.

1 = Set by ICH8 to indicate that an intrusion was detected. This bit is set even if the

system is in G3 state.

NOTE: This bit has a recovery time. After writing a 1 to this bit position (to clear it), the

bit may be read back as a 1 for up 65 microseconds before it is read as a 0.

Software must be aware of this recovery time when reading this bit after

clearing it.

NOTE: If the INTRUDER# signal is active when the software attempts to clear the

INTRD_DET bit, the bit will remain as a 1, and the SMI# will be generated again

immediately. The SMI handler can cle a r the INTRD_SEL bits (TCOBASE + 0Ah,

bits 2:1), to avoid further SMIs. However, if the INTRUDER# signals goes

inactive and then active again, there will not be further SMI’s (because the

INTRD_SEL bits would select that no SM I# be generated).

NOTE: If the INTRUDER# signal goes inactive some point after the INTRD_DET bit is

written as a 1, then the INTRD_DET signal will go to a 0 when INTRUDER# input

signal goes inactive. Note that this is slightly different than a classic sticky bit,

since most sticky bits would remain active indefinitely when the signal goes

active and would immediately go inactive when a 1 is written to the bit

Bit Description

15:13 Reserved

TCO_LOCK — R/W (special). When set to 1, this bit prevents writes from changing the

TCO_EN bit (in offset 30h of Power Management I/O space). Once this bit is set to 1, it

can not be cleared by software writing a 0 to this bit location. A core-well reset is

required to change this bit from 1 to 0. This bit defaults to 0.

TCO Timer Halt (TCO_TMR_HLT) — R/W.

0 = The TCO Timer is enabled to count.

1 = The TCO Timer will halt. It will not count, and thus cannot reach a value that will

cause an SMI# or set the SECOND_TO_STS bit. When set, this bit will prevent

rebooting and prevent Alert On LAN event messages from being tr ansmitted on the

SMLINK (but not Alert On LAN* heartbeat messages).

10 Reserved

NMI2SMI_EN — R/W.

0 = Normal NMI functi onality.

1 = Forces all NMIs to instead cause SMIs. The functionality of this bit is dependent

upon the settings of the NMI_EN bit and the GBL_SMI_EN bit as detailed in the

following table:

NMI_EN GBL_SMI_EN Description

0b 0b No SMI# at all because GBL_SMI_EN = 0

0b 1b SMI# will be caused due to NMI events

1b 0b No SMI# at all because GBL_SMI_EN = 0

1b 1b No SMI# due t o NMI because NM I_EN = 1

Intel® ICH8 Family Datasheet 421

LPC Interface Bridge Registers (D31:F0)

9.9.7 TCO2_CNT — TCO2 Control Regis t er

I/O Address: TCOBASE +0Ah Attribute: R/W

Default Value: 0008h Size: 16-bit

Lockable: No Power Well: Resume

9.9.8 TCO_MESSAGE1 and TCO_MESSAGE2 Registers

I/O Address: TCOBASE +0Ch (Message 1)Attribute: R/W

TCOBASE +0Dh (Message 2)

Default Value: 00h Size: 8-bit

Lockable: No Power Well: Resume

NMI_NOW — R/WC.

0 = Software clears this bit by writing a 1 to it. The NMI handler is expected to clear

this bit. Another NMI will not be generated until the bit is cleared.

1 = Writing a 1 to this bit causes an NMI. This allows t he BIOS or SMI handle r to fo rce

an entry to the NMI handler.

7:0 Reserved

Bit Description

15:6 Reserved

5:4

OS_POLICY — R/W. OS-based software writes to these bits to select the policy that

the BIOS will use afte r the platform resets due the WDT. The foll owing convention is

recommended for the BIOS and OS:

00 = Boot normally

01 = Shut down

10 = Don’t load OS. Hold in pre-boot state and use LAN to determine next step

11 = Reserved

NOTE: These are just scratchpad bits. They sh ould not be reset when the TCO logic

resets the plat form due to Watchdog Timer.

GPIO11_ALERT_DISABLE — R/W. At reset (via RSMRST# asserted) this bit is set

and GPIO[11] alerts are disabled.

0 = Enable.

1 = Disable GPIO11/SMBALERT# as an alert source for the heartbeats and the SMBus

slave.

2:1

INTRD_SEL — R/W. This field selects the action to take if the INTRUDER# signal goes

active.

00 = No interrupt or SMI#

01 = Interrupt (as selected by TCO_INT_SEL).

10 = SMI

11 = Reserved

0 Reserved

Bit Description

7:0 TCO_MESSAGE[n] — R/W. BIOS can write into these registers to indicate its boot

progress. The external microcontroller can read these registers to monitor the boot

progress.

LPC Interface Bridge Registers (D31:F 0)

422 Intel® ICH8 Family Datasheet

9.9.9 TCO_WDCNT—TCO Watchdog Control Register

Offset Address: TCOBASE + 0Eh Attribute: R/W

Default Value: 00h Size: 8 bits

Power Well: Resume

9.9.10 SW_IRQ_GEN—Software IRQ Generation Register

Offset Address: TCOBASE + 10h Attribute: R/W

Default Value: 03h Size: 8 bits

Power Well: Core

9.9.11 TCO_TMR—TCO Timer Initial Value Register

I/O Address: TCOBASE +12h Attribute: R/W

Default Value: 0004h Size: 16-bit

Lockable: No Power Well: Core

Bit Description

7:0

The BIOS or system management software can write into this register to indicate more

details on the boot progress. The register will reset to 00h based on a RSMRST# (but

not PLTRST#). The external microcontroller can read this register to monitor boot

progress.

Bit Description

7:2 Reserved

1IRQ12_CAUSE — R/W. The state of this bit is logically ANDed with the IRQ12 signal as

received by the ICH8’s SERIRQ logic. This bit must be a 1 (default) if the ICH8 is

expected to receive IRQ12 assertions from a SERIRQ device.

0IRQ1_CAUSE — R/W. The state of this bit is logically ANDed with the IRQ1 signal as

received by the ICH8’s SERIRQ logic. This bit must be a 1 (default) if the ICH8 is

expected to receive IRQ1 assertions from a SERIRQ device.

Bit Description

15:10 Reserved

9:0

TCO Timer Initial Value — R/W. Value that is loaded into the timer each time the

TCO_RLD register is written. Values of 0000h or 0001h will be ignored and should not

be attempted. The timer is clocked at approximately 0.6 seconds, and thus allows

timeouts ranging from 1.2 second to 613.8 seconds. Note: The timer has an error of ±

1 tick (0.6s).

The TCO Timer will only count down in the S0 state.

Intel® ICH8 Family Datasheet 423

LPC Interface Bridge Registers (D31:F0)

9.10 General Purpose I/O Registers (D31:F0)

The control for the general purpose I/O signals is handled through a separate 64-byte

I/O space. The base offset for this space is selected by the GPIOBASE register.

Table 117. Registers to Control GPIO Address Map

GPIOBASE

+ Offset Mnemonic Register Name Default Access

00h–03h GPIO_USE_SEL GPIO Use Select

197F75FFh

(Desktop) /

197E55FFh

(Mobile)

R/W

04h–07h GP_IO_SEL GPIO Input/Output Select E0EA7FFFh R/W

08h–0Bh — Reserved — —

0Ch–0Fh GP_LVL GPIO Level for Input or Output 02FE8000h R/W

10h–13h GPIO_USE_SEL

Override (LOW) GPIO Use Select Override Low 00000000h R/W

14h–17h — Reserved — —

18h–1Bh GPO_BLINK GPIO Blink Enable 00040000h R/W

1Ch–1Fh GP_SER_BLINK[31:0] GP Serial Blink [31:0] 00000000h R/W

20–23h GP_SB_CMDSTS[31:0] GP Serial Blink Command Status

[31:0] 00000800h R/W

24–27h GP_SB_DATA[31:0] GP Serial Blink Data [31:0] 00000000h R/W

28–2Bh — Reserved — —

2C–2Fh GPI_INV GPIO Signal Invert 00000000h R/W

30h–33h GPIO_USE_SEL2 GPIO Use Select 2 [63:32]

000100FFh

(Desktop) /

000100FEh

(Mobile)

R/W

34h–37h GP_IO_SEL2 GPIO Input/Output Select 2

[63:32] 00550FF0h R/W

38h–3Bh GP_LVL2 GPIO Level for Input or Output 2

[63:32] 00AA0003h R/W

3Ch–3Fh GPIO_USE_SEL

Override (HIGH) GPIO Use Select Override High 00000000h R/W

LPC Interface Bridge Registers (D31:F 0)

424 Intel® ICH8 Family Datasheet

9.10.1 GPIO_USE_SEL—GPIO Use Select Register

Offset Address: GPIOBASE + 00h Attribute: R/W

Default Value: 197F75FFh (Desktop) Size: 32-bit

197E55FFh (Mobile)

Lockable: No Power Well: Core for 0:7, 16:23,

Resume for 8:15, 24:31

9.10.2 GP_IO_SEL—GPIO Input/Output Select Register

Offset Address: GPIOBASE +04h Attribute: R/W

Default Value: E0EA7FFFh Size: 32-bit

Lockable: No Power Well: Core for 0:7, 16:23,

Resume for 8:15, 24: 3 1

Bit Description

31:0

GPIO_USE_SEL[31:0] — R/W. Each bit in this register enables the corresponding

GPIO (if it exists) to be used as a GPIO, rather than for the native function.

0 = Signal used as native function.

1 = Signal used as a GPIO.

NOTES:

1. The following bits are always 1 because they are unmultiplexed: 8, 18, 20. The

following bit s are also unmultiplexed in desktop co nfiguration: 12, 13, 16

2. If GPIO[n] does not exist, then the bit in this register will always read as 0 and

writes will have no effect.

3. When RSMRST# is asserted, all multiplexed signals in the resume and core

wells are configured as their default function. When just PLTRST# is asserted,

the GPIO in the core well are configured as their default function.

4. When configured to GPIO mode, the multiplexing logic will present the inactive

state to native logic that uses the pin as an input.

5. All GPIOs are reset to the default state by CF9h reset except GPIO24

6. If the GPIO use is configured by a soft strap, the corresponding bit in this

Bit Description

31:0

GP_IO_SEL[31:0] — R/W. When configured in native mode (GPIO_USE_SEL[n] is

0), writes to these bits have no effect. The value reported in this register is undefined

when programmed as native mode.

0 = Output. The corresponding GPIO signal is an output.

1 = Input. The corresponding GPIO signal is an input.

Intel® ICH8 Family Datasheet 425

LPC Interface Bridge Registers (D31:F0)

9.10.3 GP_LVL—GPIO Level for Input or Output Register

Offset Address: GPIOBASE +0Ch Attribute: R/W

Default Value: 02FE8000h Size: 32-bit

Lockable: No Power Well: Core for 0:7, 16:23,

Resume for 8:15, 24:31

9.10.4 GPIO_USE_SEL Override Register (LOW)—GPIO Use Select

Override Register Low

Offset Address: GPIOBASE +10h Attribute: R/W

Default Value: 00000000h Size: 32-bit

Lockable: No Power Well: Core for 0:7, 16:23,

Resume for 8:15, 24:31

Bit Description

31:0

GP_LVL[31:0]— R/W:

If GPIO[n] is programmed to be an output (via the corresponding bit in the

GP_IO_SEL register), then the corresponding GP_LVL[n] bit can be updated by

software to drive a high or low value on the output pin. 1 = high, 0 = low.

If GPIO[n] is programmed as an input, then the corresponding GP_L VL bit reflects the

state of the input signal (1 = high, 0 = low.) and writes will have no effect.

When configured in native mode (GPIO_USE_SEL[n] is 0), writes to these bits have

no effect. The value reported in this register is undefined when programmed as

native mode.

Bit Description

31:0

GPIO_USE_SEL Override [31:0] — R/W. Each bit in this register enables th e

corresponding GPIO (if it exists) to be used as a GPIO, rather than for the native

function.

0 = Signal used as native function.

1 = Signal used as a GPIO.

Once a bit is set to 1b, it can only be cleared a reset. Bits 31:24 and 15:8 are cleared

by RSMRST# and CF9h events. Bits 23:16 and 7:0 are cleared by PLTRST # events.

If the corresponding GPIO is not multiplexed with Native functionality or not

implemented at al l, this bit has no effect.

This register corresponds to GPIO[31:0].

LPC Interface Bridge Registers (D31:F 0)

426 Intel® ICH8 Family Datasheet

9.10.5 GPO_BLINK—GPO Blink Enable Register

Offset Address: GPIOBASE +18h Attribute: R/W

Default Value: 00040000h Size: 32-bit

Lockable: No Power Well: Core for 0:7, 16:23,

Resume for 8:15, 24: 3 1

NOTE: GPIO18 will blink by default immediately after reset. This signal could be connected to an

LED to indicate a failed boot (by programming BIOS to clear GP_BLINK18 after successful

POST).

9.10.6 GP_SER_BLINK[31:0]—GP Serial Blink

Offset Address: GPIOBASE +1Ch Attribute: R/W

Default Value: 00000000h Size: 32-bit

Lockable: No Power Well: Core for 0:7, 16:23,

Resume for 8:15, 24: 3 1

Bit Description

31:0

GP_BLINK[31:0] — R/W. The setting of this bit has no effect if the corresponding

GPIO signal is programmed as an input.

0 = The corresponding GPIO will function normally.

1 = If the corresponding GPIO is programmed as an output, the output signal will

blink at a rate of approximately once per second. The high and low times have

approximately 0.5 seconds each. The GP_LVL bit is not altered when this bit is

set.

The value of the corresponding GP_LVL bit remains unchanged during the blink

process, and does not effect the blink in any way. The GP_LVL bit is not altered

when programmed to blink. It will remain at its previous value.

These bits correspond to GPIO in th e Resume well. These bits revert to the default

value based on RSMRST# or a write to the CF9h register (but not just on

PLTRST#).

Bit Description

31:0

GP_SER_BLINK[31:0]: The setting of this bit has no effect if the corresponding

GPIO is programmed as an input or if the corresponding GPIO has the GPO_BLINK

bit set.

When set to a 0, the corresponding GPIO will function normally.

When using serial blink, this bit should be set to a 1 while the corresponding

GP_IO_SEL bit is set to 1. Setting the GP_IO_SEL bit to 0 after the GP_SER_BLINK

bit ensures ICH8 will no t drive a 1 on the pin as an output. When this

corresponding bit is set to a 1 and the pin is configured to output mode, the serial

blink capability is enabled. The ICH8 will serialize messages through an open-drain

buffer configuration.

The val ue of the corresponding GP_L VL bit remains unchanged and does not impact

the serial blink capability in any way.

Writes to this register have no effect when the corresponding pin is configured in

native mode and the read value returned is undefined.

Intel® ICH8 Family Datasheet 427

LPC Interface Bridge Registers (D31:F0)

9.10.7 GP_SB_CMDSTS[31:0]—GP Serial Blink Command Status

Offset Address: GPIOBASE +20h Attribute: R/W

Default Value: 00080000h Size: 32-bit

Lockable: No Power Well: Core

9.10.8 GP_SB_DATA[31:0]—GP Serial Blink Data

Offset Address: GPIOBASE +24h Attribute: R/W

Default Value: 00000000h Size: 32-bit

Lockable: No Power Well: Core

Bit Description

31:24 Reserved

23:22

Data Length Select (DLS): This read/write field determines th e nu mber of bytes

to serialize on GPIO.

00 = Serialize bits 7:0 of GP_SB_DATA (1 byte)

01 = Serialize bits 15:0 of GP_SB_DATA (2 bytes)

10 = Undefined - Software must not write this value

11 = Serialize bits 31:0 of GP_SB_DATA (4 bytes)

Software should not modify the value in this register unless the Busy bit is clear.

Writes to this register have no effect when the corresponding pin is configured in

native mode and the read value returned is undefined.

21:16

Data Rate Select (DRS): This read/write field selects the number of 128ns time

intervals to count between Manchester data transition s. The default of 8h re sults in

a 1024ns minimum time between transitions. A value of 0h in this register

produces undefined beh avior.

Software should not modify the value in this register unless the Busy bit is clear.

15:9 Reserved

8Busy: This read-only status bit is the hardware indication that a serialization is in

progress. Hardware sets this bit to 1 based on the Go bit being set. Hardware

clears this bit when the Go bit is cleared by the hardware.

7:1 Reserved

0Go: This bit is set to 1 by software to start the serialization process. Hardware

clears the bit after the serialized data is sent. Writes of 0 to this register have no

effect. Software should not write this bit to 1 unless the Busy status bit is cleared.

Bit Description

31:0

GP_SB_DATA[31:0]: This read-write register contains the data serialized out.

The number of bits shifted out are selected through the DLS field in the

GP_SB_CMDSTS register. This register should not be modified by software when

the Busy bit is set.

LPC Interface Bridge Registers (D31:F 0)

428 Intel® ICH8 Family Datasheet

9.10.9 GPI_INV—GPIO Signal Invert Register

Offset Address: GPIOBASE +2Ch Attribute: R/W

Default Value: 00000000h Size: 32-bit

Lockable: No Power Well: CPU I/O for 17, Core for 16, 7:0

9.10.10 GPIO_USE_SEL2—GPIO Use Select 2 Register[63:32]

Offset Address: GPIOBASE +30h Attribute: R/W

Default Value: 000100FFh (Desktop) Size: 32-bit

000100FEh (Mobile)

Lockable: No Power Well: Core for

0:7, 16:23, Resume for 8:15,

24:31

Bit Description

31:0

GP_INV[n] — R/W. Input Invers ion: This bit only has effect if the corresponding

GPIO is used as an input and used by the GPE logic, where the polarity matters. When

set to ‘1’, then the GPI is inverted as it is sent to the GPE logic that is using it. This bit

has no effect on the value that is reported in the GP_LVL register.

These bits are used to allow both active-low and active-high inputs to cause SMI# or

SCI. Note that in the S0 or S1 state, the input signal must be active for at least two PCI

clocks to ensure detection by the ICH8. In the S3, S4 or S5 states the input signal must

be active for at least 2 RTC clocks to ensure detection. The setting of these bits has no

effect if the corresponding GPIO is programmed as an output. These bits correspond to

GPI that are in the re sume well, and will be reset to their default values by RSMRST# or

by a write to the CF9h register.

0 = The corresponding GPI_STS bit is set when the ICH8 detects the state of the input

pin to be high.

1 = The corresponding GPI_STS bit is set when the ICH8 detects the state of the input

pin to be low.

Bit Description

31:0

GPIO_USE_SEL2[31:0]— R/W. Each bit in this register enables the corresponding

GPIO (if it exists) to be used as a GPIO, rather than for the native function.

0 = Signal used as native function.

1 = Signal used as a GPIO.

NOTES:

1. The following bit is always 1 because it is always unmultiplexed: 0.

2. If GPIO[n] does not exist, then the (n-32) bit in this register will always read as

0 and writes will have no effect. The following bits are always 0: [15:12],

[31:24].

3. When RSMR ST# is asserted, all multiplexed signals in the resume and core

wells are configured as their default function. when just PLTRST# is asserted,

the GPIOs in the core well are configured as their default function.

4. When configured to GPIO mode, the multiplexing logic will present the inactive

state to native logic that uses the pin as an input.

5. All GPIOs are reset to the default state by CF9h reset (except GPIO24)

Intel® ICH8 Family Datasheet 429

LPC Interface Bridge Registers (D31:F0)

9.10.11 GP_IO_SEL2—GPIO Input/Output Select 2

Offset Address: GPIOBASE +34h Attribute: R/W

Default Value: 00550FF0h Size: 32-bit

Lockable: No Power Well: CPU I/O for 17, Core for 16, 7:0

9.10.12 GP_LVL2—GPIO Level for Input or Output 2

Offset Address: GPIOBASE +38h Attribute: R/W

Default Value: 00AA0003h Size: 32 -bit

Lockable: No Power Well: CPU I/O for 17, Core for 16, 7:0

Bit Description

31:24,

15:12 Always 0. No corresponding GPIO.

23:16,

11:0

GP_IO_SEL2[49:48, 39:32] — R/W.

0 = GPIO signal is programmed as an output.

1 = Corresponding GPIO signal (if enabled in the GPIO_USE_SEL2 register) is

programmed as an input.

This register corresponds to GPIO[55:48, 43:32]. Bit 0 corresponds to GPIO32.

Bit Description

31:24,

15:12 Reserved. Read-only 0

23:16,

11:0

GP_LVL[49:48, 39:32] — R/W.

If GPIO[n] is progr am med to be an output (via t he correspondin g bit in the GP _IO_SEL

high or low value on the output pin. 1 = high, 0 = low.

If GPIO[n] is programmed as an input, then the corresponding GP_LVL bit reflects the

state of the input signal (1 = high, 0 = low.) and writes will have no effect.

When configured in native mode (GPIO_USE_SEL[n] is 0), writes to these bits have no

effect. The value reported in this register is undefined when programmed as native

mode.

This register corresponds to GPIO[55:48, 43:32]. Bit 0 corresponds to GPIO32.

LPC Interface Bridge Registers (D31:F 0)

430 Intel® ICH8 Family Datasheet

9.10.13 GPIO_USE_SEL Override Register (HIGH)—GPIO Use

Select Override Register High

Offset Address: GPIOBASE +3Ch Attribute: R/W

Default Value: 00000000h Size: 32-bit

Lockable: No Power Well: Core for 0:7, 16:23,

Resume for 8:15, 24: 3 1

§ §

Bit Description

31:0

GPIO_USE_SEL Override [63:32] — R/W. Each bit in this field corresponds to one

of the Host GPIO indexed signals. A 1b in this field forces the corresponding Host

Signal used as native function mode, regardless of the Host GPIO_USE_SEL register

bit. A 0b in this field leaves the determination of the pin usage to the GPIO_USE_SEL

Once a bit is set to 1b, it can only be cleared a reset. Bits 31:24 and 15:8 are cleared

by RSMRST# and CF9h events. Bits 23:16 and 7:0 are cleared by PLTRST# events.

If the corresponding GPIO is not multiplexed with Native fu nctionality or not

implemented at all, this bit has no effect.

This register corresponds to GPIO[55:48, 43:32]. Bit 0 corresponds to GPIO32.

Intel® ICH8 Family Datasheet 431

PCI-to-PCI Bridge Registers (D30:F0)

10 PCI-to-PCI Bridge Registers

(D30:F0)

The ICH8 PCI bridge resides in PCI Device 30, Function 0 on bus #0. This implements

the buffering and control logic between PCI and the backbone. The arbitration for the

PCI bus is handled by this PCI device.

10.1 PCI Configuration Registers (D30:F0)

Note: Address locations that are not shown should be treated as Reserved (see Section 6.2

for details).

Table 118. PCI Bridge Register Address Map (PCI-PCI—D30:F0) (Sheet 1 of 2)

Offset Mnemonic Register Name Default Type

00h–01h VID Vendor Identification 8086h RO

02h–03h DID Device Identification See register

description RO

04h–05h PCICMD PCI Command 0000h R/W, RO

06h–07h PSTS PCI Status 0010h R/WC, RO

08h RID Revision Identification See register

description RO

09h–0Bh CC Class Code 00060401h RO

0Dh PMLT Primary Master Latency Timer 00h RO

0Eh HEADTYP Header Type 81h RO

18h–1Ah BNUM Bus Number 000000h R/W, RO

1Bh SMLT Secondary Master Latency Timer 00h R/W, RO

1Ch–1Dh IOBASE_LIMIT I/O Base and Limit 0000h R/W, RO

1Eh–1Fh SECSTS Secondary Status 0280h R/WC, RO

20h–23h MEMBASE_LIMIT Memory Base and Limit 00000000h R/W, RO

24h–27h PREF_MEM_BASE

_LIMIT Prefetchable Memory Base and

Limit 00010001h R/W, RO

28h–2Bh PMBU32 Prefetchable Memory Upper 32 Bits 00000000h R/W

2Ch–2Fh PMLU32 Prefetchable Memory Limit Upper

32 Bits 00000000h R/W

34h CAPP Capability List Pointer 50h RO

3Ch-3Dh INTR Interrupt Information 0000h R/W, RO

3Eh–3Fh BCTRL Bridge Control 0000h R/WC, RO

40h–41h SPDH Secondary PCI Device Hiding 00h R/W, RO

44h–47h DTC Delayed Transaction Control 00000000h R/W, RO

48h–4Bh BPS Bridge Proprietary Status 00000000h R/WC, RO

PCI-to-PCI Bridge Register s (D30:F0)

432 Intel® ICH8 Family Datasheet

10.1.1 VID— Vendor Identification Register (PCI-PCI—D30:F0)

Offset Address: 00h–01h Attribute: RO

Default Value: 8086h Size: 16 bits

10.1.2 DID— Device Identification Register (PCI-PCI—D30:F0)

Offset Address: 02h–03h Attribute: RO

Default Value: See bit description Size: 16 bits

10.1.3 PCICMD—PCI Command (PCI-PCI—D30:F0)

Offset Address: 04h–05h Attribute: R/W, RO

Default Value: 0000h Size: 16 bits

4Ch–4Fh BPC Bridge Policy Configuration 00001200h R/W RO

50–51h SVCAP Subsystem Vendor Capability

Pointer 000Dh RO

54h–57h SVID Subsystem Vendor IDs 00000000 R/WO

Table 118. PCI Bridge Registe r Addre s s Map (PCI -PCI—D3 0:F 0) (Sheet 2 of 2)

Offset Mnemonic Register Name Default Type

Bit Description

15:0 Vendor ID — RO. This is a 16-bit value assigned to Intel. Intel VID = 8086h.

Bit Description

15:0 Device ID — RO.This is a 16-bit value assigned to the PCI bridge. Refer to the Intel®

ICH8 Family Specification Update for the value of the Device ID Register.

Bit Description

15:11 Reserved

10 Interrupt Disable (ID) — RO. Hardwired to 0. The PCI bridge has no interrupts to

disable.

9Fast Back to Back Enable (FBE) — RO. Hardwired to 0, per the PCI Express* Base

Specification, Revision 1.0a.

SERR# Enable (SERR_EN) — R/W.

0 = Disable.

1 = Enable the ICH8 to generate an NMI (or SMI# if NMI routed to SMI#) when the

D30:F0 SSE bit (offset 06h, bit 14) is set.

7Wait Cycle Control (WCC) — RO. Hardwired to 0, per the PCI Express* Base

Specification, Revision 1.0a.

Parity Error Response (PER) — R/W.

0 = The ICH8 ignores parity errors on the PCI bridge.

1 = The ICH8 will set the SSE bit (D30:F0, offset 06h, bit 14) when parity errors are

detected on the PCI bridge.

5VGA Palette Snoop (VPS) — RO. Hardwired to 0, per the PCI Express* Base

Specification, Revision 1.0a.

Intel® ICH8 Family Datasheet 433

PCI-to-PCI Bridge Registers (D30:F0)

10.1.4 PSTS—PCI Status Register (PCI-PCI—D30:F0)

Offset Address: 06h–07h Attribute: R/WC, RO

Default Value: 0010h Size: 16 bits

Note: For the writable bits, software must write a 1 to clear bits that are set. Writing a 0 to

the bit has no effect.

4Memory Write and Invalidate Enable (MWE) — RO. Hardwired to 0, per the PCI

Express* Base Specification, Revision 1.0a

3Special Cycle Enable (SCE) — RO. Hardwired to 0, per the PCI Express* Base

Specification, Revision 1.0a an d the PCI- to-PCI Bridge Specification.

2Bus Master Enable (BME) — R/W.

0 = Disable

1 = Enable. Allows the PCI-to-PCI bridge to accept cycles from PCI.

Memory Space Enable (MSE) — R/W. Controls the response as a target for memory

cycles targeting PCI.

0 = Disable

1 = Enable

I/O Space Enable (IOSE) — R/W. Controls the response as a target for I/O cycles

targeting PCI.

0 = Disable

1 = Enable

Bit Description

Detected Parity Error (DPE) — R/WC.

0 = Parity error Not detected.

1 = Indicates that the ICH8 detected a parity error on the internal backbone. This bit

gets set even if the Parity Error Response bit (D30:F0:04 bit 6) is not set.

PCI-to-PCI Bridge Register s (D30:F0)

434 Intel® ICH8 Family Datasheet

Signaled System Error (SSE) — R/WC. Several internal and external sources of the

bridge can cause SERR#. The first class of errors is parity errors related to the

backbone. The PCI bridge captures generic data parity errors (errors it finds on the

backbone) as well as errors returned on backbone cycles where the bridge was the

master. If either of these two conditions is met, and the primary side of the bridge is

enabled for parity error response, SERR# will be captured as shown below.

As with the backbone, the PCI bus captures the same sets of errors. The PCI bridge

captures generic data parity errors (errors it finds on PCI) as well as errors returned on

PCI cycles where the bridge was the master. If either of these tw o conditions is met,

and the secondary side of the bridge is enabled for parity error response, SERR# will be

captured as shown below.

The final class of errors is system bus errors. There are three status bits associated with

system bus er rors, each with a corresponding enable. The diagram capturing this is

shown below.

After checking for the three above classes of errors, an SERR# is generated, and

PSTS.SSE logs the generation of SERR#, if CMD.SEE (D30:F0:04, bit 8) is set, as shown

below.

13 Received Master Abort (RMA) — R/WC.

0 = No master abort received.

1 = Set when the bridge receives a master abort status from the backbone.

12 Received Target Abort (RTA) — R/WC.

0 = No target abort received.

1 = Set when the bridge receives a target abort status from the backbone.

Bit Description

Intel® ICH8 Family Datasheet 435

PCI-to-PCI Bridge Registers (D30:F0)

10.1.5 RID—Revision Identification Register (PCI-PCI—D30:F0)

Offset Address: 08h Attribute: RO

Default Value: See bit description Size: 8 bits

10.1.6 CC—Class Code Register (PCI-PCI—D30:F0)

Offset Address: 09h-0Bh Attribute: RO

Default Value: 060401h Size: 24 bits

Signaled Target Abort (STA) — R/WC.

0 = No signaled target abort

1 = Set when the bridge generates a c ompleti on pack et with tar get abort statu s on the

backbone.

10:9 Reserved.

Data Parity Error Detected (DPD) — R/WC.

0 = Data parity error Not detected.

1 = Set when the bridge receives a completion packet from the backbone from a

previous request, and detects a parity error, and CMD.PERE is set (D30:F0:04,

bit 6).

7:5 Reserved.

4Capabilities List (CLIST) — RO. Hardwired to 1. Capability list exist on the PCI

bridge.

3Interrupt Status (IS) — RO. Hardwired to 0. The PCI bridge does not generate

interrupts.

2:0 Reserved

Bit Description

7:0 Revision ID — RO. Refer to the Intel® I/O Controller Hub 8 (ICH8) Family

Specification Update for the value of the Revision ID Register

Bit Description

23:16 Base Class Code (BCC) — RO. Hardwired to 06h. Indicates this is a bridge device.

15:8 Sub Class Code (SCC) — RO. Hardwired to 04h. Indicates this device is a PCI-to-PCI

bridge.

7:0 Programming Interface (PI) — RO. Hardwired to 01h. Indicates the bridge is

subtractive decode

PCI-to-PCI Bridge Register s (D30:F0)

436 Intel® ICH8 Family Datasheet

10.1.7 PMLT—Primary Master Latency Timer Register

(PCI-PCI—D30:F0)

Offset Address: 0Dh Attribute: RO

Default Value: 00h Size: 8 bits

10.1.8 HEADTYP—Header Type Register (PCI-PCI—D30:F0)

Offset Address: 0Eh Attribute: RO

Default Value: 01h Size: 8 bits

10.1.9 BNUM—Bus Number Register (PCI-PCI—D30:F0)

Offset Address: 18h–1Ah Attribute: R/W, RO

Default Value: 000000h Size: 24 bits

Bit Description

7:3 Master Latency Timer Count (MLTC) — RO. Reserved per the PCI Express* Base

Specification, Revision 1.0a.

2:0 Reserved

Bit Description

7Multi-Function Device (MFD) — RO. A 0 indicates a single function device

6:0 Header Type (HTYPE) — RO. This 7-bit field identifies the header layout of the

configuration space, which is a PCI-to-PCI bridge in this case.

Bit Description

23:16 Subordinate Bus Numb er (SBBN) — R/W. This field indicates the highest PCI bus

number below the bridge.

15:8 Secondary Bus Number (SCBN) — R/W. This field indicates the bus number of PCI.

7:0

Primary Bus Number (PBN) — R/W. This field is default to 00h. In a multiple-ICH8

system, programmable PBN allows an ICH8 to be located on any bus. System

configuration software is responsible for initializing these registers to appropriate

values. PBN is not used by hardware in determining its bus number.

Intel® ICH8 Family Datasheet 437

PCI-to-PCI Bridge Registers (D30:F0)

10.1.10 SMLT—Secondary Master Latency Timer Register

(PCI-PCI—D30:F0)

Offset Address: 1Bh Attribute: R/W, RO

Default Value: 00h Size: 8 bits

This timer controls the amount of time the ICH8 PCI-to-PCI bridge will burst data on its

secondary interface. The counter starts counting down from the assertion of FRAME#.

If the grant is removed, then the expiration of this counter will result in the de-

assertion of FRAME#. If the grant has not been removed, then the ICH8 PCI-to-PCI

bridge may continue ownership of the bus.

10.1.11 IOBASE_LIMIT—I/O Base and Limit Register

(PCI-PCI—D30:F0)

Offset Address: 1Ch-1Dh Attribute: R/W, RO

Default Value: 0000h Size: 16 bits

Bit Description

7:3 Master Latency Timer Count (MLTC) — R/W. This 5-bit field indicates the number of

PCI clocks, in 8-clock increments, that the ICH8 rem a ins as master of the bus.

2:0 Reserved

Bit Description

15:12 I/O Limit Address Limit bits[15 :12 ] — R/W. I/O Base bits corresponding to address

lines 15:12 for 4-KB alignment. Bits 11:0 are assumed to be padded to FFFh.

11:8 II/O Limit Address Capability (IOLC) — RO. Indicates that the bridge does not support

32-bit I/O addressing.

7:4 I/O Base Address (IOBA) — R/W. I/O Base bits corresponding to address lines 15:12

for 4-KB alignment. Bits 11:0 are assumed to be padded to 000h.

3:0 I/O Base Address Capability (IOBC) — RO. Indicates that the bridge does not

support 32-bit I/O addressing.

PCI-to-PCI Bridge Register s (D30:F0)

438 Intel® ICH8 Family Datasheet

10.1.12 SECSTS—Secondary Status Register (PCI-PCI—D30:F0)

Offset Address: 1Eh–1Fh Attribute: R/WC, RO

Default Value: 0280h Size: 16 bits

Note: For the writable bits, software must write a 1 to clear bits that are set. Writing a 0 to

the bit has no effect.

Bit Description

15 Detected Parity Error (DPE) — R/WC.

0 = Parity error not detected.

1 = Intel® ICH8 PCI bridge detected an address or data parity error on the PCI bus

14 Received System Error (RSE) — R/WC.

0 = SERR# assertion not received

1 = SERR# assertion is received on PCI.

Received Master Abort (RMA) — R/WC.

0 = No master abort.

1 = This bit is set whenever the bridge is acting as an initiator on the PCI bus and the

cycle is master-aborted. For (G)MCH/ICH8 interface packets that have completion

required, th is must also c ause a target abort to be returned and sets PSTS.STA.

(D30:F0:06 bit 11)

Received Target Abort (RTA) — R/WC.

0 = No target abort.

1 = This bit is set whenever the bridge is acting as an initiator on PCI and a cycle is

target-aborted on PCI. For (G)MCH/ICH8 interface packets that have completion

required, this event must also cause a target abort to be returned, and sets

PSTS.STA. (D30:F0:06 bit 11).

Signaled Target Abort (STA) — R/WC.

0 = No target abort.

1 = This bit is set wh en the bridge is acting as a target on the PCI Bus and signals a

target abort.

10:9 DEVSEL# Timing (DEVT) — RO.

01h = Medium decode timing.

Data Parity Error Detected (DPD) — R/WC.

0 = Conditions described below not met.

1 = The ICH8 sets this bit when all of the following three conditions are met:

• The bridge is the initiator on PCI.

• PERR# is detected asserted or a parity error is detected internally

• BCTRL.PERE (D30:F0:3E bit 0) is set.

7Fast Back to Back Capable (FBC) — RO. Hardwired to 1 to indicate that the PCI to PCI

target logic is capable of receiving fast back-to-back cycles.

6 Reserved

566 MHz Capable (66MHZ_CAP) — RO. Hardwired to 0. This bridge is 33 MHz capable

only.

4:0 Reserved

Intel® ICH8 Family Datasheet 439

PCI-to-PCI Bridge Registers (D30:F0)

10.1.13 MEMBASE_LIMIT—Memory Base and Limit Register

(PCI-PCI—D30:F0)

Offset Address: 20h–23h Attribute: R/W, RO

Default Value: 00000000h Size: 32 bits

This register defines the base and limit, aligned to a 1-MB boundary, of the non-

prefetchable memory area of the bridge. Accesses that are within the ranges specified

in this register will be sent to PCI if CMD.MSE is set. Accesses from PCI that are outside

the ranges specified will be accepted by the bridge if CMD.BME is set.

10.1.14 PREF_MEM_BASE_LIMIT—Prefetchable Memory Base

and Limit Register (PCI-PCI—D30:F0)

Offset Address: 24h–27h Attribute: R/W, RO

Default Value: 00010001h Size: 32-bit

Defines the base and limit, aligned to a 1-MB boundary, of the prefetchable memory

area of the bridge. Accesses that are within the ranges specified in this register will be

sent to PCI if CMD.MSE is set. Accesses from PCI that are outside the ranges specified

will be accepted by the bridge if CMD.BME is set.

Bit Description

31-20 Memory Limit (ML) — R/W. These bits are compared with bits 31:20 of the incoming

address to determine the upper 1-MB aligned value (exclusive) of the range. The

incoming address must be less than this value.

19-16 Reserved

15:4 Memory Base (MB) — R/W. These bits are compared with bits 31:20 of the incoming

address to determine the lower 1-MB aligned value (inclusive) of the range. The

incoming address must be greater than or equal to this value.

3:0 Reserved

Bit Description

31-20 Prefetchabl e Memory Limi t (PML) — R/W. Thes e bits are co mpared with bits 31:20

of the incoming address to determine the upper 1-MB aligned value (exclusive) of the

range. The incoming address must be less than this value.

19-16 64-bit Indicator (I64L) — RO. Indicates support for 64-bit addressing.

15:4 Prefetchabl e Me mory B ase ( PMB) — R/W. These bits are compared with bits 31:20

of the incoming address to determine the lower 1-MB aligned value (inclusive) of the

range. The incoming address must be greate r than or equal to this value.

3:0 64-bit Indicator (I64B) — RO. Indicates support for 64-bit addressing.

PCI-to-PCI Bridge Register s (D30:F0)

440 Intel® ICH8 Family Datasheet

10.1.15 PMBU32—Prefetchable Memory Base Upper 32 Bits

Offset Address: 28h–2Bh Attribute: R/W

Default Value: 00000000h Size: 32 bits

10.1.16 PMLU32—Prefetchable Memory Limit Upper 32 Bits

Offset Address: 2C–2Fh Attribute: R/W

Default Value: 00000000h Size: 32 bits

10.1.17 CAPP—Capability List Pointer Register (PCI-PCI—D30:F0)

Offset Address: 34h Attribute: RO

Default Value: 50h Size: 8 bits

10.1.18 INTR—Interrupt Informat ion Register (PCI-PCI—D30:F0)

Offset Address: 3Ch–3Dh Attribute: R/W, RO

Default Value: 0000h Size: 16 bits

Bit Description

31:0 Prefetchable Memory Base Upper Portion (PMBU) — R/W. Upper 32-bits of the

prefetchable address base.

Bit Description

31:0 Prefetchable Memory Limit Upper Portion (PMLU) — R/W. Upper 32-bits of the

prefetchable address limit.

Bit Description

7:0 Capabilities Pointer (PTR) — RO. Indicates that the pointer for the first entry in the

capabilities list is at 50h in configuration space.

Bit Description

15:8 Interrupt Pin (IPIN) — RO. The PCI bridge does not assert an interrupt.

7:0

Interrupt Line (ILINE) — R /W. Software writte n val ue to indicate which int errupt line

(vector) the interrupt is connected to. No hardware action is taken on this registe r.

Since the bridge does not gener ate an interrupt , BIOS should progr am this valu e to FFh

as per the PCI bridge specification.

Intel® ICH8 Family Datasheet 441

PCI-to-PCI Bridge Registers (D30:F0)

10.1.19 BCTRL—Bridge Control Register (PCI-PCI—D30:F0)

Offset Address: 3Eh–3Fh Attribute: R/WC, RO

Default Value: 0000h Size: 16 bits

Bit Description

15:12 Reserved

Discard Timer SERR# Enable (DTE) — R/W. Controls the generation of SERR# on

the primary interface in response to the DTS bit being set:

0 = Do not generate SERR# on a sec ondary timer discard

1 = Generate SERR# in response to a secondary timer discard

10 Discard Timer Status (DTS) — R/WC. This bit is set to 1 when the secondary discard

timer (see the SDT bit below) expires for a delayed transaction in the hard state.

Secondary Discard Timer (SDT) — R/W. This bit sets the maximum number of PCI

clock cycles that the Int el® ICH8 waits for an initiator on PCI to repeat a delayed

transaction request. The counter starts once the delayed transaction data is has been

returned by the system and is in a buffer in the ICH8 PCI bridge. If the master has not

repeated the transaction at least once before the counter expires, the ICH8 PCI bridge

discards the transaction from its queue.

0 = The PCI master timeout value is between 215 and 216 PCI clocks

1 = The PCI master timeout value is between 210 and 211 PCI clocks

8Primary Discard Timer (PDT) — R/W. This bit is R/W for software compatibility only.

7Fast Back to Back Enable (FBE) — RO. Hardwired to 0. The PCI logic will not generate

fast back-to-back cycles on the PC I bus.

Secondary Bus Reset (SBR) — R/W. Controls PCIRST# assertion on PCI.

0 = Bridge de-asserts PCIRST#

1 = Bridge asserts PCIRST#. When PCIRST# is asserted, the delayed transaction

buffers, posting buffers, and the PCI bus are initialized back to reset conditions.

The rest of the part and the configuration registers are not affected.

Master Abort Mode (MAM) — R/W. Controls the ICH8 PCI bridge’s behavior when a

master abort occu rs :

Master Abort on (G)MCH/ICH8 Interconnect (DMI):

0 = Bridge asserts TRDY# on PCI. It drives all 1’s for reads, and discards data on

writes.

1 = Bridge returns a target abort on PCI.

Master Abort PCI (non-locked cycles):

0 = Normal completion status will be returned on th e (G)MCH/ICH8 interco nnect.

1 = Target abort completion status will be returned on the (G)MCH/ICH8 interconnect.

NOTE: All locked reads will return a completer abort completion status on the (G)MCH/

ICH8 interconnect.

4VGA 16-Bit Deco de (V16D) — R/W. Enables the ICH8 PCI bridge to provide 16-bits

decoding of VGA I/O address precluding the decode of VGA alias addresses every 1 KB.

This bit requires the VGAE bit in this register be set.

PCI-to-PCI Bridge Register s (D30:F0)

442 Intel® ICH8 Family Datasheet

10.1.20 SPDH—Secondary PCI Device Hiding Register

(PCI-PCI—D30:F0)

Offset Address: 40h–41h Attribute: R/W, RO

Default Value: 00h Size: 16 bits

This register allows software to hide the PCI devices, either plugged into slots or on the

motherboard.

VGA Enable (VGAE) — R/W. When set to a 1, the ICH8 PCI bridge forwards the

following tr ansactions to PCI r egardless of th e v alue of the I/O base and li mit registers .

The transactions are qualified by CMD.MSE (D30:F0:04 bit 1) and CMD.IOSE

(D30:F0:04 bit 0) being set.

• Memory addresses: 000A0000h-000BFFFFh

• I/O addresses: 3B0h-3BBh and 3C0h-3DFh. For the I/O addresses, bits [63:16] of the address

must be 0, and bits [15:10] of the address are ignored (i.e., aliased).

The same holds true from secon dary acce sses t o the pri mary inter face in rev erse. That

is, when the bit is 0, memory and I/O addresses on the secondary interface between

the above ranges will be claimed.

ISA Enable (IE) — R/W. This bit only applies to I/O addresses that are enabled by the

I/O Base and I/O Limit registers and are in the first 64 KB of PCI I/O space. If this bit is

set, the ICH8 PCI bridge will block any forwarding from primary to secondary of I/O

transactions addressing the last 768 bytes in each 1-KB block (offsets 100h to 3FFh).

SERR# Enable (SEE) — R/W. Controls the forwarding of secondary interface SERR#

assertions on the primary interface. When set, the PCI bridge will forward SERR# pin.

• SERR# is asserted on the secondary interface.

• This bit is set.

• CMD.SEE (D30:F0:04 bit 8) is set.

Parity Error Response Enable (PERE) — R/W.

0 = Disable

1 = The ICH8 PCI bridge is enabled for parity error reporting based on parity errors on

the PCI bus.

Bit Description

15:4 Reserved

3Hide Device 3 (HD3) — R/W, RO. Same as bit 0 of this register, except for device 3

(AD[19])

2Hide Device 2 (HD 2) — R/W, RO. Same as bit 0 of this register, except for device 2

(AD[18])

1Hide Device 1 (HD1) — R/W, RO. Same as bit 0 of this register, except for device 1

(AD[17])

Hide Device 0 (HD 0) — R/W, RO.

0 = The PCI configuration cycles for this slot are not affected.

1 = Intel® ICH8 hides device 0 on the PCI bus. This is done by masking the IDSEL

(keeping it low) for configuration c ycles to that device. Sinc e the device will not see

its IDSEL go active, it will not respond to PCI conf iguration c ycles and the

processor will thin k the device is not present. AD[16] is used as IDSEL for device 0.

Intel® ICH8 Family Datasheet 443

PCI-to-PCI Bridge Registers (D30:F0)

10.1.21 DTC—Delayed Transaction Control Register

(PCI-PCI—D30:F0)

Offset Address: 44h–47h Attribute: R/W, RO

Default Value: 00000000h Size: 32 bits

Bit Description

Discard Delayed Transactions (DDT) — R/W.

0 = Logged delayed transactions are kept.

1 = The ICH8 PCI bridge will discard any delayed transactions it has logged. This

includes transactions in the pending queue, and any transactions in the active

queue, whether in the hard or soft DT state. The prefetchers will be disabled and

return to an idle state.

NOTE: If a transaction is runni ng on P CI at the t ime t h is bit i s s et, that transaction will

continue until either the PCI master disconnects (by de-asserting FRAME#) or

the PCI bridge disconne cts (by asserting STOP#). This bit is cleared by the PCI

bridge when the delayed transaction queues are empty and have returned to an

idle state. Software sets this bit and polls for its completion

Block Delayed Transactions (BDT) — R/W.

0 = Delayed transactions accept ed

1 = The ICH8 PCI bridge will not accept incomin g transactions which will result in

delayed transactions. It will blindly retry these cycles by asserting STOP#. All

postable cycles (memory writes) will still be accepted.

29: 8 Reserved

7: 6

Maximum Delayed Transactions (MDT) — R/W. Controls the maximum number of

delayed transactions that the ICH8 PCI bridge will run. Encodings are:

00 =) 2 Active, 5 pending

01 =) 2 active, no pending

10 =) 1 active, no pending

11 =) Reserved

5 Reserved

Auto Flush After Disconnect Enable (AFADE) — R/W.

0 = The PCI bridge will retain any fetched data until required to discard by producer/

consumer rules.

1 = The PCI bridge will flush any prefetched data after either the PCI master (by de-

asserting FRAME#) or the PCI bridge (by asserting STOP#) disconnects the PCI

transfer.

Never Prefetc h (NP) — R/W.

0 = Prefetch enabled

1 = The ICH8 will only fetch a single DW and will not enable prefetching, regardless of

the command being an Memory read (MR), Memory read line (MRL), or Memory

read multiple (MRM).

PCI-to-PCI Bridge Register s (D30:F0)

444 Intel® ICH8 Family Datasheet

10.1.22 BPS—Bridge Proprietary Status Register

(PCI-PCI—D30:F0)

Offset Address: 48h–4Bh Attribute: R/WC, RO

Default Value: 00000000h Size: 32 bits

Memory Read Multiple Prefetch Disable (MRMPD) — R/W.

0 = MRM commands will fetch multiple cache lines as defined by the prefetch

algorithm.

1 = Memory read multiple (MRM) commands will fetch only up to a single, 64-byte

aligned cache line.

Memory Read Line Prefetch Disable (MRLPD) — R/W.

0 = MRL commands will fetch multiple cache lines as defined by the prefetch algorithm.

1 = Memory read line (MRL) commands will fetch only up to a single, 64-byte aligned

cache line.

0Memory Read Prefetch Disabl e (MRPD) — R/W.

0 = MR commands will fetch up to a 64-byte aligned cache line.

1 = Memory read (MR) commands will fetch only a single DW.

Bit Description

31:17 Reserved

PERR# Assertion Dete cted (PAD) — R/WC. Th is bit is set b y hardware whenev er the

PERR# pin is asserted on the rising edge of PCI clock. This includes cases in which the

chipset is the agent driving PERR#. It remains asserted until cleared by software

writing a 1 to this location. Whe n enabled by the PERR#-to-SER R# Enable bit (in the

Bridge Policy Configuration regi ster), a 1 in this bit can generate an internal SERR# and

be a source for the NMI logic.

This bit can be used by software to determine the source of a system problem.

15:7 Reserved

6:4

Number of Pending Transactions (NPT) — RO. This read-only indicator tells debug

software how many transactions are in the pending queue. Possible values are:

000 = No pending transaction

001 = 1 pending transaction

010 = 2 pending transactions

011 = 3 pending transactions

100 = 4 pending transactions

101 = 5 pending transactions

110 - 111 = Reserved

NOTE: This field is not valid if DTC.MDT (offset 44h:bits 7:6) is any value other than

‘00’.

3:2 Reserved

1:0

Number of Active Transactio ns (N AT) — RO. This read-only indicator tells debug

software how many transactions are in the active queue. Possible values are:

00 = No active transactions

01 = 1 active transaction

10 = 2 active transactions

11 = Reserved

Intel® ICH8 Family Datasheet 445

PCI-to-PCI Bridge Registers (D30:F0)

10.1.23 BPC—Bridge Policy Configuration Register

(PCI-PCI—D30:F0)

Offset Address: 4Ch–4Fh Attribute: R/W, RO

Default Value: 00001200h Size: 32 bits

Bit Description

31:14 Reserved

13:8

Upstream Read Latency Threshold (URLT) — R/W: This field specifies the number

of PCI clocks after internally enqueuing an upstream memory read request at which

point the PCI target logic s hould insert w ait state s in order to optimi ze lead-off late ncy.

When the master returns after this threshold has been reached and data has not

arrived in the Delayed Transaction completion queue, then the PCI target logic will

insert wait states instead of immediately retrying the cycle. The PCI target logic will

insert up to 16 clocks of target initial latency (from FRAME# assertion to TRDY# or

STOP# assertion) before retrying the PCI read cycle (if the read data has not arrived

yet).

Note that the starting event for this Read Latency Timer is not explicitly visible

externally.

A value of 0h disables this policy completely such that wait states will never be inserted

on the read lead-off data phase.

The default value (12h) specifies 18 PCI clocks (540 ns) and is approximately 4 clocks

less than the typical idle lead-off latency expected for desktop ICH8 systems. This value

may need to be changed by BIOS, depending on the platform.

Subtractive Decode Policy (SDP) — R/W.

0 = The PCI bridge always forwards memory and I/O cycles that are not claimed by any

other device on the backbone (primary interface) to the PCI bus (secondary

interface).

1 = The PCI bridge will not claim and forward memory or I/O cycles at all unless the

corresponding Space Enable bit is set in the Command register.

NOTE: The Boot BIOS Destination Selection strap can force the BIOS accesses to PCI.

PERR#-to-SERR# Enable (PSE) — R/W. When this bit is set, a 1 in the PERR#

Assertion status bit (in the Bridge Proprietary Status register) will result in an internal

SERR# assertion on the primary side of the bridge (if also enabled by the SERR#

Enable bit in the primary Command register). SERR# is a sou r ce of NMI.

Secondary Discard Timer Testmode (SDTT) — R/W.

0 = The secondary discard timer expiration will be defined in BCTRL.SDT (D30:F0:3E,

bit 9)

1 = The secondary discard t im er will expire after 128 PCI clocks.

4:3 Reserved

CMD.MSE BPC.SDP Range Forwarding Policy

00Don’t Care

Forward unclaimed

cycles

0 1 Don’t Care Forwarding Prohibited

1XWithin range

Positive decode and

forward

1XOutside

Subtractive decode &

forward

PCI-to-PCI Bridge Register s (D30:F0)

446 Intel® ICH8 Family Datasheet

10.1.24 SVCAP—Subsystem Vendor Capability Register

(PCI-PCI—D30:F0)

Offset Address: 50h–51h Attribute: RO

Default Value: 000Dh Size: 16 bits

10.1.25 SVID—Subsystem Vendor IDs Register (PCI-PCI—D30:F0)

Offset Address: 54h–57h Attribute: R/WO

Default Value: 00000000h Size: 32 bits

§ §

Peer Decode Enable (PDE) — R/W.

0 = The PCI bridge assumes that all memory cycles target main memory, and all I/O

cycles are not claimed.

1 = The PCI bridge will perform peer decode on any memory or I/O cycl e from PCI that

falls outside of the memory and I/O window registers

1Reserved

0Received Target Abort SERR# Enable (RTAE) — R/W. When set, the PCI bridge will

report SERR# when PSTS.RTA (D30:F0:06 bit 12) or SSTS.RTA (D30:F0:1E bit 12) are

set, and CMD.SEE (D30:F0:04 bit 8) is set.

Bit Description

15:8 Next Capability (NEXT) — RO. Value of 00h indicates this is the last item in the list.

7:0 Capability Identifier (CID) — RO. Value of 0Dh indicates this is a PCI bridge subsystem

vendor capability.

Bit Description

31:16 Subsystem Identifier (SID) — R/WO. Indicates the subsystem as identified by the

vendor. This field is write once and is locked down until a bridge reset occurs (not the

PCI bus reset).

15:0 Subsystem Vendor Identifier (SVID) — R/WO. Indicates the manufacturer of the

subsystem. This field is write once and is locked down until a bridge reset occurs (not

the PCI bus reset).

Intel® ICH8 Family Datasheet 447

IDE Controller Registers (D31:F1) (Mobile Only)

11 IDE Controller Registers

(D31:F1) (Mobile Only)

11.1 PCI Configuration Registers (IDE—D31:F1)

Note: Address locations that are not shown should be treated as Reserved (See Section 6.2

for details).

All of the IDE registers are in the core well. None of the registers can be locked.

NOTE: The ICH 8M IDE controller is not arbitrated as a PCI device; therefore, it does not need a

master latency timer.

Table 119. IDE Controller PCI Register Address Map (IDE-D31:F1)

Offset Mnemonic Register Name Default Type

00h–01h VID Vendor Identification 8086h RO

02h–03h DID Device Identification See register

description RO

04h–05h PCICMD PCI Command 00h R/W, RO

06h–07h PCISTS PCI Status 0280h R/W, RO

08h RID Revision Identification See register

description RO

09h PI Programming Interface 8Ah R/W, RO

0Ah SCC Sub Class Code 01h RO

0Bh B CC Base Class Code 01h RO

0Ch CLS Cache Line Size 00h RO

0Dh PMLT Primary Master Latency Timer 00h RO

10h–13h PCMD_BAR Primary Command Block Base Address 00000001h R/W, RO

14h–17h PCNL_BAR Primary Control Block Base Address 00000001h R/W, RO

18h–1Bh SCMD_BAR Secondary Command Block Base Address 00000001h R/W, RO

1Ch–1Fh SCNL_BAR Secondary Control Block Base Address 00000001h R/W, RO

20h–23h BM_BASE Bus Master Base Address 00000001h R/W, RO

2Ch–2Dh IDE_SVID Subsystem Vendor ID 00h R/WO

2Eh–2Fh IDE_SID Subsystem ID 0000h R/WO

3C INTR_LN Interrupt Line 00h R/W

3D INTR_PN Interrupt Pin See register

description RO

40h–41h IDE_TIMP Primary IDE Timing 0000h R/W

42h–43h IDE_TIMS Secondary IDE Timing 0000h R/W

44h SLV_IDETIM Slave IDE Timing 00h R/W

48h SDMA_CNT Synchronous DMA Control 00h R/W

4Ah–4Bh SDMA_TIM Synchronous DMA Timing 0000h R/W

54h IDE_CONFIG IDE I/O Configuration 00000000h R/W

C0h ATC APM Trapping Control 00h R/W

C4h ATS APM Trapping Status 00h R/WC

IDE Controller Registers (D31:F1) (Mobile Only)

448 Intel® ICH8 Family Datasheet

11.1.1 VID—Vendor Identification Register (IDE—D31:F1)

Offset Address: 00h–01h Attribute: RO

Default Value: 8086h Size: 16-bit

Lockable: No Power Well: Core

11.1.2 DID—Device Identification Register (IDE—D31:F1)

Offset Address: 02h–03h Attribute: RO

Default Value: See bit description Size: 16 -b it

Lockable: No Power Well: Core

Bit Description

15:0 Vendor ID — RO. This is a 16-bit value assigned to In tel. Intel VID = 8086h

Bit Description

15:0 Device ID — RO. This is a 16 -bit value assigned to the Intel® ICH8M IDE controller.

Refer to the Intel ICH8 ICH8M Family EDS Specification Update for the value of the

Device ID Register.

Intel® ICH8 Family Datasheet 449

IDE Controller Registers (D31:F1) (Mobile Only)

11.1.3 PCICMD—PCI Command Register (IDE—D31:F1)

Address Offset: 04h–05h Attribute: RO, R/W

Default Value: 00h Size: 16 bits

Bit Description

15:11 Reserved

10 Interrupt Disable (ID) — R/W.

0 = Enables the IDE controller to assert INTA# (native mode) or IRQ14/15 (legacy mode).

1 = Disable. The interrupt will be deasserted.

9 Fast Back to Back Enable (FBE) — RO. Reserved as 0.

8 SERR# Enable (SERR_EN) — RO. Reserved as 0.

7 Wait Cycle Control (WCC) — RO. Reserved as 0.

6 Parity Error Response (PER) — RO. Reserved as 0.

5 VGA Palette Snoop (VPS) — RO. Reserved as 0.

4 Postable Memory Write Enable (PMW E) — RO. Reserved as 0.

3 Special Cycle Enable (SCE) — RO. Reserved as 0.

2Bus Master Enable (BME) — R/W. Controls the ICH8M’ s abilit y to act as a PCI master

for IDE Bus Master transfers.

Memory Space Enable (MSE) — R/W.

0 = Disables access.

1 = Enables access to the IDE Expan sion memory range. The EXBAR reg iste r (Offs et 24h) mus t be

programmed before this bit is set.

NOTE: BIOS should set this bit to a 1.

I/O Space Enable (IOSE) — R/W. This bit controls access to the I /O space regist er s.

0 = Disables access to the Legacy or Nativ e IDE port s (both Primary an d Secondary) as well as th e

Bus Master IO registers.

1 = Enable. Note that the Base Address register for the Bus Master registers should be

programmed before this bit is set.

NOTES:

1.Separate bits are provided (IDE Decode Enable, in the IDE Timing register) to

independently disable the Primary or Secondary I/O spaces.

2.When this bit is 0 and the IDE co ntroller is in Native Mode, the Interrupt Pin

Regi ster (see Section 11.1.19) will be masked (the interrupt will not be

asserted).

If an interrupt occurs while the masking is in place and the interrupt is still

active when the masking ends, the interrupt will be allowed to be asserted.

IDE Controller Registers (D31:F1) (Mobile Only)

450 Intel® ICH8 Family Datasheet

11.1.4 PCISTS — PCI Status Register (IDE—D31:F1)

Address Offset: 06h–07h Attribute: R/WC, RO

Default Value: 0280h Size: 16 bits

Note: For the writable bits, software must write a 1 to clear bits that are set. Writing a 0 to

the bit has no effect.

Bit Description

15 Detected Parity Error (DPE) — RO. Reserved as 0.

14 Signaled System Error (SSE) — RO. Reserved as 0.

13 Received Master Abort (RMA) — R/WC.

0 = Master abort Not generated by Bus Master IDE interface function.

1 = Bus Master IDE interface function, as a master, generated a master abort.

12 Reserved as 0 — RO.

11 Reserved as 0 — RO.

10:9 DEVSEL# Timing Status (DEV_STS) — RO.

01 = Hardwired; however, the ICH8M does not have a real DEVSEL# signal associated

with the IDE unit, so these bits have no effect.

8 Data Parity Error Detected (DPED) — RO. Reserved as 0.

7 Fast Back to Back Capable (FB2BC) — RO. Reserved as 1.

6 User Definable Features (UDF) — RO. Reserved as 0.

5 66MHz Capable (66MHZ_CAP) — RO. Reserved as 0.

4 Reserved

Interrupt Status (INTS) — RO. This bit is independent of the state of the Interrupt

Disable bit in the command register.

0 = Interrupt is cleared.

1 = Interrupt/MSI is asserted.

2:0 Reserved

Intel® ICH8 Family Datasheet 451

IDE Controller Registers (D31:F1) (Mobile Only)

11.1.5 RID—Revision Identification Register (IDE—D31:F1)

Offset Address: 08h Attribute: RO

Default Value: See bit description Size: 8 bits

11.1.6 PI—Programming Interface Register (IDE—D31:F1)

Address Offset: 09h Attribute: RO, R/W

Default Value: 8Ah Size: 8 bits

11.1.7 SCC—Sub Class Code Register (IDE—D31:F1)

Address Offset: 0Ah Attribute: RO

Default Value: 01h Size: 8 bits

Bit Description

7:0 R evision ID — RO. Refer to the Intel® I/O Controller Hub 8 (ICH8) Fami ly Specification

Update for the value of the Revision ID Register

Bit Description

7 This read-only bit is a 1 to indicate that the ICH8M supports bus master operation

6:4 Reserved. Hardwired to 000b.

3SOP_MODE_CAP — RO. This read-only bit is a 1 to indicate that the secondary

controller supports both legacy and native modes.

SOP_MODE_SEL — R/W. This read/write bit determines the mode that the secondary

IDE channel is operating in.

0 = Legacy-PCI mode (default)

1 = Native-PCI mode

1POP_MODE_CAP — RO. This read-only bit is a 1 to indicate that the primary controller

supports both legacy and native modes.

POP_MODE_SEL — R/W. This read/write bits determines the mode that the primary

IDE channel is operating in.

0 = Legacy-PCI mode (default)

1 = Native-PCI mode

Bit Description

7:0 Sub Class Code (SCC) — RO.

01h = IDE device, in the context of a mass storage device.

IDE Controller Registers (D31:F1) (Mobile Only)

452 Intel® ICH8 Family Datasheet

11.1.8 BCC—Base Class Code Register (IDE—D31:F1)

Address Offset: 0Bh Attribute: RO

Default Value: 01h Size: 8 bits

11.1.9 CLS—Cache Line Size Register (IDE—D31:F1)

Address Offset: 0Ch Attribute: RO

Default Value: 00h Size: 8 bits

11.1.10 PMLT—Primary Master Latency Timer Register

(IDE—D31:F1)

Address Offset: 0Dh Attribute: RO

Default Value: 00h Size: 8 bits

11.1.11 PCMD_BAR—Primary Command Block Base Address

Address Offset: 10h–13h Attribute: R/W, RO

Default Value: 00000001h Size: 32 bits

NOTE: This 8-byte I/O space is used in native mode for the Primary Controller’s Command Block.

Bit Description

7:0 Base Class Code (BCC) — RO.

01 = Mass storage device

Bit Description

7:0 Cache Line Size (CLS) — RO.

00h = Hardwired. The IDE controller is implemented internally so this register has no

meaning.

Bit Description

7:0 Mast er Latency Timer Count (MLTC) — RO.

00h = Hardwired. The IDE controller is implemented internally, and is not arbitrated as

a PCI device, so it does not need a Master Latency Timer.

Bit Description

31:16 Reserved

15:3 Base Address — R/W. Base address of the I/O space (8 consecu ti ve I/O locations).

2:1 Reserved

0 Resource Type Indicator (RTE) — RO. Hardwired to 1 indicating a request for I/O space.

Intel® ICH8 Family Datasheet 453

IDE Controller Registers (D31:F1) (Mobile Only)

11.1.12 PCNL_BAR—Primary Control Block Base Address

Address Offset: 14h–17h Attri bute: R/W, RO

Default Value: 00000001h Size: 32 bits

NOTE: This 4-byte I/O space is used in native mode for the Primary Controller’s Command Block.

11.1.13 SCMD_BAR—Secondary Command Block Base Address

Address Offset: 18h–1Bh Attribute: R/W, RO

Default Value: 00000001h Size: 32 bits

NOTE: This 4-byte I/O spa ce is used in native mode for the Secondary Controller’s Command

Block.

11.1.14 SCNL_BAR—Secondary Control Block Base Address

Address Offset: 1Ch–1Fh Attribute: R/W, RO

Default Value: 00000001h Size: 32 bits

NOTE: This 4-byte I/O spa ce is used in native mode for the Secondary Controller’s Command

Block.

Bit Description

31:16 Reserved

15:2 Base Address — R/W. Base address of the I/O space (4 consecutive I/O locations).

1 Reserved

0 Resource Type Indicator (R TE) — RO. Hardwired to 1 indicating a request for I/O space.

Bit Description

31:16 Reserved

15:3 Base Address — R/W. Base address of the I/O space (8 consecutive I/O locations).

2:1 Reserved

0 Resource Type Indicator (R TE) — RO. Hardwired to 1 indicating a request for I/O space.

Bit Description

31:16 Reserved

15:2 Base Address — R/W. Base address of the I/O space (4 consecutive I/O locations).

1 Reserved

0 Resource Type Indicator (R TE) — RO. Hardwired to 1 indicating a request for I/O space.

IDE Controller Registers (D31:F1) (Mobile Only)

454 Intel® ICH8 Family Datasheet

11.1.15 BM_BASE — Bus Master Base Address Register

(IDE—D31:F1)

Address Offset: 20h–23h Attribute: R/W, RO

Default Value: 00000001h Size: 32 bits

The Bus Master IDE interface function uses Base Address register 5 to request a 16-

byte I/O space to provide a software interface to the Bus Master functions. Only 12

bytes are actually used

(6 bytes for primary, 6 bytes for secondary). Only bits [15:4] are used to decode the

address.

11.1.16 IDE_SVID — Subsystem Vendor Identification

(IDE—D31:F1)

Address Offset: 2Ch–2Dh Attribute: R/WO

Default Value: 00h Size: 16 bits

Lockable: No Power Well: Core

11.1.17 IDE_SID — Subsystem Identification Register

(IDE—D31:F1)

Address Offset: 2Eh–2Fh Attribute: R/WO

Default Value: 0000h Size: 16 bits

Lockable: No Power Well: Core

Bit Description

31:16 Reserved

15:4 Base Address — R/W. This field provides the base address of the I/O space (16

consecutive I/O locations).

3:1 Reserved

0 Resource Type Indicator (RTE) — RO . Hardwired to 1 indicati ng a request for I/O space.

Bit Description

15:0

Subsystem Vendor ID (SVID) — R/WO. The SVID register, in combination with the

Subsystem ID (SID) register, enables the operating system (OS) to distinguish

subsystems from each other. Software (BIOS) sets the value in this register. After that,

the value can be read, but subsequent writes to this register have no effect. The value

written to this register will also be readable via the corresponding SVID registers for the

USB#1, USB#2, and SMBus functions.

Bit Description

15:0

Subsystem ID (SID) — R/WO. The SID register, in combination with the SVID

Software (BIOS) sets the value in this register. After that, the value can be read, but

subsequent writes to this register have no e ffect. The value written to this register will

also be readable via the corresponding SID registers for the USB#1, USB#2, and

SMBus functions.

Intel® ICH8 Family Datasheet 455

IDE Controller Registers (D31:F1) (Mobile Only)

11.1.18 INTR_LN—Interrupt Line Register (IDE—D31:F1)

Address Offset: 3Ch Attribute: R/W

Default Value: 00h Size: 8 bits

11.1.19 INTR_PN—Interrupt Pin Register (IDE—D31:F1)

Address Offset: 3Dh Attribute: RO

Default Value: See Register Description Size: 8 bits

11.1.20 IDE_TIMP — IDE Primary Timing Register (IDE—D31:F1)

Address Offset: 40–41h Attribute: R/W

Default Value: 0000h Size: 16 bits

This register controls the timings driven on the IDE cable for PIO and 8237 style DMA

transfers. It also controls operation of the buffer for PIO transfers.

Bit Description

7:0 Interrupt Line (INT_LN) — R/W. This field is used to communicate to software the

interrupt line that the interrupt pin is connected to.

Bit Description

7:0 Interrupt Pin — RO. This reflects the value of D31IP.PIP (Chipset Config

Registers:Offset 3100h:bits 7:4).

Bit Description

IDE Decode Enable (IDE) — R/W. The IDE I/O Space Enable bit (D31:F1:04h, bit 0)

in the Command register must be set in order for this bit to have any effect.

0 = Disable.

1 = Enables the ICH8M to decode the Command (1F0–1F7h) and Control (3F6h) Blocks.

This bit also effects the memory decode range for IDE Expansion.

14 Drive 1 Timing Register Enable (SITRE) — R/W.

0 = Use bits 13:12, 9:8 for both drive 0 and drive 1.

1 = Use bits 13:12, 9:8 for drive 0, and use the Slave IDE Timing register for drive 1

13:12

IORDY Sample Po int (I SP) — R/W. The setting of these bits determine the number

of PCI clocks between IDE IOR#/IOW# assertion and the first IORDY sample point.

00 = 5 clocks

01 = 4 clocks

10 = 3 clocks

11 = Reserved

11:10 Reserved

9:8

Recovery Time (RCT) — R/W. The setting of these bits determines the minimum

number of PCI clocks between the last IORD Y sample point and the IOR#/IOW# strobe

of the next cycle.

00 = 4 clocks

01 = 3 clocks

10 = 2 clocks

11 = 1 clock

IDE Controller Registers (D31:F1) (Mobile Only)

456 Intel® ICH8 Family Datasheet

Drive 1 DMA Timing Enable (DTE1) — R/W.

0 = Disable.

1 = Enable the fast timing mode for DMA transfers only for this driv e. PIO transfers to the IDE data

port will run in compatible timing.

6Drive 1 Prefetch/Posting Enable (PPE1) — R/W.

0 = Disable.

1 = Enable Prefetch and posting to the IDE data port for this drive.

5Drive 1 IORDY Sample Poin t En able (IE1) — R/W.

0 = Disable IORDY sampling for this drive.

1 = Enable IORDY sampling for this drive.

Drive 1 Fast Timing Bank (TIME1) — R/W.

0 = Accesses to the data port will use compatible timings for this drive.

1 = When this bit = 1 and bit 14 = 0, accesses to the data port will use bits 13:12 for the IORDY

sample point, and bits 9:8 for the recov ery time. When this bit = 1 and bit 14 = 1, accesses to

the data port will use the IORDY sample point and recover time specified in the slave IDE

timing register.

Drive 0 DMA Timing Enable (DTE0) — R/W.

0 = Disable

1 = Enable fast timing mode for DMA transfers only for this drive. PIO transfers to the IDE data

port will run in compatible timing.

2Drive 0 Prefetch/Posting Enable (PPE0) — R/W.

0 = Disable prefetch and posting to the IDE data port for this drive.

1 = Enable prefetch and posting to the ID E data port for this drive.

1Drive 0 IORDY Sample Poin t En able (IE0) — R/W.

0 = Disable IORDY sampling is disabled for this drive.

1 = Enable IORDY sampling for this drive.

Drive 0 Fast Timing Bank (TIME0) — R/W.

0 = Accesses to the data port will use compatible timings for this drive.

1 = Accesses to the data port will use bits 13:12 for the IORDY sample point, and bits 9:8 for the

recovery time

Bit Description

Intel® ICH8 Family Datasheet 457

IDE Controller Registers (D31:F1) (Mobile Only)

11.1.21 IDE_TIMS — IDE Secondary Timing Register

(IDE—D31:F1)

Address Offset: 42h–43h Attribute: R/W

Default Value: 0000h Size : 16 bits

11.1.22 SLV_IDETIM—Slave (Drive 1) IDE Timing Register

(IDE—D31:F1)

Address Offset: 44h Attri bute: R/W

Default Value: 00h Size: 8 bits

Bit Description

IDE Decode Enable (IDE) — R/W. This bit enables/disables the Secondary decode.

The IDE I/O Space Enable bit (D31:F1:04h, bit 0) in the Command register must be

set in order for this bit to have any effect. Addit ionally, separate configuration bits are

provided (in the IDE I/O Configuration register) to individually disable the secondary

IDE interface signals, even if the IDE Decode Enable bit is set.

0 = Disable.

1 = Enables the ICH8M to decode the associated Command Blocks (170–177h) and Control Block

(376h). Accesses to these ranges return 00h, as the secondary channel is not implemented.

14:12 No Operation (NOP) — R/W. These bits are read/write for legacy software

compatibility, but have no functionality in the ICH8M since a secondary channel does

not exist.

11 Reserved

10:0 No Operation (NOP) — R/W. These bits are read/write for legacy software

compatibility, but have no functionality in the ICH8M since a secondary channel does

not exist.

Bit Description

7:4 No Oper ation (NOP) — R/W. T hese bits are read/write for le gacy software compatibil ity,

but have no functionality in the ICH8M.

3:2

Primary Drive 1 IORDY Sam ple Point (PIS P 1) — R/W. This field determines the

number of PCI clocks between IOR#/IOW# assertion and the first IORDY sample point,

if the access is to drive 1 data port and bit 14 of the IDE timing register for primary is

set.

00 = 5 clocks

01 = 4 clocks

10 = 3 clocks

11 = Reserved

1:0

Primary Driv e 1 R eco very Time (PRCT1) — R/W. This field determines the

minimum number of PCI clocks between the last IORDY sample point and the IOR#/

IOW# strobe of the next cycle, if the access is to drive 1 data port and bit 14 of the IDE

timing register for primary is set.

00 = 4 clocks

01 = 3 clocks

10 = 2 clocks

11 = 1 clocks

IDE Controller Registers (D31:F1) (Mobile Only)

458 Intel® ICH8 Family Datasheet

11.1.23 SDMA_CNT—Synchronous DMA Control Register

(IDE—D31:F1)

Address Offset: 48h Attribute: R/W

Default Value: 00h Size: 8 bits

Bit Description

7:4 Reserved

3:2 No Operation (NOP) — R/W. These bits are read/write for legacy software compatibility,

but have no functionality in the ICH8M.

1Primary Drive 1 Synchronous DMA Mode Enable (PSDE1) — R/W.

0 = Disable (default)

1 = Enable Synchronous DMA mode for primary channel drive 1.

0Primary Drive 0 Synchronous DMA Mode Enable (PSDE0) — R/W.

0 = Disable (default)

1 = Enable Synchronous DMA mode for primary channel drive 0.

Intel® ICH8 Family Datasheet 459

IDE Controller Registers (D31:F1) (Mobile Only)

11.1.24 SDMA_TIM—Synchronous DMA Timing Register

(IDE—D31:F1)

Address Offset: 4Ah–4Bh Attribute: R/W

Default Value: 0000h Size: 16 bits

Note: For F A ST_PCB1 = 1 (133 MHz clk) in bits [13:12, 9:8, 5:4, 1:0], refer to Section 5.15.4

for details.

Bit Description

15:14 Reserved

13:12 No Operation (NOP) — R/W. These bits are read/write for legacy software compatibility,

but have no functionality in the ICH8M.

11:10 Reserved

9:8 No Operation (NOP) — R/W. These bits are read/write for legacy software compatibility,

but have no functionality in the ICH8M.

7:6 Reserved

5:4

Primary Drive 1 Cycle Time (PCT1) — R/W. For Ultr a A T A mode , the setting of these

bits determines the minimum write strobe cycle time (CT). The DMARDY#-to-STOP

(RP) time is also determined by the setting of these bits.

3:2 Reserved

1:0

Primary Drive 0 Cycle Time (PCT0) — R/W. For Ultr a A T A mode , the setting of these

bits determines the minimum write strobe cycle time (CT). The DMARDY#-to-STOP

(RP) time is also determined by the setting of these bits.

PCB1 = 0

(33 MHz clk) PCB1 = 1

(66 MHz clk) FAST_PCB1 = 1

(133 MHz clk)

00 = CT 4 clocks,

RP 6 clocks 00 = Reserved 00 = Reserved

01 = CT 3 clocks,

RP 5 clocks 01 = CT 3 clocks,

RP 8 clocks 01 = CT 3 clocks,

RP 16 clocks

10 = CT 2 clocks,

RP 4 clocks 10 = CT 2 clocks,

RP 8 clocks 10 = Reserved

11 = Reserved 11 = Reserved 11 = Reserved

PCB1 = 0

(33 MHz clk) PCB1 = 1

(66 MHz clk) FAST_PCB1 = 1

(133 MHz clk)

00 = CT 4 clocks,

RP 6 clocks 00 = Reserved 00 = Reserved

01 = CT 3 clocks,

RP 5 clocks 01 = CT 3 clocks,

RP 8 clocks 01 = CT 3 clocks,

RP 16 clocks

10 = CT 2 clocks,

RP 4 clocks 10 = CT 2 clocks,

RP 8 clocks 10 = Reserved

11 = Reserved 11 = Reserved 11 = Reserved

IDE Controller Registers (D31:F1) (Mobile Only)

460 Intel® ICH8 Family Datasheet

11.1.25 IDE_CONFIG—IDE I/O Configur ation Register

(IDE—D31:F1)

Address Offset: 54h Attribute: R/W

Default Value: 00000000h Size: 32 bits

Bit Description

31:24 Reserved

23:20 Miscellaneous Scratchpad (MS) — R/W. Previously defined as a scratchpad bit to

indicate to a driver that ATA-100 is supported. This is not used by software as all they

needed to know was located in bits 7:4. See the definition of those bits.

19:18 No Operation (NOP) — R/W. These bits are read/wri te for legacy software compatibility,

but have no functionality in the ICH8M.

17:16

SIG_MODE — R/W . These bits are used to control mode of the IDE signal pins for swap

bay support.

If the PRS bit (Chipset Config Regi sters:Offs et 3414h:b it 1) is 1, t he reset st ates of bits

17:16 will be 01 (tri-state) instead of 00 (normal).

00 = Normal (Enabled)

01 = Tri-state (Disabled)

10 = Drive low (Disabled)

11 = Reserved

15:14 No Operation (NOP) — R/W. These bits are read/wri te for legacy software compatibility,

but have no functionality in the ICH8M.

Fast Primary Drive 1 Base Clock (FAST_PCB1) — R/W. This bit is used in

conjunction with the PCT1 bits to enable/disable Ultra ATA/100 timings for the Primary

Slave drive.

0 = Disable Ultra ATA/100 timing for the Primary Slave drive.

1 = Enable Ultra ATA/100 timing for the Primary Slave drive (overrides bit 1 in this register).

Fast Primary Drive 0 Base Clock (FAST_PCB0) — R/W. This bit is used in

conjunction with the PCT0 bits to enable/disable Ultra ATA/100 timings for the Primary

Master drive.

0 = Disable Ultra ATA/100 timing for the Primary Master drive.

1 = Enable Ultra ATA/100 timing for the Primary Master drive (overrides bit 0 in this register).

11:8 Reserved

7No Operation (NOP) — R/W. These bits are read/write for le gacy software compatibility,

but have no functionality in the ICH8M.

6No Operation (NOP) — R/W. These bits are read/write for le gacy software compatibility,

but have no functionality in the ICH8M.

Primary Slave Channel Cable Reporting — R/W. BIOS should program this bit to tell

the IDE driver which cable is plugged into the channel.

0 = 40 conductor cable is present.

1 = 80 conductor cable is present.

4Primary Master Channel Cable Reporting — R/W. Same description as bit 5

3:2 No Operat ion (NOP) — R/W. These bits are read/write for legacy software compatibility,

but have no functionality in the ICH8M.

1Primary Drive 1 Base Clock (PCB1) — R/W.

0 = 33 MHz base clock for Ultra ATA timings.

1 = 66 MHz base clock for Ultra ATA timings

0Primary Drive 0 Base Clock (PCB0) — R/W.

0 = 33 MHz base clock for Ultra ATA timings.

1 = 66 MHz base clock for Ultra ATA timings

Intel® ICH8 Family Datasheet 461

IDE Controller Registers (D31:F1) (Mobile Only)

11.1.26 ATC—APM Trapping Control Register (IDE—D31:F1)

Address Offset: C0h Attribute: R/W

Default Value: 00h Size: 8 bits

11.1.27 ATS—APM Trapping Status Register (IDE—D31:F1)

Address Offset: C4h Attribute: R/WC

Default Value: 00h Size: 8 bits

Bit Description

7:2 Reserved

1Slave Trap (PST) — R/W. Enables trapping and SMI# assertion on legacy I/O

accesses to 1F0h-1F7h and 3F6h. The active device must be the slave device for the

trap and/or SMI# to occur.

0Master Trap (PMT) — R/W. Enables trapping and SMI# assertion on legacy I/O

accesses to 1F0h- 1F7h and 3F6h. The activ e device must be master devic e for the tr ap

and/or SMI# to occur.

Bit Description

7:2 Reserved

1Slave Trap Status (PSTS) — R/WC. Indicates that a trap occurred to the slave device

0Master Trap Status (PMTS) — R/WC. Indicates that a trap occurred to the master

device

IDE Controller Registers (D31:F1) (Mobile Only)

462 Intel® ICH8 Family Datasheet

11.2 Bus Master IDE I/O Registers (IDE—D31:F1)

The bus master IDE function uses 16 bytes of I/O space, allocated via the BMIBA

master IDE I/O space registers can be accessed as byte, word, or dword quantities.

Reading reserved bits returns an indeterminate, inconsistent value, and writes to

reserved bits have no affect (but should not be attempted). The description of the I/O

registers is shown in Table 120.

11.2.1 BMICP—Bus Master IDE Command Register

(IDE—D31:F1)

Address Offset: BMIBASE + 00h Attribute: R/W

Default Value: 00h Size: 8 bits

Table 120. Bus Master IDE I/O Registers

BMIBASE

+ Offset Mnemonic Register Name Default Type

00 BMICP Bus Master IDE Command Primary 00h R/W

01 — Reserved 00h RO

02 BMISP Bus Master IDE Status Primary 00h R/W,

R/WC

03 — Reserved 00h RO

04–07 BMIDP Bus Master IDE Descriptor Table Pointer

Primary xxxxxxxxh R/W

Bit Description

7:4 Reserved. Returns 0.

Read / Write Control (R/WC) — R/W. This bit sets the direction of the bus master

transfer: This bit must NOT be changed when the bus master funct ion i s ac tive.

0 = Memory reads

1 = Memory writes

2:1 Reserved. Returns 0.

Start/Stop Bus Master (START) — R/W.

0 = All state information is lost when this bit is cleared. Master mode operation cannot be stopped

and then resumed. If this bit is reset while bus master operation is still active (i.e., the Bus

Master IDE Active bit (BMIBASE + 02h, bit 0) of the Bus Master IDE Status register for that IDE

channel is set) and the drive has not yet finished its data transfer (the Interrupt bit (BMIBASE

+ 02h, bit 2) in the Bus Master IDE Status register for that IDE channel is not set), the bus

master command is said to be aborted and data transferred from the drive may be discarded

instead of being written to system memory.

1 = Enables bus master operation of the controller. Bus master operation does not actually start

unless the Bus Master Enable bit (D31:F1:04h, bit 2) in PCI config uration sp ace is also set. Bus

master operation begins when this bit is detected changing from 0 to 1. The controller will

transfer data between the IDE device and memory only when this bit is set. Master operation

can be halted by writing a 0 to this bit.

NOTE: This bit is intended to be cleared by software after the data transfer is

completed, as indicated by either the Bus Master IDE Active bit being cleared or

the Interrupt bit of the Bus Master IDE Status register for that IDE channel

being set, or both. Hardware does not clear this bit automatically.

Intel® ICH8 Family Datasheet 463

IDE Controller Registers (D31:F1) (Mobile Only)

11.2.2 BMISP—Bus Master IDE Status Register (IDE—D31:F1)

Address Offset: BMIBASE + 02h Attribute: R/W, R/WC

Default Value: 00h Size: 8 bits

11.2.3 BMIDP—Bus Master IDE Descriptor Table Pointer Register

(IDE—D31:F1)

Address Offset: BMIBASE + 04h Attribute: R/W

Default Value: All bits undefined Size: 32 bits

§ §

Bit Description

PRD Interrupt Status (PRDIS) — R/WC.

0 = When this bit is cleared by software, the interrupt is cleared.

1 = Set when the host controller completes execution of a PRD that has its Interrupt bit (bit 2 of

this register) set.

Drive 1 DMA Capable — R/W.

0 = Not Capable.

1 = Capable. Set by device depe nde nt co de (BIOS or de vice driv e r) to in dicate that drive 1 for this

channel is capable of DMA transfers, and that the controller has been initialized for optimum

performance. The ICH8M does not use this bit. It is intended for systems that do not attach

BMIDE to the PCI bus.

Drive 0 DMA Capable — R/W.

0 = Not Capable

1 = Capable. Set by device depe nde nt co de (BIOS or de vice driv e r) to in dicate that drive 0 for this

channel is capable of DMA transfers, and that the controller has been initialized for optimum

performance. The ICH8M does not use this bit. It is intended for systems that do not attach

BMIDE to the PCI bus.

4:3 Reserved. Re turn s 0.

Interrupt — R/WC. Software can use this bit to determine if an IDE device has

asserted its interrupt line (IDEIRQ).

0 = Software clears this bit by writing a 1 to it. If thi s bit is cleared while the interrupt is still active,

this bit will remain clear until another assertion edge is detected on the interrupt line.

1 = Set by the rising edge of the IDE interrupt line, regardless of whether or not the interrupt is

masked in the 8259 or the internal I/O APIC. When this bit is read as 1, all data transferred

from the drive is visible in system memory.

Error — R/WC.

0 = Software clears this bit by writing a 1 to it.

1 = This bit is set when the controller encounters a target abort or master abort when transferring

data on PCI.

Bus Master IDE Active (ACT) — RO.

0 = This bit is cleared by the ICH8M when the l ast trans fer for a r egion is pe rformed, where EO T fo r

that region is set in the region descriptor. It is also cleared by the ICH8M when the Start bit is

cleared in the Command register. When this bit is read as 0, all data transferred from the dri v e

during the previous bus master command is visible in system memory, unless the bus master

command was aborted.

1 = Set by the ICH8M when the Start bit is written to the Command register.

Bit Description

31:2 Address of Descriptor Table (ADDR) — R/W. Corresponds to A[31:2]. The

Descriptor Table must be dword-aligned. The Descriptor Table must not cross a 64-K

boundary in memory.

1:0 Reserved

IDE Controller Registers (D31:F1) (Mobile Only)

464 Intel® ICH8 Family Datasheet

Intel® ICH8 Family Datasheet 465

SATA Controller Registers (D31:F2)

12 SATA Controller Registers

(D31:F2)

12.1 PCI Configuration Registers (SATA–D31:F2)

Note: Address locations that are not shown should be treated as Reserved.

All of the SATA registers are in the core well. None of the registers can be locked.

Table 121. SATA Controller PCI Register Address Map (SATA–D31:F2) (Sheet 1 of 2)

Offset Mnemonic Register Name Default Type

00h–01h VID Vendor Identification 8086h RO

02h–03h DID Device Identification See register

description RO

04h–05h PCICMD PCI Command 0000h R/W, RO

06h–07h PCISTS PCI Status 02B0h R/WC, RO

08h RID Revision Ide n tification See register

description RO

09h PI Programming Interface See register

description See register

description

0Ah SCC Sub Class Code See register

description See register

description

0Bh BCC Base Class Code 01h RO

0Dh PMLT Primary Master Latency Timer 00h RO

10h–13h PCMD_BAR Primary Command Block Base Address 00000001h R/W, RO

14h–17h PCNL_BAR Primary Control Block Base Address 00000001h R/W, RO

18h–1Bh SCMD_BAR Secondary Command Block Base

Address 00000001h R/W, RO

1Ch–1Fh SCNL_BAR Secondary Control Block Base Address 00000001h R/W, RO

20h–23h BAR Legacy Bus Master Base Address 00000001h R/W, RO

24h–27h ABAR /

SIDPBA AHCI Base Address / SA TA Index Data

Pair Base Address 00000000h See register

description

2Ch–2Dh SVID Subsystem Vendor Identification 0000h R/WO

2Eh–2Fh SID Subsystem Identification 0000h R/WO

34h CAP Capabilities Pointer 80h RO

3Ch INT_LN Interrupt Line 00h R/W

3Dh INT_PN Interrupt Pin See register

description. RO

40h–41h IDE_TIMP Primary IDE Timing 0000h R/W

42h–43h IDE_TIMS Secondary IDE Timing 0000h R/W

44h SIDETIM Slave IDE Timing 00h R/W

48h SDMA_CNT Synchronous DMA Control 00h R/W

SATA Controller Registers (D31:F2)

466 Intel® ICH8 Family Datasheet

NOTE: The ICH8 SATA controller is not arbitrated as a PCI device, therefore it does not need a

master latency timer.

12.1.1 VID—Vendor Identification Register (SATA—D31:F2)

Offset Address: 00h–01h Attribute: RO

Default Value: 8086h Size: 16 bit

Lockable: No Power Well: Core

4Ah–4Bh SDMA_TIM Synchronous DMA Timing 0000h R/W

54h–57h IDE_CONFIG IDE I/O Configuration 00000000h R/W

70h–71h PID PCI Power Management Capability ID See register

description RO

72h–73h PC PCI Power Management Capabilities 4002h RO

74h–75h PMCS PCI Power Management Control and

Status 0000h R/W, RO,

R/WC

80h–81h MSICI Message Signaled Interrupt Capability

ID 7005h RO

82h–83h MSIMC Message Signaled Interrupt Message

Control 0000h RO, R/W

84h–87h MSIMA Message Signaled Interrupt Message

Address 00000000h RO, R/W

88h–89h MSIMD Message Signaled Interrupt Message

Data 0000h R/W

90h MAP Address Map 00h R/W

92h–93h PCS Port Control and Status 0000h R/W, RO,

R/WC

94h–97h SIR SATA Initialization Register 00000000h R/W

A0h SIRI SATA Indexed Registers Index 00h R/W

A4h STRD SATA Indexed Register Data XXXXXXXXh R/W

A8h–ABh SCAP0 SATA Capability Register 0 00100012h RO

ACh–AFh SCAP1 SATA Capability Register 1 00000048h RO

C0h ATC APM Trapping Control 00h R/W

C4h ATS ATM Trapping Status 00h R/WC

D0h–D3h SP Scratch Pad 00000000h R/W

E0h–E3h BFCS BIST FIS Control/Status 00000000h R/W, R/WC

E4h–E7h BFTD1 BIST FIS Transmit Data, DW1 00000000h R/W

E8h–EBh BFTD2 BIST FIS Transmit Data, DW2 00000000h R/W

Table 121. SATA Controller PCI Register Address Map (SATA–D31:F2) (Sheet 2 of 2)

Offset Mnemonic Register Name Default Type

Bit Description

15:0 Vendor ID — RO. This is a 16-bit value assigned to Intel. Intel VID = 8086h

Intel® ICH8 Family Datasheet 467

SATA Controller Registers (D31:F2)

12.1.2 DID—Device Identification Register (SATA—D31:F2)

Offset Address: 02h–03h Attribute: RO

Default Value: See bit description Size: 16 bit

Lockable: No Power Well: Core

12.1.3 PCICMD—PCI Command Register (SATA–D31:F2)

Address Offset: 04h–05h Attribute: RO, R/W

Default Value: 0000h Size: 16 bits

Bit Description

15:0 Device ID — RO. This is a 16-bit value assigned to the Intel® ICH8 SATA controller.

NOTE: The value of this fiel d will change dependent upon the value of the MAP

Bit Description

15:11 Reserved

Interrupt Disable — R/W. This disables pin-based INTx# interrupts. This bit has no

effect on MSI operation.

0 = Internal INTx# messages are generated if there is an interrupt and MSI is not

enabled.

1 = Internal INTx# messages will not be generated.

9 Fast Back to Back Enable (FBE) — RO. Reserved as 0.

8 SERR# Enable (SERR_EN) — RO. Reserved as 0.

7 Wait Cycle Control (WCC) — RO. Reserved as 0.

Parity Error Response (PER) — R/W.

0 = Disabled. SATA controller will not generate PERR# when a data parity error is

detected.

1 = Enabled. SATA cont roller will generate PERR# when a data parity error is detected.

5 VGA Palette Snoop (VPS) — RO. Reserved as 0.

4 Postable Memory Write Enable (PMWE) — RO. Reserved as 0.

3 Special Cycle Enable (SCE) — RO. Reserved as 0.

2Bus Master Enable (BME) — R/W. This bit controls the ICH8’s ability to act as a PCI

master for IDE Bus Master transfers. This bit does not im pact the generation of

completions for split transaction commands.

Memory Space Enable (MSE) — R/W / RO. Controls access to the SATA controller’s

target memory space (for AHCI).

NOTE: When MAP.MV (offset 90:bits 1:0) is not 00h, this register is Read Only (RO).

Software is responsible for clearing this bit before entering combined mode.

I/O Space Enable (IOSE) — R/W. This bit controls access to the I/O space registers.

0 = Disables access to the Legacy or Native IDE ports (both Primary and Secondary) as

well as the Bus Master I/O registers.

1 = Enable. Note that the Base Address register for the Bus Master registers should be

programmed before this bit is set.

SATA Controller Registers (D31:F2)

468 Intel® ICH8 Family Datasheet

12.1.4 PCISTS — PCI Status Register (SATA–D31:F2)

Address Offset: 06h–07h Attribute: R/WC, RO

Default Value: 02B0h Size: 16 bits

Note: For the writable bits, software must write a 1 to clear bits that are set. Writing a 0 to

the bit has no effect.

12.1.5 RID—Revision Identification Register (SATA—D31:F2)

Offset Address: 08h Attribute: RO

Default Value: See bit description Size: 8 bits

Bit Description

15 Detected Parity Error (DPE) — R/WC.

0 = No parity error detected by SATA controller.

1 = SATA controller detects a parity error on its interface.

14 Signaled System Err or (S SE) — RO. Reserved as 0.

13 Received Master Abort (RMA) — R/WC.

0 = Master abort Not generated.

1 = SATA controller, as a master, generated a master abort.

12 Reserved as 0 — RO.

11 Signaled Target Abort (STA) — RO. Reserved as 0.

10:9 DEVSEL# Timing Status (DEV_STS) — RO.

01 = Hardwired; Controls the device select time for the SATA controller’ s PCI interface.

Data Parity Erro r Detected (DPED) — RO. F or ICH8, this bit can only be set on read

completions received from SiBUS where there is a parity error.

1 = SATA controller, as a master, either detects a parity error or sees the parity error

line asserted, and the parity error response bit (bit 6 of the command register) is

set.

7Fast Back to Back Capable (FB2BC) — RO. Reserved as 1.

6User Definable Features (UDF ) — RO. Reserved as 0.

566MHz Capable (66MHZ_CAP) — RO. Reserved as 1.

4Capabilities List (CAP_LIST) — RO. This bit indicates the presence of a capabilities

list. The m inimum requirement for the capabilit ies list must be PCI power management

for the SATA controller.

Interrupt Status (INTS) — RO. Reflects the state o f INTx# messages.

0 = Interrupt is cleared (independent of the state of Interrupt Disable bit in the

command register [offset 04h]).

1 = Interrupt is to be asserted

2:0 Reserved

Bit Description

7:0 Revision ID — RO . Refer to the Intel® I/O Controller Hub 8 (ICH8) Family Specification

Update for the value of the Revision ID Register

Intel® ICH8 Family Datasheet 469

SATA Controller Registers (D31:F2)

12.1.6 PI—Programming Interface Register (SATA–D31:F2)

12.1.6.1 When Sub Class Code Register (D31:F2:Offset 0Ah) = 01h

Address Offset: 09h Attribute: R/W, RO

Default Value: See bit description Size: 8 bits

12.1.6.2 When Sub Class Code Register (D31:F2:Offset 0Ah) = 04h

Address Offset: 09h Attribute: RO

Default Value: 00h Size: 8 bits

Bit Description

7 This read-only bit is a 1 to indicate that the ICH8 supports bus master operation

6:4 Reserved. Will always return 0.

Secondary Mode Native Capable (SNC) — RO.

0 = Secondary controller only supports legacy mode.

1 = Secondary controller supports both legacy and native modes.

When MAP.MV (D31:F2:Offset 90:bits 1:0) is any v alue other than 00b, thi s bit reports

as a 0. When MAP.MV is 00b, this bit reports as a 1.

Secondary Mode Native Enable (SNE) — R/W / RO.

Determines the mode that the secondary channel is operating in.

0 = Secondary controller operating in legacy (compatibility) mode

1 = Secondary controller operating in native PCI mode.

When MAP.MV (D31:F2:Offset 9 0:bits 1:0) is any value othe r than 00b, this bit is read-

only (RO). Software is responsible for cleari ng this bit before entering combined mode.

When MAP.MV is 00b, this bit is read/write (R/W).

If this bit is set by softw are, then the PN E bit (bit 0 of this regist er) must also be set by

software. While in theory these bits can be programmed separately, such a

configuration is not supported by hardware.

Primary Mode Native Capable (PNC) — RO.

0 = Primary controller only supports legacy mode.

1 = Primary controller supports both legacy and native modes.

When MAP.MV (D31:F2:Offset 90:bits 1:0) is any v alue other than 00b, thi s bit reports

as a 0. When MAP.MV is 00b, this bit reports as a 1

Primary Mode Native Enable (PNE) — R/W / RO.

Determines the mode that the primary channel is operating in.

0 = Primary controller operating in legacy (compatibility) mode.

1 = Primary controller operating in native PCI mode.

When MAP.MV (D31:F2:Offset 9 0:bits 1:0) is any value othe r than 00b, this bit is read-

only (RO). Software is responsible for cleari ng this bit before entering combined mode.

When MAP.MV is 00b, this bit is read/write (R/W).

If this bit is set by software, then the SNE bit (bit 2 of this register) must also be set by

software. While in theory these bits can be programmed separately, such a

configuration is not supported by hardware.

Bit Description

7:0 Interface (IF) — RO.

When configured as RAID, this register becomes read only 0.

SATA Controller Registers (D31:F2)

470 Intel® ICH8 Family Datasheet

12.1.6.3 When Sub Class Code Register (D31:F2:Offset 0Ah) = 06h

Address Offset: 09h Attribute: RO

Default Value: 01h Size: 8 bits

12.1.7 SCC—Sub Class Code Register (SATA–D31:F2)

Address Offset: 0Ah Attribute: RO

Default Value: See bit description Size: 8 bits

12.1.8 BCC—Base Class Code Register

(SATA–D31:F2SATA–D31:F2)

Address Offset: 0Bh Attribute: RO

Default Value: 01h Size: 8 bits

Bit Description

7:0 Interface (IF) — RO.

Indicates the SATA Controller supports AHCI, rev 1.1.

Bit Description

7:0

Sub Class Code (SCC) — RO. This field specifies the sub-class code of the controller,

per the table below:

Intel® ICH8 Only:

ICH8M Only:

(Intel® ICH8R, ICH8DH, ICH8DO, and ICH8M-E Only):

SCC Register Attribute Scc Register Value

RO 01h (IDE Controller)

MAP.SMS (D31:F2:Offs et

90h:bit 7:6) SCC Register Value

00b 01h (IDE Controller)

01b 06h (AHCI Controller)

MAP.SMS (D31:F2:Offs et

90h:bit 7:6) SCC Default Register

Value

00b 01h (IDE Controller)

01b 06h (AHCI Controller)

10b 04h (RAID Controller)

Bit Description

7:0 Base Class Code (BCC) — RO.

01h = Mass storage device

Intel® ICH8 Family Datasheet 471

SATA Controller Registers (D31:F2)

12.1.9 PMLT—Primary Master Latency Timer Register

(SATA–D31:F2)

Address Offset: 0Dh A ttribute: RO

Default Value: 00h Size: 8 bits

12.1.10 PCMD_BAR—Primary Command Block Base Address

Address Offset: 10h–13h Attribute: R/W, RO

Default Value: 00000001h Size: 32 bits

NOTE: This 8-byte I/O space is used in native mode for the Primary Controller’s Command Block.

12.1.11 PCNL_BAR—Primary Control Block Base Address Register

(SATA–D31:F2)

Address Offset: 14h–17h Attribute: R/W, RO

Default Value: 00000001h Size: 32 bits

NOTE: This 4-byte I/O space is used in native mode for the Primary Controller’s Command Block.

Bit Description

7:0 Master La tency Timer Count (MLTC) — RO.

00h = Hardwired. The SATA controller is implemented internally, and is not arbitrated

as a PCI device, so it does not need a Master Latency Timer.

Bit Description

31:16 Reserved

15:3 Base Address — R/W. This field provides the base address of the I/O space

(8 consecutive I/ O lo cat ion s ).

2:1 Reserved

0Resource Type Indicator (RTE) — RO. Hardwired to 1 to indicate a request for I/O

space.

Bit Description

31:16 Reserved

15:2 Base Address — R/W. This field provides the base address of the I/O space

(4 consecutive I/ O lo cat ion s ).

1 Reserved

0 Resource Type Indicator (RTE) — RO. Hardwired to 1 to indicate a request for I/O

space.

SATA Controller Registers (D31:F2)

472 Intel® ICH8 Family Datasheet

12.1.12 SCMD_BAR—Secondary Command Block Base Address

Address Offset: 18h–1Bh Attribute: R/W, RO

Default Value: 00000001h Size: 32 bits

NOTE: This 4-byte I/O space is used in native mode for the Secondary Controller’s Command

Block.

12.1.13 SCNL_BAR—Secondary Control Block Base Address

Address Offset: 1Ch–1Fh Attribute: R/W, RO

Default Value: 00000001h Size: 32 bits

NOTE: This 4-byte I/O space is used in native mode for the Secondary Controller’s Command

Block.

Bit Description

31:16 Reserved

15:3 Base Address — R/W. This field provides the base address of the I/O space

(8 consecutive I/O locations).

2:1 Reserved

0Resource Type Indicator (RTE) — RO. Hardwired to 1 to indicate a request for I/O

space.

Bit Description

31:16 Reserved

15:2 Base Address — R/W. This field provides the base address of the I/O space

(4 consecutive I/O locations).

1Reserved

0Resource Type Indicator (RTE) — RO. Hardwired to 1 to indicate a request for I/O

space.

Intel® ICH8 Family Datasheet 473

SATA Controller Registers (D31:F2)

12.1.14 BAR — Legacy Bus Master Base Address Register

(SATA–D31:F2)

Address Offset: 20h–23h Attribute: R/W, RO

Default Value: 00000001h Size: 32 bits

The Bus Master IDE interface function uses Base Address register 5 to request a 16-

byte IO space to provide a software interface to the Bus Master functions. Only 12

bytes are actually used (6 bytes for primary, 6 bytes for secondary). Only bits [15:4]

are used to decode the address.

12.1.15 ABAR/SIDPBA1 — AHCI Base Address Register/Serial ATA

Index Data Pair Base Address (SATA–D31:F2)

When the programming interface is not IDE (i.e., is not 01h), this register is named

ABAR. When the programming interface is IDE, this register becomes SIDPBA.

Note that hardware does not clear those BA bits when switching from IDE SKU to non-

IDE SKU or vice versa. BIOS is responsible for clearing those bits to 0 since the number

of writable bits changes after SKU switching (as indicated by a change in CC.SCC). In

the case, this register will then have to be re-programmed to a proper value.

12.1.15.1 When CC.SCC is not 01h

Address Offset: 24–27h Attribute: R/WO

Default Value: 00000000h Size: 32 bits

When the programming interface is not IDE, the register represents a memory BAR

allocating space for the AHCI memory registers defined in Section 12.4.

NOTES:

1. When the MAP.MV register is programmed for combined mode (00b), this register is RO.

Software is responsible for clearing this bit before entering combined mode.

2. The ABAR register must be set to a value of 0001_0000h or greater.

Bit Description

31:16 Reserved

15:4 Base Address — R/W. This field provides the base address of the I/O space

(16 consecutive I/O lo cations).

3:1 Reserved

0Resource Type Indicator (RTE) — RO. Hardwired to 1 to indicate a request for I/O

space.

Bit Description

31:11 Base Address (BA) — R/W. Base address of register memory space (aligned to 1 KB)

10:4 Reserved

3 Prefetchable (PF) — RO. Indicates that this range is not pre-fetchable

2:1 Type (TP) — RO. Indicates that this range can be mapped anywhere in 32-bit address

space.

0Resource Type Indicator (RTE) — RO. Hardwired to 0 to indicate a request for register

memory space.

SATA Controller Registers (D31:F2)

474 Intel® ICH8 Family Datasheet

12.1.15.2 When CC.SCC is 01h

Address Offset: 24h–27h Attribute: R/WO

Default Value: 00000001h Size: 32 bits

When the programming interface is IDE, the register becomes an I/O BAR allocating

16 bytes of I/O space for the I/O-mapped registers defined in Section 12.3. Note that

although 16 bytes of locations are allocated, only 8 bytes are used to as SINDX and

SDATA registers; with the remaining 8 bytes preserved for future enhancement.

12.1.16 SVID—Subsystem Vendor Identification Register

(SATA–D31:F2)

Address Offset: 2Ch–2Dh Attribute: R/WO

Default Value: 0000h Size: 16 bits

Lockable: No Power Well: Core

12.1.17 SID—Subsystem Identification Register (SATA–D31:F2)

Address Offset: 2Eh–2Fh Attribute: R/WO

Default Value: 0000h Size: 16 bits

Lockable: No Power Well: Core

12.1.18 CAP—Capabilities Pointer Register (SATA–D31:F2)

Address Offset: 34h Attribute: RO

Default Value: 80h Size: 8 bits

Bit Description

31:16 Reserved

15:4 Base Address (BA) — R/W. Base address of the I/O space.

3:1 Reserved

0 Resource Type Indicator (RTE) — RO. Indicates a request for I/O space.

Bit Description

15:0 Subsystem Vendor ID (SVID) — R/WO. Value is written by BI OS. No hardware

action taken on this value.

Bit Description

15:0 Subsystem ID (SID) — R/WO . V alue is written by BIOS. No hardw are action tak en on

this value.

Bit Description

7:0

Capabilities Pointer (CAP_PTR) — RO. Indicates that the first capability pointer offset is

80h. This value changes to 70h if the MAP.MV register (Dev 31:F2:90h, bits 1:0) in

configuration space indicates that the SATA function and PATA functions are combined

(values of 10b or 10b) or Sub Class Code (CC.SCC) (Dev 31:F2:0Ah) is configure as IDE

mode (value of 01).

Intel® ICH8 Family Datasheet 475

SATA Controller Registers (D31:F2)

12.1.19 INT_LN—Interrupt Line Register (SATA–D31:F2)

Address Offset: 3Ch Attribute: R/W

Default Value: 00h Size: 8 bits

12.1.20 INT_PN—Interrupt Pin Register (SATA–D31:F2)

Address Offset: 3Dh A ttribute: RO

Default Value: See Register Description Size: 8 bits

12.1.21 IDE_TIM — IDE Timing Register (SATA–D31:F2)

Address Offset: Primary: 40h–41h Attribute: R/W

Secondary: 42h–43h

Default Value: 0000h Size: 16 bits

This register controls the timings driven on the IDE cable for PIO and 8237 style DMA

transfers. It also controls operation of the buffer for PIO transfers.

Note: This register is R/W to maintain software compatibility and enable parallel ATA

functionality when the PCI functions are combined. These bits have no effect on SATA

operation unless otherwise noted.

Bit Description

7:0 Interrupt Line — R/W. This field is used to communi cate to software the inte rrupt line

that the interrupt pin is connected to.

Bit Description

7:0 Interrupt Pin — RO. This reflects the value of D31IP.SIP (Chipset Configuration

Registers: Offset 3100h:bits 11:8).

Bit Description

IDE Decode Enable (IDE) — R/W. Individually enable/disable the Primary or

Secondary decode.

0 = Disable.

1 = Enables the Intel® ICH8 to decode the associated Command Blocks (1F0–1F7h for

primary, 170–177h for secondary) and Control Block (3F6h for primary and 376h

for secondary).

This bit effects the IDE decode ranges for both legacy and native-Mode decoding.

NOTE: This bit affects SA T A operation in both combined and non-combined AT A modes.

See Section 5.16 for more on ATA modes of operation.

14 Drive 1 Timing Register Enable (SITRE) — R/W.

0 = Use bits 13:12, 9:8 for both drive 0 and drive 1.

1 = Use bits 13:12, 9:8 for drive 0, and use the Slave IDE Timing register for drive 1

13:12

IORDY Sample Point (ISP) — R/W. The setting of these bits det erm in es th e numbe r

of PCI clocks between IDE IOR#/IOW# assertion and the first IORDY sample point.

00 = 5 clocks

01 = 4 clocks

10 = 3 clocks

11 = Reserved

SATA Controller Registers (D31:F2)

476 Intel® ICH8 Family Datasheet

11:10 Reserved

9:8

Recovery Time (RCT) — R/W. The setting of these bits determines the minimum

number of PCI clocks between the last IORDY sample point and the IOR#/IOW# strobe

of the next cycle.

00 = 4 clocks

01 = 3 clocks

10 = 2 clocks

11 = 1 clock

Drive 1 DMA Timing Enable (DTE1) — R/W.

0 = Disable.

1 = Enable the fast timing mode for DMA transfers only for this drive. PIO transfers to

the IDE data port will run in compatible timing.

6Drive 1 Prefetch/Posting Enable (PPE1) — R/W.

0 = Disable.

1 = Enable Prefetch and posting to the IDE data port for this drive.

5Drive 1 IORDY Sample Point Enable (IE1) — R/W.

0 = Disable IORDY sampling for this drive.

1 = Enable IORDY sampling for this drive.

Drive 1 Fast Timing Bank (TIME1) — R/W.

0 = Accesses to the data port will use compatible timings for this drive.

1 = When this bit =1 and bit 14 = 0, accesses to the data port will use bits 13:12 for

the IORDY sample point, and bits 9:8 for the recov e ry ti me. When thi s bit = 1 and

bit 14 = 1, accesses to the data port will use the IORDY sample point and recover

time specified in the slave IDE timing register.

Drive 0 DMA Timing Enable (DTE0) — R/W.

0 = Disable

1 = Enable fast timing mode for DMA transfers only for this drive. PIO transfers to the

IDE data port will run in compatible timing.

2Drive 0 Prefetch/Posting Enable (PPE0) — R/W.

0 = Disable prefetch and posting to the IDE data port for this drive.

1 = Enable prefetch and posting to the IDE data port for this drive.

1Drive 0 IORDY Sample Point Enable (IE0) — R/W.

0 = Disable IORDY sampling is disabled for this drive.

1 = Enable IORDY sampling for this drive.

Drive 0 Fast Timing Bank (TIME0) — R/W.

0 = Accesses to the data port will use compatible timings for this drive.

1 = Accesses to the data port will use bits 13:12 for the IORDY sample point, and bits

9:8 for the recovery time

Bit Description

Intel® ICH8 Family Datasheet 477

SATA Controller Registers (D31:F2)

12.1.22 SIDETIM—Slave IDE Timing Register (SATA–D31:F2)

Address Offset: 44h Attribute: R/W

Default Value: 00h Size: 8 bits

Note: This register is R/W to maintain software compatibility and enable parallel ATA

functionality when the PCI functions are combined. These bits have no effect on SATA

operation unless otherwise noted.

Bit Description

7:6

Secondary Drive 1 I ORDY Sample Point ( SI SP1) — R/W. This field determines the

number of PCI clocks between IDE IOR#/IOW# assertion and the first IORDY sample

point, if the access is to drive 1 data port and bit 14 of the IDE timing register for

secondary is set.

00 = 5 clocks

01 = 4 clocks

10 = 3 clocks

11 = Reserved

5:4

Secondary Drive 1 Recove ry Time (SRCT1) — R/W. This field determines the

minimum number of PCI cl ocks between the last IORDY sample poi nt and the IOR#/

IOW# strobe o f the next cy cle, if the ac cess is to driv e 1 data port and bit 14 of the IDE

timing register for secondary is set.

00 = 4 clocks

01 = 3 clocks

10 = 2 clocks

11 = 1 clocks

3:2

Primary Drive 1 IORDY Sample Point (PISP1) — R/W. This field determines the

number of PCI clocks between IOR#/IOW# assertion and the first IORDY sample poi nt,

if the access is to drive 1 data port and bit 14 of the IDE timing register for primary is

set.

00 = 5 clocks

01 = 4 clocks

10 = 3 clocks

11 = Reserved

1:0

Primary Drive 1 Recovery Time (PRCT1) — R/W. This field determines the

minimum number of PCI cl ocks between the last IORDY sample poi nt and the IOR#/

IOW# strobe o f the next cy cle, if the ac cess is to driv e 1 data port and bit 14 of the IDE

timing register for primary is set.

00 = 4 clocks

01 = 3 clocks

10 = 2 clocks

11 = 1 clocks

SATA Controller Registers (D31:F2)

478 Intel® ICH8 Family Datasheet

12.1.23 SDMA_CNT—Synchronous DMA Control Register

(SATA–D31:F2)

Address Offset: 48h Attribute: R/W

Default Value: 00h Size: 8 bits

Note: This register is R/W to maintain software compatibility and enable parallel ATA

functionality when the PCI functions are combined. These bits have no effect on SATA

operation unless otherwise noted.

12.1.24 SDMA_TIM—Synchronous DMA Timing Register

(SATA–D31:F2)

Address Offset: 4Ah–4Bh Attribute: R/W

Default Value: 0000h Size: 16 bits

Note: This register is R/W to maintain software compatibility and enable parallel ATA

functionality when the PCI functions are combined. These bits have no effect on SATA

operation, unless otherwise noted.

Bit Description

7:4 Reserved

3Secondary Drive 1 Synchronous DMA Mode Enable (SSDE1) — R/W.

0 = Disable (de fault)

1 = Enable Synchronous DMA mode for secondary channel drive 1

2Secondary Drive 0 Synchronous DMA Mode Enable (SSDE0) — R/W.

0 = Disable (de fault)

1 = Enable Synchronous DMA mode for secondary drive 0.

1Primary Drive 1 Synchronous DMA Mode Enable (PSDE1) — R/W.

0 = Disable (de fault)

1 = Enable Synchronous DMA mode for primary channel drive 1

0Primary Drive 0 Synchronous DMA Mode Enable (PSDE0) — R/W.

0 = Disable (de fault)

1 = Enable Synchronous DMA mode for primary channel drive 0

Bit Description

15:14 Reserved

13:12

Secondary Drive 1 Cycle Time (SCT1) — R/W. For Ultra ATA mode. The setting of

these bits determines the minimum write strobe cycle time (CT). The DMARDY#-to-

STOP (RP) time is also determined by the setting of these bits.

11:10 Reserved

SCB1 = 0

(33 MHz clock) SCB1 = 1

(66 MHz clock) FAST_SCB1 = 1

(133 MHz clock)

00 = CT 4 clocks,

RP 6 clocks 00 = Reserved 00 = Reserved

01 = CT 3 clocks,

RP 5 clocks 01 = CT 3 clocks,

RP 8 clocks 01 = CT 3 clocks,

RP 16 clocks

10 = CT 2 clocks,

RP 4 clocks 10 = CT 2 clocks,

RP 8 clocks 10 = Rese rved

11 = Reserved 11 = Reserved 11 = Reserved

Intel® ICH8 Family Datasheet 479

SATA Controller Registers (D31:F2)

9:8

Secondary Drive 0 Cycle Time (SCT0) — R/W. For Ultra ATA mode. The setting of

these bits determines the m inimum write strobe cycle time (CT). The DM ARDY#-to-

STOP (RP) time is also determined by the setting of these bits.

7:6 Reserved

5:4

Primary Drive 1 Cycle Time (PCT1) — R/W. For Ultr a A T A mode , the setting of these

bits determines the minimum write strobe cycle time (CT). The DMARDY#-to-STOP

(RP) time is also determined by the setting of these bits.

3:2 Reserved

1:0

Primary Drive 0 Cycle Time (PCT0) — R/W. For Ultr a A T A mode , the setting of these

bits determines the minimum write strobe cycle time (CT). The DMARDY#-to-STOP

(RP) time is also determined by the setting of these bits.

Bit Description

SCB1 = 0

(33 MHz clock) SCB1 = 1

(66 MHz clock) FAST_SCB1 = 1

(133 MHz clock)

00 = CT 4 clocks,

RP 6 clocks 00 = Reserved 00 = Reserved

01 = CT 3 clocks,

RP 5 clocks 01 = CT 3 clocks,

RP 8 clocks 01 = CT 3 clocks, RP 16 clocks

10 = CT 2 clocks,

RP 4 clocks 10 = CT 2 clocks,

RP 8 clocks 10 = Reserved

11 = Reserved 11 = Reserved 11 = Reserved

PCB1 = 0

(33 MHz clock) PCB1 = 1

(66 MHz clock) FAST_P CB1 = 1

(133 MHz clock)

00 = CT 4 clocks,

RP 6 clocks 00 = Reserved 00 = Reserved

01 = CT 3 clocks,

RP 5 clocks 01 = CT 3 clocks,

RP 8 clocks 01 = CT 3 clocks, RP 16 clocks

10 = CT 2 clocks,

RP 4 clocks 10 = CT 2 clocks,

RP 8 clocks 10 = Reserved

11 = Reserved 11 = Reserved 11 = Reserved

PCB1 = 0

(33 MHz clock) PCB1 = 1

(66 MHz clock) F AST_PCB1 = 1

(133 MHz clock)

00 = CT 4 clocks,

RP 6 clocks 00 = Reserved 00 = Reserved

01 = CT 3 clocks,

RP 5 clocks 01 = CT 3 clocks,

RP 8 clocks 01 = CT 3 clocks, RP 16 clocks

10 = CT 2 clocks,

RP 4 clocks 10 = CT 2 clocks,

RP 8 clocks 10 = Reserved

11 = Reserved 11 = Reserved 11 = Reserved

SATA Controller Registers (D31:F2)

480 Intel® ICH8 Family Datasheet

12.1.25 IDE_CONFIG—IDE I/O Configur ation Register

(SATA–D31:F2)

Address Offset: 54h–57h Attribute: R/W

Default Value: 00000000h Size: 32 bits

Note: This register is R/W to maintain software compatibility and enable parallel ATA

functionality when the PCI functions are combined. These bits have no effect on SATA

operation, unless otherwise noted.

Bit Description

31:24 Reserved

23:20 Scratchpad (SP2). Intel® ICH8 does not perform any actions on these bits.

19:18

SEC_SIG_MODE — R/W. These bits are used to control mode of the Secondary IDE

signal pins for swap bay support.

If the SRS bit ( Chipset Configur ation Re gisters:Offset 3414h :bit 1) is 1, the re set states

of bits 19:18 will be 01 (tri-state) instead of 00 (normal).

00 = Normal (Enabled)

01 = Tr i-state (Disabl ed)

10 = Drive low (Disabled)

11 = Reserved

NOTE: In th e non-combined mode, these bits are for software compatibility and have

no effect on the SATA controller. In the combined mode, these bi ts are

controlling t h e behavior of t h e PATA controller. (Mobile Only)

17:16

PRIM_SIG_MODE — R/W. These bits are used to c o ntrol mode of the Primary IDE

signal pins for mobile swap bay support.

If the PRS bit (Chipset Confide Registers:Offset 3414h:bit 1) is 1, the reset states of

bits 17:16 will be 01 (tri-state) instead of 00 (normal).

00 = Normal (Enabled)

01 = Tr i-state (Disabl ed)

10 = Drive low (Disabled)

11 = Reserved

NOTE: In th e non-combined mode, these bits are for software compatibility and have

no effect on the SATA controller. In the combined mode, these bi ts are

controlling t h e behavior of t h e PATA controller. (Mobile Only)

Fast Secondary Drive 1 Base Clock (FAST_SCB1) — R/W. This bit is used in

conjunction with the SCT1 bits (D31:F2:4Ah, bits 13:12) to enable/disable Ultra ATA/

100 timings for the Secondary Slave drive.

0 = Disable Ultra ATA/100 timing for the Secondary Slave drive.

1 = Enable Ultra ATA/100 timing for the Secondary Slave drive (overrides bit 3 in this

Fast Secondary Drive 0 Base Clock (FAST_SCB0) — R/W. This bit is used in

conjunction with the SCT0 bits (D31:F2:4 Ah, bits 9:8) to enable/di sable Ultra ATA/100

timings for the Secondary Master drive.

0 = Disable Ul tra ATA/100 timing for the Secondary Master drive.

1 = Enable Ultra ATA/100 timing for the Secondary Master drive (overrides bit 2 in this

Intel® ICH8 Family Datasheet 481

SATA Controller Registers (D31:F2)

12.1.26 PID—PCI Power Management Capability Identification

Address Offset: 70h–71h Attribute: RO

Default Value: XX01h Size: 16 bits

Fast Primar y D r iv e 1 Base Clock (FAS T _ PCB1) — R/W. This bit is used in

conjunction with the PCT1 bits (D31:F2:4Ah, bits 5:4) to enable/disable Ultra ATA/100

timings for the Primary Slave drive.

0 = Disable Ultra ATA/100 timing for the Primary Slave drive.

1 = Enable Ultra ATA/100 timing for the Primary Slave drive (overrides bit 1 in this

Fast Primar y D r iv e 0 Base Clock (FAS T _ PCB0) — R/W. This bit is used in

conjunction with the PCT0 bits (D31:F2:4Ah, bits 1:0) to enable/disable Ultra ATA/100

timings for the Primary Master drive.

0 = Disable Ultra ATA/100 timing for the Primary Master drive.

1 = Enable Ultra ATA/100 timing for the Primary Master drive (overrides bit 0 in this

11:8 Reserved

7:4 Scratchpad (SP1). ICH8 does not perform any action on these bits.

3Secondary Driv e 1 B a se Clock (SCB1) — R/W.

0 = 33 MHz base clock for Ultra ATA timings.

1 = 66 MHz base clock for Ultra ATA timings

2Secondary Drive 0 Base Clock (SCBO) — R/W.

0 = 33 MHz base clock for Ultra ATA timings.

1 = 66 MHz base clock for Ultra ATA timings

1Primary Driv e 1 Base Clock (PCB1) — R/W.

0 = 33 MHz base clock for Ultra ATA timings.

1 = 66 MHz base clock for Ultra ATA timings

0Primary Driv e 0 Base Clock (PCB0) — R/W.

0 = 33 MHz base clock for Ultra ATA timings.

1 = 66 MHz base clock for Ultra ATA timings

Bit Description

Bits Description

15:8 Next Capability (NEXT) — RO.

00h — if SCC = 01h (IDE mode).

A8h — for all other values of SCC to point to the next capability structure.

7:0 Capability ID (CID) — RO. Indicates that this pointer is a PCI power management.

SATA Controller Registers (D31:F2)

482 Intel® ICH8 Family Datasheet

12.1.27 PC—PCI Power Management Capabilities Register

(SATA–D31:F2)

Address Offset: 72h–73h Attribute: RO

Default Value: 4003h Size: 16 bits

12.1.28 PMCS—PCI Power Management Control and Status

Address Offset: 74h–75h Attribute: RO, R/W, R/WC

Default Value: 0008h Size: 16 bits

Bits Description

15:11 PME Support (PME_SUP) — RO. Indicates PME# can be generated from the D3HOT state

in the SATA host controller.

10 D2 Supp ort (D2_SUP) — RO. Hardwired to 0. The D2 state is not supported

9 D1 Support (D1_SUP) — RO. Hardwired to 0. The D1 state is not supported

8:6 Auxiliary Current (AUX_CUR) — RO. PME# from D3COLD state is not supported,

therefore this field is 00 0b.

5Device Specifi c Initialization (DSI) — RO. Hardwired to 0 to indicate that no device-

specific initialization is required.

4 Reserved

3PME Clock (PME_CLK) — RO. Hardwired to 0 to indicate that PCI clock is no t required to

generate PME#.

2:0 Version (VER) — RO. Hardwired to 011 to indicates support for Revision 1.2 of the PCI

Power Management Specification.

Bits Description

15 PME Status (PMES) — R/WC. Bit i s set when a PME eve nt is to be requested, and if this

bit and PMEE is set, a PME# will be generated from the SATA controller

14:9 Reserved

8PME Enable (PMEE) — R/W. When set, the SATA controller generates PME# form

D3HOT on a wa ke event .

7:4 Reserved

No Soft Reset (NSFRST) — RO. These bits are used to indi cate whether devices

transitioning from D3HOT state to D0 state will perform an internal reset.

0 = Device transitioning from D3HOT state to D0 state perform an internal reset.

1 = Device transitioning from D3HOT state to D0 state do not perform an internal reset.

Configuration content is preserved. Upon transition from the D3HOT state to D0 state

initialized state , no additional operating system intervention is required to preserve

configuration context beyond writing to the Power State bits.

Regardless of this bit, the controller tr ansitio n from D3HOT state to D0 state by a system

or bus segment reset will return to the state D0 uninitiali zed with only PME context

preserved if PME is supported and enabled.

2 Reserved

1:0

Power State (PS) — R/W. These bit s are used both to determine the current power

state of the SATA con troller and to set a new power state.

00 = D0 state

11 = D3HOT state

When in the D3HOT state, the controller’ s configur ation space is avai lable, but the I/O and

memory spaces are not. Additionally, interrupts are blocked.

Intel® ICH8 Family Datasheet 483

SATA Controller Registers (D31:F2)

12.1.29 MSICI—Message Signaled Interrupt Capability

Identification (SATA–D31:F2)

Address Offset: 80h–81h Attribute: RO

Default Value: 7005h Size: 16 bits

Note: There is no support for MSI when the software is oper ating in legacy (IDE) mode when

AHCI is not enabled. Prior to switching from AHCI to IDE mode, software must make

sure that MSI is disabled.

12.1.30 MSIMC—Message Signaled Interrupt Message Control

(SATA–D31:F2)

Address Offset: 82h–83h Attribute: R/W, RO

Default Value: 0000h Size: 16 bits

Note: There is no support for MSI when the software is oper ating in legacy (IDE) mode when

AHCI is not enabled. Prior to switching from AHCI to IDE mode, software must make

sure that MSI is disabled.

Bits Description

15:8 Next Pointer (NEXT): Indicates the next item in the list is the PCI power management

pointer.

7:0 Capability ID (CID): Capabilities ID indicates MSI.

Bits Description

15:8 Reserved

764 Bit Address Capable (C64): Capable of generating a 32-bit message only.

SATA Controller Registers (D31:F2)

484 Intel® ICH8 Family Datasheet

6:4

Multiple Message Enable (MME): When this field is cleared to ‘000’ (and MSIE is set),

only a single MSI message will be generated for all SATA ports, and bits [15:0] of the

message vector will be driven from MD[15:0].

When this field is set to ‘001’ (and MSIE is set), two MSI messages will be generated. Bit

[15:1] of the message vectors will be driven from MD[15:1] and bit [0] of the message

vector will be driven dependent on which SATA port is the source of the interrupt: ‘0’ for

port 0, and ‘1’ for ports 1, 2, 3, 4 and 5.

When this field is set to ‘010’ (and MSIE is set), four mess ages will be genera ted, one for

each SATA port. Bits[15:2] of the message vectors will be driven from MD[15:2], while

bits[1:0] will be driven dependent on which SA TA port is the source of the interrupt: ‘00’

for port 0, ‘01’ for port 1, ‘10’ for port 2, and ‘11’ for ports 3, 4, and 5).

When this field is set to ‘100’ (and MSIE is set), seven messages will be generated, one

for each SATA port. Bits[15:2] of the message vectors will be driven from MD[15:3],

while bits[2:0] will be driven dependent on which SATA port is the source of the

interrupt: ‘000’ for port 0, ‘001’ for port 1, ‘010’ for port 2, ‘011’ for port 3, ‘100’ for port

4, ‘101 for port 5, and ‘110’ for port 6 (CCC interrupt).

Values ‘011b’ to ‘111b’ are reserved. If this field is set to one of these reserved values,

the results are undefined.

NOTE: Note: The CCC interrupt is generated on unimplemented port (AHCI PI register

bit equal to 0). If CCC interrupt is disabled, no MSI shall be generated for the port

dedicated to the CCC interrupt. When CCC interrupt occurs, MD[2:0] is

dependant on CCC_CTL.INT (in addition to MME).

3:1

Multiple Message Capable (MMC): I ndicates the number of interru pt messages

supported by the ICH8 SATA controller.

000 = 1 MSI Capable (When CC.SCC bit is set to 01h . MSI is not supported in IDE mo de)

010 = 4 MSI Capable

100 = 8 MSI Capable

MSI Enable (MSIE): If set, MSI is enabled and traditional interrupt pins are not used to

generate interrupts. This bit is R/W when SC.SCC is not 01h and is read-only 0 when

CC.SCC is 01h. Note that CMD.ID bit has no effect on MSI.

NOTE: Software must clear this bit to ‘0’ to disable MSI first before changing the number

of messages allocated in the MMC field. Software must also make sure this bit is

cleared to ‘0’ when operating in legacy mode (when GHC.AE = 0).

Bits Description

MME Value Driven on MSI Memory Write

Bits[15:2] Bit[2] Bit[1] Bit[0]

000 MD[15:0] MD[1] MD[1] MD[0]

001 MD[15:2] MD[1] MD[1] Ports 0: 0

Port s 1,2, 3: 1

010 MD[15:2]

Port 0: 0

Port 1: 0

Port 2: 1

Port 3: 1

Port 0: 0

Port 1: 0

Port 2: 1

Port 3: 1

Port 0: 0

Port 1: 1

Port 2: 0

Port 3: 1

100 MD[15:3]

Port 0: 000

Port 1: 001

Port 2: 010

Port 3: 011

Port 4: 100

Port 5: 101

Port 0: 000

Port 1: 001

Port 2: 010

Port 3: 011

Port 4: 100

Port 5: 101

Port 0: 000

Port 1: 001

Port 2: 010

Port 3: 011

Port 4: 100

Port 5: 101

Intel® ICH8 Family Datasheet 485

SATA Controller Registers (D31:F2)

12.1.31 MSIMA— Message Signaled Interrupt Message Address

(SATA–D31:F2)

Address Offset: 84h–87h Attribute: RO, R/W

Default Value: 00000000h Size: 32 bits

Note: There is no support for MSI when the software is oper ating in legacy (IDE) mode when

AHCI is not enabled. Prior to switching from AHCI to IDE mode, software must make

sure that MSI is disabled.

12.1.32 MSIMD—Message Signaled Interrupt Message Data

(SATA–D31:F2)

Address Offset: 88h-89h Attribute: R/W

Default Value: 0000h Size: 16 bits

Note: There is no support for MSI when the software is oper ating in legacy (IDE) mode when

AHCI is not enabled. Prior to switching from AHCI to IDE mode, software must make

sure that MSI is disabled.

Bits Description

31:2 Address (ADDR): Lower 32 bits of the system specified message address, always

DWORD aligned.

1:0 Reserved

Bits Description

15:0

Data (DATA) — R/W: This 16-bit field is programmed by system software if MSI is

enabled. Its content is driven onto the lower word of the data bus of the MSI memory

write transaction. Note that when the MME field is set to ‘001’ or ‘010’, bit [0] and bits

[1:0] respectively of the MSI memory write transaction will be driven based on the

source of the interrupt rather than from MD[2:0]. See the description of the MME field.

SATA Controller Registers (D31:F2)

486 Intel® ICH8 Family Datasheet

12.1.33 MAP—Address Map Register (SATA–D31:F2)

Address Offset: 90h Attribute: R/W

Default Value: 00h Size: 8 bits

Bits Description

7:6

SATA Mode Select (SMS) — R/W: SW programs these bits to control the mo de in

which the SATA HBA should operate:

00b = IDE mode

01b = AHCI mode

10b = RAID mode

11b = Reserved

NOTES:

1. The SATA Function Device ID will change based on the value of this register.

2. When combined m o de is used (MV = ‘10’), only IDE mode is allowed. IDE

mode can be selected when AHCI and/or RAID are enabled

3. When switching from AHCI or RAID mode to IDE mode, a 2 port SATA

controller (Device 31 , Function 5) shall be enabled.

4. AHCI mode may only be selected when MV = 00

5. RAID mode may only be selected when MV = 00

6. Progr amming t hese bits wi th v alu es that are inv alid (e.g. selecting RAID when

in combin ed mode) will result in indeterministic behavior by the hardware.

7. Software shall not manipulate SMS during runtime operation (i.e., the OS will

not do this). The BIOS may choose to switch from one mode to another during

POST.

5:2 Reserved.

1:0

(Desktop

Only) Map Value — R/W. Map Value (MV): Reserved

1:0

(Mobile

Only)

Map Value — R/W. Map Value (MV): The value in the bits below indicate the address

range the SATA ports responds to, and whether or not the PATA and SATA functions

are combined. When in combined mode, the AHCI memory space is not available and

AHCI may not be used.

00 =Non-combined. P0 is primary master, P2 is the primary slave. P1 is secondary

master, P3 is the secondary slave.

01 =Reserved

10 =Combined. P0 is primary master. P2 is primary slave. IDE is secondary

11 =Reserved

NOTES:

1. Programming thes e bits with values that are inv alid (e.g. , selec ting RAID when

in combin ed mode) will result in indeterministic behavior by the hardware.

2. SW shall not manipulate MV during runtime operation; i.e. the OS will not do

this. The BIOS may choose to switch from one mode to another during POST.

Intel® ICH8 Family Datasheet 487

SATA Controller Registers (D31:F2)

12.1.34 PCS—Port Control and Status Register (SATA–D31:F2)

Address Offset: 92h–93h Attribute: R/W , R/WC, RO

Default Value: 0000h Size: 16 bits

By default, the SA TA ports are set to the disabled state (bits [5:0] = ‘0’). When enabled

by software, the ports can transition between the on, partial, and slumber states and

can detect devices. When disabled, the port is in the “off” state and cannot detect any

devices.

If an AHCI- aware or RAID enabled oper ating system is being booted then system BIOS

shall ensure that all supported SATA ports are enabled prior to passing control to the

OS. Once the AHCI aware OS is booted it becomes the enabling/disabling policy owner

for the individual SA TA ports. This is accomplished by manipulating a port’s PxSCTL and

PxCMD fields. Because an AHCI or RAID aware OS will typically not have knowledge of

the PxE bits and because the PxE bits act as master on/off switches for the ports, pre-

boot software must ensure that these bits are set to ‘1’ prior to booting the OS,

regardless as to whether or not a device is currently on the port.

Bits Description

OOB Retry Mode (ORM) — R/W.

0 = The SATA controller will not retry after an OOB failure

1 = The SATA controller will continue to retry after an OOB failure until successful

(infinite retry)

14 Reserved.

Port 5 Present (P5P) — RO . The status of th is bit ma y change at an y time. This bit is

cleared when the port is disabled via P5E. This bit is not cleared upon surprise removal

of a device.

0 = No device detected.

1 = The presence of a device on Port 3 has been detected.

Port 4 Present (P4P) — RO . The status of th is bit ma y change at an y time. This bit is

cleared when the port is disabled via P4E. This bit is not cleared upon surprise removal

of a device.

0 = No device detected.

1 = The presence of a device on Port 3 has been detected.

Port 3 Present (P3P) — RO . The status of th is bit ma y change at an y time. This bit is

cleared when the port is disabled via P3E. This bit is not cleared upon surprise removal

of a device.

0 = No device detected.

1 = The presence of a device on Port 3 has been detected.

Port 2 Present (P2P) — RO . The status of th is bit ma y change at an y time. This bit is

cleared when the port is disabled via P2E. This bit is not cleared upon surprise removal

of a device.

0 = No device detected.

1 = The presence of a device on Port 2 has been detected.

Port 1 Present (P1P) — RO . The status of th is bit ma y change at an y time. This bit is

cleared when the port is disabled via P1E. This bit is not cleared upon surprise removal

of a device.

0 = No device detected.

1 = The presence of a device on Port 1 has been detected.

SATA Controller Registers (D31:F2)

488 Intel® ICH8 Family Datasheet

Port 0 Present (P0P) — RO. The status of this bit may change at any time. This bi t is

cleared when the port is disabled via P0E. This bit is not cleared upon surprise removal

of a device.

0 = No device detected.

1 = The presence of a device on Port 0 has been detected.

7:6 Reserved

Port 5 Enabled (P5E) — R/W.

0 = Disabled. The port is in the ‘off’ state and can not detect any devices.

1 = Enabled. The port can transition between the on, partial, and slumber states and

can detect devices.

NOTE: This bit takes precedence over P5CMD.SUD (offset ABAR+298h:bit 1)

Port 4 Enabled (P4E) — R/W.

0 = Disabled. The port is in the ‘off’ state and can not detect any devices.

1 = Enabled. The port can transition between the on, partial, and slumber states and

can detect devices.

NOTE: This bit takes precedence over P4CMD.SUD (offset ABAR+298h:bit 1)

Port 3 Enabled (P3E) — R/W.

0 = Disabled. The port is in the ‘off’ state and can not detect any devices.

1 = Enabled. The port can transition between the on, partial, and slumber states and

can detect devices.

NOTE: This bit takes precedence over P3CMD.SUD (offset ABAR+298h:bit 1)

Port 2 Enabled (P2E) — R/W.

0 = Disabled. The port is in the ‘off’ state and can not detect any devices.

1 = Enabled. The port can transition between the on, partial, and slumber states and

can detect devices.

NOTE: This bit takes precedence over P2CMD.SUD (offset ABAR+218h:bit 1)

Port 1 Enabled (P1E) — R/W.

0 = Disabled. The port is in the ‘off’ state and can not detect any devices.

1 = Enabled. The port can transition between the on, partial, and slumber states and

can detect devices.

NOTE: This bit takes precedence over P1CMD.SUD (offset ABAR+198h:bit 1)

Port 0 Enabled (P0E) — R/W.

0 = Disabled. The port is in the ‘off’ state and can not detect any devices.

1 = Enabled. The port can transition between the on, partial, and slumber states and

can detect devices.

NOTE: This bit takes precedence over P0CMD.SUD (offset ABAR+118h:bit 1)

Bits Description

Intel® ICH8 Family Datasheet 489

SATA Controller Registers (D31:F2)

12.1.35 SCLKCG—SATA Clock Gating Control Register

Address Offset: 94h-97h Attribute: R/W

Default Value: 00000000h Size: 32 bits

Bit Description

31 Reserved

SATA Clock Request Enabled (SCRE) — R/W.

0 = SATA Clock Request protocol is disabled. SATACLKREQ # pin when in native

function will always output '0' to keep the SATA clock running.

1 = SATA Clock Request protocol is enabled. SATACLKREQ# pin when in native

function will behave as the Serial ATA clock request to the system clock chip.

28 Reserved

27:24

(Desktop

Only) Reserved

27:24

(Mobile

Only)

SATA Initialization Field 3 (SIF3) — R/W. BIOS shall always program this

23 SATA Initialization Field 2 (SIF2) — R/W. BIOS shall always program this

22:9 Reserved

8:0 SATA Initialization Field 1 (SIF1) — R/W. BIOS shall always program this

SATA Controller Registers (D31:F2)

490 Intel® ICH8 Family Datasheet

12.1.36 SCLKGC—SATA Clock General Configuration Register

Address Offset: 9Ch Attribute: R/W

Default Value: 00h Size: 8 bits

12.1.37 SIRI—SATA Indexed Registers Index Register

Address Offset: A0h Attribute: R/W

Default Value: 00h Size: 8 bits

12.1.38 STRD—SATA Indexed Register Data Register

Address Offset: A4h Attribute: R/W

Default Value: XXXXXXXXh Size: 32 bits

Bit Description

7:2 Reserved

SATA2-port Configuration Indic a tor (SATA2PIND) — RO.

0 = Normal configuration.

1 = One IDE Controller is implemented supporting only two ports for a Primary

Master and a Secondary Master.

NOTE: When set, BIOS must ensure that bit 2 and bit 3 of the AHCI PI registers are

zeros. BIOS must also make sure that Port 2 and Port 3 are disabled (via PCS

configuration register) and the port clocks are gated (via SCLKCG

configuration register).

SATA4-por t Al l Master Configuration Indicator (SATA4 P MIND) — RO.

0 = Normal configuration.

1 = Two IDE Controllers are implemented, each supporting only two ports for a

Primary Master and a Secondary Master.

NOTE: When set, BIOS must ensure that bit 2 and bit 3 of the AHCI PI registers are

zeros. BIOS must also make sure that Port 2 and Port 3 are disabled (via PCS

configuration register) and the port clocks are gated (via SCLKCG

configuration register).

Bit Description

7:2 Index (IDX) — R/W. This field is a 5-bit index pointer into the SATA Indexed Register

space. Data is written into and read from the SIRD register (D31:F2:A4h).

1:0 Reserved

Bit Description

31:0 Data (DTA) — R/W. 32-bit data valu e that i s writ ten to th e regist er poin ted to by SIRI

(D31:F2;A0h) or read from the register pointed to by SIRI.

Intel® ICH8 Family Datasheet 491

SATA Controller Registers (D31:F2)

Table 122. SATA Indexed Registers

Index Name

00h–03h SATA TX Termination Test Register 1 (STTT1)

04h–17h Reserved

18h–1Bh SATA Initialization Register 18 (SIR18)

1Ch–1Fh SATA Test Mode Enable Register (STME)

20h–27h Reserved

28h–2Bh SATA Initialization Register 28 (SIR28)

40h–43h SATA Initialization Register 40 (SIR40)

44h–73h Reserved

74h–77h SATA TX Termination Test Register 2 (STTT2)

78h–7Bh SATA Initialization Register 78 (SIR78)

7Ch–83h Reserved

84h–87h SATA Initialization Register 84 (SIR84)

88h–8Bh SATA Initialization Register 88 (SIR88)

8Ch–8Fh SATA Initialization Register 8C (SIR8C)

90h–93h SATA TX Termination Test Register 3 (STTT3)

94h–97h SATA Initialization Register 94 (SIR94)

98h–9Fh Reserved

A0h–A3h SATA Initialization Register A0 (SIRA0)

A4h–A7h Reserved

A8h–ABh SATA Initialization Register A8 (SIRA8)

ACh–AFh SATA Initialization Register AC (SIRAF)

SATA Controller Registers (D31:F2)

492 Intel® ICH8 Family Datasheet

12.1.39 STTT1—SATA Indexed Registers Index 00h

(SATA TX Termination Test Register 1)

Address Offset: Index 00h - 03h Attribute: R/W

Default Value: 00000000h Size: 32 bits

12.1.40 SIR18—SATA Indexed Registers Index 18h

(SATA Initialization Register 18h)

Address Offset: Index 18h - 1Bh Attribute: R/W

Default Value: 0000025Bh Size: 32 bits

12.1.41 STME—SATA Indexed Registers Index 1Ch

(SATA Test Mode Enable Register)

Address Offset: Index 1Ch - 1Fh Attribute: R/W

Default Value: 00000000h Size: 32 bits

Bit Description

31:2 Reserved.

Port 1 TX Termination Test Enable — R/W:

0 = Port 1 TX termination port testing is disabled.

1 = Setting this bit will enable testing of Port 1 TX termination.

Note: This bit only to be used for system board testing.

Port 0 TX Termination Test Enable — R/W:

0 = Port 0 TX termination port testing is disabled.

1 = Setting this bit will enable testing of Port 0 TX termination.

Note: This bit only to be used for system board testing.

Bit Description

31:10 Reserved.

9:0 BIOS programs this field to 1000011011b.

Bit Description

31:19 Reserved.

SATA Test Mode Enable Bit — R/W:

0 = Entrance to Intel ICH6 SATA test modes are disabled.

1 = This bit allows entrance to Intel ICH6 SATA test modes when set.

Note: This bit only to be used for system board testing.

17:0 Reserved.

Intel® ICH8 Family Datasheet 493

SATA Controller Registers (D31:F2)

12.1.42 SIR28—SATA Indexed Registers Index 28h

(SATA Initialization Register 28h)

Address Offset: Index 28h - 2Bh Attribute: R/W

Default Value: 00CC2080h S i ze: 32 bits

12.1.43 SIR40—SATA Indexed Registers Index 40h

(SATA Initialization Register 40h)

Address Offset: Index 40h - 43h Attribute: R/W

Default Value: 0011006Dh Size: 32 bits

12.1.44 STTT2—SATA Indexed Registers Index 74h

(SATA TX Termination Test Register 2)

Address Offset: Index 74h - 77h Attribute: R/W

Default Value: 00000000h Size: 32 bits

Bit Description

31:0 BIOS programs this field to 00CC2080h.

Bit Description

31:24 Reserved

23:16 BIOS programs this field to 22h.

15:0 Reserved

Bit Description

31:18 Reserved.

Port 3 TX Termination Test Enable — R/W:

0 = Port 3 TX termination port testing is disabled.

1 = Setting this bit will enable testing of Port 3 TX termination.

Note: This bit only to be used for system board testing.

Port 2 TX Termination Test Enable — R/W:

0 = Port 2 TX termination port testing is disabled.

1 = Setting this bit will enable testing of Port 2 TX termination.

Note: This bit only to be used for system board testing.

15:0 Reserved.

SATA Controller Registers (D31:F2)

494 Intel® ICH8 Family Datasheet

12.1.45 SIR78—SATA Indexed Registers Index 78h

(SATA Initialization Register 78h)

Address Offset: Index 78h - 7Bh Attribute: R/W

Default Value: 00330000h Size: 32 bits

12.1.46 SIR84—SATA Indexed Registers Index 84h

(SATA Initialization Register 84h)

Address Offset: Index 84h - 87h Attribute: R/W

Default Value: 0000001Bh Size: 32 bits

12.1.47 SIR88—SATA Indexed Registers Index 88h

(SATA Initialization Register 88h)

Address Offset: Index 88h - 8Bh Attribute: R/W

Default Value: 2D2D2424h Size: 32 bits

12.1.48 SIR8C—SATA Indexed Register s Index 8Ch

(SATA Initialization Register 8Ch)

Address Offset: Index 8Ch - 8Fh Attribute: R/W

Default Value: 24240055h Size: 32 bits

Bit Description

31:24 Reserved

23:16 BIOS programs this field to 22h.

15:0 Reserved

Bit Description

31:0 BIOS programs this field to 0000001Bh.

Bit Description

31:0 BIOS programs this field to 24242424h.

Bit Description

31:0 BIOS programs this field to 090900AAh.

Intel® ICH8 Family Datasheet 495

SATA Controller Registers (D31:F2)

12.1.49 STTT3—SATA Indexed Registers Index 90h

(SATA TX Termination Test Register 3)

Address Offset: Index 90h - 93h Attribute: R/W

Default Value: 00000000h Size: 32 bits

12.1.50 SIR94—SATA Indexed Registers Index 94h

(SATA Initialization Register 94h)

Address Offset: Index 94h - 97h Attribute: R/W

Default Value: 00000011h Size: 32 bits

12.1.51 SIRA0—SATA Indexed Registers Index A0h

(SATA Initialization Register A0h)

Address Offset: Index A0h - A3h Attribute: R/W

Default Value: 0000001Bh Size: 32 bits

12.1.52 SIRA8—SATA Indexed Registers Index A8h

(SATA Initialization Register A8h)

Address Offset: Index A8h - ABh Attribute: R/W

Default Value: 002D0024h Size: 32 bits

Bit Description

31:2 Reserved.

Port 5 TX Termination Test Enable — R/W:

0 = Port 1 TX termination port testing is disabled.

1 = Setting this bit will enable testing of Port 1 TX termination.

NOTE: This bit only to be used for system board testing.

Port 4 TX Termination Test Enable — R/W:

0 = Port 0 TX termination port testing is disabled.

1 = Setting this bit will enable testing of Port 0 TX termination.

NOTE: This bit only to be used for system board testing.

Bit Description

31:0 BIOS programs this field to 00000022h.

Bit Description

31:0 BIOS programs this field to 0000001Bh.

Bit Description

31:0 BIOS programs this field to 00240024h.

SATA Controller Registers (D31:F2)

496 Intel® ICH8 Family Datasheet

12.1.53 SIRAC—SATA Indexed Registers Index ACh

(SATA Initialization Register ACh)

Address Offset: Index ACh - AFh Attribute: R/W

Default Value: 00240005h Size: 32 bits

12.1.54 SATACR0—SATA Capability Register 0 (SATA–D31:F2)

Address Offset: A8h–ABh Attribute : RO

Default Value: 00100012h Size: 32 bits

Note: This register shall be read-only 0 when CC.SCC is 01h.

Bit Description

31:0 BIOS programs this field to 0009000Ah.

Bit Description

31:24 Reserved

23:20 Major Revision (MAJREV) — RO: Major revision number of the SATA Capability Pointer

implemented.

19:16 Minor Revision (MINREV) — RO: Minor revision number of the SATA Capa bility Pointer

implemented.

15:8 Next Capability Pointer (NEXT) — RO: Points to the next capability structure. 00h

indicates this is the last capability pointer.

7:0 Capability ID (CAP)— RO: This value of 12h has been assigned by the PCI SIG to

designate the SATA Capability Structure.

Intel® ICH8 Family Datasheet 497

SATA Controller Registers (D31:F2)

12.1.55 SATACR1—SATA Capability Register 1 (SATA–D31:F2)

Address Offset: ACh–AFh Attribute: RO

Default Value: 00000048h Size: 32 bits

Note: This register shall be read-only 0 when CC.SCC is 01h.

Bit Description

31:16 Reserved

15:4

BAR Offset (BAROFST) — RO: Indicates the offset into the BAR where the Index/Data

pair are located (in Dword granularity). The Index and Data I/O registers are loca ted at

offset 10h within the I/O space defined by LBAR. A value of 004h indicates offset 10h.

000h = 0h offset

001h = 4h offset

002h = 8h offset

003h = Bh offset

004h = 10h offset

...

FFFh = 3FFFh offset (max 16KB)

3:0

BAR Location (BARLOC) — RO: Indicates the absolute PCI Configuration Register

address of the BAR containing the Index/Data pair (in Dword granularity). The Index

and Data I/O registers reside within the space defined by LBAR in the SATA controller. A

value of 8h indicates offset 20h, which is LBAR.

0000 – 0011b = reserved

0100b = 10h => BAR0

0101b = 14h => BAR1

0110b = 18h => BAR2

0111b = 1Ch => BAR3

1000b = 20h => LBAR

1001b = 24h => BAR5

1010 – 1110b = reserved

1111b = Index/Data pair in PCI Configuration space. This isn’t supported in ICH8.

SATA Controller Registers (D31:F2)

498 Intel® ICH8 Family Datasheet

12.1.56 ATC—APM Trapping Control Register (SATA–D31:F2)

Address Offset: C0h Attribute: R/W

Default Value: 00h Size: 8 bits

12.1.57 ATS—APM Trapping Status Register (SATA–D31:F2)

Address Offset: C4h Attribute: R/WC

Default Value: 00h Size: 8 bits

12.1.58 SP Scratch Pad Register (SATA–D31:F2)

Address Offset: D0h Attribute: R/W

Default Value: 00000000h Size: 32 bits

Bit Description

7:4 Reserved

3Secondary Slave Trap (SST) — R/W. Enables trapping and SMI# assertion on legacy

I/O accesses to 170h-177h and 376h. The active device on the secondary interface

must be device 1 for the trap and/or SMI# to occur.

2Secondary Master Trap (SPT) — R/W. Enables trapping and SMI# assertion on

legacy I/O accesses to 170h-177h and 37 6h. The active device on the secondary

interface must be device 0 for the trap and/or SMI# to occur.

1Primary Slave Trap (PST) — R/W. Enables trapping and SMI# assertion on legacy I/

O accesses t o 1F0h-1F7h and 3F6h. The active device on the primary interface must be

device 1 for the trap and/or SMI# to occur.

0Primary Master Trap (PMT) — R/W. Enables trapping and SMI# assertion on legacy

I/O accesses to 1F0h-1F7h and 3F6h. The active device on the primary interface must

be device 0 for the trap and/or SMI# to occur.

Bit Description

7:4 Reserved

3Secondary Slave Trap (SST) — R/WC. Indicates that a trap occurred to the

secondary slave device.

2Secondary Master Trap (SPT) — R/WC. Indicates that a trap occurred to the

secondary master device.

1Primary Slave Trap (PST) — R/WC. Indicates that a trap occurred to the primary

slave device.

0Primary Master Trap (PMT) — R/WC. Indicates that a trap occurred to the primary

master device.

Bit Description

31:0 Data (DT) — R/W. This is a read/write register that is available for software to use. No

hardware action is taken on this register.

Intel® ICH8 Family Datasheet 499

SATA Controller Registers (D31:F2)

12.1.59 BFCS—BIST FIS Control/Status Register (SATA–D31:F2)

Address Offset: E0h–E3h Attribute: R/W, R/WC

Default Value: 00000000h Size: 32 bits

Bits Description

31:16 Reserved

(Desktop

Only)

Port 5 BIST FI S Initiate (P5BFI ) — R/W . When a rising edge is detected on this bit

field, the ICH8 initiates a BIST FIS to the device on Port 5, using the par ameters

specified in this register and the data specified in BFTD1 and BFTD2. The BIST FIS

will only be initiated if a device on Port 5 is present and ready (not partial/slumber

state). After a BIST FIS is successfully completed, software must disable and re-

enable the port using the PxE bits at offset 92h prior to attempting additional BIST

FISs or to return the ICH8 to a normal operational mode. If the BIST FIS fails to

complete, as indicated by the BFF bit in the register, then software can clear then set

the P5BFI bit to initiate another BIST FIS. This can be retried until the BIST FIS

eventually com pletes successfully

(Desktop

Only)

Port 4 BIST FI S Initiate (P4BFI ) — R/W . When a rising edge is detected on this bit

field, the ICH8 initiates a BIST FIS to the device on Port 4, using the par ameters

specified in this register and the data specified in BFTD1 and BFTD2. The BIST FIS

will only be initiated if a device on Port 4 is present and ready (not partial/slumber

state). After a BIST FIS is successfully completed, software must disable and re-

enable the port using the PxE bits at offset 92h prior to attempting additional BIST

FISs or to return the ICH8 to a normal operational mode. If the BIST FIS fails to

complete, as indicated by the BFF bit in the register, then software can clear then set

the P4BFI bit to initiate another BIST FIS. This can be retried until the BIST FIS

eventually com pletes successfully

(Desktop

Only)

Port 3 BIST FI S Initiate (P3BFI ) — R/W . When a rising edge is detected on this bit

field, the ICH8 initiates a BIST FIS to the device on Port 3, using the par ameters

specified in this register and the data specified in BFTD1 and BFTD2. The BIST FIS

will only be initiated if a device on Port 3 is present and ready (not partial/slumber

state). After a BIST FIS is successfully completed, software must disable and re-

enable the port using the PxE bits at offset 92h prior to attempting additional BIST

FISs or to return the ICH8 to a normal operational mode. If the BIST FIS fails to

complete, as indicated by the BFF bit in the register, then software can clear then set

the P3BFI bit to initiate another BIST FIS. This can be retried until the BIST FIS

eventually com pletes successfully

(Mobile

Only) Reserved.

Port 2 BIST FI S Initiate (P2BFI ) — R/W . When a rising edge is detected on this bit

field, the ICH8 initiates a BIST FIS to the device on Port 2, using the par ameters

specified in this register and the data specified in BFTD1 and BFTD2. The BIST FIS

will only be initiated if a device on Port 2 is present and ready (not partial/slumber

state). After a BIST FIS is successfully completed, software must disable and re-

enable the port using the PxE bits at offset 92h prior to attempting additional BIST

FISes or to return the ICH8 to a normal operational mode. If the BIST FIS fails to

complete, as indicated by the BFF bit in the register, then software can clear then set

the P2BFI bit to initiate another BIST FIS. This can be retried until the BIST FIS

eventually com pletes successfully

BIST FIS Suc cessful (BFS) — R/WC.

0 = Software clears this bit by writing a 1 to it.

1 = This bit is set any time a BIST FIS transmitted by ICH8 receives an R_OK

completion status from the device.

NOTE: This bit must be cleared by software prior to initiating a BIST FIS.

SATA Controller Registers (D31:F2)

500 Intel® ICH8 Family Datasheet

BIST FIS Failed (BFF) — R/WC.

0 = Software clears this bit by writing a 1 to it.

1 = This bit is set any time a BIST FI S transmitted by ICH8 receives an R_ERR

completion status from the device.

NOTE: This bit must be cleared by software prior to initiating a BIST FIS.

(Desktop

Only)

Port 1 BIST FIS Initiate (P 1BFI) — R/W. When a risin g edge is detected on this bit

field, the ICH8 initiates a BIST FIS to the device on Port 1, using the parameters

specified in this register and the data specified in BFTD1 and BFTD2. The BIST FIS

will only be initiated if a device on Port 1 is present and ready (not partial/slumber

state). After a BIST FIS is successfully completed , software must disable and re-

enable the port using the PxE bits at offset 92h prior to attempting additional BIST

FISes or to return the ICH8 to a normal operational mode. If the BIST FIS fails to

complete, as indicated by the BFF bit in the register, then software can clear then set

the P1BFI bit to initiate another BIST FIS. This can be retried until the BIST FIS

eventually completes successfully

(Mobile

Only) Reserved.

Port 0 BIST FIS Initiate (P0 BFI) — R/W. When a rising edge is detected on this bit

field, the ICH8 initiates a BIST FIS to the device on Port 0, using the parameters

specified in this register and the data specified in BFTD1 and BFTD2. The BIST FIS

will only be initiated if a device on Port 0 is present and ready (not partial/slumber

state). After a BIST FIS is successfully completed , software must disable and re-

enable the port using the PxE bits at offset 92h prior to attempting additional BIST

FISes or to return the ICH8 to a normal operational mode. If the BIST FIS fails to

complete, as indicated by the BFF bit in the register, then software can clear then set

the P0BFI bit to initiate another BIST FIS. This can be retried until the BIST FIS

eventually completes successfully

7:2

BIST FIS Parameters. These 6 bits form the contents of the upper 6 bits of the

BIST FIS Pattern Definition in any BIST FIS transmitted by the ICH8. This field is not

port specific — its contents will be used for any BIST FIS initiated on port 0, po rt 1,

port 2 or port 3. The specific bit definitions are:

Bit 7: T – Far End Transmit mode

Bit 6: A – Align Bypass mode

Bit 5: S – Bypass Scrambling

Bit 4: L – Far End Retimed Loopback

Bit 3: F – Far En d Analog Loopback

Bit 2: P – Primitive bit for use with Transmit mode

1:0 Reserved

Bits Description

Intel® ICH8 Family Datasheet 501

SATA Controller Registers (D31:F2)

12.1.60 BFTD1—BIST FIS Transmit Data1 Register (SATA–D31:F2)

Address Offset: E4h–E7h Attribute: R/W

Default Value: 00000000h Size: 32 bits

12.1.61 BFTD2—BIST FIS Transmit Data2 Register (SATA–D31:F2)

Address Offset: E8h–EBh Attribute: R/W

Default Value: 00000000h Size: 32 bits

Bits Description

31:0

BIST FIS Transmit Data 1 — R/W. The data programmed into this register will form

the contents of the second dword of any BIST FIS initiated b y the ICH8. This regis te r i s

not port specific — its contents will be used for BIST FIS initiated on any port. Although

the 2nd and 3rd DWs of the BIST FIS are only meaningful when the “T” bit of the BIST

FIS is set to indicate “Far-End Transmit mode”, this register’s contents will be

transmitted as the BIST FIS 2nd DW regardless of whether or not the “T” bit is indicated

in the BFCS register (D31:F2:E0h).

Bits Description

31:0

BIST FIS Transmit Data 2 — R/W. The data programmed into this register will form

the contents of the third dword of any BIST FIS initiated by the ICH8. This register is not

port specific — its contents will be used for BIST FIS initiated on any port. Although the

2nd and 3rd DWs of the BIST FIS are only meaningful when the “T” bit of the BIST FIS

is set to indicate “Far-End T ransmit mode” , this register’s contents will be transmitted as

the BIST FIS 3rd DW regardless of whether or not the “T” bit is indicated in the BFCS

SATA Controller Registers (D31:F2)

502 Intel® ICH8 Family Datasheet

12.2 Bus Master IDE I/O Registers (D31:F2)

The bus master IDE function uses 16 by tes of I/O space, allocated via the BAR register,

located in Device 31:Function 2 Configur ation space, offset 20h. All bus master IDE I/O

space registers can be accessed as byte, word, or dword quantities. Reading reserved

bits returns an indeterminate, inconsistent value, and writes to reserved bits have no

affect (but should not be attempted). These registers are only used for legacy

operation. Software must not use these registers when running AHCI. The description

of the I/O registers is shown in Table 123.

Table 123. Bus Master IDE I/O Register Address Map

BAR+

Offset Mnemonic Register Default Type

00 BMICP Command Register Primary 00h R/W

01 — Reserved — RO

02 BMISP Bus Master IDE Status Register Primary 00h R/W , R/WC,

03 — Reserved — RO

04–07 BMIDP Bus Master IDE Descriptor Table Pointer

Primary xxxxxxxxh R/W

08 BMICS Command Register Secondary 00h R/W

09 — Reserved — RO

0Ah BMISS Bus Master IDE Status Register Secondary 00h R/W , R/WC,

0Bh — Reserved — RO

0Ch–0Fh BMIDS Bus Master IDE Descript or Table Pointer

Secondary xxxxxxxxh R/W

10h AIR AHCI Index Register 00000000h R/W, RO

14h AIDR AHCI Index Data Register xxxxxxxxh R/W

Intel® ICH8 Family Datasheet 503

SATA Controller Registers (D31:F2)

12.2.1 BMIC[P,S]—Bus Master IDE Command Register (D31:F2)

Address Offset: Primary: BAR + 00h Attribute: R/W

Secondary: BAR + 08h

Default Value: 00h Size: 8 bits

Bit Description

7:4 Reserved. Returns 0.

Read / Write Control (R/WC) — R/W. This bit sets the direction of the bus master

transfer: This bit must NOT be changed when the bus master function is active.

0 = Memory reads

1 = Memory writes

2:1 Reserved. Returns 0.

Start/Stop Bus Master (START) — R/W.

0 = All state information is lost when this bit is cleared. Master mode operation cannot

be stopped and then resumed. If this bit is reset while bus master operation is still

active (i.e., the Bus Master IDE Active bit (D31:F2:BAR + 02h, bit 0) of the Bus

Master IDE Status register for that IDE channel is set) and th e drive has not yet

finished it s data trans fer (the Interru pt bit in the Bus Master IDE Status register for

that IDE channel is not set), the bus master command is said to be aborted and

data transferred from the drive may be discarded instead of being written to

system memory.

1 = Enables bus master operation of the controller. Bus master operation does not

actually start unless the Bus Master Enable bit (D31:F1:04h, bit 2) in PCI

configuration space is also set. Bu s master operation begins when this bit is

detected changing from 0 to 1. The controller will transfer data between the IDE

device and memory only when this bit is set. Master operation can be halted by

writing a 0 to thi s bit.

NOTE: This bit is intended to be cleared by software after the data transfer is

completed, as indicated by either the Bus Master IDE Active bit being cleared or

the Interrupt bit of the Bus Master IDE Status register for that IDE channel

being set, or both. Hardware does not clear this bit automatically. If this bit is

cleared to 0 prior to the DMA data transfer being initiated by the drive in a

SATA Controller Registers (D31:F2)

504 Intel® ICH8 Family Datasheet

12.2.2 BMIS[P,S]—Bus Master IDE Status Register (D31:F2)

Address Offset: Primary: BAR + 02h Attribute: R/W, R/WC, RO

Secondary: BAR + 0Ah

Default Value: 00h Size: 8 bits

Bit Description

PRD Interrupt Status (PRDIS) — R/WC.

0 = Software clears this bit by writing a 1 to it.

1 = This bit is set when the host controller execution of a PRD that has its PRD _IN T bit

set.

Drive 1 DMA Capa ble — R/W.

0 = Not Capable.

1 = Capable. Set by device dependent code (BIOS or device driver) to indicate that

drive 1 for this channel is capable of DMA transfers, and that the controller has been

initialized for optimum performance. The Inte l® ICH8 does not use this bit. It is

intended for systems that do not attach BMIDE to the PCI bus.

Drive 0 DMA Capa ble — R/W.

0 = Not Capable

1 = Capable. Set by device dependent code (BIOS or device driver) to indicate that

drive 0 for this channel is capable of DMA transfers, and that the controller has been

initialized for optimum performance. The ICH8 does not use this bit. It is intended

for systems that do not attach BMIDE to the PCI bus.

4:3 Reserved. Retur ns 0.

Interrupt — R/WC .

0 = Software clears this bit by writing a 1 to it.

1 = Set when a device FIS is received with the ‘I’ bit set, provided that software has not

disabled interrupts via the IE N bit of the Device Control Register (see chapter 5 of

the Serial ATA Specification, Revision 2.5).

Error — R/WC.

0 = Software clears this bit by writing a 1 to it.

1 = This bit is set wh en the controller encounters a target abort or master abort when

transferring data on PCI.

Bus Master IDE Active (ACT) — RO.

0 = This bit is cleared by the ICH8 when the last transfer for a region is performed,

where EOT for that region is set in the region descriptor. It is also cleared by the

ICH8 when the Start Bus Master bit (D31:F2:BAR+ 00h, bit 0) is cleared in the

Command register. When this bit is read as a 0, all data transferred from the drive

during the previous bus master command is visible in system memory, unless the

bus master command was aborted.

1 = Set by the ICH8 when the Start bit is written to the Command register.

Intel® ICH8 Family Datasheet 505

SATA Controller Registers (D31:F2)

12.2.3 BMID[P,S]—Bus Master IDE Descriptor Table Pointer

Address Offset: Primary: BAR + 04h–07h Attribute: R/W

Secondary: BAR + 0Ch–0Fh

Default Value: All bits undefined Size: 32 bits

12.2.3.1 PxSSTS—Serial ATA Status Register (D31:F5)

Address Offset: BAR + 00h Attribute: RO

Default Value: 00000000h Size: 32 bits

This is a 32-bit register that conveys the current state of the interface and host. The

ICH8 updates it continuously and asynchronously. When the ICH8 transmits a

COMRESET to the device, this register is updated to its reset values.

Bit Description

31:2

Address of Descriptor Table (ADDR) — R/W. The bits i n this field co rrespond to bits

[31:2] of the memory location of the Physical Re gion Descriptor (PRD). The Descriptor

Table must be dword-aligned. The Descriptor Table must not cross a 64-KB boundary in

memory.

1:0 Reserved

Bit Description

31:12 Reserved

SATA Controller Registers (D31:F2)

506 Intel® ICH8 Family Datasheet

11:8

Interface Power Management (IPM) — RO. Indicates the current interface state:

All other values reserved.

7:4

Current Interface Speed (SPD) — RO. Indicates the negotiated interface

communication speed.

All other values reserved.

ICH8 Supports Generation 1 communicatio n rates (1.5 Gb/sec) and G en 2 rates (3.0

Gb/s).

3:0

Device Detection (DET) — RO. Indicates the interface device detection and Phy

state:

All other values reserved.

Bit Description

Value Description

0h Device not present or communication not established

1h Interface in active state

2h Interface in PARTIAL power management state

6h Interface in SLUMBER power management state

Value Description

0h Device not present or communication not established

1h Generation 1 communication rate negotiated

2h Generation 2 communication rate negotiated

Value Description

0h No device detected and Phy comm unication not established

1h Device presence detected but Phy communication not esta blished

3h Device presence detect ed and Phy communication established

4h Phy in offline mode as a result of the interface being disabled or

running in a BI ST loopback mode

Intel® ICH8 Family Datasheet 507

SATA Controller Registers (D31:F2)

12.2.3.2 PxSCTL — Serial ATA Control Register (D31:F5)

Address Offset: BAR + 01h Attribute: R/W, RO

Default Value: 00000004h Size: 32 bits

This is a 32-bit read-write register by which softw are controls S ATA capabilities. Writes

to the SControl register result in an action being taken by the ICH8 or the interface.

R eads from the register return the last v alue written to it.

Bit Description

31:20 Reserved

19:16 Port Multiplier Port (PMP) — RO. This field is not used by AHCI

NOTE: Port Multiplier not supported by ICH8.

15:12 Select Power Management (SPM) — RO. This field is not used by AHCI

11:8

Interface Power Management Transitions Allowed (IPM) — R/W. Indicates which

power states the ICH8 is allowed to transition to:

All other values reserved

7:4

Speed Allowed (SPD) — R/W. Indicates the highest allowable speed of the interface.

This speed is limited by the CAP.ISS (ABAR+00h:bit 23:20) field.

All other values reserved.

ICH8 Supports Generation 1 communication rates (1.5 Gb/sec) and Gen 2 rates (3.0

Gb/s).

3:0

Device Detection Initialization (DET) — R/W. Controls the ICH8’s device detection

and interface initialization.

All other values reserved.

When this field is written to a 1h, the ICH8 initiat es COMRESET and starts t he

initialization process. When the initialization is complete, this field shall remain 1h until

set to another value by software.

This field may only be changed to 1h or 4h when PxCMD.ST is 0. Changing this field

while the ICH8 is running results in undefined behavior.

Value Description

0h No interface restrictions

1h Transitions to the PARTIAL state disabled

2h Transitions to the SLUMBER state disabled

3h Transitions to both PARTIAL and SLUMBER states disabled

Value Description

0h No speed negotiation restrictions

1h Limit speed negotiation to Generation 1 communication rate

2h Limit speed negotiation to Generation 2 communication rate

Value Description

0h No device detection or initializat ion action requested

Perform interface communication initialization sequence to

establish com munication . This is functionally equivalent to a hard

reset and results in the interface being reset and communications

re-initialized

4h Disable the Serial ATA interface and put Phy in offline mode

SATA Controller Registers (D31:F2)

508 Intel® ICH8 Family Datasheet

12.2.3.3 PxSERR—Serial ATA Error Register (D31:F5)

Address Offset: BAR + 02h Attribute: R/WC

Default Value: 00000000h Size: 32 bits

Bit Description

31:16

Diagnostics (DIAG) — R/WC. Contains diagnostic error information for use by

diagnostic software in validating correct operation or isolating failure modes:

Bits Description

31:27Reserved

26 Exchanged (X): When set to one this bit indicates a COMINIT signal was

received. This bit is reflected in the interrupt register PxIS.PCS.

25 Unrecognized FIS Type (F): Indicates that one or more FISs were received by

the Transport layer with good CRC, but had a type field that was not recognized.

24 Transport state transition error (T): Indicates that an error has occurred in the

transition from one state to another within the Transport layer since the last time

this bit was cleared.

23 Link Sequence Error (S): Indicates that one or more Link state machine error

conditions was encountered. The Link Layer state machine defines the conditions

under which the link layer detects an erroneous transition.

22 Handshake Error (H): Indicates that one or more R_ERR handshake respon se

was receiv ed in response to fr ame transmis sion. Such errors may be the result of a

CRC error detected by the recipient, a disparity or 8b/10b decoding error, or other

error condition leading to a negative handshake on a transmitted frame.

21 CRC Error (C): Indicates tha t one or more CRC errors occurred with the Link

Layer.

20 Disparity Error (D): This field is not used by AHCI.

19 10b to 8b Decode Error (B): Indicates that one or more 10b to 8b decoding

errors occurred.

18 Comm Wake (W): Indicates that a Comm Wake signal was detected by the Phy.

17 Phy Internal Error (I): Indicates that the Phy detected some internal error.

16 PhyRdy Change (N): When set to 1, this bit indicates that the internal PhyRdy

signal changed state since the last time this bit was cleared. In the ICH8, this bit

will be set when PhyRdy changes fro m a 0 -> 1 or a 1 -> 0. The state of this bit is

then reflected in the PxIS.PRCS interrupt status bit and an interrupt will be

generated if enabled. Software clears this bit by writing a 1 to it.

Intel® ICH8 Family Datasheet 509

SATA Controller Registers (D31:F2)

12.2.4 AIR—AHCI Index Register (D31:F2)

Address Offset: Primary: BAR + 10h Attribute: R/W, RO

Default Value: 00000000h Size: 32 bits

This register is available only when CC.SCC is not 01h.

15:0

Error (ERR) — R/WC. The ERR field contains error inform ation for use by host software

in determining the appropriate response to the error condition.

If one or more of bits 11:8 of this register are set, the controller will stop the current

transfer.

Bits Description

15:12Reserved

11 Internal Error (E): The SATA controller failed due to a master or target abort

when attempti ng to access system memory.

10 Protocol Error (P): A violation of the Serial ATA protocol was detected.

Note: The ICH8 does not set this bit for all protocol violations that may occur on

the SATA link.

9 Persistent Communication or Data Integrity Error (C): A communication

error that was not recovered occurred that is expected to be persistent. Persistent

communications errors may arise from faulty interconnect with the device, from a

device that has been removed or has failed, or a number of other causes.

8 Transient Data Integrity Error (T): A data integrit y error occurred that w as not

recovered by the interface.

7:2 Reserved

1Recovered Communications Error (M): Communications between the device

and host wa s te mporarily lost but was re-e st abli she d . This c an arise from a devi ce

temporarily being remove d, from a tempor ary loss of Phy synchronizat ion, or from

other causes and may be derived from the PhyNRdy signal between the Phy and

Link layers.

0Recovered Data Integrity Error (I): A data integrity error occurred that was

recovered by the interface through a retry operation or other recovery action.

Bit Description

31:11 Reserved

10:2 Index (INDEX)— R/W. This Index register is used to select the DWord offset of the

Memory Mapped AHCI register to be accessed. A Dword, Word or Byte access is

specified by the active byte en ables of the I/O access to the Data register.

1:0 Reserved

SATA Controller Registers (D31:F2)

510 Intel® ICH8 Family Datasheet

12.2.5 AIDR—AHCI Index Data Register (D31:F2)

Address Offset: Primary: BAR + 14h Attribute: R/W

Default Value: All bits undefined Size: 32 bits

This register is available only when CC.SCC is not 01h.

12.3 Serial ATA Index/Data Pair Superset Registers

All of these I/O registers are in the core well. They are exposed only when CC.SCC is

01h

(i.e., IDE programming interface) and the controller is not in combined mode. These

are Index/Data Pair registers that are used to access the SerialATA superset registers

(SerialATA Status, SerialATA Control and SerialATA Error). The I/O space for these

registers is allocated through SIDPBA. Locations with offset from 08h to 0Fh are

reserved for future expansion. Software- write operations to the reserved locations shall

have no effect while software-read operations to the reserved locations shall return 0.

12.3.1 SINDX—SATA Index Register (D31:F5)

Address Offset: SIDPBA + 00h Attribute: R/W

Default Value: 00000000h Size: 32 bits

Note: These are Index/Data Pair Registers that are used to access the SSTS, SCTL, and

SERR. The I/O space for these registers is allocated through SIDPBA.

Bit Description

31:0

Data (DATA)— R/W. This Data register is a “window” through which data is read or

written to the AHCI memory mapped registers. A read or write to this Data register

triggers a corresponding read or write to the memory mapped register pointed to by

the Index register. The Index register must be setup prior to the read or write to this

Data register.

Note that a physical regist er is not actually implemented as the data is ac tually stored

in the memory mapped registers.

Since this is not a ph ysical regi ster, the “default” value i s the same as the de fault v alu e

of the register pointed to by Index.

Bit Description

31:16 Reserved

15:8

Port Index (PIDX)— R/W. This Index field is used to specify the port of the SATA

controller at which the port-specific SSTS, SCTL, and SERR registers are located.

00h = Primary Master (Port 0)

01h = Primary Slave (Port 2)

02h = Secondary Master (Port 1)

03h = Secondary SLave (Port 3)

All other values are Reserved.

7:0

registers currently being indexed into.

00h = SSTS

01h = SCTL

02h = SERR

All other values are Reserved

Intel® ICH8 Family Datasheet 511

SATA Controller Registers (D31:F2)

12.3.2 SDATA—SATA Index Data Register (D31:F5)

Address Offset: SIDPBA + 04h Attribute: R/W

Default Value: All bits undefined Size: 32 bits

Note: These are Index/Data Pair Registers that are used to access the SSTS, SCTL, and

SERR. The I/O space for these registers is allocated through SIDPBA.

Bit Description

31:0

Data (DATA)— R/W. This Data register is a “window” through which data is read or

written to the memory mapped registers. A read or write to this Data register triggers a

corresponding read or write to the memory mapped register pointed to by the Index

Note that a physical register is not actually implemented as the data is actually stored

in the memory mapped registers.

Since this is not a physical register, the “default” value is the same as the default value

of the register po inte d to by Index.

SATA Controller Registers (D31:F2)

512 Intel® ICH8 Family Datasheet

12.4 AHCI Registers (D31:F2) (Intel® ICH8R, ICH8DH,

ICH8DO, and ICH8M-E Only)

Note: These registers are AHCI-specific and available when the ICH8 is properly configured.

The Serial ATA Status, Control, and Error registers are special exceptions and may be

accessed on all ICH8 components if properly configured. See Section 12.1.31 for

details.

The memory mapped registers within the SATA controller exist in non-cacheable

memory space. Additionally, locked accesses are not supported. If software attempts to

perform locked transactions to the registers, indeterminate results may occur. Register

accesses shall have a maximum size of 64-bits; 64-bit access must not cross an 8-byte

alignment boundary.

The registers are broken into two sections – generic host control and port control. The

port control registers are the same for all ports, and there are as many registers banks

as there are ports.

Table 124. AHCI Register Address Map

ABAR +

Offset Mnemonic Register

00–1Fh GHC Generic Host Control

20h–FFh — Reserved

100h–17Fh P0PCR Port 0 port control registers

180h–1FFh P1PCR Port 1 port control registers

200h–27Fh P2PCR Port 2 port control registers

280h–2FFh P3PCR Port 3 port control registers (Desktop Only)

Registers are not available and software must not read or write

registers. (Mobile Onl y)

300h–37Fh P4PCR Port 4 port control registers (Desktop Only)

Registers are not available and software must not read or write

registers. (Mobile Onl y)

380h–3FFh P5PCR Port 5 port control registers (Desktop Only)

Registers are not available and software must not read or write

registers. (Mobile Onl y)

Intel® ICH8 Family Datasheet 513

SATA Controller Registers (D31:F2)

12.4.1 AHCI Generic Host Control Registers (D31:F2)

12.4.1.1 CAP—Host Capabilities Register (D31:F2)

Address Offset: ABAR + 00h–03h Attribute: R/WO, RO

Default Value: FF22FFC2h (Desktop) Size: 32 bits

DE127F03h (Mobile)

All bits in this register that are R/WO are reset only by PLTRST#.

Table 125. Generic Host Controller Register Address Map

ABAR +

Offset Mnemonic Register Default Type

00–03 CAP Host Capabilities

DE227F03h

(desktop)

DE127F03h

(mobile)

R/WO, RO

04–07 GHC Global ICH8 Control 00000000h R/W

08–0Bh IS Interrupt Status 00000000h R/WC, RO

0Ch–0Fh PI Ports Implemented 00000000h R/WO, RO

10h-13h VS AHCI Version 00010100h RO

Bit Description

31 Supports 64-bit Addressing (S64A) — RO. Indicates that the SA T A controller can

access 64-bit data structures. The 32-bit upper bits of the port DMA Descriptor, the

PRD Base, and each PRD entry are read/write.

Supports Command Queue Accel eration (SCQA) — RO. Hardwired to 1 to

indicate that the SATA controller supports SATA command queuing via the DMA

Setup FIS. The Intel® ICH8 handles DMA Setup FISes natively, and c a n handle

auto-activate optimization through that FIS.

29 Supports SNotification Register (SSNTF): — RO. The ICH8 SATA Controller does not

support the SNotification register.

Supports Interlock Switch (SI S) — R/WO. Indicates whether the SA TA controller

supports interlock switches on its ports for use in Hot-Plug operations. This value is

loaded by platform BIOS prior to OS initialization.

If this bit is set, BIOS must also map the SAT AGP pin s to the SAT A cont roller through

GPIO space.

Supports Staggered Spin-up (SSS) — R/WO. Indicates whether the SATA

controller supports staggered spin-up on its ports, for use in balancing power spikes.

This value is loaded by platform BIOS prior to OS initialization.

0 = Staggered spin-up not su pported.

1 = Staggered spin-up supported.

Supports Aggressive Link Power Management (SALP) — R/WO.

0 = Software shall treat the PxCMD.ALPE and PxCMD.ASP bits as reserved.

1 = The SATA controller supports auto-generating link requests to the partial or

slumber states when there are no commands to process.

25 Supports Activity LED (SAL) — RO. Indicates that the SATA controller supports a

single output pin (SATALED#) which indicates activity.

SATA Controller Registers (D31:F2)

514 Intel® ICH8 Family Datasheet

Supports Command List Override (SCLO) — R/WO. When set to '1', indicates

that the HBA supports the PxCMD.CLO bit and it's associated function. When cleared

to '0', The HBA is not capable of cl earing the BSY and DRQ bits in the Status register

in order to issue a software reset if these bits are still set from a previous operation.

23:20 Interface Speed Support (ISS) — R/WO. Indicates the maximum speed the SA T A

controller can support on its ports.

2h =3.0 Gb/s.

19 Supports Non-Zero DMA Offsets (SNZO) — RO. Reserved, as per the AHCI Revision

1.0 specification

Supports AHCI Mode Only (SAM) — RO. The SATA controller may optionally

support AHCI access me chanism only.

0 = SATA controller supports both IDE and AHCI Modes

1 = SATA controller supports AHCI Mode Only

17 Supports Port Multiplier (PMS) — R/WO. ICH8 does not support port multiplier.

BIOS/SW shall write this bit to ‘0’ during AHCI initializat ion.

16 Supports Port Multiplier FIS Based Switching (PMFS) — RO. Reserved, as per the

AHCI Revision 1.0 specification.

NOTE: Port Multiplier not supported by ICH8.

15 PIO Multip le DRQ Block (PMD) — R/WO. The SATA controller supports PIO

Multiple DRQ Com mand Block

14 Slumber State Capable (SSC) — RO. The SATA controller supports the slumber

state.

13 Partial State Capable (PSC) — RO. The SATA controller supports the partial state.

12:8 Number of Command Slots (NCS) — RO. Hardwi red to 1Fh to indicate support for 32

slots.

7Command Completion Coalescing Supported (CCCS) — R/WO.

0 = Command Completion Coalescing Not Supported

1 = Command Completion Coalescing Supported

6Enclosure Management Supported (EMS) — R/WO.

0 = Enclosure Management Not Supported

1 = Enclosure Management Supported

(ICH8R,

ICH8DO,

ICH8DH

Only)

Supports External SATA (SXS) — R/WO.

0 = External SATA is not supported on any ports

1 = External SATA is supported on one or more ports

When set, software can examine each SATA port’s Command Register (PxCMD) to

determine which port is routed externally.

5 Reserved

(ICH8

Base and

ICH8

Mobile

Only)

Reserved

4:0 Number of Ports (NPS) — RO. Hardwired to 5h to indicate support for 6 ports. Note

that the number of ports indicated in this field may be more than the number of

ports indicated in the PI (ABAR + 0Ch) register.

Bit Description

Intel® ICH8 Family Datasheet 515

SATA Controller Registers (D31:F2)

12.4.1.2 GHC—Global ICH8 Control Register (D31:F2)

Address Offset: ABAR + 04h–07h Attribute: R/W

Default Value: 00000000h Size: 32 bits

Bit Description

AHCI Enable (AE) — R/W. When set, indicates that an AHCI driver is loaded and the

controller will be talked to via AHCI mechanisms. This can be used by an ICH8 that

supports both legacy mechanisms (such as SFF-8038i) and AHCI to know when the

controller will not be talked to as legacy.

0 = Software will only talk to the ICH8 using legacy mechanisms.

1 = Software will only talk to the ICH8 using AHCI. The ICH8 will no t have to allow

command processing via both AHCI and legacy mechanisms.

Software shall set this bit to 1 before accessing other AHCI registers.

30:3 Reserved

MSI Revert to Single Message (MRSM) — RO: When set to 1 by hardware, indicates

that the host controller requested more than one MSI vector but has reverted to using

the first vector on ly. When this bit is c leared to '0', the HBA has not reverted to single

MSI mode (i.e. hardware is already in single MSI mode, software has allocated the

number of messages requested, or hardware is sharing interrupt vectors if MC.MME <

MC.MMC).

"MC.MSIE = '1' (MSI is enabled)

"MC.MMC > 0 (multiple messages requested)

"MC.MME > 0 (more than one message allocated)

"MC.MME != MC.MMC (messages allocated not equal to number requested)

When this bit is set to '1', single MSI mode operation is in use and software is

responsible for clearing bits in the IS register to clear interrupts.

This bit shall be cleared to '0' by hardware when any of the four conditions stated is

false. This bit is also cleared to '0' when MC.MSIE = '1' and MC.MME = 0h. In this case,

the hardware has be en programmed to use single MSI mode, and is not "reverting" to

that mode.

For ICH8, the HBA shall always revert to single MSI mode when the number of vectors

allocated by the host is less than the number requested.

1Interrupt Enable (IE) — R/W. This global bit enables interrupts from the ICH8.

0 = All interrupt sources from all ports are disabled.

1 = Interrupts are allowed from the AHCI controller.

HBA Reset (HR) — R/W. Resets ICH8 AHCI controller.

0 = No effect

1 = When set by SW, this bit causes an internal reset of the ICH8 AHCI controller. All

state machines th at relate to data transfers and queuing return to an idle condition,

and all ports are re-initialized via COMRESET.

NOTE: For further details, consult section 12.3.3 of the Serial ATA Advanced Host

Controller Interface specification.

SATA Controller Registers (D31:F2)

516 Intel® ICH8 Family Datasheet

12.4.1.3 IS—Interrupt Status Register (D31:F2)

Address Offset: ABAR + 08h–0Bh Attrib ute: R/WC, RO

Default Value: 00000000h Size: 32 bits

This register indicates which of the ports within the controller have an interrupt pending

and require service.

Bit Description

31:7 Reserved. Returns 0.

(Mobile

Only) Reserved. Ret urns 0.

(Desktop

Only)

Interrupt Pending Status Port[6] (IPS[6]) — R/WC.

0 = No interrupt pending.

1 = A command completion coalescing interrupt has been generated.

(Mobile

Only) Reserved. Ret urns 0.

(Desktop

Only)

Interrupt Pending Status Port[5] (IPS[5]) — R/WC.

0 = No interrupt pending.

1 = Port 5 has an interrupt pending. Software can use this information to determine

which ports require service after an interrupt.

(Mobile

Only) Reserved. Ret urns 0.

(Desktop

Only)

Interrupt Pending Status Port[4] (IPS[4]) — R/WC.

0 = No interrupt pending.

1 = Port 4 has an interrupt pending. Software can use this information to determine

which ports require service after an interrupt.

(Mobile

Only) Reserved. Ret urns 0.

(Desktop

Only)

Interrupt Pending Status Port[3] (IPS[3]) — R/WC.

0 = No interrupt pending.

1 = Port 3 has an interrupt pending. Software can use this information to determine

which ports require service after an interrupt.

Interrupt Pending Status Port[2] (IPS[2]) — R/WC

0 = No interrupt pending.

1 = Port 2 has an interrupt pending. Software can use this information to determine

which ports require service after an interrupt.

Interrupt Pending Status Port[1] (IPS[1]) — R/WC.

0 = No interrupt pending.

1 = Port 1has an interrupt pending. Software can use this information to determine

which ports require service after an interrupt.

Interrupt Pending Status Port[0] (IPS[0]) — R/WC.

0 = No interrupt pending.

1 = Port 0 has an interrupt pending. Software can use this information to determine

which ports require service after an interrupt.

Intel® ICH8 Family Datasheet 517

SATA Controller Registers (D31:F2)

12.4.1.4 PI—Ports Implemented Register (D31:F2)

Address Offset: ABAR + 0Ch–0Fh Attribute: R/WO, RO

Default Value: 00000000h Size: 32 bits

This register indicates which ports are exposed to the ICH8. It is loaded by platform

BIOS. It indicates which ports that the device supports are available for software to

use. F or ports that are not av ailable, software must not read o r write to registers within

that port.

Bit Description

31:6 Reserved. Returns 0.

(Desktop

Only)

Ports Implemented Port 5 (PI5) — R/WO.

0 = The port is not implemented.

1 = The port is implemented.

(Mobile

Only)

Ports Implemented Port 5 (PI5) — RO.

0 = The port is not implemented.

(Desktop

Only)

Ports Implemented Port 4 (PI4) — R/WO.

0 = The port is not implemented.

1 = The port is implemented.

(Mobile

Only)

Ports Implemented Port 4 (PI4) — RO.

0 = The port is not implemented.

(Desktop

Only)

Ports Implemented Port 3 (PI3) — R/WO.

0 = The port is not implemented.

1 = The port is implemented.

(Mobile

Only)

Ports Implemented Port 3 (PI3) — RO.

0 = The port is not implemented.

2Ports Implemented Port 2 (PI2)— R/WO.

0 = The port is not implemented.

1 = The port is implemented.

1 Ports Implemented Port 1 (PI1) — R/WO.

0 = The port is not implemented.

1 = The port is implemented.

0Ports Implemented Port 0 (PI0) — R/WO.

0 = The port is not implemented.

1 = The port is implemented.

SATA Controller Registers (D31:F2)

518 Intel® ICH8 Family Datasheet

12.4.1.5 VS—AHCI Version (D31:F2)

Address Offset: ABAR + 10h–13h Attribute: RO

Default Value: 00010100h Size: 32 bits

This register indicates the major and minor version of the AHCI specification. It is BCD

encoded. The upper two bytes represent the major version number, and the lower two

bytes represent the minor version number. Example: Version 3.12 would be

represented as 00030102h. The current version of the specification is 1.10

(00010100h).

12.4.1.6 CCC_CTL—Command Completion Coalescing Control Register (D31:F2)

Address Offset: ABAR + 14h–17h Attribute: R/W, RO

Default Value: 00000000h Size: 32 bits

This register is used to configure the command coalescing feature. This register is

reserved if command coalescing is not supported (CAP_CCCS = ‘0’).

Bit Description

31:16 Major Version Number (MJR) — RO. Indicates the major version is 1

15:0 Minor Version Number (MNR) — RO. Indicates the minor version is 10.

Bit Description

31:16

Timeout Value (TV) — R/W. The timeout value is specified in 10 microsecond

intervals. hbaCCC_Timer is loaded with this timeout value. hbaCCC_Timer is only

decremented when commands are outstanding on the selected ports. The HBA will

signal a CCC interrupt when hbaCCC_Timer has decremented to ‘0’. The

hbaCCC_Timer is reset to the timeout v alue on the assertion of each CCC interrupt. A

timeout value of’0’ is invalid.

15:8

Command Completions (CC) — R/W. Specifies the number of command

completions that are necessary to cause a CCC interrupt. The HBA has an internal

command completion counter, hbaCCC_CommandsComplete.

hbaCCC_CommandsComplete is incremented by one each time a selected port has a

command completion. When hbaCCC_CommandsComplete is equal to the command

completions value, a CCC interrupt is signaled. The internal command completion

counter is reset to ‘0’ on the assertion of each CCC interrupt.

7:3

Interrupt (INT) — RO. Specifies the interrupt used by the CCC feature. This

interrupt must be marked as unused in the AHCI Ports Implemented memory register

by the corresponding bit being set to ‘0’. Thus, the CCC_interrupt corresponds to the

interrupt for an unimplemented port on the controller. When a CCC interrupt occurs,

the IS[INT] bit shall be asserted to ‘1’ regardless of whether PIRQ interrupt or MSI is

used.

For desktop INT is always 6.

Note that in MSI, CC interrupt may share an interrupt vector with other ports. For

example, if the number of message allocated is 4, then CCC interrupt share interrupt

vector 3 along with port 3, 4, and 5 but IS[6] shall get set.

2:1 Reserved

Enable (EN) — R/W.

0 = The command completion coalescing feature is disabled and no CCC interrupts are

generated

1 = The command completion coalescing feature is enabled and CCC interrupts may

be generated based on timeout or command completion conditions.

Software shall only change the contents of the TV and CC fields when EN is cleared to '0'. On

transition of this bit from '0' to '1', any updated values for the TV and CC fields shall take effect.

Intel® ICH8 Family Datasheet 519

SATA Controller Registers (D31:F2)

12.4.1.7 CCC_Ports—Command Completion Coalescing Ports Register (D31:F2)

Address Offset: ABAR + 18h–1Ch Attribute: R/W

Default Value: 00000000h Size: 32 bits

This register is used to specify the ports that are coalesced as part of the CCC feature

when CCC_CTL.EN = ‘1’. This register is reserved if command coalescing is not

supported (CAP_CCCS = ‘0’).

12.4.1.8 EM_LOC—Enclosure Management Location Register (D31:F2)

Address Offset: ABAR + 1Ch–1Fh Attribute: RO

Default Value: 01000002h Size: 32 bits

This register identifies the location and size of the enclosure management message

buffer. This register is reserved if enclosure management is not supported (i.e.

CAP.EMS = 0).

Bit Description

31:0

Ports (PRT) — R/W.

0 = The port is not part of the command comple ti on coalescing feature.

1 = The corresponding port is part of the command completi on coalescing feature.

Bits set to ‘1’ i n this regi ster must al so hav e the co rresponding bi t set to ‘1 ’ in the

Ports Implemented register.

Bits set to 1 in this register must also have the corresponding bit se t to 1 in the P orts Implemented

Bit Description

31:16 Offset (OFST) — RO. The offset of the message buffer in DW ords from the beginning

of the ABAR.

15:0 Buffer Size (SZ) — RO. Specifies the si ze of the transmit message buffer area in

DWords. The ICH8 SATA controller only supports transmit buffer.

A value of 0 is invalid.

SATA Controller Registers (D31:F2)

520 Intel® ICH8 Family Datasheet

12.4.1.9 EM_CTL—Enclosure Management Control Register (D31:F2)

Address Offset: ABAR + 20h–23h Attribute: R/W, R/WO, RO

Default Value: 07010000h Size: 32 bits

This register is used to control and obtain status for the enclosure management

interface. This register includes information on the attributes of the implementation,

enclosure management messages supported, the status of the interface, whether any

message are pending, and is used to initiate sending messages. This register is

reserved if enclosure management is not supported (CAP_EMS = ‘0’).

Bit Description

31:27 Reserved

Activity LED Hardware Driven (ATTR.ALHD) — R/WO.

1 = The SAT A co ntroller drive s the activit y LED for the LED message type in hardw are

and does not utilize software for this LED.

The host controller does not begin transmitting the hardware based activity signal until after

software has written CTL.TM=1 after a reset condition.

Transmit Only (ATTR.XMT) — RO.

0 = The SATA controller supports transmitting and receiving messages.

1 = The SATA controller only supports transmitting messages and does not support

receiving messages.

Single Message Buffer (ATTR.SMB) — RO.

0 = There are separate receive and transmit buffers such that unsolicited messages

could be supported.

1 = The SATA controller has one message buffer that is shared for messages to

transmit and messages received. Unsolicite d rece ive mess ages are not supported

and it is software’s responsibility to manage access to this buffer.

23:20 Reserved

19 SGPIO Enclosure Management Messages (SUPP.SGPIO): — RO.

1 = The SATA controller supports the SGPIO register interface message type.

18 SES-2 Enclosure Management Messages (SUPP.SES2): — RO.

1 = The SATA controller supports the SES-2 message type.

17 SAF-TE Enclosure Management Messages (SUPP.SAFTE): — RO.

1 = The SATA controller supports the SAF-TE message type.

16 LED Message Types (SUPP.LED): — RO.

1 = The SATA controller supports the LED message type.

15:10 Reserved

Reset (RST) — R/W O.

0 = A write of ‘0’ to this bit by software will have no effect.

1 = When set by software, The SATA controller shall reset all enclosure management

message logic and take all appropriate reset actions to ensure messages can be

transmitted / received after the reset. After the SATA controller completes the

reset operation, the SATA controller shall set the value to ‘0’.

Transmit Message (CTL.TM) — R/WO.

0 = A write of ‘0’ to this bit by software will have no effect.

1 = When set by software, The SATA controller shall transmit the message contain ed

in the message buffer. When the message is completely sent, the SATA controller

shall set the value to 0.

Software shall not change the contents of the message buffer while CTL.TM is set to 1.

7:1 Reserved

0Message Received (STS.MR) — RO. Message Received is not supported in ICH8 .

Intel® ICH8 Family Datasheet 521

SATA Controller Registers (D31:F2)

12.4.2 Port Registers (D31:F2)

Table 126. Port [3:0] DMA Register Address Map (Sheet 1 of 3)

ABAR +

Offset Mnemonic Register

100h–103h P0CLB Port 0 Command List Base Address

104h–107h P0CLBU Port 0 Command List Base Address Upper 32-Bit s

108h–10Bh P0FB Port 0 FIS Base Address

10Ch–10Fh P0FBU Port 0 FIS Base Address Upper 32-Bits

110h–113h P0IS Port 0 Interrupt Status

114h–117h P0IE Port 0 Interrupt Enable

118h–11Bh P0CMD Port 0 Command

11Ch–11Fh — Reserved

120h–123h P0TFD Port 0 Task File Data

124h–127h P0SIG Port 0 Signature

128h–12Bh P0SSTS Port 0 Serial ATA Status

12Ch–12Fh P0SCTL Port 0 Serial ATA Control

130h–133h P0SERR Port 0 Serial ATA Error

134h–137h P0SACT Port 0 Serial ATA Active

138h–13Bh P0CI Port 0 Command Issue

13Ch–17Fh — Reserved

180h–1FFh

(Mobile

Only) —Reserved

Registers are not available and software must

not read from or write to registers.

180h–183h P1CLB Port 1 Command List Base Address

184h–187h P1CLBU Port 1 Command List Base Address Upper 32-Bit s

188h–18Bh P1FB Port 1 FIS Base Address

18Ch–18Fh P1FBU Port 1 FIS Base Address Upper 32-Bits

190h–193h P1IS Port 1 Interrupt Status

194h–197h P1IE Port 1 Interrupt Enable

198h–19Bh P1CMD Port 1 Command

19Ch–19Fh — Reserved

1A0h–1A3h P1TFD Port 1 Task File Data

1A4h–1A7h P1SIG Port 1 Signature

1A8h–1ABh P1SSTS Port 1 Serial ATA Status

1ACh–1AFh P1SCTL Port 1 Serial ATA Control

1B0h–1B3h P1SERR Port 1 Serial ATA Error

1B4h–1B7h P1SACT Port 1 Serial ATA Active

1B8h–1BBh P1CI Port 1 Command Issue

1BCh–1FFh — Reserved

200h–203h P2CLB Port 2 Command List Base Address

204h–207h P2CLBU Port 2 Command List Base Address Upper 32-Bit s

208h–20Bh P2FB Port 2 FIS Base Address

SATA Controller Registers (D31:F2)

522 Intel® ICH8 Family Datasheet

20Ch–20Fh P2FBU Port 2 FIS Base Address Upper 32-Bits

210h–213h P2IS Port 2 Interrupt Status

214h–217h P2IE Port 2 Interrupt Enable

218h–21Bh P2CMD Port 2 Command

21Ch–21Fh — Reserved

220h–223h P2TFD Port 2 Task File Data

224h–227h P2SIG Port 2 Signature

228h–22Bh P2SSTS Port 2 Serial ATA Status

22Ch–22Fh P2SCTL Port 2 Serial ATA Control

230h–233h P2SERR Port 2 Serial ATA Error

234h–237h P2SACT Port 2 Serial ATA Active

238h–23Bh P2CI Port 2 Command Issue

23Ch–27Fh — Reserved

280h–2FFh

(Mobile

Only) —Reserved

Registers are not available and software must

not read from or write to registers.

280h–283h P3CLB Port 3 Command List Base Address

284h–287h P3CLBU Port 3 Command List Bas e Address Upper 32- Bits

288h–28Bh P3FB Port 3 FIS Base Address

28Ch–28Fh P3FBU Port 3 FIS Base Address Upper 32-Bits

290h–293h P3IS Port 3 Interrupt Status

294h–297h P3IE Port 3 Interrupt Enable

298h–29Bh P3CMD Port 3 Command

29Ch–29Fh — Reserved

2A0h–2A3h P3TFD Port 3 Task File Data

2A4h–2A7h P3SIG Port 3 Signature

2A8h–2ABh P3SSTS Port 3 Serial ATA Status

2ACh–2AFh P3SCTL Port 3 Serial ATA Control

2B0h–2B3h P3SERR Port 3 Serial ATA Error

2B4h–2B7h P3SACT Port 3 Serial ATA Active

2B8h–2BBh P3CI Port 3 Command Issue

2BCh–2FFh — Reserved

300h–303h P2CLB Port 2 Command List Base Address

304h–307h P2CLBU Port 2 Command List Bas e Address Upper 32- Bits

308h–30Bh P2FB Port 2 FIS Base Address

30Ch–30Fh P4FBU Port 4 FIS Base Address Upper 32-Bits

310h–313h P4IS Port 4 Interrupt Status

314h–317h P4IE Port 4 Interrupt Enable

318h–31Bh P4CMD Port 4 Command

31Ch–31Fh — Reserved

Table 126. Port [3:0] DMA Register Address Map (Sheet 2 of 3)

ABAR +

Offset Mnemonic Register

Intel® ICH8 Family Datasheet 523

SATA Controller Registers (D31:F2)

320h–323h P4TFD Port 4 Task File Data

324h–327h P4SIG Port 4 Signature

328h–32Bh P4SSTS Port 4 Serial ATA Status

32Ch–32Fh P4SCTL Port 4 Serial ATA Control

330h–333h P4SERR Port 4 Serial ATA Error

334h–337h P4SACT Port 4 Serial ATA Active

338h–33Bh P4CI Port 4 Command Issue

33Ch–37Fh — Reserved

380h–3FFh

(Mobile

Only) —Reserved

Registers are not available and software must

not read from or write to registers.

380h–383h P5CLB Port 5 Command List Base Address

384h–387h P5CLBU Port 5 Command List Base Address Upper 32-Bit s

388h–38Bh P5FB Port 5 FIS Base Address

38Ch–38Fh P5FBU Port 5 FIS Base Address Upper 32-Bits

390h–393h P5IS Port 5 Interrupt Status

394h–397h P5IE Port 5 Interrupt Enable

398h–39Bh P5CMD Port 5 Command

39Ch–39Fh — Reserved

3A0h–3A3h P5TFD Port 5 Task File Data

3A4h–3A7h P5SIG Port 5 Signature

3A8h–3ABh P5SSTS Port 5 Serial ATA Status

3ACh–3AFh P5SCTL Port 5 Serial ATA Control

3B0h–3B3h P5SERR Port 5 Serial ATA Error

3B4h–3B7h P5SACT Port 5 Serial ATA Active

3B8h–3BBh P5CI Port 5 Command Issue

3BCh–3FFh — Reserved

Table 126. Port [3:0] DMA Register Address Map (Sheet 3 of 3)

ABAR +

Offset Mnemonic Register

SATA Controller Registers (D31:F2)

524 Intel® ICH8 Family Datasheet

12.4.2.1 PxCLB—Port [5:0] Command List Base Address Register

(D31:F2)

Address Offset: Port 0: ABAR + 100h Attribute: R/W, RO

Port 1: ABAR + 180h

Port 2: ABAR + 200h

Port 3: ABAR + 280h (Desktop Only)

Port 4: ABAR + 300h (Desktop Only)

Port 5: ABAR + 380h (Desktop Only)

Default Value: Undefined Size: 32 bits

12.4.2.2 PxCLBU—Port [5:0] Command List Base Address Upper

32-Bits Register (D31:F2)

Address Offset: Port 0: ABAR + 104h Attribute: R/W

Port 1: ABAR + 184h

Port 2: ABAR + 204h

Port 3: ABAR + 284h (Desktop Only)

Port 4: ABAR + 304h (Desktop Only)

Port 5: ABAR + 384h (Desktop Only)

Default Value: Undefined Size: 32 bits

Bit Description

31:10

Command List Base Address (CLB) — R/W. Indicates the 32-bit base for the

command list for this port. This base is used when fetching commands to execute. The

structure pointed to by this address range is 1 KB in length. This address must be 1-KB

aligned as indicated by bits 31:10 being read/write.

Note that these bits are not reset on a HBA reset.

9:0 Reserved — RO

Bit Description

31:0

Command List Base Address Upper (CLBU) — R/W. Indicates the upper 3 2-bits for

the command list base address for this port. This base is used when fetching

commands to execute.

Note that these bits are not reset on a HBA reset.

Intel® ICH8 Family Datasheet 525

SATA Controller Registers (D31:F2)

12.4.2.3 PxFB—Port [5:0] FIS Base Address Register (D31:F2)

Address Offset: Port 0: ABAR + 108h Attribute: R/W, RO

Port 1: ABAR + 188h

Port 2: ABAR + 208h

Port 3: ABAR + 284h (Desktop Only)

Port 4: ABAR + 304h (Desktop Only)

Port 5: ABAR + 384h (Desktop Only)

Default Value: Undefined Size: 32 bits

12.4.2.4 PxFBU—Port [5:0] FIS Base Address Upper 32 -Bits

Address Offset: Port 0: ABAR + 10Ch Attribute: R/W

Port 1: ABAR + 18Ch

Port 2: ABAR + 20Ch

Port 3: ABAR + 28Ch

Port 4: ABAR + 30Ch

Port 5: ABAR + 38Ch

Default Value: Undefined Size: 32 bits

Bit Description

31:8

FIS Base Address (FB) — R/W. Indicates the 32-bit base for received FISes. The

structure pointed to by this address range is 25 6 bytes in length. This address must be

256-byte aligned, as indicated by bits 31:3 being read/write.

Note that these bits are not reset on a HBA reset.

7:0 Reserved — RO

Bit Description

31:3 Command List Base Address Upper (CLBU) — R/W. Indicates the upper 32-bits for

the received FIS base for this port.

Note that these bits are not reset on a HBA reset.

2:0 Reserved

SATA Controller Registers (D31:F2)

526 Intel® ICH8 Family Datasheet

12.4.2.5 PxIS—Port [5:0] Interrupt Status Register (D31:F2)

Address Offset: Port 0: ABAR + 110h Attribute: R/WC, RO

Port 1: ABAR + 190h

Port 2: ABAR + 210h

Port 3: ABAR + 290h (Desktop Only)

Port 4: ABAR + 310h (Desktop Only)

Port 5: ABAR + 390h (Desktop Only)

Default Value: 00000000h Size: 32 bits

Bit Description

31 Cold Port Detect Status (CPDS) — RO. Cold presence detect is not supported.

30 Task File Error Status (TFES) — R/WC. This bit is s et whenev er the statu s register i s

updated by the device and the error bit (PxTFD.bit 0) is set.

29 Host Bus Fatal Error Status (HBFS) — R/WC. Indicates that the Intel® ICH8

encountered an error that it cannot recover from due to a bad software pointer. In PCI,

such an indication would be a target or master abort.

28 Host Bus Data Error Status (HBDS) — R/WC. Indicat es that the ICH8 encou ntered a

data error (uncorrectable ECC / parity) when reading from or writing to system

memory.

27 Interface Fatal Error Status (IFS) — R/WC. Indicates that the ICH8 encountered an

error on the SATA interface which caused the transfer to stop.

26 Interface Non-fatal Error Status (INFS) — R/WC. Indica tes that the ICH8

encountered an error on the SATA interface but was able to continue operation.

25 Reserved

24 Overflow Status (OFS) — R/WC. Indicates that the ICH8 received more bytes from a

device than was specified in the PRD table for the comma nd.

23 Incorrect Port Multiplier Status (IPMS) — R/WC. Indicates that the ICH8 received

a FIS from a device whose Port Multiplier field did not match what was expected.

NOTE: Port Multiplier not supported by ICH8.

PhyRdy Change Status (PRCS) — RO. When se t to one indicates the int ernal PhyRdy

signal changed state. This bit reflects the state of PxSERR.DIAG.N. Unlike most of the

other bits in the register, this bit is RO and is only cleared when PxSERR.DIAG.N is

cleared.

Note that the internal PhyRdy signal also transitions when the port interface enters

partial or slumber power management states. Partial and slumber must be disabled

when Surprise R emoval Notification is desired, otherwise the power manage ment s tat e

transitions will appear as false insertion and removal events.

21:8 Reserved

Device Interlock Status (DIS) — R/WC. When set, indicates that a platform interlock

switch has been opene d or closed, which may lead to a change in t he connection state

of the device. This bit is only valid in systems that support an interlock switch (CAP.SIS

[ABAR+00:bit 28] set).

For systems that do not support an interlock switch, this bit will always be 0.

Port Connect Change Status (PCS) — RO. This bit reflects the state of

PxSERR.DIAG.X. (ABAR+130h/1D0h/230h/2D0h, bit 26) Unlike other bits in this

0 = No change in Current Connect Status.

1 = Change in Current Connect Status.

5Descriptor Processed (DPS) — R/WC. A PRD with the I bit set has t ransferred al l i ts

data.

Intel® ICH8 Family Datasheet 527

SATA Controller Registers (D31:F2)

12.4.2.6 PxIE—Port [5:0] Interrupt Enable Register (D31:F2)

Address Offset: Port 0: ABAR + 114h Attribute: R/W, RO

Port 1: ABAR + 194h

Port 2: ABAR + 214h

Port 3: ABAR + 294h (Desktop Only)

Port 4: ABAR + 314h (Desktop Only)

Port 5: ABAR + 394h (Desktop Only)

Default Value: 00000000h Size: 32 bits

This register enables and disables the reporting of the corresponding interrupt to

system software. When a bit is set (‘1’) and the corresponding interrupt condition is

active, then an interrupt is generated. Interrupt sources that are disabled (‘0’) are still

reflected in the status registers.

Unknown FIS Interrupt (UFS) — RO. When set to ‘1’ indicates that an unknown FIS

was received and has been copied into system memory. This bit is cleared to ‘0’ by

software clearing the PxSERR.DIAG.F bit to ‘0’. Note that this bit does not directly

reflect the PxSERR.DIAG.F bit. PxSERR.DIA G.F is set immediately when an unknown

FIS is detected, whereas this bit is set when the FIS is posted to memory. Software

should wait to act on an unknown FIS until this bit is set to ‘1’ or the two bits may

become out of sync.

3Set Device Bits Interrupt (SDBS) — R/WC. A Set Device Bits FIS has been received

with the I bit set and has been copied into system memory.

2DMA Setup FIS I n terrupt (DSS) — R/WC. A DMA Setup FIS has been received with

the I bit set and has b een copied into system memory.

1PIO Setup FIS Interrupt ( PSS) — R/WC. A PIO Setup FIS has been received with the

I bit set, it has been copied into system memory, and the data related to that FIS has

been transferred.

0Device to Host Register FIS Interrupt (DHRS) — R/WC. A D2H Register FIS has

been received with the I bit set, and has been copied into system memory.

Bit Description

31 Cold Presence Detect Enable (CPDE) — RO. Cold Presence Detect is not supported.

30 Task File Error Enable (TFEE) — R/W. When set, and GHC.IE and PxTFD.STS.ERR

(due to a reception of the error register from a received FIS) are set, the Intel® ICH8

will generate an interrupt.

29 Host Bus Fatal Error Enable (HBFE) — R/W. Wh en set, and GHC.IE and PxS.HBFS

are set, the ICH8 will generate an interrupt.

28 Host Bus Data Error Enable (HBDE) — R/W. When set, and GHC.IE and PxS.HBDS

are set, the ICH8 will generate an interrupt.

27 Host Bus Data Error Enable (HBDE) — R/W. When set, GHC.IE is set, and

PxIS.HBDS is set, the ICH8 will generate an interrupt.

26 Interface Non-fatal Error Enable (INFE) — R/W. When set, GHC.IE is set, and

PxIS.INFS is set, the ICH8 will generate an interrupt.

25 Reserved - Should be written as 0

24 Overflow Error Enable (OFE) — R/W. When set, and GHC.IE and PxS.OFS are set,

the ICH8 will generate an interrupt.

SATA Controller Registers (D31:F2)

528 Intel® ICH8 Family Datasheet

23 Incorrect Port Multiplier Enable (IPME) — R/W. When set, and GHC.IE and

PxIS.IPMS are set, the ICH8 will generate an interrupt.

NOTE: Should be written as 0. Port Multiplier not supported by ICH8.

22 PhyRdy Change Interrupt Enable (PRCE) — R/W. When set, and GHC.IE is set, and

PxIS.PRCS is set, the ICH8 shall generate an interrupt.

21:8 Reserved - Should be written as 0

7Device Interlock Enable (DIE) — R/W. When set, and PxIS.DIS is set, the ICH8 will

generate an interrupt.

For systems that do not support an interlock switch, this bit shall be a read-only 0.

6Port Change Interrupt Enable (PCE) — R/W. When set, and GHC.IE and PxS.PCS

are set, the ICH8 will generate an interrupt.

5Descriptor Processed Interrupt Enable (DPE) — R/W. When set, and GHC.IE and

PxS.DPS are set, the ICH8 will generate an interrupt

4Unknown FIS Interrupt Enable (UFIE) — R/W. When set, and GHC.IE is set and an

unknown FIS is received, the ICH8 will generate this interrupt.

3Set Device Bit s FI S I nterrupt Enable (SD BE) — R/W. When set, and GHC.IE and

PxS.SDBS are se t, the ICH8 will generate an interrupt.

2DMA Setup FIS Interrupt Enable (D SE) — R/W. When set, and GHC.IE and PxS.DSS

are set, the ICH8 will generate an interrupt.

1PIO Setup FIS Interrupt Enable (PSE) — R/W. When set, and GHC.IE and PxS.PSS

are set, the ICH8 will generate an interrupt.

0Device to Host Register FIS Interrupt Enable (DHRE) — R/W. When set, and

GHC.IE and PxS.DHRS are set, the ICH8 will generate an interrupt.

Bit Description

Intel® ICH8 Family Datasheet 529

SATA Controller Registers (D31:F2)

12.4.2.7 PxCMD—Port [5:0] Command Register (D31:F2)

Address Offset: Port 0: ABAR + 118h Attribute: R/W, RO, R/WO

Port 1: ABAR + 198h

Port 2: ABAR + 218h

Port 3: ABAR + 298h (Desktop Only)

Port 4: ABAR + 318h (Desktop Only)

Port 5: ABAR + 398h (Desktop Only)

Default Value: 0000w00wh Size: 32 bits

where w = 00?0b (for?, see bit description)

Bit Description

31:28

Interface Communication Contr ol ( ICC) — R/W. This is a four bit field which

can be used to control reset and power states of the interface. Writes to this field

will cause actions on the interface, either as primitives or an OOB sequence, and

the resulting status of the interface will be reported in the PxSSTS register

(Address offset Port 0:ABAR+124h, Port 1: ABAR+1A4h, Port 2: ABAR+224h,

Port 3: ABAR+2A4h, Port 4: ABAR+224h, Port 5: ABAR+2A4h).

When system software writes a non-reserved value other than No-Op (0h), the

ICH8 will perform the action and update this field back to Idle (0h).

If software writes to this field to change the state to a state the link is already in

(e.g. interface is in the active state and a request is made to go to the acti ve

state), the ICH8 will take no action and return this field to Idle.

NOTE: When the ALPE bit (bit 26) is set, then this register should not be set to

02h or 06h.

Aggressive Slumber / Partial (ASP) — R/W. When set, and the ALPE bit (bit

26) is set, the ICH8 shall aggressively enter the sl umber state when it clears the

PxCI register and the PxSACT register is cleared. When cleared, and the ALPE bit is

set, the ICH8 will aggressively enter the partial state when it clears the PxCI

shall treat this bit as reserved.

26 Aggressive Link Power Management Enable (ALPE) — R/W. When set, the

ICH8 will aggressively enter a lower link power state (partial or slumber) based

upon the setting of the ASP bit (bit 27).

Drive LED on ATAPI Enab le (DLA E) — R/W. When set, the ICH8 will drive the

LED pin active for ATAPI commands (PxCLB[CHz.A] set) in addition to ATA

commands. When cleared, the ICH8 will only drive the LED pin active for ATA

commands. See Section 5.16.5 for details on the activity LED.

Value Definition

Fh–7h Reserved

6h Slumber: This will ca use the Intel® ICH8 to request a transition of

the interface to the slumber state. The SATA device may reject

the request and the interface will remain in its current state

5h–3h Reserved

2h Partial: This will cause the ICH8 to request a transition of the

interface to the partial state. The SATA device may reject the

request and the interface will remain in its current state.

1h Active: This will cause the ICH8 to request a transition of the

interface into the active

0h No-Op / Idle: When software reads this value, it indicate s the

ICH8 is not in the process of changing the interfac e state or

sending a device rese t, and a new link command may be issued.

SATA Controller Registers (D31:F2)

530 Intel® ICH8 Family Datasheet

Device is ATAPI (ATAPI) — R/W. When set, the connecte d dev ice is an ATAPI

device. This bit is used by the ICH8 to control whether or not to generate the

desktop LED when commands are active. See Section 5.16.5 for details on the

activity LED.

23:22 Reserved

(ICH8R,

ICH8DO,

ICH8DH

Only)

External SATA Port (ESP) — R/WO.

0 = This port supports internal SATA devices only.

1 = This port will be used with an external SATA device. When set, CAP.SXS must

also be set.

21 Reserved

(ICH8 Base,

and ICH8

Mobile Only)

Reserved

20 Reserved

Interlock Switch Attached to Port (ISP) — R/ WO. When interlock switches are

supported in the platform (CAP.SIS [ABAR+00 h :bit 28] set), this indicates

whether this particular port has an interlock switch attached. This bit can be used

by system software to enable such features as aggressive power management, as

disconnects can always be detected regardless of PHY state with an interlock

switch. When this bit is set, it is expect ed that HPCP (bit 18) in this register is also

set.

The ICH8 takes no action on the state of this bit – it is for system software only.

For example, if this bit is cleared, and an interlock switch toggles, the ICH8 still

treats it as a proper interlock switch event.

Note that these bits are not reset on a HBA reset.

Hot Plug Capable Port (HPCP) — R/WO.

0 = Port is not capable of Hot-Plug.

1 = Port is Hot-Plug capable.

This indicates whether the platform exposes this port to a device which can be

Hot-Plugged. SATA by definition is hot-pluggable, but not all platforms are

constructed to allow the device to be removed (it may be screwed into the ch assis,

for example). This bit can be used by system software to indicate a feature such

as “eject device” to the end-user. The ICH8 takes no action on the state of this bit

- it is for system software only. For example, if this bit is cleared, and a Hot-Plug

event occurs, the ICH8 still treats it as a proper Hot-Plug event.

Note that these bits are not reset on a HBA reset.

Port Multiplier Attached (PMA) — RO / R/W. When this bit is set, a port

multiplier is attached to the ICH8 for this port. When cleared, a port multiplier is

not attached to this port.

This bit is RO 0 when CAP.PMS (offset ABAR+00h:bit 17) = 0 and R/W when

CAP.PMS = 1.

NOTE: Port Multiplier not supported by ICH8.

16 Port Multiplier FIS Based Switching Enable (PMFSE) — RO. The ICH8 does not

support FIS-based switching.

NOTE: Port Multiplier not supported by ICH8.

15 Controller Running (CR) — RO. When this bi t is set, the DM A en gines for a po rt

are running. See section 5.2.2 of the Serial ATA AHCI Specification for details on

when this bit is set and cleared by the ICH8.

14 FIS Receive Running (FR) — RO. Wh en set, the FI S Rece ive DMA en gine for the

port is running. See section 12.2.2 of the Serial ATA AHCI Specification for details

on when this bit is set and cleared by the ICH8.

Bit Description

Intel® ICH8 Family Datasheet 531

SATA Controller Registers (D31:F2)

Interloc k Switch State (ISS ) — RO. For systems that support interlock switches

(via CAP.SIS [ABAR+00h:bit 28]), if an interlock switch exists on this port (via ISP

in this register), this bit indicates the current state of the interlock switch. A 0

indicates the switc h is closed, and a 1 indicates the switch is opened.

For systems that do not support interlock switches, or if an interlock switch is not

attached to this port, this bit reports 0.

12:8

Current Command Slot (CCS) — RO. Indicates the current command slot the

ICH8 is processing. This field is valid when the ST bit is set in this register, and is

constantly updated by the ICH8. This field can be updated as soon as the ICH8

recognizes an active command slot, or at some point soon after when it begins

processing the com mand.

This field is used by software to determine the current command issue location of

the ICH8. In queued mode, software shall not use this field, as its value do es not

represent the current command being executed. Software shall only use PxCI and

PxSACT when running queued commands.

7:5 Reserved

FIS Receive Enable (FRE) — R/W. When set, the ICH8 may post received FISes

into the FIS receive area pointed to by PxFB (ABAR+108h/188h/208h/288h) and

PxFBU (ABAR+10Ch/18Ch/20Ch/28Ch). When cleared, received FISes are not

accepted by the ICH8, except for the first D2H (device-to-host) register FIS after

the initializat ion sequence.

System software must not set this bit until PxFB (PxFBU) have been programmed

with a valid pointer to the FIS receive area, and if software wishes to move the

base, this bit must first be cleared, and software must wait for the FR bit (bit 14)

in this register to be cleared.

Command List Override (CLO) — R/ W. Setting this bit to '1' cau ses PxTFD.STS .BSY

and PxTFD.STS.DRQ to be cleared to '0'. This allows a software reset to be

transmit te d to the device re gardless of whether the BSY and DRQ bits are still set

in the PxTFD.STS register. The HBA se ts this bit to '0' when PxTFD.STS.BSY and

PxTFD.ST S.DRQ hav e been cleared to '0'. A wri te to this register with a value of '0'

shall have no effect.

This bit shall only be set to '1' immediately prior to setting the PxCMD.ST bit to 1

from a previous value of 0. Setting this bit to 1 at any other time is not supported

and will result in indeterminate behavior. Software must wait for CLO to be cleared

to 0 before setting PxCMD.ST to 1.

2 Power On Device (POD) — RO. Cold presence detect not supported. Defaults to 1.

Spin-Up Device (SUD) — R/W / RO

This bit is R/W and defaults to 0 for systems that support staggered spin-up (R/W

when CAP.SSS (ABAR+00h:bit 27) is 1). Bit is RO 1 for systems that do not

support staggered spin-up (when CAP.SSS is 0).

0 = No action.

1 = On an edge detect from 0 to 1, the ICH8 starts a COMRESET initialization

sequence to the device.

Clearing this b it to 0 do es not cause any OO B sig n al t o be s ent on the interface. When this bit

is cleared to 0 and PxSCTL.DET=0h, the HBA will enter listen mode.

Start (ST) — R/W. When set, the ICH8 may process the command list. When

cleared, the ICH8 may not process the command list. Whenever this bit is changed

from a 0 to a 1, the ICH8 starts processing the command lis t at entry 0. Whenev er

this bit is changed from a 1 to a 0, the PxCI register is cleared by the ICH8 upon

the ICH8 putting the controller into an idle state.

Refer to Section 12.2.1 of the Serial ATA AHCI Specification for important

restrictions on when ST can be set to 1.

Bit Description

SATA Controller Registers (D31:F2)

532 Intel® ICH8 Family Datasheet

12.4.2.8 PxTFD—Port [5:0] Task File Data Register (D31:F2)

Address Offset: Port 0: ABAR + 120h Attribute: RO

Port 1: ABAR + 1A0h

Port 2: ABAR + 220h

Port 3: ABAR + 2A0h (Desktop Only)

Port 4: ABAR + 320h (Desktop Only)

Port 5: ABAR + 3A0h (Desktop Only)

Default Value: 0000007Fh Size: 32 bits

This is a 32-bit register that copies specific fields of the task file when FISes are

received. The FISes that contain this information are:

D2H Register FIS

PIO Setup FIS

Set Device Bits FIS

12.4.2.9 PxSIG—Port [5:0] Signature Register (D31:F2)

Address Offset: Port 0: ABAR + 124h Attribute: RO

Port 1: ABAR + 1A4h

Port 2: ABAR + 224h

Port 3: ABAR + 2A4h (Desktop Only)

Port 4: ABAR + 324h (Desktop Only)

Port 5: ABAR + 3A4h (Desktop Only)

Default Value: FFFFFFFFh Size: 32 bits

This is a 32-bit register which contains the initial signature of an attached device when

the first D2H Register FIS is received from that device. It is updated once after a reset

sequence.

Bit Description

31:16 Reserved

15:8 Error (ERR) — RO. Contains the latest copy of the task file error register.

7:0

Status (STS) — RO. Contains the latest copy of the task file status register. Fields of

note in this register that affect AHCI.

Bit Field Definition

7 BSY Indicate s the interface is busy

6:4 N/A Not applicable

3 DRQ Indicates a data transfer is requested

2:1 N/A Not applicable

0 ERR Indicates an error during the transfer

Bit Description

31:0

Signature (S IG) — RO. Contains the signature received from a device on the first D2H

Bit Field

31:24 LBA High Register

23:16 LBA Mid Register

15:8 LBA Low Register

7:0 Sector Count Register

Intel® ICH8 Family Datasheet 533

SATA Controller Registers (D31:F2)

12.4.2.10 PxSSTS—Port [5:0] Serial ATA Status Register (D31:F2)

Address Offset: Port 0: ABAR + 128h Attribute: RO

Port 1: ABAR + 1A8h

Port 2: ABAR + 228h

Port 3: ABAR + 2A8h (Desktop Only)

Port 4: ABAR + 328h (Desktop Only)

Port 5: ABAR + 3A8h (Desktop Only)

Default Value: 00000000h Size: 32 bits

This is a 32-bit register that conveys the current state of the interface and host. The

ICH8 updates it continuously and asynchronously. When the ICH8 transmits a

COMRESET to the device, this register is updated to its reset values.

Bit Description

31:12 Reserved

11:8

Interface Power Management (IPM) — RO. Indicates the current interface state:

All other values reserved.

7:4

Current Interface Speed (SPD) — RO. Indicates the negotiated interface

communication speed.

All other values reserved.

ICH8 Supports Generation 1 communication rates (1.5 Gb/sec) and Gen 2 rates (3.0

Gb/s).

3:0

Device Detection (DET) — RO. Indicates the interface device detection and Phy

state:

All other values reserved.

Value Description

0h Device not present or communication not established

1h Interface in active state

2h Interface in PARTIAL power management state

6h Interface in SLUMBER power management state

Value Description

0h Device not present or communication not established

1h Generation 1 communication rate negotiated

2h Generation 2 communication rate negotiated

Value Description

0h No device detected and Phy comm unication not established

1h Device presence detected but Phy communication not esta blished

3h Device presence detect ed and Phy communication established

4h Phy in offline mode as a result of the interface being disabled or

running in a BI ST loopback mode

SATA Controller Registers (D31:F2)

534 Intel® ICH8 Family Datasheet

12.4.2.11 PxSCTL — Port [5:0] Serial ATA Control Register (D31:F2)

Address Offset: Port 0: ABAR + 12Ch Attribute: R/W, RO

Port 1: ABAR + 1ACh

Port 2: ABAR + 22Ch

Port 3: ABAR + 2ACh (Desktop Only)

Port 4: ABAR + 32Ch (Desktop Only)

Port 5: ABAR + 3ACh (Desktop Only)

Default Value: 00000004h Size: 32 bits

This is a 32-bit read-write register by which software controls SATA capabilities. Writes

to the SControl register result in an action being taken by the ICH8 or the interface.

Reads from the register return the last value written to it.

Bit Description

31:20 Reserved

19:16 Port Multiplier Port (PMP) — RO. This field is not used by AHCI

NOTE: Port Multiplier not supported by ICH8.

15:12 Select Power Management (SPM) — RO. This field is not used by AHCI

11:8

Interface Power Management Transitions Allowed (IPM) — R/W. Indicates which

power states the ICH8 is allowed to transition to:

All other values reserved

7:4

Speed Allowed (SPD) — R/W. Indicates the highest allowable speed of the interface.

This speed is limited by the CAP.ISS (ABAR+00h:bit 23:20) field.

ICH8 Supports Generation 1 communication rates ( 1.5 Gb/sec) and Gen 2 rates

(3.0 Gb/s).

3:0

Device Detecti on Initialization (DET) — R/W. Controls the ICH8’s device detection

and interface initialization.

All other values reserved.

When this field is written to a 1h, the ICH8 initiates COMRESET and starts the

initialization process . When the initiali zation is complete, this field shall remain 1h until

set to another value by software.

This field may only be changed to 1h or 4h when PxCMD.ST is 0. Changing this field

while the ICH8 is running results in undefined behavior.

Note: It is permissible to im plement any of the Serial ATA defined behaviors for

transmission of COMRESET when DET=1h.

Value Description

0h No interface restrictions

1h Transitions to the PARTIAL state disabled

2h Transitions to the SLUMBER state disabled

3h Transitions to both PARTIAL and SLUMBER states disabled

Value Description

0h No speed negotiation restrictions

1h Limit speed negotiation to Generation 1 communication rate

2h Limit speed negotiation to Generation 2 communication rate

Value Description

0h No device detection or initializat ion action requested

1h Perform interface communication initialization sequence to establish

communication. This is functionally equivalent to a hard reset and

results in the interface being reset and comm unications re-initialized

4h Disable the Serial ATA interface and put Phy in offline mode

Intel® ICH8 Family Datasheet 535

SATA Controller Registers (D31:F2)

12.4.2.12 PxSERR—Port [5:0] Serial ATA Error Register (D31:F2)

Address Offset: Port 0: ABAR + 130h Attribute: R/WC

Port 1: ABAR + 1B0h

Port 2: ABAR + 230h

Port 3: ABAR + 2B0h (Desktop Only)

Port 4: ABAR + 330h (Desktop Only)

Port 5: ABAR + 3B0h (Desktop Only)

Default Value: 00000000h Size: 32 bits

Bit Description

31:16

Diagnostics (DIAG) — R/WC. This field contains diagnostic error information for use

by diagnostic software in validating correct operation or isolating failure modes:

Bits Description

31:27 Reserved

26 Exchanged (X): When set to one this bit indicates a COMINIT signal was

received. This bit is reflected in the interrupt register PxIS.PCS.

25 Unrecognized FIS Type (F): Indicates that one or more FISs were received

by the Transport layer with good CRC, but had a type field that was not

recognized.

24 Transport state transition error (T): Indicates that an error has occurred in

the transitionfrom one state to another within the Transport layer since the last

time this bit was cleared.

23 Link Sequence Error (S): Indicates that one or more Link state machine error

conditions was encountered. The Link Layer state machine defines the

conditions under which the li nk layer detects an erroneous transition.

22 Handshake Error (H): Indicate s that one or more R_ERR handsh ake response

was received in response to frame transmission. Such errors ma y be t he re su l t

of a CRC error detected by the recipient, a disparity or 8b/10b decoding error,

or other error condition leading to a negative handshake on a transmitted

frame.

21 CRC Error (C): Indicates that one or more CRC errors occurred with the Link

Layer.

20 Disparity Error (D): This fi eld is not used by AHCI.

19 10b to 8b Decode Error (B): Indicates that one or more 10b to 8b decoding

errors occurred.

18 Comm Wake (W): Indicates that a Comm Wake signal was detected by the

Phy.

17 Phy Internal Error (I): Indica tes that the Phy detect ed some internal error.

16 PhyRdy Change (N): When set to 1 th is bit in dicates that t he internal PhyRdy

signal changed state since the last tim e this bit was cleared. In the ICH8, this

bit will be set when PhyRdy changes from a 0 -> 1 or a 1 -> 0. The state of this

bit is then reflected in the PxIS.PRCS interrupt status bit and an interrupt will

be generated if enabled. Software clears this bit by writing a 1 to it.

SATA Controller Registers (D31:F2)

536 Intel® ICH8 Family Datasheet

15:0

Error (ERR) — R/WC. The ERR field contains error information for use by host

software in determining the appropriate response to the error condition.

If one or more of bits 11:8 of this register are set, the controller will stop the current

transfer.

Bits Description

15:12 Reserved

11 Internal Error (E): The SAT A con troller fail ed due to a master or target abo rt

when attempting to access system memory.

10 Protocol Error (P): A violation of the Serial ATA protocol was detected.

Note: The ICH8 does not set this bit for all protocol violations that may occur

on the SATA link.

9 Persistent Communication or Data Integrity Error (C): A communi cation

error that was not recovered occurred that is expected to be persistent.

Persistent communications errors may arise from faulty interconnect with the

device, from a device that has been removed or has failed, or a number of

other causes.

8 Transient Data In tegrity Error (T) : A data integrity erro r occurred that was

not recovered by the interface.

7:2 Reserved

1Recovered Communications Error (M): Communications between the

device and host was temporarily lost but was re-established. This can arise

from a device temporarily being removed, from a temporary loss of Phy

synchronization, or from other causes and may be derived from the PhyNRdy

signal between the Phy and Link layers.

0Recovered Data Integrity Error (I): A data integrity error occurred that was

recovered by the interface through a retry operation or other recovery action.

Bit Description

Intel® ICH8 Family Datasheet 537

SATA Controller Registers (D31:F2)

12.4.2.13 PxSACT—Port [5:0] Serial ATA Active (D31:F2 )

Address Offset: Port 0: ABAR + 134h Attribute: R/W

Port 1: ABAR + 1B4h

Port 2: ABAR + 234h

Port 3: ABAR + 2B4h (Desktop Only)

Port 4: ABAR + 334h (Desktop Only)

Port 5: ABAR + 3B4h (Desktop Only)

Default Value: 00000000h Size: 32 bits

12.4.2.14 PxCI—Port [5:0] Command Issue Register (D31:F2)

Address Offset: Port 0: ABAR + 138h Attribute: R/W

Port 1: ABAR + 1B8h

Port 2: ABAR + 238h

Port 3: ABAR + 2B8h (Desktop Only)

Port 4: ABAR + 338h (Desktop Only)

Port 5: ABAR + 3B8h (Desktop Only)

Default Value: 00000000h Size: 32 bits

§ §

Bit Description

31:0

Device Status (DS) — R/W. S ystem software sets this bit for SA T A queuing oper ations

prior to setting the PxCI.CI bit in the same command slot entry. This field is cleared via

the Set Device Bits FIS.

This field is also cleared when PxCMD.ST (ABAR+118h/198h/218h/298h:bit 0) is

cleared by software, and as a result of a COMRESET or SRST.

Bit Description

31:0

Commands Issued (CI) — R/W. This field is set by software to indicate to the ICH8

that a command has been built-in system memory for a command slot and may be sent

to the device. Wh en th e ICH8 re ceiv es a FI S which clears the B SY and DRQ bits for the

command, it clears the corresponding bit in th is register for that command slot. Bits in

this field shall only be set to 1 by software when PxCMD.ST is set to 1.

This field is also cleared when PxCMD.ST (ABAR+118h/198h/218h/298h:bit 0) is

cleared by software.

SATA Controller Registers (D31:F2)

538 Intel® ICH8 Family Datasheet

Intel® ICH8 Family Datasheet 539

SATA Controller Registers (D31:F5)

13 SATA Controller Registers

(D31:F5)

13.1 PCI Configuration Registers (SATA–D31:F5)

Note: Address locations that are not shown should be treated as Reserved.

All of the SATA registers are in the core well. None of the registers can be locked.

Table 127. SATA Controller PCI Register Address Map (SATA–D31:F5) (Sheet 1 of 2)

Offset Mnemonic Register Name Default Type

00h–01h VID Vendor Identification 8086h RO

02h–03h DID Device Identification See register

description RO

04h–05h PCICMD PCI Command 0000h R/W, RO

06h–07h PCISTS PCI Status 02B0h R/WC, RO

08h RID Revision Ide n tification See register

description RO

09h PI Programming Interface See register

description See register

description

0Ah SCC Sub Class Code See register

description See register

description

0Bh BCC Base Class Code 01h RO

0Dh PMLT Primary Master Latency Timer 00h RO

10h–13h PCMD_BAR Primary Command Block Base Address 00000001h R/W, RO

14h–17h PCNL_BAR Primary Control Block Base Address 00000001h R/W, RO

18h–1Bh SCMD_BAR Secondary Command Block Base

Address 00000001h R/W, RO

1Ch–1Fh SCNL_BAR Secondary Control Block Base Address 00000001h R/W, RO

20h–23h BAR Legacy Bus Master Base Address 00000001h R/W, RO

24h–27h SIDPBA Serial ATA Index / Data Pair Base

Address 00000000h See register

description

2Ch–2Dh SVID Subsystem Vendor Identification 0000h R/WO

2Eh–2Fh SID Subsystem Identification 0000h R/WO

34h CAP Capabilities Pointer 80h RO

3Ch INT_LN Interrupt Line 00h R/W

3Dh INT_PN Interrupt Pin See register

description RO

40h–41h IDE_TIMP Primary IDE Timing 0000h R/W

42h–43h IDE_TIMS Secondary IDE Timing 0000h R/W

44h SIDETIM Slave IDE Timing 00h R/W

48h SDMA_CNT Synchronous DMA Control 00h R/W

SATA Controller Registers (D31:F5)

540 Intel® ICH8 Family Datasheet

NOTE: The ICH8 SATA controller is not arbitrated as a PCI device, therefore it does not need a

master latency timer.

13.1.1 VID—Vendor Identification Register (SATA—D31:F5)

Offset Address: 00h–01h Attribute: RO

Default Value: 8086h Size: 16 bit

Lockable: No Power Well: Core

4Ah–4Bh SDMA_TIM Synchronous DMA Timing 0000h R/W

54h–57h IDE_CONFIG IDE I/O Configuration 00000000h R/W

70h–71h PID PCI Power Management Capability ID See register

description RO

72h–73h PC PCI Power Management Capabilities 4002h RO

74h–75h PMCS PCI Power Management Control and

Status 0000h R/W, R O,

R/WC

80h–81h MSICI Message Signaled Interrupt Capability

ID 7005h RO

82h–83h MSIMC Message Signaled Interrupt Message

Control 0000h RO, R/W

84h–87h MSIMA Message Signaled Interrupt Message

Address 00000000h RO, R/W

88h–89h MSIMD Message Signaled Interrupt Message

Data 0000h R/W

90h MAP Address Map 00h R/W

92h–93h PCS Port Control and Status 0000h R/W, RO,

R/WC

94h–97h SIR SATA Initialization Register 00000000h R/W

A0h SIRI SATA Indexed Registers Index 00h R/W

A4h STRD SATA Indexed Register Data XXXXXXXXh R/W

A8h–ABh SCAP0 SATA Capability Register 0 00100012h RO

ACh–AFh SCAP1 SATA Capability Register 1 00000048h RO

C0h ATC APM Trapping Control 00h R/W

C4h ATS ATM Trapping Status 00h R/WC

D0h–D3h SP Scratch Pad 00000000h R/W

E0h–E3h BFCS BIST FIS Control/Status 00000000h R/W, R/WC

E4h–E7h BFTD1 BIST FIS Transmit Data, DW1 00000000h R/W

E8h–EBh BFTD2 BIST FIS Transmit Data, DW2 00000000h R/W

Table 127. SATA Controller PCI Register Address Map (SATA–D31:F5) (Sheet 2 of 2)

Offset Mnemonic Register Name Default Type

Bit Description

15:0 Vendor ID — RO. This is a 16-bit value assigned to Intel. Intel VID = 8086h

Intel® ICH8 Family Datasheet 541

SATA Controller Registers (D31:F5)

13.1.2 DID—Device Identification Register (SATA—D31:F5)

Offset Address: 02h–03h Attribute: RO

Default Value: See bit description Size: 16 bit

Lockable: No Power Well: Core

13.1.3 PCICMD—PCI Command Register (SATA–D31:F5)

Address Offset: 04h–05h Attribute: RO, R/W

Default Value: 0000h Size: 16 bits

Bit Description

15:0 Device ID — RO. This is a 16-bit value assigned to the Intel® ICH8 SATA controller.

NOTE: The value of this fiel d will change dependent upon the value of the MAP

Bit Description

15:11 Reserved

Interrupt Disable — R/W. This disables pin-based INTx# interrupts. This bit has no

effect on MSI operation.

0 = Internal INTx# messages are generated if there is an interrupt and MSI is not

enabled.

1 = Internal INTx# messages will not be generated.

9 Fast Back to Back Enable (FBE) — RO. Reserved as 0.

8 SERR# Enable (SERR_EN) — RO. Reserved as 0.

7 Wait Cycle Control (WCC) — RO. Reserved as 0.

Parity Error Response (PER) — R/W.

0 = Disabled. SATA controller will not generate PERR# when a data parity error is

detected.

1 = Enabled. SATA cont roller will generate PERR# when a data parity error is detected.

5 VGA Palette Snoop (VPS) — RO. Reserved as 0.

4 Postable Memory Write Enable (PMWE) — RO. Reserved as 0.

3 Special Cycle Enable (SCE) — RO. Reserved as 0.

2Bus Master Enable (BME) — R/W. This bit controls the ICH8’s ability to act as a PCI

master for IDE Bus Master transfers. This bit does not im pact the generation of

completions for split transaction commands.

1Memory Space Enable (MSE) — RO. This controller does not support AHCI, therefore

no memory space is required.

I/O Space Enable (IOSE) — R/W. This bit controls access to the I/O space registers.

0 = Disables access to the Legacy or Native IDE ports (both Primary and Secondary) as

well as the Bus Master I/O registers.

1 = Enable. Note that the Base Address register for the Bus Master registers should be

programmed before this bit is set.

SATA Controller Registers (D31:F5)

542 Intel® ICH8 Family Datasheet

13.1.4 PCISTS — PCI Status Register (SATA–D31:F5)

Address Offset: 06h–07h Attribute: R/WC, RO

Default Value: 02B0h Size: 16 bits

Note: For the writable bits, software must write a 1 to clear bits that are set. Writing a 0 to

the bit has no effect.

13.1.5 RID—Revision Identification Register (SATA—D31:F5)

Offset Address: 08h Attribute: RO

Default Value: See bit description Size: 8 bits

Bit Description

15 Detected Parity Error (DPE) — R/WC.

0 = No parity error detected by SATA controller.

1 = SATA controller detects a parity error on its interface.

14 Signaled System Err or (S SE) — RO. Reserved as 0.

13 Received Master Abort (RMA) — R/WC.

0 = Master abort Not generated.

1 = SATA controller, as a master, generated a master abort.

12 Reserved as 0 — RO.

11 Signaled Target Abort (STA) — RO. Reserved as 0.

10:9 DEVSEL# Timing Status (DEV_STS) — RO.

01 = Hardwired; Controls the device select time for the SATA controller’ s PCI interface.

Data Parity Erro r Detected (DPED) — RO. F or ICH8, this bit can only be set on read

completions received from SiBUS where there is a parity error.

1 = SATA controller, as a master, either detects a parity error or sees the parity error

line asserted, and the parity error response bit (bit 6 of the command register) is

set.

7Fast Back to Back Capable (FB2BC) — RO. Reserved as 1.

6User Definable Features (UDF ) — RO. Reserved as 0.

566MHz Capable (66MHZ_CAP) — RO. Reserved as 1.

4Capabilities List (CAP_LIST) — RO. This bit indicates the presence of a capabilities

list. The m inimum requirement for the capabilit ies list must be PCI power management

for the SATA controller.

Interrupt Status (INTS) — RO. Reflects the state of INTx# messages.

0 = Interrupt is cleared (independent of the state of Interrupt Disable bit in the

command register [offset 04h]).

1 = Interrupt is to be asserted

2:0 Reserved

Bit Description

7:0 Revision ID — RO . Refer to the Intel® I/O Controller Hub 8 (ICH8) Family Specification

Update for the value of the Revision ID Register

Intel® ICH8 Family Datasheet 543

SATA Controller Registers (D31:F5)

13.1.6 PI—Programming Interface Register (SATA–D31:F5)

Address Offset: 09h Attribute: RO

Default Value: 85h Size: 8 bits

13.1.7 SCC—Sub Class Code Register (SATA–D31:F5)

Address Offset: 0Ah Attribute: RO

Default Value: 01h Size: 8 bits

13.1.8 BCC—Base Class Code Register

(SATA–D31:F5SATA–D31:F5)

Address Offset: 0Bh Attribute: RO

Default Value: 01h Size: 8 bits

13.1.9 PMLT—Primary Master Latency Timer Register

(SATA–D31:F5)

Address Offset: 0Dh A ttribute: RO

Default Value: 00h Size: 8 bits

Bit Description

7 This read-only bit is a 1 to indicate that the ICH8 supports bus master operation

6:4 Reserved. Will always return 0.

3Secondary Mode Native Capable (SNC) — RO.

0 = Secondary controller only supports legacy mode. This bit will always return ‘0’

2Secondary Mode Native Enable (SNE) — R/W / RO.

Determines the mode that the secondary channel is operating in.

1 = Secondary controller operating in native PCI mode. This bit will always return ‘1’

1Primary Mode Native Capable (PNC) — RO.

0 = Primary controller only supports legacy mode. This bit will always return ‘0’

0Primary Mode Native Enable (PNE) — RO.

Determines the mode that the primary channel is operating in.

1 = Primary controller operating in native PCI mode. This bit will always return ‘1’

Bit Description

7:0 Interface (IF) — RO.

This controller only supports ID E programming interface and is only 01h.

Bit Description

7:0 Base Class Code (BCC) — RO.

01h = Mass storage device

Bit Description

7:0 Master La tency Timer Count (MLTC) — RO.

00h = Hardwired. The SATA controller is implemented internally, and is not arbitrated

as a PCI device, so it does not need a Master Latency Timer.

SATA Controller Registers (D31:F5)

544 Intel® ICH8 Family Datasheet

13.1.10 PCMD_BAR—Primary Command Block Base Address

Address Offset: 10h–13h Attribute: R/W, RO

Default Value: 00000001h Size: 32 bits

NOTE: This 8-byte I/O space is used in native mode for the Primary Controller’s Command Block.

13.1.11 PCNL_BAR—Primary Control Block Base Address Register

(SATA–D31:F5)

Address Offset: 14h–17h Attribute: R/W, RO

Default Value: 00000001h Size: 32 bits

NOTE: This 4-byte I/O space is used in native mode for the Primary Controller’s Command Block.

13.1.12 SCMD_BAR—Secondary Command Block Base Address

Address Offset: 18h–1Bh Attribute: R/W, RO

Default Value: 00000001h Size: 32 bits

NOTE: This 8-byte I/O space is used in native mode for the Secondary Controller’s Command

Block.

Bit Description

31:16 Reserved

15:3 Base Address — R/W. This field provides the base address of the I/O space (8

consecutive I/O locations).

2:1 Reserved

0Resource Type Indicator (RTE) — RO. Hardwired to 1 to indicate a request for I/O

space.

Bit Description

31:16 Reserved

15:2 Base Address — R/W. This field provides the base address of the I/O space (4

consecutive I/O locations).

1 Reserved

0 Resource Type Indicator (RTE) — RO. Hardwired to 1 to indicate a request for I/O

space.

Bit Description

31:16 Reserved

15:3 Base Address — R/W. This field provides the base address of the I/O space (8

consecutive I/O locations).

2:1 Reserved

0Resource Type Indicator (RTE) — RO. Hardwired to 1 to indicate a request for I/O

space.

Intel® ICH8 Family Datasheet 545

SATA Controller Registers (D31:F5)

13.1.13 SCNL_BAR—Secondary Control Block Base Address

Address Offset: 1Ch–1Fh Attribute: R/W, RO

Default Value: 00000001h Size: 32 bits

NOTE: This 4-byte I/O spa ce is used in native mode for the Secondary Controller’s Command

Block.

13.1.14 BAR — Legacy Bus Master Base Address Register

(SATA–D31:F5)

Address Offset: 20h–23h Attribute: R/W, RO

Default Value: 00000001h Size: 32 bits

The Bus Master IDE interface function uses Base Address register 5 to request a

16-byte I/O space to provide a software interface to the Bus Master functions. Only

12 bytes are actually used (6 bytes for primary, 6 bytes for secondary). Only bits

[15:4] are used to decode the address.

Bit Description

31:16 Reserved

15:2 Base Address — R/W. This field provides the base address of the I/O space (4

consecutive I/O locations).

1 Reserved

0Resource Ty pe Indicator (RTE) — RO. Hardwired to 1 to indicate a request for I/O

space.

Bit Description

31:16 Reserved

15:4 Base Address — R/W. This field provides the base address of the I/O space

(16 consecutive I/O lo cations).

3:1 Reserved

0Resource Type Indicator (RTE) — RO. Hardwired to 1 to indicate a request for I/O

space.

SATA Controller Registers (D31:F5)

546 Intel® ICH8 Family Datasheet

13.1.15 SIDPBA — SATA Index/Data Pair Base Address Register

(SATA–D31:F5)

Address Offset: 24h–27h Attribute: R/W, RO

Default Value: 00000001h Size: 32 bits

This register is an I/O BAR allocating 16 bytes of I/O space for the I/O-mapped

registers defined in Section 13.3. Note that although 16 bytes of locations are

allocated, some locations are reserved.

13.1.16 SVID—Subsystem Vendor Identification Register

(SATA–D31:F5)

Address Offset: 2Ch–2Dh Attribute: R/WO

Default Value: 0000h Size: 16 bits

Lockable: No Power Well: Core

13.1.17 SID—Subsystem Identification Register (SATA–D31:F5)

Address Offset: 2Eh–2Fh Attribute: R/WO

Default Value: 0000h Size: 16 bits

Lockable: No Power Well: Core

13.1.18 CAP—Capabilities Pointer Register (SATA–D31:F5)

Address Offset: 34h Attribute: RO

Default Value: 80h Size: 8 bits

Bit Description

31:16 Reserved

15:4 Base Address (BA) — R/W. Base address of register I/O space

3:1 Reserved

0Resource Type Indicator (RTE) — RO. Hardwired to 1 to indicate a request for I/O

space.

Bit Description

15:0 Subsystem Vendor ID (SVID) — R/WO. Value is written by BI OS. No hardware

action taken on this value.

Bit Description

15:0 Subsystem ID (SID) — R/WO . V alue is written by BIOS. No hardw are action tak en on

this value.

Bit Description

7:0

Capabilities Pointer (CAP_PTR) — RO. Indicates that the first capability pointer offset is

80h. This value changes to 70h if the MAP.MV register (Dev 31:F2:90h, bits 1:0) in

configuration space indicates that the SATA function and PATA functions are combined

(values of 10b or 10b) or Sub Class Code (CC.SCC) (Dev 31:F2:0Ah) is configure as IDE

mode (value of 01).

Intel® ICH8 Family Datasheet 547

SATA Controller Registers (D31:F5)

13.1.19 INT_LN—Interrupt Line Register (SATA–D31:F5)

Address Offset: 3Ch Attribute: R/W

Default Value: 00h Size: 8 bits

13.1.20 INT_PN—Interrupt Pin Register (SATA–D31:F5)

Address Offset: 3Dh A ttribute: RO

Default Value: See Register Description Size: 8 bits

13.1.21 IDE_TIM — IDE Timing Register (SATA–D31:F5)

Address Offset: Primary: 40h–41h Attribute: R/W

Secondary: 42h–43h

Default Value: 0000h Size: 16 bits

This register controls the timings driven on the IDE cable for PIO and 8237 style DMA

transfers. It also controls operation of the buffer for PIO transfers.

Note: This register is R/W to maintain software compatibility and enable parallel ATA

functionality when the PCI functions are combined. These bits have no effect on SATA

operation unless otherwise noted.

Bit Description

7:0 Interrupt Line — R/W. This field is used to communi cate to software the inte rrupt line

that the interrupt pin is connected to.

Bit Description

7:0 Interrupt Pin — RO. This reflects the value of D31IP.SIP1 (Chipset Configuration

Registers:Offset 3100h:bits 11:8).

Bit Description

IDE Decode Enable (IDE) — R/W. Individually enable/disable the Primary or

Secondary decode.

0 = Disable.

1 = Enables the Intel® ICH8 to decode the associated Command Blocks (1F0–1F7h for

primary, 170–177h for secondary) and Control Block (3F6h for primary and 376h

for secondary).

This bit effects the IDE decode ranges for both legacy and native-Mode decoding.

NOTE: This bit affects SA T A operation in both combined and non-combined AT A modes.

See Section 5.16 for more on ATA modes of operation.

14 Drive 1 Timing Register Enable (SITRE) — R/W.

0 = Use bits 13:12, 9:8 for both drive 0 and drive 1.

1 = Use bits 13:12, 9:8 for drive 0, and use the Slave IDE Timing register for drive 1

13:12

IORDY Sample Point (ISP) — R/W. The setting of these bits det erm in es th e numbe r

of PCI clocks between IDE IOR#/IOW# assertion and the first IORDY sample point.

00 = 5 clocks

01 = 4 clocks

10 = 3 clocks

11 = Reserved

SATA Controller Registers (D31:F5)

548 Intel® ICH8 Family Datasheet

11:10 Reserved

9:8

Recovery Time (RCT) — R/W. The setting of these bits determines the minimum

number of PCI clocks between the last IORDY sample point and the IOR#/IOW# strobe

of the next cycle.

00 = 4 clocks

01 = 3 clocks

10 = 2 clocks

11 = 1 clock

Drive 1 DMA Timing Enable (DTE1) — R/W.

0 = Disable.

1 = Enable the fast timing mode for DMA transfers only for this drive. PIO transfers to

the IDE data port will run in compatible timing.

6Drive 1 Prefetch/Posting Enable (PPE1) — R/W.

0 = Disable.

1 = Enable Prefetch and posting to the IDE data port for this drive.

5Drive 1 IORDY Sample Point Enable (IE1) — R/W.

0 = Disable IORDY sampling for this drive.

1 = Enable IORDY sampling for this drive.

Drive 1 Fast Timing Bank (TIME1) — R/W.

0 = Accesses to the data port will use compatible timings for this drive.

1 = When this bit =1 and bit 14 = 0, accesses to the data port will use bits 13:12 for

the IORDY sample point, and bits 9:8 for the recov e ry ti me. When thi s bit = 1 and

bit 14 = 1, accesses to the data port will use the IORDY sample point and recover

time specified in the slave IDE timing register.

Drive 0 DMA Timing Enable (DTE0) — R/W.

0 = Disable

1 = Enable fast timing mode for DMA transfers only for this drive. PIO transfers to the

IDE data port will run in compatible timing.

2Drive 0 Prefetch/Posting Enable (PPE0) — R/W.

0 = Disable prefetch and posting to the IDE data port for this drive.

1 = Enable prefetch and posting to the IDE data port for this drive.

1Drive 0 IORDY Sample Point Enable (IE0) — R/W.

0 = Disable IORDY sampling is disabled for this drive.

1 = Enable IORDY sampling for this drive.

Drive 0 Fast Timing Bank (TIME0) — R/W.

0 = Accesses to the data port will use compatible timings for this drive.

1 = Accesses to the data port will use bits 13:12 for the IORDY sample point, and bits

9:8 for the recovery time

Bit Description

Intel® ICH8 Family Datasheet 549

SATA Controller Registers (D31:F5)

13.1.22 D1TIM—Device 1 IDE Timing Register (SATA–D31:F5)

Address Offset: 44h Attribute: R/W

Default Value: 00h Size: 8 bits

Note: This register is R/W to maintain software compatibility and enable parallel ATA

functionality when the PCI functions are combined. Device 1 is not allowed on this

controller.

13.1.23 SDMA_CNT—Synchronous DMA Control Register

(SATA–D31:F5)

Address Offset: 48h Attribute: R/W

Default Value: 00h Size: 8 bits

Note: This register is R/W to maintain software compatibility and enable parallel ATA

functionality when the PCI functions are combined. These bits have no effect on SATA

operation unless otherwise noted.

Bit Description

7:0 Reserved

Bit Description

7:3 Reserved

2Secondary Drive 0 ATAxx Enable (SDAE0) — R/W.

0 = Disable (default)

1 = Enable DMA timing modes for the secondary master device.

1 Reserved

0Primary Drive ATAxx Enable (PDAE0) — R/W.

0 = Disable (default)

1 = Enable DMA timing modes for the primary master device

SATA Controller Registers (D31:F5)

550 Intel® ICH8 Family Datasheet

13.1.24 SDMA_TIM—Synchronous DMA Timing Register

(SATA–D31:F5)

Address Offset: 4Ah–4Bh Attribute: R/W

Default Value: 0000h Size: 16 bits

Note: This register is R/W to maintain software compatibility and enable parallel ATA

functionality when the PCI functions are combined. These bits have no effect on SATA

operation, unless otherwise noted.

Bit Description

15:10 Reserved

9:8

Secondary Drive 0 Cycle Time (SCT0) — R/W. For Ultra ATA mode. The setting of

these bits determines the minimum write strobe cycle time (CT). The DMARDY#-to-

STOP (RP) time is also determined by the setting of these bits.

7:2 Reserved

1:0

Primary Drive 0 Cycle T ime (PCT0) — R/W. For Ultra A TA mode, the setting of these

bits determines the minimum write strobe cycle time (CT). The DMARDY#-to-STOP

(RP) time is also determined by the setting of these bits.

SCB1 = 0

(33 MHz clock) SCB1 = 1

(66 MHz clock) FAST_SCB1 = 1

(133 MHz clock)

00 = CT 4 clocks,

RP 6 clocks 00 = Reserved 00 = Reserved

01 = CT 3 clocks,

RP 5 clocks 01 = CT 3 clocks,

RP 8 clocks 01 = CT 3 clocks, RP 16 clocks

10 = CT 2 clocks,

RP 4 clocks 10 = CT 2 clocks,

RP 8 clocks 10 = Reserved

11 = Reserved 11 = Reserved 11 = Reserved

PCB1 = 0

(33 MHz clock) PCB1 = 1

(66 MHz clock) FAST_PCB1 = 1

(133 MHz clock)

00 = CT 4 clocks,

RP 6 clocks 00 = Reserved 00 = Reserved

01 = CT 3 clocks,

RP 5 clocks 01 = CT 3 clocks,

RP 8 clocks 01 = CT 3 clocks, RP 16 clocks

10 = CT 2 clocks,

RP 4 clocks 10 = CT 2 clocks,

RP 8 clocks 10 = Reserved

11 = Reserved 11 = Reserved 11 = Reserved

Intel® ICH8 Family Datasheet 551

SATA Controller Registers (D31:F5)

13.1.25 IDE_CONFIG—IDE I/O Configuration Register

(SATA–D31:F5)

Address Offset: 54h–57h Attribute: R/W

Default Value: 00000000h Size: 32 bits

Note: This register is R/W to maintain software compatibility and enable parallel ATA

functionality when the PCI functions are combined. These bits have no effect on SATA

operation, unless otherwise noted.

Bit Description

31:24 Reserved

23:20 Scratchpad (SP2). Intel® ICH8 does not perform any actions on these bits.

19:18

SEC_SIG_MODE — R/W. These bits are used to control mode of the Secondary IDE

signal pins for swap bay support.

If the SRS bit (Chi pset Configurat ion Registers :Offset 3414h:bit 1) is 1, the reset stat es

of bits 19:18 will be 01 (tri-state) instead of 00 (normal).

00 = Normal (Enabled)

01 = Tri-state (Disabled)

10 = Drive low (Disabled)

11 = Reserved

17:16

PRIM_SIG_MODE — R/W. These bits are used to control mode of the Primary IDE

signal pins for mobile swap bay support.

If the PRS bit (Chipset Configu ration R egisters:Offs et 3414h:bit 1) is 1, the reset states

of bits 17:16 will be 01 (tri-state) instead of 00 (normal).

00 = Normal (Enabled)

01 = Tri-state (Disabled)

10 = Drive low (Disabled)

11 = Reserved

Fast Secondary Drive 1 Base Clock (FAST_SCB1) — R/W. This bit is used in

conjunction with the SCT1 bits (D31:F5:4Ah, bits 13:12) to enable/disable Ultra ATA/

100 timings for the Secondary Slave drive.

0 = Disable Ultra ATA/100 timing for the Secondary Slave drive.

1 = Enable Ultra ATA/100 timing for the Secondary Slave drive (overrides bit 3 in this

Fast Secondary Drive 0 Base Clock (FAST_SCB0) — R/W. This bit is used in

conjunction with the SCT0 bits (D31:F5: 4Ah, bits 9:8) to enable/di sabl e Ul tra ATA/100

timings for the Secondary Master drive.

0 = Disable Ultra ATA/100 timing for the Secondary Master drive.

1 = Enable Ultr a ATA/100 timing fo r t he Se condary Mast er drive (overrides bit 2 i n this

Fast Primar y D r iv e 1 Base Clock (FAS T _ PCB1) — R/W. This bit is used in

conjunction with the PCT1 bits (D31:F5:4Ah, bits 5:4) to enable/disable Ultra ATA/100

timings for the Primary Slave drive.

0 = Disable Ultra ATA/100 timing for the Primary Slave drive.

1 = Enable Ultra ATA/100 timing for the Primary Slave drive (overrides bit 1 in this

Fast Primar y D r iv e 0 Base Clock (FAS T _ PCB0) — R/W. This bit is used in

conjunction with the PCT0 bits (D31:F5:4Ah, bits 1:0) to enable/disable Ultra ATA/100

timings for the Primary Master drive.

0 = Disable Ultra ATA/100 timing for the Primary Master drive.

1 = Enable Ultra ATA/100 timing for the Primary Master drive (overrides bit 0 in this

SATA Controller Registers (D31:F5)

552 Intel® ICH8 Family Datasheet

13.1.26 PID—PCI Power Management Capability Identification

Address Offset: 70h–71h Attribute: RO

Default Value: 0001h Size: 16 bits

13.1.27 PC—PCI Power Management Capabilities Register

(SATA–D31:F5)

Address Offset: 72h–73h Attribute: RO

Default Value: 4003h Size: 16 bits

11:8 Reserved

7:4 Scratchpad (SP1). ICH8 does not perform any action on these bits.

3Secondary Drive 1 Base Cl ock (SCB1) — R/W.

0 = 33 MHz b ase clock fo r Ultra ATA timings.

1 = 66 MHz b ase clock fo r Ultra ATA timings

2Secondary Drive 0 Base Clock (SCBO) — R/W.

0 = 33 MHz b ase clock fo r Ultra ATA timings.

1 = 66 MHz b ase clock fo r Ultra ATA timings

1Primary Drive 1 Base Clock (PCB1) — R/W.

0 = 33 MHz b ase clock fo r Ultra ATA timings.

1 = 66 MHz b ase clock fo r Ultra ATA timings

0Primary Drive 0 Base Clock (PCB0) — R/W.

0 = 33 MHz b ase clock fo r Ultra ATA timings.

1 = 66 MHz b ase clock fo r Ultra ATA timings

Bit Description

Bits Description

15:8 Next Capability (NEXT) — RO.

00h — This is the last item in the list.

7:0 Capability ID (CID) — RO. Indicates that this pointer is a PCI power management.

Bits Description

15:11 PME Support (PME_SUP) — RO. Indicates PME# can be generated from the D3HOT state

in the SATA host controller.

10 D2 Supp ort (D2_SUP) — RO. Hardwired to 0. The D2 state is not supported

9 D1 Support (D1_SUP) — RO. Hardwired to 0. The D1 state is not supported

8:6 Auxiliary Current (AUX_CUR) — RO. PME# from D3COLD state is not supported,

therefore this field is 00 0b.

5Device Specifi c Initialization (DSI) — RO. Hardwired to 0 to indicate that no device-

specific initialization is required.

4 Reserved

3PME Clock (PME_CLK) — RO. Hardwired to 0 to indicate that PCI clock is no t required to

generate PME#.

2:0 Version (VER) — RO. Hardwired to 011 to indicates support for Revision 1.2 of the PCI

Power Management Specification.

Intel® ICH8 Family Datasheet 553

SATA Controller Registers (D31:F5)

13.1.28 PMCS—PCI Power Management Control and Status

Address Offset: 74h–75h Attribute: RO, R/W, R/WC

Default Value: 0008h Size: 16 bits

13.1.29 MAP—Address Map Register (SATA–D31:F5)

Address Offset: 90h Attribute: RO

Default Value: 00h Size: 8 bits

Bits Description

15 PME Status (PMES) — R/WC. Bit is set when a PME event is to be requested, and if

this bit and PMEE is set, a PME# will be generated from the SATA controller

14:9 Reserved

8PME Enable (PMEE) — R/W. When set, the SATA controller generates PME# form

D3HOT on a wake event.

7:4 Reserved

No Soft Reset (NSFRST) — RO. These bits are used to indicate whether devices

transitioning from D3HOT state to D0 state will perform an internal reset.

0 = Device transitioning from D3HOT state to D0 state perform an internal reset.

1 = Device transitioning from D3HOT state to D0 state do not perform an internal reset.

Configuration content is preserved. Upon transition from the D3HOT state to D0 state

initialized state, no additional operating system intervention is required to preserve

configuration contex t beyond writing to the PowerState bits.

Regardle ss of this bit, the controll er transition from D3HOT state to D0 state by a system

or bus segment reset will return to the state D0 uninitialized with only PME conte xt

preserved if PME is supported and enabled.

2Reserved

1:0

Power State (PS) — R/W. These bits are used both to determine the current power

state of the

SATA controller and to set a new power state.

00 = D0 state

11 = D3HOT state

When in the D3HOT state, the controller’s configuration space is available, but the I/O

and memory spaces are not. Additionally, interrupts are blocked.

Bits Description

7:2 Reserved.

1:0 Map Value — RO. Map Value (MV): This field is hardwired to read-only ‘00’ indicating

the controller shall support two logical master devices with Port 0 and Port 1 being

mapped to Primary Channel and Secondary Channel Respectively

SATA Controller Registers (D31:F5)

554 Intel® ICH8 Family Datasheet

13.1.30 PCS—Port Control and Status Register (SATA–D31:F5)

Address Offset: 92h–93h Attribute: R/W, R/WC, RO

Default Value: 0000h Size: 16 bits

By default, the SAT A ports are set to the disabled state (bits [5:0] = ‘0’). When enabled

by software, the ports can transition between the on, partial, and slumber states and

can detect devices. When disabled, the port is in the “off” state and cannot detect any

devices.

If an AHCI-aware or RAID enabled operating system is being booted then system BIOS

shall insure that all supported SATA ports are enabled prior to passing control to the

OS. Once the AHCI aware OS is booted it becomes the enablin g/di sabling po licy owner

for the individual SA TA ports. This is accomplished b y manipulating a port’ s PxSC TL and

PxCMD fields. Because an AHCI or RAID aware OS will typically not have knowledge of

the PxE bits and because the PxE bits act as master on/off switches for the ports, pre-

boot software must insure that these bits are set to ‘1’ prior to booting the OS,

regardless as to whether or not a device is currently on the port.

Bits Description

15:10 Reserved

Port 1 Present (P1P) — RO. The status of this bit may change at any time. This bi t is

cleared when the port is disabled via P1E. This bit is not cleared upon surprise removal

of a device.

0 = No device detected.

1 = The presence of a device on Port 1 has been detected.

Port 0 Present (P0P) — RO. The status of this bit may change at any time. This bi t is

cleared when the port is disabled via P0E. This bit is not cleared upon surprise removal

of a device.

0 = No device detected.

1 = The presence of a device on Port 0 has been detected.

7:2 Reserved

Port 1 Enabled (P1E) — R/W.

0 = Disabled. The port is in the ‘off’ state and can not detect any devices.

1 = Enabled. The port can transition between the on, partial, and slumber states and

can detect devices.

Port 0 Enabled (P0E) — R/W.

0 = Disabled. The port is in the ‘off’ state and can not detect any devices.

1 = Enabled. The port can transition between the on, partial, and slumber states and

can detect devices.

Intel® ICH8 Family Datasheet 555

SATA Controller Registers (D31:F5)

13.1.31 ATC—APM Trapping Control Register (SATA–D31:F5)

Address Offset: C0h Attribute: R/W

Default Value: 00h Size: 8 bits

Note: This SATA controller does not support legacy I/O access. Therefore, this register is

reserved. Software shall not change the default values of the register; otherwise the

result will be undefined.

13.1.32 ATS—APM Trapping Status Register (SATA–D31:F5)

Address Offset: C4h Attribute: R/WC

Default Value: 00h Size: 8 bits

Note: This SATA controller does not support legacy I/O access. Therefore, this register is

reserved. Software shall not change the default values of the register; otherwise the

result will be undefined.

Bit Description

7:0 Reserved

Bit Description

7:0 Reserved

SATA Controller Registers (D31:F5)

556 Intel® ICH8 Family Datasheet

13.2 Bus Master IDE I/O Registers (D31:F5)

The bus master IDE function uses 16 by tes of I/O space, allocated via the BAR register,

located in Device 31:Function 2 Configur ation space, offset 20h. All bus master IDE I/O

space registers can be accessed as byte, word, or dword quantities. Reading reserved

bits returns an indeterminate, inconsistent value, and writes to reserved bits have no

affect (but should not be attempted). These registers are only used for legacy

operation. Software must not use these registers when running AHCI. The description

of the I/O registers is shown in Table 128.

Table 128. Bus Master IDE I/O Register Address Map

BAR+

Offset Mnemonic Register Default Type

00 BMICP Command Register Primary 00h R/W

01 — Reserved — RO

02 BMISP Bus Master IDE Status Register Primary 00h R/W, R/WC,

03 — Reserved — RO

04–07 BMIDP Bus Master IDE Descriptor Table Pointer

Primary xxxxxxxxh R/W

08 BMICS Command Register Secondary 00h R/W

09 — Reserved — RO

0Ah BMISS Bus Master IDE Status Register Secondary 00h R/W, R/WC,

0Bh — Reserved — RO

0Ch–0Fh BMIDS Bus Master IDE Descriptor Table Pointer

Secondary xxxxxxxxh R/W

Intel® ICH8 Family Datasheet 557

SATA Controller Registers (D31:F5)

13.2.1 BMIC[P,S]—Bus Master IDE Command Register (D31:F5)

Address Offset: Primary: BAR + 00h Attribute: R/W

Secondary: BAR + 08h

Default Value: 00h Size: 8 bits

Bit Description

7:4 Reserved. Returns 0.

Read / Write Control (R/WC) — R/W. This bit sets the direction of the bus master

transfer: This bit must NOT be changed when the bus master function is active.

0 = Memory reads

1 = Memory writes

2:1 Reserved. Returns 0.

Start/Stop Bus Master (START) — R/W.

0 = All state information is lost when this bit is cleared. Master mode operation cannot

be stopped and then resumed. If this bit is reset while bus master operation is still

active (i.e., the Bus Master IDE Active bit (D31:F5:BAR + 02h, bit 0) of the Bus

Master IDE Status register for that IDE channel is set) and th e drive has not yet

finished it s data trans fer (the Interru pt bit in the Bus Master IDE Status register for

that IDE channel is not set), the bus master command is said to be aborted and

data transferred from the drive may be discarded instead of being written to

system memory.

1 = Enables bus master operation of the controller. Bus master operation does not

actually start unless the Bus Master Enable bit (D31:F1:04h, bit 2) in PCI

configuration space is also set. Bu s master operation begins when this bit is

detected changing from 0 to 1. The controller will transfer data between the IDE

device and memory only when this bit is set. Master operation can be halted by

writing a 0 to thi s bit.

NOTE: This bit is intended to be cleared by software after the data transfer is

completed, as indicated by either the Bus Master IDE Active bit being cleared or

the Interrupt bit of the Bus Master IDE Status register for that IDE channel

being set, or both. Hardware does not clear this bit automatically. If this bit is

cleared to 0 prior to the DMA data transfer being initiated by the drive in a

SATA Controller Registers (D31:F5)

558 Intel® ICH8 Family Datasheet

13.2.2 BMIS[P,S]—Bus Master IDE Status Register (D31:F5)

Address Offset: Primary: BAR + 02h Attribute: R/W, R/WC, RO

Secondary: BAR + 0Ah

Default Value: 00h Size: 8 bits

13.2.3 BMID[P,S]—Bus Master IDE Descriptor Table Pointer

Address Offset: Primary: BAR + 04h–07h Attribute: R/W

Secondary: BAR + 0Ch–0Fh

Default Value: All bits undefined Size: 32 bits

Bit Description

PRD Interrupt Status (PRDIS) — R/WC.

0 = Software clears this bit by writing a 1 to it.

1 = This bit is set when th e host cont roller ex ecution of a PRD that has its PRD_INT bit

set.

6 Reserved.

Drive 0 DMA Capa ble — R/W.

0 = Not Capable

1 = Capable. Set by device dependent code (BIOS or device driver) to indicate that

drive 0 for this channel is capable of DMA transfers, and that the controller has

been initialized for optimum performance. The ICH8 does not use this bit. It is

intended for systems that do not attach BMIDE to the PCI bus.

4:3 Reserved. Retur ns 0.

Interrupt — R/WC .

0 = Software clears this bit by writing a 1 to it.

1 = Set when a device FIS is rece ived with the ‘I’ bit se t, provided that softw are has not

disabled interrupts via the IE N bit of the Device Control Register (see chapter 5 of

the Serial ATA Specification, Revision 2.5).

Error — R/WC.

0 = Software clears this bit by writing a 1 to it.

1 = This bit is set wh en the controller encounters a target abort or master abort when

transferring data on PCI.

Bus Master IDE Active (ACT) — RO.

0 = This bit is cleared by the ICH8 when the last transfer for a region is performed,

where EOT for that region is set in the region descriptor. It is also cleared by the

ICH8 when the Start Bus Master bit (D31:F5:BAR+ 00h, bit 0) is cleared in the

Command register. When this bit is read as a 0, all data transferred from the drive

during the previous bus master command is visible in system memory, unless the

bus master command was aborted.

1 = Set by the ICH8 when the Start bit is written to the Command register.

Bit Description

31:2

Address of Descriptor Table (ADDR) — R/W. The bits in this field correspond to bits

[31:2] of the memory location of the Physical Region Descriptor (PRD). The Descriptor

Table must be DW ord-aligned. The Descriptor Table must not cross a 64-KB boundary in

memory.

1:0 Reserved

Intel® ICH8 Family Datasheet 559

SATA Controller Registers (D31:F5)

13.2.3.1 PxSSTS—Serial ATA Status Register (D31:F5)

Address Offset: BAR + 00h Attribute: RO

Default Value: 00000000h Size: 32 bits

This is a 32-bit register that conveys the current state of the interface and host. The

ICH8 updates it continuously and asynchronously. When the ICH8 transmits a

COMRESET to the device, this register is updated to its reset values.

Bit Description

31:12 Reserved

11:8

Interface Power Management (IPM) — RO. Indicates the current interface state:

All other values reserved.

7:4

Current Interface Speed (SPD) — RO. Indicates the negotiated interface

communication speed.

All other values reserved.

ICH8 Supports Generation 1 communication rates (1.5 Gb/sec) and Gen 2 rates (3.0

Gb/s).

3:0

Device Detection (DET) — RO. Indicates the interface device detection and Phy

state:

All other values reserved.

Value Description

0h Device not present or communication not established

1h Interface in active state

2h Interface in PARTIAL power management state

6h Interface in SLUMBER power management state

Value Description

0h Device not present or communication not established

1h Generation 1 communication rate negotiated

2h Generation 2 communication rate negotiated

Value Description

0h No device detected and Phy comm unication not established

1h Device presence detected but Phy communication not esta blished

3h Device presence detect ed and Phy communication established

4h Phy in offline mode as a result of the interface being disabled or

running in a BI ST loopback mode

SATA Controller Registers (D31:F5)

560 Intel® ICH8 Family Datasheet

13.2.3.2 PxSCTL — Serial ATA Control Register (D31:F5)

Address Offset: BAR + 01h Attribute: R/W, RO

Default Value: 00000004h Size: 32 bits

This is a 32-bit read-write register by which software controls SATA capabilities. Writes

to the SControl register result in an action being taken by the ICH8 or the interface.

Reads from the register return the last value written to it.

Bit Description

31:20 Reserved

19:16 Port Multiplier Port (PMP) — RO. This field is not used by AHCI

NOTE: Port Multiplier not supported by ICH8.

15:12 Select Power Management (SPM) — RO. This field is not used by AHCI

11:8

Interface Power Management Transitions Allowed (IPM) — R/W. Indicates which

power states the ICH8 is allowed to transition to:

All other values reserved

7:4

Speed Allowed (SPD) — R/W. Indicates the highest allowable speed of the interface.

This speed is limited by the CAP.ISS (ABAR+00h:bit 23:20) field.

All other values reserved.

ICH8 Supports Generation 1 communication rates ( 1.5 Gb/sec) and Gen 2 rates

(3.0 Gb/s).

3:0

Device Detecti on Initialization (DET) — R/W. Controls the ICH8’s device detection

and interface initialization.

All other values reserved.

When this field is written to a 1h, the ICH8 initiates COMRESET and starts the

initialization process . When the initiali zation is complete, this field shall remain 1h until

set to another value by software.

This field may only be changed to 1h or 4h when PxCMD.ST is 0. Changing this field

while the ICH8 is running results in undefined behavior.

Value Description

0h No interface restrictions

1h Transitions to the PARTIAL state disabled

2h Transitions to the SLUMBER state disabled

3h Transitions to both PARTIAL and SLUMBER states disabled

Value Description

0h No speed negotiation restrictions

1h Limit speed negotiation to Generation 1 communication rate

2h Limit speed negotiation to Generation 2 communication rate

Value Description

0h No device detection or initializat ion action requested

Perform interface communication initialization sequence to establish

communication. This is functionally equivalent to a hard reset and

results in the interface being reset and communications re-

initialized

4h Disable the Serial ATA interface and put Phy in offline mode

Intel® ICH8 Family Datasheet 561

SATA Controller Registers (D31:F5)

13.2.3.3 PxSERR—Serial ATA Error Register (D31:F5)

Address Offset: BAR + 02h Attribute: R/WC

Default Value: 00000000h Size: 32 bits

Bit Description

31:16

Diagnostics (DIAG) — R/WC. Contains diagnostic error information for use by

diagnostic software in validating correct operation or isolating failure modes:

Bits Description

31:27 Reserved

26 Exchanged (X): When set to one this bit indicates a COMINIT signal was

received. This bit

is reflected in the interrupt register PxIS.PCS.

25 Unreco gnized FIS Type (F): Indicates that one or more FISs were received

by the Transport layer with good CRC, but had a type field that was not

recognized.

24 Transport state transition error (T): Indicates that an error has occurred in

the tr ansition from one state to another with in the T r ansport layer sin ce the last

time this bit was cleared.

23 Link Sequence Error (S): Indicates that one or more Link state machine

error conditions was encountered. The Link Layer state machine defines the

conditions under which t he link layer detects an erroneous transition.

22 Handshak e Erro r (H ) : Indicates that one or more R_ERR handshake

response was received in response to frame transmission. Such errors may be

the result of a CRC error detected by the recipient, a disparity or 8b/10b

decoding error, or other error condition leading to a negative handshake on a

transmitted frame.

21 CRC Error (C): Indicate s that one or more CRC errors occurred with the Link

Layer.

20 Disparity Error (D): This field is not used by AHCI.

19 10b to 8b Decode Error (B): Indicates that one or more 10b to 8b decoding

errors occurred.

18 Comm Wake (W): Indicates that a Comm Wake signal was detected by the

Phy.

17 Phy Internal Error (I): Indicates that the Phy detected some internal error.

16 PhyRdy Change (N): When set to 1 this bit in dicates that the internal Ph yRdy

signal changed state since the last time this bit was cleared. In the ICH8, this

bit will be set when PhyRdy changes from a 0 -> 1 or a 1 -> 0. The state of this

bit is then reflected in the PxIS.PRCS interrupt status bit and an interru pt will

be generated if enabled. Software clears this bit by writing a 1 to it.

SATA Controller Registers (D31:F5)

562 Intel® ICH8 Family Datasheet

15:0

Error (ERR) — R/WC. The ERR field contains error information for use by host

software in determining the appropriate response to the error condition.

If one or more of bits 11:8 of this register are set, the controller will stop the current

transfer.

Bits Description

15:12 Reserved

11 Internal Error (E): The SATA controller fai led due t o a m ast er or targe t abort

when attempting to access system memory.

10 Proto col Error (P): A violation of the Serial ATA protocol was detected.

Note: The ICH8 does not set this bit for all protocol violations that may occur on

the SATA link.

9 Persistent Communication or Data Integrity Error (C): A communication

error that was not recovered occurred that is expected to be persistent.

Persistent communications errors may arise from faulty interconnect with the

device, from a device that has been removed or has failed, or a number of

other causes.

8 Transient Data Integrity Error (T): A data integrity error occurred that was

not recovered by the interface.

7:2 Reserved

1Recovered Communications Error (M): Communications between the

device and host was temporarily lost but was re-established. This can arise

from a device temporarily being removed, from a temporary loss of Phy

synchronization, or from other causes and may be derived from the PhyNRdy

signal between the Phy and Link layers.

0Recovered Data Integrity Error (I): A data integrity er ror occurred that was

recovered by the interface through a retry operation or other recovery action.

Bit Description

Intel® ICH8 Family Datasheet 563

SATA Controller Registers (D31:F5)

13.3 Serial ATA Index/Data Pair Superset Registers

All of these I/O registers are in the core well. They are exposed only when CC.SCC is

01h (i.e. IDE programming interface) and the controller is not in combined mode.

These are Index/Data Pair registers that are used to access the SerialATA superset

registers (SerialATA Status, SerialATA Control and SerialATA Error). The I/O space for

these registers is allocated through SIDPBA. Locations with offset from 08h to 0Fh are

reserved for future expansion. Software- write operations to the reserved locations shall

have no effect while software-read operations to the reserved locations shall return 0.

13.3.1 SINDX—SATA Index Register (D31:F5)

Address Offset: SIDPBA + 00h Attribute: R/W

Default Value: 00000000h Size: 32 bits

Note: These are Index/Data Pair Registers that are used to access the SSTS, SCTL, and

SERR. The I/O space for these registers is allocated through SIDPBA.

13.3.2 SDATA—SATA Index Data Register (D31:F5)

Address Offset: SIDPBA + 04h Attribute: R/W

Default Value: All bits undefined Size: 32 bits

Note: These are Index/Data Pair Registers that are used to access the SSTS, SCTL, and

SERR. The I/O space for these registers is allocated through SIDPBA.

Bit Description

31:16 Reserved

15:8

Port Index (PIDX)— R/W: This Index field is used to specify the port of the SATA

controller at which the port-specific SSTS, SCTL, and SERR registers are located.

00h = Primary Master ( Port 0)

02h = Secondary Ma ster (Port 1)

All other values are Reserved.

7:0

registers currently being indexed into.

00h = SSTS

01h = SCTL

02h = SERR

All other values are Reserved

Bit Description

31:0

Data (DATA)— R/W: This Data register is a “window” through which data is read or

written to the memory mapped registers. A read or write to this Data register triggers a

corresponding read or write to the memory mapped register pointed to by the Index

Note that a physical register is not actually implemented as the data is actually stored

in the memory mapped registers.

Since this is not a physical register, the “default” value is the same as the default value

of the register po inte d to by Index.

SATA Controller Registers (D31:F5)

564 Intel® ICH8 Family Datasheet

§ §

Intel® ICH8 Family Datasheet 565

UHCI Controllers Registers

14 UHCI Controllers Registers

14.1 PCI Configuration Registers

(USB—D29:F0/F1/F2, D26:F0/F1)

Note: The USB functions may be hidden based on the value of the corresponding bits in the

Function Disable Register (see Chipset Configuration Registers). UHCIs must be

disabled from highest number to lowest within their specific PCI device.

Note: Register address locations that are not shown in Table 130 and should be treated as

Reserved (see Section 6.2 for details).

Table 129. UHCI Controller PCI Configuration Map

UHCI PCI

Device:Function Notes

UHCI #1 D29:F0

UHCI #2 D29:F1

UHCI #3 D29:F2

UHCI #4 D26:F0

UHCI #5 D26:F1

Table 130. UHCI Controller PCI Register Address Map ( USB—D29:F0/F1/ F2, D26:F0/F1)

(Sheet 1 of 2)

Offset Mnemonic Register Name UHCI #1–5

Default Type

00–01h VID Vendor Identification 8086h RO

02–03h DID Device Identificati on See register

description RO

04–05h PCICMD PCI Command 0000h R/W, RO

06–07h PCISTS PCI Status 0280h R/WC, RO

08h RID Revi si on Ide n ti fic ation See register

description RO

09h PI Programming Interface 00h RO

0Ah SCC Sub Class Code 03h RO

0Bh BCC Base Class Code 0Ch RO

0Dh MLT Master Latency Timer 00h RO

0Eh HEADTYP Header Type See regi ster

description RO

20–23h BASE Base Address 00000001h R/W, RO

2C–2Dh SVID Subsystem Vendor Identification 0000h R/WO

2E–2Fh SID Subsystem Identification 0000h R/WO

3Ch INT_LN Interrupt Line 00h R/W

UHCI Controllers Registers

566 Intel® ICH8 Family Datasheet

NOTE: Refer to the Intel® ICH8 Family Specification Update for the value of the Revision ID

14.1.1 VID—Vendor Identification Register

(USB—D29:F0/F1/F2, D26:F0/F1)

Address Offset: 00h–01h Attribute: RO

Default Value: 8086h Size: 16 bits

14.1.2 DID—Device Identification Register

(USB—D29:F0/F1/F2, D26:F0/F1)

Address Offset: 02h–03h Attribute: RO

Default Value: See bit description Size: 16 bits

3Dh INT_PN Interrupt Pin See register

description RO

60h USB_RELNUM Serial Bus Release Number 10h RO

C0–C1h USB_LEGKEY USB Legacy K ey board/Mouse Control 2000h R/W, RO

R/WC

C4h USB_RES USB Resume Enable 00h R/W

C8h CWP Core Well Policy 00h R/W

Table 130. UHCI Controller PCI Register Addre ss Map (USB—D2 9:F 0/F 1/ F2, D2 6:F0/F1)

(Sheet 2 of 2)

Offset Mnemonic Register Name UHCI #1–5

Default Type

Bit Description

15:0 Vendor ID — RO. This is a 16-bit value assigned to Intel

Bit Description

15:0 Device ID — RO. This is a 16 -bit value assigned to the Intel® ICH8 USB universal host

controllers. Refer to the Intel ICH8 Family Specification Update for the value of the

Device ID Register.

Intel® ICH8 Family Datasheet 567

UHCI Controllers Registers

14.1.3 PCICMD—PCI Command Register (USB—D29:F0/F1/F2,

D26:F0/F1)

Address Offset: 04h–05h Attribute: R/W, RO

Default Value: 0000h Size: 16 bits

Bit Description

15:11 Reserved

Interrupt Disable — R/W.

0 = Enable. The function is able to generate its interrupt to the interrupt controller.

1 = Disable. The function is not capable of generating interrupts.

NOTE: The corresponding Interrupt Status bit is not affected by the interrupt enable.

9 Fast Back to Back Enable (FBE) — RO. Hardwired to 0.

8 SERR# Enable — RO. Reserved as 0.

7 Wait Cycle Control (WCC) — RO. Hardwired to 0.

6 Parity Error Response (PER) — RO. Hardwired to 0.

5 VGA Palette Snoop (VPS) — RO. Hardwired to 0.

4 Postable Memory Write Enable (PMW E) — RO. Hardwired to 0.

3 Special Cycle Enable (SCE) — RO. Hardwired to 0.

2Bus Master Enable (BME) — R/W.

0 = Disable

1 = Enable. ICH8 can act as a master on the PCI bus for USB transfers.

1 Memory Space Enable (MSE) — RO. Hardwired to 0.

I/O Space Enable (IOSE) — R/W. This bit controls acc ess to the I/O space regi ster s.

0 = Disable

1 = Enable accesses to the USB I/O registers. The Base Address register for USB should

be programmed before this bit is set.

UHCI Controllers Registers

568 Intel® ICH8 Family Datasheet

14.1.4 PCISTS—PCI Status Register

(USB—D29:F0/F1/F2, D26:F0/F1)

Address Offset: 06h–07h Attribute: R/WC, RO

Default Value: 0280h Size: 16 bits

Note: For the writable bits, software must write a 1 to clear bits that are set. Writing a 0 to

the bit has no effect.

14.1.5 RID—Revision Identification Register

(USB—D29:F0/F1/F2, D26:F0/F1)

Offset Address: 08h Attribute: RO

Default Value: See bit description Size: 8 bits

Bit Description

Detected Parity Error (DPE) — R/WC.

0 = No parity error detected.

1 = Set when a data parity error data parity error is detected on writes to the UHCI

14 Reserved as 0b. Read Only.

13 Received Master Abort (RMA) — R/WC.

0 = No master abort generated by USB.

1 = USB, as a master, generated a master abort.

12 Reserved. Always read as 0.

Signaled Target Abort (STA) — R/WC .

0 = ICH8 did Not terminate transaction for USB function with a target abort.

1 = USB function is targeted with a transaction that the ICH8 terminates with a target

abort.

10:9 DEVSEL# Timing Status (DEV_STS) — RO. This 2-bit field defines the timing for

DEVSEL# assertion. These read only bits indicate the ICH8's DEVSEL# timing when

performing a positive decode. ICH8 generates DEVSEL# with medium timing for USB.

8 Data Parity Error Detected (DPED) — RO. Hardwired to 0.

7 Fast Back to Back Capable (FB2BC) — RO. Hardwired to 1.

6 User Definable Features (UDF) — RO. Hardwired to 0.

5 66 MHz Capable — RO. Hardwired to 0.

4 Capabilities List — RO. Hardwired to 0.

Interrupt Status — RO. This bit reflects the state of this function’s interrupt at the

input of the enable/disable logic.

0 = Interrupt is deasserted.

1 = Interrupt is asserted.

The value reported in this bit is independent of the value in the Interrupt Enable bit.

2:0 Reserved

Bit Description

7:0 Revision ID — RO . Refer to the Intel® I/O Controller Hub 8 (ICH8) Family Specification

Update for the value of the Revision ID Register

Intel® ICH8 Family Datasheet 569

UHCI Controllers Registers

14.1.6 PI—Programming Interface Register

(USB—D29:F0/F1/F2, D26:F0/F1)

Address Offset: 09h Attribute: RO

Default Value: 00h Size: 8 bits

14.1.7 SCC—Sub Class Code Register

(USB—D29:F0/F1/F2, D26:F0/F1)

Address Offset: 0Ah Attribute: RO

Default Value: 03h Size: 8 bits

14.1.8 BCC—Base Class Code Register

(USB—D29:F0/F1/F2, D26:F0/F1)

Address Offset: 0Bh Attribute: RO

Default Value: 0Ch Size: 8 bits

14.1.9 MLT—Master Latency Timer Register

(USB—D29:F0/F1/F2, D26:F0/F1)

Address Offset: 0Dh A ttribute: RO

Default Value: 00h Size: 8 bits

Bit Description

7:0 Programming Interface — RO.

00h = No specific register level programming interface define d.

Bit Description

7:0 Sub Class Code (SCC) — RO.

03h = USB host controller.

Bit Description

7:0 Base Class Code (BCC) — RO.

0Ch = Serial Bus controller.

Bit Description

7:0 Master Latency Timer (MLT) — RO. The USB controller is implemented internal to the

ICH8 and not arbitrated as a PCI device. Therefore the device does not require a

Master Latency Timer.

UHCI Controllers Registers

570 Intel® ICH8 Family Datasheet

14.1.10 HEADTYP—Header Type Register

(USB—D29:F0/F1/F2, D26:F0/F1)

Address Offset: 0Eh Attribute: RO

Default Value: See Bit Description Size: 8 bits

For UH CI #2, 3, and 5 this register is hardwired to 00h. For UHCI #1 and UHCI #4,

bit 7 is determined by the v alues in the USB Function Disable bits (11:8 of the Function

Disable register Chipset Configuration Registers:Offset 3418h).

14.1.11 BASE—Base Address Register

(USB—D29:F0/F1/F2, D26:F0/F1)

Address Offset: 20h–23h Attribute: R/W, RO

Default Value: 00000001h Size: 32 bits

14.1.12 SVID — Subsystem Vendor Identification Register

(USB—D29:F0/F1/F2, D26:F0/F1)

Address Offset: 2Ch–2Dh Attribute: R/WO

Default Value: 0000h Size: 16 bits

Lockable: No Power Well: Core

Bit Description

Multi-Function Device — RO. Since the upper functions in this device can be

individually hidden, this bit is based on the function-disable bits in Chipset Config

Space: Offset 3418h as follows:

0 = Single-function device. (Default for UHCI #2,3 and5)

1 = Multi-function device. (Default for UHCI #1 and 4)

6:0 Configuration Layout. Hardwired to 00h, which indicates the standard P CI configurati on

layout.

Bit Description

31:16 Reserved

15:5 Base Address — R/W. Bits [15:5] correspond to I/O address signals AD [15:5],

respectively. This gives 32 bytes of relocatable I/O space.

4:1 Reserved

0Resource Type Indicator (RTE) — RO. Hardwired to 1 to indicate that the base address

field in this register maps to I/O space.

Bit Description

15:0

Subsystem Vendor ID (SVID) — R/WO. BIOS sets the value in this register to identify

the Subsystem Vendor ID. The USB_SVID register, in combination with the USB

Subsystem ID register, enables the operating system to distinguish each subsystem

from the others.

NOTE: The software can write to this register only once per core well reset. Writes

should be done as a single, 16-bit cycle.

Intel® ICH8 Family Datasheet 571

UHCI Controllers Registers

14.1.13 SID — Subsystem Identification Register

(USB—D29:F0/F1/F2/F3, D26:F0/F1)

Address Offset: 2Eh–2Fh Attribute: R/WO

Default Value: 0000h Size: 16 bits

Lockable: No Power Well: Core

14.1.14 INT_LN—Interrupt Line Register

(USB—D29:F0/F1/F2, D26:F0/F1)

Address Offset: 3Ch Attribute: R/W

Default Value: 00h Size: 8 bits

14.1.15 INT_PN—Interrupt Pin Register

(USB—D29:F0/F1/F2/F3, D26:F0/F1)

Address Offset: 3Dh Attribute: RO

Default Value: See Description Size: 8 bits

Bit Description

15:0

Subsystem ID (SID ) — R/WO. BIOS sets the value in this register to identify the

Subsystem ID. The SID r egi st er, in combination with t h e SVID re gis ter (D2 9:F 0/F 1/ F2,

D26:F0/F1:2C), enables the operating system to distin guish each subsystem from

other(s). The v alue read in this register is the same as what was written to the IDE_SID

NOTE: The software can write to this register only once per core well reset. Writes

should be done as a single, 16-bit cycle.

Bit Description

7:0 Interrupt Line (INT_LN) — RO. This data is not used by the ICH8. It is to

communicate to software the interrupt line that the interrupt pin is connected to.

Bit Description

7:0

Interrupt Line (INT_LN) — RO. This value tells the software which interrupt pin each

USB host controller uses. The upper 4 bits are hardwired to 0000b; the lower 4 bits are

determine by the Interrupt Pin default values that are programmed in the memory-

mapped configuration space as follows:

UHCI #1 - D29IP.U0P (Chipset Config Registers:Offset 3108:bits 3:0)

UHCI #2 - D29IP.U1P (Chipset Config Registers:Offset 3108:bits 7:4)

UHCI #3 - D29IP.U2P (Chipset Config Registers:Offset 3108:bits 11:8)

UHCI #4 - D26IP.U0P (Chipset Config Registers:Offset 3114:bits 3:0)

UHCI #5 - D26IP.U1P (Chipset Config Registers:Offset 3114:bits 7:4)

NOTE: This does not determine the mapping to the PIRQ pins.

UHCI Controllers Registers

572 Intel® ICH8 Family Datasheet

14.1.16 USB_RELNUM—Serial Bus Release Number Register

(USB—D29:F0/F1/F2, D26:F0/F1)

Address Offset: 60h Attribute: RO

Default Value: 10h Size: 8 bits

14.1.17 USB_LEGKEY—USB Legacy Keyboard/Mouse Control

Address Offset: C0h–C1h Attribute: R/W, R/WC, RO

Default Value: 2000h Size: 16 bits

This register is implemented separately in each of the USB UHCI functions. However,

the enable and status bits for the trapping logic are OR’d and shared, respectively,

since their functionality is not specific to any one host controller.

Bit Description

7:0 Serial Bus Release Number — RO.

10h = USB controller supports the USB Specification, Release 1.0.

Bit Description

SMI Caused by End of Pass-Through (SMIBYENDPS) — R/WC. This bit indicates if

the event occurred. Note that even if the corresponding enable bit is not set in bit 7,

then this bit will still be active. It is up to the SMM code to use the enable bit to

determine the exact cause of the SMI#.

0 = Software clears this bit by writing a 1 to the bit location in any of the controllers.

1 = Event Occurred

14 Reserved

PCI Interrupt Enable (USBPIRQEN) — R/W. This bit is used to prevent the USB

controller from generating an in terrupt due to transactions on its ports. Note that, when

disabled, it will probably be configured to generate an SMI using bit 4 of this register.

Default to 1 for compatibility with older USB software.

0 = Disable

1 = Enable

SMI Caused by USB Interrupt (SMIBYUSB) — RO. This bit indicates if an interrupt

event occ urred from this con troller. The interrupt from the control ler is taken before the

enable in bit 13 has any effect to create this read-only bit. Note that even if the

corresponding enable bit is not set in Bit 4, this bit may still be active. It is up to the

SMM code to use the enable bit to determine the exact cause of the SMI#.

0 = Software shoul d clear the interrupts via the USB controllers. Writing a 1 to this bit

will have no effect.

1 = Event Occurred.

SMI Caused by Port 64 Write (TRAPBY64W) — R/ WC. This bit indicates if the event

occurred. Note that even if the corresponding enable bit is not set in bit 3, this bit will

still be active. It is up to the SMM code to use the enable bit to de termine the exact

cause of the SMI#. Note that the A20Gate Pass-Through Logic allows specific port 64h

writes to complete without setting this bit.

0 = Software clears this bit by writing a 1 to the bit location in any of the controllers.

1 = Event Occurred.

Intel® ICH8 Family Datasheet 573

UHCI Controllers Registers

SMI Caused by Port 64 Read (T RA PBY6 4R) — R/ WC. This bit indic ates i f the ev e nt

occurred. Note that even if the corresponding enable bit is not set in bit 2, this bit will

still be active. It is up to the SMM code to use the enable bit to determine th e exact

cause of the SMI#.

0 = Software clears this bit by writing a 1 to the bit location in any of the controllers.

1 = Event Occurred.

SMI Caused by Po rt 60 Write (TRAPBY60W) — R/WC. This bit indicates if the ev ent

occurred. Note that even if the corresponding enable bit is not set in bit 1, this bit will

still be active. It is up to the SMM code to use the enable bit to determine th e exact

cause of the SMI#. Note that the A20Gate Pass-Through Logic allows specific port 64h

writes to complete without setting this bit.

0 = Software clears this bit by writing a 1 to the bit location in any of the controllers.

1 = Event Occurred.

SMI Caused by Port 60 Read ( TRAPBY60R) — R/WC. This bit indicates if the event

occurred. Note that even if the corresponding enable bit is n ot set in the bit 0, then this

bit will still be active. It is up to the SMM code to use the enable bit to determine the

exact cause of the SMI#.

0 = Software clears this bit by writing a 1 to the bit location in any of the controllers.

1 = Event Occurred.

SMI at End of Pass-Through Enable (SMIATENDPS) — R/W. This bit enables SMI

at the end of a pass-through. This can occur if an SMI is generated in the middle of a

pass-through, and needs to be serviced later.

0 = Disable

1 = Enable

Pass Through State (PSTATE) — RO.

0 = If software needs to reset this bit, it should set bit 5 in all of the host controllers to

1 = Indicates that the state machine is in the middle of an A2 0GATE pass-through

sequence.

A20Gate Pass-Through Enable (A20PASSEN) — R/W.

0 = Disable.

1 = Enable. Allows A20GA TE sequence Pass-Through function. A spec ific cycle sequence

involving writes to port 60h and 64h does not result in the setting of the SMI status

bits.

4SMI on USB IRQ Enable (USBSMIEN) — R/W.

0 = Disable

1 = Enable. USB interrupt will cause an SMI event.

3SMI on Port 64 Writes Enable (64WEN) — R/W.

0 = Disable

1 = Enable. A 1 in bit 1 1 will cause an SMI even t.

2SMI on Port 64 Reads Enable (64REN) — R/W.

0 = Disable

1 = Enable. A 1 in bit 1 0 will cause an SMI even t.

1SMI on Port 60 Writes Enable (60WEN) — R/W.

0 = Disable

1 = Enable. A 1 in bit 9 will cause an SMI event.

0SMI on Port 60 Reads Enable (60REN) — R/W.

0 = Disable

1 = Enable. A 1 in bit 8 will cause an SMI event.

Bit Description

UHCI Controllers Registers

574 Intel® ICH8 Family Datasheet

14.1.18 USB_RES—USB Resume Enable Register

(USB—D29:F0/F1/F2, D26:F0/F1)

Address Offset: C4h Attribute: R/W

Default Value: 00h Size: 8 bits

14.1.19 CWP—Core Well Policy Register

(USB—D29:F0/F1/F2, D26:F0/F1)

Address Offset: C8h Attribute: R/W

Default Value: 00h Size: 8 bits

Bit Description

7:2 Reserved

PORT1EN — R/W. Enable port 1 of the USB controller to respond to wakeup events.

0 = The USB controller will not look at this port for a wakeup event.

1 = The USB controller will monitor this port for remote wakeup and connect/

disconnect events.

PORT0EN — R/W. Enable port 0 of the USB controller to respond to wakeup events.

0 = The USB controller will not look at this port for a wakeup event.

1 = The USB controller will monitor this port for remote wakeup and connect/

disconnect events.

Bit Description

7:1 Reserved

Static Bus Master Status Policy Enable (SBMSPE) — R/W.

0 = The UHCI host controller dynam ically sets the Bus Master status bit (Power

Management 1 Statu s Register,[PMBASE+00h], bit 4) based on the memory

accesses that are scheduled. For mobile components, the default setting provides a

more accurate indication of snoopable memory accesses in order to help with

software-invoked entry to C3 and C4 power states.

1 = The UHCI host controller statically forces the Bus Master Status bit in power

management space to 1 whenever the HCHalted bit (USB Status Register,

Base+02h, bit 5) is cleared.

NOTE: The PCI Power Management registers are enabled in the PCI Device 31:

Function 0 space (PM_IO_EN), and can be moved to any I/O location (128-byte

aligned).

Intel® ICH8 Family Datasheet 575

UHCI Controllers Registers

14.2 USB I/O Registers

Some of the read/write register bits that deal with changing the state of the USB hub

ports function such that on read back they reflect the current state of the port, and not

necessarily the state of the last write to the register. This allows the software to poll the

state of the port and wait until it is in the proper state before proceeding. A host

controller reset, global reset, or port reset will immediately terminate a transfer on the

affected ports and disable the port. This affects the USBCMD register, bit 4 and the

PORTSC registers, bits [12,6,2]. See individual bit descriptions for more detail.

NOTES:

1. These registers are WORD writable only. Byte writes to these registers have unpredictable

effects.

Table 131. USB I/O Registers

BASE +

Offset Mnemonic Register Name Default Type

00–01h USBCMD USB Command 0000h R/W

02–03h USBSTS USB Status 0020h R/WC

04–05h USBINTR USB Interrupt Enable 0000h R/W

06–07h FRNUM Frame Number 0000h R/W (see Note 1)

08–0Bh FRBASEADD Frame List Base Address Undefined R/W

0Ch SOFMOD Start of Frame Modify 40h R/W

0D–0Fh — Reserved — —

10–11h PORTSC0 Port 0 Status/Control 0080h R/WC, RO, R/W

(see Note 1)

12–13h PORTSC1 Port 1 Status/Control 0080h R/WC, RO, R/W

(see Note 1)

UHCI Controllers Registers

576 Intel® ICH8 Family Datasheet

14.2.1 USBCMD—USB Command Register

I/O Offset: BASE + (00h–01h) Attribute: R/W

Default Value: 0000h Size: 16 bits

The Command Register indicates the command to be executed by the serial bus host

controller. Writing to the register causes a command to be executed. Table 132

provides additional information on the operation of the Run/Stop and Debug bits.

Bit Description

15:7 Reserved

Loop Back Test Mode — R/W.

0 = Disable loop back test mode.

1 = ICH8 is in loop back test mode. When both ports are connected togethe r, a write to

one port will be seen on the other port and the data will be stored in I/O offset 18h.

Max Packet (M AX P) — R/W. This bit selects the maximu m packet size that can be

used for full speed bandwidth reclamation at the end of a frame. This value is used by

the host co ntroller to de termine wh ether it should initiate another tr ansaction based on

the time remaining in the SOF counter. Use of reclamation packets larger than the

programmed size will cause a Babble error if executed during the critical window at

frame end. The Babble error results in the offending endpoint being stalled. Software is

responsible for ensuring that any packet which could be executed under bandwidth

reclamation be within this size limit.

0 = 32 bytes

1 = 64 bytes

Configure Flag (CF) — R/W. This bit has no effect on the hardware. It is provided only

as a semaphore service for software.

0 = Indicates that software has not completed host controller configuration.

1 = HCD software sets this bit as the last action in its process of configuring the host

controller.

Software Debug (SWDBG) — R/W. The SWDBG bit must only be manipulated when

the controller is in the stopped state. This can be determined by checking the HCHalted

bit in the USBSTS register.

0 = Normal Mode.

1 = Debug mode. In SW Debug mode, the host controller clears the Run/Stop bit after

the completion of each U SB transaction. The next transaction is executed when

software sets the Run/Stop bit back to 1.

Force Global Resume (FGR) — R/W.

0 = Software resets this bit to 0 after 20 ms has elapsed to stop sending the Global

Resume signal. At that time all USB devices should be ready for bus activity. The 1

to 0 transition causes the po rt to send a low speed EOP signal. This bit will remain

a 1 until the EOP has completed.

1 = Host controller sends the Global Resume signal on the USB, and sets this bit to 1

when a resume event (connect, disconnect, or K-state) is detected while in global

suspend mode.

Enter Global Suspend Mode (EGSM) — R/W.

0 = Software resets this bit to 0 to come out of Global Suspend mode. Software writes

this bit to 0 at the same time that Force Global Resume (bit 4) is written to 0 or

after writing bit 4 to 0.

1 = Host controller en ters the Glo bal S uspen d mode. No USB tr ansactions occur during

this time. The Host contro ller is able to receive resume signals from USB and

interrupt the system. Software must ensure that the Run/Stop bit (bit 0) is cleared

prior to setting this bit.

Intel® ICH8 Family Datasheet 577

UHCI Controllers Registers

Global Re s e t (GRESET) — R/W.

0 = This bit is reset by the software after a minimu m of 10 ms has elaps ed as specifie d

in Chapter 7 of the USB Specificatio n.

1 = Global Reset. The host contr oller sends th e global reset si gnal on the USB and t hen

resets all its logic, including the internal hub registers. The hub registers are reset

to their power on state. Chip Hardware Reset has the same effect as Global Reset

(bit 2), except that the host controller does not send the Global Reset on USB.

Host Controller Reset (HCRESET) — R/W. The effects of HCRESET on Hub registers

are slightly different from Chip Hardware Reset and Global USB Reset. The HCRESET

affects bits [8,3:0] of the Port Status and Control Register (PORTSC) of each port.

HCRESET resets the state machines of the ho st controller including the Connect/

Disconnect state machine (one for ea ch port). When the Connect/Disconnect state

machine is rese t, the output that signals connect/disconnect are negated to 0,

effectively signaling a disconnect, even if a device is attached to the port. This virtual

disconnect causes the port to be disabled. This disconnect and disabling of the port

causes bit 1 (connect status change) and bit 3 (port enable/disable change) of the

PORTSC to get set. The disconnect also causes bit 8 of PORTSC to reset. About 64 bit

times after HCRESET goes to 0, the connect and low-speed detect will take place, and

bits 0 and 8 of the PORTSC will change accordingly.

0 = Reset by the host controller when the reset process is complete.

1 = Re s et . When this bit is set, the host controller module resets its internal timers,

counters, state machines, etc. to their initial value. Any transaction currently in

progress on USB is immediately terminated.

Run/Stop (RS) — R/W. When set to 1, the ICH8 proceeds with execution of the

schedule. The ICH8 continues execution as long as this bit is set. When this bit is

cleared, the ICH8 complete s the current tr ans action on th e USB and then h alts. The HC

Halted bit in the status register indicates when the host controller has finished the

transaction and has entered the stopped state. The host controller clears this bit when

the following fatal errors occur: consistency check failure, PCI Bus errors.

0 = Stop

1 = Run

NOTE: This bit should only be cleared if there are no active Transaction Descriptors in

the executable schedule or software will reset the host controller prior to setting

this bit again.

Bit Description

UHCI Controllers Registers

578 Intel® ICH8 Family Datasheet

When the USB host controller is in Software Debug Mode (USBCMD Register bit 5=1),

the single stepping software debug operation is as follows:

To Enter Software Debug Mode:

1. HCD puts host controller in Stop state by setting the Run/Stop bit to 0.

2. HCD puts host controller in Debug Mode by setting the SWDBG bit to 1.

3. HCD sets up the correct command list and Start Of Fr ame value for starting point in

the Frame List Single Step Loop.

4. HCD sets Run/Stop bit to 1.

5. Host controller executes next active TD, sets Run/Stop bit to 0, and stops.

6. HCD reads the USBCMD register to check if the single step execution is completed

(HCHalted=1).

7. HCD checks results of TD execution. Go to step 4 to execute next TD or step 8 to

end Software De bu g mod e.

8. HCD ends Software Debug mode by setting SWDBG bit to 0.

9. HCD sets up normal command list and Frame List table.

10.HCD sets Run/Stop bit to 1 to resume normal schedule execution.

In Software Debug mode, when the Run/Stop bit is set, the host controller starts.

When a valid TD is found, the Run/Stop bit is reset. When the TD is finished, the

HCHalted bit in the USBSTS register (bit 5) is set.

The SW Debug mode skips over inactive TDs and only halts after an active TD has been

executed. When the last active TD in a frame has been executed, the host controller

waits until the next SOF is sent and then fetches the first TD of the next frame before

halting.

Table 132. Run/Stop, Debug Bit Interaction SWDBG (Bit 5), Run/Stop (Bit 0) Operation

SWDBG

(Bit 5) Run/Stop

(Bit 0) Description

If executing a command, the host controller completes the command

and then stops. The 1.0 ms frame counter is reset and command list

execution resumes from start of frame using the frame list pointer

selected by the current value in the FRNUM register. (While Run/

Stop=0, the FRNUM register (BASE + 06h) can be reprogrammed).

Execution of the command list resumes from Start Of Frame using the

frame list pointer selected by the current value in the FRNUM register.

The host controller remains running until the Run/Stop bit is cleared

(by software or hardware).

If executing a command, the host controller completes the command

and then stops and the 1.0 ms frame counter is frozen at its current

value. All status are preserved. The host controller begins execution

of the command list from where it left off when the Run/Stop bit is

set.

Execution of the command list resumes from where the previou s

execution stopped. The Run/Stop bit is set to 0 by the host controller

when a TD is being fetched. This causes the host controller to stop

again after the executio n of the TD (single step ). When the host

controller has completed execution, the HC Halted bit in the Status

Intel® ICH8 Family Datasheet 579

UHCI Controllers Registers

This HCHalted bit can also be used outside of Software Debug mode to indicate when

the host controller has detected the Run/Stop bit and has completed the current

transaction. Outside of the Softw are Debug mode, setting the Run/Stop bit to 0 always

resets the SOF counter so that when the Run/Stop bit is set the host controller starts

over again from the frame list location pointed to by the Frame List Index (see FRNUM

14.2.2 USBSTS—USB Status Register

I/O Offset: BASE + (02h–03h) Attribute: R/WC

Default Value: 0020h Size: 16 bits

This register indicates pending interrupts and various states of the host controller. The

status resulting from a transaction on the serial bus is not indicated in this register.

Bit Description

15:6 Reserved

HCHalted — R/WC.

0 = Software clears this bit by writing a 1 to it.

1 = The host controller has stopped executing as a result of the Run/Stop bit being set

to 0, either by software or by the host controller hardware (debug mode or an

internal error). Default.

Host Controller Process Error — R/WC.

0 = Software clears this bit by writing a 1 to it.

1 = The host controller has detected a fatal error. This indicates that the host controller

suffered a consistency check failure while processing a Transfer Descriptor. An

example of a consistency check failure would be finding an invalid PID field while

processing the packet header portion of the TD. When this error occurs, the host

controller clears the Run/Stop bit in the Command register (D29:F0/F1/F2,

D26:F0/F1:BASE + 00h, bit 0) to prevent further schedule execution. A hardware

interrupt is generated to the system.

Host System Error — R/WC.

0 = Software clears this bit by writing a 1 to it.

1 = A serious error occurred during a host system access involving the host controller

module. In a PCI system, conditions that set this bit to 1 include PCI Parity error,

PCI Master Abort, and PCI Target Abort. When this error occurs, the host controller

clears the Run/Stop bit in the Command register to prevent further execution of

the scheduled TDs. A hardware interrupt is generated to the system.

Resume Detect (RSM_DET) — R/WC.

0 = Software clears this bit by writing a 1 to it.

1 = The host controller received a “RESUME” signal from a USB device. This is only

valid if the Host controller is in a global suspend state (Command register, D29:F0/

F1/F2, D26:F0/F1:BASE + 00h, bit 3 = 1).

USB Error Interrupt — R/WC.

0 = Software clears this bit by writing a 1 to it.

1 = Completion of a USB transaction resulted in an error condition (e.g., error counter

underflow). If the TD on which the error interrupt occurred also had its IOC bit

(D29:F0/F1/F2, D26:F0/F1:BASE + 04h, bit 2) set, both this bit and Bit 0 are set.

USB Interrupt (USBINT) — R/WC.

0 = Software clears this bit by writing a 1 to it.

1 = The host controller sets this bit when the cause of an interrupt is a completion of a

USB transaction whose Transfer Descriptor had its IOC bit set. Also set when a

short packet is detected (actual length field in TD is less than maximum length field

in TD), and short packet detection is enabled in that TD.

UHCI Controllers Registers

580 Intel® ICH8 Family Datasheet

14.2.3 USBINTR—USB Interrupt Enable Register

I/O Offset: BASE + (04h–05h) Attribute: R/W

Default Value: 0000h Size: 16 bits

This register enables and disables reporting of the corresponding interrupt to the

software. When a bit is set and the corresponding interrupt is active, an interrupt is

generated to the host. Fatal errors (host controller processor error, (D29:F0/F1/F2,

D26:F0/F1:BASE + 02h, bit 4, USBSTS Register) cannot be disabled by the host

controller. Interrupt sources that are disabled in this register still appear in the Status

14.2.4 FRNUM—Frame Number Register

I/O Offset: BASE + (06–07h) Attribute: R/W (Writes must be

Word Writes)

Default Value: 0000h Size: 16 bits

Bits [10:0] of this register contain the current frame number that is included in the

frame SOF packet. This register reflects the count value of the internal frame number

counter. Bits [9:0] are used to select a particular entry in the Frame List during

scheduled execution. This register is updated at the end of each frame time.

This register must be written as a word. Byte w ri tes are not supported. Th is regis t e r

cannot be written unless the host controller is in the ST OPPED state as indicated by the

HCHalted bit (D29:F0/F1/F2/, D26:F0/F1:BASE + 02h, bit 5). A write to this register

while the Run/Stop bit is set (D29:F0/F1/F2/, D26:F0/F1:BASE + 00h, bit 0) is ignored.

Bit Description

15:5 Reserved

4Scratchpad (SP) — R/W.

3Short Packet Interrupt Enable — R/W.

0 = Disabled.

1 = Enabled.

2Interrupt on Complete Enable (IOC) — R/W.

0 = Disabled.

1 = Enabled.

1Resume Interrupt Enable — R/W.

0 = Disabled.

1 = Enabled.

0Timeout/CRC Interrupt Enable — R/W.

0 = Disabled.

1 = Enabled.

Bit Description

15:11 Reserved

10:0

Frame List Current Index/Frame Number — R/W. This field provides the frame

number in the SOF Frame. The value in this register increments at the end of each time

frame (approximately every 1 ms). In addition, bits [9: 0] are used for the Frame List

current index and correspond to memory address signals [11:2].

Intel® ICH8 Family Datasheet 581

UHCI Controllers Registers

14.2.5 FRBASEADD—Frame List Base Address Register

I/O Offset: BASE + (08h–0Bh) Attribute: R/W

Default Value: Undefined Size: 32 bits

This 32-bit register contains the beginning address of the Frame List in the system

memory. HCD loads this register prior to starting the schedule execution by the host

controller. When written, only the upper 20 bits are used. The lower 12 bits are written

as 0’s (4 KB alignment). The contents of this register are combined with the frame

number counter to enable the host controller to step through the Frame List in

sequence. The two least significant bits are always 00. This requires dword-alignment

for all list entries. This configuration supports 1024 Frame List entries.

14.2.6 SOFMOD—Start of Frame Modify Register

I/O Offset: Base + (0Ch) Attribute: R/W

Default Value: 40h Size: 8 bits

This 1-byte register is used to modify the v alue used in the gener ation of SOF timing on

the USB. Only the 7 least significant bits are used. When a new value is written into

these 7 bits, the SOF timing of the next frame will be adjusted. This feature can be

used to adjust out any offset from the clock source that gener ates the clock that driv es

the SOF counter. This register can also be used to maintain real time synchronization

with the rest of the system so that all devices have the same sense of real time. Using

this register, the frame length can be adjusted across the full range required by the

USB specification. Its initial programmed value is system dependent based on the

accuracy of hardware USB clock and is initialized by system BIOS. It may be

reprogrammed by USB system software at any time. Its value will take effect from the

beginning of the next frame. This register is reset upon a host con troller reset or global

reset. Software must maintain a copy of its value for reprogramming if necessary.

Bit Description

31:12 Base Address — R/W. These bits correspond to memory address signals [31:12],

respectively.

11:0 Reserved

Bit Description

7Reserved

6:0

SOF Timing Value — R/W. Guidelines for the modification of frame time are contained

in Chapter 7 of the USB Spec ifi cat ion. The SOF cycle time (number of SOF counter clock

periods to generate a SOF frame length) is equal to 11936 + value in this field. The

default value is decimal 64 which gives a SOF cycle time of 12000. For a 12 MHz SOF

counter clock input, this prod uces a 1 ms Frame period. The following table indicates

what SOF Timing Value to program into this field for a certain frame period.

Frame Length (# 12 MHz

Clocks) (decimal) SOF Timing Value (this register)

(decimal)

11936 0

11937 1

——

11999 63

12000 64

12001 65

——

12062 126

12063 127

UHCI Controllers Registers

582 Intel® ICH8 Family Datasheet

14.2.7 PORTSC[0,1]—Port Status and Control Register

I/O Offset: Port 0/2/4/6/8: BASE + (10h–11h) Attribute:R/WC, RO,

Port 1/3/5/7/9: BASE + (12h–13h) R/W (Word writes only)

Default Value: 0080h Size:16 bits

Note: For UHCI #1 (D29:F0), this applies to ICH8 USB ports 0 and 1; for UHCI #2 (D29:F1),

this applies to ICH8 USB ports 2 and 3; for UHCI #3 (D29:F2), this applies to ICH8 USB

ports 4 and 5, for UHCI #4 (D26:F0), this applies to ICH8 USB ports 6 and 7, and for

UHCI #5 (D26:F1), this applies to ICH8 USB ports 8 and 9.

After a power-up reset, global reset, or host controller reset, the initial conditions of a

port are: no device connected, Port disabled, and the bus line status is 00 (single-

ended 0).

Port Reset and Enable Sequence

When software wishes to reset a USB device it will assert the Port Reset bit in the Port

Status and Control register. The minimum reset signaling time is 10 mS and is enforced

by software. To complete the reset sequence, software clears the port reset bit. The

Intel UHCI controller must re-detect the port connect after reset signaling is complete

before the controller will allow the port enable bit to de set by software. This time is

approximately 5.3 uS. Software has several possible options to meet the timing

requirement and a partial list is enumerated below:

• Iterate a short wait, setting the port enable bit and reading it back to see if the

enable bit is set.

• Poll the connect status bit and wait for the hardw are to recognize the connect prior

to enabling the port.

• W ait longer than the hardware detect time after clearing the port reset and prior to

enabling the port.

Intel® ICH8 Family Datasheet 583

UHCI Controllers Registers

Bit Description

15:13 Reserved — RO.

Suspend — R/W. This bit should not be written to a 1 if global suspend is active

(bit 3=1 in the USBCMD register). Bit 2 and bi t 12 of this regi ster define the hub sta tes

as follows:

When in suspend state, downstream propagation of data is blocked on this port, except

for single-ended 0 resets (global reset and port reset). The blocking occurs at the end

of the current transaction, if a transaction was in progress when this bit was written to

1. In the suspend state, the port is sensitive to resume detection. Note that the bit

status does not change until the port is suspended and that there may be a delay in

suspending a port if there is a transaction currently in progress on the USB.

1 = Port in suspend state.

0 = Port not in suspend state.

NOTE: Normally, if a transaction is in progress when this bit is set, the port will be

suspended when the c urrent transaction completes. However, in the case of a

specific error condition (out transaction with babble), the ICH8 may issue a

start-of-frame, and then suspend the port.

11 Overcurrent Indica to r — R/WC. Set by hardware.

0 = Software clears this bit by writing a 1 to it.

1 = Overcurrent pin has gone from inactive to active on this port.

10 Overcurrent Active — RO. This bit is set and cleared by hardware.

0 = Indicates that the overcurrent pin is inactive (high).

1 = Indicates that the overcurrent pin is active (low).

9Port Reset — R/W.

0 = Port is not in Reset.

1 = Port is in Reset. When set, the port is disabled and sends the USB Reset signaling.

8Low Speed Device Attached (LS) — RO.

0 = Full speed device is attached.

1 = Low speed device is attached to this port.

7 Reserved — RO. Always read as 1.

Resume Detect (RSM_DET) — R/W. Software sets this bit to a 1 to drive resume

signaling. The host controller sets this bit to a 1 if a J-to-K transition is detected for at

least 32 microseconds while the port is in the Suspend state. The ICH8 will then reflect

the K-state back onto the bus as long as the bit remains a 1, and the port is still in the

suspend state (bit 12,2 are ‘11’). Writing a 0 (from 1) causes the port to send a low

speed EOP. This bit will remain a 1 until the EOP has completed.

0 = No resume (K-state) dete cted/driven on port.

1 = Resume detected/driven on port.

5:4 Line Status — RO. These bits reflect the D+ (bit 4) and D– (bit 5) signals lines’ logical

levels. These bits are used for fault detect and recovery as well as for USB diagnostics.

This field is updated at EOF2 time (See Chapter 11 of the USB Specification).

Port Enable/Disable Change — R/WC. F or the root hub, this bit gets set only when a

port is disabled due to disconnect on that port or due to the appropriate conditions

existing at the EOF2 point (See Chapter 11 of the USB Specification).

0 = No change. Software clears this bit by writing a 1 to the bit location.

1 = Port enabled/disabled status has changed.

Bits [12,2] Hub State

X,0 Disable

0, 1 Enable

1, 1 Suspend

UHCI Controllers Registers

584 Intel® ICH8 Family Datasheet

§ §

Port Enabled/Disabled (PORT_EN) — R/W. Ports can be enabled by host software

only. Ports can be disabled by either a fault condition (dis connect event or other faul t

condition) or by host software. Note that the bit status does not change until the port

state actually changes and that there may be a delay in disabling or enabling a port if

there is a transaction currently in progress on the USB.

0 = Disable

1 = Enable

Connect Status Change — R/WC. This bi t indicates that a change has oc curred in the

port’s Current Connect Status (see bit 0). The hub device sets this bit for any changes

to the port device connect status, even if system software has not cleared a connect

status change. If, for example, the insertion status changes twice before system

software has cleared the changed condition, hub hardware will be setting” an already-

set bit (i.e., the bit will remain set). However, the hub transfers the change bit only

once when the host controller requests a data transfer to the Status Change endpoint.

System software is responsible for determining state change history in such a case.

0 = No change. Software clears this bit by writing a 1 to it.

1 = Change in Current Connect Status.

Current Connect Status — RO. This value reflects the current state of the port, and

may not correspond directly to the event that caused the Connect Status Change bit

(Bit 1) to be set.

0 = No device is present.

1 = Device is present on port.

Bit Description

Intel® ICH8 Family Datasheet 585

EHCI Controller Registers (D29:F7, D26:F7)

15 EHCI Controller Registers

(D29:F7, D26:F7)

15.1 USB EHCI Configuration Registers

(USB EHCI—D29:F7, D26:F7)

Note: Register address locations that are not shown in Table 133 should be treated as

Reserved (see Section 6.2 for details).

Table 133. USB EHCI PCI Register Address Map (USB EHCI—D29:F7, D26:F7) (Sheet 1 of

Offset Mnemonic Register Name Default Type

00h–01h VID Vendor Identification 8086h RO

02h–03h DID Device Identification See regist er

description RO

04h–05h PCICMD PCI Command 0000h R/W, RO

06h–07h PCISTS PCI Status 0290h R/W, RO

08h RID Revision Identification See register

description RO

09h PI Programming Interface 20h RO

0Ah SCC Sub Class Code 03h RO

0Bh BCC Base Class Code 0Ch RO

0Dh PMLT Primary Master Latency Timer 00h RO

10h–13h MEM_BASE Memory Base Address 00000000h R/W, RO

2Ch–2Dh SVID USB EHCI Subsystem Vendor

Identification XXXXh R/W

(special)

2Eh–2Fh SID USB EHCI Subsystem Identification XXXXh R/W

(special)

34h CAP_PTR Capabilities Pointer 50h RO

3Ch INT_LN Interrupt Line 00h R/W

3Dh INT_PN Interrupt Pin See register

description RO

50h PWR_CAPID PCI Power Management Capability

ID 01h RO

51h N XT_PTR1 Next Item Pointer 58h R/W

(special)

52h–53h PWR_CAP Power Management Capabilities C9C2h R/W

(special)

54h–55h PWR_CNTL_STS Power Management Control/Status 0000h R/W , R/WC,

58h DEBUG_CAPID Debug Port Capability ID 0Ah RO

59h N XT_PTR2 Next Item Pointer #2 00h RO

EHCI Controller Registers (D29:F7, D26:F7)

586 Intel® ICH8 Family Datasheet

Note: All configuration registers in this section are in the core well and reset by a core well

reset and the D3-to-D0 warm reset, except as noted.

15.1.1 VID—Vendor Identification Register

(USB EHCI—D29:F7, D26:F7)

Offset Address: 00h–01h Attribute: RO

Default Value: 8086h Size: 16 bits

15.1.2 DID—Device Identification Register

(USB EHCI—D29:F7, D26:F7)

Offset Address: 02h–03h Attribute: RO

Default Value: See bit description Size: 16 bits

5Ah–5Bh DEBUG_BASE Debug Port Base Offset 20A0h RO

60h USB_RELNUM USB Release Number 20h R O

61h FL_ADJ Frame Length Adjustment 20h R/W

62h–63h PWAKE_CAP Port Wake Capabilities 01FFh R/W

64h–67h — Reserved — —

68h–6Bh LEG_EXT_CAP USB EHCI Legacy Support Extended

Capability 00000001h R/W, RO

6Ch–6Fh LEG_EXT_CS USB EHCI Legacy Extended Support

Control/Status 00000000h R/W , R/WC,

70h–73h SPECIAL_SMI Intel Specific USB 2.0 SMI 00000000h R/W, R/WC

74h–7Fh — Reserved — —

80h ACCESS_CNTL Access Control 00h R/W

84h EHCIIR1 EHCI Initialization Register 1

(Mobile Only) 01h R/W, R/WL

FC–FFh EHCIIR2 EHCI Initialization Register 2 20001706 R/W

Table 133. USB EHCI PCI Register Address Map (USB EHCI—D29:F7, D26:F7) (Sheet 2 of

Offset Mnemonic Register Name Default Type

Bit Description

15:0 Vendor ID — RO. This is a 16-bit value assigned to Intel.

Bit Description

15:0 Device ID — RO. This is a 16-bit value assigned to the Intel® ICH8 USB EHCI

controller. Refer to the Intel ICH8 Family Specification Update for the value of the

Device ID Register.

Intel® ICH8 Family Datasheet 587

EHCI Controller Registers (D29:F7, D26:F7)

15.1.3 PCICMD—PCI Command Register

(USB EHCI—D29:F7, D26:F7)

Address Offset: 04h–05h Attribute: R/W, RO

Default Value: 0000h Size: 16 bits

Bit Description

15:11 Reserved

Interrupt Disable — R/W.

0 = The function is capable of generating inte rru pts .

1 = The function can not generate its interrupt to the interrupt controller.

Note that the corresponding Interrupt Status bit (D29:F7, D26:F7:06h, bit 3) is not

affected by the interrupt enable.

9 Fast Back to Back Enable (FBE) — RO. Hardwired to 0.

SERR# Enable (SERR_EN) — R/W.

0 = Disables EHC’s capability to generate an SERR#.

1 = The Enhanced Host controller (EHC) is capable of generating (internally) SERR#

when it receive a completion status other than “successful” for one of its DMA-

initiated memory reads on DMI (and subsequently on its internal interface).

7 Wait Cycle Control (WCC) — RO. Hardwired to 0.

6 Parity Error Response (PER) — RO. Hardwired to 0.

5 VGA Palette Snoop (VPS) — RO. Hardwired to 0.

4 Postable Memory Write Enable (PMW E) — RO. Hardwired to 0.

3 Special Cycle Enable (SCE) — RO. Hardwired to 0.

2Bus Master Enable (BME) — R/W.

0 = Disables this functionality.

1 = Enables the ICH8 to act as a master on the PCI bus for USB transfers.

Memory Space Enable (MSE) — R/W. This bit controls access to the USB 2.0 Memory

Space registers.

0 = Disables this functionality.

1 = Enables accesse s to the USB 2.0 registers. The Base Address regi ster (D29:F7,

D26:F7:10h) for USB 2.0 should be programmed before this bit is set.

0 I/O Space Enable (IOSE) — RO. Hardwired to 0.

EHCI Controller Registers (D29:F7, D26:F7)

588 Intel® ICH8 Family Datasheet

15.1.4 PCISTS—PCI Status Register

(USB EHCI—D29:F7, D26:F7)

Address Offset: 06h–07h Attribute: R/W, RO

Default Value: 0290h Size: 16 bits

Note: For the writable bits, software must write a 1 to clear bits that are set. Writing a 0 to

the bit has no effect.

Bit Description

15 Detected Parity Error (DPE) — RO. Hardwired to 0.

Signaled System Error (SSE) — R/W.

0 = No SERR# signaled by ICH8.

1 = This bit is se t by the ICH8 when it signals SERR# (internally). The SER_EN bit (bit

8 of the Command Register) must be 1 for this bit to be set.

Received Master Abort (RMA) — R/W.

0 = No master abort received by EHC on a memory access.

1 = This bit is set when EHC, as a master, receives a master abort status on a memory

access. This is treated as a Host Error and halts the DMA engines. This event can

optionally generate an SERR# by setting the SERR# Enable bit.

Received Target Abort (RTA) — R/W.

0 = No target abort received by EHC on memory access.

1 = This bit is set when EHC, as a master, receives a target abort status on a memory

access. This is treated as a Host Error and halts the DMA engines. This event can

optionally generate an SERR# by setting the SERR# Enable bit (D29:F7,

D26:F7:04h, bit 8).

Signaled Target Abort (STA) — RO. This bit is used to indicate when the EHCI function

responds to a cycle with a target abort. There is no reason for this to happen, so this bit

will be

hardwired to 0.

10:9 DEVSEL# Timing Status (DEVT_STS) — RO. This 2-bit field defines the timing for

DEVSEL# assertion.

Master Data Parity Error Detected (DPED) — R/W.

0 = No data parity error detected on USB2.0 read completion packet.

1 = This bit is set by the ICH8 when a data parity error is detected on a USB 2.0 read

completion packet on the internal interface to the EHCI host controller and bit 6 of

the Command register is set to 1.

7 Fast Back to Back Capable (FB2BC) — RO. Hardwired to 1.

6 User Definable Features (UDF) — RO. Hardwired to 0.

5 66 MHz Capable (66 MHz _CAP) — RO. Hardwired to 0.

4Capabilities List (CAP_LIST) — RO. Hardwired to 1 indica ting that offset 34h contains a

valid capabilities pointer.

Interrupt Status — RO. This bit reflects the state of this function’s interrupt at the

input of the enable/disable logic.

0 = This bit will be 0 when the interrupt is deasserted.

1 = This bit is a 1 when the interrupt is asserted.

The value reported in this bit is independent of the value in the Interrupt Enable bit.

2:0 Reserved

Intel® ICH8 Family Datasheet 589

EHCI Controller Registers (D29:F7, D26:F7)

15.1.5 RID—Revision Identification Register

(USB EHCI—D29:F7, D26:F7)

Offset Address: 08h Attribute: RO

Default Value: See bit description Size: 8 bits

15.1.6 PI—Programming Interface Register

(USB EHCI—D29:F7, D26:F7)

Address Offset: 09h Attribute: RO

Default Value: 20h Size: 8 bits

15.1.7 SCC—Sub Class Code Register

(USB EHCI—D29:F7, D26:F7)

Address Offset: 0Ah Attribute: RO

Default Value: 03h Size: 8 bits

15.1.8 BCC—Base Class Code Register

(USB EHCI—D29:F7, D26:F7)

Address Offset: 0Bh Attribute: RO

Default Value: 0Ch Size: 8 bits

Bit Description

7:0 R evision ID — RO. Refer to the Intel® I/O Controll er Hub 8 (ICH8) Family Specification

Update for the value of the Revision ID Register

Bit Description

7:0 Programming Inte rface — RO. A v alue of 20h indica tes that this USB 2.0 host controller

conforms to the EHCI Specification.

Bit Description

7:0 Sub Class Code (SCC) — RO.

03h = Universal serial bus host controller.

Bit Description

7:0 Base Class Code (BCC) — RO.

0Ch = Serial bus controller.

EHCI Controller Registers (D29:F7, D26:F7)

590 Intel® ICH8 Family Datasheet

15.1.9 PMLT—Primary Master Latency Timer Register

(USB EHCI—D29:F7, D26:F7)

Address Offset: 0Dh Attribute: RO

Default Value: 00h Size: 8 bits

15.1.10 MEM_BASE—Memory Base Address Register

(USB EHCI—D29:F7, D26:F7)

Address Offset: 10h–13h Attribute: R/W, RO

Default Value: 00000000h Size: 32 bits

15.1.11 SVID—USB EHCI Subsystem Vendor ID Register

(USB EHCI—D29:F7, D26:F7)

Address Offset: 2Ch–2Dh Attribute: R/W (special)

Default Value: XXXXh Size: 16 bits

Reset: None

Bit Description

7:0 Master Latency Timer Count (MLTC) — RO. Hardwired to 00h. Because the EHCI

controller is internally implemented with arbitration on an interface (and not PCI), it

does not need a master latency timer.

Bit Description

31:10 Base Address — R/W. Bits [31:10] correspond to memory address signals [31:10],

respectively. This gives 1-KB of locatable memory space aligned to 1-KB boundaries.

9:4 Reserved

3 Prefetchable — RO. Hardwired to 0 indicating that this range should not be prefetched.

2:1 Type — RO. Hardwired to 00b indicating that this range can be mapped anywhere

within 32-bit address space.

0Resource Type Indicator (RTE) — RO. Hardwired to 0 indicating that the base address

field in this register maps to memory space.

Bit Description

15:0

Subsystem Vendor ID (SVID) — R/W (s pecial). This register, in combination with the

USB 2.0 Subsystem ID register, enables the operating system to distinguish each

subsystem from the others.

NOTE: Writes to this register are enabled when the WRT_RDONLY bit (D29:F7,

D26:F7:80h, bit 0) is set to 1.

Intel® ICH8 Family Datasheet 591

EHCI Controller Registers (D29:F7, D26:F7)

15.1.12 SID—USB EHCI Subsystem I D Re gister

(USB EHCI—D29:F7, D26:F7)

Address Offset: 2Eh–2Fh Attribute: R/W (special)

Default Value: XXXXh Size: 16 bits

Reset: None

15.1.13 CAP_PTR—Capabilities Pointer Register

(USB EHCI—D29:F7, D26:F7)

Address Offset: 34h Attribute: RO

Default Value: 50h Size: 8 bits

15.1.14 INT_LN—Interrupt Line Register

(USB EHCI—D29:F7, D26:F7)

Address Offset: 3Ch Attribute: R/W

Default Value: 00h Size: 8 bits

15.1.15 INT_PN—Interrupt Pin Register

(USB EHCI—D29:F7, D26:F7)

Address Offset: 3Dh A ttribute: RO

Default Value: See Description Size: 8 bits

Bit Description

15:0

Subsystem ID (SID) — R/W (special). BIOS sets the value in this register to identify

the Subsystem ID. This register, in combination with the Subsystem Ve ndor ID register,

enables the operating system to distinguish each subsystem from other(s).

NOTE: Writes to this register are enabled when the WRT_RDONLY bit (D29:F7,

D26:F7:80h, bit 0) is set to 1.

Bit Description

7:0 Capabilities Pointer (CAP_PTR) — RO. This register points to the starting offset of the

USB 2.0 capabilities ranges.

Bit Description

7:0 Interrupt Line (INT_LN) — R/W. This data is not used by the Intel® ICH8. It is used

as a scratchpad register to communicate to software the interrupt line that the

interrupt pi n is connected to.

Bit Description

7:0

Interrupt Pin — RO. This reflects the value of D29IP.EIP (Chipset Config

Registers:Offset 3108:bits 31:28) or D26IP.EIP (Chipset Config Registers:Offset

3114:bits 31:28).

NOTE: Bits 7:4 are always 0h

EHCI Controller Registers (D29:F7, D26:F7)

592 Intel® ICH8 Family Datasheet

15.1.16 PWR_CAPID—PCI Power Management Capability ID

Address Offset: 50h Attribute: RO

Default Value: 01h Size: 8 bits

15.1.17 NXT_PTR1—Next Item Pointer #1 Register

(USB EHCI—D29:F7, D26:F7)

Address Offset: 51h Attribute: R/W (special)

Default Value: 58h Size: 8 bits

Bit Description

7:0 Power Management Capability ID — RO. A value of 01h indicates that this is a PCI

Power Management capabilities field.

Bit Description

7:0

Next Item Pointer 1 Value — R/W (special). This register defaults to 58h, which

indicates that the next capability registers begin at config uration offset 58h. This

allows BIOS to effectively hide the Debug Port capability registers, if necessary. This

software has enabled any master-initiated traffic. Only values of 58h (Debug Port

visible) and 00h (Debug Port invisible) are expected to be programmed in this register.

NOTE: Register not reset by D3-to-D0 warm reset.

Intel® ICH8 Family Datasheet 593

EHCI Controller Registers (D29:F7, D26:F7)

15.1.18 PWR_CAP—Power Management Capabilities Register

(USB EHCI—D29:F7, D26:F7)

Address Offset: 52h–53h Attribute: R/W (special), RO

Default Value: C9C2h Size: 16 bits

NOTES:

1. Normally, this register is read-only to report capabilities to the power management

software. To report different power management capabilities, depending on the system in

which the ICH8 is used, bits 15:11 and 8:6 in this register are writable when the

WRT_RDONLY bit (D29:F7, D26:F7:80h, bit 0) is set. The value written to this register

does not affect the hardware other than changing the value returned during a read.

2. Reset: core well, but not D3-to-D0 warm reset.

Bit Description

15:11

PME Support (PME_SUP) — R/W (special ). This 5-bit field indicates the power states

in which the function may assert PME#. The Intel® ICH8 EHC does not support the D1

or D2 states. For all other states, the ICH8 EHC is capable of generating PME#.

Software should never need to modify this field.

10 D2 Support (D2_SUP) — RO.

0 = D2 State is not supported

9D1 Support (D1_SUP) — RO.

0 = D1 State is not supported

8:6 Auxiliary Current (AUX_CUR) — R/W (special). The ICH8 EHC reports 375 mA

maximum suspend well current required when in the D3COLD state.

5Device Specific Initialization (DSI)— RO. The ICH8 reports 0, indicating that no

device-specific initialization is required.

4 Reserved

3PME Clock (PME_CLK) — RO. The ICH8 reports 0, indicating that no PCI clock is

required to generate PME#.

2:0 Version (VER) — RO. The ICH8 re ports 010b , i ndicating that it c omplies with R evision

1.1 of the PCI Power Management Specification.

EHCI Controller Registers (D29:F7, D26:F7)

594 Intel® ICH8 Family Datasheet

15.1.19 PWR_CNTL_STS—Power Management Control/

Status Register (USB EHCI—D29:F7, D26:F7)

Address Offset: 54h–55h Attribute: R/W, R/WC, RO

Default Value: 0000h Size: 16 bits

NOTE: Reset (bits 15, 8): suspend well, and not D3-to-D0 warm reset nor core well reset.

Bit Description

PME Status — R/WC.

0 = Writing a 1 to this bit will clear it and cause the internal PME to deassert (if

enabled).

1 = This bit is set when the ICH8 EHC would normally assert the PME# signal

independent of the state of the PME_En bit.

NOTE: This bit must be explicitly cleared by the operating system each time the

operating system is loaded.

14:13 Data Scale — RO. Hardwired to 00b indicating it does not support the associated Data

12:9 Data Select — RO. Hardwired to 0000b indicating it does not support the associated

Data register.

PME Enable — R/W.

0 = Disable.

1 = Enable. Enables Intel® ICH8 EHC to generate an internal PME signal when

PME_Status is 1.

NOTE: This bit must be explicitly cleared by the operating system each time it is

initially loaded.

7:2 Reserved

1:0

Power State — R/W. This 2 -bit field is used both to determine the current power state

of EHC function and to set a new power state. The definition of the field values are:

00 = D0 st ate

11 = D3HOT state

If software attempts to write a value of 10b or 01b in to this field, the write operation

must complete normally; however, the data is discarded and no state change occurs.

When in the D3HOT state, the ICH8 must not accept accesses to the EHC memory

range; but the configuration space must still be accessible. Wh en not in the D0 state,

the generation of the interrupt output is blocked. Specifically , the PIRQH is not asserted

by the ICH8 when not in the D0 state.

When software changes this value from the D3HOT state to the D0 state, an internal

warm (soft) reset is generated, and software must re-initialize the function.

Intel® ICH8 Family Datasheet 595

EHCI Controller Registers (D29:F7, D26:F7)

15.1.20 DEBUG_CAPID—Debug Port Capability ID Register

(USB EHCI—D29:F7, D26:F7)

Address Offset: 58h Attribute: RO

Default Value: 0Ah Size: 8 bits

15.1.21 NXT_PTR2—Next Item Pointer #2 Register

(USB EHCI—D29:F7, D26:F7)

Address Offset: 59h Attribute: RO

Default Value: 00h Size: 8 bits

15.1.22 DEBUG_BASE—Debug Port Base Offset Register

(USB EHCI—D29:F7, D26:F7)

Address Offset: 5Ah–5Bh Attribute: RO

Default Value: 20A0h Size: 16 bits

15.1.23 USB_RELNUM—USB Release Number Regist er

(USB EHCI—D29:F7, D26:F7)

Address Offset: 60h Attribute: RO

Default Value: 20h Size: 8 bits

Bit Description

7:0 Debug Port Capability ID — RO. Hardwired to 0Ah indicating that this is the start of a

Debug Port Capability structure.

Bit Description

7:0 Next Item Pointer 2 Capability — RO. Hardwired to 00h to indicate there are no more

capability structures in this function.

Bit Description

15:13 BAR Number — RO. Hardwired to 001b to indicate the memory BAR begins at offset

10h in the EHCI configuration space.

12:0 Debug Port Offset — RO. Hardwired to 0A0h to indicate that the Debug Port registers

begin at offset A0h in the EHCI memory range.

Bit Description

7:0 USB Release Number — RO. A value of 20h indicates that this controller follows

Universal Serial Bus (USB) Specificatio n, Revision 2.0.

EHCI Controller Registers (D29:F7, D26:F7)

596 Intel® ICH8 Family Datasheet

15.1.24 FL_ADJ—Frame Length Adjustment Register

(USB EHCI—D29:F7, D26:F7)

Address Offset: 61h Attribute: R/W

Default Value: 20h Size: 8 bits

This feature is used to adjust any offset from the clock source that generates the clock

that drives the SOF counter. When a new value is written into these six bits, the length

of the frame is adjusted. Its initial programmed value is system dependent based on

the accuracy of hardware USB clock and is initialized by system BIOS. This register

should only be modified when the HChalted bit (D29:F7, D26:F7:CAPLENGTH + 24h,

bit 12) in the USB2.0_STS register is a 1. Changing value of this register while the host

controller is operating yields undefined results. It should not be reprogrammed by USB

system software unless the default or BIOS programmed values are incorrect, or the

system is restoring the register while returning from a suspended state.

These bits in suspend well and not reset by a D3-to-D0 warm rest or a core well reset.

Bit Description

7:6 Reserved — RO. These bits are reserved for future use and should read as 00b.

5:0

Frame Length Timing Value — R/W. Each decimal value change to this register

corresponds to 16 high-speed bit times. The SOF cycle time (number of SOF counter

clock periods to generate a SOF micro-frame length) is equal to 59488 + value in this

field. The default value is decimal 32 (20h), which gives a SOF cycle time of 60000.

Frame Length (# 480 MHz

Clocks) (decimal) Frame Length Timing Value (this

59488 0

59504 1

59520 2

——

59984 31

60000 32

——

60480 62

60496 63

Intel® ICH8 Family Datasheet 597

EHCI Controller Registers (D29:F7, D26:F7)

15.1.25 PWAKE_CAP—Port Wake Capability Register

(USB EHCI—D29:F7, D26:F7)

Address Offset: 62–63h Attribute: R/W

Default Value: 01FFh Size: 16 bits

This register is in the suspend power well. The intended use of this register is to

establish a policy about which ports are to be used for wake events. Bit positions 1–

6(D29) or 1–4(D26) in the mask correspond to a physical port implemented on the

current EHCI controller. A 1 in a bit position indicates that a device connected below the

port can be enabled as a wake -up dev ice and th e port may be enabled for disconnect/

connect or overcurrent events as wake-up events. This is an information-only mask

controller. The system-specific policy can be established by BIOS initializing this

These bits are not reset by a D3-to-D0 warm rest or a core well reset.

15.1.26 LEG_EXT_CAP—USB EHCI Legacy Support Extended

Capability Register (USB EHCI—D29:F7, D26:F7)

Address Offset: 68–6Bh Attribute: R/W, RO

Default Value: 00000001h Size: 32 bits

Power Well: Suspend

NOTE: These bits are not reset by a D3-to-D0 warm rest or a core well reset.

Bit Description

15:7 (D29)

15:5 (D26) Reserved — RO.

6:1 (D29)

4:1 (D26)

Port Wake Up Capability Mask — R/W. Bit positions 1 through 6 (Device 29)

or 1 through 4 (Device 26) correspond to a physical port implemented on this

host controller. For example, bit position 1 corresponds to port 1, bit position 2

corresponds to port 2, etc.

0Port Wake Implemented — R/W. A 1 in this bit indicates that this register is

implemented to software.

Bit Description

31:25 Reserved — RO. Hardwired to 00h

24 HC OS Owned Semaphore — R/W. System softw are sets this bit to request ownership

of the EHCI controller. Ownership is obtained when this bit reads as 1 and the HC BIOS

Owned Semaphore bit reads as clear.

23:17 Reserved — RO. Hardwired to 00h

16 HC BIOS Owned Semaphore — R/W. The BIOS sets this bit to establish ownership of

the EHCI controller. System BIOS will clear this bit in response to a request for

ownership of the EHCI controller by system software.

15:8 Next EHCI Capability Pointer — RO. Hardwired to 00h to indicate that there are no

EHCI Extended Capability structures in this device.

7:0 Capability ID — RO. Hardwired to 01h to indicate that this EHCI Extended Capability is

the Legacy Support Capability.

EHCI Controller Registers (D29:F7, D26:F7)

598 Intel® ICH8 Family Datasheet

15.1.27 LEG_EXT_CS—USB EHCI Legacy Support Extended

Control / Status Register (USB EHCI—D29:F7, D26:F7)

Address Offset: 6C–6Fh Attribute: R/W, R/WC, RO

Default Value: 00000000h Size: 32 bits

Power Well: Suspend

Note: These bits are not reset by a D3-to-D0 warm rest or a core well reset.

Bit Description

31 SMI on BAR — R/WC. Software clears this bit by writing a 1 to it.

0 = Base Address Register (BAR) not written.

1 = This bit is set t o 1 when the Base Address Register (BAR) is written.

30 SMI on PCI Command — R/WC. Software clears this bit by writing a 1 to it.

0 = PCI Command (PCICMD) Register Not writte n.

1 = This bit is set t o 1 when the PCI Command (PCICMD) Register is written.

SMI on OS Ownership Change — R/WC. Software clears this bit by writing a 1 to it.

0 = No HC OS Owned Semaphore bit change.

1 = This bit is set to 1 when the HC OS Owned Semaphore bit in the LEG_EXT_CAP

28:22 Reserved — RO. Hardwired to 00h

SMI on Async Advance — RO. This bit is a shadow bit of the Interrupt on Async

Advance bit (D29:F7, D26:F7:CAPLENGTH + 24h, bit 5) in the USB2.0_STS register.

NOTE: To clear this bit system software must write a 1 to the Interrupt on Async

Advance bit in the USB2. 0_STS registe r.

SMI on Host System Error — RO. This bit is a shadow bit of Host System Error bit in

the USB2.0_STS register (D29:F7, D26:F7:CAPLENGTH + 24h, bit 4).

NOTE: To clear this bit system software must write a 1 to the Host System Error bit in

the USB2.0_STS register.

SMI on Frame List Rollover — RO. This bit is a shadow bit of Frame List Rollover bit

(D29:F7, D26:F7:CAPLENGTH + 24h, bit 3) in the USB2.0_STS register.

NOTE: To clear this bit system software must write a 1 to the Frame List Rollover bit in

the USB2.0_STS register.

SMI on Port Change Detect — RO. This bit is a shadow bit of Port Change Detect bit

(D29:F7, D26:F7:CAPLENGTH + 24h, bit 2) in the USB2.0_STS register.

NOTE: To clear this bit system software must write a 1 to the Port Change Detect bit in

the USB2.0_STS register.

SMI on USB Error — RO. This bit is a shadow bit o f USB Error Interrupt (USBERRINT)

bit (D29:F7, D26:F7:CAPLENGTH + 24h, bit 1) in the USB2.0_STS register.

NOTE: To clear this bit system so ftware mus t write a 1 to the USB Er ror Interrupt bit i n

the USB2.0_STS register.

SMI on USB Complete — RO. This bit is a shadow bit of USB Interrupt (USBINT) bit

(D29:F7, D26:F7:CAPLENGTH + 24h, bit 0) in the USB2.0_STS register.

NOTE: To clear this bit system software must write a 1 to the USB Interrupt bit in the

USB2.0_STS register.

Intel® ICH8 Family Datasheet 599

EHCI Controller Registers (D29:F7, D26:F7)

SMI on BAR Enable — R/W.

0 = Disable.

1 = Enable. When this bit is 1 and SMI on BAR (D29:F7, D26:F7:6 Ch, bit 31 ) is 1, then

the host controller will issue an SMI.

SMI on PCI Command Enable — R/W.

0 = Disable.

1 = Enable. When this bit is 1 and SMI on PCI Command (D29:F7, D26:F7:6Ch, bit 30)

is 1, then the host controller will issue an SMI.

SMI on OS Ownership Enable — R/W.

0 = Disable.

1 = Enable. When this bit is a 1 AND the OS Ownership Change bit (D29:F7,

D26:F7:6Ch, bit 29) is 1, the host controller will issue an SMI.

12:6 Reserved — RO. Hardwired to 00h

SMI on Async Advance Enabl e — R/W.

0 = Disable.

1 = Enable. When this bit is a 1, and the SMI on Async Advance bit (D29:F7,

D26:F7:6Ch, bit 21) is a 1, the host controller will issue an SMI immediately.

SMI on Host System Error Enable — R/W.

0 = Disable.

1 = Enable. When this bit is a 1, and the SMI on Host System Error (D29:F7,

D26:F7:6Ch, bit 20) is a 1, the host controller will issue an SMI.

SMI on Frame List Rollover Enable — R/W.

0 = Disable.

1 = Enable. When this bit is a 1, and the SMI on Frame List Rollover bit (D29:F7,

D26:F7:6Ch, bit 19) is a 1, the host controller will issue an SMI.

SMI on Port Change Enable — R/W.

0 = Disable.

1 = Enable. When this bit is a 1, and the SMI on Port Change Detect bit (D29:F7,

D26:F7:6Ch, bit 18) is a 1, the host controller will issue an SMI.

SMI on USB Error Enable — R/W.

0 = Disable.

1 = Enable. When this bit is a 1, and the SMI on USB Error bit (D29:F7, D26:F7:6Ch,

bit 17) is a 1, the host controller will issue an SMI immediately.

SMI on USB Complete Enable — R/W.

0 = Disable.

1 = Enable. When this bit is a 1, and the SMI on USB Complete bit (D29:F7,

D26:F7:6Ch, bit 16) is a 1, the host controller will issue an SMI immediately.

Bit Description

EHCI Controller Registers (D29:F7, D26:F7)

600 Intel® ICH8 Family Datasheet

15.1.28 SPECIAL_SMI—Intel Specific USB 2.0 SMI Register

(USB EHCI—D29:F7, D26:F7)

Address Offset: 70h–73h Attribute: R/W, R/WC

Default Value: 00000000h Size: 32 bits

Power Well: Suspend

Note: These bits are not reset by a D3-to-D0 warm rest or a core well reset.

Bit Description

31:28 (D29)

31:26 (D26) Reserved — RO. Hardwired to 00h

27:22 (D29)

25:22 (D26)

SMI on PortOwner — R/WC. Software clears these bits by writing a 1 to it.

0 = No Port Owner bit change.

1 = Bits 27:22, 25 :22 correspond to the Port Owner bi ts for ports 1 (22) through

4 (25) or 6 (27). These bits are set to 1 when the associat ed Port Owne r bits

transition from 0 to 1 or 1 to 0.

SMI on PMCSR — R/WC. Software clears these bits by writing a 1 to it.

0 = Power State bits Not modified.

1 = Software modified the Power State bits in the Power Management Control/

Status (PMCSR) register (D29:F7, D26:F7:54h).

20 SMI on Async — R/WC. Software clears these bits by writing a 1 to it.

0 = No Async Schedule Enable bit change

1 = Async Schedule Enable bit transitioned from 1 to 0 or 0 to 1.

19 SMI on Periodi c — R/WC. Software clears this bit by writing a 1 it.

0 = No Periodic Schedule Enable bit change.

1 = Periodic Schedule Enable bit transitions from 1 to 0 or 0 to 1.

18 SMI on CF — R/WC. Software clears this bit by writing a 1 it.

0 = No Configure Flag (CF) change.

1 = Configure Flag (CF) transitions from 1 to 0 or 0 to 1.

SMI on HCHalted — R/WC. Software clears this bit by writing a 1 it.

0 = HCHalted did Not transition to 1 (as a result of the Run/Stop bit being

cleared).

1 = HCHalted transitions to 1 (as a result of the Run/Stop bit being cleared).

16 SMI on HCReset — R/WC. Software clears this bit by writing a 1 it.

0 = HCRESET did Not transitioned to 1.

1 = HCRESET transitioned to 1.

15:14 Reserved — RO. Hardwired to 00h

13:6

SMI on PortOwner Enable — R/W.

0 = Disable.

1 = Enable. When any of these bits are 1 and the corresponding SMI on

PortOwner bits are 1, then the host controller will issue an SMI. Unused

ports should have their corresponding bits cleared.

SMI on PMSCR Enable — R/W.

0 = Disable.

1 = Enable. When this bit is 1 and SMI on PMSCR is 1, then the host controller

will issue an SM I.

SMI on Async Enable — R/W.

0 = Disable.

1 = Enable. When this bit is 1 and SMI on As ync is 1, then the host controll er will

issue an SMI

Intel® ICH8 Family Datasheet 601

EHCI Controller Registers (D29:F7, D26:F7)

15.1.29 ACCESS_CNTL—Access Control Register

(USB EHCI—D29:F7, D26:F7)

Address Offset: 80h Attribute: R/W

Default Value: 00h Size: 8 bits

SMI on Periodic Enable — R/W.

0 = Disable.

1 = Enable. When this bit is 1 and SMI on Periodic is 1, then the host controller

will issue an SMI.

SMI on CF Enable — R/W.

0 = Disable.

1 = Enable. When this bit is 1 and SMI on CF is 1, then the host controller will

issue an SMI.

SMI on HCHalted Enable — R/W.

0 = Disable.

1 = Enable. When this bit is a 1 and SMI on HCHalted is 1, then the host

controller will issue an SMI.

SMI on HCReset Enable — R/W.

0 = Disable.

1 = Enable. When this bit is a 1 and SMI on HCReset is 1, then host controller

will issue an SMI.

Bit Description

7:1 Reserved

WRT_RDONLY — R/W. When set to 1, this bit enables a select group of normally read-

only registers in the EHC function to be written by software. R egisters that may only be

written when this mode is entere d are noted in the summary tables and detailed

description as “Read/Write-Special”. The regist ers fall into two categories:

1. System-configured parameters, and

2. Status bits

EHCI Controller Registers (D29:F7, D26:F7)

602 Intel® ICH8 Family Datasheet

15.1.30 EHCIIR1—EHCI Initialization Register 1 (Mobile Only)

(USB EHCI—D29:F7, D26:F7)

Address Offset: 84h Attribute: R/W, R/WL

Default Value: 01h Size: 8 bits

15.1.31 EHCIIR2—EHCI Initialization Register 2

(USB EHCI—D29:F7, D26:F7)

Address Offset: FCh Attribute: R/W

Default Value: 20001706h Size: 32 bits

Bit Description

7:5 Reserved

4Pre-fetch Based Pause Disable – R/W.

0 = Pre-fetch Based Pause is enabled

1 = Pre-fetch Based Pause is disabled.

3:0 Reserved

Bit Description

31:30 Reserved

29 EHCIIR2 Field 2 — R/W. BIOS must set this bit

28:18 Reserved

17 EHCIIR2 Field 1 — R/W. BIOS must set this bit

16:0 Reserved

Intel® ICH8 Family Datasheet 603

EHCI Controller Registers (D29:F7, D26:F7)

15.2 Memory-Mapped I/O Registers

The EHCI memory-mapped I/O space is composed of two sets of registers: Capability

Registers and Operational Registers.

Note: The ICH8 EHCI controller will not accept memory transactions (neither reads nor

writes) as a target that are locked transactions. The locked transactions should not be

forwarded to PCI as the address space is known to be allocated to USB.

Note: When the EHCI function is in the D3 PCI power state, accesses to the USB 2.0 memory

range are ignored and result a master abort. Similarly, if the Memory Space Enable

(MSE) bit (D29:F7, D26:F7:04h, bit 1) is not set in the Command register in

configuration space, the memory r ange will not be decoded by the ICH8 enhanced host

controller (EHC). If the MSE bit is not set, then the ICH8 must default to allowing any

memory accesses for the range specified in the BAR to go to PCI. This is because the

range may not be valid and, therefore, the cycle must be made available to any other

targets that may be currently using that range.

15.2.1 Host Controller Capability Registers

These registers specify the limits, restrictions and capabilities of the host controller

implementation. Within the host controller capability registers, only the structural

parameters register is writable. These reg is t ers are i mp l em ente d in the s uspe nd well

and is only reset by the standard suspend-well hardw are reset, not by HCRESET or the

D3-to-D0 reset.

Note: Note that the EHCI controller does not support as a target memory transactions that

are locked transactions. Attempting to access the EHCI controller Memory-Mapped I/O

space using locked memory transactions will result in undefined behavior.

Note: Note that when the USB2 function is in the D3 PCI power state, accesses to the USB2

memory range are ignored and will result in a master abort Similarly, if the Memory

Space Enable (MSE) bit is not set in the Command register in configuration space, the

memory range will not be decoded by the Enhanced Host Controller (EHC). If the MSE

bit is not set, then the EHC will not claim any memory accesses for the range specified

in the BAR.

NOTE: “Read/Write Special” means that the register is normally read-only, but may be written

when the WRT_RDONLY bit is set. Because these registers are expected to be programmed

by BIOS during initialization, their contents must not get modified by HCRESET or D3-to-

D0 internal reset.

Table 134. Enhanced Host Controller Capability Registers

MEM_BASE

+ Offset Mnemonic Register Default Type

00h CAPLENGTH Capabilities Registers Length 20h RO

02h–03h HCIVERSION Host Controller Interface Version

Number 0100h RO

04h–07h HCSPARAMS Host Controller Structural Parameters 00104208h R/W

(special),

08h–0Bh HCCPARAMS Host Controller Capability Parameters 00006871h RO

EHCI Controller Registers (D29:F7, D26:F7)

604 Intel® ICH8 Family Datasheet

15.2.1.1 CAPLENGTH—Capability Registers Length

Offset: MEM_BASE + 00h Attribute: RO

Default Value: 20h Size: 8 bits

15.2.1.2 HCIVERSION—Host Controller Interface Version Number

Offset: MEM_BASE + 02h–03h Attribute: RO

Default Value: 0100h Size: 16 bits

Bit Description

7:0

Capability Register Length Value — RO. This register is used as an offset to add to the

Memory Base Register (D29:F7, D26:F7:10h) to find the beginning of the Operational

begin at offset 20h.

Bit Description

15:0 Host Controller Interface V ersion Number — RO . This is a two-byte register containin g a

BCD encoding of the version number of interface that this host controller interface

conforms.

Intel® ICH8 Family Datasheet 605

EHCI Controller Registers (D29:F7, D26:F7)

15.2.1.3 HCSPARAMS—Host Controller Structural Parameters

Offset: MEM_BASE + 04h–07h Attribute: R/W (special), RO

Default Value: 00103206h (D29:F7) Size: 3 2 bits

00102204h (D26:F7)

Note: This register is reset by a suspend well reset and not a D3-to-D0 reset or HCRESET.

NOTE: This register is writable when the WRT_RDONLY bit is set.

Bit Description

31:24 Reserved — RO. Default=0h.

23:20 Debug Port Number (DP_N) — RO (special). Hardwired to 1h indicating that the Debug

Port is on the lowest numbered port on the EHCI.

19:16 Reserved

15:12

Number of Companion Controllers (N_CC) — R/W (special). This field indicates the

number of companion controllers ass o ciated with this USB EHCI host controller.

A 0 in this field indicates there are no companion host controllers. Port-ownership hand-

off is not supported. Only high-speed devices are supported on the host controller root

ports.

A value of 1 or more in this field indicates there are companion USB UHCI host

controller(s). Port-ownership hand-offs are supported. High, Full- and Low-speed

devices are supported on the host controller root ports.

The ICH8 allows the default value of 3h (D29) or 2 (D26) to be over-written by BIOS.

When removing classic controllers, they must be disabled in the following order:

Function 2, Function 1, and Function 0, which correspond to ports 5:4, 3:2, and 1:0,

respectively for Device 2 9. F or Device 26 the following order is Function 1 then Func tion

0, which correspond to ports 9:8 and 7:6, respectively.

11:8 Number of Ports per Companion Controller (N_PCC) — RO. Hardwired to 2h. This field

indicates the number of ports supported per companion host controller. It is used to

indicate the port routing configuration to system software.

7:4 Reserved. These bits are reserved and default to 0.

3:0

N_PORTS — R/W (special). This field specifies the number of physical downstream

ports implemented on this host controller. The value of this field determines how many

port registers are addressable in the Operational Register Space. V alid values are in the

range of 1h to Fh.

The ICH8 reports 6h for D29 and 4h for D26 by default. However, software may write a

value less than the default for some platform configurations. A 0 in this field is

undefined.

EHCI Controller Registers (D29:F7, D26:F7)

606 Intel® ICH8 Family Datasheet

15.2.1.4 HCCPARA M S—Host Controller Capability Parameters

Offset: MEM_BASE + 08h–0Bh Attribute: RO

Default Value: 00006871h Size: 32 bits

Bit Description

31:16 Reserved

15:8 EHCI Extended Capabilities Pointer (EECP) — RO. This field is hardwired to 68h,

indicating that the EHCI capabilities list exists and begins at offset 68h in the PCI

configuration space.

7:4

Isochronous Scheduling Threshold — RO. This field indicates, relative to the current

position of the executing host controller, where software can reliably update the

isochronous schedule. When bit 7 is 0, the value of the least significant 3 bits indi cates

the number of micro-frames a hos t c ont rol le r hold a set of isochronous data structures

(one or more) before flushing the state. When bit 7 is a 1, then host software assumes

the host controller may cache an isochronous data structure for an entire frame. Refer

to the EHCI specification for details on how software uses this information for

scheduling isochronous transfers.

This field is hardwired to 7h.

3 Reserved. These bits are reserved and should be set to 0.

2Asynchronous Schedule Park Capability — RO. Thi s bit is hardwired to 0 indicat in g th at

the host controller does not support this optional feature

Programmable Frame List Flag — RO.

0 = System software must use a frame list length of 1024 elements with this host

controller. The USB2.0_CMD register (D29:F7, D26:F7:CAPLENGTH + 20h, bits

3:2) Frame List Size field is a read-only register and must be set to 0.

1 = System software can specify and use a smaller frame list and configure the host

controller via the USB2.0_CMD register Frame List Size field. The frame list must

always be aligned on a 4K page boundary. This requirement ensures that the frame

list is always physically contiguous.

64-bit Addressing Capability — RO. This field documents the addressing range

capability of this implementation. The value of this field determines whether software

should use the 32-bit or 64-bit data structures. Values for this field have the following

interpretation:

0 = Data structures using 32-bit address memory pointers

1 = Data structures using 64-bit address memory pointers

This bit is hardwired to 1.

NOTE: ICH8 only implements 44 bits of addressing. Bits 63:44 will always be 0.

Intel® ICH8 Family Datasheet 607

EHCI Controller Registers (D29:F7, D26:F7)

15.2.2 Host Controller Operational Registers

This section defines the enhanced host controller operational registers. These registers

are located after the capabilities registers. The operational register base must be

dword-aligned and is calculated by adding the value in the first capabilities register

(CAPLENGTH) to the base address of the enhanced host controller register address

space (MEM_BASE). Since CAPLENGTH is always 20h, Table 135 already accounts for

this offset. All registers are 32 bits in length.

Note: Software must read and write these registers using only dword accesses.These

registers are divided into two sets. The first set at offsets MEM_BASE + 00:3Bh are

implemented in the core power well. Unless otherwise noted, the core well registers are

reset by the assertion of any of the following:

• Core well hardware reset

• HCRESET

• D3-to-D0 reset

Table 135. Enhanced Host Controller Operational Register Address Map

MEM_BASE

+ Offset Mnemonic Register Name Default Special

Notes Type

20h–23h USB2.0_CMD USB 2.0 Command 00080000h R/W, RO

24h–27h USB2.0_STS USB 2.0 Status 00001000h R/WC, RO

28h–2Bh USB2.0_INTR USB 2.0 Interrupt Enable 00000000h R/W

2Ch–2Fh FRINDEX USB 2.0 Frame Index 00000000h R/W,

30h–33h CTRLDSSEGM

ENT Control Data Structure

Segment 00000000h R/W, RO

34h–37h PERODICLIST

BASE Period Frame List Base

Address 00000000h R/W

38h–3Bh ASYNCLISTAD

DR Current Asynchronous

List Address 00000000h R/W

3Ch–5Fh — Reserved 0h RO

60h–63h CONFIGFLAG Configure Flag 00000000h Suspend R/W

64h–67h PORT0SC Port 0 Status and Control 00003000h Suspend R/W,

R/WC, RO

68h–6Bh PORT1SC Port 1 Status and Control 00003000h Suspend R/W,

R/WC, RO

6Ch–6Fh PORT2SC Port 2 Status and Control 00003000h Suspend R/W,

R/WC, RO

70h–73h PORT3SC Port 3 Status and Control 00003000h Suspend R/W,

R/WC, RO

74h–77h

D29 Only PORT4SC Port 4 Status and Control 00003000h Suspend R/W,

R/WC, RO

78h–7Bh

D29 Only PORT5SC Port 5 Status and Control 00003000h Suspend R/W,

R/WC, RO

7Ch–9Fh — Reserved Undefined RO

A0h–B3h — Debug Port Registers Undefined See register

description

B4h–3FFh — Reserved Undefined RO

EHCI Controller Registers (D29:F7, D26:F7)

608 Intel® ICH8 Family Datasheet

The second set at offsets MEM_BASE + 60h to the end of the implemented register

space are implemented in the Suspend power well. Unless otherwise noted, the

suspend well registers are reset by the assertion of either of the following:

• Suspend well hardware reset

• HCRESET

15.2.2.1 USB2.0_CMD—USB 2.0 Command Register

Offset: MEM_BASE + 20–23h Attribute: R/W, RO

Default Value: 00080000h Size: 32 bits

Bit Description

31:24 Reserved. These bits are reserved and should be set to 0 when writing this register.

23:16

Interrupt Threshold Control — R/W. System software uses this field to select the

maximum rate at which the hos t controller will issue interrupts. The only valid values

are defined below. If software writes an invalid value to this register, the results are

undefined.

15:8 Reserved. These bits are reserved and should be set to 0 when writing this register.

11:8 Unimplemented Asynchronous Park Mode Bits. Hardwired to 000b indicating the host

controller does not support this optional feature.

7Light Host Controller Reset — RO. Hardwired to 0. The ICH8 does not implement this

optional reset.

Interrupt on Async Advance Doorbe ll — R/W. This bit is used as a doorbell by

software to tell the host controller to issue an interrupt the next time it a dvances

asynchronous schedule .

0 = The host controller sets this bit to a 0 after it has set the Interrupt on A sy nc

Advance status bit (D29:F7, D26:F7:CAPLENGTH + 24h, bit 5) in the USB2.0_STS

1 = Software must write a 1 to this bit to ring the doorbell. When the host controller

has evicted all appropriate cached schedule state, it sets the Interrupt on Async

Advance status bit in the USB2.0_STS register. If the Interrupt on Async Advance

Enable bit in the USB2.0_INTR register (D29:F7, D26:F7:CAPLENGTH + 2 8h, bit 5)

is a 1 then the host controller will assert an interrupt at the next interrupt

threshold. See the EHCI specification for operational details.

NOTE: Software should not write a 1 to this bit when the asynchronous schedule is

inactive. Doi n g so will yield undefined results.

Asynchronous Schedule Enable — R/W. Default 0b. This bit controls whether the

host controller skips processing the Asynchronous Schedule.

0 = Do not process the Asynchronous Schedule

1 = Use the ASYNCLISTADDR register to access the Asynchronous Schedule.

Value Maximum Interrupt Interval

00h Reserved

01h 1 micro-frame

02h 2 micro-frames

04h 4 micro-frames

08h 8 micro-frames (default, equates to 1 ms)

10h 16 micro-frames (2 ms)

20h 32 micro-frames (4 ms)

40h 64 micro-frames (8 ms)

Intel® ICH8 Family Datasheet 609

EHCI Controller Registers (D29:F7, D26:F7)

NOTE: The Command Register indicates the command to be executed by the serial bus host

controller. Writing to the register causes a command to be executed.

Periodic Schedule Enable — R/W. Default 0b. This bit controls whether the host

controller skips processing the Periodic Schedule.

0 = Do not process the Periodic Schedule

1 = Use the PERIODICLISTBASE register to access the Periodic Schedule.

3:2 Frame List Size — RO. The ICH8 hardwires this field to 00b because it only supports

the

1024-element frame list size.

Host Controller Reset (HCRESET) — R/W. This control bit used by software to reset

the host controller. The effects of this on root hub registers are similar to a Chip

Hardware Reset

(i.e., RSMRST# assertion and PWROK deassertion on the ICH8).

When software writes a 1 to this bit, the host controller resets its internal pipelines,

timers, counters, state machines, etc. to their initial value. Any transaction currently in

progress on USB is immediately terminated. A USB reset is not driven on downstream

ports.

NOTE: PCI configuration registers and Host controller capability registers are not

effected by this reset.

All operational registers, including port registers and port state ma chines are set to

their initial v alues . P ort ownership re verts to th e companion host cont roller(s), wit h the

side effects described in the EHCI spec. Software must re-initialize the host controller in

order to return the host controller to an operational state.

This bit is set to 0 by the host controller when the reset process is complete. Software

cannot terminate the reset process early by writing a 0 to this register.

Software should not set this bit to a 1 when the HCHalted bit (D29:F7,

D26:F7:CAPLENGTH + 24h, bit 12) in the USB2.0_STS register is a 0. Attempting to

reset an actively running host controller will result in undefi ned behavior. This reset me

be used to leave EHCI port test modes.

Run/Stop (RS) — R/W.

0 = Stop (default)

1 = Run. When set to a 1, the Host controller proceeds with execution of the schedule.

The Host con tr oller continues execution as long as this bit is set. When this bit is

set to 0, the Hos t controller c ompletes the curr ent tran saction on the USB and then

halts. The HCHalted bit in the USB2.0_STS register indicat es when the Host

controller has fi nished the transaction and has entered the stopped state.

Software should not write a 1 to this field unless the host controller is in the Halted

state (i.e., HCHalted in the USBSTS register is a 1). The Halted bit is cleared

immediately when the Run bit is set.

The following table explains how the different combinations of Run and Halted should

be interpreted:

Memory read cycles initiated by the EHC that receive any status other than Successful

will result in this bit being cleared.

Bit Description

Run/Stop Halted Interpretation

0b 0b In the process of halting

0b 1b Halted

1b 0b Running

1b 1b Invalid - the HCHalted bi t clears immediately

EHCI Controller Registers (D29:F7, D26:F7)

610 Intel® ICH8 Family Datasheet

15.2.2.2 USB2.0_STS—USB 2.0 Status Register

Offset: MEM_BA SE + 24h–27h Attribute: R/WC, RO

Default Value: 00001000h Size: 32 bits

This register indicates pending interrupts and various states of the Host controller. The

status resulting from a transaction on the serial bus is not indicated in this register. See

the Interrupts description in section 4 of the EHCI specification for additional

information concerning USB 2.0 interrupt conditions.

Note: For the writable bits, software must write a 1 to clear bits that are set. W riting a 0 has

no effect.

Bit Description

31:16 Reserved. These bits are reserved and should be set to 0 when writing this register.

Asynchronous Schedule Status ⎯ RO. This bit reports the current real status of the

Asynchronous Schedule.

0 = Status of the Asynchronous Schedule is disabled. (Default)

1 = Status of the Asynchronous Schedule is enabled.

NOTE: The Host controller is not required to immediately disable or enable the

Asynchronous Schedule when software transitions the Asynchronous Schedule

Enable bit (D29:F7, D26:F7:CAPLENGTH + 20h, bit 5) in the USB2.0_C MD

value, the Asynchronous Schedule is either enabled (1) or disabled (0).

Periodic Schedule St atus ⎯ RO. This bit reports the current real status of the Periodic

Schedule.

0 = Status of the Periodic Schedule is disabled. (Default)

1 = Status of the Periodic Schedule is enabled.

NOTE: The Host controller is not required to immediately disable or enable the Periodic

Schedule when software transitions the Periodic Schedule Enable bit (D29:F7,

D26:F7:CAPLENGTH + 20h, bit 4) in the USB2.0_ CMD register. When this bit and

the Periodic Schedule Enable bit are the same value, the Periodic Schedule is

either enabled (1) or disabled (0).

13 Reclamation ⎯ RO. 0=Default. This read-only status bit is used to detect an empty

asynchronous schedule. The operational model and valid transitions for this bit are

described in Section 4 of the EHCI Specification.

HCHalted ⎯ RO.

0 = This bit is a 0 when the Run/Stop bit is a 1.

1 = The Host controller sets this bit to 1 after it has stopped executing as a result of the

Run/Stop bit being set to 0, either by software or by the Host controller hardware

(e.g., internal error). (Default)

11:6 Reserved

Interrupt on Async Advance — R/WC. 0=Default. System software can force the host

controller to issue an int errup t the next time the host controller advances the

asynchronous schedule by writing a 1 to the Interrupt on Async Advance Doorbell bit

(D29:F7, D26:F7:CAPLENGTH + 20h, bit 6) in the USB2.0_CMD register. This bit

indicates the assertion of that interrupt source.

Intel® ICH8 Family Datasheet 611

EHCI Controller Registers (D29:F7, D26:F7)

Host System Error — R/WC.

0 = No serious error occurred during a host system access involving the Host controller

module

1 = The Host controller sets this bit to 1 when a serious error occurs during a host

system acce ss involving the Host controller module. A hardware interrupt is

generated to the system. Memory read cycles initiated by the EHC that rece ive any

status other than Successful will result in this bit being set.

When this error occurs, the Host controller clears the Run/Stop bit in the

USB2.0_CMDregister (D29: F7, D26:F7:CAPLENGTH + 2 0h, bit 0) to pre vent further

execution of the scheduled TDs. A hardware interrupt is generated to the system (if

enabled in the Interrupt Enable Register).

Frame List Rollover — R/WC.

0 = No Frame List Index rollover from its maximum value to 0.

1 = The Host controller se ts this bit to a 1 wh en the Frame List Index (see Section) rolls

over from its maximum value to 0. Since the ICH8 only supports the 1024-entry

Frame List Size, the Frame List Index rolls over every time FRNUM13 toggles.

Port Change Detect — R/WC. This bit is allowed to be maintained in the Auxiliary

power well. Alternatively, it is also acceptable that on a D3 to D0 transition of the EHCI

HC device, this bit is loaded with the OR of all of the PORTSC change bits (including:

Force port resume, overcurrent change, enable/disable change and connect status

change). Regardless of the implementation, when this bit is readable (i.e., in the D0

state), it must provide a valid view of the Port Status registers.

0 = No change bit transition from a 0 to 1 or No Force P ort R esume bit transition from 0

to 1 as a result of a J-K transition detected on a suspended port.

1 = The Host controller sets this bit to 1 when any port for which the Port Owner bit is

set to 0 has a change bit transition from a 0 to 1 or a Force Port Resume bit

transition from 0 to 1 as a result of a J-K transition detected on a suspended port.

USB Error Interrupt (USBERRINT) — R/WC.

0 = No error condition.

1 = The Host controller sets this bit to 1 when completion of a USB transaction results in

an error condition (e.g., error counter underflow). If the TD on which the error

interrupt occurred also had its IOC bit set, both this bit and Bit 0 are set. See the

EHCI specification for a list of the USB errors that will result in this interrupt being

asserted.

USB Interrupt (USBINT) — R/WC.

0 = No completion of a USB transact ion whose Transfer D escriptor had its IOC bit set.

No short packet is dete cted.

1 = The Host controlle r sets this bit to 1 when the cause of an interrupt is a completion

of a USB transaction whose Transfer Descriptor had its IOC bit set.

The Host controller also sets this bit to 1 when a short packet is detected (actual

number of bytes received was less than the expected number of bytes).

Bit Description

EHCI Controller Registers (D29:F7, D26:F7)

612 Intel® ICH8 Family Datasheet

15.2.2.3 USB2.0_INTR—USB 2.0 Interrupt Enable Register

Offset: MEM_BASE + 28h–2Bh Attribute: R/W

Default Value: 00000000h Size: 32 bits

This register enables and disables reporting of the corresponding interrupt to the

software. When a bit is set and the corresponding interrupt is active, an interrupt is

generated to the host. Interrupt sources that are disabled in this register still appear in

the USB2.0_STS Register to allow the softw are to poll for events. Each interrupt enable

bit description indicates whether it is dependent on the interrupt threshold mechanism

(see Section 4 of the EHCI specification), or not.

Bit Description

31:6 Reserved. These bits are reserved and should be 0 when writing this register.

Interrupt on Async Advance Enable — R/W.

0 = Disable.

1 = Enable. When this bit is a 1, and the Interrupt on Async Advance bit (D29:F7,

D26:F7:CAPLENGTH + 24h, bit 5) in the USB2.0_STS register is a 1, the host

controller will issue an interrupt at the next interrupt threshold. The interrupt is

acknowledged by software clearing the Interru pt on Async Advance bit.

Host System Error Enable — R/W.

0 = Disable.

1 = Enable. When this bit is a 1, and the Host System Error Status bit (D29:F7,

D26:F7:CAPLENGTH + 24h, bit 4) in the USB2.0_STS register is a 1, the host

controller will issue an interrupt. The interrupt is acknowledged by software

clearing the Host System Error bit.

Frame List Rollover Enable — R/W.

0 = Disable.

1 = Enable. When this bit is a 1, and the Frame List Rollover bit (D29:F7,

D26:F7:CAPLENGTH + 24h, bit 3) in the USB2.0_STS register is a 1, the host

controller will issue an interrupt. The interrupt is acknowledged by software

clearing the F rame List Rollover bit.

Port Change Interrupt Enable — R/W.

0 = Disable.

1 = Enable. When this bit is a 1, and the Port Change Detect bit (D29:F7,

D26:F7:CAPLENGTH + 24h, bit 2) in the USB2.0_STS register is a 1, the host

controller will issue an interrupt. The interrupt is acknowledged by software

clearing the Port Change Detect bit.

USB Error Interrupt Enable — R/W.

0 = Disable.

1 = Enable. When this bit is a 1, and the USBERRINT bit (D2 9:F7, D26: F7:CAPLENGTH

+ 24h, bit 1) in the USB2.0_STS register is a 1, the host controller will issue an

interrupt at the next interrupt threshold. The interrupt is acknowledged by software

by clearing the USBERRINT bit in the USB2.0_STS register.

USB Interrupt Enable — R/W.

0 = Disable.

1 = Enable. When this bit is a 1, and the USBINT bit (D29:F7, D26:F7:CAPLENGTH +

24h, bit 0) in the USB2.0_STS register is a 1, the host controller will issue an

interrupt at the next interrupt threshold. The interrupt is acknowledged by software

by clearing the USBINT bit in the USB2.0_STS register.

Intel® ICH8 Family Datasheet 613

EHCI Controller Registers (D29:F7, D26:F7)

15.2.2.4 FRINDEX—Frame Index Register

Offset: MEM_BASE + 2Ch–2Fh Attribute: R/W

Default Value: 00000000h Size: 32 bits

The SOF frame number v alue for the bus SOF token is derived or alternatively managed

from this register. Refer to Section 4 of the EHCI specification for a detailed explanation

of the SOF value management requirements on the host controller. The value of

FRINDEX must be within 125 µs (1 micro-frame) ahead of the SOF token value. The

SOF value may be implemented as an 11-bit shadow register. For this discussion, this

shadow register is 11 bits and is named SOFV. SOFV updates every 8 micro-frames. (1

millisecond). An example implementation to achieve this behavior is to increment SOFV

each time the FRINDEX[2:0] increments from 0 to 1.

Software must use the value of FRINDEX to derive the current micro-frame number,

both for high-speed isochronous scheduling purposes and to provide the get micro-

fram e nu mb er function required to cl ient dr ivers. Therefore , the value of FRINDEX and

the value of SOFV must be kept consistent if chip is reset or software writes to

FRINDEX. Writes to FRINDEX must also write-through FRINDEX[13:3] to

SOFV[10:0]. In order to keep the update as simple as possible, software should never

write a FRINDEX value where the three least significant bits are 111b or 000b.

Note: This register is used by the host controller to index into the periodic frame list. The

used to select a particular entry in the Periodic Frame List during periodic schedule

execution. The number of bits used for the inde x is fixed at 10 for the ICH8 since it only

supports 1024-entry frame lists. This register must be written as a dword. Word and

byte writes produce undefined results. This register cannot be written unless the Host

controller is in the Halted state as indicated by the HCHalted bit (D29:F7,

D26:F7:CAPLENGTH + 24h, bit 12). A write to this register while the Run/Stop bit

(D29:F7, D26:F7:CAPLENGTH + 20h, bit 0) is set to a 1 (USB2.0_CMD register)

produces undefined results. Writes to this register also effect the SOF value. See

Section 4 of the EHCI specification for details.

Bit Description

31:14 Reserved

13:0

Frame List Current Index/Frame Number — R/W. The value in this register

increments at the end of each time frame (e.g., micro-frame).

Bits [12:3] are used for the Frame List current index. This means that each location of

the frame list is access ed 8 times (frames or micro-frames) before moving to the next

index.

EHCI Controller Registers (D29:F7, D26:F7)

614 Intel® ICH8 Family Datasheet

15.2.2.5 CTRLDSSEGMENT—Control Data Structure Segment

Offset: MEM_BASE + 30h–33h Attribute: R/W, RO

Default Value: 00000000h Size: 32 bits

This 32-bit register corresponds to the most significant address bits [63:32] for all

EHCI data structures. Since the ICH8 hardwires the 64-bit Addressing Capability field in

HCCPARAMS to 1, then this register is used with the link pointers to construct 64-bit

addresses to EHCI control data structures. This register is concatenated with the link

pointer from either the PERIODICLISTBASE, ASYNCLISTADDR, or any control data

structure link field to construct a 64-bit address. This register allows the host software

to locate all control data structures within the same 4 GB memory segment.

15.2.2.6 PERIODICLISTBASE—Periodic Frame List Base Address

Offset: MEM_BASE + 34h–37h Attribute: R/W

Default Value: 00000000h Size: 32 bits

This 32-bit register contains the beginning address of the Periodic Frame List in the

system memory. Since the ICH8 host controller operates in 64-bit mode (as indicated

by the 1 in the 64-bit Addressing Capability field in the HCCSPARAMS register) (offset

08h, bit 0), then the most significant 32 bits of every control data structure address

comes from the CTRLDSSEGMENT register. HCD loads this register prior to starting the

schedule execution by the host controller. The memory structure referenced by this

physical memory pointer is assumed to be 4-Kbyte aligned. The contents of this

controller to step through the Periodic Frame List in sequence.

Bit Description

31:12 Upper Address[63:44] — RO. Hardwired to 0s. The ICH8 EHC is only capable of

generating addresses up to 16 terabytes (44 bits of address).

11:0 Upper Address[43:32] — R/W. This 12-bit field corresponds to address bits 43:32 when

forming a control data structure address.

Bit Description

31:12 Base Address (Low) — R/W. These bits correspond to memory address signals

[31:12], respectively.

11:0 Reserved. Must be written as 0s. During runtime, the value of these bits are undefined.

Intel® ICH8 Family Datasheet 615

EHCI Controller Registers (D29:F7, D26:F7)

15.2.2.7 ASYNCLISTADDR—Current Asynchronous List Address

Offset: MEM_BASE + 38h–3Bh Attribute: R/W

Default Value: 00000000h Size: 32 bits

This 32-bit register contains the address of the next asynchronous queue head to be

executed. Since the ICH8 host controller operates in 64-bit mode (as indicated by a 1 in

64-bit Addressing Capability field in the HCCPARAMS register) (offset 08h, bit 0), then

the most significant 32 bits of every control data structure address comes from the

CTRLDSSEGMENT register (offset 08h). Bits [4:0 ] of this register cannot be modified by

system software and will always return 0’ s when read. The memory structure

referenc ed by this physical me mory pointer is assumed to be 32-byte aligned.

15.2.2.8 CONFIGFLAG—Configure Flag Register

Offset: MEM_BASE + 60h–63h Attribute: R/W

Default Value: 00000000h Size: 32 bits

This register is in the suspend power well. It is only reset by hardware when the

suspend power is initially applied or in response to a host controller reset.

Bit Description

31:5 Link Pointer Low (LPL) — R/W. These bits correspond to memory address signals

[31:5], respectively. This field may only reference a Queue Head (QH).

4:0 Reserved. These bits are reserved and their value has no effect on operation.

Bit Description

31:1 Reserved. Read from this field will always return 0.

Configure Flag (CF) — R/W. Host software sets this bit as the last action in its process

of configuring the Host controller. This bit controls the default port -routing control logic.

Bit values and side-effects are listed below. See section 4 of the EHCI spec for

operation d e tails.

0 = Port routing control logic default-routes each port to the UHCIs (default).

1 = Port routing control logic default-routes all ports to this host controller.

EHCI Controller Registers (D29:F7, D26:F7)

616 Intel® ICH8 Family Datasheet

15.2.2.9 PORTSC—Port N Status and Control Register

Offset: Port 0, Port 6: MEM_BASE + 64h–67h

Port 1, Port 7: MEM_BASE + 68–6Bh

Port 2, Port 8: MEM_BASE + 6C–6Fh

Port 3, Port 9: MEM_BASE + 70–73h

Port 4: MEM_BASE + 74–77h (Device 29 Only)

Port 5: MEM_BASE + 78–7Bh (Device 29 Only)

Attribute: R/W, R/WC, RO

Default Value: 00003000h Size: 32 bits

A host controller must implement one or more port registers. Softw are uses the N_Port

information from the Structural Parameters Register to determine how many ports

need to be serviced. All ports have the structure defined below. Software must not

write to unreported Port Status and Control R e gisters.

This register is in the suspend power well. It is only reset by hardware when the

suspend power is initially applied or in response to a host controller reset. The initial

conditions of a port are:

• No device connected

• Port disabled.

When a device is attached, the port state transitions to the attached state and system

software will process this as with any status change notification. Refer to Section 4 of

the EHCI specification for operational requirements for how change events interact with

port suspend mode.

Bit Description

31:23 Reserved. These bits are reserved for future use and will return a value of 0’s when

read.

Wake on Overcurrent Enable (WKOC_E) — R/W.

0 = Disable. (Default)

1 = Enable. Writing this bit to a 1 enables the setting of the PME Status bit in the Power

Management Control/Status Register (offset 54, bit 15) when the overcurrent

Active bit (bit 4 of this register) is set.

Wake on Disconnect Enable (WKDSCNNT_E) — R/W.

0 = Disable. (Default)

1 = Enable. Writing this bit to a 1 enables the setting of the PME Status bit in the Power

Management Control/Status Register (offset 54, bit 15) when the Current Connect

Status changes from connected to discon ne ct ed (i.e., bit 0 of this r egi st er ch ange s

from 1 to 0).

Wake on Connect Enable (WKCNNT_E) — R/W.

0 = Disable. (Default)

1 = Enable. Writing this bit to a 1 enables the setting of the PME Status bit in the Power

Management Control/Status Register (offset 54, bit 15) when the Current Connect

Status changes from di sc onn ect ed to connected (i.e., bit 0 of this register changes

from 0 to 1).

Intel® ICH8 Family Datasheet 617

EHCI Controller Registers (D29:F7, D26:F7)

19:16

Port Test Control — R/W. When this field is 0s, the port is NOT operating in a test

mode. A non-zero value indicates that it is operating in test mode and the specific test

mode is indicated by the specific value. The encoding of the test mode bits are (0110b

– 1111b are reserved):

Refer to USB Specification Revision 2.0, Chapter 7 for details on each test mode.

15:14 Reserved — R/W. Should be written to =00b.

Port Owner — R/W. Default = 1b. This bit unconditionally goes to a 0 when the

Configured Flag bit in the USB2.0_CMD register makes a 0 to 1 transition.

System software uses this field to release ownership of the port to a selected host

controller (in the event that the attached device is not a high-speed device). Software

writes a 1 to this bit when the attached device is not a high-speed device. A 1 in this bit

means that a companion host controller owns and controls the port. See Section 4 of

the EHCI Specification for operational details.

12 Port Power (PP) — RO . R e ad-on ly with a v al ue of 1. This in dicate s that the port does

have power.

11:10

Line Status— RO.These bits reflect the current logical levels of the D+ (bit 11) and D–

(bit 10) signal lines. These bits are used for detection of low-speed USB devices prior to

the port reset and enable sequence. This field is valid only when the port enable bit is 0

and the current connect status bit is set to a 1.

00 = SE0

10 = J-state

01 = K-state

11 = Undefined

9 Reserved. This bit will return a 0 when read.

Bit Description

Value Maximum Interrupt Inte rval

0000b Test mode not enabled (default)

0001b Test J_STATE

0010b Test K_STATE

0011b Test SE0_NAK

0100b Test Packet

0101b FORCE_ENABLE

EHCI Controller Registers (D29:F7, D26:F7)

618 Intel® ICH8 Family Datasheet

Port Reset — R/W. Default = 0. When software writes a 1 to this bit (from a 0), the

bus reset sequence as defined in the USB Specification, Revision 2.0 is started.

Software write s a 0 to this bit t o terminate the bus re set sequence. Softw are must keep

this bit at a 1 long enough to assure the reset sequence completes as specified in th e

USB Specification, Revision 2.0.

1 = Port is in Reset.

0 = Port is not in Reset.

NOTE: When software writes a 0 to this bit, there may be a delay be fore the bi t status

changes to a 0. The bit status will not read as a 0 until after the reset has

completed. If the port is in high-speed mode after reset is complete, the host

controller will automatically enable this port (e.g., set the Port Enable bit to a

1). A host controller must terminate the reset and stabilize the state of t he port

within 2 milliseconds of software transitioning this bit from 0 to 1.

For example: if the port detects that the attached device is high-speed during

reset, then the host controller must have the port in the enabled state within

2 ms of software writing this bit to a 0. The HCHalted bit (D29:F7,

D26:F7:CAPLENGTH + 24h, bit 12) in the USB2.0_STS register should be a 0

before software attempts to use this bit. The ho st controller ma y hold Port R eset

asserted to a 1 when the HCHalted bit is a 1. This bit is 0 if Port Power is 0

NOTE: System software should not attempt to reset a port if the HCHalted bit in the

USB2.0_STS register is a 1. Doing so will result in undefined behavior.

Suspend — R/W.

0 = Port not in suspend state.(Defaul t)

1 = Port in suspend state.

Port Enabled Bit and Suspend bit of this register define the port states as follows:

When in suspend state, downstream propagation of data is blocked on this port, except

for port reset. Note that the bit status does not change until the por t is suspended and

that there may be a delay in suspending a port depending on the activity on the port.

The host controller will unconditionally set this bit to a 0 when software sets the Force

Port Resume bit to a 0 (from a 1). A write of 0 to this bit is ignored by the host

controller.

If host softw are sets this bi t to a 1 when the port is not enabled (i.e. , P ort enabled bit is

a 0) the results are undefined.

Bit Description

Port Enabled Suspend Port State

0XDisabled

10Enabled

11Suspend

Intel® ICH8 Family Datasheet 619

EHCI Controller Registers (D29:F7, D26:F7)

Force Port Resume — R/W.

0 = No resume (K-state) detected/driven on port. (Default)

1 = Resume detected/driven on port. Software sets this bit to a 1 to drive resume

signaling. The Host controller sets this bit to a 1 if a J-to-K transition is detected

while the port is in the Suspend state. When this bit transitions to a 1 because a J-

to-K transition is detected, the Port Change Detect bit (D29:F7,

D26:F7:CAPLENGTH + 24h, bit 2) in the USB2.0_STS register is also set to a 1. If

software sets this bit to a 1, th e host controller must not set the Port Change

Detect bit.

NOTE: When the EHCI controller owns the port, the resume sequence follows the

defined sequence documented in the USB Specification, Revision 2.0. The

resume signaling (Full-speed 'K') is driven on the port as long as this bit

remains a 1. Software must appropriately time the Resume and set this bit to a

0 when the appropriate amount of time has elapsed. Writing a 0 (from 1)

causes the port to return to high-speed mode (forcing the bus below the port

into a high-speed idle). This bit will remain a 1 until the port has switched to the

high-speed idle.

Overcurrent Change — R/WC. The functionality of this bit is not dependent upon the

port owner. Software clears this bit by writing a 1 to it.

0 = No change. (Default)

1 = There is a change to Overcurrent Active.

Overcurrent Active — RO.

0 = This port does not have an overcurrent condition. (Default)

1 = This port currently has an overcurrent condition. This bit will automatically

transition from 1 to 0 when the over current condition is removed. The ICH8

automatically disabl es the port when the overcurrent active bit is 1.

Port Enable/Disable Change — R/WC. For the root hub, this bit gets set to a 1 only

when a port is disabled due to the appropriate conditions existing at the EOF2 point

(See Chapter 11 of the USB Specification for the definition of a port error). This bit is

not set due to the Disabled-to-Enabled transition, nor due to a disconnect. Software

clears this bit by writing a 1 to it .

0 = No change in status. (Default).

1 = Port enabled/disabled status has changed.

Bit Description

EHCI Controller Registers (D29:F7, D26:F7)

620 Intel® ICH8 Family Datasheet

15.2.3 USB 2.0-Based Debug Port Register

The Debug port’s registers are located in the same memory area, defined by the Base

Address Register (MEM_BASE), as the standard EHCI registers. The base offset for the

debug port registers (A0h) is declared in the Debug P ort Base Offset Capability R egister

at Configuration offset 5Ah (D29:F7, D26:F7:offset 5Ah). The specific EHCI port that

supports this debug capability (Port 0 for D29:F7 and P ort 6 for D26:F7) is indicated by

a 4-bit field (bits 20–23) in the HCSP ARAMS register of the EHCI controller. The address

map of the Debug Port registers is shown in Table 136.

NOTES:

1. All of these registers are implemented in the core well and reset by PLTRST#, EHC

HCRESET, and a EHC D3-to-D0 transition.

2. The hardware associated with this register provides no checks to ensure that software

programs the interface correctly. How the hardware behaves when programmed invalidlly

is undefined.

Port Enabled/Disabled — R/W. Ports can only be enabled by the host controller as a

part of the reset and enable. Software cannot enable a port by writing a 1 to this bit.

Ports can be disabled by either a fault condition (disconnect event or ot her fault

condition) or by host software. Note that the bit status does not change until the port

state actually changes. There may be a delay in disabling or enabling a port due to

other host controller and bus events.

0 = Disable

1 = Enable (Default)

Connect Status Change — R/WC. This bit indicates a change has occurred in the

port’s Current Connect Status. Software sets this bit to 0 by writing a 1 to it.

0 = No change (Default).

1 = Change in Current Connect Status. The host controller sets this bit for all changes

to the port device connect status, even if system software has not cleared an

existing connect status change. For example, the insertion status changes twice

before system software has cleared the changed condition, hub hardware will be

“setting” an already-set bit (i.e., the bit will remain set).

Current Connect Status — RO. This value reflects the current state of the port, and

may not correspond directly to the event that caused the Connect Status Change bit

(Bit 1) to be set.

0 = No device is present. (Default)

1 = Device is present on port.

Bit Description

Table 136. Debug Port Register Address Map

MEM_BASE +

Offset Mnemonic Register Name Default Type

A0–A3h CNTL_STS Control/Status 00000000h R/W , R/WC,

RO, WO

A4–A7h USBPID USB PIDs 00000000h R/W, RO

A8–ABh DATABUF[3:0] Data Buffer (Bytes 3:0) 00000000h R/W

AC–AFh DATABUF[7:4] Data Buffer (Bytes 7:4) 00000000h R/W

B0–B3h CONFIG Configuration 00007F01h R/W

Intel® ICH8 Family Datasheet 621

EHCI Controller Registers (D29:F7, D26:F7)

15.2.3.1 CNTL_STS—Control/Status Register

Offset: MEM_BASE + A0h Attribute: R/W, R/WC, RO, WO

Default Value: 0000h Size: 32 bits

Bit Description

31 Reserved

OWNER_CNT — R/W.

0 = Ownership of the debug port is NOT forced to the EHCI controller (Default)

1 = Ownership of the debug port is forced to the EHCI controller (i .e. immediately

taken away from the companion Classic USB Host controller) If the port was

already owned by the EHCI controller, then setting this bit has no effect. This bit

overrides all of the ownership-related bits in the standard EHCI registers.

29 Reserved

ENABLED_CNT — R/W.

0 = Software can clear this by writing a 0 to it. The hardware clears this bit for the

same conditions where the Port Enable/Disable Change bit (in the PORTSC

1 = Debug port is enabled for operation. Software can directly se t this bit if th e port is

already enabled in the associated PORTSC register (this is enforced by the

hardware).

27:17 Reserved

16 DONE_STS — R/WC. Software can clear this by writing a 1 to it.

0 = Request Not complete

1 = Set by ha rdware to indicate that the request is complete.

15:12 LINK_ID_STS — RO. This field ident if ies the link interface.

0h = Hardwired. Indicates that it is a USB Debug Port.

11 Reserved. This bit returns 0 when read. Wr ites have no effect.

10 IN_USE_CNT — R/W. Set by software to indicate that the port is in use. Cleared by

software to indicate that t he port is free an d may be used by other software. Thi s bit is

cleared after reset. (This bit has no affect on hardware.)

9:7

EXCEPTION_STS — RO. This field indicates the exception when the

ERROR_GOOD#_STS bit is set. This field should be ignored if the ERROR_GOOD#_STS

bit is 0.

000 =No Error. (Default)

Note: this should not be seen, since this field should only be checked if there is

an error.

001 =Transaction error: indicates the USB 2. 0 transaction had an error (CRC, bad PID,

timeout, etc .)

010 =Hardware error. Request was attempted (or in progress) when port was

suspended or reset.

All Other combinations are reserved

ERROR_GOOD#_STS — RO.

0 = Hardware clears this bit to 0 after the proper completion of a read or write.

(Default)

1 = Error has occurred. Details on the nature of the error are provided in the Exception

field.

EHCI Controller Registers (D29:F7, D26:F7)

622 Intel® ICH8 Family Datasheet

NOTES:

1. Software should do Read-Modify- Write operations to this register to preserve the contents

of bits not being modified. This include Reserved bits.

2. To preserve th e usage of RESERVED bits in the future, software should always write the

same value read from the bit until it is defined. Reserved bits will always return 0 when

read.

15.2.3.2 USBPID—USB PIDs Register

Offset: MEM_BASE + A4h Attribute: R/W, RO

Default Value: 0000h Size: 32 bits

This Dword register is used to communicate PID information between the USB debug

driver and the USB debug port. The debug port uses some of these fields to generate

USB packets, and uses other fields to return PID information to the USB debug driver.

GO_CNT — WO.

0 = Hardware clears this bit when hardware sets the DONE_STS bit. (Default)

1 = Causes hardware to perform a read or write request.

NOTE: Writing a 1 to this bit when it is already set may result in undefined beh avio r.

WRITE_READ#_CNT — R/W. Software clears this bit to indicate that the current

request is a read. Software sets this bit to indicate that th e current request is a write.

0 = Read (Default)

1 = Write

3:0

DATA_LEN_CNT — R/W. This field is used to indicate the size of the data to be

transferred. default = 0h.

For write oper ations, this field is set by softw are to indicate to the hardware how many

bytes of data in Data Buffer are to be transferred to the console. A value of 0h

indicates that a zero-length packet should be sent. A value of 1–8 indicates 1–8 bytes

are to be transferred. Values 9–Fh are invalid and how hardware behaves if used is

undefined.

For read operations, this field is set by hardware to indicate to software how many

bytes in Data Buffer are valid in response to a read operation. A value of 0h indicates

that a zero length packet was returned and the state of Data Buffer is not defined. A

value of 1–8 indicates 1–8 bytes were received. Hardware is not allowed to return

values 9–Fh.

The transferring of data always starts with byte 0 in the data area and moves toward

byte 7 until the transfer size is reached.

Bit Description

31:24 Reserved: These bits will return 0 when read. Writes will have no effect.

23:16

RECEIVED_PID_STS[23:16] — RO. Hardware updates this field with the received

PID for transactions in either direction. When the controller is writing data, this field

is updated with the handshake PID that is received from the device. When the host

controller is reading data, this field is updated with the data packet PID (if the device

sent data), or the handshake PID (if the device NAKs the request). This field is valid

when the hardware clears the GO_DONE#_CNT bit.

15:8 SEND_PID_CNT[15:8] — R/W. Hardware sends this PID to begin the data packet

when sending data to USB (i.e., WRITE_READ#_CNT is asserted). Software typi cally

sets this field to either DATA0 or DATA1 PID values.

7:0 TOKEN_PID_CNT[7:0] — R/W. Hardware sends this PID as the Token PID for each

USB transaction. Software typically sets this field to either IN, OUT, or SETUP PID

values.

Intel® ICH8 Family Datasheet 623

EHCI Controller Registers (D29:F7, D26:F7)

15.2.3.3 DATABUF[7:0]—Data Buffer Bytes[7:0] Register

Offset: MEM_BASE + A8h–AFh Attribute: R/W

Default Value: 0000000000000000h Size: 6 4 bits

This register can be accessed as 8 separate 8-bit registers or 2 separate 32-bit register.

15.2.3.4 CONFIG—Configuration Register

Offset: MEM_BASE + B0–B3h Attribute: R/W

Default Value: 00007F01h Size: 32 bits

§ §

Bit Description

63:0

DATABUFFER[63:0] — R/W. This field is the 8 bytes of the data buffer. Bits 7:0

correspond to least significant byte (byte 0). Bits 63:56 correspond to the most

significant byte (byte 7).

The bytes in the Data Buffer must be written with data before software initiates a write

request. For a read request, the Data Buffer contains valid data when DONE_STS bit

(offset A0, bit 16) is cleared by the hardware, ERROR_GOOD#_STS (offset A0, bit 6)

is cleared by the hardware, and the DATA_LENGTH_CNT field (offset A0, bits 3:0)

indicates the number of bytes that are valid.

Bit Description

31:15 Reserved

14:8 USB_ADDRESS_CNF — R/W. This 7-bit field identifies the USB device address used

by the controller for all Token PID generation. (Default = 7F h)

7:4 Reserved

3:0 USB_ENDPOINT_CNF — R/W. This 4-bit field identifies the endpoint used by the

controller for all Token PID generation. (Default = 01h)

EHCI Controller Registers (D29:F7, D26:F7)

624 Intel® ICH8 Family Datasheet

Intel® ICH8 Family Datasheet 625

SMBus Controller Registers (D31:F3)

16 SMBus Controller Registers

(D31:F3)

16.1 PCI Configuration Registers (SMBUS—D31:F3)

NOTE: Registers that are not shown should be treated as Reserved (See Section 6.2 for details).

16.1.1 VID—Vendor Identification Register (SMBUS—D31:F3)

Address: 00h–01h Attribute: RO

Default Value: 8086h Size: 16 bits

Table 137. SMBus Controller PCI Register Address Map (SMBUS—D31:F3)

Offset Mnemonic Register Name Default Type

00h–01h VID Vendor Identification 8086 RO

02h–03h DID Device Identification See register

description RO

04h–05h PCICMD PCI Command 0000h R/W, RO

06h–07h PCISTS PCI Status 0280h RO, R/WC

08h RID Revision Identifica tion See register

description RO

09h PI Programming Interface 00h RO

0Ah SCC Sub Class Code 05h RO

0Bh BCC Base Class Code 0Ch RO

14h SMBMBAR1 Memory Based Address Register 1

(Bit 35:32) 00000000h RO

20h–23h SMB_BASE SMBus Base Address 00000001h R/W, RO

2Ch–2Dh SVID Subsystem Vendor Identification 00h RO

2Eh–2Fh SID Subsystem Identification 00h R/WO

3Ch INT_LN Interrupt Line 00h R/W

3Dh INT_PN Interrupt Pin See register

description RO

40h HOSTC Host Configuration 00h R/W

Bit Description

15:0 Vendor ID — RO. This is a 16-bit value assigned to Intel

SMBus Controller Registers (D31:F3)

626 Intel® ICH8 Family Datasheet

16.1.2 DID—Device Identification Register (SMBUS—D31:F3)

Address: 02h–03h Attribute: RO

Default Value: See bit description Size: 16 bits

16.1.3 PCICMD—PCI Command Register (SMBUS—D31:F3)

Address: 04h–05h Attributes: RO, R/W

Default Value: 0000h Size: 16 bits

Bit Description

15:0 Device ID — RO. This is a 16-bit value assigned to the Intel® ICH8 SMBus controller.

Refer to the Intel® ICH8 Family Specification Update for the value of the Device ID

Bit Description

15:11 Reserved

10 Interrupt Disable — R/W.

0 = Enable

1 = Disables SMB us to assert its PIRQB# signal.

9 Fast Back to Back Enable (FBE) — RO. Hardwired to 0.

8SERR# Enable (SERR_EN) — R/W.

0 = Enables SERR# generation.

1 = Disables SERR# generation.

7 Wait Cycle Control (WCC) — RO. Hardwired to 0.

6Parity Error Response (PER) — R/W.

0 = Disable

1 = Sets Detected Parity Error bit (D31:F3:06, bit 15) when a parity error is detected.

5 VGA Palette Snoop (VPS) — RO. Hardwired to 0.

4 Postable Memory Write Enable (PMWE) — RO. Hardwired to 0.

3 Special Cycle Enable (SCE) — RO. Hardwired to 0.

2 Bus Master Enable (BME) — RO. Hardwired to 0.

1Memory Space Enable (MSE) — R/W.

0 = Disables memory mapped configuration space.

1 = Enables memory mapped configuration space.

I/O Space Enable (IOSE) — R/W.

0 = Disable

1 = Enables access to the SM Bus I/O space registers as defined by the Base Address

Intel® ICH8 Family Datasheet 627

SMBus Controller Registers (D31:F3)

16.1.4 PCISTS—PCI Status Register (SMBUS—D31:F3)

Address: 06h–07h Attributes: RO, R/WC

Default Value: 0280h Size: 16 bits

Note: For the writable bits, software must write a 1 to clear bits that are set. Writing a 0 to

the bit has no effect.

16.1.5 RID—Revision Identification Register (SMBUS—D31:F3)

Offset Address: 08h Attribute: RO

Default Value: See bit description Size: 8 bits

Bit Description

15 Detected Parity Error (DPE) — R/WC.

0 = No parity error detected.

1 = Parity error detected.

14 Signaled System Error (SSE) — R/WC.

0 = No system error detected.

1 = System error detected.

13 Received Master Abort (RMA) — RO. Hardwired to 0.

12 Received Target Abort (RTA) — RO. Hardwired to 0.

Signaled Target Abort (STA) — R/WC.

0 = ICH8 did Not terminate transaction for this function with a target abort.

1 = The function is targeted with a transaction that the Intel® ICH8 terminates with a

target abort.

10:9 DEVSEL# Timing Status (DEVT) — RO. This 2-bit field defines the timing for DEVSEL#

assertion for positive decode.

01 = Medium timing.

8 Data Parity Error Detected (DPED) — RO. Hardwired to 0.

7 Fast Back to Back Capable (FB2BC) — RO. Hardwired to 1.

6 User Definable Features (UDF) — RO. Hardwired to 0.

5 66 MHz Capable (66MHZ_CAP) — RO. Hardwired to 0.

4Capabilities List (CAP_LIST) — RO. Hardwired to 0 because there are no capability list

structures in this function

3Interrupt Status (INTS) — RO. This bit indicates that an interrupt is pending. It is

independent from the state of the Interrupt Enable bit in the PCI Command register.

2:0 Reserved

Bit Description

7:0 R evision ID — RO. Refer to the Intel® I/O Controller Hub 8 (ICH8) Fami ly Specification

Update for the value of the Revision ID Register.

SMBus Controller Registers (D31:F3)

628 Intel® ICH8 Family Datasheet

16.1.6 PI—Programming Interface Register (SMBUS—D31:F3)

Offset Address: 09h Attribute: RO

Default Value: 00h Size: 8 bits

16.1.7 SCC—Sub Class Code Register (SMBUS—D31:F3)

Address Offset: 0Ah Attributes: RO

Default Value: 05h Size: 8 bits

16.1.8 BCC—Base Class Code Register (SMBUS—D31:F3)

Address Offset: 0Bh Attributes: RO

Default Value: 0Ch Size: 8 bits

16.1.9 SMBMBAR0 – D31_F3_SMBu s Memory Base Address 0

Address Offset: 10h Attributes: R/W

Default Value: 00000000h Size: 32 bits

Bit Description

7:0 Reserved

Bit Description

7:0 Sub Class Code (SCC) — RO.

05h = SM Bus serial controller

Bit Description

7:0 Base Class Code (BCC) — RO.

0Ch = Serial controller.

Bit Description

31:8 Base Address: Provides the 32 byte t system memory base address for the Intel ICH8

SMB logic.

7:1 Reserved

0Memory Spac e Indicator: This re ad-only bit alwa ys is 0, indicatin g that the SMB lo gic

is Memory mapped.

Intel® ICH8 Family Datasheet 629

SMBus Controller Registers (D31:F3)

16.1.10 SMB_BASE—SMBUS Base Address Register

(SMBUS—D31:F3)

Address Offset: 20–23h Attribute: R/W, RO

Default Value: 00000001h S i ze: 32-bits

16.1.11 SVID — Subsystem Vendor Identification Register

(SMBUS—D31:F2/F4)

Address Offset: 2Ch–2Dh Attribute: RO

Default Value: 0000h Size: 16 bits

Lockable: No Power Well: Core

16.1.12 SID — Subsystem Identification Register

(SMBUS—D31:F2/F4)

Address Offset: 2Eh–2Fh Attribute: R/WO

Default Value: 00h Size: 16 bits

Lockable: No Power Well: Core

Bit Description

31:16 Reserved — RO

15:5 Base Address — R/W. This field provides the 32-byte system I/O base address for th e

ICH8 SMB logic.

4:1 Reserved — RO

0 IO Space Indicator — RO. Hardwired to 1 indicating that the SMB logic is I/O mapped.

Bit Description

15:0

Subsystem Ve ndor ID (SVID) — RO. The SVID register, in combination with the

Subsystem ID (SID) register, enables the operating system (OS) to distinguish

subsystems from each other. The value returned by reads to this register is the same as

that which was written by BIOS into the IDE SVID register.

NOTE: Software can write to this register only once per core well reset. Writes should

be done as a single 16-bit cycle.

Bit Description

15:0

Subsystem ID (SID) — RO. The SID register, in combination with the SVID register,

enables the operating system (OS) to distinguish subsystems from each other. The

value returned by reads to this register is the same as that which was written by BIOS

into the IDE SID register.

NOTE: Software can write to this register only once per core well reset. Writes should

be done as a single 16-bit cycle.

SMBus Controller Registers (D31:F3)

630 Intel® ICH8 Family Datasheet

16.1.13 INT_LN—Interrupt Line Register (SMBUS—D31:F3)

Address Offset: 3Ch Attributes: R/W

Default Value: 00h Size: 8 bits

16.1.14 INT_PN—Interrupt Pin Register (SMBUS—D31:F3)

Address Offset: 3Dh Attributes: RO

Default Value: See description Size: 8 bits

16.1.15 HOSTC—Host Configuration Register (SMBUS—D31:F3)

Address Offset: 40h Attribute: R/W

Default Value: 00h Size: 8 bits

Bit Description

7:0 Interrupt Line (INT_LN) — R/W. This data is not used by the ICH8. It is to

communicate to software the interrupt line that the inte rrupt pin is connected to

PIRQB#.

Bit Description

7:0 Interrupt PIN (INT_PN) — RO. This reflects the value of D31IP.SMIP in chipset

configuration space.

Bit Description

7:4 Reserved

3Soft SMBUS Reset (SSRESET)— R/W.

0 = The HW will reset this bit to 0 when SMBus reset operation is completed.

1 = The SMBbus state ma chine and logic in ICH8 is reset.

I2C_EN — R/W.

0 = SMBus behavior.

1 = The ICH8 is enable d to communicate with I2C devices. This will change the

formatting of some commands.

SMB_SMI_EN — R/W.

0 = SMBus interrupts will not generate an SMI#.

1 = Any source of an SMB interrupt will instead be routed to generate an SMI#. Refer

to Section 5.20.4 (Interrupts / SMI#).

This bit needs to be set for SMBALERT# to be enabled.

SMBus Host Enable (HST_EN) — R/W.

0 = Disable the SMBus Host controller.

1 = Enable. The SMB Host controller interface is enabled to execute commands. The

INTREN bit (offset SMBASE + 02h, bit 0) needs to be enabled for the SMB Host

controller to interrupt or SMI#. Note that the SMB Host controller will not respond

to any new requests until all interrupt requests have been cleared.

Intel® ICH8 Family Datasheet 631

SMBus Controller Registers (D31:F3)

16.2 SMBus I/O and Memory Mapped I/O Registers

Table 138. SMBus I/O and Memory Mapped I/O Register Address Map

SMB_BASE

+ Offset Mnemonic Register Name Default Type

00h HST_STS Host Status 00h R/WC, RO,

R/WC (special)

02h HST_CNT Host Control 00h R/W, WO

03h HST_CMD Host Command 00h R/W

04h XMIT_SLVA Transmit Slave Address 00h R/W

05h HST_D0 Host Data 0 00h R/W

06h HST_D1 Host Data 1 00h R/W

07h HOST_BLOCK_DB Host Block Data Byte 00h R/W

08h PEC Packet Error Check 00h R/W

09h RCV_SLV A Receive Slave Address 44h R/W

0Ah–0Bh SL V _D ATA Receive Slave Data 0000h RO

0Ch AUX_STS Auxiliary Status 00h R/WC, RO

0Dh AUX_CTL Auxiliary Control 00h R/W

0Eh SMLINK_PIN_CTL SMLink Pin Control (TCO

Compatible Mode) See register

description R/W, RO

0Fh SMBUS_PIN_CTL SMBus Pin Control See register

description R/W, RO

10h SLV_STS Slave Status 00h R/WC

11h SLV_CMD Slave Command 00h R/W

14h NOTIFY_DADDR Notify Device Address 00h RO

16h NOTIFY_DLOW Notify Data Low Byte 00h RO

17h NOTIFY_DHIGH Notify Data High Byte 00h RO

SMBus Controller Registers (D31:F3)

632 Intel® ICH8 Family Datasheet

16.2.1 HST_STS—Host Status Register (SMBUS—D31:F3)

Default Value: 00h Size: 8-bits

All status bits are set by hardware and cleared by the software writing a one to the

particular bit position. Writing a 0 to any bit position has no effect.

Bit Description

Byte Done Status (DS) — R/WC.

0 = Software can clear this by writing a 1 to it.

1 = Host controller received a byte (for Block Read commands) or if it has completed

transmission of a byte (for Block Write commands) when the 32-byte buffer is not

being used. Note that this bit will be set, even on the last byte of the transfer. This

bit is not set when transmission is due to th e LAN interface heartbeat .

This bit has no meaning for block transfers when the 32-byte buffer is enabled.

NOTE: When the last byte of a block message is received, the host controller will set

this bit. Howeve r, it will not immediately set t he INTR bit (bit 1 i n this registe r).

When the interrupt handler clears the DS bit, the message is considered

complete, and the host controller will then set the INTR bit (and generate

another interrupt). Thus, for a block message of n bytes, the ICH8 will generate

n+1 interrupts. The interrupt handler needs to be implemented to handle these

cases. When not using the 32 Byte Buffer, hardware will drive the SMBCLK

signal low when the DS bit is set until SW clears the bit. This includes the last

byte of a transfer. Software must clear the DS bit before it can clear the BUSY

bit.

INUSE_STS — R/WC (special). This bit is used as semaphore among various

independent software threads that ma y need to use the ICH8’s SMBus logic, and has no

other effect on hardware.

0 = After a full PCI reset, a read to this bit returns a 0.

1 = After the first read, subsequent reads will return a 1. A write of a 1 to this bit will

reset the next read value to 0. Writing a 0 to this bit has no effect. Software can

poll this bit until it reads a 0, and will then own th e usage of the host controller.

SMBALERT_STS — R/WC.

0 = Interrupt or SMI# was not generated by SMBALERT#. Software clears this bit by

writing a 1 to it.

1 = The source of the interrupt or SMI# was the SMBALERT# signal. This bit is only

cleared by software writing a 1 to the bit position or by RSMRST# going low.

If the signal is programmed as a GPIO, then this bit will never be set.

FAILED — R/WC.

0 = Software clear s this bit by writing a 1 to it.

1 = The source of the interrupt or SMI# was a failed bus transaction. This bit is set in

response to the KILL bit being set to terminate the host transaction.

3BUS_ERR — R/WC.

0 = Software clear s this bit by writing a 1 to it.

1 = The source of the interrupt of SMI# was a transaction collision.

DEV_ERR — R/WC.

0 = Software clears this bit by writing a 1 to it. The ICH8 will then deassert the

interrupt or SMI#.

1 = The source of the interrupt or SMI# was due to one of the following:

• Invalid Command Field,

• Unclaimed Cycle (host initiated),

• Host Device Time-out Error.

Intel® ICH8 Family Datasheet 633

SMBus Controller Registers (D31:F3)

16.2.2 HST_CNT—Host Control Register (SMBUS—D31:F3)

Default Value: 00h Size: 8-bits

Note: A read to this register will clear the byte pointer of the 32-byte buffer.

INTR — R/WC (special ). This bit can only be set b y termi natio n of a co mmand. IN TR is

not dependent on the INTREN bit (offset SMBASE + 02h, bit 0) of the Host controller

INTREN bit is not set, then the INTR bit will be set, although the interrupt will not be

generated. Software can poll the INTR bit in this non-interrupt case.

0 = Software clears this bit by writing a 1 to it. The ICH8 then deasserts the interrupt

or SMI#.

1 = The source of the interrupt or SMI# was the successful completion of its last

command.

HOST_BUSY — R/WC.

0 = Cleared by the ICH8 when the current transaction is completed.

1 = Indicates that the ICH8 is running a command from the host interface. No SMB

registers should be acce ssed while this bit is set, except the BLOCK DATA BYTE

when the SMB_CMD bits in the Host Control Register are programmed for Block

command or I2C Read command. This is necessary in order to check the

DONE_STS bit.

Bit Description

PEC_EN. — R/W.

0 = SMBus host controller does not perform the transaction with the PEC phas e

appended.

1 = Causes the host controller to perform the SMBus transaction with the Packet Error

Checking phase appended. For writes, the value of the PEC byte is transferred from

the PEC Register. For reads, the PEC byte is loaded in to the PEC Register. This bit

must be written prior to the write in which the START bit is set.

START — WO.

0 = This bit will always return 0 on reads. The HOST_BUSY bit in the Host Status

command.

1 = Writing a 1 to this bit initiates the command described in the SMB_CMD field. All

registers should be setup prior to writing a 1 to this bit position.

LAST_BYTE — WO. This bit is used for Block Read commands.

1 = Software sets this bit to indicate that the next byte will be the last byte to be

received for the block. This causes the ICH8 to send a NACK (instead of an ACK)

after receiving the last byte.

NOTE: Once the SECOND_TO_STS bit in TCO2_STS regist er (D31:F0, TCOB ASE+6h ,

bit 1) is set, the LAST_BYTE bit also gets set. While the SECOND_TO_STS bit is

set, the LAST_BYTE bit c annot be c leare d. This pre ven ts the ICH8 from ru nning

some of the SMBus commands (Block Read/Write, I2C Read, Block I2C Write).

SMBus Controller Registers (D31:F3)

634 Intel® ICH8 Family Datasheet

4:2

SMB_CMD — R/W. The bit encoding below indicates which command the ICH8 is to

perform. If enabled, the ICH8 will generate an interrupt or SMI# when the command

has completed If the value is for a non-supported or reserved command, the ICH8 will

set the device error (DEV_ERR) status bit (offset SMBASE + 00h, bit 2) and generate

an interrupt when the START bit is set. The ICH8 will perform no command, and will not

operate until DEV_ERR is cleared.

000 = Quick: The slave address and read/write value (bit 0) are stored in the

transmit slave address register.

001 = Byte: This command uses the transmit slave address and command registers.

Bit 0 of the slave address register determines if this is a read or write

command.

010 = Byte Data: This command uses the transmit slave address, command, and

DATA0 registers. Bit 0 of the slave address register determines if this is a read

or write command. If it is a read, the DATA0 register will contain the read data.

011 = Word Data: This command us es the tr ansmit slave address, command, DAT A0

and DATA1 registers. Bit 0 of the slave address register determines if this is a

read or write command. If it is a read, after the command completes, the

DATA0 and DATA1 registers will contain the read data.

100 = Process Call: This command uses the transmit slave address, command,

DATA0 and DATA1 registers. Bit 0 of the slave address register determines if

this is a read or write command. After the command completes, the DA TA0 and

DATA1 registers will contain the read data.

101 = Block: This command uses the transmit slave address, command, DATA0

registers, and the Block Data Byte register. For block write, the count is stored

in the DA TA0 register and indicates how many bytes of data will be transferred.

For block reads, the count is received and stored in the DATA0 register. Bit 0 of

the slave address register selects if this is a read or write command. For writes,

data is retrieved from the first n (where n is equal to the specified count)

addresses of the SRAM array. For reads, the data is stored in the Block Data

Byte register.

110 = I2C Read: This command uses the transmit slave address, command, DATA0,

DA T A1 re gisters, and the Bl ock Data Byte register. The read data is store d in the

Block Data Byte register. The ICH8 continues reading data until the NA K is

received.

111 = Block Process: This command uses the transmit slave address, command,

DATA0 and the Block Data Byte register. For block write, the count is stored in

the DATA0 regist er and indicates how ma ny bytes of data will be transferred.

For block read, the count is received and stored in the DATA0 register. Bit 0 of

the slav e addres s r egi st er always indic ate a writ e com mand. For writes, data is

retrieved from the fir st m (where m is equal to the specified count) addresses of

the SRAM array. For reads, the data is stored in the Block Data Byte register.

NOTE: E32B bit in the Auxiliary Control regi ster must be set for this command to work.

KILL — R/W.

0 = Normal SMBus host controller functionality.

1 = Kills the current host transaction taking place, sets the FAILED status bit, and

asserts the interrupt (or SMI#). This bit, once set, must be cleared by software to

allow the SMBus h ost controller to function normally.

INTREN — R/W.

0 = Disable.

1 = Enable the generation of an interrupt or SMI# upon the completion of the

command.

Bit Description

Intel® ICH8 Family Datasheet 635

SMBus Controller Registers (D31:F3)

16.2.3 HST_CMD—Host Command Register (SMBUS—D31:F3)

Default Value: 00h Size: 8 bits

16.2.4 XMIT_SLVA—Transm it Sla ve Address Register

(SMBUS—D31:F3)

Default Value: 00h Size: 8 bits

This register is transmitted by the host controller in the slave address field of the

SMBus protocol.

16.2.5 HST_D0—Host Data 0 Register (SMBUS—D31:F3)

Default Value: 00h Size: 8 bits

16.2.6 HST_D1—Host Data 1 Register (SMBUS—D31:F3)

Default Value: 00h Size: 8 bits

Bit Description

7:0 This 8-bit field is tr ansm itt ed by the host controller in the com man d fiel d of the SMBu s

protocol during the execution of any command.

Bit Description

7:1 Address — R/W. This field provides a 7-bit address of the targeted slave.

0Read-Write — R/W. Direction of the host transfer.

0 = Write

1 = Read

Bit Description

7:0

Data0/Count — R/W. This field contains the 8-bit data sent in the D ATA0 field of the

SMBus protocol. F or block write commands, this register reflects the number of bytes to

transfer. This register should be programmed to a value between 1 and 32 for block

counts. A count of 0 or a count above 32 will result in unpredictable behavior. The host

controller does not check or lo g invalid block counts.

Bit Description

7:0 Data1 — R/W. This 8-bit register is transmitted in the DATA1 field of the SMBus

protocol during the execution of any command.

SMBus Controller Registers (D31:F3)

636 Intel® ICH8 Family Datasheet

16.2.7 Host_BLOCK_DB—Host Block Data Byte Register

(SMBUS—D31:F3)

Default Value: 00h Size: 8 bits

16.2.8 PEC—Packet Error Check (PEC) Register

(SMBUS—D31:F3)

Default Value: 00h Size: 8 bits

Bit Description

7:0

Block Data (BDTA) — R/W. This is either a register, or a pointer into a 32-byte block

array, depending upon whether the E32B bit is set in the Auxiliary Control register.

When the E32B bit (offset SMBASE + 0Dh, bit 1) is cleared, this is a register containing

a byte of data to be sent on a block write or read from on a block read, just as it

behaved on the ICH3.

When the E32B bit is set, reads and writes to this register are used to access the 32-

byte block data storage array. An internal index pointer is used to address the array,

which is reset to 0 by reading the HCTL register (offset 02h). The index pointer then

increments automatically upon each access to this register. The transfer of block data

into (read) or out of (write) this storage array during an SMBus transaction always

starts at index address 0.

When the E2B bit is set, for writes, software will write up to 32-bytes to this register as

part of the setup for the command. After the Host controller has sent the Address,

Command, and Byte Count fields, it will send the bytes in the SRAM pointed to by this

When the E2B bit is cleared for writes, software will place a single byte in this register.

After the host controller has sent the address, command, and byte count fields, it will

send the byte in this regi ster. If there is more data to send, soft ware will write th e next

series of bytes to the SRAM pointed to by this register and clear the DONE_STS bit. The

controller will then send the ne xt byte. During the time between the last byte being

transmitted to the next byte being transmitted, the controller will insert wait-states on

the interface.

When the E2B bit is set for reads, after receiving the byte count into the Data0 register,

the first series of data bytes go into the SRAM pointed to by this register. If the byte

count has been exhau sted or the 32-byte SRAM has been filled, the controller will

generate an SMI# or interrupt (depending on configur ation) an d set the DONE_STS bit.

Software will then read the data. During the time between when the last byte is read

from the SRAM to when the DONE_STS bit is cleared, the controller will insert wait-

states on the interface.

Bit Description

7:0

PEC_DATA — R/W. This 8-bit register is written with the 8-bit CRC value that is used

as the SMBus PEC data prior to a write tr ansaction. F or read transacti ons, the PEC data

is loaded from the SMBus into this register and is then read by software. Softw are must

ensure that the INUSE_STS bit is properly maintained to avoid hav ing this fiel d over-

written by a write transaction following a read transaction.

Intel® ICH8 Family Datasheet 637

SMBus Controller Registers (D31:F3)

16.2.9 RCV_SLVA—Receive Slave Address Register

(SMBUS—D31:F3)

Default Value: 44h Size: 8 bits

Lockable: No Power Well: Resume

16.2.10 SLV_DATA—Receive Slave Data Register (SMBUS—D31:F3)

Default Value: 0000h Size: 16 bits

Lockable: No Power Well: Resume

This register contains the 16-bit data value written by the external SMBus master. The

processor can then read the value from this register. This register is reset by RSMRST#,

but not PLTRST#

16.2.11 AUX_STS—Auxiliary Status Register (SMBUS—D31:F3)

Default Value: 00h Size: 8 bits

Lockable: No Power Well: Resume

Bit Description

7Reserved

6:0

SLAVE_ADDR — R/W. This field is the slave address that the Int el® ICH8 decodes for

read and write cycles. the default is not 0, so the SMBus Slave Interface can respond

even before the processor comes up (or if the processor is dead). This register is

cleared by RSMRST#, but not by PLTRST#.

Bit Description

15:8 Data Message Byte 1 (DATA_MSG1) — RO. See Section 5.20.7 for a discussion of

this field.

7:0 Data Message Byte 0 (DATA_MSG0) — RO. See Section 5.20.7 for a discussion of

this field.

Bit Description

7:2 Reserved

SMBus TCO Mode (STCO) — RO. This bit reflects the strap setting of TCO compatible

mode vs. Advanced TCO mode.

0 = Intel® ICH8 is in the compatible TCO mode.

1 = ICH8 is in the advanced TCO mode.

This register reflects the value of bit 7 in Section 20.2.5.1.

CRC Error (CRCE) — R/WC.

0 = Software clear s this bit by writing a 1 to it.

1 = This bit is set if a received message contained a CRC error. When this bit is set, the

DERR bit of the host status register will also be set. This bit will be set by the

controller if a software abort occurs i n the middl e of the CR C portion of the cy cl e or

an abort happens after the ICH8 has received the final data bit transmitte d by an

external slave.

SMBus Controller Registers (D31:F3)

638 Intel® ICH8 Family Datasheet

16.2.12 AUX_CTL—Auxiliary Control Register (SMBUS—D31:F3)

Default Value: 00h Size: 8 bits

Lockable: No Power Well: Resume

16.2.13 SMLINK_PIN_CTL—SMLink Pin Control Regi ster

(SMBUS—D31:F3)

Default Value: See below Size: 8 bits

Note: This register is in the resume well and is reset by RSMRST#.

This register is only applicable in the TCO compatible mode.

Bit Description

7:2 Reserved

Enable 32-Byte Buffer (E32B) — R/W.

0 = Disable.

1 = Enable. When set, the Host Block Data re gister is a pointer in to a 32-byte buffer, as

opposed to a single regi ster. This enables the block commands t o transfer or receiv e

up to 32-bytes before the ICH8 generates an interrupt.

Automatically Append CRC (AAC) — R/W.

0 = ICH8 will Not automatically append the CRC.

1 = The ICH8 will automatically append the CRC. This bit must not be changed during

SMBus transactions or undetermined behavior will result. It should be programmed

only once during the lifetime of the function.

Bit Description

7:3 Reserved

SMLINK_CLK_CTL — R/W.

0 = ICH8 will drive the SMLINK0 pin low, independent of what the other SMLINK logic

would otherwise indicate for the SMLINK0 pin.

1 = The SMLINK0 pin is not overdriven low. The other SMLINK logic controls the state

of the pin. (Default)

SMLINK1_CUR_STS — RO . This read-only bit has a default value that is depend ent on

an external signal level. This pin returns the value on the SMLINK1 pin. This allows

software to read the current state of the pin.

0 = Low

1 = High

SMLINK0_CUR_STS — RO . This read-only bit has a default value that is depend ent on

an external signal level. This pin returns the value on the SMLINK0 pin. This allows

software to read the current state of the pin.

0 = Low

1 = High

Intel® ICH8 Family Datasheet 639

SMBus Controller Registers (D31:F3)

16.2.14 SMBUS_PIN_CTL—SMBus Pin Control Register

(SMBUS—D31:F3)

Default Value: See below Size: 8 bits

Note: This register is in the resume well and is reset by RSMRST#.

16.2.15 SLV_STS—Slave Status Register (SMBUS—D31:F3)

Default Value: 00h Size: 8 bits

Note: This register is in the resume well and is reset by RSMRST#.

All bits in this register are implemented in the 64 kHz clock domain. Therefore,

software must poll this register until a write takes effect before assuming that a write

has completed internally.

Bit Description

7:3 Reserved

SMBCLK_CTL — R/W.

0 = ICH8 drives the SMBCLK pin low, independent of what the other SMB logic would

otherwise indicate for the SMBCLK pin. (Default)

1 = The SMBCLK pin is not overdriven low. The other SMBus logic controls the state of

the pin.

SMBDATA_CUR_STS — RO. This read-only bit has a default value that is dependent

on an external signal level. This pin returns the value on the SM B DATA pin . Thi s allows

software to read the current state of the pin.

0 = Low

1 = High

SMBCLK_CUR_STS — RO . This read-o nly bit has a default value that is dependent on

an external signal level. This pin returns the value on the SMBCLK pin. This allows

software to read the current state of the pin.

0 = Low

1 = High

Bit Description

7:1 Reserved

HOST_NOTIFY_STS — R/WC. The ICH8 sets this bit to a 1 when it has completely

received a succ essful Host Not ify Command on the SMLink pins. Software reads this bit

to determine that the source of the interrupt or SMI# was the reception of the Host

Notify Command. Software clears this bit after reading any information needed from

the Notify address and data registers by writing a 1 to this bit. Note that the ICH8 will

allow the Notify Address and Data registers to be over-written once this bit has been

cleared. When this bit is 1, the ICH8 will NACK the first byte (host address) of any new

“Host Notify” commands on the SMLink. Writing a 0 to this bit has no effect.

SMBus Controller Registers (D31:F3)

640 Intel® ICH8 Family Datasheet

16.2.16 SLV_CMD—Slave Command Register (SMBUS—D31:F3)

Default Value: 00h Size: 8 bits

Note: This register is in the resume well and is reset by RSMRST#.

16.2.17 NOTIFY_DADDR—Notify Device Address Register

(SMBUS—D31:F3)

Default Value: 00h Size: 8 bits

Note: This register is in the resume well and is reset by RSMRST#.

Bit Description

7:2 Reserved

SMBALERT_DIS — R/W.

0 = Allows the generation of the interrupt or SMI#.

1 = Software sets this bit to block the generation of the interrupt or SMI# due to the

SMBALERT# source. This bit is logically inverted and ANDed with the

SMBALERT_STS bit (o ffset SMBASE + 00h, bit 5). The resulting signal is distributed

to the SMI# and/or interrupt generation logic. This bit does not effect the wake

logic.

HOST_NOTIFY_WKEN — R/W. Software sets this bit to 1 to enable the reception of a

Host Notify command as a wake event. When enabled this event is “OR”’d in with the

other SMBus wake events and is reflected in the SMB_WAK_STS bit of the General

Purpose Event 0 Status register.

0 = Disable

1 = Enable

HOST_NOTIFY_INTREN — R/W. Software sets this bit to 1 to enable the generation

of interrupt or SMI# when HOST_NOTIFY_STS (offset SMBASE + 10h, bit 0) is 1. This

enable does not affect the setting of the HOST_NOTIFY_STS bit. When the interrupt is

generated, either PIRQB# or SMI# is generated, depending on the value of the

SMB_SMI_EN bit (D 31:F3: 40h, bit 1) . If t he HOST_NOTIFY_STS bit is set wh en th is bi t

is written to a 1, then the interrupt (or SMI#) will be generated. The interrupt (or

SMI#) is logically generated by AND’ing the STS and INTREN bits.

0 = Disable

1 = Enable

Bit Description

7:1

DEVICE_ADDRESS — RO. This field contains the 7-bit device address received during

the Host Notify protocol of the SMBus 2.0 Specification. Sof tw a re should only cons ider

this field valid when the HOST_NOTIFY_STS bit (D31:F3:SMBASE +10, bit 0) is set to

0Reserved

Intel® ICH8 Family Datasheet 641

SMBus Controller Registers (D31:F3)

16.2.18 NOTIFY_DLOW—Notify Data Low Byte Register

(SMBUS—D31:F3)

Default Value: 00h Size: 8 bits

Note: This register is in the resume well and is reset by RSMRST#.

16.2.19 NOTIFY_DHIGH—Notify Data High Byte Regi ster

(SMBUS—D31:F3)

Default Value: 00h Size: 8 bits

Note: This register is in the resume well and is reset by RSMRST#.

§ §

Bit Description

7:0

DATA_LOW_BYTE — RO. This field contains the first (low) byte of data received

during the Host Notify protocol of the SMBus 2.0 specification. Software should only

consider this field valid when the HOST_NOTIFY_STS bit (D31:F3:SMBASE +10, bit 0)

is set to 1.

Bit Description

7:0

DATA_HIGH_BYTE — RO. This field contains the second (high) byte of data received

during the Host Notify protocol of the SMBus 2.0 specification. Software should only

consider this field valid when the HOST_NOTIFY_STS bit (D31:F3:SMBASE +10, bit 0)

is set to 1.

SMBus Controller Registers (D31:F3)

642 Intel® ICH8 Family Datasheet

Intel® ICH8 Family Datasheet 643

Intel® High Definition Audio Controller Registers (D27:F0)

17 Intel® High Definition Audio

Controller Registers (D27:F0)

The Intel High Definition Audio controller resides in PCI Device 27, Function 0 on bus 0.

This function contains a set of DMA engines that are used to move samples of digitally

encoded data between system memory and external codecs.

Note: All registers in this function (including memory-mapped registers) must be addressable

in byte, word, and DWord quantities. The software must alwa ys make register accesses

on natural boundaries (i.e., DWord accesses must be on DWord boundaries; word

accesses on word boundaries, etc.) In addition, the memory-mapped register space

must not be accessed with the LOCK semantic exclusive-access mechanism. If software

attempts exclusive-access mechanisms to the Intel High Definition Audio memory-

mapped space, the results are undefined.

Note: Users interested in providing feedback on the Intel High Definition Audio specification

or planning to implement the Intel High Definition Audio specification into a future

product will need to execute the Intel® High Definition Audio Specification Developer’s

Agreement. For more information, contact nextgenaudio@intel.com.

17.1 Intel® High Definition Audio PCI Configuration

Space (Intel® High Definition Audio— D27:F0)

Note: Address locations that are not shown should be treated as Reserved.

Table 139. Intel® High Definition Audio PCI Register Address Map

(Intel® High Definition Audio D27:F0)

Offset Mnemonic Register Name Default Access

00h–01h VID Vendor Identification 8086h RO

02h–03h DID Device Identi fic a ti on See register

description RO

04h–05h PCICMD PCI Command 0000h R/W, RO

06h–07h PCISTS PCI Status 0010h R/WC, RO

08h RID Revi si on Ide n ti fic a ti on See register

description RO

09h PI Programming Interface 00h RO

0Ah SCC Sub Class Code 03h RO

0Bh BCC Base Class Code 04h RO

0Ch CLS Cache Line Size 00h R/W

0Dh LT Latency Timer 00h RO

0Eh HEADTYP Header Type 00h RO

10h–13h HDBARL Intel® High Definition Audio Lower Base

Address (Memory) 00000004h R/W, RO

14h–17h HDBARU Intel High Definition Audio Upper Base

Address (Memory) 00000000h R/W

2Ch–2Dh SVID Subsystem Vendor Identification 0000h R/WO

Intel® High Definition Audio Controller Registers (D27:F0)

644 Intel® ICH8 Family Datasheet

2Eh–2Fh SID Subsystem Identification 0000h R/WO

34h CAPPTR Capability List Pointer 50h RO

3Ch INTLN Interrupt Line 00h R/W

3Dh INTPN Interrupt Pin See Register

Description RO

40h HDCTL Intel High Definition Audio Control 00h R/W, RO

44h TCSEL Traffic Class Select 00h R/W

4Ch DCKCTL Docking Control (Mobile Only) 00h R/W, RO

4Dh DCKSTS Docking Status (Mobile Only) 80h R/WO, RO

50h–51h PID PCI Power Management Capability ID 6001h RO

52h–53h PC Power Management Capabilities C842 RO

54h–57h PCS Power Management Control and Status 00000000h R/W, RO,

R/WC

60h–61h MID MSI Capability ID 7005h RO

62h–63h MMC MSI Message Control 0080h R/W, RO

64h–67h MMLA MSI Message Lower Address 00000000h R/W, RO

68h–6Bh MMUA SMI Message Upper Address 00000000h R/W

6Ch–6Dh MMD MSI Message Data 0000h R/W

70h–71h PXID PCI Express* Capability Identifiers 0010h RO

72h–73h PXC PCI Express Capabilities 0091h RO

74h–77h DEVCAP Device Capabilities 00000000h RO, R/WO

78h–79h DEVC Device Control 0800h R/W, RO

7Ah–7Bh DEVS Device Status 0010h RO

100h–103h VCCAP Virtual Channel Enhanced Capability

Header 13010002h RO

104h–107h PVCCAP1 Port VC Capability Register 1 00000001h RO

108h–10Bh PVCCAP2 Port VC Capability Register 2 00000000h RO

10Ch–10D PVCCTL Port VC Control 0000h RO

10Eh–10Fh PVCSTS Port VC Status 0000h RO

110h–103h VC0CAP VC0 Resource Capability 00000000h RO

114h–117h VC0CTL VC0 Resource Control 800000FFh R/W, RO

11Ah–11Bh VC0STS VC0 Resource Status 0000h RO

11Ch–11Fh VCiCAP VCi Resource Capability 00000000h RO

120h–123h VCiCTL VCi Resource Control 00000000h R/W, RO

126h–127h VCiSTS VCi Resource Status 0000h RO

130h–133h RCCAP Root Complex Link Declaration Enhanced

Capability Header 00010005h RO

134h–137h ESD Element Self Description 0F000100h RO

Table 139. Intel® High Definition Audio PCI Register Address Map

(Intel® High Definition Audio D27:F0)

Offset Mnemonic Register Name Default Access

Intel® ICH8 Family Datasheet 645

Intel® High Definition Audio Controller Registers (D27:F0)

17.1.1 VID—Vendor Identification Register

(Intel® High Definition Audio Controller—D27:F0)

Offset: 00h-01h Attribute: RO

Default Value: 8086h Size: 16 bits

17.1.2 DID—Device Identification Register

(Intel® High Definition Audio Controller—D27:F0)

Offset Address: 02h–03h Attribute: RO

Default Value: See bit description Size: 16 bits

140h–143h L1DESC Link 1 Description 00000001h RO

148h–14Bh L1ADDL Link 1 Lower Address See Register

Description RO

14Ch–14Fh L1ADDU Link 1 Upper Address 00000000h RO

Table 139. Intel® High Definition Audio PCI Register Address Map

(Intel® High Definition Audio D27:F0)

Offset Mnemonic Register Name Default Access

Bit Description

15:0 Vendor ID — RO. This is a 16-bit value assigned to Intel. Intel VID = 8086h

Bit Description

15:0 Device ID — RO. This is a 16-bit value assigned to the Intel® ICH8 Intel High

Definition Audio controller. Refer to the Intel® ICH8 Family Specification Update for

the value of the Device ID Register.

Intel® High Definition Audio Controller Registers (D27:F0)

646 Intel® ICH8 Family Datasheet

17.1.3 PCICMD—PCI Command Register

(Intel® High Definition Audio Controller—D27:F0)

Offset Address: 04h–05h Attribute: R/W, RO

Default Value: 0000h Size: 16 bits

Bit Description

15:11 Reserved

Interrupt Disable (ID) — R/W.

0 = The INTx# signals may be asserted.

1 = The Intel® High Definition Audio controller’s INTx# signal will be de-asserted

Note that this bit do es not affect the gen eration o f MSIs.

9 Fast Back to Back Enable (FBE) — RO. Not implemented. Hardwired to 0.

8SERR# Enable (SERR_EN) — R/W. SERR# is not generated by the ICH8 Intel High

Definition Audio Controller.

7 Wait Cycle Control (WCC) — RO. Not implemented. Hardwired to 0.

6 Parity Error Response (PER) — RO. Not implemented. Hardwired to 0.

5 VGA Palette Snoop (VPS). Not implemented. Hardwired to 0.

4Memory Write and Invalidate Enable (MWIE) — RO. Not implemented. Hardwired to

3 Special Cycle Enable (SCE). Not implemented. Hardwired to 0.

Bus Master Enable (BME) — R/W. This bit controls standard PCI Express* bus

mastering capabilities for Memory and I/O, reads and writes. Note that this bit also

controls MSI generation since MSIs are essentially Memory writes.

0 = Disable

1 = Enable

Memory Space Enable (MSE) — R/W. This bit enables memory space addresses to

the Intel High De finition Audio controller.

0 = Disable

1 = Enable

0I/O Space Enable (IOSE)—RO. Hardwired to 0 since the Intel High Definition Audio

controller does not implement I/O space.

Intel® ICH8 Family Datasheet 647

Intel® High Definition Audio Controller Registers (D27:F0)

17.1.4 PCISTS—PCI Status Register

(Intel® High Definition Audio Controller—D27:F0)

Offset Address: 06h–07h Attribute: RO, R/WC

Default Value: 0010h Size: 16 bits

17.1.5 RID—Revision Identification Register

(Intel® High Definition Audio Controller—D27:F0)

Offset: 08h Attribute: RO

Default Value: See bit description Size: 8 Bits

Bit Description

15 Detected Parity Error (DPE) — RO. Not implemented. Hardwired to 0.

14 SERR# Status (SERRS) — RO. Not implemented. Hardwired to 0.

Received Master Abort (RMA) — R/WC. Software clears this bit by writing a 1 to it.

0 = No master abort received.

1 = The Intel® High Definition Audio controller sets thi s bit wh en, as a bu s mast er, it

receives a master abort. When set, the Intel High Definition Audio controller

clears the run bit for the channel that received the abort.

12 Received Target Abort (RTA) — RO. Not implemented. Hardwired to 0.

11 Signaled Target Abort (STA) — RO. Not implemented. Hardwired to 0.

10:9 DEVSEL# Timing Status (DEV_STS) — RO. Does not apply. Hardwired to 0.

8 Data Parity Error Detected (DPED) — RO. Not implemented. Hardwired to 0.

7 Fast Back to Back Capable (FB2BC) — RO. Does not apply. Hardw ired to 0.

6 Reserved.

5 66 MHz Capable (66MHZ_CAP) — RO. Does not apply. Hardwired to 0.

4Capabilities List (CAP_LIST) — RO. Hardwired to 1. Indicates that the controller

contains a capabilities pointer list. The first item is pointed to by looking at

configuration offset 34h.

Interrupt Status (IS) — RO.

0 = This bit is 0 after the interrupt is cleared.

1 = INTx# is asserted.

Note that this bit is not set by an MSI.

2:0 Reserved.

Bit Description

7:0 R e vision ID — RO. Re fer to the Intel® I/O Controller Hub 8 (ICH8) Family Specification

Update for the value of the Revision ID Register

Intel® High Definition Audio Controller Registers (D27:F0)

648 Intel® ICH8 Family Datasheet

17.1.6 PI—Programming Interface Register

(Intel® High Definition Audio Controller—D27:F0)

Offset: 09h Attribute: RO

Default Value: 00h Size: 8 bits

17.1.7 SCC—Sub Class Code Register

(Intel® High Definition Audio Controller—D27:F0)

Address Offset: 0Ah Attribute: RO

Default Value: 03h Size: 8 bits

17.1.8 BCC—Base Class Code Register

(Intel® High Definition Audio Controller—D27:F0)

Address Offset: 0Bh Attribute: RO

Default Value: 04h Size: 8 bits

17.1.9 CLS—Cache Line Size Register

(Intel® High Definition Audio Controller—D27:F0)

Address Offset: 0Ch Attribute: R/W

Default Value: 00h Size: 8 bits

17.1.10 LT—Latency Timer Register

(Intel® High Definition Audio Controller—D27:F0)

Address Offset: 0Dh Attribute: RO

Default Value: 00h Size: 8 bits

Bit Description

7:0 Programming Interface — RO.

Bit Description

7:0 Sub Class Code (SCC) — RO.

03h = Audio Device

Bit Description

7:0 Base Class Code (BCC) — RO.

04h = Multimedia device

Bit Description

7:0 Cache Line Size — R/W. Implemented as R/W register, but has no functional impact to

the ICH8

Bit Description

7:0 Latency Timer — RO. Hardwired to 00

Intel® ICH8 Family Datasheet 649

Intel® High Definition Audio Controller Registers (D27:F0)

17.1.11 HEADTYP—Header Type Register

(Intel® High Definition Audio Controller—D27:F0)

Address Offset: 0Eh Attribute: RO

Default Value: 00h Size: 8 bits

17.1.12 HDBARL—Intel® High Definition Audio Lower Base

Address Register (Intel® High Definition Audio—D27:F0)

Address Offset: 10h–13h Attribute: R/W, RO

Default Value: 00000004h Size: 32 bits

17.1.13 HDBARU—Intel® High Definition Audio Upper Base

Address Register (Intel® High Definition Audio

Controller—D27:F0)

Address Offset: 14h–17h Attribute: R/W

Default Value: 00000000h Size: 32 bits

Bit Description

7:0 Header Type — RO. Hardwired to 00.

Bit Description

31:14 Lower Base Address (LBA) — R/W. Base address for the Intel® High Definition Audio

controller’s memory-mapped configuration registers. A 16 KB size are requested by

hardwiring bits 13:4 to 0s.

13:4 RO. Hardwired to 0’s

3 Prefetchable (PREF) — RO. Hardwired to 0 to indicate that this BAR is NOT prefetchable

2:1 Address Range (ADDRNG) — RO. Hardwired to 10b indicating that this BAR can be

located anywhere in 64-bit address space.

0Space Type (SPTYP) — RO. Hardwired to 0 indicating this BAR is located in memory

space.

Bit Description

31:0 Upper Base Address (UBA) — R/W. This field contains the upper 32 bits of the Base

address for the Intel® High Definition Audio controller’s memory-mapped configur ation

registers.

Intel® High Definition Audio Controller Registers (D27:F0)

650 Intel® ICH8 Family Datasheet

17.1.14 SVID—Subsystem Vendor Identification Register

(Intel® High Definition Audio Controller—D27:F0)

Address Offset: 2Ch–2Dh Attribute: R/WO

Default Value: 0000h Size: 16 bits

The SVID register, in combination with the Subsystem ID register (D27:F0:2Eh),

enable the operating environment to distinguish one audio subsystem from the

other(s).

This register is implemented as write-once register. Once a value is written to it, the

value can be read back. Any subsequent writes will have no effect.

This register is not affected by the D3HOT to D0 transition.

17.1.15 SID—Subsystem Identification Register

(Intel® High Definition Audio Controller—D27:F0)

Address Offset: 2Eh–2Fh Attribute: R/WO

Default Value: 0000h Size: 16 bits

The SID register, in combination with the Subsystem Vendor ID register (D27:F0:2Ch)

make it possible for the operating environment to distinguish one audio subsystem

from the other(s).

This register is implemented as write-once register. Once a value is written to it, the

value can be read back. Any subsequent writes will have no effect.

This register is not affected by the D3HOT to D0 transition.

17.1.16 CAPPTR—Capabilities Pointer Register (Audio—D30:F2)

Address Offset: 34h Attribute: RO

Default Value: 50h Size: 8 bits

This register indicates the offset for the capability pointer.

Bit Description

15:0 Subsystem Vendor ID — R/WO.

Bit Description

15:0 Subsystem ID — R/WO.

Bit Description

7:0 Capabilities Pointer (CAP_PTR) — RO. This field indicate s that the first capability pointer

offset is offset 50h (Power Management Capability)

Intel® ICH8 Family Datasheet 651

Intel® High Definition Audio Controller Registers (D27:F0)

17.1.17 INTLN—Interrupt Line Register

(Intel® High Definition Audio Controller—D27:F0)

Address Offset: 3Ch Attribute: R/W

Default Value: 00h Size: 8 bits

17.1.18 INTPN—Interrupt Pin Register

(Intel® High Definition Audio Controller—D27:F0)

Address Offset: 3Dh A ttribute: RO

Default Value: See Description Size: 8 bits

17.1.19 HDCTL—Intel® High Definition Audio Control Register

(Intel® High Definition Audio Controller—D27:F0)

Address Offset: 40h Attribute: R/W, RO

Default Value: 00h Size: 8 bits

Bit Description

7:0 Interrupt Line (INT_LN) — R/W. This data is not us ed by t he Inte l® ICH8. It is used

to communicate to software the interrupt line that the interrupt pin is connected to.

Bit Description

7:4 Reserved.

3:0 Interrupt Pin — RO. This reflects the value of D27IP.ZIP (Chipset Configuration

Registers, Offset 3110h, bits 3:0).

Bit Description

7:1 Reserved.

0Intel® High Definition Signal Mode — RO. This bit is hardwired to 1 (Hi gh Definition

Audio mode)

Intel® High Definition Audio Controller Registers (D27:F0)

652 Intel® ICH8 Family Datasheet

17.1.20 TCSEL—Traffic Class Select Register

(Intel® High Definition Audio Controller—D27:F0)

Address Offset: 44h Attribute: R/W

Default Value: 00h Size: 8 bits

This register assigned the value to be placed in the TC field. CORB and RIRB data will

always be assigned TC0.

17.1.21 DCKCTL—Docking Control Register

(Intel® High Definition Audio Controller—D27:F0) (Mobile

Only)

Address Offset: 4Ch Attribute: R/W, RO

Default Value: 00h Size: 8 bits

Bit Description

7:3 Reserved.

2:0

Intel® HIgh Defini tion Audio Traffic Class Assignment (TCSEL)— R/W. This

data, and buffer descriptor transactions.

000 = TC0

001 = TC1

010 = TC2

011 = TC3

100 = TC4

101 = TC5

110 = TC6

111 = TC7

NOTE: These bits are not reset on D3 HOT to D0 transition; however, they are reset by

PLTRST#.

Bit Description

7:1 Reserved.

Dock Attach (DA) — R/W / RO. Software writes a 1 to this bit to initiate the docking

sequence on the HDA_DOCK_EN# and HDA_DOCK_RST# signals. When the docking

sequence is complete hardware will set the Dock Mated (GSTS.DM) status bit to 1.

Software writes a 0 to this bit to initiate the undocking sequence on the

HDA_DOCK_EN# and HDA_DOCK_RST# signals. When the undocking sequence is

complete hardware will set the Dock Mated (GSTS.DM) status bit to 0.

Note that software must check the state of the Dock Mated (GSTS.DM) bit prior to

writing to the Dock Attach bit. Software shall only change the DA bit from 0 to 1 when

DM=0. Likewise, software shall only change the DA bit from 1 to 0 when DM=1. If

these rules are violated, the results are undefined.

Note that this bit is Read Only when the DCKSTS.DS bit = 0.

Intel® ICH8 Family Datasheet 653

Intel® High Definition Audio Controller Registers (D27:F0)

17.1.22 DCKSTS—Docking Status Register

(Intel® High Definition Audio Controller—D27:F0) (Mobile

Only)

Address Offset: 4Dh A ttribute: R/WO, RO

Default Value: 80h Size: 8 bits

17.1.23 PID—PCI Power Management Capability ID Register

(Intel® High Definition Audio Controller—D27:F0)

Address Offset: 50h-51h Attribute: RO

Default Value: 6001h Size: 16 bits

Bit Description

Docking Supported (DS) — R/WO. A 1 indicate s that ICH8 supports HD Audio Docking.

The DCKCTL.DA bit i s only writable when this DS bit is 1. ACPI BIOS software should

only branch to the docking routine when this DS bit is 1. BIOS may clear this bit to 0 to

prohibit the ACPI BIOS software from attempting to run the docking routines.

Note that this bit is reset to its default value only on a PLTRST#, but not on a CRST# or

D3hot-to-D0 transition.

6:1 Reserved.

Dock Mated (DM) — RO. This bit effectively communicates to software that an Intel®

HD Audio docked codec is physically and electrically attached.

Controller hardware sets this bit to 1 after the docking sequence triggered by writing a

1 to the Dock Attach (GCTL.DA) bit is completed (HDA_DOCK_RST# deassertion). This

bit indicates to sof tware th at the dock ed codec(s) ma y be discovered via the STATESTS

Controller hardware sets this bit to 0 after the undocking sequence triggered by writing

a 0 to the Dock Attach (GCTL.DA) bit is completed (HDA_DOCK_EN# deasserted). This

bit indicates to software that the docked codec(s) may be physically undocked.

Bit Description

15:8 Next Capability (Next) — RO. Hardwired to 60h. Po ints to th e next capability structure

(MSI)

7:0 Cap ID (CAP) — RO. Hardwired to 01h. Indicates that this pointer is a PCI power

management capability.

Intel® High Definition Audio Controller Registers (D27:F0)

654 Intel® ICH8 Family Datasheet

17.1.24 PC—Power Management Capabilities Register

(Intel® High Definition Audio Controller—D27:F0)

Address Offset: 52h-53h Attribute: RO

Default Value: C842h Size: 16 bits

17.1.25 PCS—Power Management Control and Status Register

(Intel® High Definition Audio Controller—D27:F0)

Address Offset: 54h-57h Attribute: RO, R/W, R/WC

Default Value: 00000000h Size: 32 bits

Bit Description

15:11 PME Support — RO. Hardwired to 11001b. Indicates PME# can be generated from D3

and D0 states.

10 D2 Support — RO. Hardwired to 0. Indicates that D2 state is not supported.

9 D1 Support —RO. Hardwired to 0. Indicates that D1 state is not supported.

8:6 Aux Current — RO. Hardwired to 001b. Reports 55 mA maximum suspend well current

required when in the D3COLD state.

5Device Specifi c Initialization (DSI) — RO. Hardwired to 0. Indicates that no device

specific initialization is required.

4 Reserved

3 PME Clock (PMEC) — RO. Does not apply. Hardwired to 0.

2:0 Version — RO. Hardwired to 010b. Indicates support for version 1.1 of the PCI Power

Management Specification.

Bit Description

31:24 Data — RO. Does not apply. Hardwired to 0.

23 Bus Power/Clock Control Enable — RO. Does not apply. Hardwired to 0.

22 B2/B3 Support — RO. Does not apply. Hardwired to 0.

21:16 Reserved.

PME Status (PMES) — R/WC.

0 = Software clears the bit by writing a 1 to it.

1 = This bit is set when the Intel® High Definition Audio controller would normally

assert the PME# signal independent of the state of the PME_EN bit (bit 8 in this

This bit is in the resume well and only cleared on a power-on reset. Software must not

make assumptions about the reset state of this bit and must set it appropriately.

14:9 Reserved

PME Enable (PMEE) — R/W.

0 = Disable

1 = Enable. When set and if corresponding PMES also set, the Intel High Definition

Audio controller sets the PME_B0_STS bit in the GPE0_STS register (PMBASE

+28h).

This bit is in the resume well and only cleared on a power-on reset. Software must not

make assumptions about the reset state of this bit and must set it appropriately.

7:2 Reserved

Intel® ICH8 Family Datasheet 655

Intel® High Definition Audio Controller Registers (D27:F0)

17.1.26 MID—MSI Capability ID Register

(Intel® High Definition Audio Controller—D27:F0)

Address Offset: 60h-61h Attribute: RO

Default Value: 7005h Size: 16 bits

17.1.27 MMC—MSI Message Control Regist er

(Intel® High Definition Audio Controller—D27:F0)

Address Offset: 62h-63h Attribute: RO, R/W

Default Value: 0080h Size: 16 bits

1:0

Power State (PS) — R/W. This field is used both to determine the current power state

of the Intel High Definition Audio controller and to set a new power state.

00 = D0 state

11 = D3HOT state

Others = reserved

NOTES:

1. If software attempts to write a value of 01b or 10b in to this field, the write

operation must complete normally; however, the data is discarded and no state

change occurs.

2. When in the D3HOT states, the Intel High D efinition Audio controller’s

configuration space is available, but the I/O and memory space are not.

Additionally, interrupts are blocked.

3. When software changes this v alue from D3HOT state to the D0 state, an internal

warm (soft) reset is generated, and software must re-initialize the function.

Bit Description

15:8 Next Capability (Next) — RO. Hardwired to 70h. Points to the PCI Express* capability

structure.

7:0 Cap ID (CAP) — RO. Hardwired to 05h. Indicates that this pointer is a MSI capability

Bit Description

15:8 Reserved

764b Address Capability (64ADD) — RO. Hardwired to 1. Indicates the ability to generate

a 64-bit message address

6:4 Multiple Message Enable (MME) — RO. Normally this is a R/W register. However, si nce

only 1 message is supported, these bits are hardwired to 000 = 1 message.

3:1 Multiple Message Capable (MMC) — RO. Hardwired to 0 indicating request for 1

message.

0MSI Enable (ME) — R/W.

0 = MSI may not be generated

1 = MSI will be generated instead of an INTx signal.

Intel® High Definition Audio Controller Registers (D27:F0)

656 Intel® ICH8 Family Datasheet

17.1.28 MMLA—MSI Message Lower Address Register

(Intel® High Definition Audio Controller—D27:F0)

Address Offset: 64h-67h Attribute: RO, R/W

Default Value: 00000000h Size: 32 bits

17.1.29 MMUA—MSI Message Upper Address Register

(Intel® High Definition Audio Controller—D27:F0)

Address Offset: 68h-6Bh Attribute: R/W

Default Value: 00000000h Size: 32 bits

17.1.30 MMD—MSI Message Data Register

(Intel® High Definition Audio Controller—D27:F0)

Address Offset: 6Ch-6Dh Attribute: R/W

Default Value: 0000h Size: 16 bits

17.1.31 PXID—PCI Express* Capability ID Register

(Intel® High Definition Audio Controller—D27:F0)

Address Offset: 70h-71h Attribute: RO

Default Value: 0010h Size: 16 bits

Bit Description

31:2 Message Lower Address (MLA) — R/W. Lower address used for MSI message.

1:0 Reserved.

Bit Description

31:0 Message Upper Address (MUA) — R/W. Upper 32-bits of address used for MSI

message.

Bit Description

15:0 Message Data (MD) — R/W. Data used for MSI message.

Bit Description

15:8 Next Capability (Next) — RO. Hardwired to 0. Indicates that this is the last capability

structure in the list.

7:0 Cap ID (CAP) — RO. Hardwired to 10h. Indicates that this pointer is a PCI Express*

capability structure

Intel® ICH8 Family Datasheet 657

Intel® High Definition Audio Controller Registers (D27:F0)

17.1.32 PXC—PCI Express* Capabilities Register

(Intel® High Definition Audio Controller—D27:F0)

Address Offset: 72h-73h Attribute: RO

Default Value: 0091h Size: 16 bits

17.1.33 DEVCAP—Device Capabilities Register

(Intel® High Definition Audio Controller—D27:F0)

Address Offset: 74h-77h Attribute: R/WO, RO

Default Value: 00000000h Size: 32 bits

Bit Description

15:14 Reserved

13:9 Interrupt Message Number (IMN) — RO. Hardwired to 0.

8 Slot Implemented (SI) — RO. Hardwired to 0.

7:4 Device/Port Type (DPT) — RO. Hardwire d to 1001b. Indicates that this is a Root

Complex Integrated endpoint device.

3:0 Capability Version (CV) — RO. Hardwired to 0001b. Indicates version #1 PCI Express

capability

Bit Description

31:28 Reserved

27:26 Captured Slot Power Limit Scale (SPLS) — RO. Hardwired to 0.

25:18 Captured Slot Power Limit Value (SPLV) — RO. Hardwired to 0.

17:15 Reserved

14 Power Indicator Present — RO. Hardwired to 0.

13 Attention Indicator Present — RO. Hardwired to 0.

12 Attention Button Present — RO. Hardwired to 0.

11:9 Endpoint L1 Acceptable Latency — R/WO.

8:6 Endpoint L0s Acceptable Latency — R/WO.

5 Extended Tag Field Support — RO. Hardwired to 0. Indicates 5-bit tag field support

4:3 Phantom Functions Supported — RO. Hardwired to 0. Indicates that phantom functions

not supported

2:0 Max P ayload Size Supported — RO . Hardwired to 0 . Indic ates 128-B maxi mum payload

size capability

Intel® High Definition Audio Controller Registers (D27:F0)

658 Intel® ICH8 Family Datasheet

17.1.34 DEVC—Device Control Register

(Intel® High Definition Audio Controller—D27:F0)

Address Offset: 78h-79h Attribute: R/W, RO

Default Value: 0800h Size: 16 bits

Bit Description

15 Reserved

14:12 Max Read Request Size — RO. Hardwired to 0 enabling 128B maximum read request

size.

No Snoop Enable (NSNPEN) — R/W.

0 = The Intel® High Definition Audio controller will not set the No Snoop bit. In this

case, isochronou s tr an sfers wil l not u se VC1 (VCi) ev en if it is enabled si nce VC1 is

never snooped. Isochronous transfers will use VC0.

1 = The Intel High Definition Audio controller is permitte d to set the No Snoop bit in the

Requester Attributes of a bus master transaction. In this case, VC0 or VC1 may be

used for isochronous transfers.

NOTE: This bit is not reset on D3HOT to D0 transition; however, it is reset by PLTRST#.

10 Auxiliary P ower Enable — RO. Hardwired to 0, indicating t hat Intel High Definition Audio

device does not draw AUX power

9 Phantom Function Enable — RO. Hardwired to 0 disabling phantom functions.

8 Extended Tag Field Enable — RO. Hardwired to 0 enabling 5-bit tag.

7:5 Max Payload Size — RO. Hardwired to 0 indicating 128B.

4 Enable Relaxed Ordering — RO. Hardwired to 0 disabling relaxed ordering.

3 Unsupported Request Re porting Enable — RO. Not implemented. Hardwired to 0.

2 Fatal Error Reporting Enable — RO. Not implemented. Hardwired to 0.

1 Non-Fatal Error Reporting Enable — RO. Not implement ed. Hardwired to 0.

0 Correctable Error Reporting Enable — RO. Not implemented. Hardwired to 0.

Intel® ICH8 Family Datasheet 659

Intel® High Definition Audio Controller Registers (D27:F0)

17.1.35 DEVS—Device Status Register

(Intel® High Definition Audio Controller—D27:F0)

Address Offset: 7Ah-7Bh Attribute: RO

Default Value: 0010h Size: 16 bits

17.1.36 VCCAP—Virtual Channel Enhanced Capability Header

(Intel® High Definition Audio Controller—D27:F0)

Address Offset: 100h-103h Attribute: RO

Default Value: 13010002h Size: 32 bits

Bit Description

15:6 Reserved

Transactions Pending — RO.

0 = Completions for all non-posted requests have been received

1 = Intel® High Definition Audio controller has issued non-posted requests that have

not been completed.

4AUX Power Detected — RO . Hardwired to 1 indicating the device is connected to resume

power

3 Unsupported Request Detected — RO. Not implemented. Hardwired to 0.

2 Fatal Error Detected — RO. Not implemented. Hardwired to 0.

1 Non-Fatal Error Detected — RO. Not implemented. Hardwired to 0.

0 Correctable Error Detected — RO. Not implemented. Hardwired to 0.

Bit Description

31:20 Next Capability Offset — RO. Hardwired to 130h. Points to the next capability header,

which is the Root Complex Link Declaration Enhanced Capability Header.

19:16 Capability Version — RO. Hardwired to 1h.

15:0 PCI Express* Extended Capability — RO. Hardwired to 0002h.

Intel® High Definition Audio Controller Registers (D27:F0)

660 Intel® ICH8 Family Datasheet

17.1.37 PVCCAP1—Port VC Capability Register 1

(Intel® High Definition Audio Controller—D27:F0)

Address Offset: 104h-107h Attribute: RO

Default Value: 00000001h Size: 32 bits

17.1.38 PVCCAP2 — Port VC Capability Register 2

(Intel® High Definition Audio Controller—D27:F0)

Address Offset: 108h-10Bh Attribute: RO

Default Value: 00000000h Size: 32 bits

17.1.39 PVCCTL — Port VC Control Register

(Intel® High Definition Audio Controller—D27:F0)

Address Offset: 10Ch-10Dh Attribute: RO

Default Value: 0000h Size: 16 bits

Bit Description

31:12 Reserved.

11:10 Port Arbitration Table Entry Size — RO. Hardwired to 0 since this is an endpoint device.

9:8 Reference Clock — RO. Hardwired to 0 since this is an endpoint device.

7 Reserved.

6:4 Low Priority Extended VC Count — RO. Hardwired to 0. Indicates that only VC0 belongs

to the low priority VC group

3 Reserved.

2:0 Extended VC Count — RO. Hardwired to 001b. Indicates that 1 extended VC (in addition

to VC0) is supported by the Intel® High Definition Audio controller.

Bit Description

31:24 VC Arbitration Table Offset — RO. Hardwired to 0 indicating that a VC arbitration table

is not present.

23:8 Reserved.

7:0 VC Arbitration Capability — RO . Hardwired to 0. These bits are not applicable since the

Intel® High Definition Audio controller reports a 0 in the Low Priority Extended VC

Count bits in the PVCCAP1 register.

Bit Description

15:4 Reserved.

3:1 VC Arbitration Select — RO. Hardwired to 0. Normal ly thes e bits are R/W. However,

these bits are not applicable since the Intel® High Definition Audio controller reports a

0 in the Low Priority Extended VC Count bits in the PVCCAP1 register.

0Load VC Arbitration Table — RO. Hardwired to 0 since an arbitration table is not

present.

Intel® ICH8 Family Datasheet 661

Intel® High Definition Audio Controller Registers (D27:F0)

17.1.40 PVCSTS—Port VC Status Register

(Intel® High Definition Audio Controller—D27:F0)

Address Offset: 10Eh–10Fh Attribute: RO

Default Value: 0000h Size: 16 bits

17.1.41 VC0CAP—VC0 Resource Capability Register

(Intel® High Definition Audio Controller—D27:F0)

Address Offset: 110h–113h Attribute: RO

Default Value: 00000000h Size: 32 bits

17.1.42 VC0CTL—VC0 Resource Control Register

(Intel® High Definition Audio Controller—D27:F0)

Address Offset: 114h–117h Attribute: R/W, RO

Default Value: 800000FFh Size: 32 bits

Bit Description

15:1 Reserved.

0VC Arbitration Table Status — RO. Hardwired to 0 since an arbitration table is not

present.

Bit Description

31:24 Port Arbitration Table Offset — RO. Hardwired to 0 since this field is not valid for

endpoint devices

23 Reserved.

22:16 Maximum Time Slots — RO. Hardwired to 0 since this field is not valid for endpoint

devices

15 Reject Snoop Transactions — RO. Hardwired to 0 since this fiel d is not valid for endpoint

devices.

14 Advanced Packet Switching — RO. Hardwired to 0 since this field is not valid for

endpoint devices

13:8 Reserved.

7:0 Port Arbitr ation Capability — RO . Hardwired to 0 since this field is not valid for endpoint

devices

Bit Description

31 VC0 Enable — RO. Hardwired to 1 for VC0.

30:27 Reserved.

26:24 VC0 ID — RO. Hardwired to 0 since the first VC is always assigned as VC0.

23:20 Reserved.

19:17 Port Arbitration Select — RO. Hardwired to 0 since this field is not valid for endpoint

devices.

16 Load Port Arbitr ation Table — RO. Hardwired to 0 since this field is not valid for endpoint

devices.

15:8 Reserved.

7:0 TC/VC0 Map — R/W, RO. Bit 0 is hardwire d to 1 since T C0 is always mapped VC0. Bits

7:1 are implemented as R/W bits.

Intel® High Definition Audio Controller Registers (D27:F0)

662 Intel® ICH8 Family Datasheet

17.1.43 VC0STS—VC0 Resource Status Register

(Intel® High Definition Audio Controller—D27:F0)

Address Offset: 11Ah–11Bh Attribute: RO

Default Value: 0000h Size: 16 bits

17.1.44 VCiCAP—VCi Resource Capability Register

(Intel® High Definition Audio Controller—D27:F0)

Address Offset: 11Ch–11Fh Attribute: RO

Default Value: 00000000h Size: 32 bits

Bit Description

15:2 Reserved.

1VC0 Negotiation Pending — RO. Hardwired to 0 since this bit does not apply to the

integrated Intel® High Definition Audio device.

0Port Arbitration Table Status — RO. Hardwired to 0 since this field is not valid for

endpoint devices.

Bit Description

31:24 Port Arbitration Table Offset — RO. Hardwired to 0 since this field is not valid for

endpoint devices.

23 Reserved.

22:16 Maximum Time Slots — RO. Hardwired to 0 since this field is not valid for endpoint

devices.

15 Reject Snoop Transactions — RO. Hardwired to 0 since this field is not valid for endpoint

devices.

14 Advanced Packet Switching — RO. Hardwired to 0 since this field is not valid for

endpoint devices.

13:8 Reserved

7:0 Port Arbitr ation Capability — RO. Hardwired to 0 since this field i s not valid for endpoint

devices.

Intel® ICH8 Family Datasheet 663

Intel® High Definition Audio Controller Registers (D27:F0)

17.1.45 VCiCTL—VCi Resource Control Register

(Intel® High Definition Audio Controller—D27:F0)

Address Offset: 120h–123h Attribute: R/W, RO

Default Value: 00000000h Size: 32 bits

17.1.46 VCiSTS—VCi Resource Status Register

(Intel® High Definition Audio Controller—D27:F0)

Address Offset: 126h–127h Attribute: RO

Default Value: 0000h Size: 16 bits

Bit Description

VCi Enable — R/W.

0 = Disabled

1 = Enabled

NOTE: This bit is not reset on D3HOT to D0 transition; however, it is reset by PLTRST#.

30:27 Reserved.

26:24 VCi ID — R/W. This field assigns a VC ID to the VCi resource. This field is not used by

the ICH8 hardware, but it is R/W to avoid confusing software.

23:20 Reserved.

19:17 Port Arbitration Select — RO. Hardwired to 0 since this field is not valid for endpoint

devices

16 Load Port Arbitr ation Table — RO. Hardwired to 0 since this field is not valid for endpoint

devices

15:8 Reserved.

7:0

TC/VCi Map — R/W, RO. This field indicates the TCs that are mapped to the VCi

resource. Bit 0 is hardwired to 0 indicating that it cannot be mapped to VCi. Bits [7:1]

are implemented as R/W bits. This field is not used by the ICH8 hardware, but it is R/W

to avoid confusing software.

Bit Description

15:2 Reserved.

1 VCi Negotiation Pending — RO. Does not apply. Hardwired to 0.

0Port Arbitration Table Status — RO. Hardwired to 0 since this field is not valid for

endpoint devices.

Intel® High Definition Audio Controller Registers (D27:F0)

664 Intel® ICH8 Family Datasheet

17.1.47 RCCAP—Root Complex Link Declaration Enhanced

Capability Header Register (Intel® High Definition Audio

Controller—D27:F0)

Address Offset: 130h Attribute: RO

Default Value: 00010005h Size: 32 bits

17.1.48 ESD—Element Self Description Register

(Intel® High Definition Audio Controller—D27:F0)

Address Offset: 134h–137h Attribute: RO

Default Value: 0F000100h Size: 32 bits

17.1.49 L1DESC—Link 1 Description Register

(Intel® High Definition Audio Controller—D27:F0)

Address Offset: 140h–143h Attribute: RO

Default Value: 00000001h Size: 32 bits

Bit Description

31:20 Next Capability Offset — RO. Hardwired to 0 indicating this is the last capability.

19:16 Capability Version — RO. Hardwired to 1h.

15:0 PCI Express* Extended Capability ID — RO. Hardwired to 0005h.

Bit Description

31:24 Port Number — RO. Hardwired to 0Fh indicating that the Intel® High Definition Audio

controller is assigned as Port #15d.

23:16 Component ID — RO. This field returns the value of the ESD.CID field of the chip

configuration section. ESD.CID is programmed by BIOS.

15:8 Number of Link Entri es — RO. The Intel High Definition Audio only connects to one

device, the ICH8 egress port. Therefore this field reports a value of 1h.

7:4 Reserved.

3:0 Element Type (ELTYP) — RO. The Intel High Definition Audio controller is an integrated

Root Complex Device. Therefore, the field reports a value of 0h.

Bit Description

31:24 Target Port Number — RO. The Intel High Definition Audio controller targets the Intel®

ICH8’s Port #0.

23:16 Target Component ID — RO. This field returns the value of the ESD .CID fiel d of the chip

configuration section. ESD.CID is programmed by BIOS.

15:2 Reserved.

1 Link Type — RO. Hardwired to 0 indicating Type 0.

0 Link Valid — RO. Hardwired to 1.

Intel® ICH8 Family Datasheet 665

Intel® High Definition Audio Controller Registers (D27:F0)

17.1.50 L1ADDL—Link 1 Lower Address Register

(Intel® High Definition Audio Controller—D27:F0)

Address Offset: 148h–14Bh Attribute: RO

Default Value: See Register Description Size: 32 bits

17.1.51 L1ADDU—Link 1 Upper Address Register

(Intel® High Definition Audio Controller—D27:F0)

Address Offset: 14Ch–14Fh Attribute: RO

Default Value: 00000000h Size: 32 bits

Bit Description

31:14 Link 1 Lower Address — RO . Hardwired to match the RCBA register value in the PCI-LPC

bridge (D31:F0:F0h).

13:0 Reserved.

Bit Description

31:0 Link 1 Upper Address — RO. Hardwired to 00000000h.

Intel® High Definition Audio Controller Registers (D27:F0)

666 Intel® ICH8 Family Datasheet

17.2 Intel® High Definition Audio Memory Mapped

Configuration Registers

(Intel® High Definition Audio— D27:F0)

The base memory location for these memory-mapped configuration registers is

specified in the HDBAR register (D27:F0, offset 10h and D27:F0, offset 14h). The

individual registers are then accessible at HDBAR + Offset as indicated in the following

table.

These memory-mapped registers must be accessed in byte, word, or DWord quantities.

Table 140. Intel® High Definition Audio PCI Register Address Map

(Intel® High Definition Audio D27:F0) (Sheet 1 of 4)

HDBAR +

Offset Mnemonic Register Name Default Access

00h–01h GCAP Global Capabilities 4401h RO

02h VMIN Minor Version 00h RO

03h VMAJ Major Version 01h RO

04h–05h OUTPAY Output Payload Capability 003Ch RO

06h–07h INPAY Input Payload Capability 001Dh RO

08h–0Bh GCTL Global Control 00000000h R/W

0Ch–0Dh WAKEEN Wake Enable 0000h R/W

0Eh–0Fh STATESTS State Change Status 0000h R/WC

10h–11h GSTS Global Status 0000h R/WC

12h–13h Rsv Reserved 0000h RO

14h–17h ECAP Extended Capabilities 00000001h RO

18h–19h OUTSTRMPAY Output Stream Payload Capability 0030h RO

1Ah–1Bh INSTRMPAY Input Stream Payload Capability 0018h RO

1Ch–1Fh Rsv Reserved 00000000h RO

20h–23h INTCTL Interrupt Control 00000000h R/W

24h–27h INTSTS Interrupt Status 00000000h RO

30h–33h WALCLK Wall Clock Counter 00000000h RO

34h–37h SSYNC Stream Synchronization 00000000h R/W

40h–43h CORBLBASE CORB Lower Base Address 00000000h R/W, RO

44h–47h CORBUBASE CORB Upper Base Address 00000000h R/W

48h–49h CORBWP CORB Write Pointer 0000h R/W

4Ah–4Bh CORBRP CORB Read Pointer 0000h R/W

4Ch CORBCTL CORB Control 00h R/W

4Dh CORBST CORB Status 00h R/WC

4Eh CORBSIZE CORB Size 42h RO

50h–53h RIRBLBASE RIRB Lower Base Address 00000000h R/W, RO

54h–57h RIRBUBASE RIRB Upper Base Address 00000000h R/W

58h–59h RIRBWP RIRB Write Pointer 0000h R/W, RO

Intel® ICH8 Family Datasheet 667

Intel® High Definition Audio Controller Registers (D27:F0)

5Ah–5Bh RINT CNT Response Interrupt Count 0000h R/W

5Ch RIRBCTL RIRB Control 00h R/W

5Dh RIRBSTS RIRB Status 00h R/WC

5Eh RIRBSIZE RIRB Size 42h RO

60h–63h IC Immediate Command 00000000h R/W

64h–67h IR Immediate Response 00000000h RO

68h–69h IRS Immediate Command Status 0000h R/W, R/

70h–73h DPLBASE DMA Position Lower Base Address 00000000h R/W, RO

74h–77h DPUBASE DMA Position Upper Base Address 00000000h R/W

80–82h ISD0CTL Input Stream Descriptor 0 (ISD0)

Control 040000h R/W, RO

83h ISD0STS ISD0 Status 00h R/WC, RO

84h–87h ISD0LPIB ISD0 Link Position in Buffer 00000000h RO

88h–8Bh ISD0CBL ISD0 Cyclic Buffer Length 00000000h R/W

8Ch–8Dh ISD0LVI ISD0 Last Valid Index 0000h R/W

8Eh–8F ISD0FIFOW ISD0 FIFO Watermark 0004h R/W

90h–91h ISD0FIFOS ISD0 FIFO Size 0077h RO

92h–93h ISD0FMT ISD0 Format 0000h R/W

98h–9Bh ISD0BDPL ISD0 Buffer Descriptor List Pointer-

Lower Base Address 00000000h R/W, RO

9Ch–9Fh ISD0BDPU ISD0 Buffer Description List Pointer-

Upper Base Address 00000000h R/W

A0h–A2h ISD1CTL Input Stream Descriptor 1(ISD01)

Control 040000h R/W, RO

A3h ISD1STS ISD1 Status 00h R/WC, RO

A4h–A7h ISD1LPIB ISD1 Link Position in Buffer 00000000h RO

A8h–ABh ISD1CBL ISD1 Cyclic Buffer Length 00000000h R/W

ACh–ADh ISD1LVI ISD1 Last Valid Index 0000h R/W

AEh–AFh ISD1FIFOW ISD1 FIFO Watermark 0004h R/W

B0h–B1h ISD1FIFOS ISD1 FIFO Size 0077h RO

B2h–B3h ISD1FMT ISD1 Format 0000h R/W

B8h–BBh ISD1BDPL ISD1 Buffer Descriptor List Pointer-

Lower Base Address 00000000h R/W, RO

BCh–BFh ISD1BDPU ISD1 Buffer Description List Pointer-

Upper Base Address 00000000h R/W

C0h–C2h ISD2CTL Input Stream Descriptor 2 (ISD2)

Control 040000h R/W, RO

C3h ISD2STS ISD2 Status 00h R/WC, RO

Table 140. Intel® High Definition Audio PCI Register Address Map

(Intel® High Definition Audio D27:F0) (Sheet 2 of 4)

HDBAR +

Offset Mnemonic Register Name Default Access

Intel® High Definition Audio Controller Registers (D27:F0)

668 Intel® ICH8 Family Datasheet

C4h–C7h ISD2LPIB ISD2 Link Position in Buffer 00000000h RO

C8h–CBh ISD2CBL ISD2 Cyclic Buffer Length 00000000h R/W

CCh–CDh ISD2LVI ISD2 Last Valid Index 0000h R/W

CEh–CFh ISD1FIFOW ISD1 FIFO Watermark 0004h R/W

D0h–D1h ISD2FIFOS ISD2 FIFO Size 0077h RO

D2h–D3h ISD2FMT ISD2 Format 0000h R/W

D8h–DBh ISD2BDPL ISD2 Buffer Descriptor List Pointer-

Lower Base Address 00000000h R/W, RO

DCh–DFh ISD2BDPU ISD2 Buffer Description List Pointer-

Upper Base Address 00000000h R/W

E0h–E2h ISD3CTL Input Stream Descriptor 3 (ISD3)

Control 040000h R/W, RO

E3h ISD3STS ISD3 Status 00h R/WC, RO

E4h–E7h ISD3LPIB ISD3 Link Position in Buffer 00000000h RO

E8h–EBh ISD3CBL ISD3 Cyclic Buffer Length 00000000h R/W

ECh–EDh ISD3LVI ISD3 Last Valid Index 0000h R/W

EEh–EFh ISD3FIFOW ISD3 FIFO Watermark 0004h R/W

F0h–F1h ISD3FIFOS ISD3 FIFO Size 0077h RO

F2h–F3h ISD3FMT ISD3 Format 0000h R/W

F8h–FBh ISD3BDPL ISD3 Buffer Descriptor List Pointer-

Lower Base Address 00000000h R/W, RO

FCh–FFh ISD3BDPU ISD3 Buffer Description List Pointer-

Upper Base Address 00000000h R/W

100h–102h OSD0CTL Output Stream Descriptor 0 (OSD0)

Control 040000h R/W, RO

103h OSD0STS OSD0 Status 00h R/WC, RO

104h–107h OSD0LPIB OSD0 Link Position in Buffer 00000000h RO

108h–10Bh OSD0CBL OSD0 Cyclic Buffer Length 00000000h R/W

10Ch–10Dh OSD0LVI OSD0 Last Valid Index 0000h R/W

10Eh–10Fh OSD0FIFOW OSD0 FIFO Watermark 0004h R/W

110h–111h OSD0FIFOS OSD0 FIFO Size 00BFh R/W

112h–113h OSD0FMT OSD0 Format 0000h R/W

118h–11Bh OSD0BDPL OSD0 Buffer Descriptor List Pointer-

Lower Base Address 00000000h R/W, RO

11Ch–11Fh OSD0BDPU OSD0 Buffer Description List Pointer-

Upper Base Address 00000000h R/W

120h–122h OSD1CTL Output Stream Descriptor 1 (OSD1)

Control 040000h R/W, RO

123h OSD1STS OSD1 Status 00h R/WC, RO

Table 140. Intel® High Definition Audio PCI Register Address Map

(Intel® High Definition Audio D27:F0) (Sheet 3 of 4)

HDBAR +

Offset Mnemonic Register Name Default Access

Intel® ICH8 Family Datasheet 669

Intel® High Definition Audio Controller Registers (D27:F0)

124h–127h OSD1LPIB OSD1 Link Position in Buffer 00000000h RO

128h–12Bh OSD1CBL OSD1 Cyclic Buffer Length 00000000h R/W

12Ch–12Dh OSD1LVI OSD1 Last Valid Index 0000h R/W

12Eh–12Fh OSD1FIFOW OSD1 FIFO Watermark 0004h R/W

130h–131h OSD1FIFOS OSD1 FIFO Size 00BFh R/W

132h–133h OSD1FMT OSD1 Format 0000h R/W

138h–13Bh OSD1BDPL OSD1 Buffer Descriptor List Pointer-

Lower Base Address 00000000h R/W, RO

13Ch–13Fh OSD1BDPU OSD1 Buffer Description List Pointer-

Upper Base Address 00000000h R/W

140h–142h OSD2CTL Output Stream Descriptor 2 (OSD2)

Control 040000h R/W, RO

143h OSD2STS OSD2 Status 00h R/WC, RO

144h–147h OSD2LPIB OSD2 Link Position in Buffer 00000000h RO

148h–14Bh OSD2CBL OSD2 Cyclic Buffer Length 00000000h R/W

14Ch–14Dh OSD2LVI OSD2 Last Valid Index 0000h R/W

14Eh–14Fh OSD2FIFOW OSD2 FIFO Watermark 0004h R/W

150h–151h OSD2FIFOS OSD2 FIFO Size 00BFh R/W

152h–153h OSD2FMT OSD2 Format 0000h R/W

158h–15Bh OSD2BDPL OSD2 Buffer Descriptor List Pointer-

Lower Base Address 00000000h R/W, RO

15Ch–15Fh OSD2BDPU OSD2 Buffer Description List Pointer-

Upper Base Address 00000000h R/W

160h–162h OSD3CTL Output Stream Descriptor 3 (OSD3)

Control 040000h R/W, RO

163h OSD3STS OSD3 Status 00h R/WC, RO

164h–167h OSD3LPIB OSD3 Link Position in Buffer 00000000h RO

168h–16Bh OSD3CBL OSD3 Cyclic Buffer Length 00000000h R/W

16Ch–16Dh OSD3LVI OSD3 Last Valid Index 0000h R/W

16Eh–16Fh OSD3FIFOW OSD3 FIFO Watermark 0004h R/W

170h–171h OSD3FIFOS OSD3 FIFO Size 00BFh R/W

172h–173h OSD3FMT OSD3 Format 0000h R/W

178h–17Bh OSD3BDPL OSD3 Buffer Descriptor List Pointer-

Lower Base Address 00000000h R/W, RO

17Ch–17Fh OSD3BDPU OSD3 Buffer Description List Pointer-

Upper Base Address 00000000h R/W

Table 140. Intel® High Definition Audio PCI Register Address Map

(Intel® High Definition Audio D27:F0) (Sheet 4 of 4)

HDBAR +

Offset Mnemonic Register Name Default Access

Intel® High Definition Audio Controller Registers (D27:F0)

670 Intel® ICH8 Family Datasheet

17.2.1 GCAP—Global Capabilities Register

(Intel® High Definition Audio Controller—D27:F0)

Memory Address:HDBAR + 00h Attribute: RO

Default Value: 4401h Size: 16 bits

17.2.2 VMIN—Minor Version Register

(Intel® High Definition Audio Controller—D27:F0)

Memory Address:HDBAR + 02h Attribute: RO

Default Value: 00h Size: 8 bits

17.2.3 VMAJ—Major Version Register

(Intel® High Definition Audio Controller—D27:F0)

Memory Address:HDBAR + 03h Attribute: RO

Default Value: 01h Size: 8 bits

Bit Description

15:12 Number of Output Stream Supported — RO. Hardwired to 0100b indicating that the

ICH8 Intel® High Definition Audio controller supports 4 output streams.

11:8 Number of Input Stream Supported — RO. Hardwired to 0100b indicating that the ICH8

Intel High Definition Audio controller supports 4 input streams.

7:3 Number of Bidirectional Stream Supported — RO. Hardwired to 0 indicating that the

ICH8 Intel High Definition Audio controller supports 0 bidirectional stream.

2 Reserved.

1Number of Serial Data Out Signals — RO. Hardwired to 0 indicating that the ICH8 Intel

High Definition Audio controller supports 1 serial data output signal.

064-bit Address Supported — RO. Hardwired to 1b indicating that the ICH8 Intel High

Definition Audio controller supports 64-bit addressing for BDL addresses, data buffer

addressees, and command buffer addresses.

Bit Description

7:0 Minor Version — RO. Hardwired to 0 indicating that the Intel® ICH8 supports minor

revision number 00h of the Intel® High Definition Audio specification.

Bit Description

7:0 Major Version — RO. Hardwired to 01h indicat ing that the Intel® ICH8 supports major

revision number 1 of the Intel® High Definition Audio specification.

Intel® ICH8 Family Datasheet 671

Intel® High Definition Audio Controller Registers (D27:F0)

17.2.4 OUTPAY—Output Payload Capability Register

(Intel® High Definition Audio Controller—D27:F0)

Memory Address:HDBAR + 04h Attribute: RO

Default Value: 003Ch Size: 16 bits

17.2.5 INPAY—Input Payload Capability Register

(Intel® High Definition Audio Controller—D27:F0)

Memory Address:HDBAR + 06h Attribute: RO

Default Value: 001Dh Size: 16 bits

Bit Description

15:7 Reserved.

6:0

Output Payload Capability — RO. Hardwired to 3Ch indicating 60 word payload.

This field indicates the total output payload available on the link. This does not include

bandwidth used for command and control. This measurement is in 16-bit word

quantities per 48 MHz frame. The default link clock of 24.000 MHz (the data is double

pumped) provides 1000 bits per frame, or 62.5 words in total. 40 bits are used for

command and control, leaving 60 words available for data payload.

00h = 0 word

01h = 1 word payload.

.....

FFh = 256 word payload.

Bit Description

15:7 Reserved.

6:0

Input Payload Capability — RO. Hardwired to 1Dh indicating 29 word payload.

This field indicates the total output payload available on the link. This does not include

bandwidth used for response. This measurement is in 16-bit word quantities per 48

MHz frame. The default link clock of 24.000 MHz provides 500 bits per frame, or

31.25 words in total. 36 bits are used for response, l ea ving 29 words available for data

payload.

00h = 0 word

01h = 1 word payload.

.....

FFh = 256 word payload.

Intel® High Definition Audio Controller Registers (D27:F0)

672 Intel® ICH8 Family Datasheet

17.2.6 GCTL—Global Control Register

(Intel® High Definition Audio Controller—D27:F0)

Memory Address:HDBAR + 08h Attribute: R/W

Default Value: 00000000h Size: 32 bits

Bit Description

31:9 Reserved.

Accept Unsolicited Respon se Enable — R/W.

0 = Unsolicited response s from the codecs are not accepted.

1 = Unsolicited response from the codecs are accepted by the controller and placed

into the Response Input Ring Buffer.

7:2 Reserved.

Flush Control — R/W. Writing a 1 to this bit initiates a flush. When the flush

completion is receiv ed by the controll er, hardw are sets the Flush Status bit and clears

this Flush Control bit. Before a flush cy cle is initiat ed, the DMA Position Buffer must be

programmed with a valid memory address by software, but the DMA Position Buffer

bit 0 needs not be set to enable the position reporting mechanism. Also, all streams

must be stopped (the associated RUN bit must be 0).

When the flush is initiated, the controller will flush the pipelines to memory to assure

that the hardware is ready to transition to a D3 state. Settin g this bit is not a criti cal

step in the power state transition if the co ntent of the FIFIO s is not critical.

Controller Reset # — R/W.

0 = Writing a 0 resets the Intel High Definition Audio controller. All state machines,

FIFOs and non-resume well memory mapped configuration registers (not PCI

configuration registers) in the controller will be reset. The Intel High Definition

Audio link RESET# signal will be asserted, and all other link signals will be driven

to their default values. After the hardware has completed sequencing into t he

reset state, it will report a 0 in this bit. Software must read a 0 from this bit to

verify the controller is in reset.

1 = Writing a 1 causes the controller to exit its reset state and de-assert the Intel

High Definition Audio link RESET# signal. Software is responsible for setting/

clearing this bit such that the minimum Intel High Defi nition Audio link RESET#

signal assertion pulse width specification is met. When the controller hardware is

ready to begin operation, it will report a 1 in thi s bit. Software must read a 1 from

this bit before accessing any controller registers. This bit defaults to a 0 after

Hardware reset, therefore, software needs to write a 1 to this bit to begin

operation.

NOTES:

1. The CORB/RIRB RUN bits and all stream RUN bits must be verified cleared to 0

before writing a 0 to this bit in order to assure a clean re-start.

2. When setting or clearing this bit, software must ensure that minimum link

timing requirements (minimum RESET# assertion time, etc.) are met.

3. When this bit is 0 indicating that the controller is in reset, writes to all Intel

High Definition Audio memory mapped registers are ignored as if the device is

not present. T he only exception is th is register itself. The Global Control

0 if the byte enable for the byte containing the CRST# bit (Byte Enable 0) is

active. If Byte Enable 0 is not active, writes to the Global Control register will

be ignored when CRST# is 0. When CRST# is 0, reads to Intel High Definition

Audio memory mapped registers will return their default value except for

registers that are not reset with PLTRST# or on a D3HOT to D0 transition.

Intel® ICH8 Family Datasheet 673

Intel® High Definition Audio Controller Registers (D27:F0)

17.2.7 WAKEEN—Wake Enable Register

(Intel® High Definition Audio Controller—D27:F0)

Memory Address:HDBAR + 0Ch Attribute: R/W

Default Value: 0000h Size: 16 bits

17.2.8 STATESTS—State Change Status Register

(Intel® High Definition Audio Controller—D27:F0)

Memory Address:HDBAR + 0Eh Attribute: R/WC

Default Value: 0000h Size: 16 bits

Bit Description

15:4 Reserved.

3:0

SDIN Wake Enable Flags — R/W. These bits control which SDI signal(s) may

generate a wake event. A 1b in the bit mask indicates that the associated SDIN signal is

enabled to generate a wake.

Bit 0 is used for SDI[0]

Bit 1 is used for SDI[1]

Bit 2 is used for SDI[2]

Bit 3 is used for SDI[3]

NOTE: These bits are in the resume well and only cleared on a power on reset.

Software must not make assumptions abou t the reset state of t hese bits and

must set them appropriately.

Bit Description

15:4 Reserved.

3:0

SDIN State Change Status Flags — R/WC. Flag bits that indicate which SDI signal(s )

received a state change event. The bits are cleared by writing 1’s to them.

Bit 0 = SDI[0]

Bit 1 = SDI[1]

Bit 2 = SDI[2]

Bit 3 = SDI[3]

NOTE: These bits are in the resume well and only cleared on a power on reset.

Software must not make assumptions abou t the reset state of t hese bits and

must set them appropriately.

Intel® High Definition Audio Controller Registers (D27:F0)

674 Intel® ICH8 Family Datasheet

17.2.9 GSTS—Global Status Register

(Intel® High Definition Audio Controller—D27:F0)

Memory Address:HDBAR + 10h Attribute: R/WC

Default Value: 0000h Size: 16 bits

Bit Description

15:4 Reserved.

(Mobile

Only)

Dock Mated Interrupt Status (DMIS) — R/W/C. A 1 indicates that the dock

mating or unmating process has completed. F or the docking process it indicates that

dock is electrically connected and that software may detect and enumerate the

docked codecs. For the undocking process it indicates that the dock is electrically

isolated and that software may report to the user that physical undocking may

commence. This bit gets set to a 1 by hardware when the DM bit transitions from a 0

to a 1 (docking) or from a 1 to a 0 (undocking). Note th at this bit is set regardl ess of

the state of the DMIE bi t.

Software clears this bit by writing a 1 to it. Writing a 0 to this bit has no affect.

(Desktop

Only) Reserved

(Mobile

Only)

Dock Mated (DM)—RO. This bit effectively communicates to software that an Intel®

HD Audio docked codec is physically and electrically attached.

Controller hardware sets this bit to 1 after the docking sequence triggered b y writing

a 1 to the Dock Attach (GCTL.DA) bit is completed (HDA_DOCK_RST# deassertion).

This bit indicates to software that the docked codec(s) may be discovered via the

STATESTS register and then enumerated.

Controller hardware sets this bit to 0 after the undocking sequence triggered by

writing a 0 to the Dock Attach (GCTL.DA ) bi t is compl eted (D OCK_ EN# deasserted).

This bit indicates to software that the docked codec(s) may be physically undocked.

This bit is Read Only. Writes to this bit have no effect.

(Desktop

Only) Reserved

Flush Status — R/WC. This bit is set to 1 by hardware to indicate that the flush

cycle initiated when the Flush Control bit (HDBAR + 08h, bit 1) was set has

completed. Software must write a 1 to clear this bit before the next time the Flush

Control bit is set to clear the bit.

0 Reserved.

Intel® ICH8 Family Datasheet 675

Intel® High Definition Audio Controller Registers (D27:F0)

17.2.10 ECAP—Extended Capabilities

(Intel® High Definition Audio Controller—D27:F0)

Memory Address:HDBAR + 14h Attribute: R/WO

Default Value: 00000001h Size: 32 bits

17.2.11 OUTSTRMPAY—Output Stream Payload Capability

(Intel® High Definition Audio Controller—D27:F0)

Memory Address:HDBAR + 18h Attribute: RO

Default Value: 0030h Size: 16 bits

Bit Description

31:1 Reserved

Docking Supported (DS)— R/WO. A 1 indicates that Inte l® ICH8 supports Intel® HD

Audio Docking. The GCTL.DA bit is only writable when this DS bit is 1. Intel HD Audio

driver software should only branch to its docking routine when this DS bit is 1. BIOS

may clear this bit to 0 to prohibit the Intel HD Audio driver software from attempting to

run the docking routines.

Note that this bit is reset to its default value only on a PLTRST#, but not on a CRST# or

D3hot-to-D0 transition.

Bit Description

15:14

Output FIFO Padding Type (OPADTYPE)— RO. This field indicates how the

controller pads the samples in the controller's buffer (FIFO). Controllers may not pad at

all or may pad to byte or memory container sizes.

0h = Controller pads all samples to bytes

1h = Reserved

2h = Controller pads to memory container size

3h = Controller does not pad and uses samples directly

13:0

Output Stream Payload Capability (O UTSTRMPAY)— RO. This field indicates

maximum number of words per frame for any single outpu t stream. Th is measu rem ent

is in 16-bit word quantities per 48 kHz frame. The maximum supported is 48 Words

(96B); therefore, a value of 30h is reported in this regist er. The value does not specify

the number of words actually tr ansmitted in the fr ame, but is the siz e of the data in the

controller buffer (FIFO) after the samples are padded as specified by OPADTYPE. Thus,

to compute the support ed streams, eac h sample is padded according to OPAD TYPE and

then multiplied by the number of channels and samp les per frame. If this computed

value is larger than OUTSTRMPAY, then that stream is not supported. The value

specified is not affected by striping.

Software must ensure that a format which would cause more Words per frame than

indicated is not programmed into the Output Stream Descriptor Register.

The value may be larger than the OUTPAY register value in some cases.

Intel® High Definition Audio Controller Registers (D27:F0)

676 Intel® ICH8 Family Datasheet

17.2.12 INSTRMPAY—Input Stream Payload Capability

(Intel® High Definition Audio Controller—D27:F0)

Memory Address:HDBAR + 1Ah Attribute: RO

Default Value: 0018h Size: 16 bits

Bit Description

15:14

Input FIFO Padding Type (IPADTYPE)— RO. This field indicates how the controller

pads the samples in the controller's buffer (FIFO). Controllers may not pad at all or may

pad to byte or memory container sizes.

0h = Controller pads all samples to bytes

1h = Reserved

2h = Controller pads to memory container size

3h = Controller does not pad and uses samples directly

13:0

Input Stream Payload Capability (INSTRMPAY)— RO. This field indicates the

maximum number of W ords per frame for any single input stre am. This measurement is

in 16-bit Word quantities per 48-kHz frame. The maximum supported is 24 Words

(48B); therefore, a value of 18h is reported in this register.

The value does not specify the number of words actually transmitted in the frame, but

is the size of the data as it will be placed into the controller's buffer (FIFO). Thus

samples will be padded according to IPADTYPE before being stored into controller

buffer. To compute the supported streams, each sample is padded according to

IPADTYPE and then multiplied by the number of channels and samples per frame. If this

computed value is larger than INSTRMPAY then that stream is not supported. As the

inbound stream tag is not stored with the samples it is not included in the word count.

The value may be larger than INPAY register value in some cases, although values less

than INPAY may also be invalid due to overhead. Software must ensure that a format

which would cause more Words per frame than indicated is not programmed into the

Input Stream Descriptor Register.

Intel® ICH8 Family Datasheet 677

Intel® High Definition Audio Controller Registers (D27:F0)

17.2.13 INTCTL—Interrupt Control Register

(Intel® High Definition Audio Controller—D27:F0)

Memory Address:HDBAR + 20h Attribute: R/W

Default Value: 00000000h Size: 32 bits

Bit Description

Global Interrupt Enable (GIE) — R/W. Global bit to enable device interrupt

generation. When set to 1, the Intel® High Definition Audio function is enabled to

generate an interrupt. This control is in addition to any bits in the bus specific address

space, such as the Interrupt Enable bit in the PCI configuration space.

0 = Disable

1 = Enable

NOTE: This bit is not affected by the D3HOT to D0 transition.

Controller Interrupt Enable (CIE) — R/W. Enables the general interrupt for

controller functions.

When set to 1, the contro ll er gen erates an inte rrupt whe n the corresponding status bit

gets set due to a Response Interrupt, a Response Buffer Overrun, and State Change

events.

NOTE: This bit is not affected by the D3HOT to D0 transition.

29:8 Reserved

7:0

Stream Interrupt Enable (SIE) — R/W. When set to 1, the individual streams are

enabled to generate an interrupt when the corresponding status bits get set.

A stream interrupt will be caused as a result of a buffer with IOC = 1in the BDL entry

being completed, or as a result of a FIFO error (underrun or ove rrun) occurring. Control

over the generation of each of these sources is in the associated Stream Descriptor.

The streams are numbered and the SIE bits assigned sequentially, based on their order

in the register set.

Bit 0: input stream 1

Bit 1: input stream 2

Bit 2: input stream 3

Bit 3: input stream 4

Bit 4: output stream 1

Bit 5: output stream 2

Bit 6: output stream 3

Bit 7: output stream 4

Intel® High Definition Audio Controller Registers (D27:F0)

678 Intel® ICH8 Family Datasheet

17.2.14 INTSTS—Interrupt Status Regist er

(Intel® High Definition Audio Controller—D27:F0)

Memory Address:HDBAR + 24h Attribute: RO

Default Value: 00000000h Size: 32 bits

Bit Description

Global Interrupt Status (GIS) — RO. This bit is an OR of all the interrupt status bits in

this register.

NOTE: This bit is not affected by the D3HOT to D0 transition.

Controller Interrupt Status (CIS) — RO. Status of general controller interrupt.

1 = Interrupt condition occurred due to a Response Interru pt, a Response Buffer

Overrun Interrupt, or a SDIN State Change event. The exact cause can be

determined by interrogating other registers. This bit is an OR of all of the stated

interrupt status bits for this register.

NOTES:

1. This bit is set regardless of the state of the corresponding interrupt enable bit,

but a hardware interrupt will not be gener at ed unless the corr es pondin g enable

bit is set.

2. This bit is not affected by the D3HOT to D0 transition.

29:8 Reserved

7:0

Stream Interrupt S tat us (S IS) — RO.

1 = Interrupt condition occurred on the corresponding stream. This bit is an O R of all of

the stream’s interrupt status bits.

NOTE: These bits are set regardless of th e state of the corresponding interrupt enable

bits.

The streams are numbered and the SIE bits assigned sequentially, based on their order

in the register set.

Bit 0: input stream 1

Bit 1: input stream 2

Bit 2: input stream 3

Bit 3: input stream 4

Bit 4: output stream 1

Bit 5: output stream 2

Bit 6: output stream 3

Bit 7: output stream 4

Intel® ICH8 Family Datasheet 679

Intel® High Definition Audio Controller Registers (D27:F0)

17.2.15 WALCLK—Wall Clock Counter Register

(Intel® High Definition Audio Controller—D27:F0)

Memory Address:HDBAR + 30h Attribute: RO

Default Value: 00000000h Size: 32 bits

17.2.16 SSYNC—Stream Synchronization Register

(Intel® High Definition Audio Controller—D27:F0)

Memory Address:HDBAR + 34h Attribute: R/W

Default Value: 00000000h Size: 32 bits

Bit Description

31:0

Wall Clock Counter — RO. This field provides results from a 32 bit counter that is

incremented on each link BCLK period and rolls over from FFFF FFFFh to 0000 0000h.

This counter will roll over to 0 with a period of approximately 179 seconds.

This counter is enabled while the BCLK bit is set to 1. Software uses this counter to

synchronize between multiple controllers. Will be reset on controller reset.

Bit Description

31:8 Reserved

7:0

Stream Synchronization (SSYNC) — R/W. When set to 1, these bits block data from

being sent on or received from the link. Each bit controls the associated stream

descriptor (i.e., bit 0 corresponds to the first stream descriptor, et c.)

To synchronously start a set of DMA engines, these bits are first set to 1. The RUN bits

for the associated stream descriptors are then set to 1 to start the DMA engines. When

all streams are ready (FIFORDY =1), the associated SSYNC bits can all be set to 0 at

the same time, and transmission or reception of bits to or from the link will begin

together at the start of the next full link frame.

To synchr onously stop the streams, fist these bits are set, and then the individual RUN

bits in the stream descriptor are cleared by software.

If synchronization is not desired, these bits may be left as 0, and the stream will simply

begin running normally when the stream’s RUN bit is set.

The streams are numbered and the SIE bits assigned sequentially, based on their order

in the register set.

Bit 0: input stream 1

Bit 1: input stream 2

Bit 2: input stream 3

Bit 3: input stream 4

Bit 4: output stream 1

Intel® High Definition Audio Controller Registers (D27:F0)

680 Intel® ICH8 Family Datasheet

17.2.17 CORBLBASE—CORB Lower Base Address Register

(Intel® High Definition Audio Controller—D27:F0)

Memory Address:HDBAR + 40h Attribute: R/W, RO

Default Value: 00000000h Size: 32 bits

17.2.18 CORBUBASE—CORB Upper Base Address Register

(Intel® High Definition Audio Controller—D27:F0)

Memory Address:HDBAR + 44h Attribute: R/W

Default Value: 00000000h Size: 32 bits

17.2.19 CORBWP—CORB Write Pointer Register

(Intel® High Definition Audio Controller—D27:F0)

Memory Address:HDBAR + 48h Attribute: R/W

Default Value: 0000h Size: 16 bits

Bit Description

31:7

CORB Lower Base Address — R/W. This field provides the lower address of the

Command Output Ring Buffer, allowing the CORB base address to be assigned on any

128-B boundary. Th is register field must not be written when the DMA engine is

running or the DMA transfer may be corrupted.

6:0 CORB Lower Base Unimplemented Bits — RO. Hardwired to 0. This required the CORB

to be allocated with 128B granularity to allow for cache line fetch optimizations.

Bit Description

31:0 CORB Upper Base Address — R/W. This field provides the upper 32 bits of the

address of the Command Output Ring buffer. This register field must not be written

when the DMA engine is running or the DMA transfer may be corrupted.

Bit Description

15:8 Reserved.

7:0

CORB Write Pointer — R/W. Software writes the last valid CORB entry offset into this

field in DWord granularity. The DMA engine fetches commands from the CORB until the

Read pointer matches the Write pointer; supports 256 CORB entries (256x4B = 1 KB).

This register field may be written when the DMA engine is running.

Intel® ICH8 Family Datasheet 681

Intel® High Definition Audio Controller Registers (D27:F0)

17.2.20 CORBRP—CORB Read Pointer Register

(Intel® High Definition Audio Controller—D27:F0)

Memory Address:HDBAR + 4A h Attribute: R/W

Default Value: 0000h Size: 16 bits

17.2.21 CORBCTL—CORB Control Regi ster

(Intel® High Definition Audio Controller—D27:F0)

Memory Address:HDBAR + 4Ch Attribute: R/W

Default Value: 00h Size: 8 bits

Bit Description

CORB Read Pointer Reset — R/W. Software writes a 1 to this bit to reset the CORB

Read Pointer to 0 and clear any residual prefetched commands in the CORB hardware

buffer within the High Definition Audio controller. The hardware will physically update

this bit to 1 when the CORB Pointer reset is complete. Software must read a 1 to verify

that the reset completed correctly. Software must clear this bit back to 0 and read back

the 0 to verify that the clear completed correctly. The CORB DMA engine must be

stopped prior to resetting the Read Pointer or else DMA transfer may be corrupted.

14:8 Reserved.

7:0

CORB Read Pointer (CORBRP)— RO. Software reads this field to determine how many

commands it can write to the CORB without over-running. The value read indicates the

CORB Read P ointer offset in DW ord gr anularity. The offset entry read from this field has

been successfully fetched by the DMA controller and may be over-written by software;

supports 256 CORB entries (256 x 4B=1KB). This field may be read while the DMA

engine is running.

Bit Description

7:2 Reserved.

Enable CORB DMA Engine — R/W. After software writes a 0 to this bit, the hardware

may not stop immediately. The hardware will physically update the bit to 0 when the

DMA engine is truly stopped. Software must read a 0 from this bit to verify that the

DMA engine is truly stopped.

0 = DMA stop

1 = DMA run

CORB Memory Error Interrupt Enab le — R/W.

0 = Disable

1 = Enable. The controller will generate an interrupt if the CMEI stat us bit (HDBAR +

4Dh: bit 0) is set.

Intel® High Definition Audio Controller Registers (D27:F0)

682 Intel® ICH8 Family Datasheet

17.2.22 CORBST—CORB Status Register

(Intel® High Definition Audio Controller—D27:F0)

Memory Address:HDBAR + 4Dh Attribute: R/WC

Default Value: 00h Size: 8 bits

17.2.23 CORBSIZE—CORB Size Register

Intel® High Definition Audio Controller—D27:F0)

Memory Address:HDBAR + 4Eh Attribute: RO

Default Value: 42h Size: 8 bits

17.2.24 RIRBLBASE—RIRB Lower Base Address Register

(Intel® High Definition Audio Controller—D27:F0)

Memory Address:HDBAR + 50h Attribute: R/W, RO

Default Value: 00000000h Size: 32 bits

Bit Description

7:1 Reserved.

CORB Memory Error Indication (CMEI) — R/WC. Software can clear this bit by

writing a 1 to it. However, this type of error leaves the audio subsystem in an un- viable

state and typically required a controller reset by wri ting a 0 to the Controller R eset # bit

(HDBAR + 08h: bit 0).

0 = Error Not detected.

1 = Controller has detected an error in the path way between the controller and

memory. This may be an ECC bit error or any other type of detectable data error

which renders the command data fetched invalid.

Bit Description

7:4 CORB Size Capability — RO. Hardwired to 0100b i ndicating that the ICH8 only supports

a CORB size of 256 CORB entries (1024B).

3:2 Reserved.

1:0 CORB Size — RO. Hardwired to 10b which sets the CORB size to 256 entries (1024B).

Bit Description

31:7

CORB Lower Base Address — R/W. This field provides the lower address of the

Response Input Ring Buffer, allowing the RIRB base address to be assigned on any

128-B boundary. Th is register field must not be written when the DMA engine is

running or the DMA transfer may be corrupted.

6:0 RIRB Lower Base Unimplemented Bits — RO. Hardwired to 0. This required the RIRB to

be allocated with 128-B granularity to allow for cache line fe tc h opti mizat ion s .

Intel® ICH8 Family Datasheet 683

Intel® High Definition Audio Controller Registers (D27:F0)

17.2.25 RIRBUBASE—RIRB Upper Base Address Register

(Intel® High Definition Audio Controller—D27:F0)

Memory Address:HDBAR + 54h Attribute: R/W

Default Value: 00000000h Size: 32 bits

17.2.26 RIRBWP—RIRB Write Pointer Register

(Intel® High Definition Audio Controller—D27:F0)

Memory Address:HDBAR + 58h Attribute: R/W, RO

Default Value: 0000h Size: 16 bits

Bit Description

31:0 RIRB Upper Base Address — R/W. This field provides the upper 32 bits of the

address of the Response Input Ring Buffer. This register field mu st not be written whe n

the DMA engine is running or the DMA transfer may be corrupted.

Bit Description

RIRB Write Pointer Reset — R/W. Software writes a 1 to this bit to reset the RIRB

Write Pointer to 0. The RIRB DMA engine must be stopped prior to resetting the Write

Pointer or else DMA transfer may be corrupted.

NOTE: This bit is always read as 0.

14:8 Reserved.

7:0

RIRB Write Pointer (RIRBWP) — RO. This field indicates the last valid RIRB entry written

by the DMA controller. Software reads this field to determine how many responses it

can read from the RIRB. The value read indicates the RIRB Write Pointer offset in

2 DWord RIRB entry units (since each RIRB entry is 2 DWords long); supports up to

256 RIRB entries (256 x 8 B = 2 KB). This register field may be written when the DMA

engine is running.

Intel® High Definition Audio Controller Registers (D27:F0)

684 Intel® ICH8 Family Datasheet

17.2.27 RINTCNT—Response Interrupt Count Register

(Intel® High Definition Audio Controller—D27:F0)

Memory Address:HDBAR + 5Ah Attribute: R/W

Default Value: 0000h Size: 16 bits

17.2.28 RIRBCTL—RIRB Control Register

(Intel® High Definition Audio Controller—D27:F0)

Memory Address:HDBAR + 5Ch Attribute: R/W

Default Value: 00h Size: 8 bits

Bit Description

15:8 Reserved.

31:0

N Response Interrupt Count — R/W.

0000 0001b = 1 response sent to RIRB

...........

1111 1111b = 255 responses sent to RIRB

0000 0000b = 256 responses sent to RIRB

The DMA engine should be stopped when changing this field; otherwise, an interrupt

may be lost.

Note that each re sponse occupies 2 DWords in the RIRB.

This is compared to the total numbe r of responses that hav e been returned, as opposed

to the number of frames in which there were responses. If more than one codecs

responds in one frame, then the count is increased by the number of responses

received in the frame.

Bit Description

7:3 Reserved.

2Response Overrun Interrupt Control — R/W. If this bit is set, the hardware will

gener ate an in terru pt whe n th e Response O ver run In terrupt St atus bit (HDBAR + 5Dh:

bit 2) is set.

Enable RIRB DMA Engine — R/W. After software writes a 0 to this bit, the hardware

may not stop immediately. The hardware will physically update the bit to 0 when the

DMA engine is truly stopped. Software must read a 0 from this bit to verify that the

DMA engine is truly stopp ed.

0 = DMA stop

1 = DMA run

Response Interrupt Control — R/W.

0 = Disable Interrupt

1 = Generate an interrupt after N number of responses are sent to the RIRB buffer OR

when an empty Response slot is encountered on all SDI[x] inputs (whichever

occurs first). The N counter is reset when the interrupt is generated.

Intel® ICH8 Family Datasheet 685

Intel® High Definition Audio Controller Registers (D27:F0)

17.2.29 RIRBSTS—RIRB Status Register

(Intel® High Definition Audio Controller—D27:F0)

Memory Address:HDBAR + 5D h Attribute: R/WC

Default Value: 00h Size: 8 bits

17.2.30 RIRBSIZE—RIRB Size Register

(Intel® High Definition Audio Controller—D27:F0)

Memory Address:HDBAR + 5Eh Attribute: RO

Default Value: 42h Size: 8 bits

17.2.31 IC—Immediate Command Register

(Intel® High Definition Audio Controller—D27:F0)

Memory Address:HDBAR + 60h Attribute: R/W

Default Value: 00000000h Size: 32 bits

Bit Description

7:3 Reserved.

Response Overrun Interrupt Status — R/WC. Software sets this bit to 1 when the

RIRB DMA engine is not able t o write the incoming responses to memory before

additional incoming responses overrun the in ternal FIFO . When the o verrun occurs, the

hardware will drop the responses which overrun the buffer. An interrupt may be

generated if the Response Overrun Interrupt Control bit is set. Note that this status bit

is set even if an interrupt is not enabled for this event.

Software clears this bit by writing a 1 to it.

1 Reserved.

Response Interrupt — R/WC. Hardware sets this bit to 1 when an interrupt has been

generat ed af ter N number of Responses are sent to the RIRB buffer O R when an em pty

Response slot is encountered on all SDI[x] inputs (whichever occurs first). Note that

this status bit is set even if an interrupt is not enabled for this event.

Software clears this bit by writing a 1 to it.

Bit Description

7:4 RIRB Size Capabili t y — RO . Hardwired to 0100b indicating that the ICH8 only supports

a RIRB size of 256 RIRB entries (2048B).

3:2 Reserved.

1:0 RIRB Size — RO. Hardwired to 10b which sets the CORB size to 256 entries (2048B).

Bit Description

31:0

Immediate Command Write — R/W. The command to be sent to the codec via the

Immediate Command mechanism is written to this register. The command stored in this

the ICB bit (HDBAR + 68h: bit 0).

Intel® High Definition Audio Controller Registers (D27:F0)

686 Intel® ICH8 Family Datasheet

17.2.32 IR—Immediate Response Register

(Intel® High Definition Audio Controller—D27:F0)

Memory Address:HDBAR + 64h Attribute: RO

Default Value: 00000000h Size: 32 bits

17.2.33 IRS—Immediate Command Status Register

(Intel® High Definition Audio Controller—D27:F0)

Memory Address:HDBAR + 68h Attribute: R/W, R/WC

Default Value: 0000h Size: 16 bits

Bit Description

31:0

Immediate Response Read (IRR) — RO. This register contains the response received

from a codec resulting from a command sent via the Immediate Command mech anis m.

If multiple codecs responded in the same time, there is no assurance as to which

response will be latched. Therefore, broadcast-type commands must not be issued via

the Immediate Command mechanism.

Bit Description

15:2 Reserved.

Immediate Result Valid (IRV) — R/WC. This bit is set to 1 by hardware when a new

response is latched into the Immediate Response register (HDBAR + 64). This is a

status flag indicating that software may read the response from the Immediate

Response register.

Software must clear this bit by writing a 1 to it before issuing a new command so that

the software may determine when a new response has arrived.

Immediate Command Busy (ICB) — R/W . When this bit is read as 0, it indicates that

a new command ma y be iss ued usin g the Immediat e Command me chanism. Wh en this

bit tran sitions from 0-to-1 (via so ftware writing a 1), the c ontroller issues the com mand

currently stored in the Immediate Command register to the codec over the link. When

the corresponding response is latched into the Immediate Response register, the

controller hardware sets the IRV flag and clears the ICB bit back to 0.

NOTE: An Immediate Command must not be issued while the CORB/RIRB mechanism

is operating; otherwise, the responses conflict. This must be enforced by

software.

Intel® ICH8 Family Datasheet 687

Intel® High Definition Audio Controller Registers (D27:F0)

17.2.34 DPLBASE—DMA Position Lower Base Address Register

(Intel® High Definition Audio Controller—D27:F0)

Memory Address:HDBAR + 70h Attribute: R/W, RO

Default Value: 00000000h Size: 32 bits

17.2.35 DPUBASE—DMA Position Upper Base Address Register

(Intel® High Definition Audio Controller—D27:F0)

Memory Address:HDBAR + 74h Attribute: R/W

Default Value: 00000000h Size: 32 bits

Bit Description

31:7

DMA Position Lower Base Address — R/W. This field provides the lower 32 bits of

the DMA Position Buffer Base Address. This register field must not be written when any

DMA engine is running or the DMA transfer may be corrupted. This same address is

used by the Flush Control and must be programmed with a val id v alue before the Flush

Control bit (HDBAR+08h:bit 1) is set.

6:1 DMA Position Lower Base Unimplemented bits — RO. Hardwired to 0 to force the

128-byte buffer alignment for cache line write optimizations.

DMA Position Buffer Enable — R/W.

0 = Disable.

1 = Enable. Controller will write the DMA positions of each of the DMA engines to the

buffer in the main memory periodically (typically, once per frame). Software can

use this value to know what data in memory is valid data.

Bit Description

31:0 DMA Position Upper Base Address — R/W. This field provides the upper 32 bits of

the DMA Position Buffer Base Address. This register field must not be written when any

DMA engine is running or the DMA transfer may be corrupted.

Intel® High Definition Audio Controller Registers (D27:F0)

688 Intel® ICH8 Family Datasheet

17.2.36 SDCTL—Stream Descriptor Control Register

(Intel® High Definition Audio Controller—D27:F0)

Memory Address:Input Stream[0]: HDBAR + 80hAttribute: R/W, RO

Input Stream[1]: HDBAR + A0h

Input Stream[2]: HDBAR + C0h

Input Stream[3]: HDBAR + E0h

Output Stream[0]: HDBAR + 100h

Output Stream[1]: HDBAR + 120h

Output Stream[2]: HDBAR + 140h

Output Stream[3]: HDBAR + 160h

Default Value: 040000h Size: 24 bits

Bit Description

23:20

Stream Number — R/W. This value reflects the Tag associated with the data being

transferred on the link. When data controlled by this descriptor is sent out over the link,

it will have its stream number encoded on the SYNC signal. When an input stream is

detected on any of the SDI signals that match this value, the data s a mples are loaded

into FIFO associated with this descriptor.

NOTE: While a single SDI input may contain data from more than one stream number,

two different SDI inputs may not be configured with the same stream number.

0000 = Reserved

0001 = Stream 1

........

1110 = Stream 14

1111 = Stream 15

19 Bidirectional Direction Control — RO. This bit is only meaningful for bidirectional

streams; therefore, thi s bit is hardwired to 0.

18 Traffic Priority — RO. Hardwired to 1 indicating that all streams will use VC1 if it is

enabled through the PCI Express* registers.

17:16 Stripe Control — RO. This bit is only meaningful for input streams; therefore, this bit is

hardwired to 0.

15:5 Reserved

4Descriptor Error Interrupt Enable — R/W.

0 = Disable

1 = Enable. An interrupt is generated when the Descriptor Error Status bit is set.

FIFO Error Interrupt Enable — R/W. This bit controls whether the occurrence of a

FIFO error (overrun for input or underrun for output) will cause an interrupt. If this bit

is not set, bit 3in the Status register will be set, but the interrupt will not occur. Either

way, the samples will be dropped.

2Interrupt on Completion Enable — R/W. This bit controls whether or not an interrupt

occurs when a buffer completes with the IOC bit set in its descriptor. If this bit is not

set, bit 2 in the Status register will be set, but the interrupt will not occur.

Intel® ICH8 Family Datasheet 689

Intel® High Definition Audio Controller Registers (D27:F0)

Stream Run (RUN) — R/W.

0 = Disable. When cleared to 0, the DMA engine associated with this input stream will

be disabled. The hardware will report a 0 in this bit when the DMA engine is

actually stopped. Software must read a 0 from this bit before modifying related

control registers or restarting the DMA engine.

1 = Enable. When set to 1, the DMA engine associated with this input stream will be

enabled to transfer data from the FIFO to the main memory. The SSYNC bit must

also be cleared in order for the DMA engine to run. For output streams, the

cadence generator is reset whenever the RUN bit is set.

Stream Reset (SRST) — R/W.

0 = Writing a 0 causes the corresponding stream to exit reset. When the stream

hardware is ready to begin operation, it will report a 0 in this bit. Software must

read a 0 from this bit before accessing any of the stream registers.

1 = Writing a 1 causes the corresponding stream to be reset. The Stream Descriptor

registers (except the SRST bit itself) and FIFO’s for the corresponding stream are

reset. After the st ream hardware has com p le ted se qu en ci ng into the reset st ate , i t

will report a 1 in this bit. Software must read a 1 from this bit to verify that the

stream is in reset. The RUN bit must be cleared before SRST is asserted.

Bit Description

Intel® High Definition Audio Controller Registers (D27:F0)

690 Intel® ICH8 Family Datasheet

17.2.37 SDSTS—Stream Descriptor Status Register

(Intel® High Definition Audio Controller—D27:F0)

Memory Address:Input Stream[0]: HDBAR + 83h Attribute:R/WC, RO

Input Stream[1]: HDBAR + A3h

Input Stream[2]: HDBAR + C3h

Input Stream[3]: HDBAR + E3h

Output Stream[0]: HDBAR + 103h

Output Stream[1]: HDBAR + 123h

Output Stream[2]: HDBAR + 143h

Output Stream[3]: HDBAR + 163h

Default Value: 00h Size: 8 bits

Bit Description

7:6 Reserved.

FIFO Ready (FIFORDY) — RO. For output streams, the controller hardware will set this

bit to 1 while the output DMA FIFO contains enough data to maintain the stream on the

link. This bit defaults to 0 on reset because the FIFO is cleared on a reset.

For input streams, the controller hardware will set this bit to 1 when a valid descriptor

is loaded and the engine is ready for the RUN bit to be set.

Descriptor Error — R/WC.

0 = No error

1 = Serious error occurred during the fetch of a descriptor. This could be a result of a

Master Abort, a parity or ECC error on the bus, or any other error that renders the

current Buffer Descriptor or Buffer Descriptor list useless. This error is treated as a

fatal stream error, as the stream cannot continue running. The RUN bit will be

cleared and the stream will stopped.

Software may attempt to restart the stream engine after addressing the cause of the

error and writing a 1 to this bit to clear it.

FIFO Error — R/WC. The bit is cleared by writing a 1 to it.

0 = No error

1 = FIFO error occurred. This bit is set even if an interrupt is not enabled.

For an input stream, this indicates a FIFO overrun occurring while the RUN bit is set.

When this happens, the FIFO pointers do not increment and the incoming data is no t

written into the FIFO, thereby being lo st.

For an output stream, this indicates a FIFO underrun when there are still buffers to

send. The hardware should not tr ansmi t any thing on the link for the associated stream

if there is not valid data to send.

Buffer Completion Interrupt Status — R/WC.

0 = Last sample of buffer Not processed.

1 = Set by the hardware after the last sample of a buffer has been processed, AND if

the Interrupt on Completion bit is set in the command byte of the buffer descriptor.

It remains active until software clears it by writing a 1 to it.

1:0 Reserved.

Intel® ICH8 Family Datasheet 691

Intel® High Definition Audio Controller Registers (D27:F0)

17.2.38 SDLPIB—Stream Descriptor Link Position in Buffer

Memory Address:Input Stream[0]: HDBAR + 84h Attribute: RO

Input Stream[1]: HDBAR + A4h

Input Stream[2]: HDBAR + C4h

Input Stream[3]: HDBAR + E4h

Output Stream[0]: HDBAR + 104h

Output Stream[1]: HDBAR + 124h

Output Stream[2]: HDBAR + 144h

Output Stream[3]: HDBAR + 164h

Default Value: 00000000h S ize: 32 bit s

17.2.39 SDCBL—Stream Descriptor Cyclic Buffer Length Register

(Intel® High Definition Audio Controller—D27:F0)

Memory Address:Input Stream[0]: HDBAR + 88h Attribute: R/W

Input Stream[1]: HDBAR + A8h

Input Stream[2]: HDBAR + C8h

Input Stream[3]: HDBAR + E8h

Output Stream[0]: HDBAR + 108h

Output Stream[1]: HDBAR + 128h

Output Stream[2]: HDBAR + 148h

Output Stream[3]: HDBAR + 168h

Default Value: 00000000h Size: 32 bits

Bit Description

31:0 Link Position in Buffer — RO. This field indicates the number of bytes that have been

received off the link. This register will count from 0 to the value in the Cyclic Buffer

Length register and then wrap to 0.

Bit Description

31:0

Cyclic Buffer Length — R/W. This field indicates the number of bytes in the complete

cyclic buffer. This register represents an integer number of samples. Link Position in

Buffer will be reset when it reaches this value.

Software may only write to this register after Global R eset, Controller R eset, or Stream

Res et has occurred. This value sh ould be only modified when th e RUN bit is 0. Once the

RUN bit has be en set to enable the engine, s oftware must not write to this register u ntil

after the next reset is asserted, or transfer may be corrupted.

Intel® High Definition Audio Controller Registers (D27:F0)

692 Intel® ICH8 Family Datasheet

17.2.40 SDLVI—Stream Descriptor Last Valid Index Register

(Intel® High Definition Audio Controller—D27:F0)

Memory Address:Input Stream[0]: HDBAR + 8Ch Attribute: R/W

Input Stream[1]: HDBAR + ACh

Input Stream[2]: HDBAR + CCh

Input Stream[3]: HDBAR + ECh

Output Stream[0]: HDBAR + 10Ch

Output Stream[1]: HDBAR + 12Ch

Output Stream[2]: HDBAR + 14Ch

Output Stream[3]: HDBAR + 16Ch

Default Value: 0000h Size: 16 bits

17.2.41 SDFIFOW—Stream Descriptor FIFO Watermark Register

(Intel® High Definition Audio Controller—D27:F0)

Memory Address:Input Stream[0]: HDBAR + 8Eh Attri bute: R/W

Input Stream[1]: HDBAR + AEh

Input Stream[2]: HDBAR + CEh

Input Stream[3]: HDBAR + EEh

Output Stream[0]: HDBAR + 10Eh

Output Stream[1]: HDBAR + 12Eh

Output Stream[2]: HDBAR + 14Eh

Output Stream[3]: HDBAR + 16Eh

Default Value: 0004h Size: 16 bits

Bit Description

15:8 Reserved.

7:0

Last Valid Index — R/W. The value written to this register indicates the index for the

last valid Buffer Descriptor in BDL. After the controller has processed this descriptor, it

will wrap back to the first descriptor in the list and co ntinue processing.

This field must be at least 1 (i.e., there must be at least 2 valid entries in the buffer

descriptor list before DMA operations can begin).

This value should only modified when the RUN bit is 0.

Bit Description

15:3 Reserved.

2:0

FIFO Watermark (FIFOW) — R/W. This field indicates the minimum n umber of bytes

accumulated/free in the FIFO before the controller will start a fetch/eviction of data.

010 = 8B

011 = 16B

100 = 32B (Default)

Others = Unsupported

NOTES:

1. When the bit field is programmed to an unsupported size, the hardware sets

itself to the default value.

2. Software mu st read the bit field to test if the v alue is suppo rted after setting the

bit field.

Intel® ICH8 Family Datasheet 693

Intel® High Definition Audio Controller Registers (D27:F0)

17.2.42 SDFIFOS—Stream Descriptor FIFO Size Register

(Intel® High Definition Audio Controller—D27:F0)

Memory Address:Input Stream[0]: HDBAR + 90h Attribute: Input: RO

Input Stream[1]: HDBAR + B0h Output: R/W

Input Stream[2]: HDBAR + D0h

Input Stream[3]: HDBAR + F0h

Output Stream[0]: HDBAR + 110h

Output Stream[1]: HDBAR + 130h

Output Stream[2]: HDBAR + 150h

Output Stream[3]: HDBAR + 170h

Default Value: Input Stream: 0077h Size: 16 bits

Output Stream: 00BFh

Bit Description

15:8 Reserved.

7:0

FIFO Size — RO (Input stream), R/W (Output stream). This field indicates the

maximum number of bytes that could be fetched by the controller at one time. This is

the maximum number of bytes that may have been DMA’d into memory but not yet

transmitted on the link, and is also the maximum possible value that the PICB count

will increase by at one time.

The value in this field is different for input and output streams. It is also dependent on

the Bits per Samples setting for the corresponding stream. Following are the values

read/written from/to this register for input and output streams, and for non-padded

and padded bit formats:

Output Stream R/W value

NOTES:

1. All other values not listed are not supported.

2. When the output stream is programmed to an unsupported size, the hardware

sets itself to the default value (BFh).

3. Software must read the bit field to test if the value is supported after setti ng the

bit field.

Input Stream RO value

NOTE: The default value is different for input and output streams, and reflects the

default state of the BITS fields (in Stream Descriptor Format registers) for the

corresponding stream.

Value Output Streams

0Fh = 16B 8, 16, 20, 24, or 32 bit Output Streams

1Fh = 32B 8, 16, 20, 24, or 32 bit Output Streams

3Fh = 64B 8, 16, 20, 24, or 32 bit Output Streams

7Fh = 128B 8, 16, 20, 24, or 32 bit Output Streams

BFh = 192B 8, 16, or 32 bit Output Streams

FFh = 256B 20, 24 bit Output Streams

Value Input Streams

77h = 120B 8, 16, 32 bit Input Streams

9Fh = 160B 20, 24 bit Input Streams

Intel® High Definition Audio Controller Registers (D27:F0)

694 Intel® ICH8 Family Datasheet

17.2.43 SDFMT—Stream Descriptor Format Regist er

(Intel® High Definition Audio Controller—D27:F0)

Memory Address:Input Stream[0]: HDBAR + 92h Attribute: R/W

Input Stream[1]: HDBAR + B2h

Input Stream[2]: HDBAR + D2h

Input Stream[3]: HDBAR + F2h

Output Stream[0]: HDBAR + 112h

Output Stream[1]: HDBAR + 132h

Output Stream[2]: HDBAR + 152h

Output Stream[3]: HDBAR + 172h

Default Value: 0000h Size: 16 bits

Bit Description

15 Reserved.

14 Sample Base Rate — R/W

0 = 48 kHz

1 = 44.1 kHz

13:11

Sample Base Rate Multiple — R/W

000 = 48 kHz, 44.1 kHz or less

001 = x2 (96 kHz, 88.2 kHz, 32 kHz)

010 = x3 (144 kHz)

011 = x4 (192 kHz, 176.4 kHz)

Others = Reserved.

10:8

Sample Base Rate Devisor — R/W.

000 = Divide by 1(48 kHz, 44.1 kHz)

001 = Divide by 2 (24 kHz, 22.05 kHz)

010 = Divide by 3 (16 kHz, 32 kHz)

011 = Divide by 4 (11.025 kHz)

100 = Divide by 5 (9.6 kHz)

101 = Divide by 6 (8 kHz)

110 = Divide by 7

111 = Divide by 8 (6 kHz)

7 Reserved.

6:4

Bits per Sample (BITS) — R/W.

000 = 8 bits. The data will be packed in memory in 8-bit containers on 16-bit

boundaries

001 = 16 bits. The data will be packed in memory in 16-bit containers on 16-bit

boundaries

010 = 20 bits. The data will be packed in memory in 32-bit containers on 32-bit

boundaries

011 = 24 bits. The data will be packed in memory in 32-bit containers on 32-bit

boundaries

100 = 32 bits. The data will be packed in memory in 32-bit containers on 32-bit

boundaries

Others = Reserved.

3:0

Number of Channels (CHAN) — R/W . Indicates number of channels in each frame of the

stream.

0000 =1

0001 =2

........

1111 =16

Intel® ICH8 Family Datasheet 695

Intel® High Definition Audio Controller Registers (D27:F0)

17.2.44 SDBDPL—Stream Descriptor Buffer Descriptor List Pointer

Lower Base Address Register

(Intel® High Definition Audio Controller—D27:F0)

Memory Address:Input Stream[0]: HDBAR + 98h Attribute: R/W,RO

Input Stream[1]: HDBAR + B8h

Input Stream[2]: HDBAR + D8h

Input Stream[3]: HDBAR + F8h

Output Stream[0]: HDBAR + 118h

Output Stream[1]: HDBAR + 138h

Output Stream[2]: HDBAR + 158h

Output Stream[3]: HDBAR + 178h

Default Value: 00000000h Size: 32 bits

17.2.45 SDBDPU—Stream Descriptor Buffer Descriptor List Pointer

Upper Base Address Register (Intel® High Definition Audio

Controller—D27:F0)

Memory Address:Input Stream[0]: HDBAR + 9Ch Attribute: R/W

Input Stream[1]: HDBAR + BCh

Input Stream[2]: HDBAR + DCh

Input Stream[3]: HDBAR + FCh

Output Stream[0]: HDBAR + 11Ch

Output Stream[1]: HDBAR + 13Ch

Output Stream[2]: HDBAR + 15Ch

Output Stream[3]: HDBAR + 17Ch

Default Value: 00000000h Size: 32 bits

§ §

Bit Description

31:7 Buffer Descriptor List Pointer Lower Base Address — R/W. This field provides the

lower address of the Buffer Descriptor List. This value should only be modifi ed when the

RUN bit is 0, or DMA transfer may be corrupted.

6:0 Hardwired to 0 forcing alignment on 128-B boundaries.

Bit Description

31:0 Buffer Descriptor List Pointer Upper Base Address — R/W. This field provides the

upper 32-bit address of the Buffer Descriptor List. This value should only be modified

when the RUN bit is 0, or DMA transfer may be corrupted.

Intel® High Definition Audio Controller Registers (D27:F0)

696 Intel® ICH8 Family Datasheet

Intel® ICH8 Family Datasheet 697

PCI Express* Configuration Registers

18 PCI Express* Configuration

Registers

18.1 PCI Express* Configuration Registers

(PCI Express—D28:F0/F1/F2/F3/F4/F5)

Note: Register address locations that are not shown in Table 141 and should be treated as

Reserved.

Table 141. PCI Express* Configuration Registers Address Map

(PCI Express—D28:F0/F1/F2/F3/F4/F5) (Sheet 1 of 3)

Offset Mnemonic Register Name Function 0–5

Default Type

00h–01h VID Vendor Identification 8086h RO

02h–03h DID Device Identification See register

description RO

04h–05h PCICMD PCI Command 0000h R/W, RO

06h–07h PCISTS PCI Status 0010h R/WC, RO

08h RID Revision Identification See register

description RO

09h PI Programming Interface 00h RO

0Ah SCC Sub Class Code 04h RO

0Bh BCC Base Class Code 06h RO

0Ch CLS Cache Line Size 00h R/W

0Dh PLT Primary Latency Timer 00h RO

0Eh HEADTYP Header Type 81h RO

18h–1Ah BNUM Bus Number 000000h R/W

1Bh SLT Secondary Latency Timer 0h RO

1Ch–1Dh IOBL I/O Base and Limit 0000h R/W, RO

1Eh–1Fh SSTS Secondary Status 0000h R/WC

20h–23h MBL Memory Base and Limit 00000000h R/W

24h–27h PMBL Prefetchable Memory Base and

Limit 00010001h R/W, RO

28h–2Bh PMBU32 Prefetchable Memory Base Upper

32 Bits 00000000h R/W

2Ch–2Fh PMLU32 Prefetchable Memory Limit Upper

32 Bits 00000000h R/W

34h CAPP Capabilities List Pointer 40h RO

3Ch–3Dh INTR Interrupt Information See bit

description R/W, RO

3Eh–3Fh BCTRL Bridge Control Register 0000h R/W

40h–41h CLIST Capabilities List 8010 RO

PCI Express* Configuration Registers

698 Intel® ICH8 Family Datasheet

42h–43h XCAP PCI Express* Capabilities 0041 R/WO, RO

44h–47h DCAP Device Capabilities 00000FE0h RO

48h–49h D CTL Device Control 0000h R/W, RO

4Ah–4Bh DSTS Device Status 0010h R/WC, RO

4Ch–4Fh LCAP Link Capabilities See bit

description R/W, RO,

R/WO

50h–51h LCTL Link Control 0000h R/W, WO,

52h–53h LSTS Link Status See bit

description RO

54h–57h SLCAP Slot Capabilities Register 00000060h R/WO, RO

58h–59h SLCTL Slot Control 0000h R/W, RO

5Ah–5Bh SLSTS Slot Status 0000h R/WC, RO

5Ch–5Dh RCTL Root Control 0000h R/W

60h–63h RSTS Root Status 00000000h R/WC, RO

80h–81h MID Message Signaled Interrupt

Identifiers 9005h RO

82h–83h MC Message Signaled Interrupt

Message Control 0000h R/W, RO

84h–87h MA Message Signaled Interrupt

Message Address 00000000h R/W

88h–89h MD Message Signaled Interrupt

Message Data 0000h R/W

90h–91h SVCAP Subsystem Vendor Capability A00Dh RO

94h–97h SVID Subsystem Vendor Identification 00000000h R/WO

A0h–A1h PMCAP Power Management Capability 0001h RO

A2h–A3h PMC PCI Power Management Capability C802h RO

A4–A7h PMCS PCI Power Management Control

and Status 00000000h R/W, RO

D8–DBh MPC Miscellaneous Port Configuration 00110000h R/W

DC–DFh SMSCS SMI/SCI Status Register 00000000h R/WC

E1h RPDCGEN Root Port Dynamic Clock Gating

Enable (Mobile Only) 00h R/W

E2–E3h IPWS Intel® PRO/Wireless 3945ABG

Status 0000h RO

100–103h VCH Virtual Channel Capability Header 18010002h RO

104h–107h — Reserved — —

108h–10Bh VCAP2 Virtual Channel Capability 2 00000001h RO

10Ch–10Dh PVC Port Virtual Channel Control 0000h R/W

10Eh–10Fh PVS Port Virtual Channel Status 0000h RO

Table 141. PCI Express* Configuration Registers Address Map

(PCI Express—D28:F0/F1/F2/F3/F4/F5) (Sheet 2 of 3)

Offset Mnemonic Register Name Function 0–5

Default Type

Intel® ICH8 Family Datasheet 699

PCI Express* Configuration Registers

110h–113h V0CAP Virtual Channel 0 Resource

Capability 00000001h RO

114–117h V0CTL Virtual Channel 0 Resource Control 800000FFh R/W, RO

11A–11Bh V0STS Virtual Channel 0 Resource Status 0000h RO

11Ch–143h — Reserved — —

144h–147h UES U ncorrectable Error Status See bit

description R/WC, RO

148h–14Bh UEM Uncorrectable Error Mask 00000000h R/WO, RO

14Ch–14Fh UEV Uncorrectable Error Severity 00060011h RO

150h–153h CES Correctable Error Status 00000000h R/WC

154h–157h CEM Correctable Error Mask 00000000h R/WO

158h–15Bh AECC Advanced Error Capabilities and

Control 00000000h RO

170h–173h RES Root Error Status 00000000h R/WC, RO

180h–183h RCTCL Root Complex Topology Capability

List 00010005h RO

184h–187h ESD Element Self Description See bit

description RO

190h–193h ULD Upstream Link Description 00000001h RO

198h–19Fh ULBA Upstream Link Base Address See bit

description RO

318h PEETM PCI Express Extended Test Mode

Table 141. PCI Express* Configuration Registers Address Map

(PCI Express—D28:F0/F1/F2/F3/F4/F5) (Sheet 3 of 3)

Offset Mnemonic Register Name Function 0–5

Default Type

PCI Express* Configuration Registers

700 Intel® ICH8 Family Datasheet

18.1.1 VID—Vendor Identification Register

(PCI Express—D28:F0/F1/F2/F3/F4/F5)

Address Offset: 00h–01h Attribute: RO

Default Value: 8086h Size: 16 bits

18.1.2 DID—Device Identification Register

(PCI Express—D28:F0/F1/F2/F3/F4/F5)

Address Offset: 02h–03h Attribute: RO

Default Value: Port 1= Bit Description Size: 16 bits

Port 2= Bit Description

Port 3= Bit Description

Port 4= Bit Description

Port 5= Bit Description

Port 6= Bit Description

Bit Description

15:0 Vendor ID — RO. This is a 16-bit value assigned to Intel.

Bit Description

15:0 Device ID — RO. This is a 16-bit value assigne d to the Intel® ICH8 PCI Express

controller. Refer to the Intel® ICH8 Family Specification Update for the value of the

Revision ID Register.

Intel® ICH8 Family Datasheet 701

PCI Express* Configuration Registers

18.1.3 PCICMD—PCI Command Register

(PCI Express—D28:F0/F1/F2/F3/F4/F5)

Address Offset: 04h–05h Attribute: R/W, RO

Default Value: 0000h Size: 16 bits

Bit Description

15:11 Reserved

Interrupt Disable — R/W. This bit disables pin-based INTx# interrupts on enabled Hot-

Plug and power management events. This bit has no effect on MSI operation.

0 = Internal INTx# messages are generated if there is an interrupt for Hot-Plug or

power management and MSI is not enabled.

1 = Internal INTx# messages will not be generated.

This bit does not affect interrupt forwarding from devices connected to the root port.

Assert_INTx and Deassert_INTx messages will still be forwarded to the internal

interrupt c ontrollers if this bit is set.

9 Fast Back to Back Enable (FBE) — Reserved per the PCI Express* Base Specification .

8SERR# Enable (SEE) — R/W.

0 = Disable.

1 = Enables the root port to generate an SERR# message when PSTS.SSE is set.

7 Wait Cycle Control (WCC) — Reserved per the PCI Express Base Specification.

6Parity Error Response (PER) — R/W.

0 = Disable.

1 = Device is capable of reporting parity errors as a master on the backbone.

5 VGA Palette Snoop (VPS) — Reserved per the PCI Express* Base Specification.

4Postable Memory Write Enable (PMWE) — Reserved per the PCI Express* Base

Specification.

3 Special Cycle Enable (SCE) — Reserved per the PCI Express* Base Specification.

Bus Master Enable (BME) — R/W.

0 = Disable. All cycles from the device are maste r aborted

1 = Enable. Allows the root port to forward cycles onto the backbone from a PCI

Express* device.

Memory Space Enable (MSE) — R/W.

0 = Disable. Memory cycles wi thin the range specified by the memory base and limit

registers are master aborte d on the backbone.

1 = Enable. Allows memory cycles within the range specified by the memory base and

limit registers can be forwarded to the PCI Express device.

I/O Space Enable (IOSE) — R/W. This bit controls acc ess to the I/O space regi ster s.

0 = Disable. I/O cycles within the range specified by the I/O base and limit registers

are master aborted on the backbone.

1 = Enable. Allows I/O cycles within the range specified by the I/O base and limit

registers can be forwarded to the PCI Express dev ice.

PCI Express* Configuration Registers

702 Intel® ICH8 Family Datasheet

18.1.4 PCISTS—PCI Status Register

(PCI Express—D28:F0/F1/F2/F3/F4/F5)

Address Offset: 06h–07h Attribute: R/WC, RO

Default Value: 0010h Size: 16 bits

Bit Description

Detected Parity Error (DPE) — R/WC.

0 = No parity error detected.

1 = Set when the root port receives a command or data from the backbone with a

parity error. This is set even if PCIMD.PER (D28:F0/F1/F2/F3:04, bit 6) is not set.

14 Signaled System Error (SSE) — R/WC.

0 = No system error signaled.

1 = Set when the root port signals a system error to the internal SERR# logic.

Received Master Abort (RMA) — R/WC.

0 = Root port has not received a completion with unsupported request status from the

backbone.

1 = Set when the root port receives a completion with unsupported request status from

the backbone.

Received Target Abort (RTA) — R/WC.

0 = Root port has not received a completion with completer abort from the backbone.

1 = Set when the root port receives a completion with completer abort from the

backbone.

Signaled Target Abort (STA) — R/WC .

0 = No target abort received.

1 = Set whenever the root port forwards a target abort received from the downstream

device onto the backbone.

10:9 DEVSEL# Timing Status (DEV_STS) — Reserved per the PCI Express* Base

Specification.

Master Data Parity Error Detected (DPED) — R/WC.

0 = No data parity error received.

1 = Set when the root port receives a completion with a data parity error on the

backbone and PCIMD.PER (D28:F0/F1/F2/F3:04, bit 6) is set.

7Fast Back to Back Capable (FB2BC) — Reserved per the PCI Express* Base

Specification.

6Reserved

5 66 MHz Capable — Reserved per the PCI Express* Base Specification.

4 Capabilities List — RO. Hardwired to 1. Indicates the presence of a capabilities list.

Interrupt Status — RO. Indicates status of Hot-Plug and power management

interrupts on the root port that result in INTx# message generation.

0 = Interrupt is deasserted.

1 = Interrupt is asserted.

This bit is not set if MSI is enabled. If MSI is not enabled, this bit is set regardless of the

state of PCICMD.Interrupt Disable bit (D28:F0/F1/F2/F3/F4/F5:04h:bit 10).

2:0 Reserved

Intel® ICH8 Family Datasheet 703

PCI Express* Configuration Registers

18.1.5 RID—Revision Identification Register

(PCI Express—D28:F0/F1/F2/F3/F4/F5)

Offset Address: 08h Attribute: RO

Default Value: See bit description Size: 8 bits

18.1.6 PI—Programming Interface Register

(PCI Express—D28:F0/F1/F2/F3/F4/F5)

Address Offset: 09h Attribute: RO

Default Value: 00h Size: 8 bits

18.1.7 SCC—Sub Class Code Register

(PCI Express—D28:F0/F1/F2/F3/F4/F5)

Address Offset: 0Ah Attribute: RO

Default Value: 04h Size: 8 bits

18.1.8 BCC—Base Class Code Register

(PCI Express—D28:F0/F1/F2/F3/F4/F5)

Address Offset: 0Bh Attribute: RO

Default Value: 06h Size: 8 bits

Bit Description

7:0 R evision ID — RO. R efer to the Intel® ICH8 Family Specificat ion Update for the value of

the Revision ID Register.

Bit Description

7:0 Programming Interface — RO.

00h = No specific register level programming interface define d.

Bit Description

7:0

Sub Class Code (SCC) — RO. This field is determined by bit 2 of the MPC register

(D28:F0-5, Offset D8h, bit 2).

04h = PCI-to-PCI bridge.

00h = Host Bridge.

Bit Description

7:0 Base Class Code (BCC) — RO.

06h = Bridge device.

PCI Express* Configuration Registers

704 Intel® ICH8 Family Datasheet

18.1.9 CLS—Cache Line Size Register

(PCI Express—D28:F0/F1/F2/F3/F4/F5)

Address Offset: 0Ch Attribute: R/W

Default Value: 00h Size: 8 bits

18.1.10 PLT—Primary Latency Timer Register

(PCI Express—D28:F0/F1/F2/F3/F4/F5)

Address Offset: 0Dh Attribute: RO

Default Value: 00h Size: 8 bits

18.1.11 HEADTYP—Header Type Register

(PCI Express—D28:F0/F1/F2/F3/F4/F5)

Address Offset: 0Eh Attribute: RO

Default Value: 81h Size: 8 bits

18.1.12 BNUM—Bus Number Register

(PCI Express—D28:F0/F1/F2/F3/F4/F5)

Address Offset: 18–1Ah Attribute: R/W

Default Value: 000000h Size: 24 bits

Bit Description

7:0 Cache Line Size (CLS) — R/W. This is read/write but contains no functionality, per the

PCI Express* Base Specification.

Bit Description

7:3 Latency Count. Reserved per the PCI Express* Base Specification.

2:0 Reserved

Bit Description

7Multi-Fu nction Devic e — RO.

0 = Single-function device.

1 = Multi-function device.

6:0

Configuration Layout— RO. This field is determined by bit 2 of the MPC register

(D28:F0-5, Offset D8h, bit 2).

00h = Host Bridge.

01h = PCI-to-PCI bridge.

Bit Description

23:16 Subordinate Bus Number (SBBN) — R/W. Indicates the highest PCI bus number below

the bridge.

15:8 Secondary Bus Num b er (SCBN) — R/W. Indicates the bus number the port.

7:0 Primary Bus Number (PBN) — R/W. Indicates the bus number of the backbone.

Intel® ICH8 Family Datasheet 705

PCI Express* Configuration Registers

18.1.13 SLT—Secondary Latency Timer

(PCI Express—D28:F0/F1/F2/F3/F4/F5)

Address Offset: 1Bh Attribute: RO

Default Value: 0h Size: 8 bits

18.1.14 IOBL—I/O Base and Limit Register

(PCI Express—D28:F0/F1/F2/F3/F4/F5)

Address Offset: 1Ch–1Dh Attribute: R/W, RO

Default Value: 0000h Size: 16 bits

Bit Description

7:0 Secondary Latency Timer — Reserved for a Root Port per the PCI Express* Base

Specification.

Bit Description

15:12 I/O Limit Address (IOLA) — R/W. This field provides I/O Base bits corresponding to

address lines 15:12 for 4-KB alignment. Bits 11:0 are assumed to be padded to FFFh.

11:8 I/O Limit Address Capability (IOLC) — RO. Indicates that the bridge does not support

32-bit I/O addressing.

7:4 I/O Base Address (IOBA) — R/W. I/O Base bits corresponding to address lines 15:12

for 4-KB alignment. Bits 11:0 are assumed to be padded to 000h.

3:0 I/O Base Address Capability (IOBC) — R/O . Indicates that the bridge does not support

32-bit I/O addressing.

PCI Express* Configuration Registers

706 Intel® ICH8 Family Datasheet

18.1.15 SSTS—Secondary Status Register

(PCI Express—D28:F0/F1/F2/F3/F4/F5)

Address Offset: 1Eh–1Fh Attribute: R/WC

Default Value: 0000h Size: 16 bits

Bit Description

15 Detected Parity Error (DPE) — R/WC.

0 = No error.

1 = The port received a poisoned TLP.

14 Received System Error (RSE) — R/WC.

0 = No error.

1 = The port received an ERR_FATAL or ERR_NONFATAL message from the device.

13 Received Master Abort (RMA) — R/WC.

0 = Unsupported Request not received.

1 = The port received a completion with “Unsupported Request” status from the device.

12 Received Target Abort (RTA) — R/WC.

0 = Completion Abort not rece ived.

1 = The port received a completion with “Completion Abort” status from the device.

11 Signaled Target Abort (STA) — R/WC.

0 = Completion Abort not sent.

1 = The port generated a completion with “Completion Abort” status to the device.

10:9 Secondary DEVSEL# Timing Status (SDTS): Reserved per PCI Express* Base

Specification.

Data Parity Error Detected (DPD) — R/WC.

0 = Conditions below did not occur.

1 = Set when the BCTRL.PERE (D2 8:F O/F 1/F 2/ F3/F4/F5:3E: bit 0) i s set , and either of

the following two conditions occurs:

• Port receives completion marked poisoned.

• Port poisons a write request to the secondary side.

7Secondary Fast Back to Back Capable (SFBC): Reserved per PCI Express* Base

Specification.

6Reserved

5 Secondary 66 MHz Capable (SC66): Reserved per PCI Express* Base Specification.

4:0 Reserved

Intel® ICH8 Family Datasheet 707

PCI Express* Configuration Registers

18.1.16 MBL—Memory Base and Limit Register

(PCI Express—D28:F0/F1/F2/F3/F4/F5)

Address Offset: 20h–23h Attribute: R/W

Default Value: 00000000h Size: 32 bits

Accesses that are within the ranges specified in this register will be sent to the attached

device if CMD.MSE (D28:F0/F1/F2/F3/F4/F5:04:bit 1) is set. Accesses from the

attached device that are outside the ranges specified will be forwarded to the backbone

if CMD.BME (D28:F0/F1/F2/F3/F4/F5:04:bit 2) is set. The comparison performed is

MB ≥ AD[31:20] ≤ ML.

18.1.17 PMBL—Prefetchable Memory Base and Limit Register

(PCI Express—D28:F0/F1/F2/F3/F4/F5)

Address Offset: 24h–27h Attribute: R/W, RO

Default Value: 00010001h Size: 32 bits

Accesses that are within the ranges specified in this register will be sent to the device if

CMD.MSE (D28:F0/F1/F2/F3/F4/F5;04, bit 1) is set. Accesses from the device that are

outside the ranges specified will be forwarded to the backbone if CMD .BME (D28:F0/F1/

F2/F3/F4/F5;04, bit 2) is set. The comparison performed is PMBU32:PMB ≥

AD[63:32]:AD[31:20] ≤ PMLU32:PML.

Bit Description

31:20 Memory Limit (ML) — R/W. These bits are compared with bits 31:20 of the incoming

address to determine the upper 1-MB aligned value of the range.

19:16 Reserved

15:4 Memory Base (MB) — R/W. These bits are compared with bits 31:20 of the incoming

address to determine the lower 1-MB aligned value of the range.

3:0 Reserved

Bit Description

31:20 Prefetchable Memory Limit (PML) — R/W. These bits are compared wit h bits 31:2 0

of the incoming address to determine the upper 1-MB aligned value of the range.

19:16 64-bit Indicator (I64L) — RO. Indicates support for 64-bit addressing

15:4 Prefet chab le Memory Base (PMB) — R/W. These bits are compared with bits 31:20

of the incoming address to determine the lower 1-MB aligned value of the range.

3:0 64-bit Indicator (I64B) — RO. Indicates support for 64-bit addressing

PCI Express* Configuration Registers

708 Intel® ICH8 Family Datasheet

18.1.18 PMBU32—Prefetchable Memory Base Upper 32 Bits

Address Offset: 28h–2Bh Attribute: R/W

Default Value: 00000000h Size: 32 bits

18.1.19 PMLU32—Prefetchable Memory Limit Upper 32 Bits

Address Offset: 2Ch–2Fh Attribute: R/W

Default Value: 00000000h Size: 32 bits

18.1.20 CAPP—Capabilities List Pointer Register

(PCI Express—D28:F0/F1/F2/F3/F4/F5)

Address Offset: 34h Attribute: R0

Default Value: 40h Size: 8 bits

Bit Description

31:0 Prefetchable Memory Base Upper Portion (PMBU) — R/W. This field provides the

upper 32-bits of the prefetchable address base.

Bit Description

31:0 Prefetchable Memory Limit Upper Portion (PMLU) — R/W. This field provides the

upper 32-bits of the prefetchable address limit.

Bit Description

7:0 Capabilities Pointer (PTR) — RO. This field indicates that the pointer for the first

entry in the capabilities list is at 40h in configuration space.

Intel® ICH8 Family Datasheet 709

PCI Express* Configuration Registers

18.1.21 INTR—Interrupt Information Register

(PCI Express—D28:F0/F1/F2/F3/F4/F5)

Address Offset: 3Ch–3Dh Attribute: R/W, RO

Default Value: See bit description Size: 16 bits

18.1.22 BCTRL—Bridge Control Register

(PCI Express—D28:F0/F1/F2/F3/F4/F5)

Address Offset: 3Eh–3Fh Attribute: R/W

Default Value: 0000h Size: 16 bits

Bit Description

15:8

Interrupt Pin (IPIN) — RO. This field indicates the interrupt pin driven by the root

port. At reset, this register takes on the following values, which reflect the reset state

of the D28IP register in chipset configuration space:

NOTE: The value that is programmed into D28IP is always reflected in this register.

7:0 Interrupt Line (ILINE) — R/W. Default = 00h. Software written value to indicate

which interrupt line (vector) the interrupt is connected to. No hardware action is taken

on this register.

Port Reset Value

1D28IP.P1IP

2D28IP.P2IP

3D28IP.P3IP

4D28IP.P4IP

5D28IP.P5IP

6D28IP.P6IP

Bit Description

15:12 Reserved

11 Discard Timer SERR# Enable (DTSE): Reserved per PCI Express* Base Specification,

Revision 1.0a

10 Discard Timer Status (DTS): Reserved per PCI Express* Base Specification, Revision

1.0a.

9Secondary Discard Timer (SDT): Reserved per PCI Express* Base Specification,

Revision 1.0a.

8Primary Discard Timer (PDT): Reserved per PCI Express* Base Specificati on, Revision

1.0a.

7Fast Back to Back Enable (FBE): Reserved per PCI Express* Base Specification,

Revision 1.0a.

6Secondary Bus Reset (SBR) — R/W. Triggers a hot reset on the PCI Express* port.

5 Master Abort Mode (MAM): Reserved per Express specification.

VGA 16-Bit Deco de (V16) — R/W.

0 = VGA range is enabled.

1 = The I/O aliases of the VGA range (see BCTRL:VE definition below), are not enabled,

and only the base I/O ranges can be decoded

PCI Express* Configuration Registers

710 Intel® ICH8 Family Datasheet

18.1.23 CLIST—Capabilities List Register

(PCI Express—D28:F0/F1/F2/F3/F4/F5)

Address Offset: 40–41h Attribute: RO

Default Value: 8010h Size: 16 bits

18.1.24 XCAP—PCI Express* Capabilities Register

(PCI Express—D28:F0/F1/F2/F3/F4/F5)

Address Offset: 42h–43h Attribute: R/WO, RO

Default Value: 0041h Size: 16 bits

VGA Enable (VE)— R/W.

0 = Disable. The ranges below will not be claimed off the backbone by the root port.

1 = Enable. The following ranges will be claimed off the backbone by the root port:

• Memory ranges A0000h–BFFFFh

• I/O ranges 3B0h – 3BBh and 3C0h – 3DFh, and all aliases of bits 15:10 in any combination of 1s

ISA Enable (IE) — R/W. This bit only applies to I/O addresses that are enabled by the

I/O Base and I/O Limit registers and are in the first 64 KB of PCI I/O space.

0 = Disable. The root port will not block any forw arding from the backbone as described

below.

1 = Enable. The root port will block any forwarding from the backbone to the device of

I/O transactions addressing the last 768 bytes in each 1-KB block (offsets 100h to

3FFh).

SERR# Enable (SE) — R/W.

0 = Disable. The messages described below are not forwarded to the backbone.

1 = Enable. ERR_COR, ERR_NONFATAL, and ERR_FATAL messages received are

forwarded to the backbone.

Parity Error Response Enable (PERE) — R/W. When set,

0 = Disable. Poisoned write TLPs and completions indicating poisoned TLPs will not set

the SSTS.DPD (D28:F0/F1/F2/F3/F4/F5:1E, bit 8).

1 = Enable. Poisoned write TLPs and completions indicating poisoned TLPs will set the

SSTS.DPD (D28:F0/F1/F2/F3/F4/F5:1E, bit 8).

Bit Description

15:8 Next Capability (NEXT) — RO. Value of 80h indicates the loca tion of the next point er.

7:0 Capability ID (CID) — RO. Indicates this is a PCI Express* capability.

Bit Description

15:14 Reserved

13:9 Interrupt Message Number (IMN) — RO. The Intel® ICH8 does not have multiple

MSI interrupt numbers.

8Slot Implemented (SI) — R/WO. This bit indicates whether the root port is connected

to a slot. Slot support is platform specific. BIOS programs this field, and it is maintained

until a platform reset.

7:4 Device / Port Type (DT) — RO. Indicates this is a PCI Express* root port.

3:0 Capability Version (CV) — RO. Indicates PCI Express 1.0.

Intel® ICH8 Family Datasheet 711

PCI Express* Configuration Registers

18.1.25 DCAP—Device Capabilities Register

(PCI Express—D28:F0/F1/F2/F3/F4/F5)

Address Offset: 44h–47h Attribute: RO

Default Value: 00000FC0h S i ze: 32 bits

Bit Description

31:28 Reserved

27:26 Captured Slot Power Limit Scale (CSPS) — RO. Not supported.

25:18 Captured Slot Power Limit Value (CSPV) — RO. Not supported.

17:16 Reserved

15 Role Based Error Reporting (RBER ) — RO. This bit indicates that this device

implements t he func tionality defined in the Error Reporting ECN as required by the PCI

Express 1.1 spec.

14 Power Indicator Present (PIP) — RO. This bit indicates no power indicator is

present on the root port.

13 Attention Indicator Present (AIP) — RO. This bit indicates no attention indicator is

present on the root port.

12 Attention Button Present (ABP) — RO. This bit indicates no attentio n button is

present on the root port.

11:9 Endpoint L1 Acceptable Latency (E1AL) — RO. This bit indicates more than 4 µs.

This field essentially has no meaning for root ports since root ports are not endpoints.

8:6 Endpoint L0 Acceptable Latency (E0AL) — RO. This bit indicates more than 64 µs.

This field essentially has no meaning for root ports since root ports are not endpoints.

5Extended Tag Field Supported (ETFS) — RO. This bit indicates that 8-bit tag fields

are supported.

4:3 Phantom Functions Supported (PFS) — RO. No phantom functions supported.

2:0 Max Payload Size Supported (MPS) — RO. This field indicates the maximum

payload size supported is 128B.

PCI Express* Configuration Registers

712 Intel® ICH8 Family Datasheet

18.1.26 DCTL—Device Control Register

(PCI Express—D28:F0/F1/F2/F3/F4/F5)

Address Offset: 48h–49h Attribute: R/W, RO

Default Value: 0000h Size: 16 bits

Bit Description

15 Reserved

14:12 Max Read Request Size (MRRS) — RO. Hardwired to 0.

11 Enable No Snoop (ENS) — RO. Not supported. The root port will never issue non-

snoop requests.

10 Aux Power PM Enable (APME) — R/W. The OS will set this bit to 1 if the device

connected has detected aux power. It has no effect on the root port otherwise.

9Phantom Functions Enable (PFE) — RO. Not supported.

8Extended Tag Field Enable (ETFE) — RO. Not supported.

7:5 Max Payload Size (MPS) — R/W. The root port only supports 128-B payloads,

regardless of the programming of this field.

4Enable Relaxed Ordering (ERO) — RO. Not supported.

Unsupported Request Reporting Enable (URE) — R/W.

0 = Disable. The root port will ignore unsupported request errors.

1 = Enable. Allows signaling ERR_NONFATAL, ERR_FATAL, or ERR_COR to the Root

Control register when detecting an unmasked Unsupported Request (UR). An

ERR_COR is signaled when a u nmasked Advisory Non-Fatal UR is received. An

ERR_FATAL, ERR_or NONFATAL, is sent to the Root Control Register when an

uncorrectable non-Advisory UR is received with the severity set by the

Uncorrectable Error Severity register.

Fatal Error Reporting Enable (FEE) — R/W.

0 = Disable. The root port will ignore fatal errors.

1 = Enables signaling of ERR_FATAL to the Root Control register due to internally

detected errors or error messages received across the link. Other bits also control

the full scope of related error reporting.

Non-Fatal Error Reporting Enable (NFE ) — R/W.

0 = Disable. The root port will ignore non-fatal errors.

1 = Enables signaling of ERR_NONFATAL to the Root Control register due to internally

detected errors or error messages received across the link. Other bits also control

the full scope of related error reporting.

Correctable Error Reporting Enable (CEE) — R/W.

0 = Disable. The root port will ignore correctable errors.

1 = Enables signaling of ERR_CORR to the Root Control register due to internally

detected errors or error messages received across the link. Other bits also control

the full scope of related error reporting.

Intel® ICH8 Family Datasheet 713

PCI Express* Configuration Registers

18.1.27 DSTS—Device Status Register

(PCI Express—D28:F0/F1/F2/F3/F4/F5)

Address Offset: 4Ah–4Bh Attribute: R/WC, RO

Default Value: 0010h Size: 16 bits

18.1.28 LCAP—Link Capabilities Register

(PCI Express—D28:F0/F1/F2/F3/F4/F5)

Address Offset: 4Ch–4Fh Attribute: R/WO, RO

Default Value: See bit description Size: 32 bits

Bit Description

15:6 Reserved

5Transactions Pending (TDP) — RO. This bit has no meaning for the root port since

only one transactio n may be pending to the Intel® ICH8, so a read of this bit cannot

occur until it has already returned to 0.

4AUX Power Dete cted (APD) — RO. The root port contains AUX power for wakeup.

3Unsupported Request Detected (URD) — R/WC. Indicates an unsupported request

was detec ted.

Fatal Error Detected (FED) — R/WC. Indicates a fatal error was detected.

0 = Fatal error has not occurred.

1 = A fatal error occurred from a data link protocol error, link training error, buffer

overflow, or malformed TLP.

Non-Fatal Error Detected (NFED) — R/WC. Indica tes a non- fatal error was detected.

0 = Non-fatal error has not occurred.

1 = A non-fatal error occurred from a poisoned TLP, unexpected completions,

unsupported requests, completer abort, or completer timeout.

Correctable Error Detected (CED) — R/WC. Indicates a correctable error was

detected.

0 = Correctable error has not occurred.

1 = The port received an internal correctable error from receiver errors / framing

errors, TLP CRC error, DLLP CRC error, replay num rollover, replay timeout.

Bit Description

31:24

Port Number (PN) — RO. This field indicates the port number for the root port. This

value is different for each implemented port:

23:21 Reserved

20 Link Active Reporting Capable (LARC) — RO. Hardwired to 1 to indicate that this port

supports the optional capability of reporting the DL_Active state of the Data Link

Control and Management State Machine.

Function Port # Value of PN Field

D28:F0 1 01h

D28:F1 2 02h

D28:F2 3 03h

D28:F3 4 04h

D28:F4 5 05h

D28:F5 6 06h

PCI Express* Configuration Registers

714 Intel® ICH8 Family Datasheet

19:18 Reserved

17:15 L1 Exit Latency (EL1) — RO. Set to 010b to indicate an exit latency of 2 µs to 4 µs.

14:12

L0s Exit Latency (EL0) — RO. This field indicates as exit latency based upon

common-clock configuration.

NOTE: LCLT.CCC is at D28:F0/F1/F2/F3/F4/F5:50h:bit 6

11:10

Active State Link PM Support (APMS) — R/WO. This field indicates what level o f

active state link power management is supported on the root port.

9:4

Maximum Link Width (MLW) — RO . For the root ports, several values can be taken,

based upon the value of the chipset config register field RPC.PC1 (Chipset Config

Registers:Offset 0224h:bits1:0) for Ports 1-4 and RPC.PC2 (Chipset Config

Registers:Offset 0224h:bit s1:0) for Ports 5 and 6

3:0 Maximum Link Speed (MLS) — RO. Set to 1h to indicate the link speed is 2.5 Gb/s.

Bit Description

LCLT.CCC Value of EL0 (these bits)

0MPC.UCEL (D28:F0/F1/F2/

F3:D8h:bits20:18)

1MPC.CCEL (D28:F0/F1/F2/

F3:D8h:bits17:15)

Bits Definition

00b Neither L0s nor L1 are supported

01b L0s Entry Supported

10b L1 Entry Supported

11b Both L0s and L1 Entry Supported

Value of MLW Field

Port # RPC.PC1=00b RPC.PC1=11b

1 01h 04h

2 01h 01h

3 01h 01h

4 01h 01h

Port # RPC.PC2=00b RPC.PC2=11b

5 01h N/A

6 01h N/A

Intel® ICH8 Family Datasheet 715

PCI Express* Configuration Registers

18.1.29 LCTL—Link Control Register

(PCI Express—D28:F0/F1/F2/F3/F4/F5)

Address Offset: 50h-51h Attribute: R/W, WO, RO

Default Value: 0000h Size: 16 bits

Bit Description

15:8 Reserved

Extended Synch (ES) — R/W.

0 = Extended synch disabled.

1 = Forces extended tr ansmission of FTS ordered sets in FTS and extra TS2 at exit from

L1 prior to entering L0.

6Common Clock Conf iguration (CCC) — R/W.

0 = The ICH8 and device are not using a common reference clock.

1 = The ICH8 and device are operating with a distributed common reference clock.

Retrain Link (RL) — WO.

0 = This bit always returns 0 when read.

1 = The root port will train its downstream link.

NOTE: Software uses LSTS.LT (D28:F0/F1/F2/F3/F4/F5 :52, bit 11) to check t he status

of training.

4Link Disable (LD) — R/W.

0 = Enabled .

1 = The root port will disable the link.

3Read Completion Boundary Control (RCBC) — RO. this bit indicates the read

completion boundary is 64 bytes.

2 Reserved

1:0

Active State Link PM Control (APMC) — R/W. This field indicates whether th e root

port should enter L0s or L1 or both.

Bits Definition

00b Disabled

01b L0s Entry is Enabled

10b L1 Entry is Enabled

11b L0s and L1 Entry Enabled

PCI Express* Configuration Registers

716 Intel® ICH8 Family Datasheet

18.1.30 LSTS—Link Status Register

(PCI Express—D28:F0/F1/F2/F3/F4/F5)

Address Offset: 52h–53h Attribute: RO

Default Value: See bit description Size: 16 bits

Bit Description

15:14 Reserved

13 Data Link Layer Active (DLLA) — RO. Default value is 0b.

0 = Data Link Control and Management State Machine is not in the D L_Active state

1 = Data Link Control and Management State Machine is in the DL_Active state

12 Slot Clock Configuration (SCC) — RO. Set to 1b to indicate that the Intel® ICH8 uses

the same reference clock as on the platform and does not generate its own clo ck.

11 Link Training (LT) — RO. Default value is 0b.

0 = Link training completed.

1 = Link training is occurring.

10 Link Training Error (LTE) — RO. Not supported. Set value is 0b.

9:4

Negotiated Link Width (NLW) — RO. This field indicates the negotiated wi dth of th e

given PCI Express* link. The contents of this NLW field is undefined if the link has not

successfully trained.

NOTE: 000001b = x1 link width, 000010b =x2 linkwidth (not supported), 000100b =

x4 linkwidth

3:0 Link Speed (LS) — RO. This field indicates the negotiated Link speed of the given PCI

Express* link.

01h = Link is 2.5 Gb/s.

Port # Possible Values

1000001b, 000010b,

000100b

2 000001b

3 000001b

4 000001b

5 000001b, 000010b

6 000001b

Intel® ICH8 Family Datasheet 717

PCI Express* Configuration Registers

18.1.31 SLCAP—Slot Capabilities Register

(PCI Express—D28:F0/F1/F2/F3/F4/F5)

Address Offset: 54h–57h Attribute: R/WO, RO

Default Value: 00000060h Size: 32 bits

Bit Description

31:19 Physical Slot Number (PSN) — R/WO. This is a value that is unique to the slot

number. BIOS sets this field and it remains set until a platform reset.

18:17 Reserved

16:15 Slot Power Limit Scale (SLS) — R/WO. This field specifies the scale used for the slot

power limit value. BIOS sets this field and it remains set until a platform reset.

14:7

Slot Power Limit Value (SLV) — R/WO. Specifies the upper limit (in conjunction with

SLS value), on the upper limit on power supplied by the slot. The two values together

indicate the amount of power in watts allowed for the slot. BIOS sets this field and it

remains set until a platform reset.

6Hot Plug Capable (HPC) — RO.

1 = Hot-Plug is supported.

5Hot Plug Surprise (H PS ) — RO.

1 = Device may be removed from the slot withou t prior notificati on.

4Power Indicator Present (PIP) — RO.

0 = Power indicator LED is Not present for this slot.

3Attention Indicator Present (AIP) — RO.

0 = Attention indicator LED is Not present for this slot.

2MRL Sensor Present (MSP) — RO.

0 = MRL sensor is Not present.

1Power Controller Present (PCP) — RO.

0 = Power controller is Not implemented for this slot.

0Attention Button Present (ABP) — RO.

0 = Attention button is Not implemented for this slot.

PCI Express* Configuration Registers

718 Intel® ICH8 Family Datasheet

18.1.32 SLCTL—Slot Control Register

(PCI Express—D28:F0/F1/F2/F3/F4/F5)

Address Offset: 58h–59h Attribute: R/W, RO

Default Value: 0000h Size: 16 bits

Bit Description

15:13 Reserved

Link Active Changed Enable (LACE) — R/W. When set, this field enables ge ner a tion

of a hot plug interrupt when the D ata Link La yer Li nk Activ e field (D2 8:F0/F1/ F2/F3/F4/

F5:52h:bit 13) is changed.

0 = Disable.

1 = Enable.

11 Reserved

10 Power Control ler Control (PCC) — RO.This bit has no meaning for module based

Hot-Plug.

9:8

Power Indicato r Control (PIC) — R/W. When read, the current state of the power

indicator is returned. When written, the appropriate POWER_INDICATOR_* messages

are sent. Defined encodings are:

7:6

Attention Indicator Control (AIC) — R/W. When read, the current state of the

attention indicator is returned. When written, the appropriate

ATTENTION_INDICATOR_* messages are sent. Defined encodings are:

5Hot Plug Interrupt Enable (HPE) — R/W.

0 = Disable. Hot plug interrupts based on Hot-Plug events is disabled.

1 = Enables generation of a Hot-Plug interrupt on enabled Ho t-Plug events.

Command Completed Interrupt Enable (CCE) — R/W.

0 = Disable. Hot plug interrupts based on command completions is disabled.

1 = Enables the generation of a Hot-Plug interrupt when a command is completed by

the Hot-Plug controller.

Presence Detect Changed Enable (PDE) — R/W.

0 = Hot plug interrupts based on presence detect logic changes is disabled.

1 = Enables the generation of a Hot -Plug interrupt or wake message when the presence

detect logic changes state.

Bits Definition

00b Reserved

01b On

10b Blink

11b Off

Bits Definition

00b Reserved

01b On

10b Blink

11b Off

Intel® ICH8 Family Datasheet 719

PCI Express* Configuration Registers

18.1.33 SLSTS—Slot Status Register

(PCI Express—D28:F0/F1/F2/F3/F4/F5)

Address Offset: 5Ah–5Bh Attribute: R/WC, RO

Default Value: 0000h Size: 16 bits

2MRL Sensor Changed Enable (MSE) — R/W. MSE not supported.

1Power Fault Det ected Enable (PFE) — R/W. PFE not supported.

Attention Button Pressed Enable (A BE) — R/W. When set, enables the generation

of a Hot-Plug interrupt when the attention button is pressed.

0 = Disable. Hot plug interrupts based on the attention butt on being pressed is

disabled.

1 = Enables the generation of a Hot-Plug interrupt when the attention button is

pressed.

Bit Description

15:9 Reserved

Link Active State Changed (LASC) — R/WC. This bit is set when the value reported

in Data Link Layer Link Active field of the Link Status register (D28:F0/F1/F2/F3/F4/

F5:52h:bit 13) is changed. In response to a Data Link Layer State Changed event,

software must read Data Link Layer Link Active field of the Link Status register to

determine if the link is active before initiating configuration cycles to the hot plugged

device.

0 = No change.

1 = Change

7 Reserved

Presence Detect St at e (PDS) — RO. If XCAP.SI (D28:F0/F1/F2/F3/F4/F5:42h:bit 8)

is set (indicating that this root port spawns a slot), then this bit:

0 = Slot is empty.

1 = Slot has a device connected.

Otherwise, if XCAP.SI is cleared, this bit is always set to 1.

5 MRL Sensor State (MS) — Reserved as the MRL sensor is not implemented.

Command Completed (CC) — R/WC.

0 = Issued command not completed.

1 = The Hot-Plug controller completed an issued command. This is set when the last

message of a command is sent and indicates that software can write a new

command to the slot controller.

3Presence Detect Changed (PDC) — R/WC.

0 = No change in the PDS bit.

1 = The PDS bit changed states.

2 MRL Sensor Changed (MSC) — Reserved as the MRL sensor is not implem ented.

1 Power Fault Detected (PFD) — Reserved as a power controller is not implemented.

0Attention Button Pressed (ABP) — R/WC.

0 = The attention button has Not been pressed.

1 = The attention button is pressed.

PCI Express* Configuration Registers

720 Intel® ICH8 Family Datasheet

18.1.34 RCTL—Root Control Register

(PCI Express—D28:F0/F1/F2/F3/F4/F5)

Address Offset: 5Ch–5Dh Attribute: R/W

Default Value: 0000h Size: 16 bits

18.1.35 RSTS—Root Status Register

(PCI Express—D28:F0/F1/F2/F3/F4/F5)

Address Offset: 60h–63h Attribute: R/WC, RO

Default Value: 00000000h Size: 32 bits

Bit Description

15:4 Reserved

PME Interrupt Enable (PIE) — R/W.

0 = Disable. Interrupt generation disabled.

1 = Interrupt generation enabled when PCISTS.Inerrupt Status (D28:F0/F1/F2/F3/F4/

F5:60h, bit 16) is in a set state (either due to a 0-to-1 transition, or due to this bit

being set with RSTS. I S already set).

System Error on Fatal Error Enable (SFE) — R/W.

0 = An SERR# will Not be generated.

1 = An SERR# will be generated, assuming CMD.SEE (D28:F0/F1/F2/F3/F4/F5:04, bit

8) is set, if a fatal error is reported by any of the devices in the hierarchy of this

root port, including fatal errors in this root port.

System Error on Non-Fatal Error Enable (SNE) — R/W.

0 = An SERR# will Not be generated.

1 = An SERR# will be generated, assuming CMD.SEE (D28:F0/F1/F2/F3/F4/F5:04, bit

8) is set, if a non-fatal error is reported by any of the devices in the hierarchy of

this root port, including non-fatal errors in this root port.

System Erro r on Correctable Error Ena b le (SCE) — R/W.

0 = An SERR# will Not be generated.

1 = An SERR# will be generated, assuming CMD.SEE (D28:F0/F1/F2/F3/F4/F5:04, bit

8) if a correctable error is reported by any of the devices in the hierarchy of this

root port, including correctable errors in this root port.

Bit Description

31:18 Reserved

PME Pending (PP) — RO.

0 = When the original PME is cleared by so ftw are, it will be set again, the requestor ID

will be updated, and this bit will be cleared.

1 = Another PME is pending when the PME status bit is set.

PME Status (PS) — R/WC.

0 = PME was not asserted.

1 = PME was asserted by the requestor ID in RID. Subsequent PMEs are kept pending

until this bit i s cleared.

15:0 PME Requestor ID (RID) — RO. This field indicates the PCI requestor ID of the last

PME requestor. Valid only when PS is set.

Intel® ICH8 Family Datasheet 721

PCI Express* Configuration Registers

18.1.36 MID—Message Signaled Interrupt Identifiers Register

(PCI Express—D28:F0/F1/F2/F3/F4/F5)

Address Offset: 80h–81h Attribute: RO

Default Value: 9005h Size: 16 bits

18.1.37 MC—Message Signaled Interrupt Message Control Register

(PCI Express—D28:F0/F1/F2/F3/F4/F5)

Address Offset: 82–83h Attribute: R/W, RO

Default Value: 0000h Size: 16 bits

18.1.38 MA—Message Signaled Interrupt Message Address

Address Offset: 84h–87h Attribute: R/W

Default Value: 00000000h Size: 32 bits

Bit Description

15:8 Next Pointer (NEXT) — RO. Indicates the location of the next pointer in the list.

7:0 Capability ID (CID) — RO . Capabilities ID indicates MSI.

Bit Description

15:8 Reserved

764 Bit Address Capable (C64) — RO. Capable of generating a 32-bit message only.

6:4 Multiple Message Enable (MME) — R/W. These bits are R/W for software

compatibility, but on ly one message is ever sent by the root port.

3:1 Multiple Message Capable (MMC) — RO. Only one message is required.

MSI Enable (MSIE) — R/W.

0 = Disabled.

1 = MSI is enabled and traditional interrupt pins are not used to generate interrupts.

NOTE: CMD.BME (D28:F0/F1/F2/F3/F4/F5:04h:bit 2) must be set for an MSI to be

generated. If CMD .BME is cleared, and this bit is set, no interrupts (not even pin

based) are generated.

Bit Description

31:2 Address (ADDR) — R/W. This field provides the lower 32 bits of the system specified

message address, always DW aligned.

1:0 Reserved

PCI Express* Configuration Registers

722 Intel® ICH8 Family Datasheet

18.1.39 MD—Message Signaled Interrupt Message Data Register

(PCI Express—D28:F0/F1/F2/F3/F4/F5)

Address Offset: 88h–89h Attribute: R/W

Default Value: 0000h Size: 16 bits

18.1.40 SVCAP—Subsystem Vendor Capability Register

(PCI Express—D28:F0/F1/F2/F3/F4/F5)

Address Offset: 90h–91h Attribute: RO

Default Value: A00Dh Size: 16 bits

18.1.41 SVID—Subsystem Vendor Identification Register

(PCI Express—D28:F0/F1/F2/F3/F4/F5)

Address Offset: 94h–97h Attribute: R/WO

Default Value: 00000000h Size: 32 bits

18.1.42 PMCAP—Power Management Capability Register

(PCI Express—D28:F0/F1/F2/F3/F4/F5)

Address Offset: A0h–A1h Attribute: RO

Default Value: 0001h Size: 16 bits

Bit Description

15:0 Data (DATA) — R/W. This field is programmed by system software if MSI is enabled.

Its content is driven onto the lower word (PCI AD[15:0]) during the data phase of the

MSI memory write transaction.

Bit Description

15:8 Next Capability (NEXT) — RO. Indicates the locati on of the next poi n ter in the list.

7:0 Capability Identifier (CID) — RO. Value of 0Dh indicates this is a PCI bridge

subsystem vendor capability.

Bit Description

31:16 Subsystem Identifier (SID) — R/WO. Indicates the subsystem as identified by the

vendor. This field is write once and is locked down until a bridge reset occurs (not the

PCI bus reset).

15:0 Subsystem Vendor Identifier (SVID) — R/WO. Indicates the manufactu rer of the

subsystem. This field is write once and is locked down until a bridge reset occurs (not

the PCI bus reset).

Bit Description

15:8 Next Capability (NEXT) — RO. Indicates this is the last item in the list.

7:0 Capability Identifier (CID) — RO. Value of 01h indicates this is a PC I power

management capability.

Intel® ICH8 Family Datasheet 723

PCI Express* Configuration Registers

18.1.43 PMC—PCI Power Management Capabilities Register

(PCI Express—D28:F0/F1/F2/F3/F4/F5)

Address Offset: A2h–A3h Attribute: RO

Default Value: C802h Size: 16 bits

Bit Description

15:11

PME_Support (PMES) — RO. Indicates PME# is supported for states D0, D3HOT and

D3COLD. The root port does not generate PME#, but reporting that it does is necessary

for some legacy operating systems to enable PME# in devices connected behind this

root port.

10 D2_Support (D2S) — RO. The D2 state is not supported.

9 D1_Support (D1S) — RO The D1 state is not supported.

8:6 Aux_Current (AC) — RO. Reports 375 mA maximum suspend well current required

when in the D3COLD state.

5Device Specific Initialization (DSI) — RO. Indicates that no device- speci fic init ial ization

is required.

4 Reserved

3 PME Clock (PMEC) — RO. Indicates that PCI clock is not required to generate PME#.

2:0 Version (VS) — RO. Indicates support for Revision 1.1 of the PCI Power Management

Specification.

PCI Express* Configuration Registers

724 Intel® ICH8 Family Datasheet

18.1.44 PMCS—PCI Power Management Control and Status

Address Offset: A4h–A7h Attribute: R/W, RO

Default Value: 00000000h Size: 32 bits

Bit Description

31:24 Reserved

23 Bus Power / Clock Control Enable (BPCE) — Reserved per PCI Express* Base

Specification, Revision 1.0a.

22 B2/B3 Support (B23S) — Reserved per PCI Express* Base Specification, Revision 1.0a.

21:16 Reserved

15 PME Status (PMES) — RO.

0 = PME Not received.

1 = PME was received on the downstream link.

14:9 Reserved

PME Enable (PMEE) — R/W. The root port takes no action on this bit, but it must be

R/W for some legacy operating systems to enabl e PME# on devices connected t o this

root port.

This bit is sticky and resides in the resume well. The reset for this bit is RSMRST# which

is not asserted during a warm reset.

0 = Disable

1 = Enable

7:2 Reserved

1:0

Power State (PS) — R/W. This field is used both to determine the current power state

of the root port and to set a new power state. The values are:

00 = D0 state

11 = D3HOT state

NOTE: When in the D3HOT state, the con trol ler’s configuration space is available, but

the I/O and memory spaces are not. Type 1 configuration cycles are also not

accepted. Interrupts are not required to be blocked as software will disable

interrupts prior to placing the port into D3HOT. If software attempts to write a

‘10’ or ‘01’ to these bits, the write will be ignored.

Intel® ICH8 Family Datasheet 725

PCI Express* Configuration Registers

18.1.45 MPC—Miscellaneous Port Configuration Register

(PCI Express—D28:F0/F1/F2/F3/F4/F5)

Address Offset: D8h–DBh Attribute: R/W, RO

Default Value: 08110000h Size: 32 bits

Bit Description

Power Management SCI Enable (PMCE) — R/W.

0 = Disable. SCI generation based on a power management event is disabled.

1 = Enables the root port to generate SCI whenever a power management event is

detected.

30 Hot Plug SCI Enable (HPCE) — R/W.

0 = Disable. SCI generation based on a Hot-Plug event is disabled.

1 = Enables the root port to generate SCI whenever a Hot-Plug event is detected.

29 Link Hold Off (LHO): When set, the port will not t ake any TLP. This is used during

loopback mode to fill up the downstream queue.

28 Address Translator Enable (ATE): Used to enable address tr anslation via the AT bits

in this register during loopback mode.

Lane Reversal (LR) — RO. This register reads the setting of the SATALED# strap.

0 = PCI Express Lanes 0–3 are reversed.

1 = No Lane reversal (default).

NOTES:

1. The port configuration straps must be set such that Port 1 is configured as a x4

port using lanes 0–3 when Lane Reversal is enabled. x2 lane reversal is not

supported.

2. This register is only valid on port 1.

Invalid Receive Bus Number Che ck Enabl e (IRBNCE): When set, the receive

transaction layer will signal an error if the bus number of a Memory request does not

fall within the r ang e between SCB N and SBBN. If this check is enabled and the request

is a memory write , it is treated as an Unsupported R equest. If this check is enabled and

the request is a non-posted memory read request, the reques t is considered a

Malformed TLP and a fatal error.

Messages, IO, Configuration, and Completions are never checked for valid bus number.

Invalid Receive Range Check Enable (IRRCE): When set, the receive transaction

layer will treat the TLP as an Unsupported Request error if the address range of a

Memory reques t does not outside th e range between prefetchable and non-prefet chable

base and limit.

Messages, I/O, Configuration, and Completions are never checked for valid address

ranges.

BME Receive Check Enable (BMERCE): When set, the receive transaction layer will

treat the TLP as an Unsupported Request error if a memory read or write request is

received and the Bus Master Enable bit is not set.

Messages, I/O, Configuration, and Completions are never checked for BME.

23:21 Reserved

20:18

Unique Clock Exit Latency (UCEL) — R/W. This value represents the L0s Exit

Latency for unique-clock configurations (LCTL.CCC = 0) (D28:F0/F1/F2/F3/F4/

F5:Offset 50h:bit 6). It defaults to 512 ns to less than 1 µs, but may be overridden by

BIOS.

PCI Express* Configuration Registers

726 Intel® ICH8 Family Datasheet

17:15

Common Clock Exit Latency (C CEL) — R/W. This value represents the L0s Exit

Latency for common-clock configurations (LCTL.CCC = 1) (D28:F0/F1/F2/F3/F4/

F5:Offset 50h:bit 6). It defaults to 128 ns to less than 256 ns, but may be overridden

by BIOS.

14:8 Reserved

Port I/OxApic Enable (PAE) — R/W.

0 = Hole is disabled.

1 = A range is opened through the bridge for the following memory addresses:

6:3 Reserved

Bridge Type (BT) — RO. This register can be used to modify the Base Class and

Header Type fields from the default PCI-to-PCI bridge to a Host Bridge. Having the root

port appear as a Host Bridge is useful in some server configurations.

0 = The root port bridge type is a PCI-to-PCI Bridge, Header Sub-Class = 04h, and

Header Type = Type 1.

1 = The root port bridge type is a PCI-to-PCI Bridge, Header Sub-Class = 00h, and

Header Type = Type 0.

1Hot Plug SMI Enable (HPME) — R/W.

0 = Disable. SMI generation based on a Hot-Plug event is disabled.

1 = Enables the root port to generate SMI whenever a Hot-Plug event is detected.

Power Management SMI Enable (PMME) — R/W.

0 = Disable. SMI generation based on a power management event is disabled.

1 = Enables the root port to generate SMI whenever a power management event is

detected.

Bit Description

Port # Address

1 FEC1_0000h – FEC1_7FFFh

2 FEC1_8000h – FEC1_FFFFh

3 FEC2_0000h – FEC2_7FFFh

4 FEC2_8000h – FEC2_FFFFh

5 FEC3_0000h – FEC3_7FFFh

6 FEC3_8000h – FEC3_FFFFh

Intel® ICH8 Family Datasheet 727

PCI Express* Configuration Registers

18.1.46 SMSCS—SMI/SCI Status Register

(PCI Express—D28:F0/F1/F2/F3/F4/F5)

Address Offset: DCh–DFh Attribute: R/WC

Default Value: 00000000h Size: 32 bits

Bit Description

31 Power Management SCI Status (PMCS) — R/WC. This bit is set if the PME control

logic needs to generate an interrupt, and this interrupt has been routed to generate an

SCI.

30 Hot Plug SCI Status (HPCS) — R/WC. This bit is set if the Hot-Plug controller needs

to generate an interrupt, and has this interrupt been routed to generate an SCI.

29:5 Reserved

Hot Plug Link Active State Changed SMI Status (HPLAS) — R/WC. This bit is set

when SLSTS.LASC (D28:F0/F1/F2/F3/F4/F5:5A, bit 8) transitions from 0-to-1, and

MPC.HPME (D28: F0/F1/F 2/F3/F4/F 5:D8, bit 1) is set. When this bit is s et, an SMI# will

be generated.

Hot Plug Command Completed SMI Status (HPCCM) — R/WC. This bit is set when

SLSTS.CC (D28:F0/F1/F2/F3/F4/F5:5A, bit 4) transitions from 0-to-1, and MPC.HPME

(D28:F0/F1/F2/F3/F4/F5:D8, bit 1) is set. When this bit is set, an SMI# will be

generated.

Hot Plug Attention Button SMI Status (H PABM) — R/WC. This bit is set when

SLSTS.ABP (D28:F0/F1/F2/F3/F4/F5: 5A, bit 0) transitions from 0-to-1, and MPC.HPME

(D28:F0/F1/F2/F3/F4/F5:D8, bit 1) is set. When this bit is set, an SMI# will be

generated.

Hot Plug Presence Dete ct SMI Status (H PPDM) — R/WC. This bit is set when

SLSTS.PDC (D28:F 0/F1/ F2/F3/F4 /F5 :5A, bit 3 ) transition s from 0 -to-1 , and MPC. HPME

(D28:F0/F1/F2/F3/F4/F5:D8, bit 1) is set. When this bit is set, an SMI# will be

generated.

0Power Management SMI Status (PMMS) — R/WC. This bit is set when RSTS.PS

(D28:F0/F1/F2/F3/F4/F5:60, bit 16) transitions from 0-to-1, and MPC.PMME (D28:F0/

F1/F2/F3/F4/F5:D8, bit 1) is set.

PCI Express* Configuration Registers

728 Intel® ICH8 Family Datasheet

18.1.47 RPDCGEN—Root Port Dynamic Clock Gating Enable

(PCI Express-D28:F0/F1/F2/F3/F4/F5) (Mobile Only)

Address Offset: E1h Attribute: R/W

Default Value: 00h Size: 8-bits

18.1.48 IPWS—Intel® PRO/Wireless 3945ABG Status

(PCI Express—D28:F0/F1/F2/F3/F4/F5)

Address Offset: E2h–E3h Attribute: RO

Default Value: 0007h Size: 16 bits

Bits Description

7:4 Reserved. RO

Shared Resource Dynamic Link Clock Gating Enable (SRDLCGEN) — RW.

1 = Enables dynamic clock gating on the root port shared resource link clock domain.

0 = Disables dynamic clock gatin g of the shared resource link cloc k domain.

Only the value from Port 1 is used for ports 1–4. Only the value from Port 5 is used for

ports 5-6.

Shared Resource Dynamic Backbone Clock Gate Enable (SRDBCGEN) — RW.

1 = Enables dynamic clock gating on the root port shared resource backbone clock

domain.

0 = Disables dynamic clock gating of the shared resource backbone clock domain.

Only the value from Port 1 is used for ports 1–4. Only the value from Port 5 is used for

ports 5-6.

1Root Port Dynamic Link Clock Gate Enable (RPDLCGEN) — RW.

1 = Enables dynamic clock gating on the root port link clock domain.

0 = Disables dynamic clock gating of the root port link clock domain.

0Root Port Dynamic Backbone Clock Gate Enable (RPDBCGEN) — RW.

1 = Enables dynamic clock gating on the root port backbone clock domain.

0 = Disables dynamic clock gating of the root port backbone clock domain.

Bit Description

15 Intel PRO/Wireless 3945ABG Status (IPWSTAT) — RO. This bit is set if the link

has trained to L0 in Intel PRO/Wireless 3945ABG mode.

14:0 Reserved

Intel® ICH8 Family Datasheet 729

PCI Express* Configuration Registers

18.1.49 VCH—Virtual Channel Capability Header Register

(PCI Express—D28:F0/F1/F2/F3/F4/F5)

Address Offset: 100h–103h Attribute: RO

Default Value: 18010002h Size: 32 bits

18.1.50 VCAP2—Virtual Channel Capability 2 Register

(PCI Express—D28:F0/F1/F2/F3/F4/F5)

Address Offset: 108h–10Bh Attribute: RO

Default Value: 00000001h Size: 32 bits

18.1.51 PVC—Port Virtual Channel Control Register

(PCI Express—D28:F0/F1/F2/F3/F4/F5)

Address Offset: 10Ch–10Dh Attribute: R/W

Default Value: 0000h Size: 16 bits

18.1.52 PVS — Port Virtual Channel Status Register

(PCI Express—D28:F0/F1/F2/F3/F4/F5)

Address Offset: 10Eh–10Fh Attribute: RO

Default Value: 0000h Size: 16 bits

Bit Description

31:20 Next Capability Offset (NCO) — RO. Indicates the next item in the list.

19:16 Capability Version (CV) — RO. Indicates this is version 1 of the capability structure by

the PCI SIG.

15:0 Capability ID (CID) — RO. Indicates this is the Virtual Channel capability item.

Bit Description

31:24 VC Arbitration Table Offset (ATO) — RO. Indicates that no table is present for VC

arbitration since it is fixed.

23:0 Reserved.

Bit Description

15:4 Reserved.

3:1 VC Arbitration Select (AS) — R/W. Indicates which VC should be programmed in the

VC arbitrati on table. The root port tak es no action on the settin g of this field since ther e

is no arbitration table.

0Load VC Arbitration Table (LAT) — R/W. Indicates that the table programmed

should be loaded into the VC arbitration table. This bit always returns 0 when read.

Bit Description

15:1 Reserved.

0VC Arbitration Table Status (VAS) — RO. Indicates the coh erency status of the VC

Arbitration table when it is being updated. This field is always 0 in the root port since

there is no VC arbitration table.

PCI Express* Configuration Registers

730 Intel® ICH8 Family Datasheet

18.1.53 V0CAP — Virtual Channel 0 Resource Capability Register

(PCI Express—D28:F0/F1/F2/F3/F4/F5)

Address Offset: 110h–113h Attribute: RO

Default Value: 00000001h Size: 32 bits

Bit Description

31:24 Port Arbitration Table Offset (AT) — RO. This VC implements no port arbitration table

since the arbitration is fixed.

23 Reserved.

22:16 Maximum Time Slots (MTS) — RO. This VC implements fixed arbitration, and therefore

this field is not used.

15 Reject Snoop Transactions (RTS) — RO. This VC must be able to take snoopable

transactions.

14 Advanced Packet Switching (APS) — RO. This VC is capable of all transactions, not ju st

advanced packet switchin g transactions.

13:8 Reserved.

7:0 Port Arbitration Capability (PAC) — RO. Indicates that this VC uses fixed port

arbitration.

Intel® ICH8 Family Datasheet 731

PCI Express* Configuration Registers

18.1.54 V0CTL — Virtual Channel 0 Resource Control Register

(PCI Express—D28:F0/F1/F2/F3/F4/F5)

Address Offset: 114h–117h Attribute: R/W, RO

Default Value: 800000FFh Size: 32 bits

18.1.55 V0STS — Virtual Channel 0 Resource Status Register

(PCI Express—D28:F0/F1/F2/F3/F4/F5)

Address Offset: 11Ah–11Bh Attribute: RO

Default Value: 0000h Size: 16 bits

Bit Description

31 Virtual Channe l Enable (EN) — RO. Always set to 1. Virtual Channel 0 cannot be

disabled.

30:27 Reserved.

26:24 Virtual Channel Identifier (VCID) — RO. Indicates the ID to use for this virtual channel.

23:20 Reserved.

19:17 Port Arbitration Select (PAS) — R/W. Indicates which port table is being programmed.

The root complex takes no action on this setting since the arbitration is fixed and there

is no arbitration table.

16 Load Port Arbitration Table (LA T) — RO. The r oot port does not implement an arbitration

table for this virtual channel.

15:8 Reserved.

7:1

Transaction Class / Virtual Channel Map (TVM) — R/W. This field indicates which

transaction classes are mapped to this virtual channel. When a bit is set, this

transaction class is mapped to the virtual channel.

0 Reserved. Transaction class 0 must always mapped to VC0.

Bit Transacti on Class

7 Transaction Class 7

6 Transaction Class 6

5 Transaction Class 5

4 Transaction Class 4

3 Transaction Class 3

2 Transaction Class 2

1 Transaction Class 1

0 Transaction Class 0

Bit Description

15:2 Reserved.

1VC Negotiation Pending (NP) — RO.

0 = Negotiation is Not pen ding.

1 = Indicates the Virtual Channel is still being negotiated with ingress ports.

0Port Arbitration Tables Status (ATS). There is no port arbitration table for this VC, so

this bit is reserved as 0.

PCI Express* Configuration Registers

732 Intel® ICH8 Family Datasheet

18.1.56 UES — Uncorrectable Error Status Register

(PCI Express—D28:F0/F1/F2/F3/F4/F5)

Address Offset: 144h–147h Attribute: R/WC, RO

Default Value: 00000000000x0xxx

0x0x0000000x0000b Size: 32 bits

This register maintains its state through a platform reset. It loses its state upon

suspend.

Bit Description

31:21 Reserved

20 Unsupported Request Error Status (URE) — R/WC.

0 = Unsupported request Not received.

1 = Unsupported request was received.

19 ECRC Error Status (EE) — RO. ECRC is not supported.

18 Malformed TLP Status (MT) — R/WC.

0 = Malformed TLP Not received.

1 = Malformed TLP was received.

17 Receiver Overflow Status (RO) — R/WC.

0 = No Receiver overflow.

1 = Receiver overflow occurred.

16 Unexpected Completion Status (UC) — R/WC.

0 = Unexpected completion Not received.

1 = Unexpected completion was received.

15 Completion Abort Status (CA) — R/WC.

0 = Completer abort Not received.

1 = Completer abort was received.

14 Completion Timeout Status (CT) — R/WC. Indicates a completion timed out. This bit

is set if Completion Timeout is enabled and a completion is not returned between 40

and 50 ms.

13 Flow Control Protocol Error Status (FCPE) — RO. Flow Control Protocol Errors not

supported.

12 Poisoned TLP Status (PT) — R/WC.

0 = Poisoned TLP Not received.

1 = Poisoned TLP was received.

11:5 Reserved

4Data Link Protocol Error Status (DLPE) — R/WC.

0 = No data link protocol error.

1 = Data link protocol error occurred.

3:1 Reserved

0 Training Error Status (TE) — RO. Training Errors not supported.

Intel® ICH8 Family Datasheet 733

PCI Express* Configuration Registers

18.1.57 UEM — Uncorrectable Error Mask

(PCI Express—D28:F0/F1/F2/F3/F4/F5)

Address Offset: 148h–14Bh Attribute: R/WO, RO

Default Value: 00000000h Size: 32 bits

When set, the corresponding error in the UES register is masked, and the logged error

will cause no action. When cleared, the corresponding error is enabled.

Bit Description

31:21 Reserved

20 Unsupported Request Error Mask (URE) — R/WO.

0 = The corresponding error in the UES regist er (D28:F0/F1/F2/F3/F4 /F5:144) is enabled.

1 = The corresponding error in the UES register (D28:F0/F1 /F2/F3/F4/F5:144) is masked.

19 ECRC Error Mask (EE) — RO. ECRC is not supported.

18 Malformed TLP Mask (MT) — R/WO.

0 = The corresponding error in the UES regist er (D28:F0/F1/F2/F3/F4 /F5:144) is enabled.

1 = The corresponding error in the UES register (D28:F0/F1 /F2/F3/F4/F5:144) is masked.

17 Receiver Overflow Mask (RO) — R/WO.

0 = The corresponding error in the UES regist er (D28:F0/F1/F2/F3/F4 /F5:144) is enabled.

1 = The corresponding error in the UES register (D28:F0/F1 /F2/F3/F4/F5:144) is masked.

16 Unexpected Completion Mask (UC) — R/WO.

0 = The corresponding error in the UES regist er (D28:F0/F1/F2/F3/F4 /F5:144) is enabled.

1 = The correspondin g error in the UES regi ster (D28:F0/F1/F2 /F3/F4/F5:144) is masked.

15 Completion Abort Mask (CA) — R/WO.

0 = The corresponding error in the UES regist er (D28:F0/F1/F2/F3/F4 /F5:144) is enabled.

1 = The corresponding error in the UES register (D2 8:F0/F 1/F2/ F3/F4/ F5:14 4) i s mask ed.

14 Completion Timeout Mask (CT) — R/WO.

0 = The corresponding error in the UES regist er (D28:F0/F1/F2/F3/F4 /F5:144) is enabled.

1 = The corresponding error in the UES register (D28:F0/F1 /F2/F3/F4/F5:144) is masked.

13 Flow Control Protocol Error Mask (FCPE) — RO. Flow Cont r ol Pr otocol Errors not

supported.

12 Poisoned TLP Mask (PT) — R/WO.

0 = The corresponding error in the UES regist er (D28:F0/F1/F2/F3/F4 /F5:144) is enabled.

1 = The corresponding error in the UES register (D28:F0/F1 /F2/F3/F4/F5:144) is masked.

11:5 Reserved

4Data Link Protocol Error Mask (DLPE) — R/WO.

0 = The corresponding error in the UES regist er (D28:F0/F1/F2/F3/F4 /F5:144) is enabled.

1 = The corresponding error in the UES register (D28:F0/F1 /F2/F3/F4/F5:144) is masked.

3:1 Reserved

0 Training Error Mask (TE) — RO. Training Errors not supported

PCI Express* Configuration Registers

734 Intel® ICH8 Family Datasheet

18.1.58 UEV — Uncorrectable Error Severity

(PCI Express—D28:F0/F1/F2/F3/F4/F5)

Address Offset: 14Ch–14Fh Attribute: RO

Default Value: 00060011h Size: 32 bits

Bit Description

31:21 Reserved

20 Unsupported Request Error Severity (URE) — RO.

0 = Error considered non-fatal. (Default)

1 = Error is fatal.

19 ECRC Error Severity (EE) — RO. ECRC is not supported.

18 Malformed TLP Severity (MT) — RO.

0 = Error considered non-fatal.

1 = Error is fatal. (Default)

17 Receiver Over flo w S everity (RO) — RO.

0 = Error considered non-fatal.

1 = Error is fatal. (Default)

16 Unexpected Completion Severity (UC) — RO.

0 = Error considered non-fatal. (Default)

1 = Error is fatal.

15 Completion Abort Severity (CA) — RO.

0 = Error considered non-fatal. (Default)

1 = Error is fatal.

14 Completion Timeout Severity (CT) — RO.

0 = Error considered non-fatal. (Default)

1 = Error is fatal.

13 Flow Control Protocol Error Severity (FCPE) — RO. Flow Control Protocol Errors not

supported.

12 Poisoned TLP Severity (PT) — RO.

0 = Error considered non-fatal. (Default)

1 = Error is fatal.

11:5 Reserved

4Data Link Protocol Error Severity (DLPE) — RO.

0 = Error considered non-fatal.

1 = Error is fatal. (Default)

3:1 Reserved

0 Training Error Severity (TE) — RO. TE is not supported.

Intel® ICH8 Family Datasheet 735

PCI Express* Configuration Registers

18.1.59 CES — Correctable Error Status Register

(PCI Express—D28:F0/F1/F2/F3/F4/F5)

Address Offset: 150h–153h Attribute: R/WC

Default Value: 00000000h Size: 32 bits

Bit Description

31:14 Reserved

13 Advisory Non-Fatal Error Status (ANFES) — R/WC.

0 = Advisory Non-Fatal Error did not occur.

1 = Advisory Non-Fatal Error did occur.

12 Replay Timer Timeout Status (RTT) — R/WC.

0 = No replay timer time out.

1 = Replay timer timed out occu rred.

11:9 Reserved

8Replay Number Rollover Status (RNR) — R/WC.

0 = Replay number did Not roll over.

1 = Replay number rolled over.

7Bad DLLP Status (BD) — R/WC.

0 = Bad DLLP Not received.

1 = Bad DLLP was received.

6Bad TLP Status (BT) — R/WC.

0 = Bad TLP Not received.

1 = Bad TLP was received.

5:1 Reserved

0Receiver Error Status (RE) — R/WC.

0 = Receiver error did Not occurred.

1 = Receiver error occurred.

PCI Express* Configuration Registers

736 Intel® ICH8 Family Datasheet

18.1.60 CEM — Correctable Error Mask Register

(PCI Express—D28:F0/F1/F2/F3/F4/F5)

Address Offset: 154h–157h Attribute: R/WO

Default Value: 00000000h Size: 32 bits

When set, the corresponding error in the CES register is masked, and the logged error

will cause no action. When cleared, the corresponding error is enabled.

18.1.61 AECC — Advanced Error Capabilities and Control Register

(PCI Express—D28:F0/F1/F2/F3/F4/F5)

Address Offset: 158h–15Bh Attribute: RO

Default Value: 00000000h Size: 32 bits

Bit Description

31:14 Reserved

Advisory Non-Fatal Error Mask (ANFEM) — R/WO.

0 = Does not mask Advisory Non-Fa tal errors.

1 = Masks Advisory Non-Fatal errors from (a) signaling ERR_COR to the device control

This register is set by default to enable compatibility with software that does not

comprehend Role-Based Error Reporting.

12 Replay Timer Timeout Mask (RTT) — R/WO. Mask for replay timer timeout.

11:9 Reserved

8Replay Number Rollover Mask (RNR) — R/WO. Mask for replay number rollover.

7Bad DLLP Mask (BD) — R/WO. Mask for bad DLLP reception.

6Bad TLP Mask (BT) — R/WO. Mask for bad TLP reception.

5:1 Reserved

0Receiver Error Mask (RE) — R/WO. Mask for receiver errors.

Bit Description

31:9 Reserved

8 ECRC Check Enable (ECE) — RO. ECRC is not supported.

7 ECRC Check Capable (ECC) — RO. ECRC is not supported.

6 ECRC Generation Enable (EGE) — RO. ECRC is not supported.

5 ECRC Generation Capable (EGC) — RO. ECRC is not supported.

4:0 First Error Pointer (FEP) — RO.

Intel® ICH8 Family Datasheet 737

PCI Express* Configuration Registers

18.1.62 RES — Root Error Status Register

(PCI Express—D28:F0/F1/F2/F3/F4/F5)

Address Offset: 170h–173h Attribute: R/WC, RO

Default Value: 00000000h Size: 32 bits

18.1.63 RCTCL — Root Complex Topology Capability List Register

(PCI Express—D28:F0/F1/F2/F3/F4/F5)

Address Offset: 180–183h Attribute: RO

Default Value: 00010005h Size: 32 bits

Bit Description

31:27 Advanced Error Interrupt Message Number (AEMN) — RO. There is only one error

interrupt allocated.

26:4 Reserved

3Multiple ERR_FATAL/NONFATAL Received (MENR) — RO. For Intel® ICH8, only

one error will be captured.

2ERR_FATAL/NONF ATAL Received (ENR) — R/WC.

0 = No error message received.

1 = Either a fatal or a non-fatal error message is received.

1Multiple ERR_COR Received (MCR) — RO. F or ICH8, only one error will be captured.

0ERR_COR Received (CR) — R/WC.

0 = No error message received.

1 = A correctable error message is received.

Bit Description

31:20 Next Capability (NEXT) — RO. Indicates the next item in the list, in this case , en d of

list.

19:16 Capability Version (CV) — RO. Indicates the version of the capability structure.

15:0 Capability ID (CID) — RO. Indicates this is a root complex topology capability.

PCI Express* Configuration Registers

738 Intel® ICH8 Family Datasheet

18.1.64 ESD — Element Self Description Register

(PCI Express—D28:F0/F1/F2/F3/F4/F5)

Address Offset: 184h–187h Attribute: RO

Default Value: See Description Size: 32 bits

18.1.65 ULD — Upstream Link Description Register

(PCI Express—D28:F0/F1/F2/F3/F4/F5)

Address Offset: 190h–193h Attribute: RO

Default Value: 00000001h Size: 32 bits

Bit Description

31:24

Port Number (PN) — RO . This field indicate the ingress port number for the root port.

There is a different value per port:

23:16

Component ID (CID) — RO. Thi s field returns the v alue of the ESD .CID field (Chipset

Config Space: Offset 0104h:bits 23:16) of the chip configuration section, that is

programmed by platform BIOS, since the root port is in the same component as the

RCRB.

15:8 Number of Link Entries (NLE) — RO. (Default value is 0 1h) Indicates one link entry

(corresponding to the RCRB).

7:4 Reserved.

3:0 Element Type (ET) — RO. (Default value is 0h) Indicat es that the element type is a

root port.

Port # Value

1 01h

2 02h

3 03h

4 04h

5 05h

6 06h

Bit Description

31:24 Target Port Number (PN) — RO. Indicates the port number of the RCRB.

23:16

Target Component ID (TCID) — RO. This fi eld returns the v alue of the ESD .CID field

(Chipset Configuration Space: Offset 0104h, bits 23:16) of the chip configuration

section, that is programmed by platform BIOS, since the root port is in the same

component as the RCRB.

15:2 Reserved.

1Link Type (LT) — RO. Indicates that the link points to th e Intel® ICH8 RCRB.

0Link Valid (LV) — RO. Indicates that t his link entry is valid.

Intel® ICH8 Family Datasheet 739

PCI Express* Configuration Registers

18.1.66 ULBA — Upstream Link Base Address Register

(PCI Express—D28:F0/F1/F2/F3/F4/F5)

Address Offset: 198h–19Fh Attribute: RO

Default Value: See Description Size: 64 bits

18.1.67 PEETM — PCI Express* Extended Test Mode Register

(PCI Express—D28:F0/F1/F2/F3/F4/F5)

Address Offset: 318h Attribute: RO

Default Value: See Description Size: 8 bits

§ §§

Bit Description

63:32 Base Address Upper (BAU) — RO. The RCRB of the Intel® ICH8 is in 32-bit space.

31:0 Base Address Lower (BAL) — RO. This field matches the RCBA register

(D31:F0:Offset F0h) value in the LPC bridge.

Bit Description

7:3 Reserved

Scrambler Bypass Mode (BAU) — R/W.

0 = Normal operation. Scrambler and descrambler are use d .

1 = Bypasses the data scr ambler in the tr ansmit dire ction and the data de-scr ambler in

the receive direction.

NOTE: This func tionality intended for debug/testing only.

NOTE: If bypassing scrambler with ICH8 root port 1 in x4 configuration, each ICH8 root

port must have this bit set.

1:0 Reserved

PCI Express* Configuration Registers

740 Intel® ICH8 Family Datasheet

Intel® ICH8 Family Datasheet 741

High Precision Event Timer Registers

19 High Precision Event Timer

Registers

The timer registers are memory-mapped in a non-indexed scheme. This allows the

processor to directly access each register without having to use an index register. The

timer register space is 1024 bytes. The registers are generally aligned on 64-bit

boundaries to simplify implementation with IA64 processors. There are four possible

memory address ranges beginning at 1) FED0_0000h, 2) FED0_1000h,

3) FED0_2000h., 4) FED0_4000h. The choice of address range will be selected by

configuration bits in the High Precision Timer Configuration Register (Chipset

Configuration Reg isters:Offset 3404h).

Behavioral Rules:

1. Software must not attempt to read or write across register boundaries. For

example, a 32-bit access should be to offset x0h, x4h, x8h, or xCh. 32-bit accesses

should not be to 01h, 02h, 03h, 05h, 06h, 07h, 09h, 0Ah, 0Bh, 0Dh, 0Eh, or 0Fh.

Any accesses to these offsets will result in an unexpected behavior, and may result

in a master abort. However, these acce sses should not result in system hangs.

64-bit accesses can only be to x0h and must not cross 64-bit boundaries.

2. Software should not write to read only registers.

3. Software should not expect any particular or consistent value when reading

reserved registers or bits.

19.1 Memory-Mapped Registers

Table 142. Memory-Mapped Registers (Sheet 1 of 2)

Offset Mnemonic Register Default Type

000–007h GCAP_ID General Capabilities and Identification 0429B17F8

086A201h RO

008–00Fh — Reserved — —

010–017h GEN_CONF General Configuration 0000h R/W

018–01Fh — Reserved — —

020–027h GINTR_STA General Interrupt Status 00000000

00000000h R/WC,

R/W

028–0EFh — Reserved — —

0F0–0F7h MAIN_CNT Main Counter Value N/A R/W

0F8–0FFh — Reserved — —

100–107h TIM0_CONF Timer 0 Configuration and Capabilities N/A R/W, RO

108–10Fh TIM0_COMP Timer 0 Comparator Value N/A R/W

110–11Fh — Reserved — —

120–127h TIM1_CONF Timer 1 Configuration and Capabilities N/A R/W, RO

128–12Fh TIM1_COMP Timer 1 Comparator Value N/A R/W

130–13Fh — Reserved — —

High Precision Event Timer Registers

742 Intel® ICH8 Family Datasheet

NOTES:

1. Reads to reserved registers or bits will return a value of 0.

2. Software must not attempt locks to the memory-mapped I/O ranges for High Precision

Event Timers. If attempted, the lock is not honored, which means potential deadlock

conditions may occur.

19.1.1 GCAP_ID—General Capabilities and Identification Register

Address Offset: 00h Attribute: RO

Default Value: 0429B17F8086A201h Size: 64 bits

140–147h TIM2_CONF Timer 2 Configuration and Capabilities N/A R/W, RO

148–14Fh TIM2_COMP Timer 2 Comparator Value N/A R/W

150–15Fh — Reserved — —

160–3FFh — Reserved — —

Table 142. Memory-Mapped Registers (Sheet 2 of 2)

Offset Mnemonic Register Default Type

Bit Description

63:32 Main Counter Tick Period (COUNTER_CLK_PER_CAP) — RO. This field indicates the

period at which the counter increments in femptoseconds (10^-15 seconds). This will

return 0429B17F when read. This indicates a period of 69841279 fs (69.841279 ns).

31:16 Ven dor ID Capability (VENDOR_ID_CAP) — RO. This is a 16-bit value assigned to

Intel.

15 Legacy Replacement Rout Capable (LEG_RT_CAP) — RO. Hardwired to 1. Legacy

Replac em en t In t erru pt Rout opti on is supported.

14 Reserved. This bit returns 0 when read.

13 Counter Size Capability (COUNT_SIZE_CAP) — RO. Hardwired to 1. Counter is 64-bit

wide.

12:8 Number of Timer Capability (NUM_TIM_CAP) — RO. This field in dicates the number of

timers in this block.

02h = Three timers.

7:0 Re vision Identificat ion (REV_ID) — RO . This indicates which revision of the functi on is

implemented. D efault value will be 01h.

Intel® ICH8 Family Datasheet 743

High Precision Event Timer Registers

19.1.2 GEN_CONF—General Configuration Register

Address Offset: 010h Attribute: R/W

Default Value: 00000000 00000000h Size: 64 bits

19.1.3 GINTR_STA—General Interrupt Status Register

Address Offset: 020h Attribute: R/W, R/WC

Default Value: 00000000 00000000h Size: 64 bits

Bit Description

63:2 Reserved. These bits return 0 when read.

Legacy Replacement Rout (LEG_RT_CNF) — R/W. If the ENABLE_CNF bit and the

LEG_RT_CNF bit are both set, then the interrupts will be routed as follows:

• Timer 0 is routed to IRQ0 in 8259 or IRQ2 in the I/O APIC

• Timer 1 is routed to IRQ8 in 8259 or IRQ8 in the I/O APIC

• Timer 2-n is routed as per the routing in the timer n config registers.

• If the Legacy Replacement Rout bit is set, the individual routing bits for Timers 0 and 1 (APIC)

will have no impact.

• If the Legacy Replacement Rout bit is not set, the individual routing bits for each of the timers

are used.

• This bit will default to 0. BIOS can set it to 1 to enable the legacy replacement routing, or 0 to

disable the legacy replacement routing.

Overall Enable (ENABLE_CNF) — R/W. This bit must be set to enable any of the

timers to generate interrupts. If this bit is 0, then the main counter will halt (will not

increment) and no i nte rrupts will be caused by any of these time rs. For level-triggered

interrupts, if an interrupt is pending when the ENABLE_CNF bit is changed from 1 to 0,

the interrupt status indications (in the various Txx_INT_STS bits) will not be cleared.

Software must write to the Txx_INT_STS bits to clear the interrupts.

NOTE: This bit will default to 0. BIOS can set it to 1 or 0.

Bit Description

63:3 Reserved. These bits will return 0 when read.

2Timer 2 Interrupt Active (T02_INT_STS) — R/W. Same functionality as Timer 0.

1Timer 1 Interrupt Active (T01_INT_STS) — R/W. Same functionality as Timer 0.

Timer 0 Interrupt Active (T00_INT_STS) — R/WC. The functionality of this bit

depends on whether the edge or level-triggered mode is used for this timer.

(default = 0).

If set to level-triggered mode:

This bit will be set by hardware if the corresponding timer interru p t is active. Once the

bit is set, it can be cleared by software writing a 1 to the same bit position. Writes of 0

to this bit will have no effect.

If set to edge-triggered mode:

This bit should be ignored by software. Software should always write 0 to this bit.

NOTE: Defaults to 0. In edge triggered mode, this bit will always read as 0 and writes

will have no effect.

High Precision Event Timer Registers

744 Intel® ICH8 Family Datasheet

19.1.4 MAIN_CNT—Main Counter Value Register

Address Offset: 0F0h Attribute: R/W

Default Value: N/A Size: 64 bits

19.1.5 TIMn_CONF—Timer n Configuration and Capabilities

Address Offset: Timer 0: 100–107h, Attribute: RO, R/W

Timer 1: 120–127h,

Timer 2: 140–147h

Default Value: N/A Size: 64 bits

Note: The letter n can be 0, 1, or 2, referring to Timer 0, 1 or 2.

Bit Description

63:0

Counter Value (COUNTER_VAL[63:0]) — R/W. Reads return the current value of

the counter. Writes load the new value to the counte r.

NOTES:

1. Writes to this register should only be done while the counter is halted.

2. Reads to this register return the current value of the main counter.

3. 32-bit counters will always return 0 for the upper 32-bits of this register.

4. If 32-bit software attempts to read a 64-bit counter, it should first h alt the

counter. Since this delays the interrupts for all of the timers, this should be

done only if the conseq uences are understood. It is strongly recommended

that 32-bit software only operate the timer in 32-bit mode.

5. Reads to this register are monotonic. No two consecutive reads return the

same value. The second of two reads always returns a larger value (unless

the timer has rolled over to 0).

Bit Description

63:56 Reserved. These bits will return 0 when read.

55:52,

Timer Interrupt Rout Capability (TIMERn_INT_ROUT_CAP) — RO.

Timer 0, 1:Bits 52, 53, 54, and 55 in this fi eld (corr esponding to IRQ 20 , 21, 22 , and

23) have a value of 1. Writes will have no effect.

Timer 2:Bits 43, 52, 53, 54, and 55 in this field ( corresponding to IRQ 11, 20, 21, 22,

and 23) have a value of 1. Writes will have no effect.

NOTE: If IRQ 11 is used for HPET #2, software should ensure IRQ 11 is not shared

with any other devices to assure the proper operation of HPET #2.

51:44,

42:14 Reserved. These bits return 0 when read.

13:9

Interrupt Rout (TIMERn_INT_ROUT_CNF) — R/W. This 5-bit field indicates the

routing for the interrupt to the I/O (x) APIC. Software writes to this field to select

which interrupt in the I/O (x) will be used for this timer’ s interrupt. If the v alue is not

supported by this particular timer, then the value read back will not match what is

written. The software must only write valid values.

NOTES:

1. If the Legacy Replacement Rout bit is set, then Timers 0 and 1 will have a

different routing, and this bit field has no effect for those two timers.

2. Timer 0,1: Software is responsible to make sure it programs a valid value (20,

21, 22, or 23) for this field. The ICH8 logic does not check the validity of the

value written.

3. Timer 2: Software is responsible to make sure it programs a valid value (11,

20, 21, 22, or 23) for this field. The ICH8 logic does not check the validity of

the value written.

Intel® ICH8 Family Datasheet 745

High Precision Event Timer Registers

NOTE: Reads or writes to unimplemented timers should not be attempted. Read from any

unimplemented registers will return an undetermined value.

Timer n 32-bit Mode (TIMERn_32MODE_CNF) — R/W or RO. Software can set

this bit to force a 64-bit timer to behave as a 32-bit timer.

Timer 0: Bit is read/write (default to 0). 0 = 64 bit; 1 = 32 bit

Timers 1, 2: Hardwired to 0. Writes have no effect (since these two timers are 32-

bits).

NOTE: When this bit is set to ‘1’, the hardware counter will do a 32-bit operation on

comparator match and rollovers, thus the upper 32-bit of the Timer 0

Comparator Value register is ignored. The upper 32-bit of the main counter is

not involved in any rollover from lower 32-bit of the main counter and

becomes all ze ros.

7 Reserved. This bit returns 0 when read.

Timer n Value Set (TIMERn_VAL_SET_CNF) — R/W. Software uses this bit only

for Timer 0 if it has been set to periodic mode. By writing this bit to a 1, the software

is then allowed to directly set the timer’s accumulator. Software does not have to

write this bit back to 1 (it automatically clears).

Software should not write a 1 to this bit position if the timer is set to non-periodic

mode.

NOTE: This bit will return 0 when read. Wr ites will only have an effect for Timer 0 if it

is set to periodic mode. Writes will have no effect for Timers 1 and 2.

Timer n Size (TIMERn_SIZE_CAP) — RO . This read only field indicates the size of

the timer.

Timer 0: Value is 1 (64-bits).

Timers 1, 2: Value is 0 (32-bits).

Periodic Interrupt Capable (TIMERn_PER_INT_CAP) — RO. If this bit is 1, the

hardware supports a periodic mode for this timer’s interrupt.

Timer 0: Hardwired to 1 (supports the periodic interrupt).

Timers 1, 2: Hardwired to 0 (does not support periodic interrupt).

Timer n Type (TIMERn_TYPE_CNF) — R/W or RO.

Timer 0: Bit is read/write. 0 = Disable timer to generate periodic interrupt;

1 = Enable timer to generate a periodic interrupt.

Timers 1, 2: Hardwired to 0. Writes have no affect.

Timer n Interrupt Enabl e (TIMERn_INT_ENB_CNF) — R/W. This bit must be set

to enable timer n to cause an interrupt when it times out.

1 = Enable.

0 = Disable (Default ). Th e ti me r c a n s ti ll c ount and generate appropriate status bits,

but will not cause an interrupt.

Timer Interrupt Type (TIMERn_INT_TYPE_CNF) — R/W.

0 = The timer interrupt is edge triggered. This means that an edge-type interrupt is

generated. If another interrupt occurs, another edge will be generated.

1 = The timer interrupt is le ve l trigge red. This means that a level-triggered interrupt

is generated. The interrupt will be held active until it is cleared by writing to the

bit in the General Interrupt Status R egister. If another interrupt occurs before the

interrupt is cleared, the interrupt will remain active.

0 Reserved. These bits will return 0 when read.

Bit Description

High Precision Event Timer Registers

746 Intel® ICH8 Family Datasheet

19.1.6 TIMn_COMP—Timer n Comparator Value Register

Address Offset: Timer 0: 108h–10Fh,

Timer 1: 128h–12Fh,

Timer 2: 148h–14Fh

Attribute: R/W

Default Value: N/A Size: 64 bit

§ §

Bit Description

63:0

Timer Compare Value — R/W. R eads to this register return the current va lue of the

comparator

Timers 0, 1, or 2 are configured to non-periodic mode:

Writes to this register load the value against which the main counter should be

compared for this timer.

• When the main counter equals the value last written to this register, the corresponding

interrupt can be generated (if so enabled).

• The value in this register does not change based on the interrupt being generated.

Timer 0 is configured to periodic mode:

• When the main counter equals the value last written to this register, the corresponding

interrupt can be generated (if so enabled).

•A

fter the main counter equals the value in this register, the value in this register

is increased by the value las t wri tten to the register.

For example, if the value written to the register is 00000123h, then

1. An interrupt will be generated when the main counter reaches 00000123h.

2. The v al u e i n t his register will the n be adjust ed by the hardware to 00000246h.

3. Another interrupt will be generat ed when the m ain counter reac hes 00000246h

4. The value in this register will then be adjusted by the hardware to 00000369h

• As each periodic interrupt occurs, the value in this register will increment. When

the incremented value is greater than the maximum value possible for this

the value will wr ap around through 0. For exampl e, if the current v alue in a 32-bit

timer is FFFF0000h and t he last v alue writte n to this regis ter is 20000, then after

the next interrupt the value will change to 00010000h

Default val ue for each timer is al l 1 s for the bits that are i mpl em en te d. For example,

a 32-bit timer has a default value of 00000000FFFFFFFFh. A 64-bit timer has a

default value of FFFFFFFFFFFFFFFFh.

Intel® ICH8 Family Datasheet 747

Serial Peripheral Interface (SPI)

20 Serial Peripheral Interface

(SPI)

The Serial Peripheral Interface resides in memory-mapped space. This function

contains registers that allow for the setup and programming of devices that reside on

the SPI interface.

Note: All registers in this function (including memory-mapped registers) must be addressable

in byte, word, and dword quantities. The software must alw ays make register accesses

on natural boundaries (i.e., DWord accesses must be on DWord boundaries; word

accesses on word boundaries, etc.) In addition, the memory-mapped register space

must not be accessed with the LOCK semantic exclusive-access mechanism. If software

attempts exclusive-access mechanisms to the SPI memory-mapped space, the results

are undefined.

20.1 Serial Peripheral Interface Memory-Mapped

Configuration Registers

The SPI Host Interface registers are memory-mapped in the RCRB Chipset Register

Space with a base address (SPIBAR) of 3020h and are located within the range of

3020h to 30FFh. The individual registers are then accessible at SPIBA R + Offset as

indicated in Table 143.

These memory mapped registers must be accessed in byte, word, or DWord quantities.

Table 143. Serial Peripheral Interface (SPI) Register Address Map

(SPI Memory Mapped Configuration Registers) (Sheet 1 of 2)

SPIBAR +

Offset Mnemonic Register Name Default Access

00h–03h BFPR BIOS Flash Primary Region 00000000h RO

04h–05h HSFS Hardware Sequencing Flash Status 0000h RO, R/WC,

R/WL

06h–07h HSFC Hardware Sequencing Flash Control 0000h R/W,

R/WS

08h–0Bh FADDR Flash Address 00000000h R/W

0Ch–0Fh — Reserved 00000000h —

10h–13h FDATA0 Flash Data 0 00000000h R/W

14h–4Fh FDATAN Flash Data N 00000000h R/W

50h–53h FRACC Flash Region Access Permissions 00000000h RO, R/WL

54h–57h FREG0 Flash Region 0 00000000h RO

58h–5Bh FREG1 Flash Region 1 00000000h RO

5Ch–5F FREG2 Flash Region 2 00000000h RO

60h–63h FREG3 Flash Region 3 00000000h RO

64h–73h — Reserved — —

74h–77h FPR0 Flash Protected Range 0 00000000h R/WL

Serial Peripheral Interface (SPI)

748 Intel® ICH8 Family Datasheet

20.1.1 BFPR—BIOS Flash Primary Region Register

(SPI Memory Mapped Configuration Registers)

Memory Address:SPIBAR + 00h Attribute: RO

Default Value: 00000000h Size: 32 bits

78h–7Bh FPR1 Flash Protected Range 1 00000000h R/WL

7Ch–7Fh FPR2 Flash Protected Range 2 00000000h R/WL

80–83h FPR3 Flash Protected Range 3 00000000h R/WL

84h–87h FPR4 Flash Protected Range 4 00000000h R/WL

88h–8Fh — Reserved — —

90h SSFS Software Sequencing Flash Status 0000h RO, R/WC

91h–93h SSFC Software Sequencing Flash Control 0000h R/W

94h–95h PREOP Prefix Opcode Configuration 0000h R/WL

96h–97h OPTYPE Opcode Type Configuration 0000h R/W

98h–9Fh OPMENU Opcode Menu Configuration 00000000

00000000h R/W

B0h–B3h FDOC Flash Descriptor Observability Control 00000000h R/W

B4h–B7h FDOD Flash Descriptor Observability Data 00000000h RO

B8h–DFh — Reserved — —

C1h–C4h VSCC Vendor Specific Component Capabilities 00000000h RO, R/WL

Table 143. Serial Peripheral Interface (SPI) Register Address Map

(SPI Memory Mapped Configuration Registers) (Sheet 2 of 2)

SPIBAR +

Offset Mnemonic Register Name Default Access

Bit Description

31:29 Reserved

28:16

BIOS Flash Primary Region Limit (PRL) — RO. This field specifies address

bits 24:12 for the Primary Region Limit.

The value in this register loaded from the contents in the Flash

Descriptor.FLREG1.Region Limit.

15:13 Reserved

12:0

BIOS Flash Primary Region Base (PRB) — RO. This field speci f ies address

bits 24:12 for the Primary Region Base

The value in this register is loaded from the contents in the Flash

Descriptor.FLREG1.Region Base.

Intel® ICH8 Family Datasheet 749

Serial Peripheral Interface (SPI)

20.1.2 HSFS—Hardware Sequencing Flash Status Register

(SPI Memory Mapped Configuration Registers)

Memory Address:SPIBAR + 04h Attribute: RO, R/WC, R/WL

Default Value: 0000h Size: 16 bits

Bit Description

Flash Configuration Lock-Down (FLOCKDN)— R/W/L. When set to 1, the Flash

Program Registers that are locked down by this FLOCKDN bit cannot be written. Once

set to 1, this bit can only be cleared by a hardware reset.

Hardware reset is initiated by one of the following resets:

• Global reset (when the Ho st and the ME partitions are both reset) - on both ME-enabled and

non-ME systems.

• Host Parti tion reset (any time PLTRST# is asserted either from a cold or a warm reset) - only on

ME enabled systems.

Flash Descriptor Valid (FDV)— RO. This bit is set to a 1 if the Flash Controller read

the correct Flash Descriptor Signature.

If the Flash Descriptor Valid bit is not 1, software cannot use the Hardware Sequencing

registers, but must use the software sequencing registers. Any attempt to use the

Hardware Sequencing registers will result in the FCERR bit being set.

Flash Descriptor Override Pin-Strap Status (FDOPSS) — RO: This bit reflects the

value the Flash Descriptor Override Pin-Strap.

0 = The Flash Descriptor Override strap is set

1 = No override

12:6 Reserved

SPI Cycle In Progress (SCIP)— RO. Hardware sets this bit when software sets the

Flash Cycle Go (FGO) bit in the Hardware Sequencing Flash Control register. This bit

remains set until the cycle completes on the SPI interface. Hardware automatically sets

and clears this bit so that software can determine when read data is valid and/or when

it is safe to begin programming the next command. Software must only program the

next command when this bit is 0.

4:3

Block/Sector Erase Size (BERASE) — RO. This field identifies the erasable sec tor

size for all Flash components.

Va lid Bit Settings:

00 = 256 Byte

01 = 4 KB

10 = Reserved for future use

11 = 64 KB

Access Error Log (AEL)— R/W/C. Hardware sets this bit to a 1 when an attempt was

made to access the BIOS region using the direct access method or an access to the

BIOS Program Registers that violated the security restrictions. This bit is simply a log of

an access security violation. This bit is cleared by software writing a 1.

Flash Cycle Error (FCERR) — R/W/C. Hardware sets this bit to 1 when an program

any of the programmed cycle registers is written while a programmed access is already

in progre ss. This bit remains asserted until cleared by software writing a 1 or until

hardware reset occurs. Software must clear this bit before setting the FLASH Cycle GO

bit in this register.

Hardware reset is initiated by one of the following resets:

• Global reset (when the Ho st and the ME partitions are both reset) - on both ME-enabled and

non-ME systems.

• Host Parti tion reset (any time PLTRST# is asserted either from a cold or a warm reset) - only on

ME enabled systems.

Serial Peripheral Interface (SPI)

750 Intel® ICH8 Family Datasheet

20.1.3 HSFC—Hardware Sequencing Flash Control Register

(SPI Memory Mapped Configuration Registers)

Memory Address:SPIBAR + 06h Attribute: R/W, R/WS

Default Value: 0000h Size: 16 bits

Flash Cycle Done (FDONE) — R/W/C. Th e ICH8 set s this bit to 1 when the SP I Cy cle

completes after software previously set the FGO bit. This bit remains asserted until

cleared by software writing a 1 or hardware reset. When this bit is set and the SPI

SMI# Enable bit is set, an internal signal is asserted to the SMI# generation block.

Software must make sure this bit is cleared prior to enabling the SPI SMI# assertion for

a new programmed access.

Hardware reset is initiated by one of the following resets:

• Global reset (when the Host and the ME partitions are both reset) - on both ME-enabled and

non-ME systems.

• Host Pa rtition reset (an y time PLTRST# is asserted either from a cold or a warm reset) - only on

ME enabled systems.

Bit Description

15 Flash SPI SMI# Enable (FSMIE): — R/W. When set to 1, the SPI asserts an SMI#

request whenever the Flash Cycle Done b it is 1.

14 Reserved

13:8

Flash Data Byte Count (FDBC): — R/W. This field specifies the number of bytes to

shift in or out during the data portion of the SPI cycle. The contents of this register are

0’ s based with 0b repres enting 1 byte and 111111b repres enting 64 bytes. The number

of bytes transferred is the value of this field plus 1.

This field is ignored for the Block Erase command.

7:3 Reserved

2:1

FLASH Cycle (FCYCLE). — R/W. This field defines the Flash SPI cycle type generated

to the FLASH when the FGO bit is set as defined below:

00 = Read (1 up to 64 bytes by setting FDBC)

01 = Reserved

10 = Write (1 up to 64 bytes by setting FDBC)

11 = Block Erase

Flash Cycle Go (FGO): — R/W/S. A write to this register with a 1 in this bit initiates a

request to the Flash SPI Arbiter to start a cycle. This register is cleared by hardware

when the cycle is granted by the SPI arbiter to run the cycle on the SPI bus. When the

cycle is complete, the FDONE bit is set.

Software is forbidden to write to any regist er in the HSFLCTL register between the FGO

bit getting set and the FDONE bit being cleared. Any attempt to violate this rule will be

ignored by hardware.

Hardware allows other bits in this register to be programmed for the same transaction

when writing this bit to 1. This saves an additional memory write.

This bit always returns 0 on reads.

Intel® ICH8 Family Datasheet 751

Serial Peripheral Interface (SPI)

20.1.4 FADDR—Flash Addr ess Register

(SPI Memory Mapped Configuration Registers)

Memory Address:SPIBAR + 08h A ttribute: R/W

Default Value: 00000000h Size: 32 bits

20.1.5 FDATA0—Flash Data 0 Register

(SPI Memory Mapped Configuration Registers)

Memory Address:SPIBAR + 10h A ttribute: R/W

Default Value: 00000000h Size: 32 bits

20.1.6 FDATAN—Flash Data [N] Register

(SPI Memory Mapped Configuration Registers)

Memory Address:SPIBAR + 14h A ttribute: R/W

SPIBAR + 18h

SPIBAR + 1Ch

SPIBAR + 20h

SPIBAR + 24h

SPIBAR + 28h

SPIBAR + 2Ch

SPIBAR + 30h

SPIBAR + 34h

SPIBAR + 38h

SPIBAR + 3Ch

SPIBAR + 40h

SPIBAR + 44h

SPIBAR + 48h

SPIBAR + 4Ch

Default Value: 00000000h Size: 32 bits

Bit Description

31:25 Reserved

24:0

Flash Linear Address (FLA): — R/W. The FLA is the starting byte linear address of a

SPI Read or W rite cy cle or an address within a Block for the Block Erase command. The

Flash Linear Address must fall within a region for which BIOS has access permissions.

Hardware must conv ert the FLA into a Flash Physical Address (FPA) before running this

cycle on the SPI bus.

Bit Description

31:0

Flash Data 0 (FD0): — R/W. This field is shifted out as the SPI Data on the Master-

Out Slave-In Data pin during the data portion of the SPI cycle.

This register also shifts in the data from the Master-In Slave-Out pin into this register

during the data portion of the SPI cycle.

The data is always shifted starting with the least significan t byte, msb to lsb, followed

by the next least significant byte, msb to lsb, etc. Specifically, the shift order on SPI in

terms of bits within this register is: 7-6-5-4-3-2-1-0-15-14-13-…8-23-22-…16-31…24

Bit 24 is the last bit shifted out/in. There are no alignment assumptions; byte 0 always

represents the value spec if ied by the cycle address.

Note that the data in this register may be modified by the hardware during any

programmed SPI transaction. Direct Memory Reads do not modify the contents of this

Bit Description

31:0 Flash Data N (FD[N]): — R/W. Similar definition as Flash Data 0. However, this

Serial Peripheral Interface (SPI)

752 Intel® ICH8 Family Datasheet

20.1.7 FRAP—Flash Regions Access Permissions Register

(SPI Memory Mapped Configuration Registers)

Memory Address:SPIBAR + 50h Attribute: RO, R/WL

Default Value: 00000202h Size: 32 bits

20.1.8 FREG0—Flash Region 0 (Flash Descriptor) Register

(SPI Memory Mapped Configuration Registers)

Memory Address:SPIBAR + 54h Attribute: RO

Default Value: 00000000h Size: 32 bits

Bit Description

31:24

BIOS Master Write Access Grant (BMWAG): — R/WL. Each bit [31:29] corresponds

to Master[7:0]. BIOS can grant one or more masters write access to the BIOS region 1

overriding the permissions in the Flash Descriptor.

Master[1] is Host CPU/BIOS, Master[2] is ME, Master[3] is Host CPU/GbE. Master[0]

and Master[7:4] are res erved.

The contents of this register are locked by the FLOCKDN bit .

23:16

BIOS Master Read Access Grant (BMRAG): — R/WL. Each bit [28:16] corresponds

to Master[7:0]. BIOS can grant one or more masters read access to the BIOS regi on 1

overriding the read permissions in the Flash Descriptor.

Master[1] is Host CPU/BIOS, Master[2] is ME, Master[3] is Host CPU/GbE. Master[0]

and Master[7:4] are res erved.

The contents of this register are locked by the FLOCKDN bit

15:8

BIOS Region Write Access (BRWA): — RO. Each bit [15:8] corresponds to Regions

[7:0]. If the bit is set, this master can erase and write that particular region through

The contents of this register are that of the Flash Descriptor. Fl ash Master 1 Master

Region Write Access OR a particular master has granted BIOS write permissions in their

Master Write Access Grant register or the Flash Descriptor Security Override strap is

set.

7:0

BIOS Region Read Access (BRRA): — RO. Each bit [7:0] corresponds to Regions

[7:0]. If the bit i s set, this master can read that particular region through register

accesses.

The contents of this register are that of the Flash Descriptor.Flash Master 1.Master

Region W rite Access OR a particular master has granted BIOS read permissions in their

Master Read Access Grant register or the Flash Descriptor Security Override strap is

set.

Bit Description

31:29 Reserved

28:16

Region Limit (RL): — RO. This field specifies address bits 24:12 for the Region 0

Limit.

The value in this register is loaded from the contents in the Flash

Descriptor.FLREG0.Region Limit

15:13 Reserved

12:0

Region Base (RB) / Flash Descriptor Base Address Region (FDBAR): — RO. This

field specifies address bits 24:12 for the Region 0 Base.

The value in this register is loaded from the contents in the Flash

Descriptor.FLREG0.Region Base

Intel® ICH8 Family Datasheet 753

Serial Peripheral Interface (SPI)

20.1.9 FREG1—Flash Region 1 (BIOS Descriptor) Register

(SPI Memory Mapped Configuration Registers)

Memory Address:SPIBAR + 58h Attribute: RO

Default Value: 00000000h Size: 32 bits

20.1.10 FREG2—Flash Region 2 (ME) Register

(SPI Memory Mapped Configuration Registers)

Memory Address:SPIBAR + 5Ch Attribute: RO

Default Value: 00000000h Size: 32 bits

Bit Description

31:29 Reserved

28:16

Region Limit (RL): — RO. This field specifies address bits 24:12 for the Region 1

Limit.

The value in this register is loaded from the contents in the Flash

Descriptor.FLREG1.Region Limit.

15:13 Reserved

12:0

Region Base (RB): — RO. This field specifies address bits 24:12 for the Region 1

Base.

The value in this register is loaded from the contents in the Flash

Descriptor.FLREG1.Region Base.

Bit Description

31:29 Reserved

28:16

Region Limit (RL): — RO. This field specifies address bits 24:12 for the Region 2

Limit.

The value in this register is loaded from the contents in the Flash

Descriptor.FLREG2.Region Limit.

15:13 Reserved

12:0 Region Base (RB): — RO. This field specifies address bits 24:12 for the R e gion 2 Base

The value in this register is loaded from the contents in the Flash

Descriptor.FLREG2.Region Base.

Serial Peripheral Interface (SPI)

754 Intel® ICH8 Family Datasheet

20.1.11 FREG3—Flash Region 3 (GbE) Register

(SPI Memory Mapped Configuration Registers)

Memory Address:SPIBAR + 60h Attribute: RO

Default Value: 00000000h Size: 32 bits

20.1.12 PR0—Protected Range 0 Register

(SPI Memory Mapped Configuration Registers)

Memory Address:SPIBAR + 74h Attribute: R/WL

Default Value: 00000000h Size: 32 bits

Note: This register can not be written when the FLOCKDN bit is set to 1.

Bit Description

31:29 Reserved

28:16

Region Limit (RL): — RO. This field specifies address bits 24:12 for the Region 3

Limit.

The value in this register is loaded from the contents in the Flash

Descriptor.FLREG3.Region Limit.

15:13 Reserved

12:0 Region Base (RB): — RO. This specifies address bits 24:12 for the Region 3 Base

The value in this register is loaded from the contents in the Flash

Descriptor.FLREG3.Region Base.

Bit Description

Write Protection Enable: — R/WL. When set, this bit indicates that the Base and

Limit fields in this register are valid and that writes and erases directed to addresses

between them (inclusive) must be blocked by hardware. The base and limit fields are

ignored when this bit is cleared.

30:29 Reserved

28:16

Protected Range Limit: — R/WL. This field corresponds to FLA address bits 24:12 and

specifies the upper limit of the protected range. Address bits 11:0 are assumed to be

FFFh for the limit comparison. Any address greater than the value programmed in this

field is unaffected by this protected range.

Read Protect ion Enable: — R/WL. When set, this bit indicates that the Base and Limit

fields in this register are valid and that read directed to addresses between them

(inclusive) must be blocked by hardware. The base and limit fields are ignored when

this bit is cleared.

14:13 Reserved

12:0

Protected Range Base: — R/WL. This field corresponds to FLA address bits 24:12 and

specifies the lower base of the prot ected range. Address bits 11:0 are assumed to be

000h for the base comparison. Any address less than the value programmed in this

field is unaffected by this protected range.

Intel® ICH8 Family Datasheet 755

Serial Peripheral Interface (SPI)

20.1.13 PR1—Protected Range 1 Register

(SPI Memory Mapped Configuration Registers)

Memory Address:SPIBAR + 78h A ttribute: R/WL

Default Value: 00000000h Size: 32 bits

Note: This register can not be written when the FLOCKDN bit is set to 1.

20.1.14 PR2—Protected Range 2 Register

(SPI Memory Mapped Configuration Registers)

Memory Address:SPIBAR + 7Ch Attribute: R/WL

Default Value: 00000000h Size: 32 bits

Note: This register can not be written when the FLOCKDN bit is set to 1.

Bit Description

Write Protection Enable: — R/WL. When set, this bit indicates that the Base and

Limit fields in this register are valid and that writes and erases directed to addresses

between them (inclusive) must be blocked by hardware. The base and limit fields are

ignored when this bit is cleared.

30:29 Reserved

28:16

Protected Range Limit: — R/WL. This field corresponds to FLA address bits 24:12 and

specifies the upper limit of the protected range. Address bits 11:0 are assumed to be

FFFh for the limit comparison. Any address greater than the value programmed in this

field is unaffected by this protected range.

Read Protection Enable: — R/WL. When set, th is bit indicates that the Base and Lim it

fields in this register are valid and that read directed to addresses betwee n them

(inclusive) must be blocked by hardware. The base and limit fields are ignored when

this bit is cleared.

14:13 Reserved

12:0

Protected Rang e Base: — R/WL. This fiel d corresponds to FLA address bits 24:12 and

specifies the l ower base of the protected range. Address bits 11:0 are assumed to be

000h for the base comparison. Any address less than the value programmed in this

field is unaffected by this protected range.

Bit Description

Write Protection Enable: — R/WL. When set, this bit indicates that the Base and

Limit fields in this register are valid and that writes and erases directed to addresses

between them (inclusive) must be blocked by hardware. The base and limit fields are

ignored when this bit is cleared.

30:29 Reserved

28:16

Protected Range Limit: — R/WL. This field corresponds to FLA address bits 24:12 and

specifies the upper limit of the protected range. Address bits 11:0 are assumed to be

FFFh for the limit comparison. Any address greater than the value programmed in this

field is unaffected by this protected range.

Read Protection Enable: — R/WL. When set, th is bit indicates that the Base and Lim it

fields in this register are valid and that read directed to addresses betwee n them

(inclusive) must be blocked by hardware. The base and limit fields are ignored when

this bit is cleared.

14:13 Reserved

12:0

Protected Rang e Base: — R/WL. This fiel d corresponds to FLA address bits 24:12 and

specifies the l ower base of the protected range. Address bits 11:0 are assumed to be

000h for the base comparison. Any address less than the value programmed in this

field is unaffected by this protected range.

Serial Peripheral Interface (SPI)

756 Intel® ICH8 Family Datasheet

20.1.15 PR3—Protected Range 3 Register

(SPI Memory Mapped Configuration Registers)

Memory Address:SPIBAR + 80h Attribute: R/WL

Default Value: 00000000h Size: 32 bits

Note: This register can not be written when the FLOCKDN bit is set to 1.

20.1.16 PR4—Protected Range 4 Register

(SPI Memory Mapped Configuration Registers)

Memory Address:SPIBAR + 84h Attribute: R/WL

Default Value: 00000000h Size: 32 bits

Note: This register can not be written when the FLOCKDN bit is set to 1.

Bit Description

Write Protection Enable: — R/WL. When set, this bit indicates that the Base and

Limit fields in this register are valid and that writes and erases directed to addresses

between them (inclusive) must be blocked by hardware. The base and limit fields are

ignored when this bit is cleared.

30:29 Reserved

28:16

Protected Range Limit: — R/WL. This field corresponds to FLA address bits 24:12 and

specifies the upper limit of the protected range. Address bits 11:0 are assumed to be

FFFh for the limit comparison. Any address greater than the value programmed in this

field is unaffected by this protected range.

Read Protect ion Enable: — R/WL. When set, this bit indicates that the Base and Limit

fields in this register are valid and that read directed to addresses between them

(inclusive) must be blocked by hardware. The base and limit fields are ignored when

this bit is cleared.

14:13 Reserved

12:0

Protected Range Base: — R/WL. This field corresponds to FLA address bits 24:12 and

specifies the lower base of the prot ected range. Address bits 11:0 are assumed to be

000h for the base comparison. Any address less than the value programmed in this

field is unaffected by this protected range.

Bit Description

Write Protec tion Enable: — R/WL. When set, this bit indicates that the Base and Limit

fields in this regist er are valid and that writes and er ases directed to a ddresses between

them (inclusive) must be blocked by hardware. The base and limit fields are ignored

when this bit is clea red.

30:29 Reserved

28:16

Protected Range Limit: — R/WL. This field corresponds to FLA addr ess bits 24 :12 and

specifies the upper limit of the protected range. Address bits 11:0 are assumed to be

FFFh for the limit comparison. Any address greater than the value programmed in this

field is unaffected by this protected range.

Read Protection Enable: — R/WL. When set, this bit in dicates that th e Base and Limit

fields in this register are valid and that read directed to addresses between them

(inclusi ve) must be blocked by hardware. The base and limit fie lds are ignored when this

bit is cleared.

14:13 Reserved

12:0

Protected Range Base: — R/WL. This field corresponds to FLA address bits 24:12 and

specifies the lower base of the prot ected range. Address bits 11:0 are assumed to be

000h for the base comparison. Any address less than the value programmed in this field

is unaffected by this protected range.

Intel® ICH8 Family Datasheet 757

Serial Peripheral Interface (SPI)

20.1.17 SSFS—Software Sequencing Flash Status Register

(SPI Memory Mapped Configuration Registers)

Memory Address:SPIBAR + 90h A ttribute: RO, R/WC

Default Value: 00h Size: 8 bits

Note: The Software Sequencing control and status registers are reserved if the hardware

sequencing control and status registers are used.

Bit Description

7:5 Reserved

4Access Error Log (AEL): — RO. This bit reflects th e value of the Hardw are Sequencing

Status AEL register.

Flash Cycle Error (FCERR): — R/WC. Hardware sets this bit to 1 when a progr ammed

access is blocked from running on the SPI interface due to one of the prote ction policies

or when any of the programmed cycle register s is written while a programmed access is

already in progress. This bit remains asserted until cleared by software writing a 1 or

hardware reset.

Hardware reset is initiated by one of the following resets:

• Global reset (when the Ho st and the ME partitions are both reset) - on both ME-enabled and

non-ME systems.

• Host Part ition reset (any time PLTRST# is asserted either from a cold or a warm rese t) - only on

ME enabled systems.

Cycle Done Status: — R/WC. The ICH8 sets this bit to 1 when the SPI Cycle completes

(i.e. , SCIP bit is 0) after software sets the GO bit. This bit remains asserted until cleared

by software writing a 1 or hardware reset. When this bit is se t and the SPI SMI# Enable

bit is set, an internal signal is asserted to the SMI# generation block. Software must

make sure this bit is cleared prior to enabling the SPI SMI# assertion for a new

programmed access.

Hardware reset is initiated by one of the following resets:

• Global reset (when the Ho st and the ME partitions are both reset) - on both ME-enabled and

non-ME systems.

• Host Part ition reset (any time PLTRST# is asserted either from a cold or a warm rese t) - only on

ME enabled systems.

1 Reserved

SPI Cycle In Progress (SCIP): — RO. Hardware sets this bit when software sets the

SPI Cycle Go bit in the Command register. This bit remains set until the cycle completes

on the SPI interface. Hardware automatically sets and clears this bit so that software

can determine when read data is valid and/or when it is safe to begin programming the

next command. Software must only program the next command when this bit is 0.

Serial Peripheral Interface (SPI)

758 Intel® ICH8 Family Datasheet

20.1.18 SSFC—Software Sequencing Flash Control Register

(SPI Memory Mapped Configuration Registers)

Memory Address:SPIBAR + 91h Attribute: R/W

Default Value: 000000h Size: 24 bits

Bit Description

23:19 Reserved

18:16

SPI Cycle Freq uency (SCF): — R/W.

000 = 20 MHz

001 = 33 MHz

Software should program this register to set the frequency of the cycle that is to be

run.

15 SPI SMI# Enable (SME): — R/W. When set to 1, the SPI asserts an SMI# request

whenever the Cycle Done Status bit is 1.

14 Data Cycle (DS) : — R/W. When set to 1, there is data that corresponds to this

transaction. When 0, no data is delivered for this cycle, and the DBC and data fields

themselves are don’t cares

13:8

Data Byte Count (DBC): — R/W. This field specifies the number of bytes to shift in or

out during the data portion of the SPI cycle. The valid settings (in decimal) are any

value from 0 to 63. The number of bytes transferred is the value of this field plus 1.

Note that when this field is 00_0000b, then there is 1 byte to transfer and that

11_1111b means there are 64 bytes to transfer.

7 Reserved

6:4 Cycle Opcode Pointer (COP): — R /W. This field selects one of th e programmed

opcodes in the Opcode Menu to be used as the SPI Command/Opcode. In the case of an

Atomic Cycle Sequence, this determines the second c o mmand. — R/W.

Sequence Prefix Opcode Pointer (SPOP): — R/W. This field selects one of the two

programmed prefix opcodes for use when performing an Atomic Cycle Sequence. A

value of 0 points to the opcode in the least significant byte of the Prefix Opcodes

different opcodes for enabling writes to the data space vs. status register.

Atomic Cycle Sequence (A CS): — R/W. When set to 1 along with the SCGO

assertion, the ICH8 will execute a sequence of commands on the SPI interface without

allowing the LAN com p onent to arbitrate and interleave cycles. The sequence is

composed of:

• Atomic Sequence Prefix Command (8-bit opcode only)

• Primary Command specified below by software (can include address and data)

• Polling the Flash Status Register (opcode 05h) until bit 0 becomes 0b.

The SPI Cycle in Progress bit remains set and the Cycle Done Status bit remains unset

until the Busy bit in the Flas h Status Register returns 0.

SPI Cycle Go (SCGO): — R/WS. This bit always returns 0 on reads. However, a write

to this register wit h a ‘1’ in this bit starts th e SPI c y cl e de fin ed by the oth er bits of this

ignore writes to this bit while the Cycle In Progress bit is set.

Hardware allows other bits in this register to be programmed for the same transaction

when writing this bit to 1. This saves an additional memory write.

0 Reserved

Intel® ICH8 Family Datasheet 759

Serial Peripheral Interface (SPI)

20.1.19 PREOP—Prefix Opcode Configuration Register

(SPI Memory Mapped Configuration Registers)

Memory Address:SPIBAR + 94h A ttribute: R/WL

Default Value: 0000h Size: 16 bits

NOTE: This register is not writabl e when the Flash Configuration Lock-Down bit (SPIBAR +

04h:15) is set.

20.1.20 OPTYPE—Opcode Type Configuration Register

(SPI Memory Mapped Configuration Registers)

Memory Address:SPIBAR + 96h A ttribute: R/W

Default Value: 0000h Size: 16 bits

Entries in this register correspond to the entries in the Opcode Menu Configuration

Note: The definition below only provides write protection for opcodes that have addresses

associated with them. Therefore, any erase or write opcodes that do not use an address

should be avoided (for example, “Chip Er ase” and “Auto-Address Increment Byte

Program”)

NOTE: This register is not writab le when the SPI Co nfig ur ation Lock-Down bit (SPIBA R + 00h: 15)

is set.

Bit Description

15:8 Prefix Opcode 1— R/W. Software programs an SPI opcode into this field that is

permitted to run as the first command in an atomic cycle sequence .

7:0 Prefix Opcode 0 — R/W. Software programs an SPI opcode into this field that is

permitted to run as the first command in an atomic cycle sequence .

Bit Description

15:14 Opcode Type 7 — R/W. See the description for bits 1:0

13:12 Opcode Type 6 — R/W. See the description for bits 1:0

11:10 Opcode Type 5 — R/W. See the description for bits 1:0

9:8 Opcode Type 4 — R/W. See the description for bits 1:0

7:6 Opcode Type 3 — R/W. See the description for bits 1:0

5:4 Opcode Type 2 — R/W. See the description for bits 1:0

3:2 Opcode Type 1 — R/W. See the description for bits 1:0

1:0

Opcode Type 0 — R/W. This field specifies information about the corresponding

Opcode 0. This informat ion allows th e hardw are to 1) know whether to use the address

field and 2) provide BIOS and Shared Flash protection capabi lities . The enco ding of the

two bits is:

00 = No address associated with this Opcode; Read cycle type

01 = No address associate d with this Opcode; Write cycle type

10 = Address required; Read cycle type

11 = Address required; Write cycle type

Serial Peripheral Interface (SPI)

760 Intel® ICH8 Family Datasheet

20.1.21 OPMENU—Opcode Menu Configuration Register

(SPI Memory Mapped Configuration Registers)

Memory Address:SPIBAR + 98h Attribute: R/W

Default Value: 0000000000000000h Size: 64 bits

Eight entries are av ailable in this register to give BIOS a sufficient set of com mands for

communicating with the flash device, while also restricting what malicious software can

do. This keeps the hardware flexible enough to operate with a wide variety of SPI

devices.

Note: It is recommended that BIOS avoid programming Write Enable opcodes in this menu.

Malicious software could then perform writes and erases to the SPI flash without using

the atomic cycle mechanism. This could cause functional failures in a shared flash

environment. Write Enable opcodes should only be programmed in the Prefix Opcodes.

This register is not writable when the SPI Configuration Lock-Down bit (SPIBAR +

00h:15) is set.

Bit Description

63:56 Allowable Opcode 7 — R/W. See the description for bits 7:0

55:48 Allowable Opcode 6 — R/W. See the description for bits 7:0

47:40 Allowable Opcode 5 — R/W. See the description for bits 7:0

39:32 Allowable Opcode 4 — R/W. See the description for bits 7:0

31:24 Allowable Opcode 3 — R/W. See the description for bits 7:0

23:16 Allowable Opcode 2 — R/W. See the description for bits 7:0

15:8 Allowable Opcode 1 — R/W. See the description for bits 7:0

7:0 Allowable Opcode 0 — R/W. Software programs an SPI opcode into this field for use

when initiating SPI commands through the Control Register.

Intel® ICH8 Family Datasheet 761

Serial Peripheral Interface (SPI)

20.1.22 FDOC—Flash Descriptor Observability Control Register

(SPI Memory Mapped Configuration Registers)

Memory Address:SPIBAR + B0h Attribute: R/W

Default Value: 00000000h Size: 32 bits

Note: This register that can be used to observe the contents of the Flash Descriptor that is

stored in the ICH8 Flash Controller.

20.1.23 FDOD—Flash Descriptor Observability Data Register

(SPI Memory Mapped Configuration Registers)

Memory Address:SPIBAR + B4h Attribute: RO

Default Value: 00000000h Size: 32 bits

Note: This register that can be used to observe the contents of the Flash Descriptor that is

stored in the ICH8 Flash Controller.

Bit Description

31:15 Reserved

14:12

Flash Descriptor Section Select (FDSS): — R/W. This field selects which section

within the loaded Flash Descriptor to observe.

000 = Flash Signature and Descriptor Map

001 = Component

010 = Region

011 = Master

100 = ICH8 Soft Straps

111 = Reserved

11:2 Flash Descriptor Section Index (FDSI): — R/W. This field selects the DW offset

within the Flash Descriptor Section to observe.

1:0 Reserved

Bit Description

31:0 Flash Descriptor Section Data (FDSD): — RO. This field returns the DW of data to

observe as selected in the Flash Descriptor Observability Control.

Serial Peripheral Interface (SPI)

762 Intel® ICH8 Family Datasheet

20.1.24 VSCC—Vendor Specific Comp onent Capabilities Register

(SPI Memory Mapped Configuration Registers)

Memory Address:SPIBAR + C1h Attribute: RO, R/WL

Default Value: 00000000h Size: 32 bits

Bit Description

Vendor Component Lock (VCL): — R/W:

0 = The lock bit is not set

1 = The Vendor Component Lock bit is set.

This register locks itself wh en set.

22:16 Reserved

15:8

Erase Opcode (EO) — R/W: This register is programmed with the Flash erase

instruction opcode required by the vendor’s Flash component.

NOTE: If there is more than one component, both components must use the same

Erase Opcode.

This register is locked by the Vendor Component Lock (VCL) bit.

7:4 Reserved

Write Status Requir ed (WSR) — R/W

0 = No Enable write to the status register (50h) opcode is required to write to the SPI

flash Status Register(s) prior to write or erase to remove SPI flash protection.

1 = Enable write to the status regis ter (50h) opcode is required to write to the SPI f lash

Status Register(s) prior to write or erase to remove SPI flash protection.

NOTE: If there is more than one component, both components must use the same

Write Status Required setting. SPI Protection is removed by writing 00h to SPI

flash Status Register(s).

Write Granularity (WG) — R/W:

0 = 1 Byte

1 = 64 Byte

This register is locked by the Vendor Component Lock (VCL) bit.

NOTE: If more than one Flash component exists, this field must be set to the lowest

common write granularity of the different Flash components.

1:0

Block/Sector Erase Size (BSES)— R/W: This field identifies the erasable sector size

for all Flash components.

00 = 256 Byte

01 = 4 KB

10 =Reserved for future use

11 = 64 KB

This register is locked by the Vendor Component Lock (VCL) bit.

NOTE: If supporting more than one Flash component, all flash components must have

identical Block/Sector erase sizes.

This register is locked by the Vendor Component Lock (VCL) bit.

Hardware takes no action based on the value of this register. The contents of this

Intel® ICH8 Family Datasheet 763

Serial Peripheral Interface (SPI)

20.2 Flash Descriptor Registers

The following sections describe the data structure of the Flash Descriptor on the SPI

device. These are not registers within the ICH8.

20.2.1 Flash Descriptor Content

20.2.1.1 FLVALSIG—Flash Valid Signature Register

(Flash Descriptor Memory Mapped Configuration Registers)

Memory Address:FDBAR + 000h Size: 32 bits

20.2.1.2 FLMAP0—Flash Map 0 Register

(Flash Descriptor Memory Mapped Configuration Registers)

Memory Address:FDBAR + 004h Size: 32 bits

Bits Description

31:0h Flash Valid Signature: This field identifi es the Flash Descriptor s ector as valid. If the

contents at this location contain 0FF0A55Ah, then the Flash Descriptor is considered

valid and it will operate in Descriptor Mode, else it will operate in No n-Descri ptor Mode .

Bits Description

31:27 Reserved

26:24 Number Of Regions (NR): This field identifies the total number of Flash Regions. This

number is 0’s based, so a setting of all 0s indicates that the only Flas h region is re gion

0, the Flash Descriptor region.

23:16 Flash Region Base Address (FRBA): This identifies address bits [11:4] for the

Region portion of the Flash Descriptor. Bits [24:12] and bits [3:0] are 0.

For validation purposes, the recommended FRBA is: 04h

15:10 Reserved

9:8

Number Of Components (NC): This field identifies the total number of Flash

Components. Each supported Flash Component requires a separate chip select

00 = 1 Component

01 = 2 Components

All other settings = Reserved

7:0 Flash Component Base Address (F CB A): This identifies address bits [11:4] for the

component portion of the Flash Descriptor. Bits [24:12] and bits [3:0] are 0.

For validation purposes, the recommended FCBA is: 01h.

Serial Peripheral Interface (SPI)

764 Intel® ICH8 Family Datasheet

20.2.1.3 FLMAP1—Flash Map 1 Register

(Flash Descriptor Memory Mapped Configuration Registers)

Memory Address:FDBAR + 008h Size: 32 bits

20.2.1.4 FLMAP2—Flash Map 2 Register

(Flash Descriptor Memory Mapped Configuration Registers)

Memory Address:FDBAR + 00Ch Size: 32 bits

Bits Description

31:24 ICH8 Strap Length (ISL): This field identifies the 1’s based number of DWords of

ICH8 Straps to be read, up to 255 DWs (1 KB) maximum. A setting of all 0s indicates

there are no ICH8 DW straps.

23:16 Flash ICH8 Strap Base Address (FISBA): This field identifies address bits [11:4] for

the ICH8 Strap portion of the Flash Descriptor. Bits [24:12] and bits [3:0] are 0.

For validation purposes, the recommended FISBA is: 10h

15:11 Reserved

10:8 Number Of Masters (NM): This field identifies the total number of Flash Regions. This

number is 0’s based.

7:0 Flash Master Base Address (FMBA): This identi f ies address bits [11:4] for the

Master portion of the Flash Descriptor. Bits [24:12] and bits [3:0] are 0.

For validation purposes, the recommended FMBA is: 06h

Bits Description

31:16 Reserved

15:8 MCH Strap Length (MSL): This field identifies the 1s based number of DW ords of MCH

Straps to be read, up to 255 DWs (1 KB) maximum. A setting of all 0s indicates there

are no MCH DW straps.

7:0 Flash MCH Strap Base Address (FMSBA): This identifies address bits [11:4] for the

MCH Strap portion of the Flash Descriptor. Bits [24:12] and bits [3:0] are 0.

For validation purposes, the recommended FMSBA is: 20h

Intel® ICH8 Family Datasheet 765

Serial Peripheral Interface (SPI)

20.2.2 Flash Descriptor Component Section

The following section of the Flash Descriptor is used to identify the different Flash

Components and their capabilities.

20.2.2.1 FLCOMP—Flash Components Register

(Flash Descriptor Memory Mapped Configuration Registers)

Memory Address:FCBA + 000h Size: 32 bits

Bits Description

31:30 Reserved

29:27

Read ID and Read Status Clock Frequency:

000 = 20 MHz

001 = 33 MHz

All other Settings: Reserved

NOTE: If more than one Flash component exists, this field must be set to the lowest

common frequency of the different Flash components.

26:24

Write and Erase Clock Frequency:

000 = 20 MHz

001 = 33 MHz

All other Settings: Reserved

NOTE: If more than one Flash component exists, this field must be set to the lowest

common frequency of the different Flash components.

23:21

Fast Read Clock Frequency: This field identifies the frequency that can be used with

the Fast Read instruction. This field is undefined if the Fast Read Support field is 0.

000 = 20 MHz

001 = 33 MHz

All other Settings = Reserved

NOTE: If more than one Flash component exists, this field must be set to the lowest

common frequency of the different Flash components.

Fast Read Support:

0 = Fast Read is not Supported

1 =Fast Read is supported

If the Fast Read Support bit is a '1' and a device issues a Direct Read or issues a read

command from the Hardware Sequencer and the length is greater than 4 byte s, then

the SPI Flash instruction should be "Fast Read". If the Fast Read Support is a '0' or the

length is 1-4 bytes, then the SPI Flash instruction should be "Read".

Re ads to the Flash Descri ptor always use the R ead command independent of the setting

of this bit.

NOTE: If more than one Flash component exists, this field can only be set to '1' if both

components support Fast Read.

19:17

Read Clock Frequency:

000 = 20 MHz

All other Settings = Reserved

NOTE: If more than one Flash component exists, this field must be set to the lowest

common frequency of the different Flash components.

Serial Peripheral Interface (SPI)

766 Intel® ICH8 Family Datasheet

20.2.2.2 FLILL—Flash Invalid Instructions Register

(Flash Descriptor Memory Mapped Configuration Registers)

Memory Address:FCBA + 004h Size: 32 bits

16:06 Reserved

5:3

Component 2 Density: This field identifies the size of the 2nd Flash component. If

there is not 2nd Flash component, the contents of this field are undefined.

Valid Bit Settings:

000 = 512 KB

001 = 1 MB

010 = 2 MB

011 = 4 MB

100 = 8 MB

101 = 16 MB

111 = Reserved

2:0

Component 1 Densi ty: This field identifies the size of the 1st or only Flash component.

Valid Bit Settings:

000 = 512 KB

001 = 1 MB

010 = 2 MB

011 = 4 MB

100 = 8 MB

101 = 16 MB

111 = Reserved

This field is defaulted to "101b" (16MB) after reset. In non-descriptor mode, only one

flash component is supported and all accesses to flash will be to this component.

Bits Description

31:24 Invalid Instruction 3: See definition of Invalid Instruction 0

23:16 Invalid Instruction 2: See definition of Invalid Instruction 0

15:8 Invalid Instruction 1: See definition of Invalid Instruction 0

7:0

Invalid Instruction 0: Op-code for an invalid instruction in the tha t the Flash Contro ller

should protect against instructions such as Chip Erase. This byte should be set to 0 if

there are no in v alid i nstructi ons to protect against for this field. Op-codes programmed

in the Software Sequencing Opcode Menu Configuration and Prefix-Opcode

Configuration are not allowed to use any of the Invalid Instructions listed in this

Intel® ICH8 Family Datasheet 767

Serial Peripheral Interface (SPI)

20.2.3 Flash Descriptor Region Section

The following section of the Flash Descriptor is used to identify the different Flash

Regions

Flash Regions:

• If a particular region is not using SPI Flash, the particular region should be disabled

by setting the Re gion Base to all 1's, and the Region Limit to all 0's (base is higher

than the limit)

• For each region except FLREG0, the Flash Controller must have a default Region

Base of FFFh and the Region Limit to 000h within the Flash Controller in case the

Number of Regions specifies that a region is not used.

20.2.3.1 FLREG0—Flash Region 0 (Flash Descriptor) Register

(Flash Descriptor Memory Mapped Configuration Registers)

Memory Address:FRBA + 000h Size: 3 2 bits

20.2.3.2 FLREG1—Flash Region 1 (BIOS) Register

(Flash Descriptor Memory Mapped Configuration Registers)

Memory Address:FRBA + 004h Size: 3 2 bits

Bits Description

31:29 Reserved

28:16 Region Limit: This field specifies address bits 24:12 for the Region Limit.

15:13 Reserved

12:0 Region Base: This specifies address bits 24:12 for the Region Base.

Bits Description

31:29 Reserved

28:16 Region Limit: This field specifie s address bits 24:12 for the Region Limit.

15:13 Reserved

12:0

Region Base: This specifies address bits 24:12 for the Region Base.

NOTE: If the BIOS region is not used, the Region Base must be programmed to 1FFFh

and the Region Limit to 0000h to disable the region.

Serial Peripheral Interface (SPI)

768 Intel® ICH8 Family Datasheet

20.2.3.3 FLREG2—Flash Region 2 (ME) Register

(Flash Descriptor Memory Mapped Configuration Registers)

Memory Address:FRBA + 008h Size: 32 bits

20.2.3.4 FLREG3—Flash Region 3 (GbE) Register

(Flash Descriptor Memory Mapped Configuration Registers)

Memory Address:FRBA + 00Ch Size: 32 bits

Bits Description

31:29 Reserved

28:16 Region Limit: This field specifies address bits 24:12 for the Region Limit.

15:13 Reserved

12:0

Region Base: This field specifies address bits 24:12 for the Region Base.

NOTE: If the BIOS region is not used, the Region Base must be programmed to 1FFFh

and the Region Limit to 0000h to disable the region.

Bits Description

31:29 Reserved

28:16 Region Limit: This field specifies address bits 24:12 for the Region Limit.

NOTE: The ma ximum Region Limit is 128KB above the region base.

15:13 Reserved

12:0

Region Base: This field specifies address bits 24:12 for the Region Base.

NOTE: If the BIOS region is not used, the Region Base must be programmed to 1FFFh

and the Region Limit to 0000h to disable the region.

Intel® ICH8 Family Datasheet 769

Serial Peripheral Interface (SPI)

20.2.4 Flash Descriptor Master Section

20.2.4.1 FLMSTR1—Flash Master 1 (Host Processor/ BIOS)

Memory Address:FMBA + 000h Size: 32 bits

20.2.4.2 FLMSTR2—Flash Master 2 (ME)

Memory Address:FMBA + 004h Size: 32 bits

Bits Description

31:28 Reserved, must be zero

27 GbE Master Region Write Access: If the bit is set, this master can erase and write

that particular region through register accesses.

26 ME Master Region Write Access: If the bit is set, this master can erase and write

that particular region through register accesses.

Host CPU/BIOS Master Region Write Access: If the bit is s et, this master ca n erase

and write that particular region through register accesses.

Bit 25 is a don’t care as the primary master always has read/write permissions to it’s

primary region

24 Flash Descriptor Master Regi on Wri t e Access: If the bit is set, this master can

erase and write that particular region through register accesses.

23:20 Reserved, must be zero

19 GbE Master Region Read Access: If the bit is set, this master can read that

particular region through register accesses.

18 ME Master Region Read Access: If the bit is set, this master can read that particular

region through register accesses.

Host CPU/BIOS Master Region Read Access: If the bit is set, this master can read

that particular region through register accesses.

Bit 17 is a don’t care as the primary master always has read/write permissions to it’s

primary region

16 Flash Descriptor Master Region Read Access: If the bit is set, this master can read

that particular region through register accesses.

15:0 Requester ID: This is the Requester ID of the Host CPU. This must be set to 0000h.

Bits Description

31:28 Reserved, must be zero

27 GbE Master Region Write Access : If the bit is set, th is master can erase and write

that particular region through register accesses.

ME Master Region Write Ac cess: If the bit is set, this master can erase and write

that particular region through register accesses.

Bit 26 is a don’t care as the primary master always has read/write permissions to it’s

primary region

25 Host CPU/BIOS Master Region Write Access: If the bit is set, this master can erase

and write that particular region through register accesses.

24 Flash Descriptor Master Region Write Access: If the bit is set, this master can

erase and write that particular region through register accesses.

23:20 Reserved, must be zero

Serial Peripheral Interface (SPI)

770 Intel® ICH8 Family Datasheet

20.2.4.3 FLMSTR3—Flash Master 3 (GbE)

Memory Address:FMBA + 008 h Size: 32 bits

19 GbE Mast er Region Read Access : If the bit is set, this master can read that particular

region through register accesses.

ME Master Region Read Access: If the bit is set, this master can read that particular

region through register accesses.

Bit 18 is a don’t care as the primary master alw ays has read/write permissions to it’s

primary region

17 Host CPU/BIOS Master Region Read Access: If the bit is set, this master can read

that particular region through register accesses.

16 Flash Descriptor Master Region Read Access: If the bit is s et, th is m aster can re ad

that particular region through register accesses.

15:0 Requester ID: This is the Requester ID of the ME. This must be set to 0000h.

Bits Description

31:28 Reserved, must be zero

GbE Master Region Write Access : If the bit is set, th is master can erase and write

that particular region through register accesses.

Bit 27 is a don’t care as the primary master always has read/write permissions to it’s

primary region

26 ME Master Region Write Ac cess: If the bit is set, this master can erase and write

that particular region through register accesses.

25 Host CPU/BIOS Master Region Write Access: If the bit is set, this master can erase

and write that particular region through register accesses.

24 Flash Descriptor Master Region Write Access: If the bit is set, this master can

erase and write that particular region through register accesses.

23:20 Reserved, must be zero

GbE Master Region Read Access: If the bit is set, this master can read that

particular region through register accesses.

Bit 19 is a don’t care as the primary master always has read/write permissions to it’s

primary region

18 ME Mast er Regi on Rea d Acc ess: If the bi t is set, th is master can re ad that particular

region through register accesses.

17 Host CPU/BIOS Master Region Read Access: If the bit is set, this master can read

that particular region through register accesses.

16 Flash Descriptor Master Region Read Access: If the bit is set, this mast er can read

that particular region through register accesses.

15:0 Requester ID: This is the Requester ID of the GbE. This must be set to 0218h.

Intel® ICH8 Family Datasheet 771

Serial Peripheral Interface (SPI)

20.2.5 Flash Descriptor Strap

The following section of the Flash Descriptor is used to store strapping information.

The default value represents the internal strap signal value that is used if there is no

valid SPI Flash.

20.2.5.1 STRP0—Strap 0 Register

(Flash Descriptor Memory Mapped Configuration Registers)

Memory Address:FISBA + 000h Size: 32 bits

Bits Default Description

31:25 0000000b ME SmBus Addr[6:0] (ASD2): This field sets the 7-bit address for the

Intel AMT SMBus Controller 2.

24 0 Reserved

23 1 ME SmBus 2 Select (MESM2SEL):

0 = Management Engine SmBus Controller 2 is connected to the SmBus pins

1 = Management Engine SmBus Controller 2 is connected to the SmLink pins

22 0

SPI CS1# or LAN PHY Power Control (SPICS1_LANPH YPC_SEL)

0 = SPI_CS1# is used for SPI Chip Select

1 = SPI_CS1# is used for LAN PHY Power Control Function

NOTE: When configured as LAN PHY Power Control Function Bit 21=0 and

Bit 20=1 of the Strap 0 register is an invalid configuration. The LAN

PHY Power Control Function configures the ICH8 signal used as an

output.

21:20 00b

GPIO12 Select (GPI O1 2_SEL)

00 = GPIO12

01 = LAN PHY Power Control Function (Native Output)

11 = GLAN_DOCK# (Native Input)

10 = Invalid Configuration

NOTE: When configured for LAN PHY Power Control Function, Bit 22 of the

Strap 0 register must be set to 0. The LAN PHY Power Control

Function configures the ICH8 signal used as an out put.

19 0

Integrated GbE or PCI Express Select (GLAN_PCIE_SEL):

0 = PCIe Port 6 is used for PCI Express

1 = PCIe Port 6 is used for integrated GLAN

NOTE: If the Gigabit Platform LAN Connected Device is not used, this bit

may be set to 0.

18:16 0 Reserved

15 0

BMC Mode (BMCMODE): This field is only valid when TCOMODE bit 7 is

set to 1.

0 = Not BMC mode. Supports Intel® Active Management Technology or

ASF. Intel AMT SMBus Controller 1 is connected to SMBus.

1 = BMC Mode. Intel AMT SMBus Controller 1 is connected to SMLink.

14:8 0000000b ME SMBus Addr[6:0] (ASD): This field sets the 7-bit address for the Intel

AMT SMBus Controller 1.

Serial Peripheral Interface (SPI)

772 Intel® ICH8 Family Datasheet

NOTES:ICH8M supports 3 TCO modes.

1. Legacy TCO mode: Selection through STRAP0 BIT 7

2. Advanced TCO pro-active mode: Selection through STRAP0 BIT 7 and BIT15=0

3. Advanced TCO BMC mode: Selection through STRAP0 BIT 7 and BIT15=1

20.2.5.2 STRP1—Strap 1 Register

(Flash Descriptor Memory Mapped Configuration Registers)

Memory Address:FMSBA + 000h Size: 32 bits

TCO Mode (TCOMODE): This field configures the location of the TCO slave

and also enables/disables the Intel AMT SMBus Controller 1.

0 = Legacy/Compatible Mode: In this mode the TCO slave is Multiplexed

onto the SMLink pins. The Intel AMT SMBus Controller 1 is disabled.

1 = Advanced TCO Mode: In this mode the TCO slave is Multiplexed onto

the SMBus pins. The Intel AMT SMBus Controller 1 is enabled. The Intel

AMT SMBus Controller 1 configuration is set by BMCMODE bit 15.

The value of this strap is reflected in bit 1 of the SMBus Auxiliary Status

(Section 16.2.11: AUX_STS – Auxiliary Status Register (SMBUS: D31:F3:

SMBASE + 0Ch, bit 1).

6:1 0 Reserved

ME Disable (ME_DISABLE):

0 = ME is enabled

1 = ME is disabled

NOTE: This bit and bit 0 of Section 20.2.5.2 (FMSBA+000h) must be set to 1 to

disable Management Engine on the platform.

Bits Default Description

31:1 0 Reserved

ME Disable B(MDB):

0 = ME is enabled

1 = ME is disabled

NOTE: This bit and bit 0 of Section 20.2.5.1 (FMSBA+000h) must be set to 1 in

order to disable ME on the platform.

Intel® ICH8 Family Datasheet 773

Serial Peripheral Interface (SPI)

20.2.5.3 FLUMAP1—Flash Upper Map 1

Memory Address:EFCh Attribute:

Default Value: 00FFh Size: 32 bits

Note: if VTL and VTBA values are FF then firmware will assume there are no entries in VSCC

table.

20.2.5.4 JID0—JEDEC-ID 0 Register

Memory Address:VTBA + 000h Attribute:

Default Value: Size: 32 bits

20.2.5.5 VSCC0—Vendor Specific Component Capabilities 0

Memory Address:VTBA + 004h Attribute:

Default Value: Size: 32 bits

Bits Default Description

31:16 0 Reserved

15:8 1 VSCC Table Length (VTL): Identifies the 1’s based number of DWORDS

contained in the VSCC Table. Each SPI Component entry in the table is 2

DWORDS long.

7:0 1 VSCC Table Base Address (VTBA): This identifies address bits [11:4] for

the VSCC Table portion of the Flash Descriptor. Bits [24:12] and bits [3:0]

are 0.

Bits Description

31:24 Reserved

23:16 SPI Component Device ID 1: This identifies the second byte of the Device ID of the

SPI Flash Component. This is the third byte returned by the Read JEDEC-ID command

(opcode 9Fh).

15:8 SPI Component Dev ice ID 0: This identifies the first byte of the Device ID of the SPI

Flash Component. This is the second byte returned by the Read JEDEC-ID command

(opcode 9Fh).

7:0 SPI Component Vendor ID: This identifies the one byte Vendor ID of the SPI Flash

Component. This is the first byte returned by the Read JEDEC-ID command (opcode

9Fh).

Bits Description

31:17 Reserved

Write Enable on Wr ite to Status (WEWS ) :

0 = No Write Enable (06h) command is required to write to the Status register

1 = Write Enable (06h) is required to the Write Status Register prior to write and erase

to remove any protection.

NOTE: If there is more than one component, both components must use the same Write

Enable on to write to the Status Register on the SPI flash.

Serial Peripheral Interface (SPI)

774 Intel® ICH8 Family Datasheet

20.2.5.6 JID0—JEDEC-ID n Register

Memory Address:VTBA + (n*8)h Attribute:

Default Value: Size: 32 bits

15:8

Erase Opcode (EO): This register is progr amed with the Flash erase instruction opcode

required by this vendors Flash component.

Note: If there is more than one component, both components must use the same Erase

Opcode.

7:4 Reserved

Write Status Required (WSR):

0 = No Enable write to the status register (50h) opcode is required to write to the SPI

flash Status Register(s) prior to write or erase to remove SPI flash protection.

1 = Enable write to the status register (50h) opcode is required to write to the SPI flash Status

NOTE: If there is more than one component, both components must use the same Write Status

Required setting. SPI Protection is removed by writing 00h to SPI flash Status Register(s).

Write Granularity (W G):

0 = 1 Byte

1 = 64 Byte

All Other Settings: Reserved

NOTE: If more than one Flash component exists, this field must be set to the lowest

common write granularity of the different Flash components.

1:0

Block/Sector Erase Size (BES): This field identifies the erasable sector size for all

Flash components.

Valid Bit Settings:

00 = 256 Byte

01 = 4 KB

10 = Reserved for future use

11 = 64KB

NOTE: If supporting more than one Flash component, all flash components must have

identical Block/ Sector erase sizes.

Bits Description

31:24 Reserved

23:16 SPI Component Devic e ID 1: This identifies the second byte of the Device ID of the

SPI Flash Component. This is the third byte returned by the Read JEDEC-ID command

(opcode 9Fh).

15:8 SPI Component Device ID 0: This identifies the first byte of the Device ID of the SPI

Flash Component . This is the seco nd byte returned by the Read JEDEC-ID command

(opcode 9Fh).

7:0 SPI Component Vendo r ID: This identifies the one byte Vendor ID of the SPI Flash

Component. This is the first byte returned by the Read JEDEC-ID command (opcode

9Fh).

Intel® ICH8 Family Datasheet 775

Serial Peripheral Interface (SPI)

20.2.5.7 VSCC0n—Vendor Specific Component Capabilities n

Memory Address:VTBA + 004h + (n*8) Attribute:

Default Value: Size: 32 bits

Note: “n” is an integer denoting the number of table entries.

Bits Description

31:17 Reserved

Write Enable on Write Status (WEWS):

0 = No Write Enable (06h) opco de is required to writ e to the SPI Flash Statu s

1 = Write Enable (06h) opcode is required to write to the SPI Flash Status Regis ter(s) prior to write

and erase to remove SPI flash protection.

NOTE: If there is more than one co mponent, both components must u se the same Write

Enable on to write to the Status Register on the SPI flash.

15:8

Erase Opcode (EO): This register is programe d with the Flash erase inst ruction opcode

required by this vendors Flash component.

NOTE: If there is more than one component, both components must use the same

Erase Opcode.

7:4 Reserved

Write Status Required (WSR):

0 = No requirement to write to the Write Status Register prior to a write

1 = Enable status register write (50h) command is required to write to the Write Status register

NOTE: If there is more than one co mponent, both components must u se the same Write

Status Required. Uses 50h to enable a write to the Write Status Register

Write Granularity (W G):

0 = 1 Byte

1 = 64 Byte

All Other Settings = Reserved

NOTE: If more than one Flash component exists, this field must be set to the lowest

common write granularity of the different Flash components.

1:0

Block/Sector Erase Size (BES): This field identifies the erasable sector size for all

Flash components.

Valid Bit Settings:

00 = 256 Byte

01 = 4 KB

10 = Reserved for future use

11 = 64 KB

NOTE: If supporting more than one Flash component, all flash components must have

identical Block/ Sector erase sizes.

Serial Peripheral Interface (SPI)

776 Intel® ICH8 Family Datasheet

20.2.5.8 OEM Section

Memory Address:F00h Attribute:

Default Value: Size: 256 Bytes

256 Bytes are reserved at the top of the Flash Descriptor for use by OEM. The

information stored by the OEM can only be written during the manufacturing process as

the Flash Descriptor read/write permissions must be set to Read Only when the

computer leaves the manufacturing floor. The ICH Flash controller does not read this

information. FFh is suggested to reduce programming time.

20.3 GbE SPI Flash Program Registers

The GbE Flash registers are memory-mapped with a base address GLBAR found in the

GbE LAN register chapter Device 25: Function 0: Offset 18h. (MBARC Register). The

individual registers are then accessible at GLBAR + Offset as indicated in Table 144.

These memory-mapped registers must be accessed in byte, word, or DWord quantities.

Table 144. Gigabit LAN SPI Flash Program Register Address Map

(GbE LAN Memory Mapped Configuration Registers)

GLBAR +

Offset Mnemonic Register Name Default Access

00h–03h GLFPR Gigabit LAN Flash Primary Region 00000000h RO

04h–05h HSFS Hardware Sequencing Flash Status 0000h RO, R/W,

R/WL

06h–07h HSFC Hardware Sequencing Flash Control 0000h R/W, R/WS

08h–0Bh FADDR Flash Address 00000000h R/W

0Ch–0Fh — Reserved 00000000h —

10h–13h FDATA0 Flash Data 0 00000000h R/W

14h–4Fh —d Reserved 00000000h —

50h–53h FRACC Flash Region Access Permissions 00000000h RO, R/WL

54h–57h FREG0 Flash Region 0 00000000h RO

58h–5Bh FREG1 Flash Region 1 00000000h RO

5Ch–5F FREG2 Flash Region 2 00000000h RO

60h–63h FREG3 Flash Region 3 00000000h RO

64h–73h — Reserved for Future Flash Regions — —

74h–77h FPR0 Flash Protected Range 0 00000000h R/WL

78h–7Bh FPR1 Flash Protected Range 1 00000000h R/WL

7Ch–8Fh Reserved Reserved

90h SSFS Software Sequencing Flash Status 0000h RO, R/WC

91h–93h SSFC Software Sequencing Flash Control 0000h R/W

94h–95h PREOP Prefix Opcode Configuration 0000h R/WL

96h–97h OPTYPE Opcode Type Configuration 0000h R/W

98h–9Fh OPMENU Opcode Menu Configuratio n 00000000h R/W

A0h–DFh — Reserved — —

Intel® ICH8 Family Datasheet 777

Serial Peripheral Interface (SPI)

20.3.1 GLFPR—Gigabit LAN Flash Primary Region Register

(GbE LAN Memory Mapped Configuration Registers)

Memory Address:GLBAR + 00h Attribute: RO

Default Value: 00000000h Size: 32 bits

Bit Description

31:29 Reserved

28:16

GbE Flash Primary Region Limit (PRL):— RO. This field specifies address bits 24:12

for the Primary Region Limit.

The value in this regi ster loaded from the contents in the Flash

Descriptor.FLREG3.Region Limit

15:13 Reserved

12:0

GbE Flash Primary Region Base (PRB ) — RO. This field specifies address bits 24:12

for the Primary Region Base

The value in this register is loaded from the contents in the Flash

Descriptor.FLREG3.Region Base

Serial Peripheral Interface (SPI)

778 Intel® ICH8 Family Datasheet

20.3.2 HSFS—Hardware Sequencing Flash Status Register

(GbE LAN Memory Mapped Configuration Registers)

Memory Address:GLBAR + 04h Attribute: RO, R/WC, R/WL

Default Value: 0000h Size: 16 bits

Bit Description

Flash Configuration Lock-Down (FLOCKDN)— R/W/L. When set to 1, those Flash

Program Registers that are locked down by this FLOCKDN bit cannot be written. Once

set to 1, this bit can only be cleared by a hardware reset.

Hardware reset is initiated by one of the following resets:

• Global reset (when the Host and the ME partitions are both reset) - on both ME-enabled and

non-ME systems.

• Host Pa rtition reset (an y time PLTRST# is asserted either from a cold or a warm reset) - only on

ME enabled systems.

Flash Descriptor Valid (FDV)— RO. This bit is set to a 1 if the Flash Controller read

the correct Flash Descriptor Signature.

If the Flash Descriptor V alid bit is not 1, software ca nnot us e the Hardware Sequencing

registers, but must use the software sequencing registers. Any attempt to use the

Hardware Sequencing registers will result in the FCERR bit being set.

Flash Descriptor Override Pin Strap Status (FDOPSS)— RO. This bit reflects the

value the Flash Descriptor Override Pin-Strap.

1 = No over ride

0 = The Flash Descriptor Override strap is set

12:6 Reserved

SPI Cycle In Progress (SCIP)— RO. Hardware sets this bit when software sets the

Flash Cycle Go (FGO) bit in the Hardware Sequencing Flash Control register. This bit

remains set until the cycle completes on the SPI interface. Hardware automatically sets

and clears thi s bit so that software can dete rm ine when read data is v alid and/ or when

it is safe to begin programming the next command. Software must only program the

next command when this bit is 0.

4:3

Block/Sector Erase Size (BERASE) — RO. This field identifies the erasable sector

size for all Flash components.

Valid Bit Settings:

00 = 256 Byte

01 = 4 KB

10 = Reserved for future use

11 = 64 KB

Access Error Log (AEL)— R/W/C. Hardware sets this bit to a 1 when an attempt was

made to access the BIOS region using the direct access method or an access to the

BIOS Program Re gisters that violated the security restrictions. This bit is simply a log of

an access security violation. This bit is cleared by software writing a 1.

Intel® ICH8 Family Datasheet 779

Serial Peripheral Interface (SPI)

20.3.3 HSFC—Hardware Sequencing Flash Control Register

(GbE LAN Memory Mapped Configuration Registers)

Memory Address:GLBAR + 06h Attribute: R/W, R/WS

Default Value: 0000h Size: 16 bits

Flash Cycle Error (FCERR) — R/W/C. Hardware sets this bit to 1 when an program

any of the programmed cycle registers is written while a programmed access is already

in progre ss. This bit remains asserted until cleared by software writing a 1 or until

hardware reset occurs. Software must clear this bit before setting the FLASH Cycle GO

bit in this register.

Hardware reset is initiated by one of the following resets:

• Global reset (when the Ho st and the ME partitions are both reset) - on both ME-enabled and

non-ME systems.

• Host Parti tion reset (any time PLTRST# is asserted either from a cold or a warm reset) - only on

ME enabled systems.

Flash Cycle Done (FDONE) — R/W/C. The ICH8 sets this bit to 1 when the SPI Cycle

completes after software previously set the FGO bit. This bit remains asserted until

cleared by software writing a 1 or hardware reset. When this bit is se t and the SPI

SMI# Enable bit is set, an internal signal is asserted to the SMI# generation block.

Software must make sure this bit is cleared prior to enabling the SPI SMI# assertion for

a new programmed access.

Hardware reset is initiated by one of the following resets:

• Global reset (when the Ho st and the ME partitions are both reset) - on both ME-enabled and

non-ME systems.

• Host Parti tion reset (any time PLTRST# is asserted either from a cold or a warm reset) - only on

ME enabled systems.

Bit Description

15:10 Reserved

9:8

Flash Data Byte Count (FDBC): — R/W. This field specifies the number of bytes to

shift in or out during the data portion of the SPI cycle. The content’ s of this register are

0’s based with 0b representing 1 byte and 11b representing 4 bytes. The number of

bytes transferred is the value of this field plus 1.

This field is ignored for the Block Erase command.

Serial Peripheral Interface (SPI)

780 Intel® ICH8 Family Datasheet

20.3.4 FADDR—Flash Address Register

(GbE LAN Memory Mapped Configuration Registers)

Memory Address:GLBAR + 08h Attribute: R/W

Default Value: 00000000h Size: 32 bits

20.3.5 FDATA0—Flash Data 0 Register

(GbE LAN Memory Mapped Configuration Registers)

Memory Address:GLBAR + 10h Attribute: R/W

Default Value: 00000000h Size: 32 bits

7:3 Reserved

2:1

FLASH Cycle (FCYCLE). — R/W. This field defines the Flash SPI cycle type generated

to the FLASH when the FGO bit is set as defined below:

00 = Read (1 up to 4 bytes by setting FDBC)

01 = Reserved

10 = Write (1 up to 4 bytes by setting FDBC)

11 = Block Erase

Flash Cycle Go (FGO): — R/W/S. A write to this register with a ‘1’ in this bit initiates

a request to the F lash SPI Arbiter to start a cycle. This register is cleared by hardware

when the cycle is granted by the SPI arbiter to run the cycle on the SPI bus. When the

cycle is complete, the FDONE bit is set.

Software is forbidden to write to any regist er in the HSFLCTL register between the FGO

bit getting set and the FDONE bit being cleared. Any attempt to violate this rule will be

ignored by hardware.

Hardware allows other bits in this register to be programmed for the same transaction

when writing this bit to 1. This saves an additional memory write.

This bit always returns 0 on reads.

Bit Description

31:25 Reserved

24:0 Flash Linear Address (FLA): — R/W. The FLA is the starting byte linear address of a

SPI Read or W rite cycle or an address within a Block for the Block Er ase command. The

Flash Linear Address must fall within a region for which BIOS has access permissions.

Bit Description

31:0

Flash Data 0 (FD0): — R/W. This field is shifted out as the SPI Data on the Master-

Out Slave-In Data pin during the data portion of the SPI cycle.

This register also shifts in the data from the Master-In Slave-Out pin into this register

during the data portion of the SPI cycle.

The data is always shifted starting with the least significant byte, msb to lsb, followed

by the next least significant byte, msb to lsb, etc. Specifically, the shift order on SPI in

terms of bits within this register is: 7-6-5-4-3-2-1-0-15-14-13-…8-23-22-…16-31…24

Bit 24 is the last bit shi fted out/ in. Th ere ar e no alignme nt assum ptions ; byte 0 alwa ys

represents the value speci fied by the cycle address.

Note that the data in this register may be modified by the hardware during any

programmed SPI transaction. Direct Memory Reads do not modify the contents of this

Intel® ICH8 Family Datasheet 781

Serial Peripheral Interface (SPI)

20.3.6 FRAP—Flash Regions Access Permissions Register

(GbE LAN Memory Mapped Configuration Registers)

Memory Address:GLBAR + 50h A ttribute: RO, R/WL

Default Value: 00000808h S i ze: 32 bits

Bit Description

31:28 Reserved

27:25

GbE Master Write Access Grant (GMWAG): — R/WL. Each bit [27:25] corresponds

to Master[3:1]. GbE can grant one or more masters write acces s to the GbE region 3

overriding the permissions in the Flash Descriptor.

Master[1] is Host CPU/BIOS, Master[2] is ME, Master[3] is Host CPU/GbE.

The contents of this regist er are locked by the FLOCKDN bit.

24:20 Reserved

19:17

GbE Master Read Access Grant (GMRAG): — R/WL. Each bit [19:17] corres ponds to

Master[3:1]. GbE can grant one or more masters read access to the GbE region 3

overriding the read permissions in the Flash Descriptor.

Master[1] is Host CPU/BIOS, Master[2] is ME, Mast er[3] is GbE.

The contents of this regist er are locked by the FLOCKDN bit.

16:12 Reserved

11:8

GbE Region Write Access (GRWA): — RO. Each bit [11:8] corresponds to Regions

[3:0]. If the bit is set, this master can erase and write that particular region through

The contents of this register are that of the Flash Descriptor. Flash Master 3.Master

Region W rite Access OR a particular master has granted GbE write permissions in their

Master Write Access Grant register OR the Flash Descriptor Security Override strap is

set.

7:4 Reserved

3:0

GbE Region Read Access (GRRA): — RO. Each bit [3:0] corresponds to Regions

[3:0]. If the bit is set, this master can read that particular region through register

accesses.

The contents of this register are that of the Flash Descriptor. Flash Master 3.Master

Re gion Write Access OR a particular master has granted GbE read permissions in their

Master Read Access Grant register.

Serial Peripheral Interface (SPI)

782 Intel® ICH8 Family Datasheet

20.3.7 FREG0—Flash Region 0 (Flash Descriptor) Register

(GbE LAN Memory Mapped Configuration Registers)

Memory Address:GLBAR + 54h Attribute: RO

Default Value: 00000000h Size: 32 bits

20.3.8 FREG1—Flash Region 1 (BIOS Descriptor) Register

(GbE LAN Memory Mapped Configuration Registers)

Memory Address:GLBAR + 58h Attribute: RO

Default Value: 00000000h Size: 32 bits

Bit Description

31:29 Reserved

28:16

Region Limit (RL): — RO. This field specifies address bits 24:12 for the Region 0

Limit.

The value in this register is loaded from the contents in the Flash

Descriptor.FLREG0.Region Limit.

15:13 Reserved

12:0

Region Base (RB): — RO. This field specifies address bits 24:12 for the Region 0

Base.

The value in this register is loaded from the contents in the Flash

Descriptor.FLREG0.Region Base.

Bit Description

31:29 Reserved

28:16

Region Limit (RL): — RO. This field specifies address bits 24:12 for the Region 1

Limit.

The value in this register is loaded from the contents in the Flash

Descriptor.FLREG1.Region Limit

15:13 Reserved

12:0

Region Base (RB): — RO. This field specifies address bits 24:12 for the Region 1

Base.

The value in this register is loaded from the contents in the Flash

Descriptor.FLREG1.Region Base.

Intel® ICH8 Family Datasheet 783

Serial Peripheral Interface (SPI)

20.3.9 FREG2—Flash Region 2 (ME) Register

(GbE LAN Memory Mapped Configuration Registers)

Memory Address:GLBAR + 5Ch Attribute: RO

Default Value: 00000000h Size: 32 bits

20.3.10 FREG3—Flash Region 3 (GbE) Register

(GbE LAN Memory Mapped Configuration Registers)

Memory Address:GLBAR + 60h Attribute: RO

Default Value: 00000000h Size: 32 bits

Bit Description

31:29 Reserved

28:16

Region Limit (RL): — RO. This field specifies address bits 24:12 for the Region 2

Limit.

The value in this register is loaded from the contents in the Flash

Descriptor.FLREG2.Region Limit.

15:13 Reserved

12:0

Region Base (RB): — RO. This field specifies address bits 24:12 for the Region 2

Base.

The value in this register is loaded from the contents in the Flash

Descriptor.FLREG2.Region Base.

Bit Description

31:29 Reserved

28:16

Region Limit (RL): — RO. This field specifies address bits 24:12 for the Region 3

Limit.

The value in this register is loaded from the contents in the Flash

Descriptor.FLREG3.Region Limit

15:13 Reserved

12:0

Region Base (RB): — RO. This field specifies address bits 24:12 for the Region 3

Base.

The value in this register is loaded from the contents in the Flash

Descriptor.FLREG3.Region Base.

Serial Peripheral Interface (SPI)

784 Intel® ICH8 Family Datasheet

20.3.11 PR0—Protected Range 0 Register

(GbE LAN Memory Mapped Configuration Registers)

Memory Address:GLBAR + 74h Attribute: R/WL

Default Value: 00000000h Size: 32 bits

Note: This register can not be written when the FLOCKDN bit is set to 1.

20.3.12 PR1—Protected Range 1 Register

(GbE LAN Memory Mapped Configuration Registers)

Memory Address:GLBAR + 78h Attribute: R/WL

Default Value: 00000000h Size: 32 bits

Note: This register can not be written when the FLOCKDN bit is set to 1.

Bit Description

Write Protection Enable: — R/WL. When set, this bit indicates that the Base and

Limit fields in this register are valid and that writes and erases directed to addresses

between them (inclusive) must be blocked by hardware. The base and limit fields are

ignored when this bit is cleared.

30:29 Reserved

28:16

Protected Range Limit: — R/WL. This field corresponds to FLA address bits 24:12 and

specifies the upper limit of the protected range. Address bits 11:0 are assumed to be

FFFh for the limit comparison. Any address greater than the value programmed in this

field is unaffected by this protected range.

Read Protect ion Enable: — R/WL. When set, this bit indicates that the Base and Limit

fields in this register are valid and that read directed to addresses between them

(inclusive) must be blocked by hardware. The base and limit fields are ignored when

this bit is cleared.

14:13 Reserved

12:0

Protected Range Base: — R/WL. This field corresponds to FLA address bits 24:12 and

specifies the lower base of the prot ected range. Address bits 11:0 are assumed to be

000h for the base comparison. Any address less than the value programmed in this

field is unaffected by this protected range.

Bit Description

Write Protection Enable: — R/WL. When set, this bit indicates that the Base and

Limit fields in this register are valid and that writes and erases directed to addresses

between them (inclusive) must be blocked by hardware. The base and limit fields are

ignored when this bit is cleared.

30:29 Reserved

28:16

Protected Range Limit: — R/WL. This field corresponds to FLA address bits 24:12 and

specifies the upper limit of the protected range. Address bits 11:0 are assumed to be

FFFh for the limit comparison. Any address greater than the value programmed in this

field is unaffected by this protected range.

Read Protect ion Enable: — R/WL. When set, this bit indicates that the Base and Limit

fields in this register are valid and that read directed to addresses between them

(inclusive) must be blocked by hardware. The base and limit fields are ignored when

this bit is cleared.

14:13 Reserved

12:0

Protected Range Base: — R/WL. This field corresponds to FLA address bits 24:12 and

specifies the lower base of the prot ected range. Address bits 11:0 are assumed to be

000h for the base comparison. Any address less than the value programmed in this

field is unaffected by this protected range.

Intel® ICH8 Family Datasheet 785

Serial Peripheral Interface (SPI)

20.3.13 SSFS—Software Sequencing Flash Status Register

(GbE LAN Memory Mapped Configuration Registers)

Memory Address:GLBAR + 90h A ttribute: RO, R/WC

Default Value: 00h Size: 8 bits

Note: The Software Sequencing control and status registers are reserved if the hardware

sequencing control and status registers are used.

Bit Description

7:5 Reserved

4Access Error Log (AEL): — RO. This bit reflects the value of the Hardware

Sequencing Status AEL register.

Flash Cycle Error (FCERR): — R/WC. Hardware sets this bit to 1 when a progr ammed

access is blocked from running on the SPI interface due to one of the protection policies

or when any of the progr ammed cycle regis ters is written while a programmed access is

already in progress. This bit remains asserted until cleared by software writing a 1 or

hardware reset.

Hardware reset is initiated by one of the following resets:

• Global reset (when the Ho st and the ME partitions are both reset) - on both ME-enabled and

non-ME systems.

• Host Parti tion reset (any time PLTRST# is asserted either from a cold or a warm reset) - only on

ME enabled systems.

Cycle Done Status: — R/WC. The ICH8 sets this bit to 1 when the SPI Cycle completes

(i.e., SCIP bit is 0) after software sets the GO bit. This bit remains asserted until

cleared by software writing a 1 or hardware reset. When this bit is se t and the SPI

SMI# Enable bit is set, an internal signal is asserted to the SMI# generation block.

Software must make sure this bit is cleared prior to enabling the SPI SMI# assertion for

a new programmed access.

Hardware reset is initiated by one of the following resets:

• Global reset (when the Ho st and the ME partitions are both reset) - on both ME-enabled and

non-ME systems.

• Host Parti tion reset (any time PLTRST# is asserted either from a cold or a warm reset) - only on

ME enabled systems.

1 Reserved

SPI Cycle In P ro g ress (SCIP): — RO. Hardware sets this bit when software sets the

SPI Cycle Go bit in the Command register. This bit remains set unti l the cycle comp letes

on the SPI interface. Hardware automatically sets and clears this bit so that software

can determine when read data is valid and/or when it is safe to begin programming the

next command. Software must only program the next command when this bit is 0.

Serial Peripheral Interface (SPI)

786 Intel® ICH8 Family Datasheet

20.3.14 SSFC—Software Sequencing Flash Control Register

(GbE LAN Memory Mapped Configuration Registers)

Memory Address:GLBAR + 91h Attribute: R/W

Default Value: 000000h Size: 24 bits

Bit Description

23:19 Reserved

18:16

SPI Cycle Freq uency (SCF): — R/W.

000 = 20 MHz

001 = 33 MHz

All other values reserved

Software should program this register to set the frequency of the cycle that is to be

run.

15 Reserved

14 Data Cycle (DS) : — R/W. When set to 1, there is data that corresponds to this

transaction. When 0, no data is delivered for this cycle, and the DBC and data fields

themselves are do not cares

13:8

Data Byte Count (DBC): — R/W. This field specifies the number of bytes to shift in or

out during the data portion of the SPI cycle. The valid settings (in decimal) are any

value from 0 to 3. The number of bytes transferred is the value of this field plus 1.

Note that when this field is 00b, then there is 1 byte to transfer and that 11b means

there are 4 bytes to transfer.

7 Reserved

6:4 Cycle Opcode Pointer (COP): — R /W. This field selects one of th e programmed

opcodes in the Opcode Menu to be used as the SPI Command/Opcode. In the case of an

Atomic Cycle Sequence, this det ermines the second c o mmand.

Sequence Prefix Opcode Pointer (SPOP): — R/W. This field selects one of the two

programmed prefix opcodes for use when performing an Atomic Cycle Sequence. A

value of 0 points to the opcode in the least significant byte of the Prefix Opcodes

different opcodes for enabling writes to the data space vs. status register.

Atomic Cycle Sequence (A CS): — R/W. When set to 1 along with the SCGO

assertion, the ICH8 will execute a sequence of commands on the SPI interface without

allowing the LAN com p onent to arbitrate and interleave cycles. The sequence is

composed of:

• Atomic Sequence Prefix Command (8-bit opcode only)

• Primary Command specified below by software (can include address and data)

• Polling the Flash Status Register (opcode 05h) until bit 0 becomes 0b.

The SPI Cycle in Progress bit remains set and the Cycle Done Status bit remains unset

until the Busy bit in the Flas h Status Register returns 0.

SPI Cycle Go (SCGO): — R/WS. This bit always returns 0 on reads. However, a write

to this register with a 1 in this bit starts the SPI cycle defined by the other bits of this

ignore writes to this bit while the Cycle In Progress bit is set.

Hardware allows other bits in this register to be programmed for the same transaction

when writing this bit to 1. This saves an additional memory write.

0 Reserved

Intel® ICH8 Family Datasheet 787

Serial Peripheral Interface (SPI)

20.3.15 PREOP—Prefix Opcode Configuration Register

(GbE LAN Memory Mapped Configuration Registers)

Memory Address:GLBAR + 94h Attribute: R/WL

Default Value: 0000h Size: 16 bits

NOTE: This register is not writable when the SPI Configuration Lock-Down bit (GLBAR + 00h:15)

is set.

20.3.16 OPTYPE—Opcode Type Configuration Register

(GbE LAN Memory Mapped Configuration Registers)

Memory Address:GLBAR + 96h Attribute: R/W

Default Value: 0000h Size: 16 bits

Entries in this register correspond to the entries in the Opcode Menu Configuration

Note: The definition below only provides write protection for opcodes that have addresses

associated with them. Therefore, any erase or write opcodes that do not use an address

should be avoided (for example, “Chip Er ase” and “Auto-Address Increment Byte

Program”).

NOTE: This register is not writable when the SPI Configuration Lock-Down bit (GLBAR + 00h:15)

is set.

Bit Description

15:8 Prefix Opcode 1— R/WL. Software programs an SPI opcode into this field that is

permitted to run as the first command in an atomic cycle sequence .

7:0 Prefix Opcode 0 — R/W. Software programs an SPI opcode into this field that is

permitted to run as the first command in an atomic cycle sequence .

Bit Description

15:14 Opcode Type 7 — R/W. See the description for bits 1:0

13:12 Opcode Type 6 — R/W. See the description for bits 1:0

11:10 Opcode Type 5 — R/W. See the description for bits 1:0

9:8 Opcode Type 4 — R/W. See the description for bits 1:0

7:6 Opcode Type 3 — R/W. See the description for bits 1:0

5:4 Opcode Type 2 — R/W. See the description for bits 1:0

3:2 Opcode Type 1 — R/W. See the description for bits 1:0

1:0

Opcode Type 0 — R/W. This field specifies information about the corresponding

Opcode 0. This informat ion allows th e hardw are to 1) know whether to use the address

field and 2) provide BIOS and Shared Flash protection capabi lities . The enco ding of the

two bits is:

00 = No address associated with this Opcode; Read cycle type

01 = No address associate d with this Opcode; Write cycle type

10 = Address required; Read cycle type

11 = Address required; Write cycle type

Serial Peripheral Interface (SPI)

788 Intel® ICH8 Family Datasheet

20.3.17 OPMENU—Opcode Menu Configuration Register

(GbE LAN Memory Mapped Configuration Registers)

Memory Address:GLBAR + 98h Attribute: R/W

Default Value: 0000000000000000h Size: 64 bits

Eight entries are available in this register to give GbE a sufficient set of commands for

communicating with the flash device, while also restricting what malicious software can

do. This keeps the hardware flexible enough to operate with a wide variety of SPI

devices.

Note: It is recommended that GbE avoid programming Write Enable opcodes in this menu.

Malicious software could then perform writes and erases to the SPI flash without using

the atomic cycle mechanism. This could cause functional failures in a shared flash

environment. Write Enable opcodes should only be programmed in the Prefix Opcodes.

This register is not writable when the SPI Configuration Lock-Down bit (GLBAR +