CY25811/12/14 Spread Spectrum Clock Generator Spread Spectrum Clock Generator Features Applications 4 to 32 MHz input frequency range Printers and MFPs 4 to 128 MHz output frequency range LCD panels Accepts clock, crystal, and resonator inputs Digital copiers 1x, 2x, and 4x frequency multiplication: CY25811: 1x; CY25812: 2x; CY25814: 4x PDAs CD-ROM, VCD, and DVD Center and Down Spread modulation Networking, LAN, and WAN Low power dissipation: 3.3V = 52 mW - typ at 6 MHz 3.3V = 60 mW - typ at 12 MHz 3.3V = 72 mW - typ at 24 MHz Scanners Modems Embedded digital systems Low cycle-to-cycle jitter: 8 MHz = 480 ps-max 16 MHz = 400 ps-max 32 MHz = 450 ps-max Benefits Available in 8-pin SOIC and TSSOP packages Commercial and industrial temperature ranges Peak EMI reduction by 8 to 16 dB Fast time to market Cost reduction Functional Description For a complete list of related documentation, click here. Logic Block Diagram 300K XIN 1 8pF REFERENCE DIVIDER PD and CP LF MODULATION CONTROL VCO COUNTE R VCO XOUT 8 8pF VDD 7 INPUT DECODER LOGIC VSS 2 Cypress Semiconductor Corporation Document Number: 38-07112 Rev. *N * 6 3 4 FRSEL S1 S0 198 Champion Court COUNTER and MUX * 5 SSCLK San Jose, CA 95134-1709 * 408-943-2600 Revised May 24, 2017 CY25811/12/14 Contents Pin Configuration ............................................................. 3 Pin Definitions .................................................................. 3 Functional Overview ........................................................ 3 Input Frequency Range and Selection ........................ 3 Spread Percentage Selection ...................................... 4 Input and Output Frequency Selection ........................ 5 Absolute Maximum Conditions ....................................... 6 DC Electrical Specifications ............................................ 6 DC Electrical Specifications ............................................ 7 Thermal Resistance .......................................................... 7 AC Electrical Specifications ............................................ 8 AC Electrical Specifications ............................................ 9 Characteristic Curves .................................................... 10 SSCG Profiles ................................................................. 11 Application Schematic ................................................... 12 Document Number: 38-07112 Rev. *N Ordering Information ...................................................... 13 Ordering Code Definitions ......................................... 13 Package Drawing and Dimensions ............................... 14 Acronyms ........................................................................ 16 Document Conventions ................................................. 16 Units of Measure ....................................................... 16 Document History Page ................................................. 17 Sales, Solutions, and Legal Information ...................... 19 Worldwide Sales and Design Support ....................... 19 Products .................................................................... 19 PSoC(R)Solutions ....................................................... 19 Cypress Developer Community ................................. 19 Technical Support ..................................................... 19 Page 2 of 19 CY25811/12/14 Pin Configuration Figure 1. 8-pin SOIC/TSSOP pinout CY25811/12/14 XIN/CLKIN 1 VSS 2 S1 3 CY25811 CY25812 CY25814 S0 4 8 XOUT 7 VDD 6 FRSEL 5 SSCLK Pin Definitions Pin No. Name Type 1 XIN/CLKIN Input Description 2 VSS Power 3 S1 Input Digital Spread% Control Pin. 3-Level input (H-M-L). Default = M. Digital Spread% Control Pin. 3-Level input (H-M-L). Default = M. Crystal, Ceramic Resonator or Clock Input Pin. Power Supply Ground. 4 S0 Input 5 SSCLK Output 6 FRSEL Input 7 VDD Power Positive Power Supply. 8 XOUT Output Crystal or Ceramic Resonator Output Pin. Spread Spectrum Output Clock. Input Frequency Range Selection Digital Control Input. 3-Level input (H-M-L). Default = M. Functional Overview The CY25811/12/14 products are Spread Spectrum Clock Generator (SSCG) ICs used for the purpose of reducing electromagnetic interference (EMI) found in today's high-speed digital electronic systems. The devices use a Cypress proprietary phase-locked loop (PLL) and Spread Spectrum Clock (SSC) technology to synthesize and modulate the frequency of the input clock. By frequency modulating the clock, the measured EMI at the fundamental and harmonic frequencies is greatly reduced. This reduction in radiated energy significantly reduces the cost of complying with regulatory agency requirements and improves time to market without degrading system performance. The input frequency range is 4 to 32 MHz and accepts clock, crystal and ceramic resonator inputs. The output clock can be selected to produce 1x, 2x, or 4x multiplication of the input frequency with Spread Spectrum Frequency Modulation. The use of 2x or 4x frequency multiplication eliminates the need for higher order crystals and enables you to generate up to 128 MHz Spread Spectrum Clock (SSC) by using only first-order crystals. This reduces the cost while improving the system clock accuracy, performance, and complexity. Document Number: 38-07112 Rev. *N Select the Center Spread or Down Spread frequency modulation based on four discrete values of Spread % for each Spread mode with the option of a Non Spread mode for system test and verification purposes. The CY25811/12/14 products are available in an 8-pin SOIC (150 mils) package with a commercial operating temperature range of 0 C to 70 C and industrial temperature range of -40 C to 85 C. Refer to CY25568 for multiple clock output options such as modulated and unmodulated clock outputs or power down function. Input Frequency Range and Selection The CY25811/12/14 input frequency range is 4 to 32 MHz. This range is divided into three segments and controlled by a 3-level FRSEL pin as given in Table 1. Table 1. Input Frequency Selection FRSEL Input Frequency Range 0 4.0 to 8.0 MHz 1 8.0 to 16.0 MHz M 16.0 to 32.0 MHz Page 3 of 19 CY25811/12/14 Spread Percentage Selection The CY25811/12/14 SSCG products provide Center Spread, Down Spread, and No Spread functions. The amount of Spread percentage is selected using 3-level. S0 and S1 digital inputs and Spread percent values are given in Table 2. Table 2. Spread Percent Selection XIN (MHz) FRSEL S1 = 0 S0 = 0 S1 = 0 S0 = M S1 = 0 S0 = 1 S1 = M S0 = 0 S1 = 1 S0 = 1 S1 = 1 S0 = 0 S1 = M S0 = 1 S1 = 1 S0 = M S1 = M S0 = M Center (%) Center (%) Center (%) Center (%) Down (%) Down (%) Down (%) Down (%) No Spread 4-5 0 1.4 1.2 0.6 0.5 -3.0 -2.2 -1.9 -0.7 0 5-6 0 1.3 1.1 0.5 0.4 -2.7 -1.9 -1.7 -0.6 0 6-7 0 1.2 0.9 0.5 0.4 -2.5 -1.8 -1.5 -0.6 0 7-8 0 1.1 0.9 0.4 0.3 -2.3 -1.7 -1.4 -0.5 0 8-10 1 1.4 1.2 0.6 0.5 -3.0 -2.2 -1.9 -0.7 0 10-12 1 1.3 1.1 0.5 0.4 -2.7 -1.9 -1.7 -0.6 0 12-14 1 1.2 0.9 0.5 0.4 -2.5 -1.8 -1.5 -0.6 0 14-16 1 1.1 0.9 0.4 0.3 -2.3 -1.7 -1.4 -0.5 0 16-20 M 1.4 1.2 0.6 0.5 -3.0 -2.2 -1.9 -0.7 0 20-24 M 1.3 1.1 0.5 0.4 -2.7 -1.9 -1.7 -0.6 0 24-28 M 1.2 0.9 0.5 0.4 -2.5 -1.8 -1.5 -0.6 0 28-32 M 1.1 0.9 0.4 0.3 -2.3 -1.7 -1.4 -0.5 0 3-Level Digital Inputs Modulation Rate S0, S1, and FRSEL digital inputs are designed to sense three different logic levels designated as High "1", Low "0", and Middle "M". With this 3-Level digital input logic, the 3-Level Logic detects nine different logic states. SSCGs use frequency modulation (FM) to distribute energy over a specific band of frequencies. The maximum frequency of the clock (fmax) and minimum frequency of the clock (fmin) determine this band of frequencies. The time required to transition from fmin to fmax and back to fmin is the period of the Modulation Rate. The Modulation Rate of SSCG clocks are generally referred to in terms of frequency, or: S0, S1, and FRSEL pins include an on chip 20K (10K and 10K) resistor divider. No external application resistors are needed to implement the 3-level logic levels as shown here: Logic Level "0": 3-Level logic pin connected to GND. Logic Level "M": 3-Level logic pin left floating (no connection). Logic Level "1": 3-Level logic pin connected to VDD. Figure 2 illustrates how to implement 3-Level Logic. LOGIC MIDDLE (M) S0, S1 and FRSEL UNCONNECTED S0, S1 and FRSEL to VSS VSS Document Number: 38-07112 Rev. *N The input clock frequency, fin, and the internal divider determine the Modulation Rate. In CY25811/12/14 devices, the (Spread Spectrum) modulation rate, fmod, is given by the following formula: fmod = fin/DR Figure 2. 3-Level Logic LOGIC LOW (0) fmod = 1/Tmod. LOGIC HIGH (H) S0, S1 and FRSEL to VDD Here fmod is the Modulation Rate, fin is the Input Frequency, and DR is the Divider Ratio as given in Table 3. Note that Input Frequency Range is set by FRSEL. Table 3. Modulation Rate Divider Ratios FRSEL Input Frequency Range (MHz) Divider Ratio (DR) 0 4 to 8 128 1 8 to 16 256 M 16 to 32 512 Page 4 of 19 CY25811/12/14 Input and Output Frequency Selection The relationship between input frequency and output frequency in device selection and FRSEL setting is given in Table 4. As shown, the input frequency range is selected by FRSEL and is the same for CY25811, CY25812, and CY25814. The selection of CY25811 (1x), CY25812 (2x), or CY25814 (4x) determines the frequency multiplication at the output (SSCLK, Pin 5) with respect to input frequency (XIN, Pin-1). Table 4. Input and Output Frequency Selection Input Frequency Range (MHz) FRSEL Product Multiplication Output Frequency Range (MHz) 4 to 8 0 CY25811 1x 4 to 8 8 to 16 1 CY25811 1x 8 to 16 16 to 32 M CY25811 1x 16 to 32 4 to 8 0 CY25812 2x 8 to 16 8 to 16 1 CY25812 2x 16 to 32 16 to 32 M CY25812 2x 32 to 64 4 to 8 0 CY25814 4x 16 to 32 8 to 16 1 CY25814 4x 32 to 64 16 to 32 M CY25814 4x 64 to 128 Document Number: 38-07112 Rev. *N Page 5 of 19 CY25811/12/14 Absolute Maximum Conditions Both Commercial and Industrial Grades Parameter [1, 2] Description Condition Min Max Unit VDD Supply Voltage -0.5 4.6 V VIN Input Voltage Relative to VSS -0.5 VDD + 0.5 V TS Temperature, Storage Non Functional -65 150 C TA1 Temperature, Operating Ambient Functional, C-Grade 0 70 C TA2 Temperature, Operating Ambient Functional, I-Grade -40 85 C TJ Temperature, Junction Functional - 150 C - V Max Unit 2.97 3.63 V 0 0.15 x VDD V ESDHBM ESD Protection (Human Body Model) MIL-STD-883, Method 3015 UL-94 Flammability Rating at 1/8 in. MSL Moisture Sensitivity Level 2000 V-0 3 DC Electrical Specifications Commercial Grade Parameter Description Condition Min VDD 3.3 V Operating Voltage 3.3 V 10% VIL Input Low Voltage S0, S1 and FRSEL Inputs VIM Input Middle Voltage S0, S1 and FRSEL Inputs 0.40 x VDD 0.60 x VDD V VIH Input High Voltage S0, S1 and FRSEL Inputs 0.85 x VDD V VOL1 Output Low Voltage IOL = 4 mA, SSCLK Output - 0.4 V VOL2 Output Low Voltage IOL = 10 mA, SSCLK Output - 1.2 V VOH1 Output High Voltage IOH = 4 mA, SSCLK Output 2.4 - V VOH2 Output High Voltage IOH = 6 mA, SSCLK Output 2.0 - V CIN1 Input Pin Capacitance XIN (Pin 1) and XOUT (Pin 8) 3.5 9.0 pF CIN2 Input Pin Capacitance All Digital Inputs 2.8 6.0 pF CL Output Load Capacitor SSCLK Output - 15 pF IDD1 Dynamic Supply Current Fin = 12 MHz, no load - 28 mA IDD2 Dynamic Supply Current Fin = 24 MHz, no load - 33 mA IDD3 Dynamic Supply Current Fin = 32 MHz, no load - 40 mA VDD Notes 1. Operation at any Absolute Maximum Rating is not implied. 2. Single Power Supply: The voltage on any input or I/O pin cannot exceed the power pin during power up. Document Number: 38-07112 Rev. *N Page 6 of 19 CY25811/12/14 DC Electrical Specifications Industrial Grade Parameter Description Condition Min Max Unit 3.135 3.465 V 0 0.13 x VDD V S0, S1 and FRSEL Inputs 0.40 x VDD 0.60 x VDD V Input High Voltage S0, S1 and FRSEL Inputs 0.85 x VDD VDD V Output Low Voltage IOL = 4 mA, SSCLK Output - 0.4 V VOL2 Output Low Voltage IOL = 10 mA, SSCLK Output - 1.2 V VOH1 Output High Voltage IOH = 4 mA, SSCLK Output 2.4 - V VOH2 Output High Voltage IOH = 6 mA, SSCLK Output 2.0 - V CIN1 Input Pin Capacitance XIN (Pin 1) and XOUT (Pin 8) 3.5 9.0 pF CIN2 Input Pin Capacitance All Digital Inputs 2.8 6.0 pF CL Output Load Capacitor SSCLK Output - 15 pF IDD1 Dynamic Supply Current Fin = 12 MHz, no load - 28 mA IDD2 Dynamic Supply Current Fin = 24 MHz, no load - 33 mA IDD3 Dynamic Supply Current Fin = 32 MHz, no load - 41 mA VDD 3.3 V Operating Voltage 3.3 V 5% VIL Input Low Voltage S0, S1 and FRSEL Inputs VIM Input Middle Voltage VIH VOL1 Thermal Resistance Parameter [3] Description JA Thermal resistance (junction to ambient) JC Thermal resistance (junction to case) Test Conditions 8-pin SOIC 8-pin TSSOP Unit Test conditions follow standard test methods and procedures for measuring thermal impedance, in accordance with EIA/JESD51. 139 159 C/W 54 32 C/W Note 3. These parameters are guaranteed by design and are not tested. Document Number: 38-07112 Rev. *N Page 7 of 19 CY25811/12/14 AC Electrical Specifications Commercial Grade Condition Min Max Unit FIN Parameter Input Frequency Range Description Clock, Crystal, or Ceramic Resonator Input 4 32 MHz TR1 Clock Rise Time SSCLK, CY25811 and CY25812 2.0 5.0 ns TF1 Clock Fall Time SSCLK, CY25811 and CY25812 1.6 4.4 ns TR2 Clock Rise Time SSCLK, only CY25814 when FRSEL = M 1.0 2.2 ns TF2 Clock Fall Time SSCLK, only CY25814 when FRSEL = M 0.8 2.2 ns TDCIN Input Clock Duty Cycle XIN 40 60 % TDCOUT Output Clock Duty Cycle SSCLK 40 60 % TCCJ1 Cycle to Cycle Jitter, Spread on Fin = 4 MHz, Fout = 4 MHz, CY25811 - 800 ps TCCJ2 Cycle to Cycle Jitter, Spread on Fin = 8 MHZ, Fout = 8 MHz, CY25811 - 480 ps TCCJ3 Cycle to Cycle Jitter, Spread on Fin = 8 MHz, Fout = 16 MHz, CY25812 - 400 ps TCCJ4 Cycle to Cycle Jitter, Spread on Fin = 16 MHz, Fout = 32 MHz, CY25812 - 450 ps TCCJ5 Cycle to Cycle Jitter, Spread on Fin = 16 MHz, Fout = 64 MHz, CY25814 - 550 ps TCCJ6 Cycle to Cycle Jitter, Spread on Fin = 32 MHz, Fout = 128 MHz, CY25814 - 380 ps TSU PLL Lock Time From VDD = 3.0 V to valid SSCLK - 3 ms Document Number: 38-07112 Rev. *N Page 8 of 19 CY25811/12/14 AC Electrical Specifications Industrial Grade Condition Min Max Unit FIN Parameter Input Frequency Range Description Clock, Crystal or Ceramic Resonator Input 4 32 MHz TR1 Clock Rise Time SSCLK, CY25811, and CY25812 2.0 5.0 ns TF1 Clock Fall Time SSCLK, CY25811, and CY25812 1.6 4.4 ns TR2 Clock Rise Time SSCLK, only CY25814 when FRSEL = M 1.0 2.2 ns TF2 Clock Fall Time SSCLK, only CY25814 when FRSEL = M 0.8 2.2 ns TDCIN Input Clock Duty Cycle XIN 40 60 % TDCOUT Output Clock Duty Cycle SSCLK 40 60 % TCCJ1 Cycle to Cycle Jitter, Spread on Fin = 6 MHz, CY25811/12/14 - 650 ps TCCJ2 Cycle to Cycle Jitter, Spread on Fin = 12 MHz, CY25811/12/14 - 630 ps TCCJ3 Cycle to Cycle Jitter, Spread on Fin = 24 MHz, CY25811/12/14 - 520 ps TSU PLL Lock Time From VDD = 3.0 V to valid SSCLK - 4 ms Document Number: 38-07112 Rev. *N Page 9 of 19 CY25811/12/14 Characteristic Curves The following curves demonstrate the characteristic behavior of CY25811/12/14 when tested over a number of environmental and application specific parameters. These are typical performance curves and are not meant to replace any parameter specified in DC and AC Specification tables. Figure 3. Characteristic Curves 600 2.75 6.0 MHz 32.0 MHz 500 2.5 BW % CCJ (ps) 400 300 2.25 200 2 100 1.75 0 4 8 12 16 20 24 28 32 -40 -25 -10 5 20 Jitter vs. Input Frequency (No Load) FRSEL = M 16 - 32 MHz BW (%) IDD (mA) 24 FRSEL = 1 8 - 16 MHz 20 18 16 FRSEL = 0 4 - 8 MHz 14 12 10 4 4.5 5 5.5 6 6.5 7 7.5 Frequency (MHz), no load, normalized to FRSEL = 0, (4 - 8 MHz). IDD vs. Frequency (FRSEL = 0, 1, M) Document Number: 38-07112 Rev. *N 65 80 95 110 125 3 2.9 2.8 2.7 28 22 50 Bandwidth % vs. Temperature 30 26 35 Temp (C) Input Frequency (MHz) 8 2.6 2.5 2.4 2.3 2.2 2.1 2 1.9 1.8 2.8 4.0 MHz 8.0 MHz 2.9 3 3.1 3.2 3.3 3.4 3.5 3.6 3.7 VDD (volts) Bandwidth % vs. VDD Page 10 of 19 CY25811/12/14 SSCG Profiles CY25811/12/14 SSCG products use a non-linear "optimized" frequency profile as shown in Figure 4. The use of Cypress proprietary "optimized" frequency profile maintains flat energy distribution over the fundamental and higher order harmonics. This results in additional EMI reduction in electronic systems. Figure 4. Spread Spectrum Profiles (Frequency versus Time) Xin = 6.0 MHz S1, S0 = 0 FRSEL = 0 Xin = 12.0 MHz S1, S0 = 0 FRSEL = 1 SSCLK1 = 6.0 MHz P/N = CY25811 SSCLK1 = 48.0 MHz P/N = CY25814 Document Number: 38-07112 Rev. *N Xin = 24.0 MHz S1, S0 = 0 FRSEL = M Xin = 24.0 MHz S1, S0 = 0 FRSEL = M SSCLK1 = 24.0 MHz P/N = CY25811 SSCLK1 = 96.0 MHz P/N = CY25814 Page 11 of 19 CY25811/12/14 Application Schematic VDD C3 0.1 uF 7 C2 1 27 pF Y1 25 MHz 8 C3 XIN VDD SSCLK 5 25 MHz (CY25811) 50 MHz (CY25812) 100 MHz (CY25814) XOUT 27 pF CY25811 CY25812 CY25814 N/C 6 S1 FRSEL VSS S0 3 4 2 Document Number: 38-07112 Rev. *N Page 12 of 19 CY25811/12/14 Ordering Information Part Number Package Type Product Flow Pb-free Devices CY25811SXC 8-pin SOIC Commercial, 0C to 70 C CY25811SXCT 8-pin SOIC - Tape and Reel Commercial, 0 C to 70 C CY25811SXI 8-pin SOIC Industrial, -40 C to 85 C CY25811SXIT 8-pin SOIC - Tape and Reel Industrial, -40 C to 85 C CY25812SXC 8-pin SOIC Commercial, 0 C to 70 C CY25812SXCT 8-pin SOIC - Tape and Reel Commercial, 0 C to 70 C CY25812ZXC 8-pin TSSOP Commercial, 0 C to 70 C CY25812ZXCT 8-pin TSSOP - Tape and Reel Commercial, 0 C to 70 C CY25814SXC 8-pin SOIC Commercial, 0 C to 70 C CY25814SXCT 8-pin SOIC - Tape and Reel Commercial, 0 C to 70 C CY25814SXI 8-pin SOIC Industrial, -40 C to 85 C CY25814SXIT 8-pin SOIC - Tape and Reel Industrial, -40 C to 85 C Ordering Code Definitions CY 2581 X X X X T T = Tape and Reel; blank = Tube Temperature Range: X = C or I C = Commercial; I = Industrial Pb-free Package Type: X = S or Z S = 8-pin SOIC Z = 8-pin TSSOP Frequency Multiplier: X = 1 or 2 or 4 1 = 1X; 2 = 2X; 4 = 4X Part Identifier Company ID: CY = Cypress Document Number: 38-07112 Rev. *N Page 13 of 19 CY25811/12/14 Package Drawing and Dimensions Figure 5. 8-pin SOIC (150 Mils) S0815/SZ815/SW815 Package Outline, 51-85066 51-85066 *H Document Number: 38-07112 Rev. *N Page 14 of 19 CY25811/12/14 Package Drawing and Dimensions (continued) Figure 6. 8-pin TSSOP (4.40 mm Body) Z08.173/ZZ08.173 Package Outline, 51-85093 51-85093 *E Document Number: 38-07112 Rev. *N Page 15 of 19 CY25811/12/14 Acronyms Acronym Document Conventions Description Units of Measure CD-ROM compact disc, read only memory DVD digital versatile/video disc C degree Celsius EMI Electromagnetic Interference dB decibel ESD electrostatic discharge MHz megahertz FM frequency modulation F microfarad LAN local area network mA milliampere LCD liquid crystal display mm millimeter PLL phase locked loop ms millisecond SOIC small outline integrated circuit mW milliwatt SSC spread spectrum clock ns nanosecond SSCG spread spectrum clock generator % percent TSSOP thin shrink small outline package pF picofarad ps picosecond VCD video compact disc V volt VCO voltage controlled oscillator WAN wide area network Document Number: 38-07112 Rev. *N Symbol Unit of Measure Page 16 of 19 CY25811/12/14 Document History Page Document Title: CY25811/12/14, Spread Spectrum Clock Generator Document Number: 38-07112 Revision ECN Orig. of Change Submission Date ** 107516 NDP 06/14/02 Converted from IMI to Cypress *A 108002 NDP 06/29/02 Deleted Junction Temp. in Absolute Maximum Ratings *B 121578 RGL 01/29/03 Converted from Word to FrameMaker Added 8-pin TSSOP package in Commercial Temp. only Added an Industrial Temperature Range to all existing 8-pin SOIC packages *C 125550 RGL 05/14/03 Changed IDD values from 19.6/22/27.2 to 25/30/35 in Commercial Grade DC Specs table Changed IDD values from 24/26.5/33 to 26/32/37 in Industrial grade DC Specs table Changed TCCJ1/2 values from 675/260 to 800/450 in Commercial grade AC Specs table Changed TCCJ1 value from 350 to 650 in Industrial grade AC Specs table *D 131941 RGL 12/24/03 Removed automotive in the Applications section Changed the Output Clock Duty Cycle (TDCOUT) from min. 45 and max. 55 to 40 and 60% respectively for both industrial and commercial grade Changed the min. Input Low Voltage (VIL) from 0.15VDD to 0.13VDD Removed preliminary from the industrial AC/DC Electrical Specifications table Description of Change *E 231057 RGL See ECN Added Pb Free Devices *F 1499165 KVM See ECN Updated Ordering Information table Corrected jitter values in features section on page 1 Changed:VDD from 5% to 10%, CIN1 min from 6 to 3.5 pF, CIN2 min from 3.5 to 2.8 pF, TF1 min from 2 to 1.6 ns, and TF2 min from 1.0 to 0.8 ns. Commercial grade: IDD1 max from 25 to 28 mA, IDD2 max from 30 to 33 mA, IDD3 max from 35 to 40 mA, TCCJ2 from 450 to 480 ps, TCCJ4 from 380 to 450 ps, and TCCJ5 from 380 to 550 ps Industrial grade: IDD1 max from 26 to 28 mA, IDD2 max from 32 to 33 mA, IDD3 max from 37 to 41 mA, TCCJ2 from 400 to 630 ps, and TCCJ3 from 400 to 520 ps *G 2592288 CXQ / PYRS 10/23/08 Removed Pb package devices from Ordering Table *H 2761988 CXQ 09/10/09 Removed reference to non-existent "Automotive" version. Fixed typo in DC spec table for VDD from min of 3.97 to 2.97. Fixed typo for PLL Lock time conditions. Removed CY25812SXI, CY25812SXIT, CY25814ZXC, and CY25814ZXCT from Ordering Information. *I 2887509 CXQ 03/04/2010 Updated MSL value in Absolute Maximum Conditions Added Contents Updated 8-pin SOIC and 8-pin TSSOP package drawings. Updated URLs in Sales, Solutions, and Legal Information *J 3339686 PURU 08/08/2011 Added Ordering Code Definitions. Updated Package Drawing and Dimensions. Added Acronyms and Units of Measure. Updated to new template. *K 4499792 TAVA 09/11/2014 Updated Package Drawing and Dimensions: spec 51-85066 - Changed revision from *E to *F. spec 51-85093 - Changed revision from *C to *D. Updated to new template. Completing Sunset Review. Document Number: 38-07112 Rev. *N Page 17 of 19 CY25811/12/14 Document History Page (continued) Document Title: CY25811/12/14, Spread Spectrum Clock Generator Document Number: 38-07112 Revision ECN Orig. of Change Submission Date *L 4587350 TAVA 12/05/2014 Updated Functional Description: Added "For a complete list of related documentation, click here." at the end. Updated Package Drawing and Dimensions: spec 51-85093 - Changed revision from *D to *E. *M 5279207 PSR 05/26/2016 Added Thermal Resistance. Updated Package Drawing and Dimensions: spec 51-85066 - Changed revision from *F to *H. Updated to new template. *N 5747567 PSR 05/24/2017 Added the pin type column in Pin Definitions. Corrected unit for the VIN parameter. Updated the Cypress logo, copyright information, Sales, Solutions, and Legal Information based on the new template. Document Number: 38-07112 Rev. *N Description of Change Page 18 of 19 CY25811/12/14 Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer's representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. 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Cypress products are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of weapons, weapons systems, nuclear installations, life-support devices or systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or hazardous substances management, or other uses where the failure of the device or system could cause personal injury, death, or property damage ("Unintended Uses"). A critical component is any component of a device or system whose failure to perform can be reasonably expected to cause the failure of the device or system, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you shall and hereby do release Cypress from any claim, damage, or other liability arising from or related to all Unintended Uses of Cypress products. You shall indemnify and hold Cypress harmless from and against all claims, costs, damages, and other liabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of Cypress products. Cypress, the Cypress logo, WICED, Spansion, the Spansion logo, and combinations thereof, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners. Document Number: 38-07112 Rev. *N Revised May 24, 2017 Page 19 of 19